diff --git a/.github/linter-service.yaml b/.github/linter-service.yaml index bedee7b1..4d676607 100644 --- a/.github/linter-service.yaml +++ b/.github/linter-service.yaml @@ -1,3 +1,6 @@ +# yamllint disable rule:document-start linters: cargo-coupling: min_grade: C + max_critical: 0 + max_circular: 0 diff --git a/Cargo.lock b/Cargo.lock index 488fb85a..fc5f0c01 100644 --- a/Cargo.lock +++ b/Cargo.lock @@ -2877,6 +2877,12 @@ version = "0.16.4" source = "registry+https://github.com/rust-lang/crates.io-index" checksum = "7f66e8d5d03f609abc3a39e6f08e4164ebf1447a732906d39eb9b99b7919ef39" +[[package]] +name = "lzma-rust2" +version = "0.16.4" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "ce716bf1a316f47a280fc76295f6495b5bea4752bca01c3b3885e101b1c23c02" + [[package]] name = "mach2" version = "0.5.0" @@ -3133,7 +3139,6 @@ dependencies = [ name = "nerust_console" version = "0.1.0-dev" dependencies = [ - "crc", "log", "nerust_cartridge_data", "nerust_contract_controller_runtime", @@ -3141,6 +3146,7 @@ dependencies = [ "nerust_contract_persistence", "nerust_contract_rom", "nerust_core", + "nerust_crc64_hasher", "nerust_input_nes", "nerust_screen_buffer", "nerust_screen_filter", @@ -3213,12 +3219,12 @@ name = "nerust_core" version = "0.1.0-dev" dependencies = [ "bitflags 2.12.1", - "crc", "hound", "log", "nerust_contract_mirror", "nerust_contract_options", "nerust_contract_rom", + "nerust_crc64_hasher", "nerust_screen_video", "nerust_serialize", "nerust_sound_traits", @@ -3232,6 +3238,13 @@ dependencies = [ "typetag", ] +[[package]] +name = "nerust_crc64_hasher" +version = "0.1.0-dev" +dependencies = [ + "crc", +] + [[package]] name = "nerust_glwrap" version = "0.1.0-dev" @@ -3316,6 +3329,7 @@ dependencies = [ "nerust_contract_persistence", "nerust_contract_rom", "nerust_contract_settings", + "nerust_crc64_hasher", "nerust_gui_runtime", "nerust_gui_session", "nerust_input_nes", @@ -3325,6 +3339,9 @@ dependencies = [ "nerust_screen_buffer", "nerust_screen_filter", "nerust_screen_logical", + "nerust_screen_physical", + "nerust_snes_core", + "nerust_snes_render", "nerust_sound_android", "nerust_sound_openal", "nerust_sound_traits", @@ -3391,10 +3408,10 @@ name = "nerust_rom_test" version = "0.1.0-dev" dependencies = [ "clap", - "crc", "nerust_cartridge_data", "nerust_contract_options", "nerust_core", + "nerust_crc64_hasher", "nerust_input_nes", "nerust_input_nes_runtime", "nerust_screen_buffer", @@ -3496,6 +3513,39 @@ dependencies = [ "serde", ] +[[package]] +name = "nerust_snes_core" +version = "0.1.0-dev" +dependencies = [ + "bitflags 2.12.1", + "nerust_sound_traits", + "thiserror 2.0.18", +] + +[[package]] +name = "nerust_snes_render" +version = "0.1.0-dev" +dependencies = [ + "nerust_snes_core", + "thiserror 2.0.18", +] + +[[package]] +name = "nerust_snes_rom_test" +version = "0.1.0-dev" +dependencies = [ + "clap", + "nerust_crc64_hasher", + "nerust_snes_core", + "nerust_snes_render", + "png", + "serde", + "serde_derive", + "serde_yaml", + "sevenz-rust2", + "thiserror 2.0.18", +] + [[package]] name = "nerust_sound_android" version = "0.1.0-dev" @@ -4932,6 +4982,18 @@ dependencies = [ "unsafe-libyaml", ] +[[package]] +name = "sevenz-rust2" +version = "0.21.0" +source = "registry+https://github.com/rust-lang/crates.io-index" +checksum = "dbbd24232798280d6bc896e3429a3469174de008ec8b1b591a96618b46664195" +dependencies = [ + "crc32fast", + "js-sys", + "lzma-rust2", + "wasm-bindgen", +] + [[package]] name = "shared_library" version = "0.1.9" diff --git a/Cargo.toml b/Cargo.toml index d72b6c2a..9d68aeb2 100644 --- a/Cargo.toml +++ b/Cargo.toml @@ -37,8 +37,12 @@ members = [ "sound/openal", "sound/filter", "sound/traits", + "snes/core", + "snes/render", + "snes/rom_test", "sound/android", "timer", + "util/crc64_hasher", ] default-members = ["core", "persistence", "console"] @@ -88,6 +92,7 @@ nerust_contract_persistence = { path = "contract/persistence" } nerust_contract_rom = { path = "contract/rom" } nerust_contract_settings = { path = "contract/settings" } nerust_core = { path = "core" } +nerust_crc64_hasher = { path = "util/crc64_hasher" } nerust_gui_runtime = { path = "gui/shared/runtime" } nerust_gui_shell = { path = "gui/shared/shell" } nerust_gui_session = { path = "gui/shared/session" } @@ -107,6 +112,9 @@ nerust_screen_physical = { path = "screen/physical" } nerust_screen_rgb = { path = "screen/rgb" } nerust_screen_wgpu = { path = "screen/wgpu" } nerust_screen_video = { path = "screen/video" } +nerust_snes_core = { path = "snes/core" } +nerust_snes_render = { path = "snes/render" } +nerust_snes_rom_test = { path = "snes/rom_test" } nerust_serialize = { path = "serialize" } nerust_sound_openal = { path = "sound/openal" } nerust_sound_android = { path = "sound/android" } @@ -123,6 +131,7 @@ serde = { version = "=1.0.228", default-features = false } serde_bytes = { version = "=0.11.19" } serde_derive = { version = "=1.0.228", default-features = false } serde_yaml = { version = "=0.9.34" } +sevenz-rust2 = { version = "=0.21.0", default-features = false } shared_library = { version = "=0.1.9" } simple_logger = { version = "=5.2.0" } strum = { version = "=0.28.0" } diff --git a/README.md b/README.md index 9126d52a..fb701c5f 100644 --- a/README.md +++ b/README.md @@ -1,5 +1,5 @@ NSHumanReadableCopyright - © Mitsuharu Seki. Licensed under MPL-2.0. + © chalharu. Licensed under MPL-2.0. CFBundleIconFile diff --git a/persistence/src/lib.rs b/persistence/src/lib.rs index df759c4a..24071021 100644 --- a/persistence/src/lib.rs +++ b/persistence/src/lib.rs @@ -1,4 +1,4 @@ -// Copyright (c) 2024 Mitsuharu Seki +// Copyright (c) 2024 chalharu // // This Source Code Form is subject to the terms of the Mozilla Public // License, v. 2.0. If a copy of the MPL was not distributed with this diff --git a/rom_test/Cargo.toml b/rom_test/Cargo.toml index d40376ec..12181347 100644 --- a/rom_test/Cargo.toml +++ b/rom_test/Cargo.toml @@ -8,10 +8,10 @@ rust-version.workspace = true [dependencies] clap.workspace = true -crc.workspace = true nerust_cartridge_data.workspace = true nerust_contract_options.workspace = true nerust_core.workspace = true +nerust_crc64_hasher.workspace = true nerust_input_nes.workspace = true nerust_input_nes_runtime.workspace = true nerust_screen_buffer.workspace = true diff --git a/rom_test/build.rs b/rom_test/build.rs index 4b0df3db..0dad1c5c 100644 --- a/rom_test/build.rs +++ b/rom_test/build.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use std::env; use std::fmt::Write as _; use std::fs; diff --git a/rom_test/src/bin/perf.rs b/rom_test/src/bin/perf.rs index 15bf3cd8..e47e334a 100644 --- a/rom_test/src/bin/perf.rs +++ b/rom_test/src/bin/perf.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - fn main() { nerust_rom_test::perf::run_cli(); } diff --git a/rom_test/src/bin/rom_tool.rs b/rom_test/src/bin/rom_tool.rs index 412a4f5b..4ac7e538 100644 --- a/rom_test/src/bin/rom_tool.rs +++ b/rom_test/src/bin/rom_tool.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use clap::{Arg, ArgAction, ArgMatches, Command}; use nerust_rom_test::manifest::{RomManifest, load_default_manifest, load_manifest}; use nerust_rom_test::report::{default_output_root, write_html_report}; diff --git a/rom_test/src/error.rs b/rom_test/src/error.rs index bdeddc7d..7df943c6 100644 --- a/rom_test/src/error.rs +++ b/rom_test/src/error.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use std::path::PathBuf; #[derive(Debug, thiserror::Error)] diff --git a/rom_test/src/events.rs b/rom_test/src/events.rs index 328a8319..52a8c457 100644 --- a/rom_test/src/events.rs +++ b/rom_test/src/events.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; use super::serde_helpers::{hex_u8, hex_u16, hex_u64}; use nerust_input_nes::frame::Buttons; diff --git a/rom_test/src/harness.rs b/rom_test/src/harness.rs index b4328b30..6f9bfe89 100644 --- a/rom_test/src/harness.rs +++ b/rom_test/src/harness.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; use super::events::{ButtonCode, ControllerPad, PadState, RomAssertion, RomEventKind}; use super::manifest::RomCase; diff --git a/rom_test/src/lib.rs b/rom_test/src/lib.rs index 1ca30578..0de6ff8f 100644 --- a/rom_test/src/lib.rs +++ b/rom_test/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #![allow( unused_imports, reason = "different harness targets reuse this facade with different subsets of the shared API" diff --git a/rom_test/src/manifest.rs b/rom_test/src/manifest.rs index 1588f833..db2557ca 100644 --- a/rom_test/src/manifest.rs +++ b/rom_test/src/manifest.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; use super::events::RomEvent; use nerust_contract_options::{CoreOptions, Mmc3IrqVariant}; diff --git a/rom_test/src/media.rs b/rom_test/src/media.rs index 19fec86b..8f5e89a9 100644 --- a/rom_test/src/media.rs +++ b/rom_test/src/media.rs @@ -1,11 +1,5 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; -use crc::{CRC_64_XZ, Crc, Digest}; +use nerust_crc64_hasher::Crc64Hasher; use nerust_screen_buffer::screen_buffer::ScreenBuffer; use nerust_screen_filter::FilterType; use nerust_screen_logical::LogicalSize; @@ -14,8 +8,6 @@ use png::{BitDepth, ColorType, Encoder}; use std::hash::{Hash, Hasher}; use std::io::Cursor; -const CRC64_LEGACY_ECMA: Crc = Crc::::new(&CRC_64_XZ); - pub(crate) fn validation_screen_buffer() -> ScreenBuffer { ScreenBuffer::new( FilterType::None, @@ -61,24 +53,6 @@ pub(crate) fn encode_screenshot_png(screen_buffer: &ScreenBuffer) -> Result); - -impl Crc64Hasher { - fn new() -> Self { - Self(CRC64_LEGACY_ECMA.digest()) - } -} - -impl Hasher for Crc64Hasher { - fn write(&mut self, bytes: &[u8]) { - self.0.update(bytes); - } - - fn finish(&self) -> u64 { - self.0.clone().finalize() - } -} - #[derive(Debug, Clone)] pub(crate) struct HashingMixer { sample_rate: u32, diff --git a/rom_test/src/perf.rs b/rom_test/src/perf.rs index 0b5ef422..b4ba86cf 100644 --- a/rom_test/src/perf.rs +++ b/rom_test/src/perf.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use crate::error::RomTestError; use crate::events::{ButtonCode, ControllerPad, PadState, RomAssertion}; use crate::harness::{CaseHarness, apply_button_state, drive_case}; diff --git a/rom_test/src/report.rs b/rom_test/src/report.rs index e7ab9369..0ea64c03 100644 --- a/rom_test/src/report.rs +++ b/rom_test/src/report.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; use super::results::CaseOutcome; use std::fmt::Write as _; diff --git a/rom_test/src/results.rs b/rom_test/src/results.rs index e3f3bbf7..1a6385ba 100644 --- a/rom_test/src/results.rs +++ b/rom_test/src/results.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::manifest::{AudioExpectation, RomCategory}; #[derive(Debug, Clone, Copy)] diff --git a/rom_test/src/runner.rs b/rom_test/src/runner.rs index 0f470aba..4df8ff41 100644 --- a/rom_test/src/runner.rs +++ b/rom_test/src/runner.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod entry; mod validation; diff --git a/rom_test/src/runner/validation.rs b/rom_test/src/runner/validation.rs index 63171925..61d75052 100644 --- a/rom_test/src/runner/validation.rs +++ b/rom_test/src/runner/validation.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod artifacts; pub(in crate::runner::validation) mod assertions; mod harness_impl; diff --git a/rom_test/src/runner/validation/artifacts.rs b/rom_test/src/runner/validation/artifacts.rs index 7b7c43c7..7394c408 100644 --- a/rom_test/src/runner/validation/artifacts.rs +++ b/rom_test/src/runner/validation/artifacts.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod memory; mod screen; mod summary; diff --git a/rom_test/src/runner/validation/artifacts/memory.rs b/rom_test/src/runner/validation/artifacts/memory.rs index 620c3399..165ff2ef 100644 --- a/rom_test/src/runner/validation/artifacts/memory.rs +++ b/rom_test/src/runner/validation/artifacts/memory.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod cartridge_ram; mod ppu_vram; mod work_ram; diff --git a/rom_test/src/runner/validation/artifacts/memory/cartridge_ram.rs b/rom_test/src/runner/validation/artifacts/memory/cartridge_ram.rs index 0dae5e64..814db2b0 100644 --- a/rom_test/src/runner/validation/artifacts/memory/cartridge_ram.rs +++ b/rom_test/src/runner/validation/artifacts/memory/cartridge_ram.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::super::super::{assertions::CartridgeRamAssertion, runtime::ValidationRuntime}; use super::super::ValidationArtifacts; use crate::error::RomTestError; diff --git a/rom_test/src/runner/validation/artifacts/memory/ppu_vram.rs b/rom_test/src/runner/validation/artifacts/memory/ppu_vram.rs index 1d4c5fe8..ce58f2f6 100644 --- a/rom_test/src/runner/validation/artifacts/memory/ppu_vram.rs +++ b/rom_test/src/runner/validation/artifacts/memory/ppu_vram.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::super::super::runtime::ValidationRuntime; use super::super::ValidationArtifacts; use crate::error::RomTestError; diff --git a/rom_test/src/runner/validation/artifacts/memory/work_ram.rs b/rom_test/src/runner/validation/artifacts/memory/work_ram.rs index 9eae51f2..dd950cfa 100644 --- a/rom_test/src/runner/validation/artifacts/memory/work_ram.rs +++ b/rom_test/src/runner/validation/artifacts/memory/work_ram.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::super::super::runtime::ValidationRuntime; use super::super::ValidationArtifacts; use crate::error::RomTestError; diff --git a/rom_test/src/runner/validation/artifacts/screen.rs b/rom_test/src/runner/validation/artifacts/screen.rs index e2a83997..d42589c0 100644 --- a/rom_test/src/runner/validation/artifacts/screen.rs +++ b/rom_test/src/runner/validation/artifacts/screen.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::super::runtime::ValidationRuntime; use super::ValidationArtifacts; use crate::error::RomTestError; diff --git a/rom_test/src/runner/validation/artifacts/summary.rs b/rom_test/src/runner/validation/artifacts/summary.rs index d2e0fa94..5e9ec6d3 100644 --- a/rom_test/src/runner/validation/artifacts/summary.rs +++ b/rom_test/src/runner/validation/artifacts/summary.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::super::runtime::ValidationRuntime; use super::ValidationArtifacts; use crate::manifest::RomCase; diff --git a/rom_test/src/runner/validation/assertions.rs b/rom_test/src/runner/validation/assertions.rs index b8c70dd1..65a0e9e4 100644 --- a/rom_test/src/runner/validation/assertions.rs +++ b/rom_test/src/runner/validation/assertions.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #[derive(Clone, Copy)] pub(in crate::runner::validation) struct CartridgeRamAssertion { pub(in crate::runner::validation) frame: u64, diff --git a/rom_test/src/runner/validation/harness_impl.rs b/rom_test/src/runner/validation/harness_impl.rs index 3e61a744..d7187721 100644 --- a/rom_test/src/runner/validation/harness_impl.rs +++ b/rom_test/src/runner/validation/harness_impl.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::runner::ValidationRunner; use crate::error::RomTestError; use crate::events::{MemoryAssertionSpace, RomAssertion}; diff --git a/rom_test/src/runner/validation/runner.rs b/rom_test/src/runner/validation/runner.rs index 8852422f..73ee6a85 100644 --- a/rom_test/src/runner/validation/runner.rs +++ b/rom_test/src/runner/validation/runner.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::artifacts::ValidationArtifacts; use super::assertions::CartridgeRamAssertion; use super::runtime::ValidationRuntime; diff --git a/rom_test/src/runner/validation/runtime.rs b/rom_test/src/runner/validation/runtime.rs index db6922b1..bc9edd02 100644 --- a/rom_test/src/runner/validation/runtime.rs +++ b/rom_test/src/runner/validation/runtime.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod bootstrap; mod controller; mod execution; diff --git a/rom_test/src/runner/validation/runtime/bootstrap.rs b/rom_test/src/runner/validation/runtime/bootstrap.rs index 832fe636..eca4cf50 100644 --- a/rom_test/src/runner/validation/runtime/bootstrap.rs +++ b/rom_test/src/runner/validation/runtime/bootstrap.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::ValidationRuntime; use crate::error::RomTestError; use crate::manifest::RomCase; diff --git a/rom_test/src/runner/validation/runtime/controller.rs b/rom_test/src/runner/validation/runtime/controller.rs index 67066ec9..634084cc 100644 --- a/rom_test/src/runner/validation/runtime/controller.rs +++ b/rom_test/src/runner/validation/runtime/controller.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::ValidationRuntime; use crate::events::{ButtonCode, ControllerPad, PadState}; use crate::harness::apply_button_state; diff --git a/rom_test/src/runner/validation/runtime/execution.rs b/rom_test/src/runner/validation/runtime/execution.rs index 70819f28..7a29b0c7 100644 --- a/rom_test/src/runner/validation/runtime/execution.rs +++ b/rom_test/src/runner/validation/runtime/execution.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::ValidationRuntime; impl ValidationRuntime { diff --git a/rom_test/src/runner/validation/runtime/inspection.rs b/rom_test/src/runner/validation/runtime/inspection.rs index 8eca38c5..86872002 100644 --- a/rom_test/src/runner/validation/runtime/inspection.rs +++ b/rom_test/src/runner/validation/runtime/inspection.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::ValidationRuntime; use crate::error::RomTestError; use crate::media::{encode_screenshot_png, screen_hash}; diff --git a/rom_test/src/serde_helpers.rs b/rom_test/src/serde_helpers.rs index a9b3ebb9..9183f378 100644 --- a/rom_test/src/serde_helpers.rs +++ b/rom_test/src/serde_helpers.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use serde::de::{self, Visitor}; use std::fmt; diff --git a/rom_test/src/tests.rs b/rom_test/src/tests.rs index 7c6f2018..f28b053c 100644 --- a/rom_test/src/tests.rs +++ b/rom_test/src/tests.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::error::RomTestError; use super::events::{ ButtonCode, ControllerPad, MemoryAssertionSpace, PadState, RomAssertion, RomEvent, RomEventKind, diff --git a/rom_test/tests/lib.rs b/rom_test/tests/lib.rs index bac6a191..760cd413 100644 --- a/rom_test/tests/lib.rs +++ b/rom_test/tests/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use nerust_rom_test::manifest::{RomManifest, load_default_manifest}; use nerust_rom_test::results::{CaseOutcome, ValidationOptions}; use nerust_rom_test::runner::validate_case; diff --git a/roms/snes-apu-tests/dsp-register-smoke/README.md b/roms/snes-apu-tests/dsp-register-smoke/README.md new file mode 100644 index 00000000..2001759b --- /dev/null +++ b/roms/snes-apu-tests/dsp-register-smoke/README.md @@ -0,0 +1,17 @@ +# SNES APU DSP Register Smoke Test ROM + +A small self-authored SNES APU test ROM for the nerust `rom_test` harness. + +The S-CPU uploads a tiny SPC700 program through the IPL protocol. The SPC700 +program disables the IPL overlay, writes and reads APU DSP register data through +`$F2/$F3`, exercises the auxiliary APU IO bytes at `$F8/$F9`, and reports the +observed values back through CPU-visible APU ports. The S-CPU copies the final +ports into WRAM `$7E:0000-$7E:0003` for manifest assertions, while the manifest +also checks the APU RAM result bytes. + +The ROM leaves display output blank; `rom_test` still captures a deterministic +final screen hash and screenshot. + +## License + +Public domain. Use freely for emulator testing, development, and validation. diff --git a/roms/snes-apu-tests/dsp-register-smoke/build/ApuDspRegisterSmoke.sfc b/roms/snes-apu-tests/dsp-register-smoke/build/ApuDspRegisterSmoke.sfc new file mode 100644 index 00000000..be1f8c22 Binary files /dev/null and b/roms/snes-apu-tests/dsp-register-smoke/build/ApuDspRegisterSmoke.sfc differ diff --git a/roms/snes-apu-tests/dsp-register-smoke/generate_rom.py b/roms/snes-apu-tests/dsp-register-smoke/generate_rom.py new file mode 100644 index 00000000..dcd8c5ed --- /dev/null +++ b/roms/snes-apu-tests/dsp-register-smoke/generate_rom.py @@ -0,0 +1,175 @@ +#!/usr/bin/env python3 + +from pathlib import Path + +ROM_SIZE = 64 * 1024 +HEADER_OFFSET = 0x7FC0 +RESET_VECTOR_OFFSET = 0x7FFC +PROGRAM_ADDRESS = 0x8000 +PROGRAM_OFFSET = PROGRAM_ADDRESS - 0x8000 +SPC_ENTRY = 0x0300 +OUTPUT_PATH = Path(__file__).resolve().parent / "build" / "ApuDspRegisterSmoke.sfc" + + +def u16(value): + return [value & 0xFF, (value >> 8) & 0xFF] + + +def lda_imm(value): + return [0xA9, value & 0xFF] + + +def lda_abs(address): + return [0xAD, *u16(address)] + + +def sta_abs(address): + return [0x8D, *u16(address)] + + +def sta_long(bank, address): + return [0x8F, address & 0xFF, (address >> 8) & 0xFF, bank & 0xFF] + + +def cmp_imm(value): + return [0xC9, value & 0xFF] + + +def wait_abs_eq(address, value): + return [*lda_abs(address), *cmp_imm(value), 0xD0, 0xF9] + + +def store_imm_abs(value, address): + return [*lda_imm(value), *sta_abs(address)] + + +def copy_abs_to_wram(source, destination): + return [*lda_abs(source), *sta_long(0x7E, destination)] + + +def build_spc_program(): + return bytes( + [ + 0x8F, + 0x00, + 0xF1, # MOV $F1,#$00: disable IPL ROM overlay + 0x8F, + 0x0C, + 0xF2, # MOV $F2,#$0C: select MVOLL + 0x8F, + 0x7F, + 0xF3, # MOV $F3,#$7F + 0xE4, + 0xF3, # MOV A,$F3 + 0xC4, + 0x20, # MOV $20,A + 0xC4, + 0xF5, # MOV $F5,A + 0x8F, + 0x2C, + 0xF2, # MOV $F2,#$2C: select EVOLL + 0x8F, + 0x40, + 0xF3, # MOV $F3,#$40 + 0xE4, + 0xF3, # MOV A,$F3 + 0xC4, + 0x21, # MOV $21,A + 0xC4, + 0xF6, # MOV $F6,A + 0xE4, + 0xF2, # MOV A,$F2 + 0xC4, + 0x22, # MOV $22,A + 0xC4, + 0xF7, # MOV $F7,A + 0x8F, + 0x12, + 0xF8, # MOV $F8,#$12 + 0x8F, + 0x34, + 0xF9, # MOV $F9,#$34 + 0xE4, + 0xF8, # MOV A,$F8 + 0xC4, + 0x23, # MOV $23,A + 0xE4, + 0xF9, # MOV A,$F9 + 0xC4, + 0x24, # MOV $24,A + 0x8F, + 0xA5, + 0xF4, # MOV $F4,#$A5: success marker + 0xFF, # STOP + ] + ) + + +def build_program(): + spc_program = build_spc_program() + if len(spc_program) > 0xFD: + raise ValueError("SPC program is too large for the one-page IPL uploader") + + code = [] + code += wait_abs_eq(0x2140, 0xAA) + code += wait_abs_eq(0x2141, 0xBB) + code += store_imm_abs(SPC_ENTRY & 0xFF, 0x2142) + code += store_imm_abs(SPC_ENTRY >> 8, 0x2143) + code += store_imm_abs(0x01, 0x2141) + code += store_imm_abs(0xCC, 0x2140) + code += wait_abs_eq(0x2140, 0xCC) + + for index, value in enumerate(spc_program): + code += store_imm_abs(value, 0x2141) + code += store_imm_abs(index, 0x2140) + code += wait_abs_eq(0x2140, index) + + kick = (len(spc_program) + 2) | 1 + code += store_imm_abs(SPC_ENTRY & 0xFF, 0x2142) + code += store_imm_abs(SPC_ENTRY >> 8, 0x2143) + code += store_imm_abs(0x00, 0x2141) + code += store_imm_abs(kick, 0x2140) + code += wait_abs_eq(0x2140, kick) + code += wait_abs_eq(0x2140, 0xA5) + + for port in range(4): + code += copy_abs_to_wram(0x2140 + port, port) + + code += [0x80, 0xFE] + return bytes(code) + + +def write_header(rom): + title = b"NERUST APU DSP SMOKE " + rom[HEADER_OFFSET : HEADER_OFFSET + len(title)] = title + rom[HEADER_OFFSET + 0x15] = 0x20 # LoROM map mode + rom[HEADER_OFFSET + 0x16] = 0x00 # ROM only + rom[HEADER_OFFSET + 0x17] = 0x06 # 64 KiB ROM + rom[HEADER_OFFSET + 0x18] = 0x00 # no cartridge RAM + rom[HEADER_OFFSET + 0x19] = 0x01 # NTSC + rom[HEADER_OFFSET + 0x1A] = 0x33 # maker code + rom[HEADER_OFFSET + 0x1B] = 0x00 # version + + for vector_offset in (0x7FEA, 0x7FEC, 0x7FEE, 0x7FFA, RESET_VECTOR_OFFSET, 0x7FFE): + rom[vector_offset : vector_offset + 2] = bytes(u16(PROGRAM_ADDRESS)) + + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x20] = b"\x00\x00\x00\x00" + checksum = sum(rom) & 0xFFFF + complement = checksum ^ 0xFFFF + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x1E] = bytes(u16(complement)) + rom[HEADER_OFFSET + 0x1E : HEADER_OFFSET + 0x20] = bytes(u16(checksum)) + + +def main(): + rom = bytearray([0xFF] * ROM_SIZE) + program = build_program() + rom[PROGRAM_OFFSET : PROGRAM_OFFSET + len(program)] = program + write_header(rom) + + OUTPUT_PATH.parent.mkdir(parents=True, exist_ok=True) + OUTPUT_PATH.write_bytes(rom) + print(f"wrote {OUTPUT_PATH} ({len(rom)} bytes)") + + +if __name__ == "__main__": + main() diff --git a/roms/snes-coprocessor-tests/cx4-smoke/.gitignore b/roms/snes-coprocessor-tests/cx4-smoke/.gitignore new file mode 100644 index 00000000..7a60b85e --- /dev/null +++ b/roms/snes-coprocessor-tests/cx4-smoke/.gitignore @@ -0,0 +1,2 @@ +__pycache__/ +*.pyc diff --git a/roms/snes-coprocessor-tests/cx4-smoke/BUILD.md b/roms/snes-coprocessor-tests/cx4-smoke/BUILD.md new file mode 100644 index 00000000..86508d0c --- /dev/null +++ b/roms/snes-coprocessor-tests/cx4-smoke/BUILD.md @@ -0,0 +1,20 @@ +# Building + +## Prerequisites + +- Python 3 + +No external packages or assembler toolchains are required. + +## Build + +```bash +python3 generate_rom.py +``` + +Output: + +- `build/Cx4Smoke.sfc` - 64 KiB LoROM CX4 test ROM + +The generator writes the 65C816 machine code and SNES header directly so the +artifact is deterministic and easy to reproduce in CI or locally. diff --git a/roms/snes-coprocessor-tests/cx4-smoke/README.md b/roms/snes-coprocessor-tests/cx4-smoke/README.md new file mode 100644 index 00000000..1735ebdc --- /dev/null +++ b/roms/snes-coprocessor-tests/cx4-smoke/README.md @@ -0,0 +1,19 @@ +# SNES CX4 Smoke Test ROM + +A small self-authored SNES CX4 test ROM for the nerust `rom_test` harness. + +The program runs on the S-CPU with a CX4 cartridge header and verifies a +minimal set of host-visible CX4 behavior: + +- CX4 cartridge header detection (`map mode $20`, chipset `$F3`, subtype `$10`) +- CX4 24-bit multiply command `$25` +- CX4 identification command `$89` +- CX4 busy-status reads + +Results are copied into WRAM `$7E:0000-$7E:0006` for manifest assertions. The +ROM leaves display output blank; `rom_test` still captures a deterministic +final screen hash and screenshot. + +## License + +Public domain. Use freely for emulator testing, development, and validation. diff --git a/roms/snes-coprocessor-tests/cx4-smoke/UPSTREAM.md b/roms/snes-coprocessor-tests/cx4-smoke/UPSTREAM.md new file mode 100644 index 00000000..74d0083f --- /dev/null +++ b/roms/snes-coprocessor-tests/cx4-smoke/UPSTREAM.md @@ -0,0 +1,11 @@ +# Provenance + +This ROM is self-authored for nerust and is generated from `generate_rom.py` in +this directory. + +- No external ROM image or commercial/proprietary content is used. +- No git subtree import is required because there is no upstream repository. +- The generated artifact committed for the `rom_test` harness is: + - `build/Cx4Smoke.sfc` + - SHA-256: + `e5a13f04959d84f7cef6614bb56248401c5d3b3afe8364d3a88bd787878bd3b1` diff --git a/roms/snes-coprocessor-tests/cx4-smoke/build/Cx4Smoke.sfc b/roms/snes-coprocessor-tests/cx4-smoke/build/Cx4Smoke.sfc new file mode 100644 index 00000000..04628931 Binary files /dev/null and b/roms/snes-coprocessor-tests/cx4-smoke/build/Cx4Smoke.sfc differ diff --git a/roms/snes-coprocessor-tests/cx4-smoke/generate_rom.py b/roms/snes-coprocessor-tests/cx4-smoke/generate_rom.py new file mode 100644 index 00000000..195f4294 --- /dev/null +++ b/roms/snes-coprocessor-tests/cx4-smoke/generate_rom.py @@ -0,0 +1,105 @@ +#!/usr/bin/env python3 + +from pathlib import Path + +ROM_SIZE = 64 * 1024 +HEADER_OFFSET = 0x7FC0 +RESET_VECTOR_OFFSET = 0x7FFC +PROGRAM_ADDRESS = 0x8000 +PROGRAM_OFFSET = PROGRAM_ADDRESS - 0x8000 +OUTPUT_PATH = Path(__file__).resolve().parent / "build" / "Cx4Smoke.sfc" + + +def u16(value): + return [value & 0xFF, (value >> 8) & 0xFF] + + +def lda_imm(value): + return [0xA9, value & 0xFF] + + +def lda_abs(address): + return [0xAD, *u16(address)] + + +def sta_abs(address): + return [0x8D, *u16(address)] + + +def sta_long(bank, address): + return [0x8F, address & 0xFF, (address >> 8) & 0xFF, bank & 0xFF] + + +def store_imm_abs(value, address): + return [*lda_imm(value), *sta_abs(address)] + + +def copy_abs_to_wram(source, destination): + return [*lda_abs(source), *sta_long(0x7E, destination)] + + +def build_program(): + code = [] + + # CX4 command $25 multiplies two little-endian 24-bit inputs at $7F80. + for value, address in ( + (0x23, 0x7F80), + (0x01, 0x7F81), + (0x00, 0x7F82), + (0x04, 0x7F83), + (0x00, 0x7F84), + (0x00, 0x7F85), + ): + code += store_imm_abs(value, address) + code += store_imm_abs(0x25, 0x7F4F) + code += copy_abs_to_wram(0x7F80, 0x0000) + code += copy_abs_to_wram(0x7F81, 0x0001) + code += copy_abs_to_wram(0x7F82, 0x0002) + + # CX4 command $89 returns the CX4 identifier bytes 36 43 05. + code += store_imm_abs(0x89, 0x7F4F) + code += copy_abs_to_wram(0x7F80, 0x0003) + code += copy_abs_to_wram(0x7F81, 0x0004) + code += copy_abs_to_wram(0x7F82, 0x0005) + code += copy_abs_to_wram(0x7F5E, 0x0006) + + # Stay alive for benchmark frame loops. + code += [0x80, 0xFE] + return bytes(code) + + +def write_header(rom): + title = b"NERUST CX4 SMOKE " + rom[HEADER_OFFSET - 1] = 0x10 # CX4 expansion subtype + rom[HEADER_OFFSET : HEADER_OFFSET + len(title)] = title + rom[HEADER_OFFSET + 0x15] = 0x20 # LoROM map mode + rom[HEADER_OFFSET + 0x16] = 0xF3 # coprocessor family with enhancement subtype + rom[HEADER_OFFSET + 0x17] = 0x06 # 64 KiB ROM + rom[HEADER_OFFSET + 0x18] = 0x00 # no cartridge RAM + rom[HEADER_OFFSET + 0x19] = 0x01 # NTSC + rom[HEADER_OFFSET + 0x1A] = 0x33 # maker code + rom[HEADER_OFFSET + 0x1B] = 0x00 # version + + for vector_offset in (0x7FEA, 0x7FEC, 0x7FEE, 0x7FFA, RESET_VECTOR_OFFSET, 0x7FFE): + rom[vector_offset : vector_offset + 2] = bytes(u16(PROGRAM_ADDRESS)) + + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x20] = b"\x00\x00\x00\x00" + checksum = sum(rom) & 0xFFFF + complement = checksum ^ 0xFFFF + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x1E] = bytes(u16(complement)) + rom[HEADER_OFFSET + 0x1E : HEADER_OFFSET + 0x20] = bytes(u16(checksum)) + + +def main(): + rom = bytearray([0xFF] * ROM_SIZE) + program = build_program() + rom[PROGRAM_OFFSET : PROGRAM_OFFSET + len(program)] = program + write_header(rom) + + OUTPUT_PATH.parent.mkdir(parents=True, exist_ok=True) + OUTPUT_PATH.write_bytes(rom) + print(f"wrote {OUTPUT_PATH} ({len(rom)} bytes)") + + +if __name__ == "__main__": + main() diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/.gitignore b/roms/snes-coprocessor-tests/dsp1-smoke/.gitignore new file mode 100644 index 00000000..7a60b85e --- /dev/null +++ b/roms/snes-coprocessor-tests/dsp1-smoke/.gitignore @@ -0,0 +1,2 @@ +__pycache__/ +*.pyc diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/BUILD.md b/roms/snes-coprocessor-tests/dsp1-smoke/BUILD.md new file mode 100644 index 00000000..e9afc09d --- /dev/null +++ b/roms/snes-coprocessor-tests/dsp1-smoke/BUILD.md @@ -0,0 +1,25 @@ +# Building + +## Prerequisites + +- Python 3 + +No external packages or assembler toolchains are required. + +## Build + +```bash +python3 generate_rom.py +``` + +Output: + +- `build/Dsp1Smoke.sfc` - 64 KiB LoROM DSP-1 test ROM +- `build/Dsp1aSmoke.sfc` - 64 KiB LoROM DSP-1A-compatible test ROM +- `build/Dsp1bSmoke.sfc` - 64 KiB HiROM DSP-1B test ROM +- `build/Dsp1GeometrySmoke.sfc` - 64 KiB LoROM DSP-1 geometry test ROM +- `build/Dsp1aGeometrySmoke.sfc` - 64 KiB LoROM DSP-1A-compatible geometry test ROM +- `build/Dsp1bGeometrySmoke.sfc` - 64 KiB HiROM DSP-1B geometry test ROM + +The generator writes the 65C816 machine code and SNES headers directly so the +artifacts are deterministic and easy to reproduce in CI or locally. diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/README.md b/roms/snes-coprocessor-tests/dsp1-smoke/README.md new file mode 100644 index 00000000..064efc52 --- /dev/null +++ b/roms/snes-coprocessor-tests/dsp1-smoke/README.md @@ -0,0 +1,30 @@ +# SNES DSP-1 Family Smoke Test ROMs + +Small self-authored SNES DSP-1 family test ROMs for the nerust `rom_test` +harness. + +The generated ROMs run on the S-CPU and verify minimal host-visible DSP-1 +behavior through the cartridge DSP data/status ports: + +- DSP-1 LoROM header detection (`map mode $20`, chipset `$03`) +- DSP-1A-compatible LoROM header detection (`map mode $30`, chipset `$05`) +- DSP-1B HiROM header detection (`map mode $21`, chipset `$05`) +- DSP command `$00` fixed-point multiply +- DSP command `$27` memory-size/ROM-version response +- DSP geometry/scalar commands: + - `$04` sine/cosine + - `$0C` 2D rotation + - `$1C` 3D rotation + - `$28` vector length + - `$08` squared radius + - `$10` inverse +- reset-ready status after command completion + +Basic command results are copied into WRAM `$7E:0000-$7E:0004`; geometry command +results are copied into WRAM `$7E:0010-$7E:0028` for manifest assertions. The +ROMs leave display output blank; `rom_test` still captures deterministic final +screen hashes and screenshots. + +## License + +Public domain. Use freely for emulator testing, development, and validation. diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/UPSTREAM.md b/roms/snes-coprocessor-tests/dsp1-smoke/UPSTREAM.md new file mode 100644 index 00000000..56edc900 --- /dev/null +++ b/roms/snes-coprocessor-tests/dsp1-smoke/UPSTREAM.md @@ -0,0 +1,26 @@ +# Provenance + +These ROMs are self-authored for nerust and are generated from +`generate_rom.py` in this directory. + +- No external ROM image or commercial/proprietary content is used. +- No git subtree import is required because there is no upstream repository. +- The generated artifacts committed for the `rom_test` harness are: + - `build/Dsp1Smoke.sfc` + - SHA-256: + `bec587f10ebddb06538b3a236a5c9bc24772206ffd10af44662040fcfd3a7209` + - `build/Dsp1aSmoke.sfc` + - SHA-256: + `864d99726ad6aff58292d4bacc3129baf155d0712f69f062e70667d24360bcab` + - `build/Dsp1bSmoke.sfc` + - SHA-256: + `72af15130ee0149a664cbeb703906be49ca936beaf44817aeefb4fbdc4abaee6` + - `build/Dsp1GeometrySmoke.sfc` + - SHA-256: + `e47e81f2a28ee06368870135d430b7578473fa584e5fa7c6ec5018d26160a898` + - `build/Dsp1aGeometrySmoke.sfc` + - SHA-256: + `8877dfc5af18674fc6dc4100e411388b2a7236a2b0f8d8e89b943afbf5541c40` + - `build/Dsp1bGeometrySmoke.sfc` + - SHA-256: + `920eda8025d5ed3acf3444c697b8dc9d0837fcf7715ecfc8edf6575f1b187968` diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1GeometrySmoke.sfc b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1GeometrySmoke.sfc new file mode 100644 index 00000000..28c2595e Binary files /dev/null and b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1GeometrySmoke.sfc differ diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1Smoke.sfc b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1Smoke.sfc new file mode 100644 index 00000000..f635ddf2 Binary files /dev/null and b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1Smoke.sfc differ diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aGeometrySmoke.sfc b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aGeometrySmoke.sfc new file mode 100644 index 00000000..7ff8be48 Binary files /dev/null and b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aGeometrySmoke.sfc differ diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aSmoke.sfc b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aSmoke.sfc new file mode 100644 index 00000000..199f80b4 Binary files /dev/null and b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1aSmoke.sfc differ diff --git a/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1bGeometrySmoke.sfc b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1bGeometrySmoke.sfc new file mode 100644 index 00000000..faa912f4 --- /dev/null +++ b/roms/snes-coprocessor-tests/dsp1-smoke/build/Dsp1bGeometrySmoke.sfc @@ -0,0 +1 @@ +````@``~`~`~`~ ```#``܏```~`~`~`~``````````` ```~`~`~`~`~`~(````` ```~`~````` ``` ~`!~`"~`#~``@````$~`%~`&~`'~p(~NERUST DSP1B GEOM !3> 8) & 0xFF] + + +def lda_imm(value): + return [0xA9, value & 0xFF] + + +def lda_long(bank, address): + return [0xAF, address & 0xFF, (address >> 8) & 0xFF, bank & 0xFF] + + +def sta_long(bank, address): + return [0x8F, address & 0xFF, (address >> 8) & 0xFF, bank & 0xFF] + + +def write_imm_long(value, bank, address): + return [*lda_imm(value), *sta_long(bank, address)] + + +def copy_long_to_wram(source_bank, source_address, destination): + return [*lda_long(source_bank, source_address), *sta_long(0x7E, destination)] + + +def copy_dsp_word_to_wram(code, data_bank, data_address, destination): + code += copy_long_to_wram(data_bank, data_address, destination) + code += copy_long_to_wram(data_bank, data_address, destination + 1) + + +def write_dsp_word(code, data_bank, data_address, value): + code += write_imm_long(value & 0xFF, data_bank, data_address) + code += write_imm_long((value >> 8) & 0xFF, data_bank, data_address) + + +def build_program(data_bank, data_address, status_bank, status_address): + code = [] + + # Command $00: signed fixed-point multiply. $4000 * $4000 => $2000. + code += write_imm_long(0x00, data_bank, data_address) + write_dsp_word(code, data_bank, data_address, 0x4000) + write_dsp_word(code, data_bank, data_address, 0x4000) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0000) + + # Command $27: memory size / ROM version. DSP-1/1A return $0100, DSP-1B returns $0101. + code += write_imm_long(0x27, data_bank, data_address) + write_dsp_word(code, data_bank, data_address, 0x0000) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0002) + code += copy_long_to_wram(status_bank, status_address, 0x0004) + + # Stay alive for benchmark frame loops. + code += [0x80, 0xFE] + return bytes(code) + + +def build_geometry_program(data_bank, data_address, status_bank, status_address): + code = [] + + # Command $04: sin/cos. angle 0, radius $4000 => sin 0, cos $4000. + code += write_imm_long(0x04, data_bank, data_address) + write_dsp_word(code, data_bank, data_address, 0x0000) + write_dsp_word(code, data_bank, data_address, 0x4000) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0010) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0012) + + # Command $0C: 2D rotation. angle 0 leaves X/Y unchanged. + code += write_imm_long(0x0C, data_bank, data_address) + write_dsp_word(code, data_bank, data_address, 0x0000) + write_dsp_word(code, data_bank, data_address, 0x0123) + write_dsp_word(code, data_bank, data_address, 0xFEDC) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0014) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0016) + + # Command $1C: 3D rotation. zero Euler angles leave X/Y/Z unchanged. + code += write_imm_long(0x1C, data_bank, data_address) + for value in (0x0000, 0x0000, 0x0000, 0x0003, 0xFFFC, 0x000C): + write_dsp_word(code, data_bank, data_address, value) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0018) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x001A) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x001C) + + # Command $28: vector length. sqrt(3^2 + 4^2 + 12^2) => 13. + code += write_imm_long(0x28, data_bank, data_address) + for value in (0x0003, 0x0004, 0x000C): + write_dsp_word(code, data_bank, data_address, value) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x001E) + + # Command $08: radius/squared-length. 3^2 + 4^2 + 12^2 => $000000A9. + code += write_imm_long(0x08, data_bank, data_address) + for value in (0x0003, 0x0004, 0x000C): + write_dsp_word(code, data_bank, data_address, value) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0020) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0022) + + # Command $10: inverse. coefficient $4000, exponent 0 => $7FFF, $0001. + code += write_imm_long(0x10, data_bank, data_address) + write_dsp_word(code, data_bank, data_address, 0x4000) + write_dsp_word(code, data_bank, data_address, 0x0000) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0024) + copy_dsp_word_to_wram(code, data_bank, data_address, 0x0026) + code += copy_long_to_wram(status_bank, status_address, 0x0028) + + # Stay alive for benchmark frame loops. + code += [0x80, 0xFE] + return bytes(code) + + +def write_header(rom, *, header_offset, reset_vector_offset, title, map_mode, chipset, ram_size=0): + encoded_title = title.encode("ascii")[:21].ljust(21, b" ") + + rom[header_offset : header_offset + len(encoded_title)] = encoded_title + rom[header_offset + 0x15] = map_mode + rom[header_offset + 0x16] = chipset + rom[header_offset + 0x17] = 0x06 # 64 KiB ROM + rom[header_offset + 0x18] = ram_size + rom[header_offset + 0x19] = 0x01 # NTSC + rom[header_offset + 0x1A] = 0x33 # maker code + rom[header_offset + 0x1B] = 0x00 # version + + for vector_offset in ( + reset_vector_offset - 0x12, + reset_vector_offset - 0x10, + reset_vector_offset - 0x0E, + reset_vector_offset - 0x02, + reset_vector_offset, + reset_vector_offset + 0x02, + ): + rom[vector_offset : vector_offset + 2] = bytes(u16(PROGRAM_ADDRESS)) + + rom[header_offset + 0x1C : header_offset + 0x20] = b"\x00\x00\x00\x00" + checksum = sum(rom) & 0xFFFF + complement = checksum ^ 0xFFFF + rom[header_offset + 0x1C : header_offset + 0x1E] = bytes(u16(complement)) + rom[header_offset + 0x1E : header_offset + 0x20] = bytes(u16(checksum)) + + +def write_rom(filename, program, header, program_offset): + rom = bytearray([0xFF] * ROM_SIZE) + rom[program_offset : program_offset + len(program)] = program + write_header(rom, **header) + + output_path = OUTPUT_DIR / filename + output_path.parent.mkdir(parents=True, exist_ok=True) + output_path.write_bytes(rom) + print(f"wrote {output_path} ({len(rom)} bytes)") + + +def main(): + write_rom( + "Dsp1Smoke.sfc", + build_program(0x20, 0x8000, 0x20, 0xC000), + { + "header_offset": LOROM_HEADER_OFFSET, + "reset_vector_offset": LOROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1 SMOKE ", + "map_mode": 0x20, + "chipset": 0x03, + }, + LOROM_PROGRAM_OFFSET, + ) + write_rom( + "Dsp1aSmoke.sfc", + build_program(0x20, 0x8000, 0x20, 0xC000), + { + "header_offset": LOROM_HEADER_OFFSET, + "reset_vector_offset": LOROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1A SMOKE ", + "map_mode": 0x30, + "chipset": 0x05, + }, + LOROM_PROGRAM_OFFSET, + ) + write_rom( + "Dsp1bSmoke.sfc", + build_program(0x00, 0x6000, 0x00, 0x7000), + { + "header_offset": HIROM_HEADER_OFFSET, + "reset_vector_offset": HIROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1B SMOKE ", + "map_mode": 0x21, + "chipset": 0x05, + "ram_size": 0x02, + }, + HIROM_PROGRAM_OFFSET, + ) + write_rom( + "Dsp1GeometrySmoke.sfc", + build_geometry_program(0x20, 0x8000, 0x20, 0xC000), + { + "header_offset": LOROM_HEADER_OFFSET, + "reset_vector_offset": LOROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1 GEOM ", + "map_mode": 0x20, + "chipset": 0x03, + }, + LOROM_PROGRAM_OFFSET, + ) + write_rom( + "Dsp1aGeometrySmoke.sfc", + build_geometry_program(0x20, 0x8000, 0x20, 0xC000), + { + "header_offset": LOROM_HEADER_OFFSET, + "reset_vector_offset": LOROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1A GEOM ", + "map_mode": 0x30, + "chipset": 0x05, + }, + LOROM_PROGRAM_OFFSET, + ) + write_rom( + "Dsp1bGeometrySmoke.sfc", + build_geometry_program(0x00, 0x6000, 0x00, 0x7000), + { + "header_offset": HIROM_HEADER_OFFSET, + "reset_vector_offset": HIROM_RESET_VECTOR_OFFSET, + "title": "NERUST DSP1B GEOM ", + "map_mode": 0x21, + "chipset": 0x05, + "ram_size": 0x02, + }, + HIROM_PROGRAM_OFFSET, + ) + + +if __name__ == "__main__": + main() diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/.github/workflows/release.yml b/roms/snes-coprocessor-tests/hirom-gsu-test/.github/workflows/release.yml new file mode 100644 index 00000000..802a3e4d --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/.github/workflows/release.yml @@ -0,0 +1,77 @@ +name: Build and Release +'on': + push: + tags: + - 'v*' +permissions: + contents: write +jobs: + build: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v4 + - name: Install build dependencies + run: | + sudo apt-get update + sudo apt-get install -y cmake build-essential + - name: Build WLA-DX v9.12 + run: | + git clone --depth 1 --branch v9.12 \ + https://github.com/vhelin/wla-dx.git /tmp/wla-dx + cd /tmp/wla-dx && mkdir build && cd build + cmake .. + make -j"$(nproc)" + mkdir -p tools/wla-dx + cp /tmp/wla-dx/build/binaries/wla-65816 tools/wla-dx/wla-65816 + cp /tmp/wla-dx/build/binaries/wlalink tools/wla-dx/wlalink + chmod +x tools/wla-dx/* + - name: Download Bass v18 + run: | + mkdir -p tools/bass + gh release download v18 \ + --repo ARM9/bass \ + --pattern bass-ubuntu.zip \ + --dir /tmp + unzip /tmp/bass-ubuntu.zip -d /tmp/bass-release + cp /tmp/bass-release/bass tools/bass/bass.exe + chmod +x tools/bass/bass.exe + env: + GH_TOKEN: ${{ github.token }} + - name: Build ROM + run: | + chmod +x tools/wla-dx/* tools/bass/bass.exe + make clean && make + - name: Verify ROM + run: | + ls -la build/HiRomGsuTest.sfc build/HiRomGsuTest.msu + python3 -c " + data = open('build/HiRomGsuTest.sfc','rb').read() + assert len(data) == 4194304, f'Wrong size: {len(data)}' + print(f'Size: {len(data)} bytes') + print(f'Title: {data[0xFFC0:0xFFD5].decode(\"ascii\")}') + print(f'Mapping: 0x{data[0xFFD5]:02X}') + print('ROM OK') + " + - name: Create release archive + run: | + mkdir -p release + cp build/HiRomGsuTest.sfc \ + build/HiRomGsuTest.msu \ + hirom_gsu_test.bml \ + release/ + cd release && zip ../HiRomGsuTest-${{ github.ref_name }}.zip * + - name: Create GitHub Release + uses: softprops/action-gh-release@v2 + with: + files: | + HiRomGsuTest-${{ github.ref_name }}.zip + build/HiRomGsuTest.sfc + body: | + ## HiROM+GSU+MSU-1 Test ROM ${{ github.ref_name }} + + 4 MB standalone SNES test ROM for validating HiROM + SuperFX + (GSU-2) + MSU-1. + + **Download `HiRomGsuTest-${{ github.ref_name }}.zip`** — contains + `.sfc`, `.msu`, and `.bml` files. Place all three in the same + directory. diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/.gitignore b/roms/snes-coprocessor-tests/hirom-gsu-test/.gitignore new file mode 100644 index 00000000..255c2556 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/.gitignore @@ -0,0 +1,3 @@ +build/ +__pycache__/ +*.pyc diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/BUILD.md b/roms/snes-coprocessor-tests/hirom-gsu-test/BUILD.md new file mode 100644 index 00000000..9c866dc4 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/BUILD.md @@ -0,0 +1,71 @@ +# Building + +## Prerequisites + +- **Python 3** (any version, no packages needed) +- **WSL** or native Linux (the included tool binaries are Linux ELF + Windows PE) + +The assembler toolchain is bundled in `tools/`: +- [WLA-DX](https://github.com/vhelin/wla-dx) v9.3 — `wla-65816` (65816 assembler) + `wlalink` (linker) +- [Bass](https://github.com/ARM9/bass) v18 — `bass.exe` (GSU assembler, runs via WSL interop) + +## Build + +```bash +# WSL or Linux: +make + +# Windows PowerShell: +wsl -e bash -lc "cd /mnt/path/to/SNES-HiRomGsuTest && make" +``` + +Output: +- `build/HiRomGsuTest.sfc` — 4 MB ROM +- `build/HiRomGsuTest.msu` — 4 KB MSU-1 companion data file + +## Build Pipeline + +``` +gen_font.py ────────────────► build/font.bin (760B, 1bpp 8x8 font) +pixel_test.gsu ───[bass]───► build/pixel_test.bin (26B, GSU test binary) +gsu_demo.gsu ─────[bass]───► build/gsu_demo.bin (103B, GSU demo binary) +test_rom.65816 ───[wla]────► build/test_rom.o +test_rom.o ───────[wlalink]─► build/HiRomGsuTest.sfc (4 MB) + [python]──► inject bank signatures + [python]──► build/HiRomGsuTest.msu (4 KB) +``` + +## Clean + +```bash +make clean +``` + +## Distribution + +Place these files together for emulator/hardware testing: + +``` +HiRomGsuTest.sfc # ROM (required) +HiRomGsuTest.msu # MSU-1 data (required for MSU-1 detection) +hirom_gsu_test.bml # bsnes manifest (optional, bsnes only) +``` + +## File Structure + +``` +test_rom.65816 Main 65816 assembly (code, strings, palettes, data) +test_rom.h WLA-DX memory map (4MB HiROM, 64 banks) +pixel_test.gsu GSU-2 pixel plot test (Bass syntax) +gsu_demo.gsu GSU-2 rainbow demo (Bass syntax) +gen_font.py 8x8 1bpp font generator +inject_signatures.py Post-link: writes bank ID at $FFA0 per bank +makefile Build orchestration +linkfile.lnk WLA-DX linker configuration +hirom_gsu_test.bml bsnes board manifest +tools/ + bass/bass.exe Bass v18 assembler (Windows PE, runs via WSL interop) + bass/architectures/ GSU instruction set definition + wla-dx/wla-65816 WLA-DX v9.3 assembler (Linux ELF) + wla-dx/wlalink WLA-DX v9.3 linker (Linux ELF) +``` diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/README.md b/roms/snes-coprocessor-tests/hirom-gsu-test/README.md new file mode 100644 index 00000000..c55ee249 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/README.md @@ -0,0 +1,78 @@ +# SNES HiROM+GSU+MSU-1 Test ROM + +A standalone **4 MB** test ROM for validating **HiROM + SuperFX (GSU-2) + MSU-1** coprocessor configurations in SNES emulators and flash cartridges. + +No commercial SNES cartridge ever combined HiROM with SuperFX — all retail SuperFX games used LoROM. This ROM exists because homebrew projects targeting modern flash cartridges (FXPak Pro) can benefit from HiROM's 64KB contiguous banks alongside the GSU-2 coprocessor. + +## Screenshots + +| Mesen 2 | bsnes v115 | +|---------|------------| +| ![Mesen 2](mesen_screenshot.png) | ![bsnes v115](bsnes_screenshot.png) | + +9 hardware tests with color-coded results (green=PASS, red=FAIL, yellow=SKIP, cyan=info). The rainbow sprite at bottom-left is rendered by the GSU-2 — 15 colors written to Game Pak RAM by the SuperFX, DMA'd to VRAM, displayed via OAM. + +## Tests + +| Test | Verifies | Pass Condition | +|------|----------|----------------| +| **HiROM Mapping** | RESET vector readable from `$C0:FFFC` and `$00:FFFC` | Values match | +| **ROM Banks** | Unique signature at `$FFA0` in each of 62 ROM banks (`$C0`-`$EF`, `$F2`-`$FF`) | All 62 match | +| **WRAM Read/Write** | Write `$A55A` to `$7E:2000`, read back | Read == Write | +| **GSU-2 VCR** | Version Code Register at `$303B` | VCR == `$04` | +| **GSU SRAM R/W** | Write/read patterns to `$70:0000`-`$70:0003` | Read == Write | +| **GSU Execute** | Copy pixel_test to `$70:0100`, trigger via R15, poll SFR.GO | GSU halts via STOP | +| **Game Pak RAM** | Probe power-of-2 boundaries for address wraparound | Reports detected size | +| **MSU-1 Detect** | Read `$002002`-`$002007`, compare to `S-MSU1` | ID matches | +| **MSU-1 Status** | Read `MSU_STATUS` (`$2000`) | Informational | + +Banks `$F0`-`$F1` are skipped (SRAM mirrors). The companion `.msu` file enables MSU-1 detection in emulators. + +## ROM Configuration + +| Field | Value | +|-------|-------| +| Size | 4 MB (64 banks x 64 KB) | +| Mapping | HiROM + FastROM (`$31`) | +| Cart Type | ROM + GSU + RAM + Battery (`$15`) | +| SRAM | 8 KB at `$70`-`$71` | + +## Running + +### Emulators + +**Mesen 2** (with [HiROM+GSU patch](https://github.com/SourMesen/Mesen2/pull/89)): Load `HiRomGsuTest.sfc` directly. Place `HiRomGsuTest.msu` alongside for MSU-1 detection. + +**bsnes**: Place `hirom_gsu_test.bml` alongside the ROM. + +### Hardware (FXPak Pro) + +Stock FXPak Pro firmware (v1.11.0) does **not** enable the SuperFX FPGA core for HiROM ROMs. A [one-line firmware patch](https://github.com/mrehkopf/sd2snes/pull/289) adds support. Without it, GSU tests show FAIL/SKIPPED but all other tests (HiROM mapping, bank verification, MSU-1) work correctly. + +### Expected Results + +| Platform | HiROM | Banks | GSU VCR | GSU Exec | MSU-1 | +|----------|-------|-------|---------|----------|-------| +| Mesen 2 (patched) | PASS | 62/62 | $04 PASS | PASS | FOUND | +| bsnes (with .bml) | PASS | 62/62 | $04 PASS | PASS | FOUND | +| FXPak Pro (stock) | PASS | 62/62 | $00 FAIL | SKIP | FOUND | +| FXPak Pro (patched) | PASS | 62/62 | $04 PASS | PASS | FOUND | + +## Building + +See [BUILD.md](BUILD.md) for full instructions. + +Quick start (WSL or Linux): +```bash +make # -> build/HiRomGsuTest.sfc + build/HiRomGsuTest.msu +``` + +## Related PRs + +- **Mesen2**: [HiROM+GSU support](https://github.com/SourMesen/Mesen2/pull/89) +- **bsnes**: [HiROM+GSU board recognition](https://github.com/bsnes-emu/bsnes/pull/380) +- **FXPak Pro**: [SuperFX FPGA core for HiROM](https://github.com/mrehkopf/sd2snes/pull/289) + +## License + +Public domain. Use freely for emulator testing, development, and validation. diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/UPSTREAM.md b/roms/snes-coprocessor-tests/hirom-gsu-test/UPSTREAM.md new file mode 100644 index 00000000..9d9fb28a --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/UPSTREAM.md @@ -0,0 +1,21 @@ +# Upstream provenance + +Source: + +- Imported as a git subtree from upstream commit + `8b0c75d91d5dc55ba43c38a8171114399bc2a2e3`. +- Upstream README states: "Public domain. Use freely for emulator testing, + development, and validation." +- This repository includes generated ROM artifacts needed by the SNES rom_test + harness: + - `build/HiRomGsuTest.sfc` + - SHA-256: + `69596b80cf7170041a5226b87301bf9cfff07fb55e7cfce15ebb4144c5cb53b8` + - `build/HiRomGsuTest.msu` + - SHA-256: + `ad7facb2586fc6e966c004d7d1d16b024f5805ff7cb47c7a85dabd8b48892ca7` +- Artifacts were generated from the imported sources with upstream WLA-DX tools + and a native Linux build of ARM9/bass at + `c3962ec01f4768be1667db0d09c12141c28241f3`, using the GSU architecture files + bundled in this subtree. + diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/bsnes_screenshot.png b/roms/snes-coprocessor-tests/hirom-gsu-test/bsnes_screenshot.png new file mode 100644 index 00000000..0dd903c1 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/bsnes_screenshot.png differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.msu b/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.msu new file mode 100644 index 00000000..08e7df17 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.msu differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.sfc b/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.sfc new file mode 100644 index 00000000..1982d2f8 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.sfc differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/build/sprite_scaler.bin b/roms/snes-coprocessor-tests/hirom-gsu-test/build/sprite_scaler.bin new file mode 100644 index 00000000..e172e148 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/build/sprite_scaler.bin differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/gen_font.py b/roms/snes-coprocessor-tests/hirom-gsu-test/gen_font.py new file mode 100644 index 00000000..12b0a0b7 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/gen_font.py @@ -0,0 +1,209 @@ +#!/usr/bin/env python3 +"""Generate 1bpp 8x8 font binary for HiROM+GSU+MSU-1 test ROM. + +Outputs 760 bytes: ASCII 32 (space) through 126 (tilde). +Each glyph is 8 bytes, one per scanline, MSB = leftmost pixel. +Based on the classic IBM PC CGA 8x8 font (public domain). +""" +import sys, os + +FONT = bytes([ + # 32: space + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # 33: ! + 0x18, 0x3C, 0x3C, 0x18, 0x18, 0x00, 0x18, 0x00, + # 34: " + 0x6C, 0x6C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + # 35: hash + 0x6C, 0x6C, 0xFE, 0x6C, 0xFE, 0x6C, 0x6C, 0x00, + # 36: $ + 0x18, 0x7E, 0xC0, 0x7C, 0x06, 0xFC, 0x18, 0x00, + # 37: % + 0x00, 0xC6, 0xCC, 0x18, 0x30, 0x66, 0xC6, 0x00, + # 38: & + 0x38, 0x6C, 0x38, 0x76, 0xDC, 0xCC, 0x76, 0x00, + # 39: ' + 0x18, 0x18, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, + # 40: ( + 0x0C, 0x18, 0x30, 0x30, 0x30, 0x18, 0x0C, 0x00, + # 41: ) + 0x30, 0x18, 0x0C, 0x0C, 0x0C, 0x18, 0x30, 0x00, + # 42: * + 0x00, 0x66, 0x3C, 0xFF, 0x3C, 0x66, 0x00, 0x00, + # 43: + + 0x00, 0x18, 0x18, 0x7E, 0x18, 0x18, 0x00, 0x00, + # 44: , + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x30, + # 45: - + 0x00, 0x00, 0x00, 0x7E, 0x00, 0x00, 0x00, 0x00, + # 46: . + 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, + # 47: / + 0x06, 0x0C, 0x18, 0x30, 0x60, 0xC0, 0x80, 0x00, + # 48: 0 + 0x7C, 0xC6, 0xCE, 0xDE, 0xF6, 0xE6, 0x7C, 0x00, + # 49: 1 + 0x18, 0x38, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, + # 50: 2 + 0x7C, 0xC6, 0x06, 0x1C, 0x30, 0x66, 0xFE, 0x00, + # 51: 3 + 0x7C, 0xC6, 0x06, 0x3C, 0x06, 0xC6, 0x7C, 0x00, + # 52: 4 + 0x0C, 0x1C, 0x3C, 0x6C, 0xFE, 0x0C, 0x0C, 0x00, + # 53: 5 + 0xFE, 0xC0, 0xFC, 0x06, 0x06, 0xC6, 0x7C, 0x00, + # 54: 6 + 0x38, 0x60, 0xC0, 0xFC, 0xC6, 0xC6, 0x7C, 0x00, + # 55: 7 + 0xFE, 0xC6, 0x0C, 0x18, 0x30, 0x30, 0x30, 0x00, + # 56: 8 + 0x7C, 0xC6, 0xC6, 0x7C, 0xC6, 0xC6, 0x7C, 0x00, + # 57: 9 + 0x7C, 0xC6, 0xC6, 0x7E, 0x06, 0x0C, 0x78, 0x00, + # 58: : + 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x00, 0x00, + # 59: ; + 0x00, 0x18, 0x18, 0x00, 0x18, 0x18, 0x30, 0x00, + # 60: < + 0x0C, 0x18, 0x30, 0x60, 0x30, 0x18, 0x0C, 0x00, + # 61: = + 0x00, 0x00, 0x7E, 0x00, 0x7E, 0x00, 0x00, 0x00, + # 62: > + 0x30, 0x18, 0x0C, 0x06, 0x0C, 0x18, 0x30, 0x00, + # 63: ? + 0x7C, 0xC6, 0x0C, 0x18, 0x18, 0x00, 0x18, 0x00, + # 64: @ + 0x7C, 0xC6, 0xDE, 0xDE, 0xDE, 0xC0, 0x7C, 0x00, + # 65: A + 0x38, 0x6C, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0x00, + # 66: B + 0xFC, 0xC6, 0xC6, 0xFC, 0xC6, 0xC6, 0xFC, 0x00, + # 67: C + 0x3C, 0x66, 0xC0, 0xC0, 0xC0, 0x66, 0x3C, 0x00, + # 68: D + 0xF8, 0xCC, 0xC6, 0xC6, 0xC6, 0xCC, 0xF8, 0x00, + # 69: E + 0xFE, 0xC0, 0xC0, 0xFC, 0xC0, 0xC0, 0xFE, 0x00, + # 70: F + 0xFE, 0xC0, 0xC0, 0xFC, 0xC0, 0xC0, 0xC0, 0x00, + # 71: G + 0x3C, 0x66, 0xC0, 0xCE, 0xC6, 0x66, 0x3E, 0x00, + # 72: H + 0xC6, 0xC6, 0xC6, 0xFE, 0xC6, 0xC6, 0xC6, 0x00, + # 73: I + 0x7E, 0x18, 0x18, 0x18, 0x18, 0x18, 0x7E, 0x00, + # 74: J + 0x06, 0x06, 0x06, 0x06, 0xC6, 0xC6, 0x7C, 0x00, + # 75: K + 0xC6, 0xCC, 0xD8, 0xF0, 0xD8, 0xCC, 0xC6, 0x00, + # 76: L + 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFE, 0x00, + # 77: M + 0xC6, 0xEE, 0xFE, 0xFE, 0xD6, 0xC6, 0xC6, 0x00, + # 78: N + 0xC6, 0xE6, 0xF6, 0xDE, 0xCE, 0xC6, 0xC6, 0x00, + # 79: O + 0x7C, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, + # 80: P + 0xFC, 0xC6, 0xC6, 0xFC, 0xC0, 0xC0, 0xC0, 0x00, + # 81: Q + 0x7C, 0xC6, 0xC6, 0xC6, 0xD6, 0xDE, 0x7C, 0x06, + # 82: R + 0xFC, 0xC6, 0xC6, 0xFC, 0xD8, 0xCC, 0xC6, 0x00, + # 83: S + 0x7C, 0xC6, 0xC0, 0x7C, 0x06, 0xC6, 0x7C, 0x00, + # 84: T + 0xFE, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, + # 85: U + 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, + # 86: V + 0xC6, 0xC6, 0xC6, 0xC6, 0x6C, 0x38, 0x10, 0x00, + # 87: W + 0xC6, 0xC6, 0xD6, 0xFE, 0xEE, 0xC6, 0x82, 0x00, + # 88: X + 0xC6, 0xC6, 0x6C, 0x38, 0x6C, 0xC6, 0xC6, 0x00, + # 89: Y + 0xC6, 0xC6, 0x6C, 0x38, 0x18, 0x18, 0x18, 0x00, + # 90: Z + 0xFE, 0x06, 0x0C, 0x18, 0x30, 0x60, 0xFE, 0x00, + # 91: [ + 0x3C, 0x30, 0x30, 0x30, 0x30, 0x30, 0x3C, 0x00, + # 92: backslash + 0xC0, 0x60, 0x30, 0x18, 0x0C, 0x06, 0x02, 0x00, + # 93: ] + 0x3C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x3C, 0x00, + # 94: ^ + 0x10, 0x38, 0x6C, 0xC6, 0x00, 0x00, 0x00, 0x00, + # 95: _ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, + # 96: ` + 0x18, 0x18, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, + # 97: a + 0x00, 0x00, 0x7C, 0x06, 0x7E, 0xC6, 0x7E, 0x00, + # 98: b + 0xC0, 0xC0, 0xFC, 0xC6, 0xC6, 0xC6, 0xFC, 0x00, + # 99: c + 0x00, 0x00, 0x7C, 0xC6, 0xC0, 0xC6, 0x7C, 0x00, + # 100: d + 0x06, 0x06, 0x7E, 0xC6, 0xC6, 0xC6, 0x7E, 0x00, + # 101: e + 0x00, 0x00, 0x7C, 0xC6, 0xFE, 0xC0, 0x7C, 0x00, + # 102: f + 0x1C, 0x36, 0x30, 0x7C, 0x30, 0x30, 0x30, 0x00, + # 103: g + 0x00, 0x00, 0x7E, 0xC6, 0xC6, 0x7E, 0x06, 0x7C, + # 104: h + 0xC0, 0xC0, 0xFC, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, + # 105: i + 0x18, 0x00, 0x38, 0x18, 0x18, 0x18, 0x3C, 0x00, + # 106: j + 0x06, 0x00, 0x06, 0x06, 0x06, 0x06, 0xC6, 0x7C, + # 107: k + 0xC0, 0xC0, 0xC6, 0xCC, 0xF8, 0xCC, 0xC6, 0x00, + # 108: l + 0x38, 0x18, 0x18, 0x18, 0x18, 0x18, 0x3C, 0x00, + # 109: m + 0x00, 0x00, 0xEC, 0xFE, 0xD6, 0xD6, 0xC6, 0x00, + # 110: n + 0x00, 0x00, 0xFC, 0xC6, 0xC6, 0xC6, 0xC6, 0x00, + # 111: o + 0x00, 0x00, 0x7C, 0xC6, 0xC6, 0xC6, 0x7C, 0x00, + # 112: p + 0x00, 0x00, 0xFC, 0xC6, 0xC6, 0xFC, 0xC0, 0xC0, + # 113: q + 0x00, 0x00, 0x7E, 0xC6, 0xC6, 0x7E, 0x06, 0x06, + # 114: r + 0x00, 0x00, 0xDC, 0xE6, 0xC0, 0xC0, 0xC0, 0x00, + # 115: s + 0x00, 0x00, 0x7E, 0xC0, 0x7C, 0x06, 0xFC, 0x00, + # 116: t + 0x30, 0x30, 0x7C, 0x30, 0x30, 0x36, 0x1C, 0x00, + # 117: u + 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0xC6, 0x7E, 0x00, + # 118: v + 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0x6C, 0x38, 0x00, + # 119: w + 0x00, 0x00, 0xC6, 0xD6, 0xFE, 0xEE, 0xC6, 0x00, + # 120: x + 0x00, 0x00, 0xC6, 0x6C, 0x38, 0x6C, 0xC6, 0x00, + # 121: y + 0x00, 0x00, 0xC6, 0xC6, 0xC6, 0x7E, 0x06, 0x7C, + # 122: z + 0x00, 0x00, 0xFE, 0x0C, 0x38, 0x60, 0xFE, 0x00, + # 123: { + 0x0E, 0x18, 0x18, 0x70, 0x18, 0x18, 0x0E, 0x00, + # 124: | + 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, + # 125: } + 0x70, 0x18, 0x18, 0x0E, 0x18, 0x18, 0x70, 0x00, + # 126: ~ + 0x76, 0xDC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, +]) + +assert len(FONT) == 760, f"Expected 760 bytes, got {len(FONT)}" + +outpath = sys.argv[1] if len(sys.argv) > 1 else "build/font.bin" +os.makedirs(os.path.dirname(outpath) or ".", exist_ok=True) +with open(outpath, "wb") as f: + f.write(FONT) +print(f"Generated {len(FONT)} byte font -> {outpath}") diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/gsu_demo.gsu b/roms/snes-coprocessor-tests/hirom-gsu-test/gsu_demo.gsu new file mode 100644 index 00000000..55c8204e --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/gsu_demo.gsu @@ -0,0 +1,170 @@ +// GSU-2 Rainbow Tile Demo — Direct RAM write of 4bpp tile data +// +// Writes a pre-computed 8x8 diagonal rainbow gradient tile to Game Pak RAM +// using the GSU's STW (store word) instruction. The 32-byte tile encodes a +// diagonal color sweep through 15 rainbow colors in SNES 4bpp OBJ format. +// +// Pattern: pixel color = X + Y + 1 (colors 1-15 diagonal gradient) +// Row 0: 1 2 3 4 5 6 7 8 +// Row 1: 2 3 4 5 6 7 8 9 +// Row 7: 8 9 10 11 12 13 14 15 +// +// Executes from Game Pak RAM at $70:0100 +// Output: 32 bytes of 4bpp tile at screen base (SCBR * $400) + +arch snes.gsu +base $000100 + + cache // enable code cache + + iwt r1, #$0C00 // R1 = dest: screen base (SCBR=3 -> $0C00) + iwt r8, #2 // R8 = 2 (address step for word writes) + + // --- Bytes 0-15: BP0/BP1 interleaved for rows 0-7 --- + // Row 0 (colors 1,2,3,4,5,6,7,8): BP0=$AA BP1=$66 + iwt r0, #$66AA + stw (r1) + with r1 + add r8 + // Row 1 (colors 2,3,4,5,6,7,8,9): BP0=$55 BP1=$CC + iwt r0, #$CC55 + stw (r1) + with r1 + add r8 + // Row 2 (colors 3,4,5,6,7,8,9,10): BP0=$AA BP1=$99 + iwt r0, #$99AA + stw (r1) + with r1 + add r8 + // Row 3 (colors 4,5,6,7,8,9,10,11): BP0=$55 BP1=$33 + iwt r0, #$3355 + stw (r1) + with r1 + add r8 + // Row 4 (colors 5,6,7,8,9,10,11,12): BP0=$AA BP1=$66 + iwt r0, #$66AA + stw (r1) + with r1 + add r8 + // Row 5 (colors 6,7,8,9,10,11,12,13): BP0=$55 BP1=$CC + iwt r0, #$CC55 + stw (r1) + with r1 + add r8 + // Row 6 (colors 7,8,9,10,11,12,13,14): BP0=$AA BP1=$99 + iwt r0, #$99AA + stw (r1) + with r1 + add r8 + // Row 7 (colors 8,9,10,11,12,13,14,15): BP0=$55 BP1=$33 + iwt r0, #$3355 + stw (r1) + with r1 + add r8 + + // --- Bytes 16-31: BP2/BP3 interleaved for rows 0-7 --- + // Row 0: BP2=$1E BP3=$01 + iwt r0, #$011E + stw (r1) + with r1 + add r8 + // Row 1: BP2=$3C BP3=$03 + iwt r0, #$033C + stw (r1) + with r1 + add r8 + // Row 2: BP2=$78 BP3=$07 + iwt r0, #$0778 + stw (r1) + with r1 + add r8 + // Row 3: BP2=$F0 BP3=$0F + iwt r0, #$0FF0 + stw (r1) + with r1 + add r8 + // Row 4: BP2=$E1 BP3=$1F + iwt r0, #$1FE1 + stw (r1) + with r1 + add r8 + // Row 5: BP2=$C3 BP3=$3F + iwt r0, #$3FC3 + stw (r1) + with r1 + add r8 + // Row 6: BP2=$87 BP3=$7F + iwt r0, #$7F87 + stw (r1) + with r1 + add r8 + // Row 7: BP2=$0F BP3=$FF + iwt r0, #$FF0F + stw (r1) + + stop + nop + + +// ===================================================================== +// DISABLED: PLOT-based 16x16 demo +// +// This version uses the GSU's PLOT/COLOR pipeline to render a 16x16 +// diagonal rainbow gradient. It demonstrates per-pixel color control +// and multi-tile OBJ-mode output — the same pipeline used for 3D +// rendering in Star Fox and Doom. +// +// KNOWN BUG (Mesen2): The pixel cache does not flush intermediate tile +// rows to RAM when the Y coordinate changes between PLOT calls. Only +// the final row (flushed by STOP) survives. This produces a single +// rainbow line instead of a 16x16 square. +// +// Additionally, per-pixel COLOR changes within a single 8-pixel cache +// line produce doubled color values (1,3,5,7... instead of 1,2,3,4...). +// +// Both bugs are documented in the project issue tracker. The STW-based +// demo above works around these by writing tile data directly to RAM. +// +// To test: replace the STW block above with this code, change the +// sprite to 16x16 in SetupOBJBase, and DMA 576 bytes instead of 32. +// ===================================================================== +// +// cache +// +// ibt r3, #15 // R3 = 15 (mod constant) +// ibt r4, #0 // R4 = Y counter +// ibt r5, #16 // R5 = 16 (Y limit) +// +//row_loop: +// moves r2, r4 // R2 = Y +// ibt r1, #0 // R1 = X = 0 (PLOT auto-increments) +// ibt r7, #0 // R7 = X counter for color calc +// ibt r12, #16 // 16 pixels per row +// moves r13, r15 // R13 = loop target +// +//pixel_loop: +// // color = ((X + Y) mod 15) + 1 +// from r7 +// add r4 // R0 = X + Y (0..30) +//sub_loop: +// from r0 +// cmp r3 // compare with 15 +// blt no_sub +// from r0 +// sub r3 // R0 -= 15 +// bra sub_loop +//no_sub: +// inc r0 // R0 = (X+Y)%15 + 1 +// color // COLR = R0 +// plot // plot at (R1, R2), R1++ +// inc r7 +// loop +// +// // Next row +// inc r4 +// from r4 +// cmp r5 +// bne row_loop +// +// stop +// nop diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/hirom_gsu_test.bml b/roms/snes-coprocessor-tests/hirom-gsu-test/hirom_gsu_test.bml new file mode 100644 index 00000000..c7908e47 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/hirom_gsu_test.bml @@ -0,0 +1,26 @@ +game + sha256: 0000000000000000000000000000000000000000000000000000000000000000 + label: HiROM GSU MSU-1 Test + name: HiROM GSU MSU-1 Test + title: HIROM GSU MSU1 TEST + region: NTSC + revision: 1.0 + board: HIROM + memory + type: ROM + size: 0x400000 + content: Program + memory + type: RAM + size: 0x2000 + content: Save + oscillator + frequency: 21440000 + processor architecture=GSU + map address=00-3f,80-bf:3000-34ff + memory type=ROM content=Program + map address=00-3f,80-bf:8000-ffff + map address=c0-ff:0000-ffff + memory type=RAM content=Save + map address=00-3f,80-bf:6000-7fff size=0x2000 + map address=70-71,f0-f1:0000-ffff diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/inject_signatures.py b/roms/snes-coprocessor-tests/hirom-gsu-test/inject_signatures.py new file mode 100644 index 00000000..969d21af --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/inject_signatures.py @@ -0,0 +1,14 @@ +#!/usr/bin/env python3 +"""Inject per-bank signatures into the ROM for bank mapping verification. + +Writes the bank number (0-63) at offset $FFA0 in each 64KB bank. +The test ROM reads these back at runtime to verify HiROM bank mapping. +""" +import sys + +rom = bytearray(open(sys.argv[1], 'rb').read()) +num_banks = len(rom) // 0x10000 +for bank in range(num_banks): + rom[bank * 0x10000 + 0xFFA0] = bank +open(sys.argv[1], 'wb').write(rom) +print(f"Injected {num_banks} bank signatures into {sys.argv[1]}") diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/linkfile.lnk b/roms/snes-coprocessor-tests/hirom-gsu-test/linkfile.lnk new file mode 100644 index 00000000..1cb4afd6 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/linkfile.lnk @@ -0,0 +1,2 @@ +[objects] +build/test_rom.o diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/makefile b/roms/snes-coprocessor-tests/hirom-gsu-test/makefile new file mode 100644 index 00000000..bccb3015 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/makefile @@ -0,0 +1,44 @@ +ASM := ./tools/wla-dx/wla-65816 +LINK := ./tools/wla-dx/wlalink +BASS := ./tools/bass/bass.exe +PYTHON := python3 + +ROM := build/HiRomGsuTest.sfc +MSU := build/HiRomGsuTest.msu +OBJ := build/test_rom.o +GSU_BIN := build/pixel_test.bin +GSU_DEMO := build/gsu_demo.bin +GSU_SCALER := build/sprite_scaler.bin +FONT := build/font.bin + +.PHONY: all clean + +all: $(ROM) $(MSU) + +build: + mkdir -p build + +$(FONT): gen_font.py | build + $(PYTHON) gen_font.py $@ + +$(GSU_BIN): pixel_test.gsu | build + $(BASS) -strict -o $@ $< + +$(GSU_DEMO): gsu_demo.gsu | build + $(BASS) -strict -o $@ $< + +$(GSU_SCALER): sprite_scaler.gsu | build + $(BASS) -strict -o $@ $< + +$(OBJ): test_rom.65816 test_rom.h $(GSU_BIN) $(GSU_DEMO) $(GSU_SCALER) $(FONT) | build + $(ASM) -o $< $@ + +$(ROM): $(OBJ) linkfile.lnk inject_signatures.py + $(LINK) -dsr linkfile.lnk $@ + $(PYTHON) inject_signatures.py $@ + +$(MSU): | build + $(PYTHON) -c "open('$@','wb').write(bytes(4096))" + +clean: + rm -rf build diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/mesen_screenshot.png b/roms/snes-coprocessor-tests/hirom-gsu-test/mesen_screenshot.png new file mode 100644 index 00000000..6951f498 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/mesen_screenshot.png differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/pixel_test.gsu b/roms/snes-coprocessor-tests/hirom-gsu-test/pixel_test.gsu new file mode 100644 index 00000000..7618122a --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/pixel_test.gsu @@ -0,0 +1,51 @@ +// GSU-2 Pixel Plot Test +// Plots an 8x8 colored square to Game Pak RAM in 4bpp OBJ format. +// Proves GSU -> pixel cache -> RAM -> (DMA) -> VRAM -> OAM pipeline works. +// +// Executes from Game Pak RAM at $70:0200 +// Output: 32 bytes of 4bpp tile data at screen base (SCBR * $400) +// +// NOTE: Every branch/loop instruction has a NOP delay slot. +// The SuperFX pipeline executes the prefetched byte after a branch. +// +// Assembled by bass v18: tools/bass/bass.exe -strict -o build/gsu_pixel_test.bin pixel_test.gsu + +arch snes.gsu +base $000200 + + cache // enable instruction cache (1 cycle/op in cache) + + // Set plot color to 5 + ibt r0, #5 + color // COLR = 5 + + // Initialize row counter + ibt r4, #0 // R4 = Y row counter + ibt r5, #8 // R5 = 8 (comparison constant) + +row_loop: + // R2 = Y = current row + moves r2, r4 + + // R1 = X start = 0 (PLOT auto-increments R1) + ibt r1, #0 + + // Set up pixel loop: 8 pixels per row + ibt r12, #8 // R12 = loop counter + moves r13, r15 // R13 = address of next instruction (loop target) + +pixel_loop: + plot // plot pixel at (R1, R2) with color COLR, R1++ + loop // R12--, branch to R13 if R12 != 0 + nop // delay slot + + // Next row + inc r4 // R4++ + from r4 + cmp r5 // compare R4 with 8 + bne row_loop // branch if not equal + nop // delay slot + + // Flush pixel cache and halt + stop + nop diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/sprite_scaler.gsu b/roms/snes-coprocessor-tests/hirom-gsu-test/sprite_scaler.gsu new file mode 100644 index 00000000..41db6968 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/sprite_scaler.gsu @@ -0,0 +1,402 @@ +// GSU-2 STW-based Sprite Scaler +// Scales 4bpp source tiles to destination dimensions via fixed-point stepping. +// Uses LDB/STB for output bitplane writes (no PLOT/pixel cache). +// +// NOTE: Every branch instruction (beq/bne/jmp rN) has a NOP delay slot. +// The SuperFX pipeline executes the prefetched byte after a branch. +// +// Param block $0000-$000B: +// $00: src_w $01: src_h $02: dst_w $03: dst_h +// $04: src_data (word) $06: tiles_w $07: tiles_h +// $08: x_step (word) $0A: y_step (word) +// Bitmask LUT at $0060: {$80,$40,$20,$10,$08,$04,$02,$01} +// Output at $0C00 (SCBR=3), OBJ 16-tile-wide format. +// +// Register plan: +// R3=dst_w R4=dst_h R5=x_step R6=y_step R8=tiles_per_row R10=src_data +// R14=y_accum R2=out_y R1=out_x R11=pixel_color R7,R12=scratch +// Scratch RAM: +// $70: src row byte base (word) $72: src bitmask (byte) +// $74: out row base (word) $76: x_accum (word) +// $78: x_loop addr (word) $7A: y_loop addr (word) + +arch snes.gsu +base $000100 + + cache + + // ---- Load parameters ---- + ibt r9, #2 + ldb (r9) + to r3 + from r0 + add #0 // R3 = dst_width + + ibt r9, #3 + ldb (r9) + to r4 + from r0 + add #0 // R4 = dst_height + + iwt r9, #$0008 + ldw (r9) + to r5 + from r0 + add #0 // R5 = x_step + + iwt r9, #$000A + ldw (r9) + to r6 + from r0 + add #0 // R6 = y_step + + ibt r9, #6 + ldb (r9) + to r8 + from r0 + add #0 // R8 = tiles_per_row + + iwt r9, #$0004 + ldw (r9) + to r10 + from r0 + add #0 // R10 = src_data + + ibt r14, #0 // y_accum = 0 + ibt r2, #0 // out_y = 0 + + // Store loop addresses for jmp rN + iwt r0, #y_loop + iwt r9, #$007A + stw (r9) // $7A = y_loop addr + + // ======== Y LOOP ======== +y_loop: + // src_y = y_accum >> 8 + from r14 + hib // R0 = src_y + to r7 + from r0 + add #0 // R7 = src_y + + // tile_row = src_y >> 3 + from r7 + lsr + lsr + lsr // R0 = tile_row + + // tile_row * tiles_per_row * 32 + mult r8 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 // R0 = tile_row * tiles_per_row * 32 + + add r10 // R0 += src_data base + + // + y_byte_off = (src_y & 7) * 2 + to r12 + from r0 + add #0 // R12 = row_tile_base + from r7 + and #7 + from r0 + add r0 // R0 = y_byte_off + add r12 // R0 = src row byte base + iwt r9, #$0070 + stw (r9) // $70 = src row byte base + + // Compute output row base + from r2 + lsr + lsr + lsr // R0 = out_tile_row + from r0 + add r0 + swap // R0 = out_tile_row * 512 + iwt r12, #$0C00 + add r12 // R0 += screen base + to r12 + from r0 + add #0 // R12 = partial + from r2 + and #7 + from r0 + add r0 // R0 = (out_y & 7) * 2 + add r12 // R0 = out_row_base + iwt r9, #$0074 + stw (r9) // $74 = out_row_base + + // Init x loop + ibt r0, #0 + iwt r9, #$0076 + stw (r9) // $76 = x_accum = 0 + ibt r1, #0 // out_x = 0 + + // Store x_loop address + iwt r0, #x_loop + iwt r9, #$0078 + stw (r9) // $78 = x_loop addr + + // ======== X LOOP ======== +x_loop: + // src_x = x_accum >> 8 + iwt r9, #$0076 + ldw (r9) // R0 = x_accum + hib // R0 = src_x + to r7 + from r0 + add #0 // R7 = src_x + + // src_bitmask = LUT[src_x & 7] + from r7 + and #7 + iwt r12, #$0060 + add r12 + to r9 + from r0 + add #0 + ldb (r9) // R0 = src_bitmask + iwt r9, #$0072 + stb (r9) // $72 = src_bitmask + + // tile_col * 32 + from r7 + lsr + lsr + lsr // R0 = tile_col + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 // R0 = tile_col * 32 + + // src_addr = src_row_base + tile_col * 32 + iwt r9, #$0070 + to r12 + ldw (r9) + add r12 // R0 = src byte addr + to r7 + from r0 + add #0 // R7 = src_addr + + // R12 = src_bitmask + iwt r9, #$0072 + ldb (r9) + to r12 + from r0 + add #0 // R12 = src_bitmask + + // Extract 4 bitplanes -> R11 + ibt r11, #0 + + // BP0 (+0) + to r9 + from r7 + add #0 // R9 = src_addr + ldb (r9) + and r12 + beq bp0z + nop // delay slot + ibt r0, #1 +bp0z: + with r11 + add r0 // R11 += bit0 + + // BP1 (+1) + from r7 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + and r12 + beq bp1z + nop // delay slot + ibt r0, #2 +bp1z: + with r11 + add r0 // R11 += bit1 + + // BP2 (+16) + from r7 + add #15 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + and r12 + beq bp2z + nop // delay slot + ibt r0, #4 +bp2z: + with r11 + add r0 // R11 += bit2 + + // BP3 (+17) + from r9 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + and r12 + beq bp3z + nop // delay slot + ibt r0, #8 +bp3z: + with r11 + add r0 // R11 += bit3 + + // Skip if transparent + from r11 + add #0 + beq skip_pixel + nop // delay slot + + // ---- Write pixel to output ---- + // out_bitmask = LUT[out_x & 7] + from r1 + and #7 + iwt r12, #$0060 + add r12 + to r9 + from r0 + add #0 + ldb (r9) + to r7 + from r0 + add #0 // R7 = out_bitmask + + // out_byte_addr = out_row_base + (out_x >> 3) * 32 + from r1 + lsr + lsr + lsr // R0 = out_tile_col + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 + from r0 + add r0 // R0 = out_tile_col * 32 + iwt r9, #$0074 + to r12 + ldw (r9) + add r12 // R0 = out_byte_addr + to r12 + from r0 + add #0 // R12 = out_byte_addr + + // BP0 (color & 1) + from r11 + and #1 + beq sk0 + nop // delay slot + to r9 + from r12 + add #0 + ldb (r9) + or r7 + stb (r9) +sk0: + // BP1 (color & 2) + from r11 + and #2 + beq sk1 + nop // delay slot + from r12 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + or r7 + stb (r9) +sk1: + // BP2 (color & 4) + from r11 + and #4 + beq sk2 + nop // delay slot + from r12 + add #15 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + or r7 + stb (r9) +sk2: + // BP3 (color & 8) + from r11 + and #8 + beq sk3 + nop // delay slot + from r12 + add #15 + add #1 + add #1 + to r9 + from r0 + add #0 + ldb (r9) + or r7 + stb (r9) +sk3: + +skip_pixel: + // x_accum += x_step + iwt r9, #$0076 + ldw (r9) + add r5 + stw (r9) + + // out_x++; if out_x < dst_width, loop + inc r1 + from r1 + cmp r3 + beq x_done + nop // delay slot + iwt r9, #$0078 + to r13 + ldw (r9) // R13 = x_loop addr + jmp r13 + nop // delay slot +x_done: + + // y_accum += y_step + with r14 + add r6 + + // out_y++; if out_y < dst_height, loop + inc r2 + from r2 + cmp r4 + beq y_done + nop // delay slot + iwt r9, #$007A + to r13 + ldw (r9) // R13 = y_loop addr + jmp r13 + nop // delay slot +y_done: + + stop + nop diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.65816 b/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.65816 new file mode 100644 index 00000000..2d42f6ab --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.65816 @@ -0,0 +1,1289 @@ +; test_rom.65816 — HiROM+GSU+MSU-1 Standalone Test ROM v1.1 +; +; 4MB HiROM (64 banks) — verifies full bank mapping, WRAM, GSU-2, MSU-1. +; No dependencies on main project OOP/SCUMM engine or game assets. +; +; Build: wsl -e bash -lc "cd .../SNES-HiRomGsuTest && make" +; Output: build/HiRomGsuTest.sfc (4 MB) + +.include "test_rom.h" + +;============================================================ +; Direct Page Variables ($7E:0000) +;============================================================ +.define palByte $02 ; current palette<<2 for tilemap high byte +.define gsuDetected $03 ; 1 if GSU VCR=$04 +.define msuDetected $04 ; 1 if MSU-1 ID matches +.define gsuVcrVal $05 ; raw VCR register value +.define msuStatVal $06 ; raw MSU_STATUS value +.define bankPassed $07 ; count of banks that passed (0-64) +.define sramStrPtr $08 ; 16-bit pointer to SRAM size string +.define gsuClsrVal $0A ; raw CLSR register value +.define bankCount $13 ; scratch: bank loop counter + +;============================================================ +; Palette index constants (palette_num << 2 for tilemap) +;============================================================ +.define PAL_WHITE $00 +.define PAL_GREEN $04 +.define PAL_RED $08 +.define PAL_YELLOW $0C +.define PAL_CYAN $10 + +;============================================================ +; Bank 0 — All code and data at $8000+ +;============================================================ +.bank 0 slot 0 +.org $8000 +.section "main" force + +;------------------------------------------------------------ +; RESET entry point +;------------------------------------------------------------ +Reset: + sei + clc + xce ; switch to native mode + .ACCU 16 + .INDEX 16 + phk + plb ; DBR = PBR = $00 + rep #$30 ; 16-bit A, X, Y + ldx #$01FF + txs ; init stack at $01FF + lda #$0000 + tcd ; direct page at $0000 + + sep #$20 ; 8-bit A + .ACCU 8 + lda #$8F + sta $2100 ; INIDSP: force blank + brightness 15 + stz $4200 ; NMITIMEN: disable NMI/IRQ/auto joyread + stz $420C ; HDMAEN: disable HDMA + lda #$01 + sta $420D ; MEMSEL: FastROM enable + + ; Zero direct page variables + ldx #$0000 +_clearDP: + stz $00,x + inx + cpx #$0080 + bne _clearDP + + ; Initialize default SRAM string to "--" + rep #$10 + .INDEX 16 + ldx #str_dashes + stx sramStrPtr + + sep #$10 + .INDEX 8 + + jsr ClearVRAM + jsr UploadFont + jsr InitPPU + jsr SetupPalettes + + rep #$10 + .INDEX 16 + + ; ---- Display header ---- + rep #$20 + .ACCU 16 + lda #1*32+1 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_title + jsr PrintString + + rep #$20 + .ACCU 16 + lda #2*32+1 + sta $2116 + sep #$20 + .ACCU 8 + ldx #str_separator + jsr PrintString + + ;============================================================ + ; Test 1: HiROM Mapping + ; Read RESET vector from $C0:FFFC and $00:FFFC, compare + ;============================================================ + rep #$20 + .ACCU 16 + lda #4*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_hirom + jsr PrintString + + rep #$20 + .ACCU 16 + lda.l $C0FFFC + cmp.l $00FFFC + sep #$20 + .ACCU 8 + beq _t1_pass + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString + bra _t1_done +_t1_pass: + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString +_t1_done: + + ;============================================================ + ; Test 2: ROM Banks + ; Verify per-bank signatures at offset $FFA0 in all 64 banks. + ; inject_signatures.py writes bank_number at $FFA0 in each bank. + ; We read via indirect long from ($C0+N):$FFA0 and compare. + ;============================================================ + rep #$20 + .ACCU 16 + lda #5*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_banks + jsr PrintString + + ; Set up indirect long pointer: [$10] = bank:$FFA0 + lda #$A0 + sta $10 ; pointer low byte + lda #$FF + sta $11 ; pointer high byte + stz bankPassed + stz bankCount + +_bankLoop: + lda bankCount + clc + adc #$C0 + sta $12 ; pointer bank = $C0 + N + ; Skip banks $F0-$F1 — SRAM mirrors overlap ROM at these addresses + cmp #$F0 + beq _bankNext + cmp #$F1 + beq _bankNext + lda [$10] ; read from (bank+$C0):$FFA0 + cmp bankCount ; compare with expected bank number + bne _bankNext + inc bankPassed +_bankNext: + inc bankCount + lda bankCount + cmp #64 + bne _bankLoop + + ; Display: "NN/62 PASS" or "NN/62 FAIL" + ; (62 = 64 banks minus 2 SRAM-overlap banks at $F0-$F1) + lda #PAL_CYAN + sta palByte + lda bankPassed + jsr PrintDec8 ; print pass count + stz palByte ; white for "/62 " + lda #$2F ; '/' + sta $2118 + stz $2119 + lda #$36 ; '6' + sta $2118 + stz $2119 + lda #$32 ; '2' + sta $2118 + stz $2119 + lda #$20 ; space + sta $2118 + stz $2119 + lda bankPassed + cmp #62 + beq _t2_pass + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString + bra _t2_done +_t2_pass: + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString +_t2_done: + + ;============================================================ + ; Test 3: WRAM Read/Write + ;============================================================ + rep #$20 + .ACCU 16 + lda #6*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_wram + jsr PrintString + + rep #$20 + .ACCU 16 + lda #$A55A + sta.l $7E2000 + lda.l $7E2000 + cmp #$A55A + sep #$20 + .ACCU 8 + beq _t3_pass + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString + bra _t3_done +_t3_pass: + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString +_t3_done: + + ;============================================================ + ; Test 4: GSU-2 VCR + ;============================================================ + rep #$20 + .ACCU 16 + lda #7*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_gsu_vcr + jsr PrintString + + lda.l $303B + sta gsuVcrVal + lda #PAL_CYAN + sta palByte + lda #$24 + sta $2118 + lda palByte + sta $2119 + lda gsuVcrVal + jsr PrintHex8 + lda #$20 + sta $2118 + stz $2119 + + lda gsuVcrVal + cmp #$04 + beq _t4_pass + stz gsuDetected + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString + bra _t4_done +_t4_pass: + lda #$01 + sta gsuDetected + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString +_t4_done: + + ;============================================================ + ; Test 5: GSU SRAM R/W + ;============================================================ + rep #$20 + .ACCU 16 + lda #8*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_gsu_sram + jsr PrintString + + lda gsuDetected + bne _t5_run + lda #PAL_YELLOW + sta palByte + ldx #str_skip + jsr PrintString + bra _t5_done + +_t5_run: + rep #$20 + .ACCU 16 + lda #$1234 + sta.l $700000 + lda.l $700000 + cmp #$1234 + bne _t5_fail + lda #$5678 + sta.l $700002 + lda.l $700002 + cmp #$5678 + bne _t5_fail + sep #$20 + .ACCU 8 + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString + bra _t5_done +_t5_fail: + sep #$20 + .ACCU 8 + stz gsuDetected + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString +_t5_done: + + ;============================================================ + ; Test 6: GSU Execute + ;============================================================ + rep #$20 + .ACCU 16 + lda #9*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_gsu_exec + jsr PrintString + + lda gsuDetected + bne _t6_run + lda #PAL_YELLOW + sta palByte + ldx #str_skip + jsr PrintString + jmp _t6_done + +_t6_run: + jsr RunGSUTest + bcs _t6_pass + lda #PAL_RED + sta palByte + ldx #str_fail + jsr PrintString + bra _t6_done +_t6_pass: + lda #PAL_GREEN + sta palByte + ldx #str_pass + jsr PrintString +_t6_done: + + ;============================================================ + ; Test 7: Game Pak RAM Size + ; Detect SRAM by probing for address wraparound + ;============================================================ + rep #$20 + .ACCU 16 + lda #10*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_gpkram + jsr PrintString + + lda gsuDetected + bne _t7_run + lda #PAL_YELLOW + sta palByte + ldx #str_skip + jsr PrintString + ldx #str_dashes + stx sramStrPtr + jmp _t7_done + +_t7_run: + ; Write sentinel, probe each boundary for wraparound + ; 2KB + lda #$55 + sta.l $700000 + lda #$AA + sta.l $700800 + lda.l $700000 + cmp #$AA + bne + + ldx #str_2kb + bra _t7_print ++ + ; 4KB + lda #$55 + sta.l $700000 + lda #$AA + sta.l $701000 + lda.l $700000 + cmp #$AA + bne + + ldx #str_4kb + bra _t7_print ++ + ; 8KB + lda #$55 + sta.l $700000 + lda #$AA + sta.l $702000 + lda.l $700000 + cmp #$AA + bne + + ldx #str_8kb + bra _t7_print ++ + ; 16KB + lda #$55 + sta.l $700000 + lda #$AA + sta.l $704000 + lda.l $700000 + cmp #$AA + bne + + ldx #str_16kb + bra _t7_print ++ + ; 32KB + lda #$55 + sta.l $700000 + lda #$AA + sta.l $708000 + lda.l $700000 + cmp #$AA + bne + + ldx #str_32kb + bra _t7_print ++ + ; No wrap at 32KB — report 64KB+ + ldx #str_64kbp + +_t7_print: + stx sramStrPtr + lda #PAL_CYAN + sta palByte + jsr PrintString + + ; Clean up SRAM + lda #$00 + sta.l $700000 +_t7_done: + + ;============================================================ + ; Test 8: MSU-1 Detect + ;============================================================ + rep #$20 + .ACCU 16 + lda #11*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_msu_det + jsr PrintString + + lda.l $002002 + cmp #$53 + bne _t8_notfound + lda.l $002003 + cmp #$2D + bne _t8_notfound + lda.l $002004 + cmp #$4D + bne _t8_notfound + lda.l $002005 + cmp #$53 + bne _t8_notfound + lda.l $002006 + cmp #$55 + bne _t8_notfound + lda.l $002007 + cmp #$31 + bne _t8_notfound + + lda #$01 + sta msuDetected + lda #PAL_GREEN + sta palByte + ldx #str_found + jsr PrintString + bra _t8_done + +_t8_notfound: + stz msuDetected + lda #PAL_YELLOW + sta palByte + ldx #str_notfound + jsr PrintString +_t8_done: + + ;============================================================ + ; Test 9: MSU-1 Status + ;============================================================ + rep #$20 + .ACCU 16 + lda #12*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_t_msu_sts + jsr PrintString + + lda msuDetected + bne _t9_run + ldx #str_dashes + jsr PrintString + bra _t9_done + +_t9_run: + lda.l $002000 + sta msuStatVal + lda #PAL_CYAN + sta palByte + lda #$24 + sta $2118 + lda palByte + sta $2119 + lda msuStatVal + jsr PrintHex8 +_t9_done: + + ;============================================================ + ; Footer + ;============================================================ + ; Line 1: CPU and GSU clock speeds + rep #$20 + .ACCU 16 + lda #14*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_cpu_label + jsr PrintString + lda #PAL_CYAN + sta palByte + ldx #str_cpu_fast + jsr PrintString + stz palByte + ldx #str_gsu_label + jsr PrintString + lda gsuDetected + beq _footer_no_gsu + lda #PAL_CYAN + sta palByte + lda gsuClsrVal + and #$01 + bne _footer_gsu_fast + ldx #str_clk_10 + bra _footer_gsu_print +_footer_gsu_fast: + ldx #str_clk_21 +_footer_gsu_print: + jsr PrintString + bra _footer_rom +_footer_no_gsu: + ldx #str_dashes + jsr PrintString + +_footer_rom: + ; Line 2: ROM and SRAM sizes + rep #$20 + .ACCU 16 + lda #15*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_footer_rom + jsr PrintString + lda #PAL_CYAN + sta palByte + ldx sramStrPtr + jsr PrintString + + ; Line 3: Board + rep #$20 + .ACCU 16 + lda #16*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_board + jsr PrintString + + ; Line 4: Serial + rep #$20 + .ACCU 16 + lda #17*32+2 + sta $2116 + sep #$20 + .ACCU 8 + ldx #str_serial + jsr PrintString + + ;============================================================ + ; OBJ Sprite Demo — CPU tile upload first, GSU rainbow overlay if available + ;============================================================ + jsr SetupOBJBase + + lda gsuDetected + beq _skipGSUDemo + jsr RunGSUDemo +_skipGSUDemo: + + ; Print label on BG1 + rep #$20 + .ACCU 16 + lda #19*32+2 + sta $2116 + sep #$20 + .ACCU 8 + stz palByte + ldx #str_gsu_demo + jsr PrintString + + ;============================================================ + ; Enable display and halt + ;============================================================ + sep #$20 + .ACCU 8 + ; Reset OAM address to 0 before enabling display + stz $2102 + stz $2103 + lda #$0F + sta $2100 + lda #$80 + sta $4200 + +_halt: + wai + bra _halt + + +;============================================================ +; NMI handler — acknowledge and return +;============================================================ +NmiHandler: + sep #$20 + .ACCU 8 + lda $4210 ; acknowledge NMI + stz $2102 ; reset OAM address (prevents PPU OAM address drift) + stz $2103 + rti + +EmptyHandler: + rti + + +;============================================================ +; ClearVRAM — Zero all 64KB of VRAM using DMA +;============================================================ +ClearVRAM: + sep #$20 + .ACCU 8 + lda #$80 + sta $2115 + stz $2116 + stz $2117 + lda #$09 + sta $4300 + lda #$18 + sta $4301 + lda #<_zeroByte + sta $4302 + lda #>_zeroByte + sta $4303 + stz $4304 + stz $4305 + stz $4306 + lda #$01 + sta $420B + rts + +_zeroByte: + .db $00 + + +;============================================================ +; UploadFont — 1bpp to 2bpp, tiles 32-126 +;============================================================ +UploadFont: + sep #$20 + .ACCU 8 + rep #$10 + .INDEX 16 + lda #$80 + sta $2115 + lda #$00 + sta $2116 + lda #$11 + sta $2117 + ldx #$0000 +_fontLoop: + lda.w FontData,x + sta $2118 + sta $2119 + inx + cpx #760 + bne _fontLoop + rts + + +;============================================================ +; InitPPU — Mode 0, BG1 +;============================================================ +InitPPU: + sep #$20 + .ACCU 8 + stz $2105 + stz $2107 + lda #$01 + sta $210B + stz $210D + stz $210D + stz $210E + stz $210E + lda #$01 + sta $212C + stz $212D + rts + + +;============================================================ +; SetupPalettes +;============================================================ +SetupPalettes: + sep #$20 + .ACCU 8 + rep #$10 + .INDEX 16 + stz $2121 + ldx #$0000 +_palLoop: + lda.w PaletteData,x + sta $2122 + inx + cpx #40 + bne _palLoop + rts + + +;============================================================ +; PrintString — null-terminated string at X to VRAM tilemap +;============================================================ +PrintString: + sep #$20 + .ACCU 8 +_psLoop: + lda.w 0,x + beq _psDone + sta $2118 + lda palByte + sta $2119 + inx + bra _psLoop +_psDone: + rts + + +;============================================================ +; PrintHex8 — byte in A as 2 hex digits +;============================================================ +PrintHex8: + pha + lsr a + lsr a + lsr a + lsr a + jsr _hexDigit + pla + and #$0F + jsr _hexDigit + rts + +_hexDigit: + cmp #$0A + bcc _hexNum + adc #$36 + bra _hexPrint +_hexNum: + adc #$30 +_hexPrint: + sta $2118 + lda palByte + sta $2119 + rts + + +;============================================================ +; PrintDec8 — byte in A (0-99) as 2 decimal digits +;============================================================ +PrintDec8: + ldy #$FFFF +_decTens: + iny + sec + sbc #10 + bcs _decTens + adc #10 ; restore ones (carry was clear) + pha + tya ; A = tens digit + clc + adc #$30 + sta $2118 + lda palByte + sta $2119 + pla ; A = ones digit + clc + adc #$30 + sta $2118 + lda palByte + sta $2119 + rts + + +;============================================================ +; RunGSUTest — execute pixel_test on GSU-2 +; Returns: carry set=pass, carry clear=fail +; Side effect: stores CLSR value in gsuClsrVal +;============================================================ +RunGSUTest: + sep #$20 + .ACCU 8 + rep #$10 + .INDEX 16 + + ; Clear screen buffer at $70:0C00 + lda #0 + ldx #31 +_gsuClear: + sta.l $700C00,x + dex + bpl _gsuClear + + ; Copy pixel_test to $70:0200 (different base than demo at $70:0100 + ; so CACHE instruction naturally invalidates between programs) + ldx #PixelTestBinEnd - PixelTestBin - 1 +_gsuCopy: + lda.w PixelTestBin,x + sta.l $700200,x + dex + bpl _gsuCopy + + ; Configure GSU + lda #$80 + sta.l $3037 ; CFGR: mask IRQ + lda #$01 + sta.l $3039 ; CLSR: 21.4MHz + lda #$70 + sta.l $3034 ; PBR: bank $70 + lda #$03 + sta.l $3038 ; SCBR: screen base $0C00 + lda #$2D + sta.l $303A ; SCMR: 16-color OBJ, RAN + + ; Start GSU: R15=$0200 (pixel test at $70:0200) + lda #$00 + sta.l $301E ; R15 low + lda #$02 + sta.l $301F ; R15 high -> GO + + ; Poll SFR.GO + ldx #$FFFF +_gsuPoll: + lda.l $3030 + and #$20 + beq _gsuStopped + dex + bne _gsuPoll + clc + rts + +_gsuStopped: + ; Release buses + lda #$25 + sta.l $303A + ; Read CLSR for clock speed display + lda.l $3039 + sta gsuClsrVal + sec + rts + + +;============================================================ +; RunGSUDemo — Render 16x16 rainbow sprite and display via OAM +; Requires: gsuDetected = 1 +;============================================================ +;============================================================ +; SetupOBJBase — Initialize OBJ tile, palette, OAM, OBJSEL +; Writes a solid white 4bpp fallback tile via CPU (no GSU needed). +; RunGSUDemo overwrites the tile data if GSU is available. +;============================================================ +SetupOBJBase: + sep #$20 + .ACCU 8 + rep #$10 + .INDEX 16 + + ; OBJSEL: base at VRAM word $4000 (byte $8000), 8x8/16x16 size + lda #$02 + sta $2101 + + ; Upload a solid white 4bpp fallback tile to VRAM word $4000 + lda #$80 + sta $2115 ; VMAIN: increment on high + rep #$20 + .ACCU 16 + lda #$4000 + sta $2116 ; VRAM address + sep #$20 + .ACCU 8 + ldx #$0000 +_objTileFill: + lda #$FF ; all bitplanes set = color 15 + sta $2118 ; VMDATAL + sta $2119 ; VMDATAH → auto-increment + inx + cpx #16 ; 16 words = 32 bytes = one 4bpp tile + bne _objTileFill + + ; Load OBJ palette 0 at CGRAM[128] — rainbow + lda #128 + sta $2121 + ldx #$0000 +_objPalSetup: + lda.w ObjPaletteData,x + sta $2122 + inx + cpx #32 + bne _objPalSetup + + ; Set up OAM: sprite 0 at (120, 156), tile 0, priority 3 + stz $2102 + stz $2103 + lda #120 + sta $2104 + lda #156 + sta $2104 + lda #$00 + sta $2104 + lda #$30 + sta $2104 + + ; Move sprites 1-127 off-screen + ldx #127 +_objOamClear: + stz $2104 + lda #$F0 + sta $2104 + stz $2104 + stz $2104 + dex + bne _objOamClear + + ; 5th table: all small (8x8), no X MSB + stz $2104 ; sprite 0: small + stz $2104 + ldx #15 +_objOam5Clear: + stz $2104 + stz $2104 + dex + bne _objOam5Clear + + ; Enable OBJ + BG1 on mainscreen + lda #$11 + sta $212C + rts + + +;============================================================ +; RunGSUDemo — Overwrites the OBJ tile with GSU-rendered rainbow +;============================================================ +RunGSUDemo: + sep #$20 + .ACCU 8 + rep #$10 + .INDEX 16 + + ; Clear screen buffer at $70:0C00 (4KB to cover demo + flush tiles) + rep #$20 + .ACCU 16 + lda #$0000 + ldx #$07FE +_dClear: + sta.l $700C00,x + dex + dex + bpl _dClear + sep #$20 + .ACCU 8 + + ; Copy demo program to $70:0100 + ldx #GsuDemoBinEnd - GsuDemoBin - 1 +_dCopy: + lda.w GsuDemoBin,x + sta.l $700100,x + dex + bpl _dCopy + + ; Configure GSU (same regs as verification test) + lda #$80 + sta.l $3037 ; CFGR: mask IRQ + lda #$01 + sta.l $3039 ; CLSR: 21.4MHz + lda #$70 + sta.l $3034 ; PBR: bank $70 + lda #$03 + sta.l $3038 ; SCBR: screen base $0C00 + lda #$2D + sta.l $303A ; SCMR: 16-color OBJ, RAN + + ; Start GSU: R15=$0100 triggers GO + lda #$00 + sta.l $301E + lda #$01 + sta.l $301F + + ; Poll SFR.GO + ldx #$FFFF +_dPoll: + lda.l $3030 + and #$20 + beq _dStopped + dex + bne _dPoll + rts ; timeout — skip display +_dStopped: + lda #$25 + sta.l $303A ; release buses + + ; DMA GSU-rendered tile to VRAM $4000, overwriting the CPU fallback tile + lda #$80 + sta $2115 ; VMAIN: increment on high + rep #$20 + .ACCU 16 + lda #$4000 + sta $2116 ; VRAM address + sep #$20 + .ACCU 8 + lda #$01 ; 2-reg write once (VMDATAL/VMDATAH) + sta $4300 + lda #$18 + sta $4301 ; dest = $2118 + lda #$00 + sta $4302 ; source low + lda #$0C + sta $4303 ; source high → $0C00 + lda #$70 + sta $4304 ; source bank $70 + lda #$20 ; 32 bytes = one 4bpp tile + sta $4305 + stz $4306 + lda #$01 + sta $420B ; start DMA ch0 + rts + + +;============================================================ +; OBJ Palette — 15-step rainbow hue rotation for GSU demo +; CGRAM[128..143]: 16 colors (color 0 = transparent) +;============================================================ +ObjPaletteData: + .dw $0000 ; 0: transparent + .dw $001F ; 1: red + .dw $019F ; 2: red-orange + .dw $033F ; 3: orange-yellow + .dw $03F9 ; 4: yellow-green + .dw $03EC ; 5: chartreuse + .dw $03E0 ; 6: green + .dw $33E0 ; 7: spring green + .dw $67E0 ; 8: teal + .dw $7F20 ; 9: cyan-blue + .dw $7D80 ; 10: azure + .dw $7C00 ; 11: blue + .dw $7C0C ; 12: indigo + .dw $7C19 ; 13: violet + .dw $641F ; 14: magenta + .dw $301F ; 15: rose + + +;============================================================ +; String Data +;============================================================ +str_title: + .db "HiROM+GSU+MSU-1 TEST ROM v1.1", 0 +str_separator: + .db "==============================", 0 + +str_t_hirom: + .db "HiROM Mapping : ", 0 +str_t_banks: + .db "ROM Banks : ", 0 +str_t_wram: + .db "WRAM Read/Write : ", 0 +str_t_gsu_vcr: + .db "GSU-2 VCR : ", 0 +str_t_gsu_sram: + .db "GSU SRAM R/W : ", 0 +str_t_gsu_exec: + .db "GSU Execute : ", 0 +str_t_gpkram: + .db "Game Pak RAM : ", 0 +str_t_msu_det: + .db "MSU-1 Detect : ", 0 +str_t_msu_sts: + .db "MSU-1 Status : ", 0 + +str_pass: + .db "PASS", 0 +str_fail: + .db "FAIL", 0 +str_skip: + .db "SKIPPED", 0 +str_found: + .db "FOUND", 0 +str_notfound: + .db "NOT FOUND", 0 +str_dashes: + .db "--", 0 + +str_2kb: + .db "2KB", 0 +str_4kb: + .db "4KB", 0 +str_8kb: + .db "8KB", 0 +str_16kb: + .db "16KB", 0 +str_32kb: + .db "32KB", 0 +str_64kbp: + .db "64KB+", 0 + +str_cpu_label: + .db "CPU: ", 0 +str_cpu_fast: + .db "3.58MHz", 0 +str_gsu_label: + .db " GSU: ", 0 +str_clk_10: + .db "10.7MHz", 0 +str_clk_21: + .db "21.4MHz", 0 + +str_footer_rom: + .db "ROM: 4096KB SRAM: ", 0 +str_gsu_demo: + .db "GSU:", 0 +str_board: + .db "Board: SHVC-1CD0N7S-01", 0 +str_serial: + .db "Serial: SHVC-TEST", 0 + + +;============================================================ +; Palette Data +;============================================================ +PaletteData: + .dw $2842, $0000, $0000, $7FFF + .dw $0000, $0000, $0000, $03E0 + .dw $0000, $0000, $0000, $001F + .dw $0000, $0000, $0000, $03FF + .dw $0000, $0000, $0000, $7FE0 + + +;============================================================ +; Font Data + Pixel Test Binary +;============================================================ +FontData: + .incbin "build/font.bin" + +PixelTestBin: + .incbin "build/pixel_test.bin" +PixelTestBinEnd: + +GsuDemoBin: + .incbin "build/gsu_demo.bin" +GsuDemoBinEnd: + +GsuScalerBin: + .incbin "build/sprite_scaler.bin" +GsuScalerBinEnd: + +.ends + + +;============================================================ +; Extended Header ($FFB0-$FFBF) +;============================================================ +.bank 0 slot 0 +.org $FFB0 +.section "ext_header" force + .db "CD" + .db "TEST" + .dsb 7 0 + .db 0 + .db 0 + .db 0 +.ends + + +;============================================================ +; SNES Header ($FFC0-$FFDF) +;============================================================ +.org $FFC0 +.section "header" force + .db "HIROM GSU MSU1 TEST " + .db $31 ; HiROM + FastROM + .db $15 ; ROM + GSU + RAM + Battery + .db $0C ; ROM size: 4 MB (1<<12 KB) + .db $03 ; SRAM size: 8 KB + .db $01 ; country: USA/NTSC + .db $33 ; licensee: extended header + .db $00 ; version + .dw $FFFF ; checksum complement (dummy) + .dw $0000 ; checksum (dummy) +.ends + + +;============================================================ +; Native Mode Vectors ($FFE4-$FFEF) +;============================================================ +.org $FFE4 +.section "native_vectors" force + .dw EmptyHandler + .dw EmptyHandler + .dw EmptyHandler + .dw NmiHandler + .dw EmptyHandler + .dw EmptyHandler +.ends + + +;============================================================ +; Emulation Mode Vectors ($FFF4-$FFFF) +;============================================================ +.org $FFF4 +.section "emu_vectors" force + .dw EmptyHandler + .dw EmptyHandler + .dw EmptyHandler + .dw EmptyHandler + .dw Reset + .dw EmptyHandler +.ends diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.h b/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.h new file mode 100644 index 00000000..d0dd2206 --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/test_rom.h @@ -0,0 +1,13 @@ +; test_rom.h — HiROM+GSU+MSU-1 Test ROM +; Memory map and configuration for WLA-DX v9.3 + +.MEMORYMAP + DEFAULTSLOT 0 + SLOTSIZE $10000 + SLOT 0 $0000 +.ENDME + +.ROMBANKSIZE $10000 +.ROMBANKS 64 + +.EMPTYFILL $00 diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/defaults.arch b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/defaults.arch new file mode 100644 index 00000000..cd3d2d0d --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/defaults.arch @@ -0,0 +1,10 @@ +// This file contains default settings that should be restored whenever +// an architecture file is loaded + +#endian lsb + +#directive db 1 +#directive dw 2 +#directive dl 3 +#directive dd 4 +#directive dq 8 \ No newline at end of file diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/snes.gsu.arch b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/snes.gsu.arch new file mode 100644 index 00000000..0c0a8a7a --- /dev/null +++ b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/architectures/snes.gsu.arch @@ -0,0 +1,146 @@ +#include defaults + +// alt0 +stop ;$00 +nop ;$01 +cache ;$02 +lsr ;$03 +lsr #*08 ;*a:$03 +rol ;$04 +rol #*08 ;*a:$04 + +bra *08 ;$05 +2a +bge *08 ;$06 +2a +blt *08 ;$07 +2a +bne *08 ;$08 +2a +beq *08 ;$09 +2a +bpl *08 ;$0a +2a +bmi *08 ;$0b +2a +bcc *08 ;$0c +2a +bcs *08 ;$0d +2a +bvc *08 ;$0e +2a +bvs *08 ;$0f +2a + +to r*04 ;%0001 =a +with r*04 ;%0010 =a + +stw (r*04) ;%0011 =a + +loop ;$3c + +alt1 ;$3d +alt2 ;$3e +alt3 ;$3f + +ldw (r*04) ;%0100 =a + +plot ;$4c +swap ;$4d +color ;$4e +not ;$4f + +add r*04 ;%0101 =a +sub r*04 ;%0110 =a + +merge ;$70 + +and r*04 ;%0111 ~a + +mult r*04 ;%1000 ~a + +sbk ;$90 + +link #*03 ;%10010 =a + +sex ;$95 +asr ;$96 +asr #*08 ;*a:$96 +ror ;$97 +ror #*08 ;*a:$97 + +jmp r*04 ;%1001 =a + +lob ;$9e +fmult ;$9f + +ibt r*04, #*08 ;%1010 =a ~b + +from r*04 ;%1011 =a +hib ;$c0 + +or r*04 ;%1100 =a + +inc r*04 ;%1101 =a + +getc ;$df + +dec r*04 ;%1110 =a + +getb ;$ef + +iwt r*04, #*16 ;%1111 =a ~b +lea r*04, *16 ;%1111 =a ~b + +//--------- alt1 --------- +stb (r*04) ;$3d %0011 =a +ldb (r*04) ;$3d %0100 =a + +rpix ;$3d $4c +cmode ;$3d $4e + +adc r*04 ;$3d %0101 =a +sbc r*04 ;$3d %0110 =a + +bic r*04 ;$3d %0111 =a + +umult r*04 ;$3d %1000 =a + +div2 ;$3d $96 + +ljmp r*04 ;$3d %1001 =a + +lmult ;$3d $9f + +lms r*04, (*08) ;$3d %1010 =a >>01b + +xor r*04 ;$3d %1100 =a + +getbh ;$3d $ef +lm r*04, (*16) ;$3d %1111 =a ~b + +//--------- alt2 --------- +add #*04 ;$3e %0101 ~a +sub #*04 ;$3e %0110 ~a + +and #*04 ;$3e %0111 ~a + +mult #*04 ;$3e %1000 ~a + +sms (*08), r*04 ;$3e %1010 =b >>01a + +or #*04 ;$3e %1100 ~a + +ramb ;$3e $df +getbl ;$3e $ef + +sm (*16), r*04 ;$3e %1111 =b ~a + +//--------- alt3 --------- +adc #*04 ;$3f %0101 ~a +cmp r*04 ;$3f %0110 =a + +bic #*04 ;$3f %0111 ~a + +umult #*04 ;$3f %1000 ~a + +xor #*04 ;$3f %1100 ~a + +romb ;$3f $df +getbs ;$3f $ef + +//--------- pseudo-ops --------- +move r*04, r*04 ;%0010 =b %0001 =a +moves r*04, r*04 ;%0010 =a %1011 =b + +jal *16 ;$94 $ff ~a +ret ;$9b \ No newline at end of file diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/bass.exe b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/bass.exe new file mode 100644 index 00000000..d1547238 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/bass/bass.exe differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wla-65816 b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wla-65816 new file mode 100644 index 00000000..ec0c61d4 Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wla-65816 differ diff --git a/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wlalink b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wlalink new file mode 100644 index 00000000..88a7570f Binary files /dev/null and b/roms/snes-coprocessor-tests/hirom-gsu-test/tools/wla-dx/wlalink differ diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/.gitignore b/roms/snes-coprocessor-tests/sa1-bwram-smoke/.gitignore new file mode 100644 index 00000000..7a60b85e --- /dev/null +++ b/roms/snes-coprocessor-tests/sa1-bwram-smoke/.gitignore @@ -0,0 +1,2 @@ +__pycache__/ +*.pyc diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/BUILD.md b/roms/snes-coprocessor-tests/sa1-bwram-smoke/BUILD.md new file mode 100644 index 00000000..c70d107f --- /dev/null +++ b/roms/snes-coprocessor-tests/sa1-bwram-smoke/BUILD.md @@ -0,0 +1,20 @@ +# Building + +## Prerequisites + +- Python 3 + +No external packages or assembler toolchains are required. + +## Build + +```bash +python3 generate_rom.py +``` + +Output: + +- `build/Sa1BwramSmoke.sfc` - 64 KiB SA-1 LoROM-style test ROM + +The generator writes the 65C816 machine code and SNES header directly so the +artifact is deterministic and easy to reproduce in CI or locally. diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/README.md b/roms/snes-coprocessor-tests/sa1-bwram-smoke/README.md new file mode 100644 index 00000000..ab49620c --- /dev/null +++ b/roms/snes-coprocessor-tests/sa1-bwram-smoke/README.md @@ -0,0 +1,20 @@ +# SNES SA-1 BWRAM Smoke Test ROM + +A small self-authored SNES SA-1 test ROM for the nerust `rom_test` +harness. + +The program runs on the S-CPU with an SA-1 cartridge header and verifies a +minimal set of SA-1 host-visible behavior: + +- SA-1 cartridge header detection (`map mode $23`, chipset `$34`) +- default S-CPU BWRAM write protection +- `$2226` S-CPU BWRAM write-enable behavior +- `$2224` BMAPS page selection for `$00:6000-$00:7FFF` + +Results are copied into WRAM `$7E:0000-$7E:0003` for the manifest assertions. +The ROM intentionally leaves display output blank; `rom_test` still captures a +deterministic final screen hash and screenshot. + +## License + +Public domain. Use freely for emulator testing, development, and validation. diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/UPSTREAM.md b/roms/snes-coprocessor-tests/sa1-bwram-smoke/UPSTREAM.md new file mode 100644 index 00000000..94a2b452 --- /dev/null +++ b/roms/snes-coprocessor-tests/sa1-bwram-smoke/UPSTREAM.md @@ -0,0 +1,11 @@ +# Provenance + +This ROM is self-authored for nerust and is generated from +`generate_rom.py` in this directory. + +- No external ROM image or commercial/proprietary content is used. +- No git subtree import is required because there is no upstream repository. +- The generated artifact committed for the `rom_test` harness is: + - `build/Sa1BwramSmoke.sfc` + - SHA-256: + `e375a275fb641942c187d879c27f30edaf1656b9e4260734097a7e2606bf250d` diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/build/Sa1BwramSmoke.sfc b/roms/snes-coprocessor-tests/sa1-bwram-smoke/build/Sa1BwramSmoke.sfc new file mode 100644 index 00000000..53495566 Binary files /dev/null and b/roms/snes-coprocessor-tests/sa1-bwram-smoke/build/Sa1BwramSmoke.sfc differ diff --git a/roms/snes-coprocessor-tests/sa1-bwram-smoke/generate_rom.py b/roms/snes-coprocessor-tests/sa1-bwram-smoke/generate_rom.py new file mode 100644 index 00000000..463d76a4 --- /dev/null +++ b/roms/snes-coprocessor-tests/sa1-bwram-smoke/generate_rom.py @@ -0,0 +1,101 @@ +#!/usr/bin/env python3 + +from pathlib import Path + +ROM_SIZE = 64 * 1024 +HEADER_OFFSET = 0x7FC0 +RESET_VECTOR_OFFSET = 0x7FFC +PROGRAM_ADDRESS = 0x8000 +PROGRAM_OFFSET = PROGRAM_ADDRESS - 0x8000 +OUTPUT_PATH = Path(__file__).resolve().parent / "build" / "Sa1BwramSmoke.sfc" + + +def u16(value): + return [value & 0xFF, (value >> 8) & 0xFF] + + +def lda_imm(value): + return [0xA9, value & 0xFF] + + +def sta_abs(address): + return [0x8D, *u16(address)] + + +def lda_abs(address): + return [0xAD, *u16(address)] + + +def sta_long(bank, address): + return [0x8F, address & 0xFF, (address >> 8) & 0xFF, bank & 0xFF] + + +def build_program(): + code = [] + + # Default BWPA=$0F protects all BWRAM. This write must be ignored. + code += lda_imm(0xAA) + code += sta_abs(0x6000) + code += lda_abs(0x6000) + code += sta_long(0x7E, 0x0000) + + # Enable S-CPU BWRAM writes and verify page 0 read-back. + code += lda_imm(0x80) + code += sta_abs(0x2226) + code += lda_imm(0x5A) + code += sta_abs(0x6000) + code += lda_abs(0x6000) + code += sta_long(0x7E, 0x0001) + + # Select BMAPS page 1, write/read it, then switch back to page 0. + code += lda_imm(0x01) + code += sta_abs(0x2224) + code += lda_imm(0xA5) + code += sta_abs(0x6000) + code += lda_abs(0x6000) + code += sta_long(0x7E, 0x0002) + + code += lda_imm(0x00) + code += sta_abs(0x2224) + code += lda_abs(0x6000) + code += sta_long(0x7E, 0x0003) + + # Stay alive for benchmark frame loops. + code += [0x80, 0xFE] + return bytes(code) + + +def write_header(rom): + title = b"NERUST SA1 BWRAM " + rom[HEADER_OFFSET : HEADER_OFFSET + len(title)] = title + rom[HEADER_OFFSET + 0x15] = 0x23 # SA-1 map mode + rom[HEADER_OFFSET + 0x16] = 0x34 # SA-1 + RAM + battery family + rom[HEADER_OFFSET + 0x17] = 0x06 # 64 KiB ROM + rom[HEADER_OFFSET + 0x18] = 0x05 # 32 KiB BWRAM + rom[HEADER_OFFSET + 0x19] = 0x01 # NTSC + rom[HEADER_OFFSET + 0x1A] = 0x33 # maker code + rom[HEADER_OFFSET + 0x1B] = 0x00 # version + + for vector_offset in (0x7FEA, 0x7FEC, 0x7FEE, 0x7FFA, RESET_VECTOR_OFFSET, 0x7FFE): + rom[vector_offset : vector_offset + 2] = bytes(u16(PROGRAM_ADDRESS)) + + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x20] = b"\x00\x00\x00\x00" + checksum = sum(rom) & 0xFFFF + complement = checksum ^ 0xFFFF + rom[HEADER_OFFSET + 0x1C : HEADER_OFFSET + 0x1E] = bytes(u16(complement)) + rom[HEADER_OFFSET + 0x1E : HEADER_OFFSET + 0x20] = bytes(u16(checksum)) + + +def main(): + rom = bytearray([0xFF] * ROM_SIZE) + program = build_program() + rom[PROGRAM_OFFSET : PROGRAM_OFFSET + len(program)] = program + write_header(rom) + + OUTPUT_PATH.parent.mkdir(parents=True, exist_ok=True) + OUTPUT_PATH.write_bytes(rom) + print(f"wrote {OUTPUT_PATH} ({len(rom)} bytes)") + + +if __name__ == "__main__": + main() diff --git a/roms/snes-test-roms/.gitattributes b/roms/snes-test-roms/.gitattributes new file mode 100644 index 00000000..37346445 --- /dev/null +++ b/roms/snes-test-roms/.gitattributes @@ -0,0 +1,2 @@ +*.asm linguist-language=Assembly +*.inc linguist-language=Assembly diff --git a/roms/snes-test-roms/.gitignore b/roms/snes-test-roms/.gitignore new file mode 100644 index 00000000..a84690a5 --- /dev/null +++ b/roms/snes-test-roms/.gitignore @@ -0,0 +1,6 @@ +*.swp +*~ + +bin/ +gen/ + diff --git a/roms/snes-test-roms/.gitmodules b/roms/snes-test-roms/.gitmodules new file mode 100644 index 00000000..ca85b3e2 --- /dev/null +++ b/roms/snes-test-roms/.gitmodules @@ -0,0 +1,3 @@ +[submodule "tools/bass-untech"] + path = bass-untech + url = https://github.com/undisbeliever/bass-untech.git diff --git a/roms/snes-test-roms/.markdownlint-cli2.yaml b/roms/snes-test-roms/.markdownlint-cli2.yaml new file mode 100644 index 00000000..f20ac7f5 --- /dev/null +++ b/roms/snes-test-roms/.markdownlint-cli2.yaml @@ -0,0 +1,3 @@ +config: + MD013: false + MD025: false diff --git a/roms/snes-test-roms/.ruff.toml b/roms/snes-test-roms/.ruff.toml new file mode 100644 index 00000000..b897b9ef --- /dev/null +++ b/roms/snes-test-roms/.ruff.toml @@ -0,0 +1,2 @@ +[lint] +ignore = ["F841"] diff --git a/roms/snes-test-roms/GNUmakefile b/roms/snes-test-roms/GNUmakefile new file mode 100644 index 00000000..7f82cc55 --- /dev/null +++ b/roms/snes-test-roms/GNUmakefile @@ -0,0 +1,185 @@ + +ASM_FILES := $(wildcard src/*/*.asm src/*/*/*.asm) +COMMON_INC_FILES := $(wildcard src/*.inc src/_common/*.inc) + +MODE7_TILES_SRC := $(wildcard resources/*/*mode7-tiles.png) +8BPP_TILES_SRC := $(wildcard resources/*/*8bpp-tiles.png) +4BPP_TILES_SRC := $(wildcard resources/*/*4bpp-tiles.png) +2BPP_TILES_SRC := $(wildcard resources/*/*2bpp-tiles.png) +1BPP_TILES_SRC := $(wildcard resources/*/*1bpp-tiles.png) +BIN_RESOURCES_SRC:= $(wildcard resources/*/*.asm) + +MODE7_TILES := $(patsubst resources/%.png,gen/%.tiles, $(MODE7_TILES_SRC)) +8BPP_TILES := $(patsubst resources/%.png,gen/%.tiles, $(8BPP_TILES_SRC)) +4BPP_TILES := $(patsubst resources/%.png,gen/%.tiles, $(4BPP_TILES_SRC)) +2BPP_TILES := $(patsubst resources/%.png,gen/%.tiles, $(2BPP_TILES_SRC)) +1BPP_TILES := $(patsubst resources/%.png,gen/%.tiles, $(1BPP_TILES_SRC)) + +BIN_RESOURCES := $(patsubst resources/%.asm,gen/%.bin, $(BIN_RESOURCES_SRC)) + +MODE7_PALETTES := $(patsubst resources/%.png,gen/%.pal, $(MODE7_TILES_SRC)) +8BPP_PALETTES := $(patsubst resources/%.png,gen/%.pal, $(8BPP_TILES_SRC)) +4BPP_PALETTES := $(patsubst resources/%.png,gen/%.pal, $(4BPP_TILES_SRC)) +2BPP_PALETTES := $(patsubst resources/%.png,gen/%.pal, $(2BPP_TILES_SRC)) +1BPP_PALETTES := $(patsubst resources/%.png,gen/%.pal, $(1BPP_TILES_SRC)) + +4BPP_IMAGES := inidisp-fadein-fadeout/game inidisp-fadein-fadeout/map +2BPP_IMAGES := test-patterns/scanline-bit-pattern + +4BPP_IMAGES += hdma-textbox-wipe/bg1 hdma-textbox-wipe/bg2 +2BPP_IMAGES += hdma-textbox-wipe/bg3 + +2BPP_IMAGES += hdma-hoffset-examples/vertical-bar-2bpp +2BPP_IMAGES += hdma-hoffset-examples/two-vertical-bars-2bpp +2BPP_IMAGES += hdma-hoffset-examples/shear-titlescreen-2bpp + + +BINARIES := $(patsubst src/%.asm,bin/%.sfc,$(ASM_FILES)) + +RESOURCES := $(MODE7_TILES) $(MODE7_PALETTES) \ + $(8BPP_TILES) $(8BPP_PALETTES) \ + $(4BPP_TILES) $(4BPP_PALETTES) \ + $(2BPP_TILES) $(2BPP_PALETTES) \ + $(1BPP_TILES) $(1BPP_PALETTES) \ + $(patsubst %,gen/%.4bpp,$(4BPP_IMAGES)) $(patsubst %,gen/%.tilemap,$(4BPP_IMAGES)) $(patsubst %,gen/%.palette,$(4BPP_IMAGES)) \ + $(patsubst %,gen/%.2bpp,$(2BPP_IMAGES)) $(patsubst %,gen/%.tilemap,$(2BPP_IMAGES)) $(patsubst %,gen/%.palette,$(2BPP_IMAGES)) \ + $(BIN_RESOURCES) + + +# If VANILLA_BASS is not 'n' then the Makefile will use vanilla bass instead of bass-untech +VANILLA_BASS ?= n +# If LOCAL_TOOLS is not 'n' then the Makefile will use the tools installed in the user's $PATH +LOCAL_TOOLS ?= n + + + +ifneq ($(VANILLA_BASS), n) + bass ?= bass +else ifneq ($(LOCAL_TOOLS), n) + bass := bass-untech +endif + +ifndef bass + BASS_DIR := bass-untech + bass := $(BASS_DIR)/bass/out/bass-untech +endif + + +.DELETE_ON_ERROR: +.SUFFIXES: + +.PHONY: all +all: directories roms + + +.PHONY: roms +roms: $(BINARIES) + + +ifeq ($(VANILLA_BASS), n) +bin/%.sfc: src/%.asm $(COMMON_INC_FILES) tools/write-sfc-checksum.py + $(bass) -strict -o $@ -sym $(@:.sfc=.sym) $< + python3 tools/write-sfc-checksum.py --lorom $@ + +else +bin/%.sfc: src/%.asm $(COMMON_INC_FILES) tools/write-sfc-checksum.py + $(bass) -strict -o $@ $< + python3 tools/write-sfc-checksum.py --lorom $@ +endif + + + +ifdef BASS_DIR + tools: bass + + $(BINARIES): bass + $(BIN_RESOURCES): bass + + .INTERMEDIATE: bass + bass: $(call rwildcard_all $(BASS_DIR)) + $(MAKE) -C '$(BASS_DIR)/bass' + + $(bass): bass +endif + + +VMAIN_REMAPPING_INC_FILES := $(wildcard src/vmain-address-remapping/*.inc) +VMAIN_REMAPPING_BINARIES := $(filter bin/vmain-address-remapping/%.sfc, $(BINARIES)) + +$(VMAIN_REMAPPING_BINARIES): $(VMAIN_REMAPPING_INC_FILES) + + +QUICK_MODEL_1_DMA_CRASH_INC_FILES := $(wildcard src/hardware-glitch-tests/quick-model-1-dma-crash/*.inc) +QUICK_MODEL_1_DMA_CRASH_BINARIES := $(filter bin/hardware-glitch-tests/quick-model-1-dma-crash/%.sfc, $(BINARIES)) + +$(QUICK_MODEL_1_DMA_CRASH_BINARIES): $(QUICK_MODEL_1_DMA_CRASH_INC_FILES) + + +AUTO_JOYPAD_INC_FILES := $(wildcard src/hardware-tests/auto-joypad/*.inc) +AUTO_JOYPAD_BINARIES := $(filter bin/hardware-tests/auto-joypad/%.sfc, $(BINARIES)) + +$(AUTO_JOYPAD_BINARIES): $(AUTO_JOYPAD_INC_FILES) + + +.PHONY: resources +resources: $(RESOURCES) +$(BINARIES): $(RESOURCES) + +gen/%-1bpp-tiles.tiles gen/%-1bpp-tiles.pal: resources/%-1bpp-tiles.png + python3 tools/png2snes.py -f 1bpp -t gen/$*-1bpp-tiles.tiles -p gen/$*-1bpp-tiles.pal $< + +gen/%-2bpp-tiles.tiles gen/%-2bpp-tiles.pal: resources/%-2bpp-tiles.png + python3 tools/png2snes.py -f 2bpp -t gen/$*-2bpp-tiles.tiles -p gen/$*-2bpp-tiles.pal $< + +gen/%-4bpp-tiles.tiles gen/%-4bpp-tiles.pal: resources/%-4bpp-tiles.png + python3 tools/png2snes.py -f 4bpp -t gen/$*-4bpp-tiles.tiles -p gen/$*-4bpp-tiles.pal $< + +gen/%-8bpp-tiles.tiles gen/%-8bpp-tiles.pal: resources/%-8bpp-tiles.png + python3 tools/png2snes.py -f 8bpp -t gen/$*-8bpp-tiles.tiles -p gen/$*-8bpp-tiles.pal $< + +gen/%-mode7-tiles.tiles gen/%-mode7-tiles.pal: resources/%-mode7-tiles.png + python3 tools/png2snes.py -f mode7 -t gen/$*-mode7-tiles.tiles -p gen/$*-mode7-tiles.pal $< + + +gen/%.4bpp gen/%.tilemap gen/%.palette: resources/%.png resources/%-palette.png tools/image2snes.py tools/_snes.py + python3 tools/image2snes.py -f 4bpp -t gen/$*.4bpp -m gen/$*.tilemap -p gen/$*.palette resources/$*.png resources/$*-palette.png + +gen/%.2bpp gen/%.tilemap gen/%.palette: resources/%.png resources/%-palette.png tools/image2snes.py tools/_snes.py + python3 tools/image2snes.py -f 2bpp -t gen/$*.2bpp -m gen/$*.tilemap -p gen/$*.palette resources/$*.png resources/$*-palette.png + + +$(BIN_RESOURCES): gen/%.bin: resources/%.asm + $(bass) -strict -o $@ $< + + + +.PHONY: directories +DIRS := $(sort $(dir $(BINARIES) $(RESOURCES) $(TABLE_INCS))) +DIRS := $(patsubst %/,%,$(DIRS)) +directories: $(DIRS) +$(DIRS): + ifeq ($(OS),Windows_NT) + mkdir $(subst /,\,$@) + else + mkdir -p $@ + endif + + + +.PHONY: clean-all +clean-all: clean + +.PHONY: clean +clean: + $(RM) $(BINARIES) $(BINARIES:.sfc=.symbols) + $(RM) $(sort $(TABLE_INCS)) + $(RM) $(sort $(RESOURCES)) + +ifdef BASS_DIR + clean-all: clean-tools + + .PHONY: clean-tools + clean-tools: + $(MAKE) -C '$(BASS_DIR)/bass' clean +endif + diff --git a/roms/snes-test-roms/LICENSE b/roms/snes-test-roms/LICENSE new file mode 100644 index 00000000..337f9423 --- /dev/null +++ b/roms/snes-test-roms/LICENSE @@ -0,0 +1,22 @@ +zlib License + +Copyright © 2016 Marcus Rowe + +This software is provided 'as-is', without any express or implied warranty. +In no event will the authors be held liable for any damages arising from the +use of this software. + +Permission is granted to anyone to use this software for any purpose, including +commercial applications, and to alter it and redistribute it freely, subject to +the following restrictions: + + 1. The origin of this software must not be misrepresented; you must not + claim that you wrote the original software. If you use this software in + a product, an acknowledgment in the product documentation would be + appreciated but is not required. + + 2. Altered source versions must be plainly marked as such, and must not be + misrepresented as being the original software. + + 3. This notice may not be removed or altered from any source distribution. + diff --git a/roms/snes-test-roms/UPSTREAM.md b/roms/snes-test-roms/UPSTREAM.md new file mode 100644 index 00000000..6e7bfef3 --- /dev/null +++ b/roms/snes-test-roms/UPSTREAM.md @@ -0,0 +1,78 @@ +# Upstream provenance + +Source: + +- Upstream repository commit: `ac6ef80` +- Local artifact branch: `release-artifacts` +- Included generated ROMs: + - `bin/65816-examples/arguments-after-jsr.sfc` + - `bin/examples/hdma-double-buffered-indirect-shear.sfc` + - `bin/examples/hdma-double-buffered-parallax.sfc` + - `bin/examples/hdma-160scanline-hdma-entry.sfc` + - `bin/examples/hdma-indirect-mapping.sfc` + - `bin/examples/hdma-indirect-repeating-pattern.sfc` + - `bin/examples/hdma-to-cgram.sfc` + - `bin/examples/hdma-repeat-entry.sfc` + - `bin/examples/textbuffer-hello-world.sfc` + - `bin/examples/vram-writes-without-dma.sfc` + - `bin/effects/inidisp_extend_vblank.sfc` + - `bin/effects/inidisp_fadein_fadeout.sfc` + - `bin/effects/hdma-textbox-wipe.sfc` + - `bin/effects/repeating_hdma_pattern.sfc` + - `bin/effects/window-precalculated-single.sfc` + - `bin/effects/window-precalculated-symmetrical.sfc` + - `bin/effects/window-shapes-single.sfc` + - `bin/effects/window-mask-logic.sfc` + - `bin/effects/vmain-1bpp-tiles-0.sfc` + - `bin/effects/vmain-1bpp-tiles-1.sfc` + - `bin/effects/vmain-horizontal-scrolling.sfc` + - `bin/effects/vmain-mode7-tilemap-columns.sfc` + - `bin/effects/vmain-mode7-tilemap-rows.sfc` + - `bin/effects/vmain-vertical-scrolling-2-rows.sfc` + - `bin/effects/vmain-vertical-scrolling.sfc` + - `bin/hardware-tests/auto-joypad/auto-joy-timing-test.sfc` + - `bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sfc` + - `bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sfc` + - `bin/hardware-tests/auto-joypad/blip-autojoy-test.sfc` + - `bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sfc` + - `bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sfc` + - `bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sfc` + - `bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sfc` + - `bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sfc` + - `bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sfc` + - `bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sfc` + - `bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sfc` + - `bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sfc` + - `bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sfc` + - `bin/hardware-tests/hdma-timing-demonstration.sfc` + - `bin/hardware-tests/hdmaen_latch_test.sfc` + - `bin/hardware-tests/hdmaen_latch_test_2.sfc` + - `bin/hardware-tests/inidisp_brightness_0.sfc` + - `bin/hardware-tests/inidisp_brightness_delay.sfc` + - `bin/hardware-tests/inidisp_enable_display_mid_frame.sfc` + - `bin/hardware-tests/inidisp_forgot_to_force_blank.sfc` + - `bin/hardware-tests/inidisp_forgot_to_force_blank_2.sfc` + - `bin/hardware-tests/joypad_bounce_test.sfc` + - `bin/hardware-tests/joypad_rapid_read_test.sfc` + - `bin/hardware-tests/object-dropout-test.sfc` + - `bin/hardware-tests/reset-position-test.sfc` + - `bin/hardware-tests/vram-mid-scanline-test.sfc` + - `bin/hardware-tests/wrmpyb-in-flight.sfc` + - `bin/vmain-address-remapping/vmain-1bpp-no-remapping.sfc` + - `bin/vmain-address-remapping/vmain-1bpp-with-remapping.sfc` + - `bin/vmain-address-remapping/vmain-2bpp-no-remapping.sfc` + - `bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sfc` + - `bin/vmain-address-remapping/vmain-2bpp-with-remapping.sfc` + - `bin/vmain-address-remapping/vmain-4bpp-no-remapping.sfc` + - `bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sfc` + - `bin/vmain-address-remapping/vmain-4bpp-with-remapping.sfc` + - `bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sfc` + - `bin/vmain-address-remapping/vmain-8bpp-no-remapping.sfc` + - `bin/vmain-address-remapping/vmain-8bpp-with-remapping.sfc` + - `bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sfc` + - `bin/vmain-address-remapping/vmain-mode7-image-tilemap.sfc` + - `bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sfc` + - `bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sfc` +- Local build inputs: upstream sources plus the already vendored `bass-untech` + toolchain from this repository and the Python environment prepared in this + session for asset generation. diff --git a/roms/snes-test-roms/bass-untech/.gitignore b/roms/snes-test-roms/bass-untech/.gitignore new file mode 100644 index 00000000..e1bfa8e5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/.gitignore @@ -0,0 +1,2 @@ +bass/obj +bass/out diff --git a/roms/snes-test-roms/bass-untech/README.md b/roms/snes-test-roms/bass-untech/README.md new file mode 100644 index 00000000..759e34b0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/README.md @@ -0,0 +1,15 @@ +The UnDisbeliever's bass fork +============================= + +This repository contains The UnDisbeliever's personal fork of Near's bass assembler. + +It contains features that do not exist in vanilla bass, including: + +* Printing the instruction stack when displaying error messages +* Symbol file support +* Stricter expression evaluation + +License +======= + +bass and bass-untech is licensed under the ISC license. diff --git a/roms/snes-test-roms/bass-untech/bass/GNUmakefile b/roms/snes-test-roms/bass-untech/bass/GNUmakefile new file mode 100644 index 00000000..37b5b2e0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/GNUmakefile @@ -0,0 +1,71 @@ +name := bass-untech +build := release +console := true +flags += -I.. + +nall.path := ../nall +include $(nall.path)/GNUmakefile + +objects := obj/bass.o + +ifeq ($(platform), windows) + name := $(name).exe +endif + +obj/bass.o: bass.cpp + +all: out/$(name) out-architectures + +out/$(name): out obj $(objects) + $(info Linking out/$(name) ...) + +@$(compiler) -o out/$(name) $(objects) $(options) + +verbose: nall.verbose all; + +clean: + $(call delete,obj/*) + $(call delete,out/$(name)) + $(call delete,out/architectures/*) + +obj out: + mkdir $@ + +install: all +ifeq ($(shell id -un),root) + $(error "make install should not be run as root") +else ifneq ($(filter $(platform),linux bsd),) + cp out/$(name) $(prefix)/bin/$(name) + mkdir -p $(prefix)/share/$(name)/architectures/ + cp -R data/architectures/* $(prefix)/share/$(name)/architectures/ +endif + +uninstall: +ifeq ($(shell id -un),root) + $(error "make uninstall should not be run as root") +else ifneq ($(filter $(platform),linux bsd),) + rm -f $(prefix)/bin/$(name) +endif + + +# Copy architectures to out/ so bass-untech can be used without installing it +architectures := $(wildcard data/architectures/*.arch) + +.PHONY: out-architectures +out-architectures: out/architectures +out-architectures: $(architectures:data/architectures/%=out/architectures/%) + +out/architectures/%.arch: data/architectures/%.arch +ifeq ($(platform), windows) + copy "$(subst /,\,$<)" "$(subst /,\,$@)" +else + cp "$<" "$@" +endif + +out/architectures: +ifeq ($(platform), windows) + mkdir out\architectures +else + mkdir -p out/architectures +endif + +-include obj/*.d diff --git a/roms/snes-test-roms/bass-untech/bass/architecture/architecture.hpp b/roms/snes-test-roms/bass-untech/bass/architecture/architecture.hpp new file mode 100644 index 00000000..03c182b7 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/architecture/architecture.hpp @@ -0,0 +1,47 @@ +struct Architecture { + Architecture(Bass& self) : self(self) { + } + + virtual ~Architecture() { + } + + virtual auto assemble(const string& statement) -> bool { + return false; + } + + // + + auto pc() const -> uint { + return self.pc(); + } + + auto endian() const -> Bass::Endian { + return self.endian; + } + + auto setEndian(Bass::Endian endian) -> void { + self.endian = endian; + } + + auto evaluate(const string& expression, Bass::Evaluation mode = Bass::Evaluation::Strict) -> int64_t { + return self.evaluate(expression, mode); + } + + auto write(uint64_t data, uint length = 1) -> void { + return self.write(data, length); + } + + template auto notice(P&&... p) -> void { + return self.notice(forward

(p)...); + } + + template auto warning(P&&... p) -> void { + return self.warning(forward

(p)...); + } + + template auto error(P&&... p) -> void { + return self.error(forward

(p)...); + } + + Bass& self; +}; diff --git a/roms/snes-test-roms/bass-untech/bass/architecture/table/table.cpp b/roms/snes-test-roms/bass-untech/bass/architecture/table/table.cpp new file mode 100644 index 00000000..d9381d3a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/architecture/table/table.cpp @@ -0,0 +1,235 @@ +Table::Table(Bass& self, const string& table) : Architecture(self) { + bitval = 0; + bitpos = 0; + parseTable(table); +} + +auto Table::assemble(const string& statement) -> bool { + string s = statement; + + if(s.match("instrument \"*\"")) { + s.trim("instrument \"", "\"", 1L); + parseTable(s); + return true; + } + + uint pc = Architecture::pc(); + + for(auto& opcode : table) { + if(!tokenize(s, opcode.pattern)) continue; + + string_vector args; + tokenize(args, s, opcode.pattern); + if(args.size() != opcode.number.size()) continue; + + bool mismatch = false; + for(auto& format : opcode.format) { + if(format.type == Format::Type::Absolute) { + if(format.match != Format::Match::Weak) { + uint bits = bitLength(args[format.argument]); + if(bits != opcode.number[format.argument].bits) { + if(format.match == Format::Match::Exact || bits != 0) { + mismatch = true; + break; + } + } + } + } + } + if(mismatch) continue; + + for(auto& format : opcode.format) { + switch(format.type) { + case Format::Type::Static: { + writeBits(format.data, format.bits); + break; + } + + case Format::Type::Absolute: { + uint data = evaluate(args[format.argument], Bass::Evaluation::Lax); + writeBits(data, opcode.number[format.argument].bits); + break; + } + + case Format::Type::Relative: { + int data = evaluate(args[format.argument], Bass::Evaluation::Lax) - (pc + format.displacement); + uint bits = opcode.number[format.argument].bits; + int min = -(1 << (bits - 1)), max = +(1 << (bits - 1)) - 1; + if(data < min || data > max) error("branch out of bounds"); + writeBits(data, opcode.number[format.argument].bits); + break; + } + + case Format::Type::Repeat: { + uint data = evaluate(args[format.argument], Bass::Evaluation::Lax); + for(uint n : range(data)) { + writeBits(format.data, opcode.number[format.argument].bits); + } + break; + } + } + } + + return true; + } + + return false; +} + +auto Table::bitLength(string& text) const -> uint { + auto binLength = [&](const char* p) -> uint { + uint length = 0; + while(*p) { + if(*p == '0' || *p == '1') { p++; length += 1; continue; } + return 0; + } + return length; + }; + + auto hexLength = [&](const char* p) -> uint { + uint length = 0; + while(*p) { + if(*p >= '0' && *p <= '9') { p++; length += 4; continue; } + if(*p >= 'a' && *p <= 'f') { p++; length += 4; continue; } + if(*p >= 'A' && *p <= 'F') { p++; length += 4; continue; } + return 0; + } + return length; + }; + + char* p = text.get(); + if(*p == '<') { *p = ' '; return 8; } + if(*p == '>') { *p = ' '; return 16; } + if(*p == '^') { *p = ' '; return 24; } + if(*p == '?') { *p = ' '; return 32; } + if(*p == ':') { *p = ' '; return 64; } + if(*p == '%') return binLength(p + 1); + if(*p == '$') return hexLength(p + 1); + if(*p == '0' && *(p + 1) == 'b') return binLength(p + 2); + if(*p == '0' && *(p + 1) == 'x') return hexLength(p + 2); + return 0; +} + +auto Table::writeBits(uint64_t data, uint length) -> void { + bitval <<= length; + bitval |= data; + bitpos += length; + + while(bitpos >= 8) { + write(bitval); + bitval >>= 8; + bitpos -= 8; + } +} + +auto Table::parseTable(const string& text) -> bool { + auto lines = text.split("\n"); + for(auto& line : lines) { + if(auto position = line.find("//")) line.resize(position()); //remove comments + + if(line == "endian lsb") { setEndian(Bass::Endian::LSB); continue; } + if(line == "endian msb") { setEndian(Bass::Endian::MSB); continue; } + + auto part = line.split(";", 1L).strip(); + if(part.size() != 2) continue; + + Opcode opcode; + assembleTableLHS(opcode, part(0)); + assembleTableRHS(opcode, part(1)); + table.append(opcode); + } + + return true; +} + +auto Table::assembleTableLHS(Opcode& opcode, const string& text) -> void { + uint offset = 0; + + auto length = [&] { + uint length = 0; + while(text[offset + length]) { + char n = text[offset + length]; + if(n == '*') break; + length++; + } + return length; + }; + + while(text[offset]) { + uint size = length(); + opcode.prefix.append({slice(text, offset, size), size}); + offset += size; + + if(text[offset] != '*') continue; + uint bits = 10 * (text[offset + 1] - '0'); + bits += text[offset + 2] - '0'; + opcode.number.append({bits}); + offset += 3; + } + + for(auto& prefix : opcode.prefix) { + opcode.pattern.append(prefix.text, "*"); + } + opcode.pattern.trimRight("*", 1L); + if(opcode.number.size() == opcode.prefix.size()) opcode.pattern.append("*"); +} + +auto Table::assembleTableRHS(Opcode& opcode, const string& text) -> void { + uint offset = 0; + + auto list = text.split(" "); + for(auto& item : list) { + if(item[0] == '$' && item.length() == 3) { + Format format = {Format::Type::Static}; + format.data = toHex((const char*)item + 1); + format.bits = (item.length() - 1) * 4; + opcode.format.append(format); + } + + if(item[0] == '%') { + Format format = {Format::Type::Static}; + format.data = toBinary((const char*)item + 1); + format.bits = (item.length() - 1); + opcode.format.append(format); + } + + if(item[0] == '!') { + Format format = {Format::Type::Absolute, Format::Match::Exact}; + format.argument = item[1] - 'a'; + opcode.format.append(format); + } + + if(item[0] == '=') { + Format format = {Format::Type::Absolute, Format::Match::Strong}; + format.argument = item[1] - 'a'; + opcode.format.append(format); + } + + if(item[0] == '~') { + Format format = {Format::Type::Absolute, Format::Match::Weak}; + format.argument = item[1] - 'a'; + opcode.format.append(format); + } + + if(item[0] == '+') { + Format format = {Format::Type::Relative}; + format.argument = item[2] - 'a'; + format.displacement = +(item[1] - '0'); + opcode.format.append(format); + } + + if(item[0] == '-') { + Format format = {Format::Type::Relative}; + format.argument = item[2] - 'a'; + format.displacement = -(item[1] - '0'); + opcode.format.append(format); + } + + if(item[0] == '*') { + Format format = {Format::Type::Repeat}; + format.argument = item[1] - 'a'; + format.data = toHex((const char*)item + 3); + opcode.format.append(format); + } + } +} diff --git a/roms/snes-test-roms/bass-untech/bass/architecture/table/table.hpp b/roms/snes-test-roms/bass-untech/bass/architecture/table/table.hpp new file mode 100644 index 00000000..eaee833f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/architecture/table/table.hpp @@ -0,0 +1,39 @@ +struct Table : Architecture { + Table(Bass& self, const string& table); + auto assemble(const string& statement) -> bool override; + +private: + struct Prefix { + string text; + uint size; + }; + + struct Number { + uint bits; + }; + + struct Format { + enum class Type : uint { Static, Absolute, Relative, Repeat } type; + enum class Match : uint { Exact, Strong, Weak } match; + uint data; + uint bits; + uint argument; + int displacement; + }; + + struct Opcode { + vector prefix; + vector number; + vector format; + string pattern; + }; + + auto bitLength(string& text) const -> uint; + auto writeBits(uint64_t data, uint bits) -> void; + auto parseTable(const string& text) -> bool; + auto assembleTableLHS(Opcode& opcode, const string& text) -> void; + auto assembleTableRHS(Opcode& opcode, const string& text) -> void; + + vector table; + uint64_t bitval, bitpos; +}; diff --git a/roms/snes-test-roms/bass-untech/bass/bass.cpp b/roms/snes-test-roms/bass-untech/bass/bass.cpp new file mode 100644 index 00000000..6575ef72 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/bass.cpp @@ -0,0 +1,82 @@ +//bass-untech +//license: ISC +//author: Near +//forked by: The UnDisbeliever +//project started: 2013-09-27 + +#include "bass.hpp" +#include "core/core.cpp" +#include "architecture/table/table.cpp" + +#include +auto nall::main(Arguments arguments) -> void { + if(!arguments) { + print(stderr, "bass-untech v17\n"); + print(stderr, "\n"); + print(stderr, "usage:\n"); + print(stderr, " bass-untech [options] source [source ...]\n"); + print(stderr, "\n"); + print(stderr, "options:\n"); + print(stderr, " -o target specify default output filename [overwrite]\n"); + print(stderr, " -m target specify default output filename [modify]\n"); + print(stderr, " -d name[=value] create define with optional value\n"); + print(stderr, " -c name[=value] create constant with optional value\n"); + print(stderr, " -sym filename create symbol file\n"); + print(stderr, " -strict upgrade warnings to errors\n"); + print(stderr, " -benchmark benchmark performance\n"); + exit(EXIT_FAILURE); + } + + string targetFilename; + bool create = false; + if(arguments.take("-o", targetFilename)) create = true; + if(arguments.take("-m", targetFilename)) create = false; + + vector defines; + string define; + while(arguments.take("-d", define)) defines.append(define); + + vector constants; + string constant; + while(arguments.take("-c", constant)) constants.append(constant); + + string symFilename; + arguments.take("-sym", symFilename); + + bool strict = arguments.take("-strict"); + bool benchmark = arguments.take("-benchmark"); + + if(arguments.find("-*")) { + print(stderr, "error: unrecognized argument(s)\n"); + exit(EXIT_FAILURE); + } + + vector sourceFilenames; + for(auto& argument : arguments) sourceFilenames.append(argument); + + clock_t clockStart = clock(); + Bass bass; + bass.target(targetFilename, create); + if(symFilename) { + bass.symFile(symFilename); + } + for(auto& sourceFilename : sourceFilenames) { + bass.source(sourceFilename); + } + for(auto& define : defines) { + auto p = define.split("=", 1L); + bass.define(p(0), p(1)); + } + for(auto& constant : constants) { + auto p = constant.split("=", 1L); + bass.constant(p(0), p(1, "1")); + } + if(!bass.assemble(strict)) { + print(stderr, "bass: assembly failed\n"); + exit(EXIT_FAILURE); + } + clock_t clockFinish = clock(); + if(benchmark) { + print(stderr, "bass: assembled in ", (double)(clockFinish - clockStart) / CLOCKS_PER_SEC, " seconds\n"); + } +} diff --git a/roms/snes-test-roms/bass-untech/bass/bass.hpp b/roms/snes-test-roms/bass-untech/bass/bass.hpp new file mode 100644 index 00000000..9c710c73 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/bass.hpp @@ -0,0 +1,9 @@ +#define Architecture NallArchitecture +#include +using namespace nall; +using string_vector = vector; +#undef Architecture + +#include "core/core.hpp" +#include "architecture/architecture.hpp" +#include "architecture/table/table.hpp" diff --git a/roms/snes-test-roms/bass-untech/bass/core/analyze.cpp b/roms/snes-test-roms/bass-untech/bass/core/analyze.cpp new file mode 100644 index 00000000..9f4fd66b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/analyze.cpp @@ -0,0 +1,134 @@ +auto Bass::analyze() -> bool { + blocks.reset(); + ip = 0; + + while(ip < program.size()) { + Instruction& i = program(ip++); + if(!analyzeInstruction(i)) error("unrecognized directive: ", i.statement); + } + + return true; +} + +auto Bass::analyzeInstruction(Instruction& i) -> bool { + string s = i.statement; + + if(s.match("}") && !blocks) error("} without matching {: ", sourceFilenames[i.fileNumber], ":", i.lineNumber); + + if(s.match("{")) { + blocks.append({ip - 1, "block"}); + i.statement = "block {"; + return true; + } + + if(s.match("}") && blocks.right().type == "block") { + blocks.removeRight(); + i.statement = "} endblock"; + return true; + } + + if(s.match("namespace ?* {")) { + blocks.append({ip - 1, "namespace"}); + return true; + } + + if(s.match("}") && blocks.right().type == "namespace") { + blocks.removeRight(); + i.statement = "} endnamespace"; + return true; + } + + if(s.match("function ?* {")) { + blocks.append({ip - 1, "function"}); + return true; + } + + if(s.match("}") && blocks.right().type == "function") { + blocks.removeRight(); + i.statement = "} endfunction"; + return true; + } + + if(s.match("macro ?*(*) {")) { + blocks.append({ip - 1, "macro"}); + return true; + } + + if(s.match("}") && blocks.right().type == "macro") { + uint rp = blocks.right().ip; + program[rp].ip = ip; + blocks.removeRight(); + i.statement = "} endmacro"; + return true; + } + + if(s.match("inline ?*(*) {")) { + blocks.append({ip - 1, "inline"}); + return true; + } + + if(s.match("}") && blocks.right().type == "inline") { + uint rp = blocks.right().ip; + program[rp].ip = ip; + blocks.removeRight(); + i.statement = "} endinline"; + return true; + } + + if(s.match("?*: {") || s.match("- {") || s.match("+ {")) { + blocks.append({ip - 1, "constant"}); + return true; + } + + if(s.match("}") && blocks.right().type == "constant") { + blocks.removeRight(); + i.statement = "} endconstant"; + return true; + } + + if(s.match("if ?* {")) { + s.trim("if ", " {", 1L); + blocks.append({ip - 1, "if"}); + return true; + } + + if(s.match("} else if ?* {")) { + s.trim("} else if ", " {", 1L); + uint rp = blocks.right().ip; + program[rp].ip = ip - 1; + blocks.right().ip = ip - 1; + return true; + } + + if(s.match("} else {")) { + uint rp = blocks.right().ip; + program[rp].ip = ip - 1; + blocks.right().ip = ip - 1; + return true; + } + + if(s.match("}") && blocks.right().type == "if") { + uint rp = blocks.right().ip; + program[rp].ip = ip - 1; + blocks.removeRight(); + i.statement = "} endif"; + return true; + } + + if(s.match("while ?* {")) { + s.trim("while ", " {", 1L); + blocks.append({ip - 1, "while"}); + return true; + } + + if(s.match("}") && blocks.right().type == "while") { + uint rp = blocks.right().ip; + program[rp].ip = ip; + blocks.removeRight(); + i.statement = "} endwhile"; + i.ip = rp; + return true; + } + + return true; +} diff --git a/roms/snes-test-roms/bass-untech/bass/core/assemble.cpp b/roms/snes-test-roms/bass-untech/bass/core/assemble.cpp new file mode 100644 index 00000000..8a360f5b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/assemble.cpp @@ -0,0 +1,356 @@ +auto Bass::initialize() -> void { + queue.reset(); + scope.reset(); + for(uint n : range(256)) stringTable[n] = n; + endian = Endian::LSB; + origin = 0; + base = 0; + lastLabelCounter = 1; + nextLabelCounter = 1; +} + +auto Bass::assemble(const string& statement) -> bool { + string s = statement; + + if(s.match("block {")) return true; + if(s.match("} endblock")) return true; + + //namespace name { + if(s.match("namespace ?* {")) { + s.trim("namespace ", "{", 1L).strip(); + if(!validate(s)) error("invalid namespace specifier: ", s); + scope.append(s); + return true; + } + + //} + if(s.match("} endnamespace")) { + scope.removeRight(); + return true; + } + + //function name { + if(s.match("function ?* {")) { + s.trim("function ", "{", 1L).strip(); + setConstant(s, pc()); + writeSymbolLabel(pc(), s); + scope.append(s); + return true; + } + + //} + if(s.match("} endfunction")) { + scope.removeRight(); + return true; + } + + //constant name(value) + if(s.match("constant ?*")) { + auto p = s.trimLeft("constant ", 1L).split("=", 1L).strip(); + auto v = evaluate(p(1), Evaluation::Lax); + if(forwardReference) { + setUnknownConstant(p(0)); + } else { + setConstant(p(0), v); + } + return true; + } + + //label: or label: { + if(s.match("?*:") || s.match("?*: {")) { + s.trimRight(" {", 1L); + s.trimRight(":", 1L); + setConstant(s, pc()); + writeSymbolLabel(pc(), s); + return true; + } + + //- or - { + if(s.match("-") || s.match("- {")) { + setConstant({"lastLabel#", lastLabelCounter++}, pc()); + return true; + } + + //+ or + { + if(s.match("+") || s.match("+ {")) { + setConstant({"nextLabel#", nextLabelCounter++}, pc()); + return true; + } + + //} + if(s.match("} endconstant")) { + return true; + } + + //output "filename" [, create] + if(s.match("output ?*")) { + auto p = split(s.trimLeft("output ", 1L)); + if(!p(0).match("\"*\"")) error("missing filename"); + string filename = {filepath(), text(p.take(0))}; + bool create = (p.size() && p(0) == "create"); + target(filename, create); + return true; + } + + //architecture name + if(s.match("architecture ?*")) { + s.trimLeft("architecture ", 1L); + if(s == "none") architecture = new Architecture{*this}; + else { + string location{Path::userData(), "bass/architectures/", s, ".arch"}; + if(!file::exists(location)) location = {Path::program(), "architectures/", s, ".arch"}; + if(!file::exists(location)) error("unknown architecture: ", s); + architecture = new Table{*this, string::read(location)}; + } + return true; + } + + //endian (lsb|msb) + if(s.match("endian ?*")) { + s.trimLeft("endian ", 1L); + if(s == "lsb") { endian = Endian::LSB; return true; } + if(s == "msb") { endian = Endian::MSB; return true; } + error("invalid endian mode"); + } + + //origin offset + if(s.match("origin ?*")) { + s.trimLeft("origin ", 1L); + origin = evaluate(s); + seek(origin); + return true; + } + + //base offset + if(s.match("base ?*")) { + s.trimLeft("base ", 1L); + base = evaluate(s) - origin; + return true; + } + + //enqueue variable [, ...] + if(s.match("enqueue ?*")) { + auto p = split(s.trimLeft("enqueue ", 1L)); + for(auto& t : p) { + if(t == "origin") { + queue.append(origin); + } else if(t == "base") { + queue.append(base); + } else if(t == "pc") { + queue.append(origin); + queue.append(base); + } else { + error("unrecognized enqueue variable: ", t); + } + } + return true; + } + + //dequeue variable [, ...] + if(s.match("dequeue ?*")) { + auto p = split(s.trimLeft("dequeue ", 1L)); + for(auto& t : p) { + if(t == "origin") { + origin = queue.takeRight().natural(); + seek(origin); + } else if(t == "base") { + base = queue.takeRight().integer(); + } else if(t == "pc") { + base = queue.takeRight().integer(); + origin = queue.takeRight().natural(); + seek(origin); + } else { + error("unrecognized dequeue variable: ", t); + } + } + return true; + } + + //copy source, target, length + if(s.match("copy ?*")) { + auto p = split(s.trimLeft("copy ", 1L)); + if(p.size() == 3) { + auto origin = targetFile.offset(); + auto source = evaluate(p(0)); + auto target = evaluate(p(1)); + auto length = evaluate(p(2)); + vector memory; + memory.resize(length); + targetFile.seek(source); + targetFile.read(memory); + targetFile.seek(target); + for(uint offset : range(length)) write(memory[offset]); + targetFile.seek(origin); + return true; + } + } + + //insert [name, ] filename [, offset] [, length] + if(s.match("insert ?*")) { + auto p = split(s.trimLeft("insert ", 1L)); + string name; + if(!p(0).match("\"*\"")) name = p.take(0); + if(!p(0).match("\"*\"")) error("missing filename"); + string filename = {filepath(), text(p.take(0))}; + auto fp = file::open(filename, file::mode::read); + if(!fp) error("file not found: ", filename); + uint offset = p.size() ? evaluate(p.take(0)) : 0; + if(offset > fp.size()) offset = fp.size(); + uint length = p.size() ? evaluate(p.take(0)) : 0; + if(length == 0) length = fp.size() - offset; + if(name) { + setConstant({name}, pc()); + setConstant({name, ".size"}, length); + writeSymbolLabel(pc(), name); + } + fp.seek(offset); + while(!fp.end() && length--) write(fp.read()); + return true; + } + + //delete filename + if(s.match("delete ?*")) { + auto p = split(s.trimLeft("delete ", 1L)); + if(!p(0).match("\"*\"")) error("missing filename"); + string filename = {filepath(), text(p.take(0))}; + if(!file::exists(filename)) { + warning("file not found: ", filename); + return true; + } + if(!file::remove(filename)) { + warning("unable to delete file: ", filename); + return true; + } + return true; + } + + //fill length [, with] + if(s.match("fill ?*")) { + auto p = split(s.trimLeft("fill ", 1L)); + uint length = evaluate(p(0)); + uint byte = evaluate(p(1, "0"), Evaluation::Lax); + while(length--) write(byte); + return true; + } + + //map 'char' [, value] [, length] + if(s.match("map ?*")) { + auto p = split(s.trimLeft("map ", 1L)); + uint8_t index = evaluate(p(0)); + int64_t value = evaluate(p(1, "0")); + int64_t length = evaluate(p(2, "1")); + for(int n : range(length)) { + stringTable[index + n] = value + n; + } + return true; + } + + //d[bwldq] ("string"|variable) [, ...] + uint dataLength = 0; + if(s.beginsWith("db ")) dataLength = 1; + if(s.beginsWith("dw ")) dataLength = 2; + if(s.beginsWith("dl ")) dataLength = 3; + if(s.beginsWith("dd ")) dataLength = 4; + if(s.beginsWith("dq ")) dataLength = 8; + if(dataLength) { + s = slice(s, 3); //remove prefix + auto p = split(s); + for(auto& t : p) { + if(t.match("\"*\"")) { + t = text(t); + for(auto& b : t) write(stringTable[b], dataLength); + } else { + write(evaluate(t, Evaluation::Lax), dataLength); + } + } + return true; + } + + //ds amount + if(s.match("ds ?*")) { + s.trimLeft("ds ", 1L); + origin += evaluate(s); + seek(origin); + return true; + } + + //tracker enable|disable|reset + if(s.match("tracker ?*")) { + s.trimLeft("tracker ", 1L).strip(); + if(s == "enable") { + if(writePhase()) tracker.enable = true; + return true; + } + if(s == "disable") { + if(writePhase()) tracker.enable = false; + return true; + } + if(s == "reset") { + if(writePhase()) tracker.addresses.reset(); + return true; + } + } + + //print ("string"|[cast:]variable) [, ...] + if(s.match("print ?*")) { + if(writePhase()) { + s.trimLeft("print ", 1L).strip(); + print(stderr, assembleString(s)); + } + return true; + } + + //notice ("string"|[cast:]variable) [, ...] + if(s.match("notice ?*")) { + if(writePhase()) { + s.trimLeft("notice ", 1L).strip(); + notice(assembleString(s)); + } + return true; + } + + //warning ("string"|[cast:]variable) [, ...] + if(s.match("warning ?*")) { + if(writePhase()) { + s.trimLeft("warning ", 1L).strip(); + warning(assembleString(s)); + } + return true; + } + + //error ("string"|[cast:]variable) [, ...] + if(s.match("error ?*")) { + if(writePhase()) { + s.trimLeft("error ", 1L).strip(); + error(assembleString(s)); + } + return true; + } + + charactersUseMap = true; + bool result = architecture->assemble(statement); + charactersUseMap = false; + return result; +} + +auto Bass::assembleString(const string& parameters) -> string { + string result; + auto p = split(parameters); + for(auto& t : p) { + if(t.match("\"*\"")) { + result.append(text(t)); + } else if(t.match("binary:?*")) { + t.trimLeft("binary:", 1L); + result.append(binary(evaluate(t))); + } else if(t.match("hex:?*")) { + t.trimLeft("hex:", 1L); + result.append(hex(evaluate(t))); + } else if(t.match("char:?*")) { + t.trimLeft("char:", 1L); + result.append((char)evaluate(t)); + } else { + result.append(evaluate(t)); + } + } + return result; +} diff --git a/roms/snes-test-roms/bass-untech/bass/core/core.cpp b/roms/snes-test-roms/bass-untech/bass/core/core.cpp new file mode 100644 index 00000000..ee6e6279 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/core.cpp @@ -0,0 +1,197 @@ +#include "evaluate.cpp" +#include "analyze.cpp" +#include "execute.cpp" +#include "assemble.cpp" +#include "utility.cpp" + +auto Bass::target(const string& filename, bool create) -> bool { + if(targetFile) targetFile.close(); + if(!filename) return true; + + //cannot modify a file unless it exists + if(!file::exists(filename)) create = true; + + if(!targetFile.open(filename, create ? file::mode::write : file::mode::modify)) { + print(stderr, "warning: unable to open target file: ", filename, "\n"); + return false; + } + + tracker.addresses.reset(); + return true; +} + +auto Bass::symFile(const string& filename) -> bool { + if(symbolFile) symbolFile.close(); + if(!filename) return true; + + if(!symbolFile.open(filename, file::mode::write)) { + print(stderr, "warning: unable to open symbol file: ", filename, "\n"); + return false; + } + + return true; +} + +auto Bass::source(const string& filename) -> bool { + if(!file::exists(filename)) { + print(stderr, "warning: source file not found: ", filename, "\n"); + return false; + } + + uint fileNumber = sourceFilenames.size(); + sourceFilenames.append(filename); + + string data = file::read(filename); + data.transform("\t\r", " "); + + auto lines = data.split("\n"); + for(uint lineNumber : range(lines.size())) { + //remove single-line comments + if(auto position = lines[lineNumber].qfind("//")) { + lines[lineNumber].resize(position()); + } + + //allow multiple statements per line, separated by ';' + auto blocks = lines[lineNumber].qsplit(";").strip(); + for(uint blockNumber : range(blocks.size())) { + string statement = blocks[blockNumber]; + strip(statement); + if(!statement) continue; + + if(statement.match("include \"?*\"")) { + statement.trimLeft("include ", 1L).strip(); + source({Location::path(filename), text(statement)}); + } else { + Instruction instruction; + instruction.statement = statement; + instruction.fileNumber = fileNumber; + instruction.lineNumber = 1 + lineNumber; + instruction.blockNumber = 1 + blockNumber; + program.append(instruction); + } + } + } + + return true; +} + +auto Bass::define(const string& name, const string& value) -> void { + defines.insert({name, {}, value}); +} + +auto Bass::constant(const string& name, const string& value) -> void { + try { + constantNames.insert(name); + constants.insert({name, evaluate(value, Evaluation::Strict)}); + } catch(...) { + } +} + +auto Bass::assemble(bool strict) -> bool { + this->strict = strict; + + try { + phase = Phase::Analyze; + analyze(); + + phase = Phase::Query; + architecture = new Architecture{*this}; + execute(); + + phase = Phase::Write; + architecture = new Architecture{*this}; + execute(); + } catch(...) { + return false; + } + + return true; +} + +//internal + +auto Bass::pc() const -> uint { + return origin + base; +} + +auto Bass::seek(uint offset) -> void { + if(!targetFile) return; + if(writePhase()) targetFile.seek(offset); +} + +auto Bass::track(uint length) -> void { + if(!tracker.enable) return; + uint64_t address = targetFile.offset(); + for(auto n : range(length)) { + if(tracker.addresses.find(address + n)) { + error("overwrite detected at address 0x", hex(address + n), " [0x", hex(base + address + n), "]"); + } + tracker.addresses.insert(address + n); + } +} + +auto Bass::write(uint64_t data, uint length) -> void { + if(writePhase()) { + if(targetFile) { + track(length); + if(endian == Endian::LSB) targetFile.writel(data, length); + if(endian == Endian::MSB) targetFile.writem(data, length); + } else if(!isatty(fileno(stdout))) { + if(endian == Endian::LSB) for(uint n : range(length)) fputc(data >> n * 8, stdout); + if(endian == Endian::MSB) for(uint n : reverse(range(length))) fputc(data >> n * 8, stdout); + } + } + origin += length; +} + +auto Bass::writeSymbolLabel(int64_t value, const string& name) -> void { + if(writePhase()) { + if(symbolFile) { + string scopedName = {scope.merge("."), scope ? "." : "", name}; + symbolFile.print(hex(value, 8), ' ', scopedName, '\n'); + } + } +} + +auto Bass::printInstruction() -> void { + if(activeInstruction) { + auto& i = *activeInstruction; + print(stderr, sourceFilenames[i.fileNumber], ":", i.lineNumber, ":", i.blockNumber, ": ", i.statement, "\n"); + } +} + +auto Bass::printInstructionStack() -> void { + printInstruction(); + + for(const auto& frame : reverse(frames)) { + if(frame.ip > 0 && frame.ip <= program.size()) { + auto& i = program[frame.ip - 1]; + print(stderr, " ", sourceFilenames[i.fileNumber], ":", i.lineNumber, ":", i.blockNumber, ": ", i.statement, "\n"); + } + } +} + +template auto Bass::notice(P&&... p) -> void { + string s{forward

(p)...}; + print(stderr, terminal::color::gray("notice: "), s, "\n"); + printInstructionStack(); +} + +template auto Bass::warning(P&&... p) -> void { + string s{forward

(p)...}; + print(stderr, terminal::color::yellow("warning: "), s, "\n"); + printInstructionStack(); + + if(!strict) return; + struct BassWarning {}; + throw BassWarning(); +} + +template auto Bass::error(P&&... p) -> void { + string s{forward

(p)...}; + print(stderr, terminal::color::red("error: "), s, "\n"); + printInstructionStack(); + + struct BassError {}; + throw BassError(); +} diff --git a/roms/snes-test-roms/bass-untech/bass/core/core.hpp b/roms/snes-test-roms/bass-untech/bass/core/core.hpp new file mode 100644 index 00000000..2cedcf60 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/core.hpp @@ -0,0 +1,215 @@ +struct Architecture; + +struct Bass { + auto target(const string& filename, bool create) -> bool; + auto symFile(const string& filename) -> bool; + auto source(const string& filename) -> bool; + auto define(const string& name, const string& value) -> void; + auto constant(const string& name, const string& value) -> void; + auto assemble(bool strict = false) -> bool; + + enum class Phase : uint { Analyze, Query, Write }; + enum class Endian : uint { LSB, MSB }; + enum class Evaluation : uint { Strict = 0, Lax = 1 }; //strict mode disallows forward-declaration of constants + + struct Instruction { + string statement; + uint ip; + + uint fileNumber; + uint lineNumber; + uint blockNumber; + }; + + struct Macro { + Macro() {} + Macro(const string& name) : name(name) {} + Macro(const string& name, const string_vector& parameters, uint ip, bool inlined) : name(name), parameters(parameters), ip(ip), inlined(inlined) {} + + auto hash() const -> uint { return name.hash(); } + auto operator==(const Macro& source) const -> bool { return name == source.name; } + auto operator< (const Macro& source) const -> bool { return name < source.name; } + + string name; + string_vector parameters; + uint ip; + bool inlined; + }; + + struct Define { + Define() {} + Define(const string& name) : name(name) {} + Define(const string& name, const string_vector& parameters, const string& value) : name(name), parameters(parameters), value(value) {} + + auto hash() const -> uint { return name.hash(); } + auto operator==(const Define& source) const -> bool { return name == source.name; } + auto operator< (const Define& source) const -> bool { return name < source.name; } + + string name; + string_vector parameters; + string value; + }; + + using Expression = Define; //Define and Expression structures are identical + + struct Variable { + Variable() {} + Variable(const string& name) : name(name) {} + Variable(const string& name, int64_t value) : name(name), value(value) {} + + auto hash() const -> uint { return name.hash(); } + auto operator==(const Variable& source) const -> bool { return name == source.name; } + auto operator< (const Variable& source) const -> bool { return name < source.name; } + + string name; + int64_t value; + }; + + using Constant = Variable; //Variable and Constant structures are identical + + struct Array { + Array() {} + Array(const string& name) : name(name) {} + Array(const string& name, vector values) : name(name), values(values) {} + + auto hash() const -> uint { return name.hash(); } + auto operator==(const Array& source) const -> bool { return name == source.name; } + auto operator< (const Array& source) const -> bool { return name < source.name; } + + string name; + vector values; + }; + + struct Frame { + enum class Level : uint { + Inline, //use deepest frame (eg for parameters) + Active, //use deepest non-inline frame + Parent, //use second-deepest non-inline frame + Global, //use root frame + }; + + uint ip; + bool inlined; + + hashset macros; + hashset defines; + hashset expressions; + hashset variables; + hashset arrays; + }; + + struct Block { + uint ip; + string type; + }; + + struct Tracker { + bool enable = false; + set addresses; + }; + +protected: + auto analyzePhase() const -> bool { return phase == Phase::Analyze; } + auto queryPhase() const -> bool { return phase == Phase::Query; } + auto writePhase() const -> bool { return phase == Phase::Write; } + + //core.cpp + auto pc() const -> uint; + auto seek(uint offset) -> void; + auto track(uint length) -> void; + auto write(uint64_t data, uint length = 1) -> void; + auto writeSymbolLabel(int64_t value, const string& name) -> void; + + auto printInstruction() -> void; + auto printInstructionStack() -> void; + template auto notice(P&&... p) -> void; + template auto warning(P&&... p) -> void; + template auto error(P&&... p) -> void; + + //evaluate.cpp + auto evaluate(const string& expression, Evaluation mode = Evaluation::Strict) -> int64_t; + auto evaluate(Eval::Node* node, Evaluation mode) -> int64_t; + auto quantifyParameters(Eval::Node* node) -> int64_t; + auto evaluateParameters(Eval::Node* node, Evaluation mode) -> vector; + auto evaluateExpression(Eval::Node* node, Evaluation mode) -> int64_t; + auto evaluateString(Eval::Node* node) -> string; + auto evaluateLiteral(Eval::Node* node, Evaluation mode) -> int64_t; + auto evaluateSubscript(Eval::Node* node, Evaluation mode) -> int64_t; + auto evaluateAssign(Eval::Node* node, Evaluation mode) -> int64_t; + + //analyze.cpp + auto analyze() -> bool; + auto analyzeInstruction(Instruction& instruction) -> bool; + + //execute.cpp + auto execute() -> bool; + auto executeInstruction(Instruction& instruction) -> bool; + + //assemble.cpp + auto initialize() -> void; + auto assemble(const string& statement) -> bool; + auto assembleString(const string& parameters) -> string; + + //utility.cpp + auto setMacro(const string& name, const string_vector& parameters, uint ip, bool inlined, Frame::Level level) -> void; + auto findMacro(const string& name) -> maybe; + + auto setDefine(const string& name, const string_vector& parameters, const string& value, Frame::Level level) -> void; + auto findDefine(const string& name) -> maybe; + + auto setExpression(const string& name, const string_vector& parameters, const string& value, Frame::Level level) -> void; + auto findExpression(const string& name) -> maybe; + + auto setVariable(const string& name, int64_t value, Frame::Level level) -> void; + auto findVariable(const string& name) -> maybe; + + auto setUnknownConstant(const string& name) -> void; + auto setConstant(const string& name, int64_t value) -> void; + auto findConstant(const string& name) -> maybe; + auto findConstantName(const string& name) -> maybe; + + auto setArray(const string& name, const vector& values, Frame::Level level) -> void; + auto findArray(const string& name) -> maybe; + + auto evaluateDefines(string& statement) -> void; + + auto filepath() -> string; + auto split(const string& s) -> string_vector; + auto strip(string& s) -> void; + auto validate(const string& s) -> bool; + auto text(string s) -> string; + auto character(const string& s) -> int64_t; + + //internal state + Instruction* activeInstruction = nullptr; //used by notice, warning, error + vector program; //parsed source code statements + vector blocks; //track the start and end of blocks + set defines; //defines specified on the terminal + hashset constantNames; //set of constant names, including those with unknown values + hashset constants; //constants support forward-declaration + vector frames; //macros, defines and variables do not + vector conditionals; //track conditional matching + string_vector queue; //track enqueue, dequeue directives + string_vector scope; //track scope recursion + int64_t stringTable[256]; //overrides for d[bwldq] text strings + Phase phase; //phase of assembly + Endian endian = Endian::LSB; //used for multi-byte writes (d[bwldq], etc) + Tracker tracker; //used to track writes to detect overwrites + uint macroInvocationCounter; //used for {#} support + uint ip = 0; //instruction pointer into program + uint origin = 0; //file offset + int base = 0; //file offset to memory map displacement + uint lastLabelCounter = 1; //- instance counter + uint nextLabelCounter = 1; //+ instance counter + bool charactersUseMap = false; //0 = '*' parses as ASCII; 1 = '*' uses stringTable[] + bool strict = false; //upgrade warnings to errors when true + + bool forwardReference = false; //true if the last evaluate(string) call contained a forward reference + + file_buffer targetFile; + file_buffer symbolFile; + string_vector sourceFilenames; + + shared_pointer architecture; + friend class Architecture; +}; diff --git a/roms/snes-test-roms/bass-untech/bass/core/evaluate.cpp b/roms/snes-test-roms/bass-untech/bass/core/evaluate.cpp new file mode 100644 index 00000000..7d8ca459 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/evaluate.cpp @@ -0,0 +1,210 @@ +auto Bass::evaluate(const string& expression, Evaluation mode) -> int64_t { + forwardReference = false; + + maybe name; + if(expression == "--") name = {"lastLabel#", lastLabelCounter - 2}; + if(expression == "-" ) name = {"lastLabel#", lastLabelCounter - 1}; + if(expression == "+" ) name = {"nextLabel#", nextLabelCounter + 0}; + if(expression == "++") name = {"nextLabel#", nextLabelCounter + 1}; + if(name) { + if(auto constant = findConstant({name()})) return constant().value; + if(queryPhase()) return pc(); + error("relative label not declared"); + } + + Eval::Node* node = nullptr; + try { + node = Eval::parse(expression); + } catch(const char* reason) { + error("malformed expression: ", expression, " [", reason, "]"); + } catch(...) { + error("malformed expression: ", expression); + } + return evaluate(node, mode); +} + +auto Bass::evaluate(Eval::Node* node, Evaluation mode) -> int64_t { + #define p(n) evaluate(node->link[n], mode) + + switch(node->type) { + case Eval::Node::Type::Null: return 0; //empty expressions + case Eval::Node::Type::Function: return evaluateExpression(node, mode); + case Eval::Node::Type::Literal: return evaluateLiteral(node, mode); + case Eval::Node::Type::Subscript: return evaluateSubscript(node, mode); + case Eval::Node::Type::LogicalNot: return !p(0); + case Eval::Node::Type::BitwiseNot: return ~p(0); + case Eval::Node::Type::Positive: return +p(0); + case Eval::Node::Type::Negative: return -p(0); + case Eval::Node::Type::Multiply: return p(0) * p(1); + case Eval::Node::Type::Divide: return p(0) / p(1); + case Eval::Node::Type::Modulo: return p(0) % p(1); + case Eval::Node::Type::Add: return p(0) + p(1); + case Eval::Node::Type::Subtract: return p(0) - p(1); + case Eval::Node::Type::ShiftLeft: return p(0) << p(1); + case Eval::Node::Type::ShiftRight: return p(0) >> p(1); + case Eval::Node::Type::BitwiseAnd: return p(0) & p(1); + case Eval::Node::Type::BitwiseOr: return p(0) | p(1); + case Eval::Node::Type::BitwiseXor: return p(0) ^ p(1); + case Eval::Node::Type::Equal: return p(0) == p(1); + case Eval::Node::Type::NotEqual: return p(0) != p(1); + case Eval::Node::Type::LessThanEqual: return p(0) <= p(1); + case Eval::Node::Type::GreaterThanEqual: return p(0) >= p(1); + case Eval::Node::Type::LessThan: return p(0) < p(1); + case Eval::Node::Type::GreaterThan: return p(0) > p(1); + case Eval::Node::Type::LogicalAnd: return p(0) ? p(1) : 0; + case Eval::Node::Type::LogicalOr: return !p(0) ? p(1) : 1; + case Eval::Node::Type::Condition: return p(0) ? p(1) : p(2); + case Eval::Node::Type::Assign: return evaluateAssign(node, mode); + } + + #undef p + error("unsupported operator"); + return 0; +} + +//calculates the number of parameters to a function without evaluating its arguments yet +auto Bass::quantifyParameters(Eval::Node* node) -> int64_t { + if(node->type == Eval::Node::Type::Null) return 0; + if(node->type == Eval::Node::Type::Separator) return node->link.size(); + return 1; //any other type here signifies one argument +} + +auto Bass::evaluateParameters(Eval::Node* node, Evaluation mode) -> vector { + vector result; + if(node->type == Eval::Node::Type::Null) return result; + if(node->type != Eval::Node::Type::Separator) { result.append(evaluate(node, mode)); return result; } + for(auto& link : node->link) result.append(evaluate(link, mode)); + return result; +} + +auto Bass::evaluateExpression(Eval::Node* node, Evaluation mode) -> int64_t { + string name = node->link[0]->literal; + if(auto parameters = quantifyParameters(node->link[1])) name.append("#", parameters); + + if(name == "array.size#1") { + string s = evaluateString(node->link[1]); + if(auto array = findArray(s)) { + return array->values.size(); + } + error("unrecognized array: ", s); + return 0; + } + if(name == "array.sort#1") { + string s = evaluateString(node->link[1]); + if(auto array = findArray(s)) { + array->values.sort(); + return 0; + } + error("unrecognized array: ", s); + return 0; + } + if(name == "assert#1") { + int64_t result = evaluate(node->link[1], mode); + if(result == 0) error("assertion failed"); + return 0; + } + if(name == "file.size#1") { + string filename = evaluateString(node->link[1]).trim("\"", "\"", 1L); + string location = {filepath(), filename}; + if(file::exists(location)) return file::size(location); + error("file not found: ", filename); + return 0; + } + if(name == "file.exists#1") { + string filename = evaluateString(node->link[1]).trim("\"", "\"", 1L); + string location = {filepath(), filename}; + return file::exists(location); + } + if(name == "read#1") { + if(!targetFile) error("no target file open for reading"); + int64_t address = evaluate(node->link[1], mode); + auto origin = targetFile.offset(); + targetFile.seek(address); + uint8_t data = targetFile.read(); + targetFile.seek(origin); + return data; + } + if(name == "origin") return origin; + if(name == "base") return base; + if(name == "pc") return pc(); + + if(auto expression = findExpression(name)) { + auto parameters = evaluateParameters(node->link[1], mode); + if(parameters) frames.append({0, true}); + for(auto n : range(parameters.size())) { + setVariable(expression().parameters(n), evaluate(parameters(n)), Frame::Level::Inline); + } + auto result = evaluate(expression().value); + if(parameters) frames.removeRight(); + return result; + } + + error("unrecognized expression: ", name); + return 0; +} + +//bass' evaluate() only returns int64_t types. +//this function is used to parse string arguments while performing trivial string concatenation +//eg "foo" ~ "bar" => "foobar" +auto Bass::evaluateString(Eval::Node* node) -> string { + if(node->type == Eval::Node::Type::Literal) return node->literal; + if(node->type == Eval::Node::Type::Concatenate) { + string lhs = evaluateString(node->link[0]).trim("\"", "\"", 1L); + string rhs = evaluateString(node->link[1]).trim("\"", "\"", 1L); + return {"\"", lhs, rhs, "\""}; + }; + error("unrecognized string expression"); + return {}; +} + +auto Bass::evaluateLiteral(Eval::Node* node, Evaluation mode) -> int64_t { + string& s = node->literal; + + if(s[0] == '0' && s[1] == 'b') return toBinary(s); + if(s[0] == '0' && s[1] == 'o') return toOctal(s); + if(s[0] == '0' && s[1] == 'x') return toHex(s); + if(s[0] >= '0' && s[0] <= '9') return toInteger(s); + if(s[0] == '%') return toBinary(s); + if(s[0] == '$') return toHex(s); + if(s.match("'?*'")) return character(s); + + if(auto variable = findVariable(s)) return variable().value; + if(auto constant = findConstant(s)) return constant().value; + + forwardReference = true; + if(mode == Evaluation::Lax && queryPhase()) return pc(); + + if(auto constantName = findConstantName(s)) { + error("constant has unknown value: ", constantName()); + } else { + error("unrecognized variable: ", s); + } + return 0; +} + +auto Bass::evaluateSubscript(Eval::Node* node, Evaluation mode) -> int64_t { + string& s = node->link[0]->literal; + + if(auto array = findArray(s)) { + auto index = evaluate(node->link[1], mode); + if(index >= array->values.size()) { + error("array subscript out of bounds: ", index, " >= ", array->values.size()); + } + return array->values[index]; + } + + error("unrecognized array: ", s); + return 0; +} + +auto Bass::evaluateAssign(Eval::Node* node, Evaluation mode) -> int64_t { + string& s = node->link[0]->literal; + + if(auto variable = findVariable(s)) { + variable().value = evaluate(node->link[1], mode); + return variable().value; + } + + error("unrecognized variable assignment: ", s); + return 0; +} diff --git a/roms/snes-test-roms/bass-untech/bass/core/execute.cpp b/roms/snes-test-roms/bass-untech/bass/core/execute.cpp new file mode 100644 index 00000000..9246c64f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/execute.cpp @@ -0,0 +1,211 @@ +auto Bass::execute() -> bool { + frames.reset(); + conditionals.reset(); + ip = 0; + macroInvocationCounter = 0; + + initialize(); + + frames.append({0, false}); + for(auto& define : defines) { + setDefine(define.name, {}, define.value, Frame::Level::Inline); + } + + while(ip < program.size()) { + Instruction& i = program(ip++); + if(!executeInstruction(i)) error("unrecognized directive: ", i.statement); + } + + frames.removeRight(); + return true; +} + +auto Bass::executeInstruction(Instruction& i) -> bool { + activeInstruction = &i; + string s = i.statement; + evaluateDefines(s); + + bool global = s.beginsWith("global "); + bool parent = s.beginsWith("parent "); + if(global && parent) error("multiple frame specifiers are not allowed"); + + Frame::Level level = Frame::Level::Active; + if(global) s.trimLeft("global ", 1L), level = Frame::Level::Global; + if(parent) s.trimLeft("parent ", 1L), level = Frame::Level::Parent; + + if(s.match("macro ?*(*) {")) { + bool inlined = false; + s.trim("macro ", ") {", 1L); + auto p = s.split("(", 1L).strip(); + auto parameters = split(p(1)); + setMacro(p(0), parameters, ip, inlined, level); + ip = i.ip; + return true; + } + + if(s.match("inline ?*(*) {")) { + bool inlined = true; + s.trim("inline ", ") {", 1L); + auto p = s.split("(", 1L).strip(); + auto parameters = split(p(1)); + setMacro(p(0), parameters, ip, inlined, level); + ip = i.ip; + return true; + } + + if(s.match("define ?*(*)*")) { + auto e = s.trimLeft("define ", 1L).split("=", 1L).strip(); + auto p = e(0).trimRight(")", 1L).split("(", 1L).strip(); + auto parameters = split(p(1)); + setDefine(p(0), parameters, e(1), level); + return true; + } + + if(s.match("define ?*")) { + auto p = s.trimLeft("define ", 1L).split("=", 1L).strip(); + setDefine(p(0), {}, p(1), level); + return true; + } + + if(s.match("evaluate ?*")) { + auto p = s.trimLeft("evaluate ", 1L).split("=", 1L).strip(); + setDefine(p(0), {}, evaluate(p(1)), level); + return true; + } + + if(s.match("expression ?*(*)*")) { + auto e = s.trimLeft("expression ", 1L).split("=", 1L).strip(); + auto p = e(0).trimRight(")", 1L).split("(", 1L).strip(); + auto parameters = split(p(1)); + setExpression(p(0), parameters, e(1), level); + return true; + } + + if(s.match("variable ?*")) { + auto p = s.trimLeft("variable ", 1L).split("=", 1L).strip(); + setVariable(p(0), evaluate(p(1)), level); + return true; + } + + if(s.match("array[?*] ?*")) { + auto a = s.trimLeft("array[", 1L).split("]", 1L); + auto size = evaluate(a(0)); + auto p = a(1).split("=", 1L).strip(); + auto parameters = split(p(1)); + vector values; + for(auto& parameter : parameters) values.append(evaluate(parameter)); + if(values.size() > size) error("too many array elements: ", values.size(), " > ", size); + values.resize(size); //zero-initialize additional elements + setArray(p(0), values, level); + return true; + } + + //evaluate() will evaluate array[index] to a value prior to evaluating = + //as a result, array[index] assignment must be manually captured early + if(s.match("?*[?*] = ?*")) { + auto a = s.split("[", 1L).strip(); + auto b = a(1).split("]", 1L).strip(); + auto c = b(1).split("=", 1L).strip(); + if(auto array = findArray(a(0))) { + auto index = evaluate(b(0)); + if(index >= array->values.size()) error("array subscript out of bounds: ", index, " >= ", array->values.size()); + auto value = evaluate(c(1)); + array->values[index] = value; + return true; + } + //fallthrough: this may have matched another expression that wasn't an array[index] assignment + } + + if(global || parent) error("invalid frame specifier"); + + if(s.match("if ?* {")) { + s.trim("if ", " {", 1L).strip(); + bool match = evaluate(s, Evaluation::Strict); + conditionals.append(match); + if(match == false) { + ip = i.ip; + } + return true; + } + + if(s.match("} else if ?* {")) { + if(conditionals.right()) { + ip = i.ip; + } else { + s.trim("} else if ", " {", 1L).strip(); + bool match = evaluate(s, Evaluation::Strict); + conditionals.right() = match; + if(match == false) { + ip = i.ip; + } + } + return true; + } + + if(s.match("} else {")) { + if(conditionals.right()) { + ip = i.ip; + } else { + conditionals.right() = true; + } + return true; + } + + if(s.match("} endif")) { + conditionals.removeRight(); + return true; + } + + if(s.match("while ?* {")) { + s.trim("while ", " {", 1L).strip(); + bool match = evaluate(s, Evaluation::Strict); + if(match == false) ip = i.ip; + return true; + } + + if(s.match("} endwhile")) { + ip = i.ip; + return true; + } + + if(s.match("?*(*)")) { + auto p = string{s}.trimRight(")", 1L).split("(", 1L).strip(); + auto name = p(0); + auto parameters = split(p(1)); + if(parameters) name.append("#", parameters.size()); + if(auto macro = findMacro({name})) { + frames.append({ip, macro().inlined}); + if(!frames.right().inlined) scope.append(p(0)); + + setDefine("#", {}, {"_", macroInvocationCounter++, "_"}, Frame::Level::Inline); + for(uint n : range(parameters.size())) { + auto p = macro().parameters(n).split(" ", 1L).strip(); + if(p.size() == 1) p.prepend("define"); + + if(0); + else if(p[0] == "define") setDefine(p[1], {}, parameters(n), Frame::Level::Inline); + else if(p[0] == "string") setDefine(p[1], {}, text(parameters(n)), Frame::Level::Inline); + else if(p[0] == "evaluate") setDefine(p[1], {}, evaluate(parameters(n)), Frame::Level::Inline); + else if(p[0] == "variable") setVariable(p[1], evaluate(parameters(n)), Frame::Level::Inline); + else error("unsupported parameter type: ", p[0]); + } + + ip = macro().ip; + return true; + } + } + + if(s.match("} endmacro") || s.match("} endinline")) { + ip = frames.right().ip; + if(!frames.right().inlined) scope.removeRight(); + frames.removeRight(); + return true; + } + + if(assemble(s)) { + return true; + } + + evaluate(s); + return true; +} diff --git a/roms/snes-test-roms/bass-untech/bass/core/utility.cpp b/roms/snes-test-roms/bass-untech/bass/core/utility.cpp new file mode 100644 index 00000000..f782af47 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/core/utility.cpp @@ -0,0 +1,396 @@ +auto Bass::setMacro(const string& name, const string_vector& parameters, uint ip, bool inlined, Frame::Level level) -> void { + if(!validate(name)) error("invalid macro identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + if(parameters) scopedName.append("#", parameters.size()); + + for(int n : reverse(range(frames.size()))) { + if(level != Frame::Level::Inline) { + if(frames[n].inlined) continue; + if(level == Frame::Level::Global && n) { continue; } + if(level == Frame::Level::Parent && n) { level = Frame::Level::Active; continue; } + } + + auto& macros = frames[n].macros; + if(auto macro = macros.find({scopedName})) { + macro().parameters = parameters; + macro().ip = ip; + macro().inlined = inlined; + } else { + macros.insert({scopedName, parameters, ip, inlined}); + } + + return; + } +} + +auto Bass::findMacro(const string& name) -> maybe { + for(int n : reverse(range(frames.size()))) { + auto& macros = frames[n].macros; + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto macro = macros.find({scopedName})) { + return macro(); + } + if(!s) break; + s.removeRight(); + } + } + + return nothing; +} + +auto Bass::setDefine(const string& name, const string_vector& parameters, const string& value, Frame::Level level) -> void { + if(!validate(name)) error("invalid define identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + if(parameters) scopedName.append("#", parameters.size()); + + for(int n : reverse(range(frames.size()))) { + if(level != Frame::Level::Inline) { + if(frames[n].inlined) continue; + if(level == Frame::Level::Global && n) { continue; } + if(level == Frame::Level::Parent && n) { level = Frame::Level::Active; continue; } + } + + auto& defines = frames[n].defines; + if(auto define = defines.find({scopedName})) { + define().parameters = parameters; + define().value = value; + } else { + defines.insert({scopedName, parameters, value}); + } + + return; + } +} + +auto Bass::findDefine(const string& name) -> maybe { + for(int n : reverse(range(frames.size()))) { + auto& defines = frames[n].defines; + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto define = defines.find({scopedName})) { + return define(); + } + if(!s) break; + s.removeRight(); + } + } + + return nothing; +} + +auto Bass::setExpression(const string& name, const string_vector& parameters, const string& value, Frame::Level level) -> void { + if(!validate(name)) error("invalid expression identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + if(parameters) scopedName.append("#", parameters.size()); + + for(int n : reverse(range(frames.size()))) { + if(level != Frame::Level::Inline) { + if(frames[n].inlined) continue; + if(level == Frame::Level::Global && n) { continue; } + if(level == Frame::Level::Parent && n) { level = Frame::Level::Active; continue; } + } + + auto& expressions = frames[n].expressions; + if(auto expression = expressions.find({scopedName})) { + expression().parameters = parameters; + expression().value = value; + } else { + expressions.insert({scopedName, parameters, value}); + } + + return; + } +} + +auto Bass::findExpression(const string& name) -> maybe { + for(int n : reverse(range(frames.size()))) { + auto& expressions = frames[n].expressions; + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto expression = expressions.find({scopedName})) { + return expression(); + } + if(!s) break; + s.removeRight(); + } + } + + return nothing; +} + +auto Bass::setVariable(const string& name, int64_t value, Frame::Level level) -> void { + if(!validate(name)) error("invalid variable identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + + for(int n : reverse(range(frames.size()))) { + if(level != Frame::Level::Inline) { + if(frames[n].inlined) continue; + if(level == Frame::Level::Global && n) { continue; } + if(level == Frame::Level::Parent && n) { level = Frame::Level::Active; continue; } + } + + auto& variables = frames[n].variables; + if(auto variable = variables.find({scopedName})) { + variable().value = value; + } else { + variables.insert({scopedName, value}); + } + + return; + } +} + +auto Bass::findVariable(const string& name) -> maybe { + for(int n : reverse(range(frames.size()))) { + auto& variables = frames[n].variables; + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto variable = variables.find({scopedName})) { + return variable(); + } + if(!s) break; + s.removeRight(); + } + } + + return nothing; +} + +auto Bass::setUnknownConstant(const string& name) -> void { + if(!validate(name)) error("invalid constant identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + + if(writePhase()) error("constant value unknown at write phase: ", scopedName); + + if(constantNames.find(scopedName)) error("constant cannot be modified: ", scopedName); + constantNames.insert(scopedName); +} + +auto Bass::setConstant(const string& name, int64_t value) -> void { + if(!validate(name)) error("invalid constant identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + + if(auto constant = constants.find({scopedName})) { + if(queryPhase()) error("constant cannot be modified: ", scopedName); + if(constant().value != value) error("constant value has changed between the query and write phases: ", scopedName); + } else { + constantNames.insert(scopedName); + constants.insert({scopedName, value}); + } +} + +auto Bass::findConstant(const string& name) -> maybe { + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto constant = constants.find({scopedName})) { + return constant(); + } + if(!s) break; + s.removeRight(); + } + + return nothing; +} + +auto Bass::findConstantName(const string& name) -> maybe { + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto constant = constantNames.find({scopedName})) { + return constant(); + } + if(!s) break; + s.removeRight(); + } + + return nothing; +} + +auto Bass::setArray(const string& name, const vector& values, Frame::Level level) -> void { + if(!validate(name)) error("invalid array identifier: ", name); + string scopedName = {scope.merge("."), scope ? "." : "", name}; + + for(int n : reverse(range(frames.size()))) { + if(level != Frame::Level::Inline) { + if(frames[n].inlined) continue; + if(level == Frame::Level::Global && n) { continue; } + if(level == Frame::Level::Parent && n) { level = Frame::Level::Active; continue; } + } + + auto& arrays = frames[n].arrays; + if(auto array = arrays.find({scopedName})) { + array().values = values; + } else { + arrays.insert({scopedName, values}); + } + + return; + } +} + +auto Bass::findArray(const string& name) -> maybe { + for(int n : reverse(range(frames.size()))) { + auto& arrays = frames[n].arrays; + auto s = scope; + while(true) { + string scopedName = {s.merge("."), s ? "." : "", name}; + if(auto array = arrays.find({scopedName})) { + return array(); + } + if(!s) break; + s.removeRight(); + } + } + + return nothing; +} + +auto Bass::evaluateDefines(string& s) -> void { + for(int x = s.size() - 1, y = -1; x >= 0; x--) { + if(s[x] == '}') y = x; + if(s[x] == '{' && y > x) { + string name = slice(s, x + 1, y - x - 1); + + if(name.match("defined ?*")) { + name.trimLeft("defined ", 1L).strip(); + s = {slice(s, 0, x), findDefine(name) ? 1 : 0, slice(s, y + 1)}; + return evaluateDefines(s); + } + + string_vector parameters; + if(name.match("?*(*)")) { + auto p = name.trimRight(")", 1L).split("(", 1L).strip(); + name = p(0); + parameters = split(p(1)); + } + if(parameters) name.append("#", parameters.size()); + + if(auto define = findDefine(name)) { + if(parameters) frames.append({0, true}); + for(auto n : range(parameters.size())) { + auto p = define().parameters(n).split(" ", 1L).strip(); + if(p.size() == 1) p.prepend("define"); + + if(0); + else if(p[0] == "define") setDefine(p[1], {}, parameters(n), Frame::Level::Inline); + else if(p[0] == "string") setDefine(p[1], {}, text(parameters(n)), Frame::Level::Inline); + else if(p[0] == "evaluate") setDefine(p[1], {}, evaluate(parameters(n)), Frame::Level::Inline); + else error("unsupported parameter type: ", p[0]); + } + auto value = define().value; + evaluateDefines(value); + s = {slice(s, 0, x), value, slice(s, y + 1)}; + if(parameters) frames.removeRight(); + return evaluateDefines(s); + } + } + } +} + +auto Bass::filepath() -> string { + return Location::path(sourceFilenames[activeInstruction->fileNumber]); +} + +//split argument list by commas, being aware of parenthesis depth and quotes +auto Bass::split(const string& s) -> string_vector { + string_vector result; + uint offset = 0; + char quoted = 0; + uint depth = 0; + bool escaped = 0; + for(uint n : range(s.size())) { + if(s[n] == '\\' && quoted) { + escaped = 1; + continue; + } + if(escaped) { + escaped = 0; + continue; + } + if(!quoted) { + if(s[n] == '\"' || s[n] == '\'') quoted = s[n]; + } else if(quoted == s[n]) { + quoted = 0; + } + if(s[n] == '(' && !quoted) depth++; + if(s[n] == ')' && !quoted) depth--; + if(s[n] == ',' && !quoted && !depth) { + result.append(slice(s, offset, n - offset)); + offset = n + 1; + } + } + if(offset < s.size()) result.append(slice(s, offset, s.size() - offset)); + if(quoted) error("mismatched quotes in expression"); + if(depth) error("mismatched parentheses in expression"); + return result.strip(); +} + +//reduce all duplicate whitespace segments (eg " ") to single whitespace (" ") +auto Bass::strip(string& s) -> void { + uint offset = 0; + char quoted = 0; + for(uint n : range(s.size())) { + if(!quoted) { + if(s[n] == '"' || s[n] == '\'') quoted = s[n]; + } else if(quoted == s[n]) { + quoted = 0; + } + if(!quoted && s[n] == ' ' && s[n + 1] == ' ') continue; + s.get()[offset++] = s[n]; + } + s.resize(offset); +} + +//returns true for valid name identifiers +auto Bass::validate(const string& s) -> bool { + for(uint n : range(s.size())) { + char c = s[n]; + if(c == '_' || c == '#') continue; + if(c >= 'A' && c <= 'Z') continue; + if(c >= 'a' && c <= 'z') continue; + if(c >= '0' && c <= '9' && n) continue; + if(c == '.' && n) continue; + return false; + } + return true; +} + +auto Bass::text(string s) -> string { + if(!s.match("\"*\"")) warning("string value is unquoted: ", s); + + auto parts = s.qsplit("~").strip(); + for(auto& p : parts) { + p.trim("\"", "\"", 1L); + p.replace("\\\\", "\\"); + p.replace("\\n", "\n"); + p.replace("\\t", "\t"); + } + return parts.merge(); +} + +auto Bass::character(const string& s) -> int64_t { + maybe result; + if(s[0] == '\'') { + if(0); + else if(s[1] == '\\' && s[2] == '\\' && s[3] == '\'') result = '\\'; + else if(s[1] == '\\' && s[2] == '\'' && s[3] == '\'') result = '\''; + else if(s[1] == '\\' && s[2] == '\"' && s[3] == '\'') result = '\"'; + else if(s[1] == '\\' && s[2] == 'n' && s[3] == '\'') result = '\n'; + else if(s[1] == '\\' && s[2] == 't' && s[3] == '\'') result = '\t'; + else if(s[2] == '\'') result = s[1]; + } + + if(!result) { + warning("unrecognized character constant: ", s); + return 0; + } + + if(charactersUseMap) result = stringTable[*result]; + return *result; +} diff --git a/roms/snes-test-roms/bass-untech/bass/data/architectures/spc700.arch b/roms/snes-test-roms/bass-untech/bass/data/architectures/spc700.arch new file mode 100644 index 00000000..9116b6d3 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/data/architectures/spc700.arch @@ -0,0 +1,324 @@ +endian lsb + +nop ;$00 +brk ;$0f +rts ;$6f +rti ;$7f +xcn ;$9f +wai ;$ef +stp ;$ff + +clp ;$20 +clc ;$60 +cli ;$c0 +clv ;$e0 +sep ;$40 +sec ;$80 +sei ;$a0 +cmc ;$ed + +php ;$0d +pha ;$2d +phx ;$4d +phy ;$6d +plp ;$8e +pla ;$ae +plx ;$ce +ply ;$ee + +inx ;$3d +iny ;$fc +dex ;$1d +dey ;$dc + +tax ;$5d +tay ;$fd +tsx ;$9d +txa ;$7d +txs ;$bd +tya ;$dd + +mul ;$cf +div ;$9e + +das ;$be +daa ;$df + +jst *04 ;=a %0001 +set *08:*03 ;=b %00010 =a +clr *08:*03 ;=b %10010 =a +bbs *08:*03=*08 ;=b %00011 =a +3c +bbc *08:*03=*08 ;=b %10011 =a +3c + +jmp (*16,x) ;$1f =a +jmp *16 ;$5f =a +jsr *16 ;$3f =a +jsp *08 ;$4f =a + +bne --y=*08 ;$fe +2a +bne --*08=*08 ;$6e =a +3b +bne *08,x=*08 ;$de =a +3b +bne *08=*08 ;$2e =a +3b + +bra *08 ;$2f +2a +bpl *08 ;$10 +2a +bmi *08 ;$30 +2a +bvc *08 ;$50 +2a +bvs *08 ;$70 +2a +bcc *08 ;$90 +2a +bcs *08 ;$b0 +2a +bne *08 ;$d0 +2a +beq *08 ;$f0 +2a + +tsb *16 ;$0e =a +trb *16 ;$4e =a + +inw *08 ;$3a =a +dew *08 ;$1a =a +adw *08 ;$7a =a +sbw *08 ;$9a =a +cpw *08 ;$5a =a +ldw *08 ;$ba =a +stw *08 ;$da =a + +orc !*13:*03 ;$2a ~b ~a +orc *13:*03 ;$0a ~b ~a +and !*13:*03 ;$6a ~b ~a +and *13:*03 ;$4a ~b ~a +eor *13:*03 ;$8a ~b ~a +ldc *13:*03 ;$aa ~b ~a +stc *13:*03 ;$ca ~b ~a +not *13:*03 ;$ea ~b ~a + +ora (x) ;$06 +orr (x)=(y) ;$19 +ora (*08,x) ;$07 =a +ora (*08),y ;$17 =a +ora #*08 ;$08 =a +orr *08=#*08 ;$18 =b =a +ora *16,x ;$15 =a +ora *16,y ;$16 =a +ora *08,x ;$14 =a +orr *08=*08 ;$09 =b =a +ora *16 ;$05 =a +ora *08 ;$04 =a +// +ora.w *16,x ;$15 ~a +ora.b *08,x ;$14 ~a +ora.w *16 ;$05 ~a +ora.b *08 ;$04 ~a + +and (x) ;$26 +and (x)=(y) ;$39 +and (*08,x) ;$27 =a +and (*08),y ;$37 =a +and #*08 ;$28 =a +and *08=#*08 ;$38 =b =a +and *16,x ;$35 =a +and *16,y ;$36 =a +and *08,x ;$34 =a +and *08=*08 ;$29 =b =a +and *16 ;$25 =a +and *08 ;$24 =a +// +and.w *16,x ;$35 ~a +and.b *08,x ;$34 ~a +and.w *16 ;$25 ~a +and.b *08 ;$24 ~a + +eor (x) ;$46 +eor (x)=(y) ;$59 +eor (*08,x) ;$47 =a +eor (*08),y ;$57 =a +eor #*08 ;$48 =a +eor *08=#*08 ;$58 =b =a +eor *16,x ;$55 =a +eor *16,y ;$56 =a +eor *08,x ;$54 =a +eor *08=*08 ;$49 =b =a +eor *16 ;$45 =a +eor *08 ;$44 =a +// +eor.w *16,x ;$55 ~a +eor.b *08,x ;$54 ~a +eor.w *16 ;$45 ~a +eor.b *08 ;$44 ~a + +cmp (x) ;$66 +cmp (x)=(y) ;$79 +cmp (*08,x) ;$67 =a +cmp (*08),y ;$77 =a +cmp #*08 ;$68 =a +cmp *08=#*08 ;$78 =b =a +cmp *16,x ;$75 =a +cmp *16,y ;$76 =a +cmp *08,x ;$74 =a +cmp *08=*08 ;$69 =b =a +cmp *16 ;$65 =a +cmp *08 ;$64 =a +// +cmp.w *16,x ;$75 ~a +cmp.b *08,x ;$74 ~a +cmp.w *16 ;$65 ~a +cmp.b *08 ;$64 ~a + +adc (x) ;$86 +adc (x)=(y) ;$99 +adc (*08,x) ;$87 =a +adc (*08),y ;$97 =a +adc #*08 ;$88 =a +adc *08=#*08 ;$98 =b =a +adc *16,x ;$95 =a +adc *16,y ;$96 =a +adc *08,x ;$94 =a +adc *08=*08 ;$89 =b =a +adc *16 ;$85 =a +adc *08 ;$84 =a +// +adc.w *16,x ;$95 ~a +adc.b *08,x ;$94 ~a +adc.w *16 ;$85 ~a +adc.b *08 ;$84 ~a + +sbc (x) ;$a6 +sbc (x)=(y) ;$b9 +sbc (*08,x) ;$a7 =a +sbc (*08),y ;$b7 =a +sbc #*08 ;$a8 =a +sbc *08=#*08 ;$b8 =b =a +sbc *16,x ;$b5 =a +sbc *16,y ;$b6 =a +sbc *08,x ;$b4 =a +sbc *08=*08 ;$a9 =b =a +sbc *16 ;$a5 =a +sbc *08 ;$a4 =a +// +sbc.w *16,x ;$b5 ~a +sbc.b *08,x ;$b4 ~a +sbc.w *16 ;$a5 ~a +sbc.b *08 ;$a4 ~a + +sta (x) ;$c6 +sta (x++) ;$af +sta (*08,x) ;$c7 =a +sta (*08),y ;$d7 =a +str *08=#*08 ;$8f =b =a +sta *16,x ;$d5 =a +sta *16,y ;$d6 =a +sta *08,x ;$d4 =a +str *08=*08 ;$fa =b =a +sta *16 ;$c5 =a +sta *08 ;$c4 =a +// +sta.w *16,x ;$d5 ~a +sta.b *08,x ;$d4 ~a +sta.w *16 ;$c5 ~a +sta.b *08 ;$c4 ~a + +lda (x) ;$e6 +lda (x++) ;$bf +lda (*08,x) ;$e7 =a +lda (*08),y ;$f7 =a +lda #*08 ;$e8 =a +lda *16,x ;$f5 =a +lda *16,y ;$f6 =a +lda *08,x ;$f4 =a +lda *16 ;$e5 =a +lda *08 ;$e4 =a +// +lda.w *16,x ;$f5 ~a +lda.b *08,x ;$f4 ~a +lda.w *16 ;$e5 ~a +lda.b *08 ;$e4 ~a + +stx *08,y ;$d9 =a +stx *16 ;$c9 =a +stx *08 ;$d8 =a +// +stx.w *16 ;$c9 ~a +stx.b *08 ;$d8 ~a + +sty *08,x ;$db =a +sty *16 ;$cc =a +sty *08 ;$cb =a +// +sty.w *16 ;$cc ~a +sty.b *08 ;$cb ~a + +ldx #*08 ;$cd =a +ldx *08,y ;$f9 =a +ldx *16 ;$e9 =a +ldx *08 ;$f8 =a +// +ldx.w *16 ;$e9 ~a +ldx.b *08 ;$f8 ~a + +ldy #*08 ;$8d =a +ldy *08,x ;$fb =a +ldy *16 ;$ec =a +ldy *08 ;$eb =a +// +ldy.w *16 ;$ec ~a +ldy.b *08 ;$eb ~a + +cpx #*08 ;$c8 =a +cpx *16 ;$1e =a +cpx *08 ;$3e =a +// +cpx.w *16 ;$1e ~a +cpx.b *08 ;$3e ~a + +cpy #*08 ;$ad =a +cpy *16 ;$5e =a +cpy *08 ;$7e =a +// +cpy.w *16 ;$5e ~a +cpy.b *08 ;$7e ~a + +asl ;$1c +asl *08,x ;$1b =a +asl *16 ;$0c =a +asl *08 ;$0b =a +// +asl.w *16 ;$0c ~a +asl.b *08 ;$0b ~a + +lsr ;$5c +lsr *08,x ;$5b =a +lsr *16 ;$4c =a +lsr *08 ;$4b =a +// +lsr.w *16 ;$4c ~a +lsr.b *08 ;$4b ~a + +rol ;$3c +rol *08,x ;$3b =a +rol *16 ;$2c =a +rol *08 ;$2b =a +// +rol.w *16 ;$2c ~a +rol.b *08 ;$2b ~a + +ror ;$7c +ror *08,x ;$7b =a +ror *16 ;$6c =a +ror *08 ;$6b =a +// +ror.w *16 ;$6c ~a +ror.b *08 ;$6b ~a + +inc ;$bc +inc *08,x ;$bb =a +inc *16 ;$ac =a +inc *08 ;$ab =a +// +inc.w *16 ;$ac ~a +inc.b *08 ;$ab ~a + +dec ;$9c +dec *08,x ;$9b =a +dec *16 ;$8c =a +dec *08 ;$8b =a +// +dec.w *16 ;$8c ~a +dec.b *08 ;$8b ~a diff --git a/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816-strict.arch b/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816-strict.arch new file mode 100644 index 00000000..1efbee73 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816-strict.arch @@ -0,0 +1,341 @@ +endian lsb + +asl ;$0a +clc ;$18 +cld ;$d8 +cli ;$58 +clv ;$b8 +dec ;$3a +dex ;$ca +dey ;$88 +inc ;$1a +inx ;$e8 +iny ;$c8 +lsr ;$4a +nop ;$ea +pha ;$48 +phb ;$8b +phd ;$0b +phk ;$4b +php ;$08 +phx ;$da +phy ;$5a +pla ;$68 +plb ;$ab +pld ;$2b +plp ;$28 +plx ;$fa +ply ;$7a +rol ;$2a +ror ;$6a +rti ;$40 +rtl ;$6b +rts ;$60 +sec ;$38 +sed ;$f8 +sei ;$78 +stp ;$db +tad ;$5b +tas ;$1b +tax ;$aa +tay ;$a8 +tda ;$7b +tsa ;$3b +tsx ;$ba +txa ;$8a +txs ;$9a +txy ;$9b +tya ;$98 +tyx ;$bb +wai ;$cb +xba ;$eb +xce ;$fb +// +tcd ;$5b +tcs ;$1b +tdc ;$7b +tsc ;$3b + +ora *08,s ;$03 =a +ora (*08,s),y ;$13 =a +ora (*08,x) ;$01 =a +ora (*08),y ;$11 =a +ora [*08],y ;$17 =a +ora (*08) ;$12 =a +ora [*08] ;$07 =a +// +ora.w #*16 ;$09 ~a +ora.b #*08 ;$09 ~a +ora.w *16,y ;$19 ~a +ora.l *24,x ;$1f ~a +ora.w *16,x ;$1d ~a +ora.b *08,x ;$15 ~a +ora.l *24 ;$0f ~a +ora.w *16 ;$0d ~a +ora.b *08 ;$05 ~a + +and *08,s ;$23 =a +and (*08,s),y ;$33 =a +and (*08,x) ;$21 =a +and (*08),y ;$31 =a +and [*08],y ;$37 =a +and (*08) ;$32 =a +and [*08] ;$27 =a +// +and.w #*16 ;$29 ~a +and.b #*08 ;$29 ~a +and.w *16,y ;$39 ~a +and.l *24,x ;$3f ~a +and.w *16,x ;$3d ~a +and.b *08,x ;$35 ~a +and.l *24 ;$2f ~a +and.w *16 ;$2d ~a +and.b *08 ;$25 ~a + +eor *08,s ;$43 =a +eor (*08,s),y ;$53 =a +eor (*08,x) ;$41 =a +eor (*08),y ;$51 =a +eor [*08],y ;$57 =a +eor (*08) ;$52 =a +eor [*08] ;$47 =a +// +eor.w #*16 ;$49 ~a +eor.b #*08 ;$49 ~a +eor.w *16,y ;$59 ~a +eor.l *24,x ;$5f ~a +eor.w *16,x ;$5d ~a +eor.b *08,x ;$55 ~a +eor.l *24 ;$4f ~a +eor.w *16 ;$4d ~a +eor.b *08 ;$45 ~a + +adc *08,s ;$63 =a +adc (*08,s),y ;$73 =a +adc (*08,x) ;$61 =a +adc (*08),y ;$71 =a +adc [*08],y ;$77 =a +adc (*08) ;$72 =a +adc [*08] ;$67 =a +// +adc.w #*16 ;$69 ~a +adc.b #*08 ;$69 ~a +adc.w *16,y ;$79 ~a +adc.l *24,x ;$7f ~a +adc.w *16,x ;$7d ~a +adc.b *08,x ;$75 ~a +adc.l *24 ;$6f ~a +adc.w *16 ;$6d ~a +adc.b *08 ;$65 ~a + +sta *08,s ;$83 =a +sta (*08,s),y ;$93 =a +sta (*08,x) ;$81 =a +sta (*08),y ;$91 =a +sta [*08],y ;$97 =a +sta (*08) ;$92 =a +sta [*08] ;$87 =a +// +sta.w *16,y ;$99 ~a +sta.l *24,x ;$9f ~a +sta.w *16,x ;$9d ~a +sta.b *08,x ;$95 ~a +sta.l *24 ;$8f ~a +sta.w *16 ;$8d ~a +sta.b *08 ;$85 ~a + +lda *08,s ;$a3 =a +lda (*08,s),y ;$b3 =a +lda (*08,x) ;$a1 =a +lda (*08),y ;$b1 =a +lda [*08],y ;$b7 =a +lda (*08) ;$b2 =a +lda [*08] ;$a7 =a +// +lda.w #*16 ;$a9 ~a +lda.b #*08 ;$a9 ~a +lda.w *16,y ;$b9 ~a +lda.l *24,x ;$bf ~a +lda.w *16,x ;$bd ~a +lda.b *08,x ;$b5 ~a +lda.l *24 ;$af ~a +lda.w *16 ;$ad ~a +lda.b *08 ;$a5 ~a + +cmp *08,s ;$c3 =a +cmp (*08,s),y ;$d3 =a +cmp (*08,x) ;$c1 =a +cmp (*08),y ;$d1 =a +cmp [*08],y ;$d7 =a +cmp (*08) ;$d2 =a +cmp [*08] ;$c7 =a +// +cmp.w #*16 ;$c9 ~a +cmp.b #*08 ;$c9 ~a +cmp.w *16,y ;$d9 ~a +cmp.l *24,x ;$df ~a +cmp.w *16,x ;$dd ~a +cmp.b *08,x ;$d5 ~a +cmp.l *24 ;$cf ~a +cmp.w *16 ;$cd ~a +cmp.b *08 ;$c5 ~a + +sbc *08,s ;$e3 =a +sbc (*08,s),y ;$f3 =a +sbc (*08,x) ;$e1 =a +sbc (*08),y ;$f1 =a +sbc [*08],y ;$f7 =a +sbc (*08) ;$f2 =a +sbc [*08] ;$e7 =a +// +sbc.w #*16 ;$e9 ~a +sbc.b #*08 ;$e9 ~a +sbc.w *16,y ;$f9 ~a +sbc.l *24,x ;$ff ~a +sbc.w *16,x ;$fd ~a +sbc.b *08,x ;$f5 ~a +sbc.l *24 ;$ef ~a +sbc.w *16 ;$ed ~a +sbc.b *08 ;$e5 ~a + +// +asl.w *16,x ;$1e ~a +asl.b *08,x ;$16 ~a +asl.w *16 ;$0e ~a +asl.b *08 ;$06 ~a + +// +lsr.w *16,x ;$5e ~a +lsr.b *08,x ;$56 ~a +lsr.w *16 ;$4e ~a +lsr.b *08 ;$46 ~a + +// +rol.w *16,x ;$3e ~a +rol.b *08,x ;$36 ~a +rol.w *16 ;$2e ~a +rol.b *08 ;$26 ~a + +// +ror.w *16,x ;$7e ~a +ror.b *08,x ;$76 ~a +ror.w *16 ;$6e ~a +ror.b *08 ;$66 ~a + +// +inc.w *16,x ;$fe ~a +inc.b *08,x ;$f6 ~a +inc.w *16 ;$ee ~a +inc.b *08 ;$e6 ~a + +// +dec.w *16,x ;$de ~a +dec.b *08,x ;$d6 ~a +dec.w *16 ;$ce ~a +dec.b *08 ;$c6 ~a + +// +bit.w #*16 ;$89 ~a +bit.b #*08 ;$89 ~a +bit.w *16,x ;$3c ~a +bit.b *08,x ;$34 ~a +bit.w *16 ;$2c ~a +bit.b *08 ;$24 ~a + +// +cpx.w #*16 ;$e0 ~a +cpx.b #*08 ;$e0 ~a +cpx.w *16 ;$ec ~a +cpx.b *08 ;$e4 ~a + +// +cpy.w #*16 ;$c0 ~a +cpy.b #*08 ;$c0 ~a +cpy.w *16 ;$cc ~a +cpy.b *08 ;$c4 ~a + +// +ldx.w #*16 ;$a2 ~a +ldx.b #*08 ;$a2 ~a +ldx.w *16,y ;$be ~a +ldx.b *08,y ;$b6 ~a +ldx.w *16 ;$ae ~a +ldx.b *08 ;$a6 ~a + +// +ldy.w #*16 ;$a0 ~a +ldy.b #*08 ;$a0 ~a +ldy.w *16,x ;$bc ~a +ldy.b *08,x ;$b4 ~a +ldy.w *16 ;$ac ~a +ldy.b *08 ;$a4 ~a + +// +stx.b *08,y ;$96 ~a +stx.w *16 ;$8e ~a +stx.b *08 ;$86 ~a + +// +sty.b *08,x ;$94 ~a +sty.w *16 ;$8c ~a +sty.b *08 ;$84 ~a + +// +stz.w *16,x ;$9e ~a +stz.b *08,x ;$74 ~a +stz.w *16 ;$9c ~a +stz.b *08 ;$64 ~a + +// +trb.w *16 ;$1c ~a +trb.b *08 ;$14 ~a + +// +tsb.w *16 ;$0c ~a +tsb.b *08 ;$04 ~a + +jmp (*16,x) ;$7c =a +jmp (*16) ;$6c =a +jmp [*16] ;$dc =a +jmp *16 ;$4c =a +jml *24 ;$5c =a + +jsr (*16,x) ;$fc =a +jsr *16 ;$20 =a +jsl *24 ;$22 =a + +brl #*16 ;$82 =a +bra #*08 ;$80 =a +bpl #*08 ;$10 =a +bmi #*08 ;$30 =a +bvc #*08 ;$50 =a +bvs #*08 ;$70 =a +bcc #*08 ;$90 =a +bcs #*08 ;$b0 =a +bne #*08 ;$d0 =a +beq #*08 ;$f0 =a +// +brl *16 ;$82 +3a +bra *08 ;$80 +2a +bpl *08 ;$10 +2a +bmi *08 ;$30 +2a +bvc *08 ;$50 +2a +bvs *08 ;$70 +2a +bcc *08 ;$90 +2a +bcs *08 ;$b0 +2a +bne *08 ;$d0 +2a +beq *08 ;$f0 +2a + +mvp *08=*08 ;$44 =a =b +mvn *08=*08 ;$54 =a =b + +pea *16 ;$f4 =a +pei (*08) ;$d4 =a +per *16 ;$62 =a + +rep #*08 ;$c2 =a +sep #*08 ;$e2 =a + +brk #*08 ;$00 =a +cop #*08 ;$02 =a +wdm #*08 ;$42 =a diff --git a/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816.arch b/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816.arch new file mode 100644 index 00000000..70a913ce --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/data/architectures/wdc65816.arch @@ -0,0 +1,487 @@ +endian lsb + +asl ;$0a +clc ;$18 +cld ;$d8 +cli ;$58 +clv ;$b8 +dec ;$3a +dex ;$ca +dey ;$88 +inc ;$1a +inx ;$e8 +iny ;$c8 +lsr ;$4a +nop ;$ea +pha ;$48 +phb ;$8b +phd ;$0b +phk ;$4b +php ;$08 +phx ;$da +phy ;$5a +pla ;$68 +plb ;$ab +pld ;$2b +plp ;$28 +plx ;$fa +ply ;$7a +rol ;$2a +ror ;$6a +rti ;$40 +rtl ;$6b +rts ;$60 +sec ;$38 +sed ;$f8 +sei ;$78 +stp ;$db +tad ;$5b +tas ;$1b +tax ;$aa +tay ;$a8 +tda ;$7b +tsa ;$3b +tsx ;$ba +txa ;$8a +txs ;$9a +txy ;$9b +tya ;$98 +tyx ;$bb +wai ;$cb +xba ;$eb +xce ;$fb +// +tcd ;$5b +tcs ;$1b +tdc ;$7b +tsc ;$3b + +asl #*08 ;*a:$0a +dec #*08 ;*a:$3a +dex #*08 ;*a:$ca +dey #*08 ;*a:$88 +inc #*08 ;*a:$1a +inx #*08 ;*a:$e8 +iny #*08 ;*a:$c8 +lsr #*08 ;*a:$4a +nop #*08 ;*a:$ea +rol #*08 ;*a:$2a +ror #*08 ;*a:$6a + +ora #*16 ;$09 =a +ora #*08 ;$09 =a +ora *08,s ;$03 =a +ora (*08,s),y ;$13 =a +ora (*08,x) ;$01 =a +ora (*08),y ;$11 =a +ora [*08],y ;$17 =a +ora (*08) ;$12 =a +ora [*08] ;$07 =a +ora *16,y ;$19 =a +ora *24,x ;$1f =a +ora *16,x ;$1d =a +ora *08,x ;$15 =a +ora *24 ;$0f =a +ora *16 ;$0d =a +ora *08 ;$05 =a +// +ora.w #*16 ;$09 ~a +ora.b #*08 ;$09 ~a +ora.w *16,y ;$19 ~a +ora.l *24,x ;$1f ~a +ora.w *16,x ;$1d ~a +ora.b *08,x ;$15 ~a +ora.l *24 ;$0f ~a +ora.w *16 ;$0d ~a +ora.b *08 ;$05 ~a + +and #*16 ;$29 =a +and #*08 ;$29 =a +and *08,s ;$23 =a +and (*08,s),y ;$33 =a +and (*08,x) ;$21 =a +and (*08),y ;$31 =a +and [*08],y ;$37 =a +and (*08) ;$32 =a +and [*08] ;$27 =a +and *16,y ;$39 =a +and *24,x ;$3f =a +and *16,x ;$3d =a +and *08,x ;$35 =a +and *24 ;$2f =a +and *16 ;$2d =a +and *08 ;$25 =a +// +and.w #*16 ;$29 ~a +and.b #*08 ;$29 ~a +and.w *16,y ;$39 ~a +and.l *24,x ;$3f ~a +and.w *16,x ;$3d ~a +and.b *08,x ;$35 ~a +and.l *24 ;$2f ~a +and.w *16 ;$2d ~a +and.b *08 ;$25 ~a + +eor #*16 ;$49 =a +eor #*08 ;$49 =a +eor *08,s ;$43 =a +eor (*08,s),y ;$53 =a +eor (*08,x) ;$41 =a +eor (*08),y ;$51 =a +eor [*08],y ;$57 =a +eor (*08) ;$52 =a +eor [*08] ;$47 =a +eor *16,y ;$59 =a +eor *24,x ;$5f =a +eor *16,x ;$5d =a +eor *08,x ;$55 =a +eor *24 ;$4f =a +eor *16 ;$4d =a +eor *08 ;$45 =a +// +eor.w #*16 ;$49 ~a +eor.b #*08 ;$49 ~a +eor.w *16,y ;$59 ~a +eor.l *24,x ;$5f ~a +eor.w *16,x ;$5d ~a +eor.b *08,x ;$55 ~a +eor.l *24 ;$4f ~a +eor.w *16 ;$4d ~a +eor.b *08 ;$45 ~a + +adc #*16 ;$69 =a +adc #*08 ;$69 =a +adc *08,s ;$63 =a +adc (*08,s),y ;$73 =a +adc (*08,x) ;$61 =a +adc (*08),y ;$71 =a +adc [*08],y ;$77 =a +adc (*08) ;$72 =a +adc [*08] ;$67 =a +adc *16,y ;$79 =a +adc *24,x ;$7f =a +adc *16,x ;$7d =a +adc *08,x ;$75 =a +adc *24 ;$6f =a +adc *16 ;$6d =a +adc *08 ;$65 =a +// +adc.w #*16 ;$69 ~a +adc.b #*08 ;$69 ~a +adc.w *16,y ;$79 ~a +adc.l *24,x ;$7f ~a +adc.w *16,x ;$7d ~a +adc.b *08,x ;$75 ~a +adc.l *24 ;$6f ~a +adc.w *16 ;$6d ~a +adc.b *08 ;$65 ~a + +sta *08,s ;$83 =a +sta (*08,s),y ;$93 =a +sta (*08,x) ;$81 =a +sta (*08),y ;$91 =a +sta [*08],y ;$97 =a +sta (*08) ;$92 =a +sta [*08] ;$87 =a +sta *16,y ;$99 =a +sta *24,x ;$9f =a +sta *16,x ;$9d =a +sta *08,x ;$95 =a +sta *24 ;$8f =a +sta *16 ;$8d =a +sta *08 ;$85 =a +// +sta.w *16,y ;$99 ~a +sta.l *24,x ;$9f ~a +sta.w *16,x ;$9d ~a +sta.b *08,x ;$95 ~a +sta.l *24 ;$8f ~a +sta.w *16 ;$8d ~a +sta.b *08 ;$85 ~a + +lda #*16 ;$a9 =a +lda #*08 ;$a9 =a +lda *08,s ;$a3 =a +lda (*08,s),y ;$b3 =a +lda (*08,x) ;$a1 =a +lda (*08),y ;$b1 =a +lda [*08],y ;$b7 =a +lda (*08) ;$b2 =a +lda [*08] ;$a7 =a +lda *16,y ;$b9 =a +lda *24,x ;$bf =a +lda *16,x ;$bd =a +lda *08,x ;$b5 =a +lda *24 ;$af =a +lda *16 ;$ad =a +lda *08 ;$a5 =a +// +lda.w #*16 ;$a9 ~a +lda.b #*08 ;$a9 ~a +lda.w *16,y ;$b9 ~a +lda.l *24,x ;$bf ~a +lda.w *16,x ;$bd ~a +lda.b *08,x ;$b5 ~a +lda.l *24 ;$af ~a +lda.w *16 ;$ad ~a +lda.b *08 ;$a5 ~a + +cmp #*16 ;$c9 =a +cmp #*08 ;$c9 =a +cmp *08,s ;$c3 =a +cmp (*08,s),y ;$d3 =a +cmp (*08,x) ;$c1 =a +cmp (*08),y ;$d1 =a +cmp [*08],y ;$d7 =a +cmp (*08) ;$d2 =a +cmp [*08] ;$c7 =a +cmp *16,y ;$d9 =a +cmp *24,x ;$df =a +cmp *16,x ;$dd =a +cmp *08,x ;$d5 =a +cmp *24 ;$cf =a +cmp *16 ;$cd =a +cmp *08 ;$c5 =a +// +cmp.w #*16 ;$c9 ~a +cmp.b #*08 ;$c9 ~a +cmp.w *16,y ;$d9 ~a +cmp.l *24,x ;$df ~a +cmp.w *16,x ;$dd ~a +cmp.b *08,x ;$d5 ~a +cmp.l *24 ;$cf ~a +cmp.w *16 ;$cd ~a +cmp.b *08 ;$c5 ~a + +sbc #*16 ;$e9 =a +sbc #*08 ;$e9 =a +sbc *08,s ;$e3 =a +sbc (*08,s),y ;$f3 =a +sbc (*08,x) ;$e1 =a +sbc (*08),y ;$f1 =a +sbc [*08],y ;$f7 =a +sbc (*08) ;$f2 =a +sbc [*08] ;$e7 =a +sbc *16,y ;$f9 =a +sbc *24,x ;$ff =a +sbc *16,x ;$fd =a +sbc *08,x ;$f5 =a +sbc *24 ;$ef =a +sbc *16 ;$ed =a +sbc *08 ;$e5 =a +// +sbc.w #*16 ;$e9 ~a +sbc.b #*08 ;$e9 ~a +sbc.w *16,y ;$f9 ~a +sbc.l *24,x ;$ff ~a +sbc.w *16,x ;$fd ~a +sbc.b *08,x ;$f5 ~a +sbc.l *24 ;$ef ~a +sbc.w *16 ;$ed ~a +sbc.b *08 ;$e5 ~a + +asl *16,x ;$1e =a +asl *08,x ;$16 =a +asl *16 ;$0e =a +asl *08 ;$06 =a +// +asl.w *16,x ;$1e ~a +asl.b *08,x ;$16 ~a +asl.w *16 ;$0e ~a +asl.b *08 ;$06 ~a + +lsr *16,x ;$5e =a +lsr *08,x ;$56 =a +lsr *16 ;$4e =a +lsr *08 ;$46 =a +// +lsr.w *16,x ;$5e ~a +lsr.b *08,x ;$56 ~a +lsr.w *16 ;$4e ~a +lsr.b *08 ;$46 ~a + +rol *16,x ;$3e =a +rol *08,x ;$36 =a +rol *16 ;$2e =a +rol *08 ;$26 =a +// +rol.w *16,x ;$3e ~a +rol.b *08,x ;$36 ~a +rol.w *16 ;$2e ~a +rol.b *08 ;$26 ~a + +ror *16,x ;$7e =a +ror *08,x ;$76 =a +ror *16 ;$6e =a +ror *08 ;$66 =a +// +ror.w *16,x ;$7e ~a +ror.b *08,x ;$76 ~a +ror.w *16 ;$6e ~a +ror.b *08 ;$66 ~a + +inc *16,x ;$fe =a +inc *08,x ;$f6 =a +inc *16 ;$ee =a +inc *08 ;$e6 =a +// +inc.w *16,x ;$fe ~a +inc.b *08,x ;$f6 ~a +inc.w *16 ;$ee ~a +inc.b *08 ;$e6 ~a + +dec *16,x ;$de =a +dec *08,x ;$d6 =a +dec *16 ;$ce =a +dec *08 ;$c6 =a +// +dec.w *16,x ;$de ~a +dec.b *08,x ;$d6 ~a +dec.w *16 ;$ce ~a +dec.b *08 ;$c6 ~a + +bit #*16 ;$89 =a +bit #*08 ;$89 =a +bit *16,x ;$3c =a +bit *08,x ;$34 =a +bit *16 ;$2c =a +bit *08 ;$24 =a +// +bit.w #*16 ;$89 ~a +bit.b #*08 ;$89 ~a +bit.w *16,x ;$3c ~a +bit.b *08,x ;$34 ~a +bit.w *16 ;$2c ~a +bit.b *08 ;$24 ~a + +cpx #*16 ;$e0 =a +cpx #*08 ;$e0 =a +cpx *16 ;$ec =a +cpx *08 ;$e4 =a +// +cpx.w #*16 ;$e0 ~a +cpx.b #*08 ;$e0 ~a +cpx.w *16 ;$ec ~a +cpx.b *08 ;$e4 ~a + +cpy #*16 ;$c0 =a +cpy #*08 ;$c0 =a +cpy *16 ;$cc =a +cpy *08 ;$c4 =a +// +cpy.w #*16 ;$c0 ~a +cpy.b #*08 ;$c0 ~a +cpy.w *16 ;$cc ~a +cpy.b *08 ;$c4 ~a + +ldx #*16 ;$a2 =a +ldx #*08 ;$a2 =a +ldx *16,y ;$be =a +ldx *08,y ;$b6 =a +ldx *16 ;$ae =a +ldx *08 ;$a6 =a +// +ldx.w #*16 ;$a2 ~a +ldx.b #*08 ;$a2 ~a +ldx.w *16,y ;$be ~a +ldx.b *08,y ;$b6 ~a +ldx.w *16 ;$ae ~a +ldx.b *08 ;$a6 ~a + +ldy #*16 ;$a0 =a +ldy #*08 ;$a0 =a +ldy *16,x ;$bc =a +ldy *08,x ;$b4 =a +ldy *16 ;$ac =a +ldy *08 ;$a4 =a +// +ldy.w #*16 ;$a0 ~a +ldy.b #*08 ;$a0 ~a +ldy.w *16,x ;$bc ~a +ldy.b *08,x ;$b4 ~a +ldy.w *16 ;$ac ~a +ldy.b *08 ;$a4 ~a + +stx *08,y ;$96 =a +stx *16 ;$8e =a +stx *08 ;$86 =a +// +stx.b *08,y ;$96 ~a +stx.w *16 ;$8e ~a +stx.b *08 ;$86 ~a + +sty *08,x ;$94 =a +sty *16 ;$8c =a +sty *08 ;$84 =a +// +sty.b *08,x ;$94 ~a +sty.w *16 ;$8c ~a +sty.b *08 ;$84 ~a + +stz *16,x ;$9e =a +stz *08,x ;$74 =a +stz *16 ;$9c =a +stz *08 ;$64 =a +// +stz.w *16,x ;$9e ~a +stz.b *08,x ;$74 ~a +stz.w *16 ;$9c ~a +stz.b *08 ;$64 ~a + +trb *16 ;$1c =a +trb *08 ;$14 =a +// +trb.w *16 ;$1c ~a +trb.b *08 ;$14 ~a + +tsb *16 ;$0c =a +tsb *08 ;$04 =a +// +tsb.w *16 ;$0c ~a +tsb.b *08 ;$04 ~a + +jmp (*16,x) ;$7c =a +jmp (*16) ;$6c =a +jmp [*16] ;$dc =a +jmp *16 ;$4c =a +jml *24 ;$5c =a + +jsr (*16,x) ;$fc =a +jsr *16 ;$20 =a +jsl *24 ;$22 =a + +brl #*16 ;$82 =a +bra #*08 ;$80 =a +bpl #*08 ;$10 =a +bmi #*08 ;$30 =a +bvc #*08 ;$50 =a +bvs #*08 ;$70 =a +bcc #*08 ;$90 =a +bcs #*08 ;$b0 =a +bne #*08 ;$d0 =a +beq #*08 ;$f0 =a +// +brl *16 ;$82 +3a +bra *08 ;$80 +2a +bpl *08 ;$10 +2a +bmi *08 ;$30 +2a +bvc *08 ;$50 +2a +bvs *08 ;$70 +2a +bcc *08 ;$90 +2a +bcs *08 ;$b0 +2a +bne *08 ;$d0 +2a +beq *08 ;$f0 +2a + +mvp *08=*08 ;$44 =a =b +mvn *08=*08 ;$54 =a =b + +pea *16 ;$f4 =a +pei (*08) ;$d4 =a +per *16 ;$62 =a + +rep #*08 ;$c2 =a +sep #*08 ;$e2 =a + +brk #*08 ;$00 =a +cop #*08 ;$02 =a +wdm #*08 ;$42 =a diff --git a/roms/snes-test-roms/bass-untech/bass/doc/bass.html b/roms/snes-test-roms/bass-untech/bass/doc/bass.html new file mode 100644 index 00000000..c8c7ef49 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/bass/doc/bass.html @@ -0,0 +1,709 @@ + + + bass-untech documentation + + + +

bass-untech v17

+ DISCLAIMER: bass-untech is a fork of Near's bass assembler
+ Author: Near
+ Forked By: The UnDisbeliever
+ License: ISC
+
+ +

Terminal Usage

+
bass-untech [options] source [source ...]
+ +

Options

+ +

-o target will specify the default target filename, and overwrite + any existing file by said filename.

+ +

-m target will specify the default target filenamd, and will + modify, rather than replace, any existing file by said name.

+ +

-d name[=value] will create a define with the given name, and + assign to it either an empty value or the value provided.

+ +

-c name[=value] will create a constant with the given name, and + assign to it either a value of 1 or the value provided.

+ +

-sym filename will create a symbol file with the given filename. + The symbol file will contain the pc address and scoped name for every + named label.

+ +

-strict will abort the assembly process on warnings.

+ +

-benchmark will display the time required to assemble the source. +

+ +

Architecture

+

bass is a multi-pass assembler which can be driven by tables to support + multiple architectures.

+ +

Parsing consists of the following phases:

+ +

Tokenize

+ +

The tokenize phase will combine all source files, and insert any + nested include statements into a single stream of instructions.

+ +

Analyze

+ +

The analyze phase will parse blocks, such as macros and functions, + and note where they begin and end.

+ +

Execute

+ +

The execute phase will recurse macro invocations, substitute + defines and evaluate conditional expressions.

+ +

Query

+ +

The query phase invokes the execute phase, and computes the + values of constants and labels.

+ +

Write

+ +

The write phase invokes the execute phase, uses the + previously computed values for constants and labels, and writes to any + opened output file.

+ +

Tokenizing

+

Initially, each source file specified on the terminal is loaded in. For + each source file, all tabs (\t) and carriage returns (\r) are converted to + spaces, and each line is split by line feeds (\n). Next, each line is + clipped at the first appearance of a comment marker (//). Then, each line is + split by any semicolons (;) not appearing inside of quoted strings. + That is to say, semicolons can be used inside of quoted strings. Using + semicolons outside of strings splits the line into multiple statements. The + semicolon acts as a statement separator, and not as a statement terminator, + meaning that a semicolon is not required at the end of each line. Finally, + if the statement is an include directive, the source file parser will + be invoked recursively to load in nested source files.

+ +

Names

+

Macros, functions, defines, variables and constants must be in the + following format:

+
+    [_A-Za-z][_A-Za-z0-9.]*
+    
+ +

Numbers

+

Valid numbers must be in one of the following formats:

+
+    [0-9]+       integer
+    0b[01]+      binary
+    0o[0-7]+     octal
+    0x[0-9a-f]+   hex
+    %[01]+       binary
+    $[0-9a-f]+   hex
+    
+ +

Numbers may be prefixed with - or + if desired.

+ +

Numbers may also use ' as a digit separator. For example:

+
+    123'456'789  //same as 123456789
+    0b1001'0110   //same as 0b10010110
+    
+ +

Strings

+

Strings are surrounded by double-quotes. They support the following + escape sequences:

+ +
+    \\ = backslash (\)
+    \' = single-quote (')
+    \" = double-quote (")
+    \n = new line
+    \t = tab
+    
+ +

Strings may also be concatenated via the ~ operator, which is useful + for string construction via defines:

+ +
+    "foo" ~ "bar"  //equivalent to "foobar"
+    
+ +

Characters

+

Characters are surrounded by single-quotes, and evaluate to integer + values which can be used inside of expressions. They support the same escape + sequences as strings.

+ +

Note that characters are not escaped for block tokenization. That means + you must use '\b' instead of ';' to avoid splitting the character into two + separate statements.

+ +

Execution

+

Execution acts much like a scripting language. Statements are evaluated + and a control flow (stack frame) is maintained.

+ +

Expressions

+

Expressions can be used to transform variables or constants by use of + parameters. Expressions may be recursive.

+ +

Example:

+
+    expression sum(x, y) = x + y
+    print sum(1, 2), "\n"  //prints 3
+    
+ +

Defines

+

Defines can be used to substitute values in expressions. The + define keyword allows specifying an exact expression to substitute, + whereas the evaluate keyword will evaluate the expression to an + integer value. The latter is useful for conditional expressions. Defines + must be declared before being used, and can be re-declared later on.

+ +

Example:

+
+    define x = 1 + 2
+    print "{x}\n"        //prints "1 + 2\n"
+    evaluate x = {x} + 3  //x = evaluate(1 + 2 + 3)
+    print "{x}\n"        //prints "6\n"
+    
+ +

Defines can also take arguments for substitution.

+ +

Example:

+
+    define sum(x, y) = ({x} + {y})
+    print "{sum(1,2)}\n"  //prints "(1 + 2)\n"
+    
+ +

Invocation

+

Defines can be invoked with: {defineName}. Defines with parameters + can be invoked with {defineName(parameter, ...)}. If a define is not + matched, there is no error, the literal {defineName} will be passed + along to the assembler verbatim.

+ +

Parsing

+

Defines are evaluated from right-to-left order, meaning that expressions + such as {x{y}} will first expand {y}, and then the result of + that expression, {x...}.

+ +

Existence

+

It is possible to test if a define has been declared or not by using this + special syntax: {defined name}

+ +
+    //create {value} if it does not yet exist
+    if !{defined value} {
+      define value(...)
+    }
+    
+ +

{defined name} is substituted with either 1 (if a define by the + given name exists) or 0 (if it does not.)

+ +

Macros

+

Macros are supported. They can take zero or more arguments, and name + overloading with differing arity is possible. Recursion is supported, but + requires conditionals in order to break infinite recursion. Macros must be + declared before being used, and can be re-declared later on.

+ +

By default, macro parameters are simply the names of the values, and are + passed in as defines. It is also possible to specify the type of the + parameter, which will cause the invocation to pass the value in as the + requested type. Supported types are: define, evaluate and variable.

+ +

Example:

+
+    macro seek(offset) {
+      origin {offset} & 0x3fffff
+      base 0xc00000 | {offset}
+    }
+
+    seek(0xc08000)
+
+    macro test(define a, evaluate b, variable c, d) {
+      //{d} has no type, so it defaults to "define d"
+    }
+
+    test(1+2, 1+2, 1+2, 1+2)   //{a} = 1+2, {b} = 3, c = 3, {d} = 1+2
+    
+ +

Invocation Counter

+

Because expanded macros are passed directly to the assembler, a macro + with a label name cannot be expanded twice in the same scope, or the label + name will be declared twice, resulting in an error. The special token + {#} can be used in a label name, where it will be substituted with a + numeric value that increments every time a macro is invoked.

+ +

Note that the invocation counter may not work as expected inside of + recursive macros. Only use this for top-level macros.

+ +

Invocation

+

Macros can be invoked with the syntax: macroName(parameter, parameter, + ...). If a macro is not matched, there is no error, the literal + macroName(...) will be passed along to the assembly phase. Note that + macros cannot appear inside expressions: the macro invocation must be the + entire statement.

+ +

Stack Frame

+

Every time a macro is invoked, a new object stack frame is created, which + will supercede all previous stack frames. All macro arguments, as well as + any objects declared inside of said macro, are appended to the new frame. + When the macro completes execution, said frame is destroyed, and said + objects are lost. Note that this does not apply to constants, which must + always be placed in the global frame to support forward-declarations.

+ +

It is however possible to access the global frame by prefixing object + creation with the global keyword, for example:

+ +
+    macro square(value) {
+      global evaluate result({value} * {value})
+    }
+
+    square(16)
+    print "{square.result}\n"  //prints 256
+    
+ +

Further, it is also possible to reference the parent frame by prefixing + object creation with the parent keyword, which is useful for + recursive macros, or to represent macro return values. For example:

+ +
+    macro factorial(variable n) {
+      parent variable result = 1
+      if n >= 1 {
+        factorial(n - 1)
+        result = n * factorial.result
+      }
+    }
+
+    factorial(10)
+    print factorial.result, "\n"  //prints 3628800
+    
+ +

Inline Macros

+

Macros can also be created without a stack frame by using the + inline keyword, which will cause any objects created inside of them + to appear in the same frame as the macro was invoked in. For example:

+ +
+    inline square(variable value) {
+      variable result = value * value
+    }
+
+    function main {
+      square(16)
+    }
+
+    print main.result, "\n"  //prints 256
+    
+ +

This is obviously not a good idea to use for recursive macros.

+ +

Conditional Expressions

+

bass supports traditional conditional expressions.

+ +

Example:

+
+    define x = 16
+    while {x} > 0 {
+     print "{x}\n"
+     evaluate x = {x} - 1
+    }
+    if {x} > 16 {
+      ...
+    } else if {x} > 8 {
+      ...
+    } else {
+      ...
+    }
+    
+ +

Variables and constants can be used in conditional expressions. Just note + that variables must be declared before they can be used in expressions. Only + constants support forward-declaration.

+ +

Assembly

+

Any statements that fall through the execute phase are passed into the + assembly phase.

+ +

Variables and Constants

+

Variables and constants hold integer values. Variables must be declared + before being used, but can be redefined. Constants can be used before their + declaration, but subsequently cannot be redefined. Labels are stored as + constants.

+ +

Expressions in a constant statement can contain forward references. Just + remember that bass-untech does not perform delayed evaluation and will + abort assembly if the constant's value is unknown when used in a command, a + conditional expression, or the write phase.

+ +

Example:

+
+    variable x = 16
+    lda #x  //16
+
+    variable x = 32
+    lda #x  //32
+
+    lda #y  //64
+    constant y = 64
+
+    constant z = VeryLongLabelName
+    lda z  //VeryLongLabelName
+    
+ +

Arrays

+

Arrays of variables can be created. The size of the array is fixed once + it has been created, but the array can be redefined later on to another + size if desired. Array elements not specified initially are initialized to + zeroes.

+ +

Example:

+
+    array[4] x = 1,2,4,8
+    array[2] y
+
+    y[1] = x[3]
+    print y[0], ",", y[1], "\n"   //prints 0,8
+
+    array[8] x  //recreates a new array with eight entries
+    
+ +

Labels

+

Labels can be created with the syntax: labelName:

+ +

Example:

+
+    loop:
+      dex; bne loop
+    
+ +

Anonymous Labels

+

Labels without names can be created using - and +.

+ +

Example:

+
+    -; beq +; lsr; dex; bne -; +
+
+    -; bra ++  //A: go to D
+    -; bra +   //B: go to C
+    +; bra -   //C: go to B
+    +; bra --  //D: go to A
+    
+ +

Invocation:

+

The previous - label can be referenced with -, and the next + label can + be referenced with +. The second to last - label can be referenced with --, + and the second to next + label can be referenced with ++. Deeper scoping is + not supported: you will have to switch to named labels at this point.

+ +

Scoping

+

Macros, defines, variables and constants can be scoped. This allows reuse + of common names like loop and finish inside of scopes, without + causing declaration collisions. Note that labels are stored as constants, + meaning that scoping also applies to labels.

+ +

It's also important to understand that for macro scoping, the macro + name's scope is determined where the macro is declared, and the actual scope + used while executing a macro is determined where the macro is invoked.

+ +

Example:

+
+    variable offset = 16
+
+    namespace information {
+      variable length = 32
+
+      lda #offset  //16
+      lda #length  //32
+    }
+
+    lda #offset  //16
+    lda #information.length  //32
+    
+ +

Scoped Labels

+

It is possible to declare a scope and label at the same time, which is a + useful way to mark functions and their boundaries.

+ +

Example:

+
+    function main {
+      subroutine:
+    }
+
+    jsr main.subroutine
+    
+ +

Unscoped Blocks

+

It is also possible to create blocks which do not create scopes. These + are used strictly for code clarity, and have no functional effect.

+ +

Example:

+
+    labelName: {
+    }
+
+    - {
+    }
+
+    + {
+    }
+
+    {
+    }
+    
+ +

include "filename"

+

Note that this command is parsed in the very first phase, and is only + noted here for completeness. It includes another source file in place of + this command.

+ +

Do not attempt conditional recursion on the same source file, as this + will result in an infinite loop which will eventually exhaust all memory. +

+ +

output "filename" [, create]

+

This command can be used in place of the -o filename [-create] + command-line argument, or in addition to it, and can open multiple files + sequentially for output (only one output file can be open at a time.) The + create parameter, if specified, states to overwrite the target file if it + already exists. Otherwise, the file is opened in modification mode.

+ +

architecture name

+

This command will change the currently active architecture. An + architecture is essentially a processor that bass supports.

+ +

bass will first try to select any built-in architecture by the given + name, which allows bass to support architectures written as C++ modules. + Currently, the only built-in architecture is none, which is also the + default state at the start of assembly.

+ +

When no built-in architecture is found, bass will instead use its + table-driver assembler architecture. This architecture takes a text file as + input, which defines all supported opcodes and their encodings for a given + processor.

+ +

The name is transformed to name.arch, and bass tries to find said + file in two locations: first, in the architectures/ subdirectory next + to the main bass executable. And second, in + ~/.local/share/bass/architectures/ or + %localappdata%/bass/architectures/, depending upon your OS.

+ +

bass ships with a variety of pre-made table architecture files. On + Linux/BSD, users should run make install to place these files into + the appropriate location to be used.

+ +

bass is also extensible, so users can add their own table architecture + files to support additional processors. Architectures written in C++ will + however require recompiling bass to include said architecture.

+ +

Note that the architecture command will also change the current endian + mode of bass, to match that of the given processor architecture.

+ +

In the event that name does not match a built-in architecture, and + no appropriate name.arch file can be found, this command will + generate an error.

+ +

endian (lsb|msb)

+

This command controls whether multi-byte values (eg from dw and dd) are + output in little-endian (lsb) or big-endian (msb) format.

+ +

origin offset

+

This command seeks the output file write cursor to the specified + location.

+ +

base offset

+

This command creates a signed displacement against the origin value, + which is used when computing the pc (program counter) value for labels. This + command allows mapping file address space into a virtual memory address + space.

+ +

(enqueue|dequeue) variable [, ...]

+

This can be used to save and restore internal state. Currently supported + values are: origin, base, pc.

+ +

copy source, target, length

+

This command copies a block from the currently open file to another + location within the file. It does this by reading the entire block in first, + and then writing said block out, so be careful with overlapping addresses. +

+ +

insert [name, ] "filename" [, offset] [, length]

+

This command inserts a binary file into the target file. You can + optionally specify a name, offset and length. If you specify a name, it will + create a label by the given name, which contains the address where the data + begins, and it will also create name.size, which contains the size of the + included data. If you specify an offset, it will seek that far into the + referenced filename before copying the data. If you want to specify a + length, you must specify an offset first, and the length will determine the + maximum number of bytes to copy from the referenced filename.

+ +

delete "filename"

+

This command deletes a file from disk. Useful for removing temporary work + files needed by a project being assembled.

+ +

fill length [, with]

+

Inserts length number of bytes into the target file. The default + fill byte is 0x00, but can be specified via with.

+ +

map 'char' [, value] [, length]

+

Modifies the mappings for strings passed to db, dw, etc. This can be used + to map strings to custom tilemaps that do not follow traditional ASCII + values.

+ +

char is the first value to modify, value is the value to + map said char to, and length can be used for contiguous entries. For + instance, if A-Z appear sequentially, give a value of 26 for the length, to + avoid having to declare 26 separate assignments. Each step of length + increments both the char and value by exactly one, so the characters must be + contiguous with both ASCII and your custom map for this to work.

+ +

If you wish to restore the table to its default ASCII values, use the + following command:

+ +
map 0, 0, 256
+ +

d[bwldq] ("string"|variable|constant) [, ...]

+

Inserts binary data directly into the target file. db stores 8-bit + values, dw stores 16-bit values, dl stored 24-bit values, dd stored 32-bit + values and dq stores 64-bit values.

+ +

print ("string"|variable) [, ...]

+

Prints information to the terminal. Useful for debugging.

+ +

The print directive also supports formatting prefixes for variable or + constant expressions. These are: binary, hex, and char. + Example:

+ +
+    print "%", binary:15  //prints %1111
+    print "$", hex:65536  //prints $10000
+    print "'", char:65, "'"  //prints 'A'
+    
+ +

ds offset

+

Seeks forward or backward from the current output file write address. The + value can be positive (to seek forward) or negative (to seek backward.) This + is useful for skipping bytes when in file modification mode.

+ +

tracker enable|disable|reset

+

Tracks writes to a given output file when enabled. Selecting a new output + file automatically clears the tracking list. This is useful when using bass + as a patching assembler to detect when the same file address is written to + more than once. If this happens while the tracker is enabled, an error is + produced.

+ +

Note: disabling the tracker does not clear the previously tracked + addresses, in case you only wish to intentionally disable it for a short + time. If you want to clear the tracking history, use the reset argument.

+ +

notice "string"

+

Prints a notice to the terminal, but continues assembly.

+ +

warning "string"

+

Prints a warning to the terminal, but continues assembly.

+ +

error "string"

+

Prints an error to the terminal, and aborts assembly.

+ +

Functions

+

bass supports built-in functions. The syntax is equivalent to macros, + however they are used in expressions rather than as statements, and they + always return a numeric value.

+ +

Example:

+
+    seek(0x8000)  //this is a macro statement
+    ...
+    if pc() > 0x8fff {  //this is a function used inside an assembler statement
+      ...
+    }
+    
+ +

array.size(name)

+

Returns the number of elements in an array, or produces an error if the + array is not defined.

+ +

array.sort(name)

+

Sorts the specified array in ascending order.

+ +

assert(expression)

+

Produces an error if the expression evaluates to zero.

+ +

file.size("filename")

+

Returns the size of "filename" on disk, or produces an error if the file + is not found.

+ +

file.exists("filename")

+

Returns 1 if "filename" exists, or 0 if not.

+ +

read(address)

+

Reads a byte from the currently open output file, or produces an error if + there is no file currently open. The address provided is the origin, or + literal file address. The base offset is not factored in when this function + is used.

+ +

Important note: the resulting values read from a target file are only + valid during the write phase of assembly! If you rely on the value read + back during a previous pass to control outputting code, bass may assemble + the source code incorrectly. Use this function with caution. It is mostly + intended for when bass is used in patching mode.

+ +

origin()

+

Returns the current origin.

+ +

base()

+

Returns the current base.

+ +

pc()

+

Returns the current program counter (origin + base.)

+ +

The End

+

Hopefully this has been informative. The best way to learn is through + practice, so please do experiment and see what you can come up with!

+ +

Thank you for using bass!

+ + diff --git a/roms/snes-test-roms/bass-untech/nall/GNUmakefile b/roms/snes-test-roms/bass-untech/nall/GNUmakefile new file mode 100644 index 00000000..95833fd8 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/GNUmakefile @@ -0,0 +1,248 @@ +# disable built-in rules and variables +MAKEFLAGS := Rr +.SUFFIXES: + +[0-9] = 0 1 2 3 4 5 6 7 8 9 +[A-Z] = A B C D E F G H I J K L M N O P Q R S T U V W X Y Z +[a-z] = a b c d e f g h i j k l m n o p q r s t u v w x y z +[markup] = ` ~ ! @ \# $$ % ^ & * ( ) - _ = + [ { ] } \ | ; : ' " , < . > / ? +[all] = $([0-9]) $([A-Z]) $([a-z]) $([markup]) +[empty] := +[space] := $([empty]) $([empty]) + +# platform detection +ifeq ($(platform),) + ifeq ($(OS),Windows_NT) + platform := windows + endif +endif + +ifeq ($(platform),) + uname := $(shell uname) + ifeq ($(uname),) + platform := windows + else ifneq ($(findstring Windows,$(uname)),) + platform := windows + else ifneq ($(findstring NT,$(uname)),) + platform := windows + else ifneq ($(findstring Darwin,$(uname)),) + platform := macos + else ifneq ($(findstring Linux,$(uname)),) + platform := linux + else ifneq ($(findstring BSD,$(uname)),) + platform := bsd + else + $(error unknown platform, please specify manually.) + endif +endif + +# common commands +ifeq ($(shell echo ^^),^) + # cmd + delete = $(info Deleting $1 ...) @del /q $(subst /,\,$1) + rdelete = $(info Deleting $1 ...) @del /s /q $(subst /,\,$1) && if exist $(subst /,\,$1) (rmdir /s /q $(subst /,\,$1)) +else + # sh + delete = $(info Deleting $1 ...) @rm -f $1 + rdelete = $(info Deleting $1 ...) @rm -rf $1 +endif + +compiler.c = $(compiler) -x c -std=c11 +compiler.cpp = $(compiler) -x c++ -std=c++17 -fno-operator-names +compiler.objc = $(compiler) -x objective-c -std=c11 +compiler.objcpp = $(compiler) -x objective-c++ -std=c++17 -fno-operator-names + +flags.c = -x c -std=c11 +flags.cpp = -x c++ -std=c++17 -fno-operator-names +flags.objc = -x objective-c -std=c11 +flags.objcpp = -x objective-c++ -std=c++17 -fno-operator-names +flags.deps = -MMD -MP -MF $(@:.o=.d) + +# compiler detection +ifeq ($(compiler),) + ifeq ($(platform),windows) + compiler := g++ + compiler.cpp = $(compiler) -x c++ -std=gnu++17 + flags.cpp = -x c++ -std=gnu++17 -fno-operator-names + else ifeq ($(platform),macos) + compiler := clang++ + else ifeq ($(platform),linux) + compiler := g++ + else ifeq ($(platform),bsd) + compiler := clang++ + else + compiler := g++ + endif +endif + +# build optimization levels +ifeq ($(build),debug) + flags += -Og -g -DBUILD_DEBUG +else ifeq ($(build),stable) + flags += -O1 -DBUILD_STABLE +else ifeq ($(build),minified) + flags += -Os -DBUILD_MINIFIED +else ifeq ($(build),release) + flags += -O2 -DBUILD_RELEASE +else ifeq ($(build),optimized) + flags += -O3 -DBUILD_OPTIMIZED +else + $(error unrecognized build type.) +endif + +# link-time optimization +ifeq ($(lto),true) + flags += -fwhole-program -flto -fno-fat-lto-objects + options += -fwhole-program -flto=jobserver +endif + +# openmp support +ifeq ($(openmp),true) + # macOS Xcode does not ship with OpenMP support + ifneq ($(platform),macos) + flags += -fopenmp + options += -fopenmp + endif +endif + +# clang settings +ifeq ($(findstring clang++,$(compiler)),clang++) + flags += -fno-strict-aliasing -fwrapv -Wno-everything +# gcc settings +else ifeq ($(findstring g++,$(compiler)),g++) + flags += -fno-strict-aliasing -fwrapv -Wno-trigraphs +endif + +# windows settings +ifeq ($(platform),windows) + options += -mthreads -lpthread -lws2_32 -lole32 + options += $(if $(findstring g++,$(compiler)),-static -static-libgcc -static-libstdc++) + options += $(if $(findstring true,$(console)),-mconsole,-mwindows) + windres := windres +endif + +# macos settings +ifeq ($(platform),macos) + flags += -stdlib=libc++ + options += -lc++ -lobjc +endif + +# linux settings +ifeq ($(platform),linux) + options += -ldl +endif + +# bsd settings +ifeq ($(platform),bsd) + flags += -I/usr/local/include + options += -Wl,-rpath=/usr/local/lib + options += -Wl,-rpath=/usr/local/lib/gcc8 + options += -lstdc++ -lm +endif + +# threading support +ifeq ($(threaded),true) + ifneq ($(filter $(platform),linux bsd),) + flags += -pthread + options += -pthread -lrt + endif +endif + +# paths +ifeq ($(object.path),) + object.path := obj +endif + +ifeq ($(output.path),) + output.path := out +endif + +# rules +default: all; + +nall.verbose: + $(info Compiler Flags:) + $(foreach n,$(sort $(call unique,$(flags))),$(if $(filter-out -I%,$n),$(info $([space]) $n))) + $(info Linker Options:) + $(foreach n,$(sort $(call unique,$(options))),$(if $(filter-out -l%,$n),$(info $([space]) $n))) + +%.o: $< + $(info Compiling $(subst ../,,$<) ...) + @$(call compile) + +# function compile([arguments]) +compile = \ + $(strip \ + $(if $(filter %.c,$<), \ + $(compiler.c) $(flags.deps) $(flags) $1 -c $< -o $@ \ + ,$(if $(filter %.cpp,$<), \ + $(compiler.cpp) $(flags.deps) $(flags) $1 -c $< -o $@ \ + )) \ + ) + +# function rwildcard(directory, pattern) +rwildcard = \ + $(strip \ + $(filter $(if $2,$2,%), \ + $(foreach f, \ + $(wildcard $1*), \ + $(eval t = $(call rwildcard,$f/)) \ + $(if $t,$t,$f) \ + ) \ + ) \ + ) + +# function unique(source) +unique = \ + $(eval __temp :=) \ + $(strip \ + $(foreach s,$1,$(if $(filter $s,$(__temp)),,$(eval __temp += $s))) \ + $(__temp) \ + ) + +# function strtr(source, from, to) +strtr = \ + $(eval __temp := $1) \ + $(strip \ + $(foreach c, \ + $(join $(addsuffix :,$2),$3), \ + $(eval __temp := \ + $(subst $(word 1,$(subst :, ,$c)),$(word 2,$(subst :, ,$c)),$(__temp)) \ + ) \ + ) \ + $(__temp) \ + ) + +# function strupper(source) +strupper = $(call strtr,$1,$([a-z]),$([A-Z])) + +# function strlower(source) +strlower = $(call strtr,$1,$([A-Z]),$([a-z])) + +# function strlen(source) +strlen = \ + $(eval __temp := $(subst $([space]),_,$1)) \ + $(words \ + $(strip \ + $(foreach c, \ + $([all]), \ + $(eval __temp := \ + $(subst $c,$c ,$(__temp)) \ + ) \ + ) \ + $(__temp) \ + ) \ + ) + +# function streq(source) +streq = $(if $(filter-out xx,x$(subst $1,,$2)$(subst $2,,$1)x),,1) + +# function strne(source) +strne = $(if $(filter-out xx,x$(subst $1,,$2)$(subst $2,,$1)x),1,) + +# prefix +ifeq ($(platform),windows) + prefix := $(subst $([space]),\$([space]),$(strip $(call strtr,$(LOCALAPPDATA),\,/))) +else + prefix := $(HOME)/.local +endif diff --git a/roms/snes-test-roms/bass-untech/nall/adaptive-array.hpp b/roms/snes-test-roms/bass-untech/nall/adaptive-array.hpp new file mode 100644 index 00000000..9ca84e7c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/adaptive-array.hpp @@ -0,0 +1,64 @@ +//deprecated + +#pragma once + +#include +#include + +namespace nall { + +template +struct adaptive_array { + auto capacity() const -> uint { return Capacity; } + auto size() const -> uint { return _size; } + + auto reset() -> void { + for(uint n : range(_size)) _pool.t[n].~T(); + _size = 0; + } + + auto operator[](uint index) -> T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(index >= Capacity) throw out_of_bounds{}; + #endif + return _pool.t[index]; + } + + auto operator[](uint index) const -> const T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(index >= Capacity) throw out_of_bounds{}; + #endif + return _pool.t[index]; + } + + auto append() -> T& { + new(_pool.t + _size) T; + return _pool.t[_size++]; + } + + auto append(const T& value) -> void { + new(_pool.t + _size++) T(value); + } + + auto append(T&& value) -> void { + new(_pool.t + _size++) T(move(value)); + } + + auto begin() { return &_pool.t[0]; } + auto end() { return &_pool.t[_size]; } + + auto begin() const { return &_pool.t[0]; } + auto end() const { return &_pool.t[_size]; } + +private: + union U { + U() {} + ~U() {} + T t[Capacity]; + } _pool; + uint _size = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/algorithm.hpp b/roms/snes-test-roms/bass-untech/nall/algorithm.hpp new file mode 100644 index 00000000..34565f11 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/algorithm.hpp @@ -0,0 +1,26 @@ +#pragma once + +#include + +#undef min +#undef max + +namespace nall { + +template constexpr auto min(const T& t, const U& u) -> T { + return t < u ? t : (T)u; +} + +template constexpr auto min(const T& t, const U& u, P&&... p) -> T { + return t < u ? min(t, forward

(p)...) : min(u, forward

(p)...); +} + +template constexpr auto max(const T& t, const U& u) -> T { + return t > u ? t : (T)u; +} + +template constexpr auto max(const T& t, const U& u, P&&... p) -> T { + return t > u ? max(t, forward

(p)...) : max(u, forward

(p)...); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/any.hpp b/roms/snes-test-roms/bass-untech/nall/any.hpp new file mode 100644 index 00000000..d7e789a9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/any.hpp @@ -0,0 +1,83 @@ +#pragma once + +#include +#include + +namespace nall { + +struct any { + any() = default; + any(const any& source) { operator=(source); } + any(any&& source) { operator=(move(source)); } + template any(const T& value) { operator=(value); } + ~any() { reset(); } + + explicit operator bool() const { return container; } + auto reset() -> void { if(container) { delete container; container = nullptr; } } + + auto type() const -> const std::type_info& { + return container ? container->type() : typeid(void); + } + + template auto is() const -> bool { + return type() == typeid(typename remove_reference::type); + } + + template auto get() -> T& { + if(!is()) throw; + return static_cast::type>*>(container)->value; + } + + template auto get() const -> const T& { + if(!is()) throw; + return static_cast::type>*>(container)->value; + } + + template auto get(const T& fallback) const -> const T& { + if(!is()) return fallback; + return static_cast::type>*>(container)->value; + } + + template auto operator=(const T& value) -> any& { + using auto_t = typename conditional::value, typename remove_extent::type>::type*, T>::type; + + if(type() == typeid(auto_t)) { + static_cast*>(container)->value = (auto_t)value; + } else { + if(container) delete container; + container = new holder((auto_t)value); + } + + return *this; + } + + auto operator=(const any& source) -> any& { + if(container) { delete container; container = nullptr; } + if(source.container) container = source.container->copy(); + return *this; + } + + auto operator=(any&& source) -> any& { + if(container) delete container; + container = source.container; + source.container = nullptr; + return *this; + } + +private: + struct placeholder { + virtual ~placeholder() = default; + virtual auto type() const -> const std::type_info& = 0; + virtual auto copy() const -> placeholder* = 0; + }; + placeholder* container = nullptr; + + template struct holder : placeholder { + holder(const T& value) : value(value) {} + auto type() const -> const std::type_info& { return typeid(T); } + auto copy() const -> placeholder* { return new holder(value); } + T value; + }; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/arguments.hpp b/roms/snes-test-roms/bass-untech/nall/arguments.hpp new file mode 100644 index 00000000..6fb706d1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/arguments.hpp @@ -0,0 +1,161 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall { + +struct Arguments { + Arguments(int argc, char** argv); + Arguments(vector arguments); + + explicit operator bool() const { return (bool)arguments; } + auto size() const -> uint { return arguments.size(); } + + auto operator[](uint index) -> string& { return arguments[index]; } + auto operator[](uint index) const -> const string& { return arguments[index]; } + + auto programPath() const -> string; + auto programName() const -> string; + auto programLocation() const -> string; + + auto find(string_view name) const -> bool; + auto find(string_view name, bool& argument) const -> bool; + auto find(string_view name, string& argument) const -> bool; + + auto begin() const { return arguments.begin(); } + auto end() const { return arguments.end(); } + + auto rbegin() const { return arguments.rbegin(); } + auto rend() const { return arguments.rend(); } + + auto take() -> string; + auto take(string_view name) -> bool; + auto take(string_view name, bool& argument) -> bool; + auto take(string_view name, string& argument) -> bool; + + auto begin() { return arguments.begin(); } + auto end() { return arguments.end(); } + + auto rbegin() { return arguments.rbegin(); } + auto rend() { return arguments.rend(); } + +private: + auto construct() -> void; + + string programArgument; + vector arguments; +}; + +inline auto Arguments::construct() -> void { + if(!arguments) return; + + //extract and pre-process program argument + programArgument = arguments.takeFirst(); + programArgument = {Path::real(programArgument), Location::file(programArgument)}; + + //normalize path and file arguments + for(auto& argument : arguments) { + if(directory::exists(argument)) argument.transform("\\", "/").trimRight("/").append("/"); + else if(file::exists(argument)) argument.transform("\\", "/").trimRight("/"); + } +} + +inline Arguments::Arguments(int argc, char** argv) { + #if defined(PLATFORM_WINDOWS) + utf8_arguments(argc, argv); + #endif + for(uint index : range(argc)) arguments.append(argv[index]); + construct(); +} + +inline Arguments::Arguments(vector arguments) { + this->arguments = arguments; + construct(); +} + +inline auto Arguments::programPath() const -> string { + return Location::path(programArgument); +} + +inline auto Arguments::programName() const -> string { + return Location::file(programArgument); +} + +inline auto Arguments::programLocation() const -> string { + return programArgument; +} + +inline auto Arguments::find(string_view name) const -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name)) { + return true; + } + } + return false; +} + +inline auto Arguments::find(string_view name, bool& argument) const -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name) && arguments.size() >= index + && (arguments[index + 1] == "true" || arguments[index + 1] == "false")) { + argument = arguments[index + 1] == "true"; + return true; + } + } + return false; +} + +inline auto Arguments::find(string_view name, string& argument) const -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name) && arguments.size() >= index) { + argument = arguments[index + 1]; + return true; + } + } + return false; +} + +// + +inline auto Arguments::take() -> string { + if(!arguments) return {}; + return arguments.takeFirst(); +} + +inline auto Arguments::take(string_view name) -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name)) { + arguments.remove(index); + return true; + } + } + return false; +} + +inline auto Arguments::take(string_view name, bool& argument) -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name) && arguments.size() > index + 1 + && (arguments[index + 1] == "true" || arguments[index + 1] == "false")) { + arguments.remove(index); + argument = arguments.take(index) == "true"; + return true; + } + } + return false; +} + +inline auto Arguments::take(string_view name, string& argument) -> bool { + for(uint index : range(arguments.size())) { + if(arguments[index].match(name) && arguments.size() > index + 1) { + arguments.remove(index); + argument = arguments.take(index); + return true; + } + } + return false; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/arithmetic.hpp b/roms/snes-test-roms/bass-untech/nall/arithmetic.hpp new file mode 100644 index 00000000..388370f1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/arithmetic.hpp @@ -0,0 +1,89 @@ +#pragma once + +//multi-precision arithmetic +//warning: each size is quadratically more expensive than the size before it! + +#include +#include +#include +#include + +#include + +namespace nall { + template struct ArithmeticNatural; + template<> struct ArithmeticNatural< 8> { using type = uint8_t; }; + template<> struct ArithmeticNatural< 16> { using type = uint16_t; }; + template<> struct ArithmeticNatural< 32> { using type = uint32_t; }; + template<> struct ArithmeticNatural< 64> { using type = uint64_t; }; + #if INTMAX_BITS >= 128 + template<> struct ArithmeticNatural<128> { using type = uint128_t; }; + #endif +} + +#if INTMAX_BITS < 128 +#define PairBits 128 +#define TypeBits 64 +#define HalfBits 32 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits +#endif + +#define PairBits 256 +#define TypeBits 128 +#define HalfBits 64 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +#define PairBits 512 +#define TypeBits 256 +#define HalfBits 128 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +#define PairBits 1024 +#define TypeBits 512 +#define HalfBits 256 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +#define PairBits 2048 +#define TypeBits 1024 +#define HalfBits 512 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +#define PairBits 4096 +#define TypeBits 2048 +#define HalfBits 1024 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +#define PairBits 8192 +#define TypeBits 4096 +#define HalfBits 2048 +#include +#undef PairBits +#undef TypeBits +#undef HalfBits + +namespace nall { + //TODO: these types are for expressing smaller bit ranges in class interfaces + //for instance, XChaCha20 taking a 192-bit nonce + //however, they still allow more bits than expressed ... + //some sort of wrapper needs to be devised to ensure these sizes are masked and wrap appropriately + + using uint192_t = uint256_t; +} diff --git a/roms/snes-test-roms/bass-untech/nall/arithmetic/barrett.hpp b/roms/snes-test-roms/bass-untech/nall/arithmetic/barrett.hpp new file mode 100644 index 00000000..7774b027 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/arithmetic/barrett.hpp @@ -0,0 +1,28 @@ +#pragma once + +namespace nall { + +template struct BarrettReduction { + using type = typename ArithmeticNatural<1 * Bits>::type; + using pair = typename ArithmeticNatural<2 * Bits>::type; + + explicit BarrettReduction(type modulo) : modulo(modulo), factor(pair(1) + -pair(modulo) / modulo) {} + + //return => value % modulo + auto operator()(pair value) const -> type { + pair hi, lo; + mul(value, factor, hi, lo); + pair remainder = value - hi * modulo; + return remainder < modulo ? remainder : remainder - modulo; + } + +private: + const pair modulo; + const pair factor; +}; + +template auto operator%(T value, const BarrettReduction& modulo) { + return modulo(value); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/arithmetic/natural.hpp b/roms/snes-test-roms/bass-untech/nall/arithmetic/natural.hpp new file mode 100644 index 00000000..cc1bd907 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/arithmetic/natural.hpp @@ -0,0 +1,344 @@ +#include + +#define ConcatenateType(Size) uint##Size##_t +#define DeclareType(Size) ConcatenateType(Size) + +#define Pair DeclareType(PairBits) +#define Type DeclareType(TypeBits) +#define Half DeclareType(HalfBits) + +//pick the larger of two types to prevent unnecessary data clamping +#define Cast (typename conditional= sizeof(T), Pair, T>::type) + +namespace nall { +//namespace Arithmetic { + +struct Pair { + Pair() = default; + explicit constexpr Pair(const Pair& source) : hi(source.hi), lo(source.lo) {} + template constexpr Pair(const Hi& hi, const Lo& lo) : hi(hi), lo(lo) {} + template Pair(const T& source) { _set(*this, source); } + + explicit operator bool() const { return hi | lo; } + template operator T() const { T value; _get(*this, value); return value; } + + auto operator+() const -> Pair { return *this; } + auto operator-() const -> Pair { return Pair(0) - *this; } + auto operator~() const -> Pair { return {~hi, ~lo}; } + auto operator!() const -> bool { return !(hi || lo); } + + auto operator++() -> Pair& { lo++; hi += lo == 0; return *this; } + auto operator--() -> Pair& { hi -= lo == 0; lo--; return *this; } + + auto operator++(int) -> Pair { Pair r = *this; lo++; hi += lo == 0; return r; } + auto operator--(int) -> Pair { Pair r = *this; hi -= lo == 0; lo--; return r; } + + auto operator* (const Pair& rhs) const -> Pair { return mul(*this, rhs); } + auto operator/ (const Pair& rhs) const -> Pair { Pair q, r; div(*this, rhs, q, r); return q; } + auto operator% (const Pair& rhs) const -> Pair { Pair q, r; div(*this, rhs, q, r); return r; } + auto operator+ (const Pair& rhs) const -> Pair { return {hi + rhs.hi + (lo + rhs.lo < lo), lo + rhs.lo}; } + auto operator- (const Pair& rhs) const -> Pair { return {hi - rhs.hi - (lo - rhs.lo > lo), lo - rhs.lo}; } + auto operator<<(const Pair& rhs) const -> Pair { return shl(*this, rhs); } + auto operator>>(const Pair& rhs) const -> Pair { return shr(*this, rhs); } + auto operator& (const Pair& rhs) const -> Pair { return {hi & rhs.hi, lo & rhs.lo}; } + auto operator| (const Pair& rhs) const -> Pair { return {hi | rhs.hi, lo | rhs.lo}; } + auto operator^ (const Pair& rhs) const -> Pair { return {hi ^ rhs.hi, lo ^ rhs.lo}; } + auto operator==(const Pair& rhs) const -> bool { return hi == rhs.hi && lo == rhs.lo; } + auto operator!=(const Pair& rhs) const -> bool { return hi != rhs.hi || lo != rhs.lo; } + auto operator>=(const Pair& rhs) const -> bool { return hi > rhs.hi || (hi == rhs.hi && lo >= rhs.lo); } + auto operator<=(const Pair& rhs) const -> bool { return hi < rhs.hi || (hi == rhs.hi && lo <= rhs.lo); } + auto operator> (const Pair& rhs) const -> bool { return hi > rhs.hi || (hi == rhs.hi && lo > rhs.lo); } + auto operator< (const Pair& rhs) const -> bool { return hi < rhs.hi || (hi == rhs.hi && lo < rhs.lo); } + + template auto& operator*= (const T& rhs) { return *this = *this * Pair(rhs); } + template auto& operator/= (const T& rhs) { return *this = *this / Pair(rhs); } + template auto& operator%= (const T& rhs) { return *this = *this % Pair(rhs); } + template auto& operator+= (const T& rhs) { return *this = *this + Pair(rhs); } + template auto& operator-= (const T& rhs) { return *this = *this - Pair(rhs); } + template auto& operator<<=(const T& rhs) { return *this = *this << Pair(rhs); } + template auto& operator>>=(const T& rhs) { return *this = *this >> Pair(rhs); } + template auto& operator&= (const T& rhs) { return *this = *this & Pair(rhs); } + template auto& operator|= (const T& rhs) { return *this = *this | Pair(rhs); } + template auto& operator^= (const T& rhs) { return *this = *this ^ Pair(rhs); } + + template auto operator* (const T& rhs) const { return Cast(*this) * Cast(rhs); } + template auto operator/ (const T& rhs) const { return Cast(*this) / Cast(rhs); } + template auto operator% (const T& rhs) const { return Cast(*this) % Cast(rhs); } + template auto operator+ (const T& rhs) const { return Cast(*this) + Cast(rhs); } + template auto operator- (const T& rhs) const { return Cast(*this) - Cast(rhs); } + template auto operator<<(const T& rhs) const { return Cast(*this) << Cast(rhs); } + template auto operator>>(const T& rhs) const { return Cast(*this) >> Cast(rhs); } + template auto operator& (const T& rhs) const { return Cast(*this) & Cast(rhs); } + template auto operator| (const T& rhs) const { return Cast(*this) | Cast(rhs); } + template auto operator^ (const T& rhs) const { return Cast(*this) ^ Cast(rhs); } + + template auto operator==(const T& rhs) const -> bool { return Cast(*this) == Cast(rhs); } + template auto operator!=(const T& rhs) const -> bool { return Cast(*this) != Cast(rhs); } + template auto operator>=(const T& rhs) const -> bool { return Cast(*this) >= Cast(rhs); } + template auto operator<=(const T& rhs) const -> bool { return Cast(*this) <= Cast(rhs); } + template auto operator> (const T& rhs) const -> bool { return Cast(*this) > Cast(rhs); } + template auto operator< (const T& rhs) const -> bool { return Cast(*this) < Cast(rhs); } + +private: + Type lo; + Type hi; + + friend auto upper(const Pair&) -> Type; + friend auto lower(const Pair&) -> Type; + friend auto bits(Pair) -> uint; + friend auto square(const Pair&) -> Pair; + friend auto square(const Pair&, Pair&, Pair&) -> void; + friend auto mul(const Pair&, const Pair&) -> Pair; + friend auto mul(const Pair&, const Pair&, Pair&, Pair&) -> void; + friend auto div(const Pair&, const Pair&, Pair&, Pair&) -> void; + template friend auto shl(const Pair&, const T&) -> Pair; + template friend auto shr(const Pair&, const T&) -> Pair; +}; + +template<> struct ArithmeticNatural { + using type = Pair; +}; + +#define ConcatenateUDL(Size) _u##Size +#define DeclareUDL(Size) ConcatenateUDL(Size) + +alwaysinline auto operator"" DeclareUDL(PairBits)(const char* s) -> Pair { + Pair p = 0; + if(s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) { + s += 2; + while(*s) { + auto c = *s++; + if(c == '\''); + else if(c >= '0' && c <= '9') p = (p << 4) + (c - '0'); + else if(c >= 'a' && c <= 'f') p = (p << 4) + (c - 'a' + 10); + else if(c >= 'A' && c <= 'F') p = (p << 4) + (c - 'A' + 10); + else break; + } + } else { + while(*s) { + auto c = *s++; + if(c == '\''); + else if(c >= '0' && c <= '9') p = (p << 3) + (p << 1) + (c - '0'); + else break; + } + } + return p; +} + +#undef ConcatenateUDL +#undef DeclareUDL + +template alwaysinline auto _set(Pair& lhs, const T& rhs) -> enable_if_t<(sizeof(Pair) == sizeof(T))> { + lhs = rhs; +} + +template alwaysinline auto _set(Pair& lhs, const T& rhs) -> enable_if_t<(sizeof(Pair) > sizeof(T))> { + lhs = {0, rhs}; +} + +template alwaysinline auto _set(Pair& lhs, const T& rhs) -> enable_if_t<(sizeof(Pair) < sizeof(T))> { + lhs = {lower(rhs) >> TypeBits, lower(rhs)}; +} + +template alwaysinline auto _get(const Pair& lhs, T& rhs) -> enable_if_t<(sizeof(T) == sizeof(Pair))> { + rhs = lhs; +} + +template alwaysinline auto _get(const Pair& lhs, T& rhs) -> enable_if_t<(sizeof(T) > sizeof(Pair))> { + rhs = {0, lhs}; +} + +template alwaysinline auto _get(const Pair& lhs, T& rhs) -> enable_if_t<(sizeof(T) < sizeof(Pair))> { + rhs = lower(lhs); +} + +alwaysinline auto upper(const Pair& value) -> Type { return value.hi; } +alwaysinline auto lower(const Pair& value) -> Type { return value.lo; } + +alwaysinline auto bits(Pair value) -> uint { + if(value.hi) { + uint bits = TypeBits; + while(value.hi) value.hi >>= 1, bits++; + return bits; + } else { + uint bits = 0; + while(value.lo) value.lo >>= 1, bits++; + return bits; + } +} + +//Bits * Bits => Bits +inline auto square(const Pair& lhs) -> Pair { + static const Type Mask = (Type(0) - 1) >> HalfBits; + Type a = lhs.hi >> HalfBits, b = lhs.hi & Mask, c = lhs.lo >> HalfBits, d = lhs.lo & Mask; + Type dd = square(d), dc = d * c, db = d * b, da = d * a; + Type cc = square(c), cb = c * b; + + Pair r0 = Pair(dd); + Pair r1 = Pair(dc) + Pair(dc) + Pair(r0 >> HalfBits); + Pair r2 = Pair(db) + Pair(cc) + Pair(db) + Pair(r1 >> HalfBits); + Pair r3 = Pair(da) + Pair(cb) + Pair(cb) + Pair(da) + Pair(r2 >> HalfBits); + + return {(r3.lo & Mask) << HalfBits | (r2.lo & Mask), (r1.lo & Mask) << HalfBits | (r0.lo & Mask)}; +} + +//Bits * Bits => 2 * Bits +inline auto square(const Pair& lhs, Pair& hi, Pair& lo) -> void { + static const Type Mask = (Type(0) - 1) >> HalfBits; + Type a = lhs.hi >> HalfBits, b = lhs.hi & Mask, c = lhs.lo >> HalfBits, d = lhs.lo & Mask; + Type dd = square(d), dc = d * c, db = d * b, da = d * a; + Type cc = square(c), cb = c * b, ca = c * a; + Type bb = square(b), ba = b * a; + Type aa = square(a); + + Pair r0 = Pair(dd); + Pair r1 = Pair(dc) + Pair(dc) + Pair(r0 >> HalfBits); + Pair r2 = Pair(db) + Pair(cc) + Pair(db) + Pair(r1 >> HalfBits); + Pair r3 = Pair(da) + Pair(cb) + Pair(cb) + Pair(da) + Pair(r2 >> HalfBits); + Pair r4 = Pair(ca) + Pair(bb) + Pair(ca) + Pair(r3 >> HalfBits); + Pair r5 = Pair(ba) + Pair(ba) + Pair(r4 >> HalfBits); + Pair r6 = Pair(aa) + Pair(r5 >> HalfBits); + Pair r7 = Pair(r6 >> HalfBits); + + hi = {(r7.lo & Mask) << HalfBits | (r6.lo & Mask), (r5.lo & Mask) << HalfBits | (r4.lo & Mask)}; + lo = {(r3.lo & Mask) << HalfBits | (r2.lo & Mask), (r1.lo & Mask) << HalfBits | (r0.lo & Mask)}; +} + +//Bits * Bits => Bits +alwaysinline auto mul(const Pair& lhs, const Pair& rhs) -> Pair { + static const Type Mask = (Type(0) - 1) >> HalfBits; + Type a = lhs.hi >> HalfBits, b = lhs.hi & Mask, c = lhs.lo >> HalfBits, d = lhs.lo & Mask; + Type e = rhs.hi >> HalfBits, f = rhs.hi & Mask, g = rhs.lo >> HalfBits, h = rhs.lo & Mask; + + Pair r0 = Pair(d * h); + Pair r1 = Pair(c * h) + Pair(d * g) + Pair(r0 >> HalfBits); + Pair r2 = Pair(b * h) + Pair(c * g) + Pair(d * f) + Pair(r1 >> HalfBits); + Pair r3 = Pair(a * h) + Pair(b * g) + Pair(c * f) + Pair(d * e) + Pair(r2 >> HalfBits); + + return {(r3.lo & Mask) << HalfBits | (r2.lo & Mask), (r1.lo & Mask) << HalfBits | (r0.lo & Mask)}; +} + +//Bits * Bits => 2 * Bits +alwaysinline auto mul(const Pair& lhs, const Pair& rhs, Pair& hi, Pair& lo) -> void { + static const Type Mask = (Type(0) - 1) >> HalfBits; + Type a = lhs.hi >> HalfBits, b = lhs.hi & Mask, c = lhs.lo >> HalfBits, d = lhs.lo & Mask; + Type e = rhs.hi >> HalfBits, f = rhs.hi & Mask, g = rhs.lo >> HalfBits, h = rhs.lo & Mask; + + Pair r0 = Pair(d * h); + Pair r1 = Pair(c * h) + Pair(d * g) + Pair(r0 >> HalfBits); + Pair r2 = Pair(b * h) + Pair(c * g) + Pair(d * f) + Pair(r1 >> HalfBits); + Pair r3 = Pair(a * h) + Pair(b * g) + Pair(c * f) + Pair(d * e) + Pair(r2 >> HalfBits); + Pair r4 = Pair(a * g) + Pair(b * f) + Pair(c * e) + Pair(r3 >> HalfBits); + Pair r5 = Pair(a * f) + Pair(b * e) + Pair(r4 >> HalfBits); + Pair r6 = Pair(a * e) + Pair(r5 >> HalfBits); + Pair r7 = Pair(r6 >> HalfBits); + + hi = {(r7.lo & Mask) << HalfBits | (r6.lo & Mask), (r5.lo & Mask) << HalfBits | (r4.lo & Mask)}; + lo = {(r3.lo & Mask) << HalfBits | (r2.lo & Mask), (r1.lo & Mask) << HalfBits | (r0.lo & Mask)}; +} + +alwaysinline auto div(const Pair& lhs, const Pair& rhs, Pair& quotient, Pair& remainder) -> void { + if(!rhs) throw std::runtime_error("division by zero"); + quotient = 0, remainder = lhs; + if(!lhs || lhs < rhs) return; + + auto count = bits(lhs) - bits(rhs); + Pair x = rhs << count; + Pair y = Pair(1) << count; + if(x > remainder) x >>= 1, y >>= 1; + while(remainder >= rhs) { + if(remainder >= x) remainder -= x, quotient |= y; + x >>= 1, y >>= 1; + } +} + +template alwaysinline auto shl(const Pair& lhs, const T& rhs) -> Pair { + if(!rhs) return lhs; + auto shift = (uint)rhs; + if(shift < TypeBits) { + return {lhs.hi << shift | lhs.lo >> (TypeBits - shift), lhs.lo << shift}; + } else { + return {lhs.lo << (shift - TypeBits), 0}; + } +} + +template alwaysinline auto shr(const Pair& lhs, const T& rhs) -> Pair { + if(!rhs) return lhs; + auto shift = (uint)rhs; + if(shift < TypeBits) { + return {lhs.hi >> shift, lhs.hi << (TypeBits - shift) | lhs.lo >> shift}; + } else { + return {0, lhs.hi >> (shift - TypeBits)}; + } +} + +template alwaysinline auto rol(const Pair& lhs, const T& rhs) -> Pair { + return lhs << rhs | lhs >> (PairBits - rhs); +} + +template alwaysinline auto ror(const Pair& lhs, const T& rhs) -> Pair { + return lhs >> rhs | lhs << (PairBits - rhs); +} + +#define EI enable_if_t::value> + +template auto& operator*= (T& lhs, const Pair& rhs) { return lhs = lhs * T(rhs); } +template auto& operator/= (T& lhs, const Pair& rhs) { return lhs = lhs / T(rhs); } +template auto& operator%= (T& lhs, const Pair& rhs) { return lhs = lhs % T(rhs); } +template auto& operator+= (T& lhs, const Pair& rhs) { return lhs = lhs + T(rhs); } +template auto& operator-= (T& lhs, const Pair& rhs) { return lhs = lhs - T(rhs); } +template auto& operator<<=(T& lhs, const Pair& rhs) { return lhs = lhs << T(rhs); } +template auto& operator>>=(T& lhs, const Pair& rhs) { return lhs = lhs >> T(rhs); } +template auto& operator&= (T& lhs, const Pair& rhs) { return lhs = lhs & T(rhs); } +template auto& operator|= (T& lhs, const Pair& rhs) { return lhs = lhs | T(rhs); } +template auto& operator^= (T& lhs, const Pair& rhs) { return lhs = lhs ^ T(rhs); } + +template auto operator* (const T& lhs, const Pair& rhs) { return Cast(lhs) * Cast(rhs); } +template auto operator/ (const T& lhs, const Pair& rhs) { return Cast(lhs) / Cast(rhs); } +template auto operator% (const T& lhs, const Pair& rhs) { return Cast(lhs) % Cast(rhs); } +template auto operator+ (const T& lhs, const Pair& rhs) { return Cast(lhs) + Cast(rhs); } +template auto operator- (const T& lhs, const Pair& rhs) { return Cast(lhs) - Cast(rhs); } +template auto operator<<(const T& lhs, const Pair& rhs) { return Cast(lhs) << Cast(rhs); } +template auto operator>>(const T& lhs, const Pair& rhs) { return Cast(lhs) >> Cast(rhs); } +template auto operator& (const T& lhs, const Pair& rhs) { return Cast(lhs) & Cast(rhs); } +template auto operator| (const T& lhs, const Pair& rhs) { return Cast(lhs) | Cast(rhs); } +template auto operator^ (const T& lhs, const Pair& rhs) { return Cast(lhs) ^ Cast(rhs); } + +template auto operator==(const T& lhs, const Pair& rhs) { return Cast(lhs) == Cast(rhs); } +template auto operator!=(const T& lhs, const Pair& rhs) { return Cast(lhs) != Cast(rhs); } +template auto operator>=(const T& lhs, const Pair& rhs) { return Cast(lhs) >= Cast(rhs); } +template auto operator<=(const T& lhs, const Pair& rhs) { return Cast(lhs) <= Cast(rhs); } +template auto operator> (const T& lhs, const Pair& rhs) { return Cast(lhs) > Cast(rhs); } +template auto operator< (const T& lhs, const Pair& rhs) { return Cast(lhs) < Cast(rhs); } + +#undef EI + +template<> struct stringify { + stringify(Pair source) { + char _output[1 + sizeof(Pair) * 3]; + auto p = (char*)&_output; + do { + Pair quotient, remainder; + div(source, 10, quotient, remainder); + *p++ = remainder + '0'; + source = quotient; + } while(source); + _size = p - _output; + *p = 0; + for(int x = _size - 1, y = 0; x >= 0 && y < _size; x--, y++) _data[x] = _output[y]; + } + + auto data() const -> const char* { return _data; } + auto size() const -> uint { return _size; } + char _data[1 + sizeof(Pair) * 3]; + uint _size; +}; + +} + +#undef ConcatenateType +#undef DeclareType +#undef Pair +#undef Type +#undef Half +#undef Cast diff --git a/roms/snes-test-roms/bass-untech/nall/arithmetic/unsigned.hpp b/roms/snes-test-roms/bass-untech/nall/arithmetic/unsigned.hpp new file mode 100644 index 00000000..5ed7ecd6 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/arithmetic/unsigned.hpp @@ -0,0 +1,61 @@ +#pragma once + +namespace nall { + +template::value>> +inline auto upper(T value) -> T { + return value >> sizeof(T) * 4; +} + +template::value>> +inline auto lower(T value) -> T { + static const T Mask = ~T(0) >> sizeof(T) * 4; + return value & Mask; +} + +template::value>, enable_if_t::value>> +inline auto mul(T lhs, U rhs) -> uintmax { + return lhs * rhs; +} + +template::value>> +inline auto square(T value) -> uintmax { + return value * value; +} + +template +inline auto rol(T lhs, U rhs, enable_if_t::value>* = 0) -> T { + return lhs << rhs | lhs >> sizeof(T) * 8 - rhs; +} + +template +inline auto ror(T lhs, U rhs, enable_if_t::value>* = 0) -> T { + return lhs >> rhs | lhs << sizeof(T) * 8 - rhs; +} + +#if INTMAX_BITS >= 128 +inline auto operator"" _u128(const char* s) -> uint128_t { + uint128_t p = 0; + if(s[0] == '0' && (s[1] == 'x' || s[1] == 'X')) { + s += 2; + while(*s) { + auto c = *s++; + if(c == '\''); + else if(c >= '0' && c <= '9') p = (p << 4) + (c - '0'); + else if(c >= 'a' && c <= 'f') p = (p << 4) + (c - 'a' + 10); + else if(c >= 'A' && c <= 'F') p = (p << 4) + (c - 'A' + 10); + else break; + } + } else { + while(*s) { + auto c = *s++; + if(c == '\''); + else if(c >= '0' && c <= '9') p = (p << 3) + (p << 1) + (c - '0'); + else break; + } + } + return p; +} +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/array-span.hpp b/roms/snes-test-roms/bass-untech/nall/array-span.hpp new file mode 100644 index 00000000..4590e42e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/array-span.hpp @@ -0,0 +1,93 @@ +#pragma once + +#include + +namespace nall { + +template struct array_span : array_view { + using type = array_span; + using super = array_view; + + array_span() { + super::_data = nullptr; + super::_size = 0; + } + + array_span(nullptr_t) { + super::_data = nullptr; + super::_size = 0; + } + + array_span(void* data, uint64_t size) { + super::_data = (T*)data; + super::_size = (int)size; + } + + operator T*() { return (T*)super::operator const T*(); } + + auto operator[](uint index) -> T& { return (T&)super::operator[](index); } + + template auto data() -> U* { return (U*)super::_data; } + template auto data() const -> const U* { return (const U*)super::_data; } + + auto begin() -> iterator { return {(T*)super::_data, (uint)0}; } + auto end() -> iterator { return {(T*)super::_data, (uint)super::_size}; } + + auto rbegin() -> reverse_iterator { return {(T*)super::_data, (uint)super::_size - 1}; } + auto rend() -> reverse_iterator { return {(T*)super::_data, (uint)-1}; } + + auto write(T value) -> void { + operator[](0) = value; + super::_data++; + super::_size--; + } + + auto span(uint offset, uint length) const -> type { + #ifdef DEBUG + struct out_of_bounds {}; + if(offset + length >= super::_size) throw out_of_bounds{}; + #endif + return {super::_data + offset, length}; + } + + //array_span specializations + template auto writel(U value, uint size) -> void; + template auto writem(U value, uint size) -> void; + template auto writevn(U value, uint size) -> void; + template auto writevi(U value, uint size) -> void; +}; + +//array_span + +template<> inline auto array_span::write(uint8_t value) -> void { + operator[](0) = value; + _data++; + _size--; +} + +template<> template inline auto array_span::writel(U value, uint size) -> void { + for(uint byte : range(size)) write(value >> byte * 8); +} + +template<> template inline auto array_span::writem(U value, uint size) -> void { + for(uint byte : reverse(range(size))) write(value >> byte * 8); +} + +template<> template inline auto array_span::writevn(U value, uint size) -> void { + while(true) { + auto byte = value & 0x7f; + value >>= 7; + if(value == 0) return write(0x80 | byte); + write(byte); + value--; + } +} + +template<> template inline auto array_span::writevi(U value, uint size) -> void { + bool negate = value < 0; + if(negate) value = ~value; + value = value << 1 | negate; + writevn(value); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/array-view.hpp b/roms/snes-test-roms/bass-untech/nall/array-view.hpp new file mode 100644 index 00000000..06e68994 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/array-view.hpp @@ -0,0 +1,138 @@ +#pragma once + +#include +#include +#include + +namespace nall { + +template struct array_view { + using type = array_view; + + array_view() { + _data = nullptr; + _size = 0; + } + + array_view(nullptr_t) { + _data = nullptr; + _size = 0; + } + + array_view(const void* data, uint64_t size) { + _data = (const T*)data; + _size = (int)size; + } + + explicit operator bool() const { return _data && _size > 0; } + + operator const T*() const { + #ifdef DEBUG + struct out_of_bounds {}; + if(_size < 0) throw out_of_bounds{}; + #endif + return _data; + } + + auto operator++() -> type& { _data++; _size--; return *this; } + auto operator--() -> type& { _data--; _size++; return *this; } + + auto operator++(int) -> type { auto copy = *this; ++(*this); return copy; } + auto operator--(int) -> type { auto copy = *this; --(*this); return copy; } + + auto operator-=(int distance) -> type& { _data -= distance; _size += distance; return *this; } + auto operator+=(int distance) -> type& { _data += distance; _size -= distance; return *this; } + + auto operator[](uint index) const -> const T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(index >= _size) throw out_of_bounds{}; + #endif + return _data[index]; + } + + auto operator()(uint index, const T& fallback = {}) const -> T { + if(index >= _size) return fallback; + return _data[index]; + } + + template auto data() const -> const U* { return (const U*)_data; } + template auto size() const -> uint64_t { return _size * sizeof(T) / sizeof(U); } + + auto begin() const -> iterator_const { return {_data, (uint)0}; } + auto end() const -> iterator_const { return {_data, (uint)_size}; } + + auto rbegin() const -> reverse_iterator_const { return {_data, (uint)_size - 1}; } + auto rend() const -> reverse_iterator_const { return {_data, (uint)-1}; } + + auto read() -> T { + auto value = operator[](0); + _data++; + _size--; + return value; + } + + auto view(uint offset, uint length) const -> type { + #ifdef DEBUG + struct out_of_bounds {}; + if(offset + length >= _size) throw out_of_bounds{}; + #endif + return {_data + offset, length}; + } + + //array_view specializations + template auto readl(U& value, uint size) -> U; + template auto readm(U& value, uint size) -> U; + template auto readvn(U& value, uint size) -> U; + template auto readvi(U& value, uint size) -> U; + + template auto readl(U& value, uint offset, uint size) -> U { return view(offset, size).readl(value, size); } + + template auto readl(uint size) -> U { U value; return readl(value, size); } + template auto readm(uint size) -> U { U value; return readm(value, size); } + template auto readvn(uint size) -> U { U value; return readvn(value, size); } + template auto readvi(uint size) -> U { U value; return readvi(value, size); } + + template auto readl(uint offset, uint size) -> U { U value; return readl(value, offset, size); } + +protected: + const T* _data; + int _size; +}; + +//array_view + +template<> template inline auto array_view::readl(U& value, uint size) -> U { + value = 0; + for(uint byte : range(size)) value |= (U)read() << byte * 8; + return value; +} + +template<> template inline auto array_view::readm(U& value, uint size) -> U { + value = 0; + for(uint byte : reverse(range(size))) value |= (U)read() << byte * 8; + return value; +} + +template<> template inline auto array_view::readvn(U& value, uint size) -> U { + value = 0; + uint shift = 1; + while(true) { + auto byte = read(); + value += (byte & 0x7f) * shift; + if(byte & 0x80) break; + shift <<= 7; + value += shift; + } + return value; +} + +template<> template inline auto array_view::readvi(U& value, uint size) -> U { + value = readvn(); + bool negate = value & 1; + value >>= 1; + if(negate) value = ~value; + return value; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/array.hpp b/roms/snes-test-roms/bass-untech/nall/array.hpp new file mode 100644 index 00000000..3c9953d3 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/array.hpp @@ -0,0 +1,89 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall { + +template struct array; + +//usage: int x[256] => array x +template struct array { + array() = default; + + array(const initializer_list& source) { + uint index = 0; + for(auto& value : source) { + operator[](index++) = value; + } + } + + operator array_span() { + return {data(), size()}; + } + + operator array_view() const { + return {data(), size()}; + } + + alwaysinline auto operator[](uint index) -> T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(index >= Size) throw out_of_bounds{}; + #endif + return values[index]; + } + + alwaysinline auto operator[](uint index) const -> const T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(index >= Size) throw out_of_bounds{}; + #endif + return values[index]; + } + + alwaysinline auto operator()(uint index, const T& fallback = {}) const -> const T& { + if(index >= Size) return fallback; + return values[index]; + } + + auto fill(const T& fill = {}) -> array& { + for(auto& value : values) value = fill; + return *this; + } + + auto data() -> T* { return values; } + auto data() const -> const T* { return values; } + auto size() const -> uint { return Size; } + + auto begin() -> T* { return &values[0]; } + auto end() -> T* { return &values[Size]; } + + auto begin() const -> const T* { return &values[0]; } + auto end() const -> const T* { return &values[Size]; } + +private: + T values[Size]; +}; + +template inline auto from_array(uint index) -> T { + static const array table{p...}; + struct out_of_bounds {}; + #if defined(DEBUG) + if(index >= sizeof...(p)) throw out_of_bounds{}; + #endif + return table[index]; +} + +template inline auto from_array(uint index) -> int64_t { + static const array table{p...}; + struct out_of_bounds {}; + #if defined(DEBUG) + if(index >= sizeof...(p)) throw out_of_bounds{}; + #endif + return table[index]; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/atoi.hpp b/roms/snes-test-roms/bass-untech/nall/atoi.hpp new file mode 100644 index 00000000..d6fba252 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/atoi.hpp @@ -0,0 +1,87 @@ +#pragma once + +#include + +namespace nall { + +constexpr inline auto toBinary_(const char* s, uintmax sum = 0) -> uintmax { + return ( + *s == '0' || *s == '1' ? toBinary_(s + 1, (sum << 1) | *s - '0') : + *s == '\'' ? toBinary_(s + 1, sum) : + sum + ); +} + +constexpr inline auto toOctal_(const char* s, uintmax sum = 0) -> uintmax { + return ( + *s >= '0' && *s <= '7' ? toOctal_(s + 1, (sum << 3) | *s - '0') : + *s == '\'' ? toOctal_(s + 1, sum) : + sum + ); +} + +constexpr inline auto toDecimal_(const char* s, uintmax sum = 0) -> uintmax { + return ( + *s >= '0' && *s <= '9' ? toDecimal_(s + 1, (sum * 10) + *s - '0') : + *s == '\'' ? toDecimal_(s + 1, sum) : + sum + ); +} + +constexpr inline auto toHex_(const char* s, uintmax sum = 0) -> uintmax { + return ( + *s >= 'A' && *s <= 'F' ? toHex_(s + 1, (sum << 4) | *s - 'A' + 10) : + *s >= 'a' && *s <= 'f' ? toHex_(s + 1, (sum << 4) | *s - 'a' + 10) : + *s >= '0' && *s <= '9' ? toHex_(s + 1, (sum << 4) | *s - '0') : + *s == '\'' ? toHex_(s + 1, sum) : + sum + ); +} + +// + +constexpr inline auto toBinary(const char* s) -> uintmax { + return ( + *s == '0' && (*(s + 1) == 'B' || *(s + 1) == 'b') ? toBinary_(s + 2) : + *s == '%' ? toBinary_(s + 1) : toBinary_(s) + ); +} + +constexpr inline auto toOctal(const char* s) -> uintmax { + return ( + *s == '0' && (*(s + 1) == 'O' || *(s + 1) == 'o') ? toOctal_(s + 2) : + toOctal_(s) + ); +} + +constexpr inline auto toHex(const char* s) -> uintmax { + return ( + *s == '0' && (*(s + 1) == 'X' || *(s + 1) == 'x') ? toHex_(s + 2) : + *s == '$' ? toHex_(s + 1) : toHex_(s) + ); +} + +// + +constexpr inline auto toNatural(const char* s) -> uintmax { + return ( + *s == '0' && (*(s + 1) == 'B' || *(s + 1) == 'b') ? toBinary_(s + 2) : + *s == '0' && (*(s + 1) == 'O' || *(s + 1) == 'o') ? toOctal_(s + 2) : + *s == '0' && (*(s + 1) == 'X' || *(s + 1) == 'x') ? toHex_(s + 2) : + *s == '%' ? toBinary_(s + 1) : *s == '$' ? toHex_(s + 1) : toDecimal_(s) + ); +} + +constexpr inline auto toInteger(const char* s) -> intmax { + return ( + *s == '+' ? +toNatural(s + 1) : *s == '-' ? -toNatural(s + 1) : toNatural(s) + ); +} + +// + +inline auto toReal(const char* s) -> double { + return atof(s); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/archive/container.hpp b/roms/snes-test-roms/bass-untech/nall/beat/archive/container.hpp new file mode 100644 index 00000000..bdfce1da --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/archive/container.hpp @@ -0,0 +1,200 @@ +#pragma once + +#include + +namespace nall::Beat::Archive { + +struct Container { + Container(array_view = {}); + ~Container(); + + auto isCompressed() const -> bool { return (bool)compression.type; } + auto isSigned() const -> bool { return (bool)signature.type; } + auto isEncrypted() const -> bool { return (bool)encryption.type; } + + auto compressLZSA() -> void; + auto signEd25519(uint256_t privateKey) -> void; + auto encryptXChaCha20(uint256_t privateKey, uint192_t nonce = 0) -> void; + + auto validate() -> bool; + auto decryptXChaCha20(uint256_t privateKey) -> bool; + auto verifyEd25519(uint256_t publicKey) -> bool; + auto decompressLZSA() -> bool; + + auto append(string name, string location) -> shared_pointer; + auto appendPath(string name) -> shared_pointer; + auto appendFile(string name, array_view memory) -> shared_pointer; + auto remove(string name) -> bool; + auto find(string name) -> shared_pointer; + auto sort() -> void; + + auto begin() { return nodes.begin(); } + auto end() { return nodes.end(); } + + auto begin() const { return nodes.begin(); } + auto end() const { return nodes.end(); } + + auto rbegin() { return nodes.rbegin(); } + auto rend() { return nodes.rend(); } + + auto rbegin() const { return nodes.rbegin(); } + auto rend() const { return nodes.rend(); } + + vector> nodes; + vector memory; + string metadata; + + struct Compression { + string type; + } compression; + + struct Signature { + string type; + uint256_t privateKey = 0; + uint256_t publicKey = 0; + uint512_t value = 0; + } signature; + + struct Encryption { + string type; + uint256_t privateKey = 0; + uint192_t nonce = 0; + } encryption; +}; + +Container::Container(array_view memory) { + this->memory.resize(memory.size()); + nall::memory::copy(this->memory.data(), memory.data(), memory.size()); +} + +Container::~Container() { + metadata = {}; + signature = {}; + encryption = {}; +} + +// + +auto Container::compressLZSA() -> void { + compression.type = "lzsa"; +} + +auto Container::signEd25519(uint256_t privateKey) -> void { + signature.type = "ed25519"; + signature.privateKey = privateKey; +} + +auto Container::encryptXChaCha20(uint256_t privateKey, uint192_t nonce) -> void { + if(!nonce) { + CSPRNG::XChaCha20 csprng; + nonce = csprng.random(); + } + + encryption.type = "xchacha20"; + encryption.privateKey = privateKey; + encryption.nonce = nonce; +} + +// + +auto Container::validate() -> bool { + array_view memory = this->memory; + if(memory.size() < 44) return false; //8 (metadata size) + 32 (SHA256) + 4 (signature) + + if(memory[memory.size() - 4] != 'B') return false; + if(memory[memory.size() - 3] != 'P') return false; + if(memory[memory.size() - 2] != 'A') return false; + if(memory[memory.size() - 1] != '1') return false; + + auto sha256 = memory.readl(memory.size() - 36, 32); + if(Hash::SHA256({memory.data(), memory.size() - 36}).value() != sha256) return false; + + auto size = memory.readl(memory.size() - 44, 8); + + if(size & 1ull << 63) { + size -= 1ull << 63; + metadata = memory.view(memory.size() - 44 - size, size); + uint64_t offset = memory.size() - 44 - size; + for(auto& byte : metadata) byte ^= offset++; + } else { + metadata = memory.view(memory.size() - 44 - size, size); + } + + auto document = BML::unserialize(metadata); + + if(auto node = document["archive/encryption"]) { + if(node.text() == "xchacha20") { + encryption.type = node.text(); + encryption.nonce = Decode::Base<57, uint192_t>(node["nonce"].text()); + } + } + + if(auto node = document["archive/signature"]) { + if(node.text() == "ed25519") { + signature.type = node.text(); + signature.publicKey = Decode::Base<57, uint256_t>(node["publicKey"].text()); + signature.value = Decode::Base<57, uint512_t>(node["value"].text()); + } + } + + if(auto node = document["archive/compression"]) { + compression.type = node.text(); + } + + return true; +} + +auto Container::decryptXChaCha20(uint256_t privateKey) -> bool { + encryption.privateKey = privateKey; + Cipher::XChaCha20 xchacha20{encryption.privateKey, encryption.nonce}; + auto size = memory.readl(memory.size() - 44, 8); + memory = xchacha20.decrypt(memory.view(0, memory.size() - 44 - size)); + return true; +} + +auto Container::verifyEd25519(uint256_t publicKey) -> bool { + EllipticCurve::Ed25519 ed25519; + auto size = memory.readl(memory.size() - 44, 8); + return ed25519.verify(memory.view(0, memory.size() - 44 - size), signature.value, publicKey); +} + +auto Container::decompressLZSA() -> bool { + memory = Decode::LZSA(memory); + return (bool)memory; +} + +// + +auto Container::append(string name, string location) -> shared_pointer { + for(auto& node : nodes) if(node->name == name) return {}; + if(auto node = Node::create(name, location)) return nodes.append(node), node; + return {}; +} + +auto Container::appendPath(string name) -> shared_pointer { + for(auto& node : nodes) if(node->name == name) return {}; + if(auto node = Node::createPath(name)) return nodes.append(node), node; + return {}; +} + +auto Container::appendFile(string name, array_view memory) -> shared_pointer { + for(auto& node : nodes) if(node->name == name) return {}; + if(auto node = Node::createFile(name, memory)) return nodes.append(node), node; + return {}; +} + +auto Container::remove(string name) -> bool { + if(auto offset = nodes.find([&](auto& node) { return node->name == name; })) return nodes.remove(*offset), true; + return false; +} + +auto Container::find(string name) -> shared_pointer { + if(auto offset = nodes.find([&](auto& node) { return node->name == name; })) return nodes[*offset]; + return {}; +} + +auto Container::sort() -> void { + nodes.sort([&](auto& lhs, auto& rhs) { return string::icompare(lhs->name, rhs->name) < 0; }); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/archive/create.hpp b/roms/snes-test-roms/bass-untech/nall/beat/archive/create.hpp new file mode 100644 index 00000000..7014e489 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/archive/create.hpp @@ -0,0 +1,86 @@ +#pragma once + +#include +#include + +namespace nall::Beat::Archive { + +auto create(Container& container, string name) -> vector { + auto& metadata = container.metadata; + metadata = {}; + metadata.append("archive: ", Location::file(name), "\n"); + + vector memory; + + container.sort(); + for(auto& node : container.nodes) { + if(node->isFile()) { + node->offset = memory.size(); + memory.append(node->memory); + } + metadata.append(node->metadata()); + } + + metadata.append(" size: ", memory.size(), "\n"); + + if(container.compression.type == "lzsa") { + memory = Encode::LZSA(memory); + metadata.append(" compression: lzsa\n"); + metadata.append(" size: ", memory.size(), "\n"); + } + + if(container.signature.type == "ed25519") { + EllipticCurve::Ed25519 ed25519; + container.signature.publicKey = ed25519.publicKey(container.signature.privateKey); + container.signature.value = ed25519.sign(memory, container.signature.privateKey); + + metadata.append(" signature: ed25519\n"); + metadata.append(" publicKey: ", Encode::Base<57>(container.signature.publicKey), "\n"); + metadata.append(" value: ", Encode::Base<57>(container.signature.value), "\n"); + } + + for(auto& byte : metadata) memory.append(byte); + memory.appendl((uint64_t)metadata.size(), 8); + + auto sha256 = Hash::SHA256(memory).value(); + memory.appendl((uint256_t)sha256, 32); + + memory.append('B'); + memory.append('P'); + memory.append('A'); + memory.append('1'); + + if(container.encryption.type == "xchacha20") { + Cipher::XChaCha20 xchacha20{container.encryption.privateKey, container.encryption.nonce}; + memory = xchacha20.encrypt(memory); + + metadata = {}; + metadata.append("archive\n"); + metadata.append(" encryption: xchacha20\n"); + metadata.append(" nonce: ", Encode::Base<57>(container.encryption.nonce), "\n"); + + if(container.signature.type == "ed25519") { + EllipticCurve::Ed25519 ed25519; + container.signature.value = ed25519.sign(memory, container.signature.privateKey); + + metadata.append(" signature: ed25519\n"); + //metadata.append(" publicKey: ", Encode::Base<57>(container.signature.publicKey), "\n"); + metadata.append(" value: ", Encode::Base<57>(container.signature.value), "\n"); + } + + for(auto& byte : metadata) memory.append(byte ^ memory.size()); + memory.appendl((uint64_t)metadata.size() | 1ull << 63, 8); + + auto sha256 = Hash::SHA256(memory).value(); + memory.appendl((uint256_t)sha256, 32); + + memory.append('B'); + memory.append('P'); + memory.append('A'); + memory.append('1'); + } + + return memory; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/archive/extract.hpp b/roms/snes-test-roms/bass-untech/nall/beat/archive/extract.hpp new file mode 100644 index 00000000..41e48891 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/archive/extract.hpp @@ -0,0 +1,27 @@ +#pragma once + +#include +#include + +namespace nall::Beat::Archive { + +auto extract(Container& container) -> bool { + function extract = [&](auto metadata) { + if(metadata.name() != "path" && metadata.name() != "file") return; + shared_pointer node = new Node; + if(node->unserialize(container.memory, metadata)) { + container.nodes.append(node); + } + if(metadata.name() != "path") return; + for(auto node : metadata) extract(node); + }; + + container.nodes.reset(); + auto document = BML::unserialize(container.metadata); + for(auto node : document["archive"]) extract(node); + container.sort(); + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/archive/node.hpp b/roms/snes-test-roms/bass-untech/nall/beat/archive/node.hpp new file mode 100644 index 00000000..a8821ff7 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/archive/node.hpp @@ -0,0 +1,332 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nall::Beat::Archive { + +struct Node { + static auto create(string name, string location) -> shared_pointer; + static auto createPath(string name) -> shared_pointer; + static auto createFile(string name, array_view memory) -> shared_pointer; + + explicit operator bool() const { return (bool)name; } + auto isPath() const -> bool { return name.endsWith("/"); } + auto isFile() const -> bool { return !name.endsWith("/"); } + auto isCompressed() const -> bool { return (bool)compression.type; } + + auto metadata(bool indented = true) const -> string; + auto compressLZSA() -> bool; + + auto unserialize(array_view container, Markup::Node metadata) -> bool; + auto decompress() -> bool; + + auto getTimestamp(string) const -> uint64_t; + auto getPermissions() const -> uint; + auto getOwner() const -> string; + auto getGroup() const -> string; + + //files and paths + string name; + + bool timestamps = false; + struct Timestamp { + string created; + string modified; + string accessed; + } timestamp; + + bool permissions = false; + struct Permission { + struct Owner { + string name; + bool readable = false; + bool writable = false; + bool executable = false; + } owner; + struct Group { + string name; + bool readable = false; + bool writable = false; + bool executable = false; + } group; + struct Other { + bool readable = false; + bool writable = false; + bool executable = false; + } other; + } permission; + + //files only + vector memory; + uint64_t offset = 0; + + struct Compression { + string type; + uint size = 0; //decompressed size; memory.size() == compressed size + } compression; +}; + +auto Node::create(string name, string location) -> shared_pointer { + if(!inode::exists(location)) return {}; + shared_pointer node = new Node; + + node->name = name; + + node->timestamps = true; + node->timestamp.created = chrono::utc::datetime(inode::timestamp(location, inode::time::create)); + node->timestamp.modified = chrono::utc::datetime(inode::timestamp(location, inode::time::modify)); + node->timestamp.accessed = chrono::utc::datetime(inode::timestamp(location, inode::time::access)); + + uint mode = inode::mode(location); + node->permissions = true; + node->permission.owner.name = inode::owner(location); + node->permission.group.name = inode::group(location); + node->permission.owner.readable = mode & 0400; + node->permission.owner.writable = mode & 0200; + node->permission.owner.executable = mode & 0100; + node->permission.group.readable = mode & 0040; + node->permission.group.writable = mode & 0020; + node->permission.group.executable = mode & 0010; + node->permission.other.readable = mode & 0004; + node->permission.other.writable = mode & 0002; + node->permission.other.executable = mode & 0001; + + if(file::exists(location)) { + node->memory = file::read(location); + } + + return node; +} + +auto Node::createPath(string name) -> shared_pointer { + if(!name) return {}; + shared_pointer node = new Node; + node->name = name; + return node; +} + +auto Node::createFile(string name, array_view memory) -> shared_pointer { + if(!name) return {}; + shared_pointer node = new Node; + node->name = name; + node->memory.resize(memory.size()); + memory::copy(node->memory.data(), memory.data(), memory.size()); + return node; +} + +auto Node::metadata(bool indented) const -> string { + string metadata; + if(!name) return metadata; + + string indent; + if(indented) { + indent.append(" "); + auto bytes = string{name}.trimRight("/"); + for(auto& byte : bytes) { + if(byte == '/') indent.append(" "); + } + } + + if(isPath()) { + metadata.append(indent, "path: ", name, "\n"); + } + + if(isFile()) { + metadata.append(indent, "file: ", name, "\n"); + } + + if(timestamps) { + metadata.append(indent, " timestamp\n"); + if(timestamp.created != timestamp.modified) + metadata.append(indent, " created: ", timestamp.created, "\n"); + metadata.append(indent, " modified: ", timestamp.modified, "\n"); + if(timestamp.accessed != timestamp.modified) + metadata.append(indent, " accessed: ", timestamp.accessed, "\n"); + } + + if(permissions) { + metadata.append(indent, " permission\n"); + metadata.append(indent, " owner: ", permission.owner.name, "\n"); + if(permission.owner.readable) + metadata.append(indent, " readable\n"); + if(permission.owner.writable) + metadata.append(indent, " writable\n"); + if(permission.owner.executable) + metadata.append(indent, " executable\n"); + metadata.append(indent, " group: ", permission.group.name, "\n"); + if(permission.group.readable) + metadata.append(indent, " readable\n"); + if(permission.group.writable) + metadata.append(indent, " writable\n"); + if(permission.group.executable) + metadata.append(indent, " executable\n"); + metadata.append(indent, " other\n"); + if(permission.other.readable) + metadata.append(indent, " readable\n"); + if(permission.other.writable) + metadata.append(indent, " writable\n"); + if(permission.other.executable) + metadata.append(indent, " executable\n"); + } + + if(isFile()) { + metadata.append(indent, " offset: ", offset, "\n"); + if(!isCompressed()) { + metadata.append(indent, " size: ", memory.size(), "\n"); + } else { + metadata.append(indent, " size: ", compression.size, "\n"); + metadata.append(indent, " compression: ", compression.type, "\n"); + metadata.append(indent, " size: ", memory.size(), "\n"); + } + } + + return metadata; +} + +auto Node::unserialize(array_view container, Markup::Node metadata) -> bool { + *this = {}; + if(!metadata.text()) return false; + + name = metadata.text(); + + if(auto node = metadata["timestamp"]) { + timestamps = true; + if(auto created = node["created" ]) timestamp.created = created.text(); + if(auto modified = node["modified"]) timestamp.modified = modified.text(); + if(auto accessed = node["accessed"]) timestamp.accessed = accessed.text(); + } + + if(auto node = metadata["permission"]) { + permissions = true; + if(auto owner = node["owner"]) { + permission.owner.name = owner.text(); + permission.owner.readable = (bool)owner["readable"]; + permission.owner.writable = (bool)owner["writable"]; + permission.owner.executable = (bool)owner["executable"]; + } + if(auto group = node["group"]) { + permission.group.name = group.text(); + permission.group.readable = (bool)group["readable"]; + permission.group.writable = (bool)group["writable"]; + permission.group.executable = (bool)group["executable"]; + } + if(auto other = node["other"]) { + permission.other.readable = (bool)other["readable"]; + permission.other.writable = (bool)other["writable"]; + permission.other.executable = (bool)other["executable"]; + } + } + + if(isPath()) return true; + + uint offset = metadata["offset"].natural(); + uint size = metadata["size"].natural(); + + if(metadata["compression"]) { + size = metadata["compression/size"].natural(); + compression.type = metadata["compression"].text(); + } + + if(offset + size >= container.size()) return false; + + memory.reallocate(size); + nall::memory::copy(memory.data(), container.view(offset, size), size); + return true; +} + +auto Node::compressLZSA() -> bool { + if(!memory) return true; //don't compress empty files + if(isCompressed()) return true; //don't recompress files + + auto compressedMemory = Encode::LZSA(memory); + if(compressedMemory.size() >= memory.size()) return true; //can't compress smaller than original size + + compression.type = "lzsa"; + compression.size = memory.size(); + memory = move(compressedMemory); + return true; +} + +auto Node::decompress() -> bool { + if(!isCompressed()) return true; + + if(compression.type == "lzsa") { + compression = {}; + memory = Decode::LZSA(memory); + return (bool)memory; + } + + return false; +} + +auto Node::getTimestamp(string type) const -> uint64_t { + if(!timestamps) return time(nullptr); + + string value = chrono::utc::datetime(); + if(type == "created" ) value = timestamp.created; + if(type == "modified") value = timestamp.modified; + if(type == "accessed") value = timestamp.accessed; + + #if !defined(PLATFORM_WINDOWS) + struct tm timeInfo{}; + if(strptime(value, "%Y-%m-%d %H:%M:%S", &timeInfo) != nullptr) { + //todo: not thread safe ... + auto tz = getenv("TZ"); + setenv("TZ", "", 1); + timeInfo.tm_isdst = -1; + auto result = mktime(&timeInfo); + if(tz) setenv("TZ", tz, 1); + else unsetenv("TZ"); + if(result != -1) return result; + } + #endif + + return time(nullptr); +} + +auto Node::getPermissions() const -> uint { + if(!permissions) return 0755; + uint mode = 0; + if(permission.owner.readable ) mode |= 0400; + if(permission.owner.writable ) mode |= 0200; + if(permission.owner.executable) mode |= 0100; + if(permission.group.readable ) mode |= 0040; + if(permission.group.writable ) mode |= 0020; + if(permission.group.executable) mode |= 0010; + if(permission.other.readable ) mode |= 0004; + if(permission.other.writable ) mode |= 0002; + if(permission.other.executable) mode |= 0001; + return mode; +} + +auto Node::getOwner() const -> string { + if(!permissions || !permission.owner.name) { + #if !defined(PLATFORM_WINDOWS) + struct passwd* pwd = getpwuid(getuid()); + assert(pwd); + return pwd->pw_name; + #endif + } + return permission.owner.name; +} + +auto Node::getGroup() const -> string { + if(!permissions || !permission.group.name) { + #if !defined(PLATFORM_WINDOWS) + struct group* grp = getgrgid(getgid()); + assert(grp); + return grp->gr_name; + #endif + } + return permission.group.name; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/single/apply.hpp b/roms/snes-test-roms/bass-untech/nall/beat/single/apply.hpp new file mode 100644 index 00000000..cd81762a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/single/apply.hpp @@ -0,0 +1,88 @@ +#pragma once + +namespace nall::Beat::Single { + +inline auto apply(array_view source, array_view beat, maybe manifest = {}, maybe result = {}) -> maybe> { + #define error(text) { if(result) *result = {"error: ", text}; return {}; } + #define warning(text) { if(result) *result = {"warning: ", text}; return target; } + #define success() { if(result) *result = ""; return target; } + if(beat.size() < 19) error("beat size mismatch"); + + vector target; + + uint beatOffset = 0; + auto read = [&]() -> uint8_t { + return beat[beatOffset++]; + }; + + auto decode = [&]() -> uint64_t { + uint64_t data = 0, shift = 1; + while(true) { + uint8_t x = read(); + data += (x & 0x7f) * shift; + if(x & 0x80) break; + shift <<= 7; + data += shift; + } + return data; + }; + + auto write = [&](uint8_t data) { + target.append(data); + }; + + if(read() != 'B') error("beat header invalid"); + if(read() != 'P') error("beat header invalid"); + if(read() != 'S') error("beat header invalid"); + if(read() != '1') error("beat version mismatch"); + if(decode() != source.size()) error("source size mismatch"); + uint targetSize = decode(); + target.reserve(targetSize); + uint metadataSize = decode(); + for(uint n : range(metadataSize)) { + auto data = read(); + if(manifest) manifest->append((char)data); + } + + enum : uint { SourceRead, TargetRead, SourceCopy, TargetCopy }; + + uint sourceRelativeOffset = 0, targetRelativeOffset = 0; + while(beatOffset < beat.size() - 12) { + uint length = decode(); + uint mode = length & 3; + length = (length >> 2) + 1; + + if(mode == SourceRead) { + while(length--) write(source[target.size()]); + } else if(mode == TargetRead) { + while(length--) write(read()); + } else { + int offset = decode(); + offset = offset & 1 ? -(offset >> 1) : (offset >> 1); + if(mode == SourceCopy) { + sourceRelativeOffset += offset; + while(length--) write(source[sourceRelativeOffset++]); + } else { + targetRelativeOffset += offset; + while(length--) write(target[targetRelativeOffset++]); + } + } + } + + uint32_t sourceHash = 0, targetHash = 0, beatHash = 0; + for(uint shift : range(0, 32, 8)) sourceHash |= read() << shift; + for(uint shift : range(0, 32, 8)) targetHash |= read() << shift; + for(uint shift : range(0, 32, 8)) beatHash |= read() << shift; + + if(target.size() != targetSize) warning("target size mismatch"); + if(sourceHash != Hash::CRC32(source).value()) warning("source hash mismatch"); + if(targetHash != Hash::CRC32(target).value()) warning("target hash mismatch"); + if(beatHash != Hash::CRC32({beat.data(), beat.size() - 4}).value()) warning("beat hash mismatch"); + + success(); + #undef error + #undef warning + #undef success +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/beat/single/create.hpp b/roms/snes-test-roms/bass-untech/nall/beat/single/create.hpp new file mode 100644 index 00000000..940bdfcf --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/beat/single/create.hpp @@ -0,0 +1,99 @@ +#pragma once + +#include + +namespace nall::Beat::Single { + +inline auto create(array_view source, array_view target, string_view manifest = {}) -> vector { + vector beat; + + auto write = [&](uint8_t data) { + beat.append(data); + }; + + auto encode = [&](uint64_t data) { + while(true) { + uint64_t x = data & 0x7f; + data >>= 7; + if(data == 0) { write(0x80 | x); break; } + write(x); + data--; + } + }; + + write('B'), write('P'), write('S'), write('1'); + encode(source.size()), encode(target.size()), encode(manifest.size()); + for(auto& byte : manifest) write(byte); + + //generating lrcp() arrays for source requires O(4n) computations, and O(16m) memory, + //but it reduces find() complexity from O(n log m) to O(n + log m). and yet in practice, + //no matter how large n scales to, the O(n + log m) find() is paradoxically slower. + auto sourceArray = SuffixArray(source); + auto targetArray = SuffixArray(target).lpf(); + + enum : uint { SourceRead, TargetRead, SourceCopy, TargetCopy }; + uint outputOffset = 0, sourceRelativeOffset = 0, targetRelativeOffset = 0; + + uint targetReadLength = 0; + auto flush = [&] { + if(!targetReadLength) return; + encode(TargetRead | ((targetReadLength - 1) << 2)); + uint offset = outputOffset - targetReadLength; + while(targetReadLength) write(target[offset++]), targetReadLength--; + }; + + uint overlap = min(source.size(), target.size()); + while(outputOffset < target.size()) { + uint mode = TargetRead, longestLength = 3, longestOffset = 0; + int length = 0, offset = outputOffset; + + while(offset < overlap) { + if(source[offset] != target[offset]) break; + length++, offset++; + } + if(length > longestLength) { + mode = SourceRead, longestLength = length; + } + + sourceArray.find(length, offset, {target.data() + outputOffset, target.size() - outputOffset}); + if(length > longestLength) { + mode = SourceCopy, longestLength = length, longestOffset = offset; + } + + targetArray.previous(length, offset, outputOffset); + if(length > longestLength) { + mode = TargetCopy, longestLength = length, longestOffset = offset; + } + + if(mode == TargetRead) { + targetReadLength++; //queue writes to group sequential commands + outputOffset++; + } else { + flush(); + encode(mode | ((longestLength - 1) << 2)); + if(mode == SourceCopy) { + int relativeOffset = longestOffset - sourceRelativeOffset; + sourceRelativeOffset = longestOffset + longestLength; + encode(relativeOffset < 0 | abs(relativeOffset) << 1); + } + if(mode == TargetCopy) { + int relativeOffset = longestOffset - targetRelativeOffset; + targetRelativeOffset = longestOffset + longestLength; + encode(relativeOffset < 0 | abs(relativeOffset) << 1); + } + outputOffset += longestLength; + } + } + flush(); + + auto sourceHash = Hash::CRC32(source); + for(uint shift : range(0, 32, 8)) write(sourceHash.value() >> shift); + auto targetHash = Hash::CRC32(target); + for(uint shift : range(0, 32, 8)) write(targetHash.value() >> shift); + auto beatHash = Hash::CRC32(beat); + for(uint shift : range(0, 32, 8)) write(beatHash.value() >> shift); + + return beat; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/bit.hpp b/roms/snes-test-roms/bass-untech/nall/bit.hpp new file mode 100644 index 00000000..42898c1b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/bit.hpp @@ -0,0 +1,90 @@ +#pragma once + +#include + +namespace nall { + +template inline auto uclamp(T x) -> uint64_t { + enum : uint64_t { b = 1ull << (bits - 1), y = b * 2 - 1 }; + if constexpr(is_unsigned_v) { + return y + ((x - y) & -(x < y)); //min(x, y); + } + if constexpr(is_signed_v) { + return x < 0 ? 0 : x > y ? y : x; + } +} + +template inline auto uclip(uint64_t x) -> uint64_t { + enum : uint64_t { b = 1ull << (bits - 1), m = b * 2 - 1 }; + return (x & m); +} + +template inline auto sclamp(int64_t x) -> int64_t { + enum : int64_t { b = 1ull << (bits - 1), m = b - 1 }; + return (x > m) ? m : (x < -b) ? -b : x; +} + +template inline auto sclip(int64_t x) -> int64_t { + enum : uint64_t { b = 1ull << (bits - 1), m = b * 2 - 1 }; + return ((x & m) ^ b) - b; +} + +namespace bit { + constexpr inline auto mask(const char* s, uint64_t sum = 0) -> uint64_t { + return ( + *s == '0' || *s == '1' ? mask(s + 1, (sum << 1) | 1) : + *s == ' ' || *s == '_' ? mask(s + 1, sum) : + *s ? mask(s + 1, sum << 1) : + sum + ); + } + + constexpr inline auto test(const char* s, uint64_t sum = 0) -> uint64_t { + return ( + *s == '0' || *s == '1' ? test(s + 1, (sum << 1) | (*s - '0')) : + *s == ' ' || *s == '_' ? test(s + 1, sum) : + *s ? test(s + 1, sum << 1) : + sum + ); + } + + //lowest(0b1110) == 0b0010 + constexpr inline auto lowest(const uint64_t x) -> uint64_t { + return x & -x; + } + + //clear_lowest(0b1110) == 0b1100 + constexpr inline auto clearLowest(const uint64_t x) -> uint64_t { + return x & (x - 1); + } + + //set_lowest(0b0101) == 0b0111 + constexpr inline auto setLowest(const uint64_t x) -> uint64_t { + return x | (x + 1); + } + + //count number of bits set in a byte + constexpr inline auto count(uint64_t x) -> uint { + uint count = 0; + while(x) x &= x - 1, count++; //clear the least significant bit + return count; + } + + //return index of the first bit set (or zero of no bits are set) + //first(0b1000) == 3 + constexpr inline auto first(uint64_t x) -> uint { + uint first = 0; + while(x) { if(x & 1) break; x >>= 1; first++; } + return first; + } + + //round up to next highest single bit: + //round(15) == 16, round(16) == 16, round(17) == 32 + constexpr inline auto round(uint64_t x) -> uint64_t { + if((x & (x - 1)) == 0) return x; + while(x & (x - 1)) x &= x - 1; + return x << 1; + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/bump-allocator.hpp b/roms/snes-test-roms/bass-untech/nall/bump-allocator.hpp new file mode 100644 index 00000000..ede57471 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/bump-allocator.hpp @@ -0,0 +1,94 @@ +#pragma once + +namespace nall { + +struct bump_allocator { + static constexpr uint32_t executable = 1 << 0; + static constexpr uint32_t zero_fill = 1 << 1; + + ~bump_allocator() { + reset(); + } + + explicit operator bool() const { + return _memory; + } + + auto reset() -> void { + free(_memory); + _memory = nullptr; + } + + auto resize(uint32_t capacity, uint32_t flags = 0) -> bool { + reset(); + _offset = 0; + _capacity = capacity + 4095 & ~4095; //alignment + _memory = (uint8_t*)malloc(_capacity); + if(!_memory) return false; + + if(flags & executable) { + #if defined(PLATFORM_WINDOWS) + DWORD privileges; + VirtualProtect((void*)_memory, _capacity, PAGE_EXECUTE_READWRITE, &privileges); + #else + mprotect(_memory, _capacity, PROT_READ | PROT_WRITE | PROT_EXEC); + #endif + } + + if(flags & zero_fill) { + memset(_memory, 0x00, _capacity); + } + + return true; + } + + //release all acquired memory + auto release(uint32_t flags = 0) -> void { + _offset = 0; + if(flags & zero_fill) memset(_memory, 0x00, _capacity); + } + + auto capacity() const -> uint32_t { + return _capacity; + } + + auto available() const -> uint32_t { + return _capacity - _offset; + } + + //for allocating blocks of known size + auto acquire(uint32_t size) -> uint8_t* { + #ifdef DEBUG + struct out_of_memory {}; + if((_offset + size + 15 & ~15) > _capacity) throw out_of_memory{}; + #endif + auto memory = _memory + _offset; + _offset = _offset + size + 15 & ~15; //alignment + return memory; + } + + //for allocating blocks of unknown size (eg for a dynamic recompiler code block) + auto acquire() -> uint8_t* { + #ifdef DEBUG + struct out_of_memory {}; + if(_offset > _capacity) throw out_of_memory{}; + #endif + return _memory + _offset; + } + + //size can be reserved once the block size is known + auto reserve(uint32_t size) -> void { + #ifdef DEBUG + struct out_of_memory {}; + if((_offset + size + 15 & ~15) > _capacity) throw out_of_memory{}; + #endif + _offset = _offset + size + 15 & ~15; //alignment + } + +private: + uint8_t* _memory = nullptr; + uint32_t _capacity = 0; + uint32_t _offset = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd.hpp b/roms/snes-test-roms/bass-untech/nall/cd.hpp new file mode 100644 index 00000000..9fca9aba --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd.hpp @@ -0,0 +1,31 @@ +#pragma once + +/* CD-ROM sector functions. + * + * Implemented: + * eight-to-fourteen modulation (encoding and decoding) + * sync header creation and verification + * error detection code creation and verification + * reed-solomon product-code creation and verification + * sector scrambling and descrambling (currently unverified) + * + * Unimplemented: + * reed-solomon product-code correction + * cross-interleave reed-solomon creation, verification, and correction + * CD-ROM XA mode 2 forms 1 & 2 support + * subcode insertion and removal + * subcode decoding from CUE files + * channel frame expansion and reduction + */ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include diff --git a/roms/snes-test-roms/bass-untech/nall/cd/crc16.hpp b/roms/snes-test-roms/bass-untech/nall/cd/crc16.hpp new file mode 100644 index 00000000..d0b34b1c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/crc16.hpp @@ -0,0 +1,18 @@ +#pragma once + +//CRC-16/KERMIT + +namespace nall::CD { + +inline auto CRC16(array_view data) -> uint16_t { + uint16_t crc = 0; + while(data) { + crc ^= *data++ << 8; + for(uint bit : range(8)) { + crc = crc << 1 ^ (crc & 0x8000 ? 0x1021 : 0); + } + } + return ~crc; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/edc.hpp b/roms/snes-test-roms/bass-untech/nall/cd/edc.hpp new file mode 100644 index 00000000..bcc645a5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/edc.hpp @@ -0,0 +1,65 @@ +#pragma once + +//error detection code + +namespace nall::CD::EDC { + +//polynomial(x) = (x^16 + x^15 + x^2 + 1) * (x^16 + x^2 + x + 1) +inline auto polynomial(uint8_t x) -> uint32_t { + static uint32_t lookup[256]{}; + static bool once = false; + if(!once) { once = true; + for(uint n : range(256)) { + uint32_t edc = n; + for(uint b : range(8)) edc = edc >> 1 ^ (edc & 1 ? 0xd8018001 : 0); + lookup[n] = edc; + } + } + return lookup[x]; +} + +// + +inline auto create(array_view input) -> uint32_t { + uint32_t sum = 0; + for(auto& byte : input) sum = sum >> 8 ^ polynomial(sum ^ byte); + return sum; +} + +inline auto create(array_view input, array_span output) -> bool { + if(output.size() != 4) return false; + auto sum = create(input); + output[0] = sum >> 0; + output[1] = sum >> 8; + output[2] = sum >> 16; + output[3] = sum >> 24; + return true; +} + +inline auto createMode1(array_span sector) -> bool { + if(sector.size() != 2352) return false; + return create({sector, 2064}, {sector + 2064, 4}); +} + +// + +inline auto verify(array_view input, uint32_t edc) -> bool { + return edc == create(input); +} + +inline auto verify(array_view input, array_view compare) -> bool { + if(compare.size() != 4) return false; + auto sum = create(input); + if(compare[0] != uint8_t(sum >> 0)) return false; + if(compare[1] != uint8_t(sum >> 8)) return false; + if(compare[2] != uint8_t(sum >> 16)) return false; + if(compare[3] != uint8_t(sum >> 24)) return false; + return true; +} + +inline auto verifyMode1(array_view sector) -> bool { + if(sector.size() != 2352) return false; + return verify({sector, 2064}, {sector + 2064, 4}); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/efm.hpp b/roms/snes-test-roms/bass-untech/nall/cd/efm.hpp new file mode 100644 index 00000000..ea4896a8 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/efm.hpp @@ -0,0 +1,68 @@ +#pragma once + +//eight-to-fourteen modulation: +//separates each 1-bit by at least two 0-bits and at most ten 0-bits + +namespace nall::CD::EFM { + +//the algorithm to generate this table is unknown +inline auto lookup(uint8_t index) -> uint16_t { + static const uint16_t lookup[256] = { + 0x1220, 0x2100, 0x2420, 0x2220, 0x1100, 0x0110, 0x0420, 0x0900, + 0x1240, 0x2040, 0x2440, 0x2240, 0x1040, 0x0040, 0x0440, 0x0840, + 0x2020, 0x2080, 0x2480, 0x0820, 0x1080, 0x0080, 0x0480, 0x0880, + 0x1210, 0x2010, 0x2410, 0x2210, 0x1010, 0x0210, 0x0410, 0x0810, + 0x0020, 0x2108, 0x0220, 0x0920, 0x1108, 0x0108, 0x1020, 0x0908, + 0x1248, 0x2048, 0x2448, 0x2248, 0x1048, 0x0048, 0x0448, 0x0848, + 0x0100, 0x2088, 0x2488, 0x2110, 0x1088, 0x0088, 0x0488, 0x0888, + 0x1208, 0x2008, 0x2408, 0x2208, 0x1008, 0x0208, 0x0408, 0x0808, + 0x1224, 0x2124, 0x2424, 0x2224, 0x1124, 0x0024, 0x0424, 0x0924, + 0x1244, 0x2044, 0x2444, 0x2244, 0x1044, 0x0044, 0x0444, 0x0844, + 0x2024, 0x2084, 0x2484, 0x0824, 0x1084, 0x0084, 0x0484, 0x0884, + 0x1204, 0x2004, 0x2404, 0x2204, 0x1004, 0x0204, 0x0404, 0x0804, + 0x1222, 0x2122, 0x2422, 0x2222, 0x1122, 0x0022, 0x1024, 0x0922, + 0x1242, 0x2042, 0x2442, 0x2242, 0x1042, 0x0042, 0x0442, 0x0842, + 0x2022, 0x2082, 0x2482, 0x0822, 0x1082, 0x0082, 0x0482, 0x0882, + 0x1202, 0x0248, 0x2402, 0x2202, 0x1002, 0x0202, 0x0402, 0x0802, + 0x1221, 0x2121, 0x2421, 0x2221, 0x1121, 0x0021, 0x0421, 0x0921, + 0x1241, 0x2041, 0x2441, 0x2241, 0x1041, 0x0041, 0x0441, 0x0841, + 0x2021, 0x2081, 0x2481, 0x0821, 0x1081, 0x0081, 0x0481, 0x0881, + 0x1201, 0x2090, 0x2401, 0x2201, 0x1090, 0x0201, 0x0401, 0x0890, + 0x0221, 0x2109, 0x1110, 0x0121, 0x1109, 0x0109, 0x1021, 0x0909, + 0x1249, 0x2049, 0x2449, 0x2249, 0x1049, 0x0049, 0x0449, 0x0849, + 0x0120, 0x2089, 0x2489, 0x0910, 0x1089, 0x0089, 0x0489, 0x0889, + 0x1209, 0x2009, 0x2409, 0x2209, 0x1009, 0x0209, 0x0409, 0x0809, + 0x1120, 0x2111, 0x2490, 0x0224, 0x1111, 0x0111, 0x0490, 0x0911, + 0x0241, 0x2101, 0x0244, 0x0240, 0x1101, 0x0101, 0x0090, 0x0901, + 0x0124, 0x2091, 0x2491, 0x2120, 0x1091, 0x0091, 0x0491, 0x0891, + 0x1211, 0x2011, 0x2411, 0x2211, 0x1011, 0x0211, 0x0411, 0x0811, + 0x1102, 0x0102, 0x2112, 0x0902, 0x1112, 0x0112, 0x1022, 0x0912, + 0x2102, 0x2104, 0x0249, 0x0242, 0x1104, 0x0104, 0x0422, 0x0904, + 0x0122, 0x2092, 0x2492, 0x0222, 0x1092, 0x0092, 0x0492, 0x0892, + 0x1212, 0x2012, 0x2412, 0x2212, 0x1012, 0x0212, 0x0412, 0x0812, + }; + return lookup[index]; +} + +// + +inline auto encode(uint8_t data) -> uint16_t { + return lookup(data); +} + +// + +inline auto decode(uint16_t data) -> maybe { + static uint16_t table[1 << 14]; + static bool once = true; + if(once) { + once = false; + for(uint n : range(1 << 14)) table[n] = 0xffff; + for(uint n : range(1 << 8)) table[lookup(n)] = n; + } + uint16_t result = table[data & 0x3fff]; + if(result == 0xffff) return {}; + return (uint8_t)result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/rspc.hpp b/roms/snes-test-roms/bass-untech/nall/cd/rspc.hpp new file mode 100644 index 00000000..4f776dd2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/rspc.hpp @@ -0,0 +1,128 @@ +#pragma once + +//reed-solomon product code + +namespace nall::CD::RSPC { + +inline auto encodeP(array_view input, array_span parity) -> bool { + ReedSolomon<26,24> s; + uint lo = 0, hi = 43 * 2; + for(uint x : range(43)) { + for(uint w : range(2)) { //16-bit words + uint z = 0; + for(uint y : range(24)) { + s[z++] = input[(y * 43 + x) * 2 + w]; + } + s.generateParity(); + parity[lo++] = s[z++]; + parity[hi++] = s[z++]; + } + } + return true; +} + +inline auto encodeQ(array_view input, array_span parity) -> bool { + ReedSolomon<45,43> s; + uint lo = 0, hi = 26 * 2; + for(uint y : range(26)) { + for(uint w : range(2)) { + uint z = 0; + for(uint x : range(43)) { + s[z++] = input[((x * 44 + y * 43) * 2 + w) % (26 * 43 * 2)]; + } + s.generateParity(); + parity[lo++] = s[z++]; + parity[hi++] = s[z++]; + } + } + return true; +} + +inline auto encodeMode1(array_span sector) -> bool { + if(sector.size() != 2352) return false; + if(!encodeP({sector + 12, 2064}, {sector + 2076, 172})) return false; + if(!encodeQ({sector + 12, 2236}, {sector + 2248, 104})) return false; + return true; +} + +// + +inline auto decodeP(array_span input, array_span parity) -> int { + bool success = false; + bool failure = false; + ReedSolomon<26,24> s; + uint lo = 0, hi = 43 * 2; + for(uint x : range(43)) { + for(uint w : range(2)) { + uint z = 0; + for(uint y : range(24)) { + s[z++] = input[(y * 43 + x) * 2 + w]; + } + s[z++] = parity[lo++]; + s[z++] = parity[hi++]; + auto count = s.correctErrors(); + if(count < 0) { + failure = true; + } + if(count > 0) { + success = true; + z = 0; + for(uint y : range(24)) { + input[(y * 43 + x) * 2 + w] = s[z++]; + } + parity[lo - 1] = s[z++]; + parity[hi - 1] = s[z++]; + } + } + } + if(!success && !failure) return 0; //no errors remaining + return success ? 1 : -1; //return success even if there are some failures +} + +inline auto decodeQ(array_span input, array_span parity) -> int { + bool success = false; + bool failure = false; + ReedSolomon<45,43> s; + uint lo = 0, hi = 26 * 2; + for(uint y : range(26)) { + for(uint w : range(2)) { + uint z = 0; + for(uint x : range(43)) { + s[z++] = input[((x * 44 + y * 43) * 2 + w) % (26 * 43 * 2)]; + } + s[z++] = parity[lo++]; + s[z++] = parity[hi++]; + auto count = s.correctErrors(); + if(count < 0) { + failure = true; + } + if(count > 0) { + success = true; + z = 0; + for(uint x : range(43)) { + input[((x * 44 + y * 43) * 2 + w) % (26 * 43 * 2)] = s[z++]; + } + parity[lo - 1] = s[z++]; + parity[hi - 1] = s[z++]; + } + } + } + if(!success && !failure) return 0; + return success ? 1 : -1; +} + +inline auto decodeMode1(array_span sector) -> bool { + if(sector.size() != 2352) return false; + //P corrections can allow Q corrections that previously failed to succeed, and vice versa. + //the more iterations, the more chances to correct errors, but the more computationally expensive it is. + //there must be a limit on the amount of retries, or this function may get stuck in an infinite loop. + for(uint attempt : range(4)) { + auto p = decodeP({sector + 12, 2064}, {sector + 2076, 172}); + auto q = decodeQ({sector + 12, 2236}, {sector + 2248, 104}); + if(p == 0 && q == 0) return true; //no errors remaining + if(p < 0 && q < 0) return false; //no more errors correctable + } + return false; //exhausted all retries with errors remaining +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/scrambler.hpp b/roms/snes-test-roms/bass-untech/nall/cd/scrambler.hpp new file mode 100644 index 00000000..cf7380e5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/scrambler.hpp @@ -0,0 +1,35 @@ +#pragma once + +namespace nall::CD::Scrambler { + +//polynomial(x) = x^15 + x + 1 +inline auto polynomial(uint x) -> uint8_t { + static uint8_t lookup[2340]{}; + static bool once = false; + if(!once) { once = true; + uint16_t shift = 0x0001; + for(uint n : range(2340)) { + lookup[n] = shift; + for(uint b : range(8)) { + bool carry = shift & 1 ^ shift >> 1 & 1; + shift = (carry << 15 | shift) >> 1; + } + } + } + return lookup[x]; +} + +// + +inline auto transform(array_span sector) -> bool { + if(sector.size() == 2352) sector += 12; //header is not scrambled + if(sector.size() != 2340) return false; //F1 frames only + + for(uint index : range(2340)) { + sector[index] ^= polynomial(index); + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/session.hpp b/roms/snes-test-roms/bass-untech/nall/cd/session.hpp new file mode 100644 index 00000000..a5a4f96a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/session.hpp @@ -0,0 +1,488 @@ +#pragma once + +//subchannel processor +//note: this code is not tolerant to subchannel data that violates the Redbook standard + +namespace nall::CD { + +enum : int { InvalidLBA = 100 * 60 * 75 }; + +struct BCD { + static auto encode(uint8_t value) -> uint8_t { return value / 10 << 4 | value % 10; } + static auto decode(uint8_t value) -> uint8_t { return (value >> 4) * 10 + (value & 15); } +}; + +struct MSF { + uint8_t minute; //00-99 + uint8_t second; //00-59 + uint8_t frame = -1; //00-74 + + MSF() = default; + MSF(uint8_t m, uint8_t s, uint8_t f) : minute(m), second(s), frame(f) {} + MSF(int lba) { *this = fromLBA(lba); } + + explicit operator bool() const { + return minute <= 99 && second <= 59 && frame <= 74; + } + + static auto fromBCD(uint8_t minute, uint8_t second, uint8_t frame) -> MSF { + return {BCD::decode(minute), BCD::decode(second), BCD::decode(frame)}; + } + + static auto fromLBA(int lba) -> MSF { + if(lba < 0) lba = 100 * 60 * 75 + lba; + if(lba >= 100 * 60 * 75) return {}; + uint8_t minute = lba / 75 / 60 % 100; + uint8_t second = lba / 75 % 60; + uint8_t frame = lba % 75; + return {minute, second, frame}; + } + + auto toLBA() const -> int { + int lba = minute * 60 * 75 + second * 75 + frame; + if(minute < 90) return lba; + return -(100 * 60 * 75 - lba); + } + + //for debugging purposes + auto toString() const -> string { + if(!operator bool()) return "??:??:??"; + return {pad(minute, 2, '0'), ":", pad(second, 2, '0'), ":", pad(frame, 2, '0')}; + } +}; + +struct Index { + int lba = InvalidLBA; + int end = InvalidLBA; //inclusive range + + explicit operator bool() const { + return lba != InvalidLBA; + } + + auto inRange(int sector) const -> bool { + if(lba == InvalidLBA || end == InvalidLBA) return false; + return sector >= lba && sector <= end; + } +}; + +struct Track { + uint8_t control = 0b1111; //4-bit + uint8_t address = 0b1111; //4-bit + Index indices[100]; + uint8_t firstIndex = -1; + uint8_t lastIndex = -1; + + explicit operator bool() const { + return (bool)indices[1]; + } + + auto emphasis() const -> bool { + return control & 1; + } + + auto copyable() const -> bool { + return control & 2; + } + + auto channels() const -> uint { + if((control & 0b1100) == 0b0000) return 2; + if((control & 0b1100) == 0b1000) return 4; + return 0; //data track or reserved + } + + auto pregap() const -> int { + if(!indices[0] || !indices[1]) return InvalidLBA; + return indices[1].lba - indices[0].lba; + } + + auto isAudio() const -> bool { + return channels() != 0; + } + + auto isData() const -> bool { + return (control & 0b1100) == 0b0100; + } + + auto inIndex(int lba) const -> maybe { + for(uint8_t index : range(100)) { + if(indices[index].inRange(lba)) return index; + } + return {}; + } + + auto inRange(int lba) const -> bool { + if(firstIndex > 99 || lastIndex > 99) return false; + return lba >= indices[firstIndex].lba && lba <= indices[lastIndex].end; + } + + auto index(uint8_t indexID) -> maybe { + if(indexID < 100 && indices[indexID]) return indices[indexID]; + return {}; + } +}; + +struct Session { + Index leadIn; //00 + Track tracks[100]; //01-99 + Index leadOut; //aa + uint8_t firstTrack = -1; + uint8_t lastTrack = -1; + + auto inLeadIn(int lba) const -> bool { + return lba < 0; + } + + auto inTrack(int lba) const -> maybe { + for(uint8_t trackID : range(100)) { + auto& track = tracks[trackID]; + if(track && track.inRange(lba)) return trackID; + } + return {}; + } + + auto inLeadOut(int lba) const -> bool { + return lba >= leadOut.lba; + } + + auto track(uint8_t trackID) -> maybe { + if(trackID < 100 && tracks[trackID]) return tracks[trackID]; + return {}; + } + + auto encode(uint sectors) const -> vector { + if(sectors < abs(leadIn.lba) + leadOut.lba) return {}; //not enough sectors + + vector data; + data.resize(sectors * 96 + 96); //add one sector for P shift + + auto toP = [&](int lba) -> array_span { + //P is encoded one sector later than Q + return {&data[(lba + abs(leadIn.lba) + 1) * 96], 12}; + }; + + auto toQ = [&](int lba) -> array_span { + return {&data[(lba + abs(leadIn.lba)) * 96 + 12], 12}; + }; + + //lead-in + int lba = leadIn.lba; + while(lba < 0) { + //tracks + for(uint trackID : range(100)) { + for(uint repeat : range(3)) { + auto& track = tracks[trackID]; + if(!track) continue; + auto q = toQ(lba); + q[0] = track.control << 4 | track.address << 0; + q[1] = 0x00; + q[2] = BCD::encode(trackID); + auto msf = MSF(lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + msf = MSF(track.indices[1].lba); + q[7] = BCD::encode(msf.minute); + q[8] = BCD::encode(msf.second); + q[9] = BCD::encode(msf.frame); + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + if(++lba >= 0) break; + }}if( lba >= 0) break; + + //first track + for(uint repeat : range(3)) { + auto q = toQ(lba); + q[0] = 0x01; //control value unverified; address = 1 + q[1] = 0x00; //track# = 00 (TOC) + q[2] = 0xa0; //first track + auto msf = MSF(lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + q[7] = BCD::encode(firstTrack); + q[8] = 0x00; + q[9] = 0x00; + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + if(++lba >= 0) break; + } if( lba >= 0) break; + + //last track + for(uint repeat : range(3)) { + auto q = toQ(lba); + q[0] = 0x01; + q[1] = 0x00; + q[2] = 0xa1; //last track + auto msf = MSF(lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + q[7] = BCD::encode(lastTrack); + q[8] = 0x00; + q[9] = 0x00; + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + if(++lba >= 0) break; + } if( lba >= 0) break; + + //lead-out point + for(uint repeat : range(3)) { + auto q = toQ(lba); + q[0] = 0x01; + q[1] = 0x00; + q[2] = 0xa2; //lead-out point + auto msf = MSF(lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + msf = MSF(leadOut.lba); + q[7] = BCD::encode(msf.minute); + q[8] = BCD::encode(msf.second); + q[9] = BCD::encode(msf.frame); + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + if(++lba >= 0) break; + } if( lba >= 0) break; + } + + //tracks + int end = leadOut.lba; + for(uint8_t trackID : reverse(range(100))) { + auto& track = tracks[trackID]; + if(!track) continue; + + //indices + for(uint8_t indexID : reverse(range(100))) { + auto& index = track.indices[indexID]; + if(!index) continue; + + for(int lba = index.lba; lba < end; lba++) { + auto p = toP(lba); + uint8_t byte = indexID == 0 ? 0xff : 0x00; + for(uint index : range(12)) p[index] = byte; + + auto q = toQ(lba); + q[0] = track.control << 4 | track.address << 0; + q[1] = BCD::encode(trackID); + q[2] = BCD::encode(indexID); + auto msf = MSF(lba - track.indices[1].lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + msf = MSF(lba); + q[7] = BCD::encode(msf.minute); + q[8] = BCD::encode(msf.second); + q[9] = BCD::encode(msf.frame); + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + } + + end = index.lba; + } + } + + //lead-out + for(int lba : range(sectors - abs(leadIn.lba) - leadOut.lba)) { + auto p = toP(leadOut.lba + lba); + uint8_t byte; + if(lba < 150) { + //2s start (standard specifies 2-3s start) + byte = 0x00; + } else { + //2hz duty cycle; rounded downward (standard specifies 2% tolerance) + byte = (lba - 150) / (75 >> 1) & 1 ? 0xff : 0x00; + } + for(uint index : range(12)) p[index] = byte; + + auto q = toQ(leadOut.lba + lba); + q[0] = 0x01; + q[1] = 0xaa; //lead-out track# + q[2] = 0x01; //lead-out index# + auto msf = MSF(lba); + q[3] = BCD::encode(msf.minute); + q[4] = BCD::encode(msf.second); + q[5] = BCD::encode(msf.frame); + q[6] = 0x00; + msf = MSF(leadOut.lba + lba); + q[7] = BCD::encode(msf.minute); + q[8] = BCD::encode(msf.second); + q[9] = BCD::encode(msf.frame); + auto crc16 = CRC16({q, 10}); + q[10] = crc16 >> 8; + q[11] = crc16 >> 0; + } + + data.resize(data.size() - 96); //remove padding for P shift + return data; + } + + auto decode(array_view data, uint size, uint leadOutSectors = 0) -> bool { + *this = {}; //reset session + //three data[] types supported: subcode Q only, subcode P-W only, data+subcode complete image + if(size != 12 && size != 96 && size != 2448) return false; + + //determine lead-in sector count + for(int lba : range(7500)) { //7500 max sectors scanned + uint offset = lba * size; + if(size == 96) offset += 12; + if(size == 2448) offset += 12 + 2352; + if(offset + 12 > data.size()) break; + auto q = array_view{&data[offset], 12}; + auto crc16 = CRC16({q, 10}); + if(q[10] != uint8_t(crc16 >> 8)) continue; + if(q[11] != uint8_t(crc16 >> 0)) continue; + + uint8_t control = q[0] >> 4; + uint8_t address = q[0] & 15; + uint8_t trackID = q[1]; + if(address != 1) continue; + if(trackID != 0) continue; + + auto msf = MSF::fromBCD(q[3], q[4], q[5]); + leadIn.lba = msf.toLBA() - lba; + break; + } + if(leadIn.lba == InvalidLBA || leadIn.lba >= 0) return false; + + auto toQ = [&](int lba) -> array_view { + uint offset = (lba + abs(leadIn.lba)) * size; + if(size == 96) offset += 12; + if(size == 2448) offset += 12 + 2352; + if(offset + 12 > data.size()) return {}; + return {&data[offset], 12}; + }; + + //lead-in + for(int lba = leadIn.lba; lba < 0; lba++) { + auto q = toQ(lba); + if(!q) break; + auto crc16 = CRC16({q, 10}); + if(q[10] != uint8_t(crc16 >> 8)) continue; + if(q[11] != uint8_t(crc16 >> 0)) continue; + + uint8_t control = q[0] >> 4; + uint8_t address = q[0] & 15; + uint8_t trackID = q[1]; + if(address != 1) continue; + if(trackID != 0) continue; + + trackID = BCD::decode(q[2]); + + if(trackID <= 99) { //00-99 + auto& track = tracks[trackID]; + track.control = control; + track.address = address; + track.indices[1].lba = MSF::fromBCD(q[7], q[8], q[9]).toLBA(); + } + + if(trackID == 100) { //a0 + firstTrack = BCD::decode(q[7]); + } + + if(trackID == 101) { //a1 + lastTrack = BCD::decode(q[7]); + } + + if(trackID == 102) { //a2 + leadOut.lba = MSF::fromBCD(q[7], q[8], q[9]).toLBA(); + } + } + if(leadOut.lba == InvalidLBA) return false; + + //tracks + for(int lba = 0; lba < leadOut.lba; lba++) { + auto q = toQ(lba); + if(!q) break; + auto crc16 = CRC16({q, 10}); + if(q[10] != uint8_t(crc16 >> 8)) continue; + if(q[11] != uint8_t(crc16 >> 0)) continue; + + uint8_t control = q[0] >> 4; + uint8_t address = q[0] & 15; + uint8_t trackID = BCD::decode(q[1]); + uint8_t indexID = BCD::decode(q[2]); + if(address != 1) continue; + if(trackID > 99) continue; + if(indexID > 99) continue; + + auto& track = tracks[trackID]; + if(!track) continue; //track not found? + auto& index = track.indices[indexID]; + if(index) continue; //index already decoded? + + index.lba = MSF::fromBCD(q[7], q[8], q[9]).toLBA(); + } + + synchronize(leadOutSectors); + return true; + } + + //calculates Index::end variables: + //needed for Session::isTrack() and Track::isIndex() to function. + auto synchronize(uint leadOutSectors = 0) -> void { + leadIn.end = -1; + int end = leadOut.lba - 1; + for(uint trackID : reverse(range(100))) { + auto& track = tracks[trackID]; + if(!track) continue; + + for(uint indexID : reverse(range(100))) { + auto& index = track.indices[indexID]; + if(!index) continue; + + index.end = end; + end = index.lba - 1; + } + + for(uint indexID : range(100)) { + auto& index = track.indices[indexID]; + if(index) { track.firstIndex = indexID; break; } + } + + for(uint indexID : reverse(range(100))) { + auto& index = track.indices[indexID]; + if(index) { track.lastIndex = indexID; break; } + } + } + leadOut.end = leadOut.lba + leadOutSectors - 1; + } + + //for diagnostic use only + auto serialize() const -> string { + string s; + s.append("session\n"); + s.append(" leadIn: "); + s.append(MSF(leadIn.lba).toString(), " - ", MSF(leadIn.end).toString(), "\n"); + for(uint trackID : range(100)) { + auto& track = tracks[trackID]; + if(!track) continue; + s.append(" track", pad(trackID, 2, '0')); + if(trackID == firstTrack) s.append(" first"); + if(trackID == lastTrack) s.append( " last"); + s.append("\n"); + s.append(" control: ", binary(track.control, 4, '0'), "\n"); + s.append(" address: ", binary(track.address, 4, '0'), "\n"); + for(uint indexID : range(100)) { + auto& index = track.indices[indexID]; + if(!index) continue; + s.append(" index", pad(indexID, 2, '0'), ": "); + s.append(MSF(index.lba).toString(), " - ", MSF(index.end).toString(), "\n"); + } + } + s.append(" leadOut: "); + s.append(MSF(leadOut.lba).toString(), " - ", MSF(leadOut.end).toString(), "\n"); + return s; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cd/sync.hpp b/roms/snes-test-roms/bass-untech/nall/cd/sync.hpp new file mode 100644 index 00000000..2d9620a2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cd/sync.hpp @@ -0,0 +1,27 @@ +#pragma once + +namespace nall::CD::Sync { + +inline auto create(array_span sector) -> bool { + if(sector.size() != 12 && sector.size() != 2352) return false; + + for(uint n : range(12)) { + sector[n] = ((n == 0 || n == 11) ? 0x00 : 0xff); + } + + return true; +} + +// + +inline auto verify(array_view sector) -> bool { + if(sector.size() != 12 && sector.size() != 2352) return false; + + for(uint n : range(12)) { + if(sector[n] != ((n == 0 || n == 11) ? 0x00 : 0xff)) return false; + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/chrono.hpp b/roms/snes-test-roms/bass-untech/nall/chrono.hpp new file mode 100644 index 00000000..7e4ea829 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/chrono.hpp @@ -0,0 +1,183 @@ +#pragma once + +#include +#include + +namespace nall::chrono { + +//passage of time functions (from unknown epoch) + +inline auto nanosecond() -> uint64_t { + timespec tv; + clock_gettime(CLOCK_MONOTONIC, &tv); + return tv.tv_sec * 1'000'000'000 + tv.tv_nsec; +} + +inline auto microsecond() -> uint64_t { return nanosecond() / 1'000; } +inline auto millisecond() -> uint64_t { return nanosecond() / 1'000'000; } +inline auto second() -> uint64_t { return nanosecond() / 1'000'000'000; } + +inline auto benchmark(const function& f, uint64_t times = 1) -> void { + auto start = nanosecond(); + while(times--) f(); + auto end = nanosecond(); + print("[chrono::benchmark] ", (double)(end - start) / 1'000'000'000.0, "s\n"); +} + +//exact date/time functions (from system epoch) + +struct timeinfo { + timeinfo( + uint year = 0, uint month = 0, uint day = 0, + uint hour = 0, uint minute = 0, uint second = 0, uint weekday = 0 + ) : year(year), month(month), day(day), + hour(hour), minute(minute), second(second), weekday(weekday) { + } + + explicit operator bool() const { return month; } + + uint year; //... + uint month; //1 - 12 + uint day; //1 - 31 + uint hour; //0 - 23 + uint minute; //0 - 59 + uint second; //0 - 60 + uint weekday; //0 - 6 +}; + +inline auto timestamp() -> uint64_t { + return ::time(nullptr); +} + +//0 = failure condition +inline auto timestamp(const string& datetime) -> uint64_t { + static const uint monthDays[] = {31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31}; + uint64_t timestamp = 0; + if(datetime.match("??????????")) { + return datetime.natural(); + } + if(datetime.match("????*")) { + uint year = datetime.slice(0, 4).natural(); + if(year < 1970 || year > 2199) return 0; + for(uint y = 1970; y < year && y < 2999; y++) { + uint daysInYear = 365; + if(y % 4 == 0 && (y % 100 != 0 || y % 400 == 0)) daysInYear++; + timestamp += daysInYear * 24 * 60 * 60; + } + } + if(datetime.match("????-??*")) { + uint y = datetime.slice(0, 4).natural(); + uint month = datetime.slice(5, 2).natural(); + if(month < 1 || month > 12) return 0; + for(uint m = 1; m < month && m < 12; m++) { + uint daysInMonth = monthDays[m - 1]; + if(m == 2 && y % 4 == 0 && (y % 100 != 0 || y % 400 == 0)) daysInMonth++; + timestamp += daysInMonth * 24 * 60 * 60; + } + } + if(datetime.match("????-??-??*")) { + uint day = datetime.slice(8, 2).natural(); + if(day < 1 || day > 31) return 0; + timestamp += (day - 1) * 24 * 60 * 60; + } + if(datetime.match("????-??-?? ??*")) { + uint hour = datetime.slice(11, 2).natural(); + if(hour > 23) return 0; + timestamp += hour * 60 * 60; + } + if(datetime.match("????-??-?? ??:??*")) { + uint minute = datetime.slice(14, 2).natural(); + if(minute > 59) return 0; + timestamp += minute * 60; + } + if(datetime.match("????-??-?? ??:??:??*")) { + uint second = datetime.slice(17, 2).natural(); + if(second > 59) return 0; + timestamp += second; + } + return timestamp; +} + +namespace utc { + inline auto timeinfo(uint64_t time = 0) -> chrono::timeinfo { + auto stamp = time ? (time_t)time : (time_t)timestamp(); + auto info = gmtime(&stamp); + return { + (uint)info->tm_year + 1900, + (uint)info->tm_mon + 1, + (uint)info->tm_mday, + (uint)info->tm_hour, + (uint)info->tm_min, + (uint)info->tm_sec, + (uint)info->tm_wday + }; + } + + inline auto year(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).year, 4, '0'); } + inline auto month(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).month, 2, '0'); } + inline auto day(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).day, 2, '0'); } + inline auto hour(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).hour, 2, '0'); } + inline auto minute(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).minute, 2, '0'); } + inline auto second(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).second, 2, '0'); } + + inline auto date(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return {pad(t.year, 4, '0'), "-", pad(t.month, 2, '0'), "-", pad(t.day, 2, '0')}; + } + + inline auto time(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return {pad(t.hour, 2, '0'), ":", pad(t.minute, 2, '0'), ":", pad(t.second, 2, '0')}; + } + + inline auto datetime(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return { + pad(t.year, 4, '0'), "-", pad(t.month, 2, '0'), "-", pad(t.day, 2, '0'), " ", + pad(t.hour, 2, '0'), ":", pad(t.minute, 2, '0'), ":", pad(t.second, 2, '0') + }; + } +} + +namespace local { + inline auto timeinfo(uint64_t time = 0) -> chrono::timeinfo { + auto stamp = time ? (time_t)time : (time_t)timestamp(); + auto info = localtime(&stamp); + return { + (uint)info->tm_year + 1900, + (uint)info->tm_mon + 1, + (uint)info->tm_mday, + (uint)info->tm_hour, + (uint)info->tm_min, + (uint)info->tm_sec, + (uint)info->tm_wday + }; + } + + inline auto year(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).year, 4, '0'); } + inline auto month(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).month, 2, '0'); } + inline auto day(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).day, 2, '0'); } + inline auto hour(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).hour, 2, '0'); } + inline auto minute(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).minute, 2, '0'); } + inline auto second(uint64_t timestamp = 0) -> string { return pad(timeinfo(timestamp).second, 2, '0'); } + + inline auto date(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return {pad(t.year, 4, '0'), "-", pad(t.month, 2, '0'), "-", pad(t.day, 2, '0')}; + } + + inline auto time(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return {pad(t.hour, 2, '0'), ":", pad(t.minute, 2, '0'), ":", pad(t.second, 2, '0')}; + } + + inline auto datetime(uint64_t timestamp = 0) -> string { + auto t = timeinfo(timestamp); + return { + pad(t.year, 4, '0'), "-", pad(t.month, 2, '0'), "-", pad(t.day, 2, '0'), " ", + pad(t.hour, 2, '0'), ":", pad(t.minute, 2, '0'), ":", pad(t.second, 2, '0') + }; + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/cipher/chacha20.hpp b/roms/snes-test-roms/bass-untech/nall/cipher/chacha20.hpp new file mode 100644 index 00000000..4dcb0afd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/cipher/chacha20.hpp @@ -0,0 +1,109 @@ +#pragma once + +#include +#include + +namespace nall::Cipher { + +//64-bit nonce; 64-bit x 64-byte (256GB) counter +struct ChaCha20 { + ChaCha20(uint256_t key, uint64_t nonce, uint64_t counter = 0) { + static const uint128_t sigma = 0x6b20657479622d323320646e61707865_u128; //"expand 32-byte k" + + input[ 0] = sigma >> 0; + input[ 1] = sigma >> 32; + input[ 2] = sigma >> 64; + input[ 3] = sigma >> 96; + input[ 4] = key >> 0; + input[ 5] = key >> 32; + input[ 6] = key >> 64; + input[ 7] = key >> 96; + input[ 8] = key >> 128; + input[ 9] = key >> 160; + input[10] = key >> 192; + input[11] = key >> 224; + input[12] = counter >> 0; + input[13] = counter >> 32; + input[14] = nonce >> 0; + input[15] = nonce >> 32; + + offset = 0; + } + + auto encrypt(array_view input) -> vector { + vector output; + while(input) { + if(!offset) { + cipher(); + increment(); + } + auto byte = offset++; + output.append(*input++ ^ (block[byte >> 2] >> (byte & 3) * 8)); + offset &= 63; + } + return output; + } + + auto decrypt(array_view input) -> vector { + return encrypt(input); //reciprocal cipher + } + +//protected: + auto rol(uint32_t value, uint bits) -> uint32_t { + return value << bits | value >> 32 - bits; + } + + auto quarterRound(uint32_t x[16], uint a, uint b, uint c, uint d) -> void { + x[a] += x[b]; x[d] = rol(x[d] ^ x[a], 16); + x[c] += x[d]; x[b] = rol(x[b] ^ x[c], 12); + x[a] += x[b]; x[d] = rol(x[d] ^ x[a], 8); + x[c] += x[d]; x[b] = rol(x[b] ^ x[c], 7); + } + + auto cipher() -> void { + memory::copy(block, input, 64); + for(uint n : range(10)) { + quarterRound(block, 0, 4, 8, 12); + quarterRound(block, 1, 5, 9, 13); + quarterRound(block, 2, 6, 10, 14); + quarterRound(block, 3, 7, 11, 15); + quarterRound(block, 0, 5, 10, 15); + quarterRound(block, 1, 6, 11, 12); + quarterRound(block, 2, 7, 8, 13); + quarterRound(block, 3, 4, 9, 14); + } + } + + auto increment() -> void { + for(uint n : range(16)) { + block[n] += input[n]; + } + if(!++input[12]) ++input[13]; + } + + uint32_t input[16]; + uint32_t block[16]; + uint64_t offset; +}; + +struct HChaCha20 : protected ChaCha20 { + HChaCha20(uint256_t key, uint128_t nonce) : ChaCha20(key, nonce >> 64, nonce >> 0) { + cipher(); + } + + auto key() const -> uint256_t { + uint256_t key = 0; + for(uint n : range(4)) key |= (uint256_t)block[ 0 + n] << (n + 0) * 32; + for(uint n : range(4)) key |= (uint256_t)block[12 + n] << (n + 4) * 32; + return key; + } +}; + +//192-bit nonce; 64-bit x 64-byte (256GB) counter +struct XChaCha20 : ChaCha20 { + XChaCha20(uint256_t key, uint192_t nonce, uint64_t counter = 0): + ChaCha20(HChaCha20(key, nonce).key(), nonce >> 128, counter) { + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/counting-sort.hpp b/roms/snes-test-roms/bass-untech/nall/counting-sort.hpp new file mode 100644 index 00000000..e4f7100e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/counting-sort.hpp @@ -0,0 +1,19 @@ +#pragma once + +#include + +namespace nall { + +//counting sort by powers of two: used to implement radix sort +template +auto counting_sort(T* output, const T* input, uint size) -> void { + static_assert(Bits >= 1 && Bits <= 20, "must be between 1 and 20 bits"); + enum : uint { Base = 1 << Bits, Mask = Base - 1 }; + + uint64_t count[Base] = {}, last = 0; + for(uint n : range(size)) ++count[(input[n] >> Shift) & Mask]; + for(uint n : range(Base)) last += count[n], count[n] = last - count[n]; + for(uint n : range(size)) output[count[(input[n] >> Shift) & Mask]++] = input[n]; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/database/odbc.hpp b/roms/snes-test-roms/bass-untech/nall/database/odbc.hpp new file mode 100644 index 00000000..bd3cba17 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/database/odbc.hpp @@ -0,0 +1,299 @@ +#pragma once + +//legacy code; no longer used + +#include + +#include +#include +#include + +namespace nall::Database { + +struct ODBC { + struct Statement { + Statement(const Statement& source) = delete; + auto operator=(const Statement& source) -> Statement& = delete; + + Statement(SQLHANDLE statement) : _statement(statement) {} + Statement(Statement&& source) { operator=(move(source)); } + + auto operator=(Statement&& source) -> Statement& { + _statement = source._statement; + _output = source._output; + _values = move(source._values); + source._statement = nullptr; + source._output = 0; + return *this; + } + + auto columns() -> unsigned { + SQLSMALLINT columns = 0; + if(statement()) SQLNumResultCols(statement(), &columns); + return columns; + } + + auto integer(unsigned column) -> int64_t { + if(auto value = _values(column)) return value.get(0); + int64_t value = 0; + SQLGetData(statement(), 1 + column, SQL_C_SBIGINT, &value, 0, nullptr); + _values(column) = (int64_t)value; + return value; + } + + auto natural(unsigned column) -> uint64_t { + if(auto value = _values(column)) return value.get(0); + uint64_t value = 0; + SQLGetData(statement(), 1 + column, SQL_C_UBIGINT, &value, 0, nullptr); + _values(column) = (uint64_t)value; + return value; + } + + auto real(unsigned column) -> double { + if(auto value = _values(column)) return value.get(0.0); + double value = 0.0; + SQLGetData(statement(), 1 + column, SQL_C_DOUBLE, &value, 0, nullptr); + _values(column) = (double)value; + return value; + } + + auto text(unsigned column) -> string { + if(auto value = _values(column)) return value.get({}); + string value; + value.resize(65535); + SQLLEN size = 0; + SQLGetData(statement(), 1 + column, SQL_C_CHAR, value.get(), value.size(), &size); + value.resize(size); + _values(column) = (string)value; + return value; + } + + auto data(unsigned column) -> vector { + if(auto value = _values(column)) return value.get>({}); + vector value; + value.resize(65535); + SQLLEN size = 0; + SQLGetData(statement(), 1 + column, SQL_C_CHAR, value.data(), value.size(), &size); + value.resize(size); + _values(column) = (vector)value; + return value; + } + + auto integer() -> int64_t { return integer(_output++); } + auto natural() -> uint64_t { return natural(_output++); } + auto real() -> double { return real(_output++); } + auto text() -> string { return text(_output++); } + auto data() -> vector { return data(_output++); } + + protected: + virtual auto statement() -> SQLHANDLE { return _statement; } + + SQLHANDLE _statement = nullptr; + unsigned _output = 0; + vector _values; //some ODBC drivers (eg MS-SQL) do not allow the same column to be read more than once + }; + + struct Query : Statement { + Query(const Query& source) = delete; + auto operator=(const Query& source) -> Query& = delete; + + Query(SQLHANDLE statement) : Statement(statement) {} + Query(Query&& source) : Statement(source._statement) { operator=(move(source)); } + + ~Query() { + if(statement()) { + SQLFreeHandle(SQL_HANDLE_STMT, _statement); + _statement = nullptr; + } + } + + auto operator=(Query&& source) -> Query& { + Statement::operator=(move(source)); + _bindings = move(source._bindings); + _result = source._result; + _input = source._input; + _stepped = source._stepped; + source._result = SQL_SUCCESS; + source._input = 0; + source._stepped = false; + return *this; + } + + explicit operator bool() { + //this is likely not the best way to test if the query has returned data ... + //but I wasn't able to find an ODBC API for this seemingly simple task + return statement() && success(); + } + + //ODBC SQLBindParameter only holds pointers to data values + //if the bound paramters go out of scope before the query is executed, binding would reference dangling pointers + //so to work around this, we cache all parameters inside Query until the query is executed + + auto& bind(unsigned column, nullptr_t) { return _bindings.append({column, any{(nullptr_t)nullptr}}), *this; } + auto& bind(unsigned column, int32_t value) { return _bindings.append({column, any{(int32_t)value}}), *this; } + auto& bind(unsigned column, uint32_t value) { return _bindings.append({column, any{(uint32_t)value}}), *this; } + auto& bind(unsigned column, int64_t value) { return _bindings.append({column, any{(int64_t)value}}), *this; } + auto& bind(unsigned column, uint64_t value) { return _bindings.append({column, any{(uint64_t)value}}), *this; } + auto& bind(unsigned column, double value) { return _bindings.append({column, any{(double)value}}), *this; } + auto& bind(unsigned column, const string& value) { return _bindings.append({column, any{(string)value}}), *this; } + auto& bind(unsigned column, const vector& value) { return _bindings.append({column, any{(vector)value}}), *this; } + + auto& bind(nullptr_t) { return bind(_input++, nullptr); } + auto& bind(int32_t value) { return bind(_input++, value); } + auto& bind(uint32_t value) { return bind(_input++, value); } + auto& bind(int64_t value) { return bind(_input++, value); } + auto& bind(uint64_t value) { return bind(_input++, value); } + auto& bind(double value) { return bind(_input++, value); } + auto& bind(const string& value) { return bind(_input++, value); } + auto& bind(const vector& value) { return bind(_input++, value); } + + auto step() -> bool { + if(!_stepped) { + for(auto& binding : _bindings) { + if(binding.value.is()) { + SQLLEN length = SQL_NULL_DATA; + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_NUMERIC, SQL_NUMERIC, 0, 0, nullptr, 0, &length); + } else if(binding.value.is()) { + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_SLONG, SQL_INTEGER, 0, 0, &binding.value.get(), 0, nullptr); + } else if(binding.value.is()) { + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_ULONG, SQL_INTEGER, 0, 0, &binding.value.get(), 0, nullptr); + } else if(binding.value.is()) { + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_SBIGINT, SQL_INTEGER, 0, 0, &binding.value.get(), 0, nullptr); + } else if(binding.value.is()) { + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_UBIGINT, SQL_INTEGER, 0, 0, &binding.value.get(), 0, nullptr); + } else if(binding.value.is()) { + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_DOUBLE, SQL_DOUBLE, 0, 0, &binding.value.get(), 0, nullptr); + } else if(binding.value.is()) { + auto& value = binding.value.get(); + SQLLEN length = SQL_NTS; + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_CHAR, SQL_VARCHAR, value.size(), 0, (SQLPOINTER)value.data(), 0, &length); + } else if(binding.value.is>()) { + auto& value = binding.value.get>(); + SQLLEN length = value.size(); + SQLBindParameter(_statement, 1 + binding.column, SQL_PARAM_INPUT, SQL_C_CHAR, SQL_VARBINARY, value.size(), 0, (SQLPOINTER)value.data(), 0, &length); + } + } + + _stepped = true; + _result = SQLExecute(_statement); + if(!success()) return false; + } + + _values.reset(); //clear previous row's cached read results + _result = SQLFetch(_statement); + _output = 0; + return success(); + } + + struct Iterator { + Iterator(Query& query, bool finished) : query(query), finished(finished) {} + auto operator*() -> Statement { return query._statement; } + auto operator!=(const Iterator& source) const -> bool { return finished != source.finished; } + auto operator++() -> Iterator& { finished = !query.step(); return *this; } + + protected: + Query& query; + bool finished = false; + }; + + auto begin() -> Iterator { return Iterator(*this, !step()); } + auto end() -> Iterator { return Iterator(*this, true); } + + private: + auto success() const -> bool { + return _result == SQL_SUCCESS || _result == SQL_SUCCESS_WITH_INFO; + } + + auto statement() -> SQLHANDLE override { + if(!_stepped) step(); + return _statement; + } + + struct Binding { + unsigned column; + any value; + }; + vector _bindings; + + SQLRETURN _result = SQL_SUCCESS; + unsigned _input = 0; + bool _stepped = false; + }; + + ODBC() { + _result = SQLAllocHandle(SQL_HANDLE_ENV, SQL_NULL_HANDLE, &_environment); + if(!success()) return; + + SQLSetEnvAttr(_environment, SQL_ATTR_ODBC_VERSION, (void*)SQL_OV_ODBC3, 0); + } + + ODBC(const string& database, const string& username, const string& password) : ODBC() { + open(database, username, password); + } + + ~ODBC() { + if(_environment) { + close(); + SQLFreeHandle(SQL_HANDLE_ENV, _environment); + _environment = nullptr; + } + } + + explicit operator bool() const { return _connection; } + + auto open(const string& database, const string& username, const string& password) -> bool { + if(!_environment) return false; + close(); + + _result = SQLAllocHandle(SQL_HANDLE_DBC, _environment, &_connection); + if(!success()) return false; + + SQLSetConnectAttr(_connection, SQL_LOGIN_TIMEOUT, (SQLPOINTER)5, 0); + _result = SQLConnectA(_connection, + (SQLCHAR*)database.data(), SQL_NTS, + (SQLCHAR*)username.data(), SQL_NTS, + (SQLCHAR*)password.data(), SQL_NTS + ); + if(!success()) return close(), false; + + return true; + } + + auto close() -> void { + if(_connection) { + SQLDisconnect(_connection); + SQLFreeHandle(SQL_HANDLE_DBC, _connection); + _connection = nullptr; + } + } + + template auto execute(const string& statement, P&&... p) -> Query { + if(!_connection) return {nullptr}; + + SQLHANDLE _statement = nullptr; + _result = SQLAllocHandle(SQL_HANDLE_STMT, _connection, &_statement); + if(!success()) return {nullptr}; + + Query query{_statement}; + _result = SQLPrepareA(_statement, (SQLCHAR*)statement.data(), SQL_NTS); + if(!success()) return {nullptr}; + + bind(query, forward

(p)...); + return query; + } + +private: + auto success() const -> bool { return _result == SQL_SUCCESS || _result == SQL_SUCCESS_WITH_INFO; } + + auto bind(Query&) -> void {} + template auto bind(Query& query, const T& value, P&&... p) -> void { + query.bind(value); + bind(query, forward

(p)...); + } + + SQLHANDLE _environment = nullptr; + SQLHANDLE _connection = nullptr; + SQLRETURN _result = SQL_SUCCESS; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/database/sqlite3.hpp b/roms/snes-test-roms/bass-untech/nall/database/sqlite3.hpp new file mode 100644 index 00000000..10ab8729 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/database/sqlite3.hpp @@ -0,0 +1,218 @@ +#pragma once + +//SQLite3 C++ RAII wrapper for nall +//note: it is safe (no-op) to call sqlite3_* functions on null sqlite3 objects + +#include + +#include +#include + +namespace nall::Database { + +struct SQLite3 { + struct Statement { + Statement(const Statement& source) = delete; + auto operator=(const Statement& source) -> Statement& = delete; + + Statement(sqlite3_stmt* statement) : _statement(statement) {} + Statement(Statement&& source) { operator=(move(source)); } + + auto operator=(Statement&& source) -> Statement& { + _statement = source._statement; + _response = source._response; + _output = source._output; + source._statement = nullptr; + source._response = SQLITE_OK; + source._output = 0; + return *this; + } + + explicit operator bool() { + return sqlite3_data_count(statement()); + } + + auto columns() -> uint { + return sqlite3_column_count(statement()); + } + + auto boolean(uint column) -> bool { + return sqlite3_column_int64(statement(), column) != 0; + } + + auto integer(uint column) -> int64_t { + return sqlite3_column_int64(statement(), column); + } + + auto natural(uint column) -> uint64_t { + return sqlite3_column_int64(statement(), column); + } + + auto real(uint column) -> double { + return sqlite3_column_double(statement(), column); + } + + auto string(uint column) -> nall::string { + nall::string result; + if(auto text = sqlite3_column_text(statement(), column)) { + result.resize(sqlite3_column_bytes(statement(), column)); + memory::copy(result.get(), text, result.size()); + } + return result; + } + + auto data(uint column) -> vector { + vector result; + if(auto data = sqlite3_column_blob(statement(), column)) { + result.resize(sqlite3_column_bytes(statement(), column)); + memory::copy(result.data(), data, result.size()); + } + return result; + } + + auto boolean() -> bool { return boolean(_output++); } + auto integer() -> int64_t { return integer(_output++); } + auto natural() -> uint64_t { return natural(_output++); } + auto real() -> double { return real(_output++); } + auto string() -> nall::string { return string(_output++); } + auto data() -> vector { return data(_output++); } + + protected: + virtual auto statement() -> sqlite3_stmt* { return _statement; } + + sqlite3_stmt* _statement = nullptr; + int _response = SQLITE_OK; + uint _output = 0; + }; + + struct Query : Statement { + Query(const Query& source) = delete; + auto operator=(const Query& source) -> Query& = delete; + + Query(sqlite3_stmt* statement) : Statement(statement) {} + Query(Query&& source) : Statement(source._statement) { operator=(move(source)); } + + ~Query() { + sqlite3_finalize(statement()); + _statement = nullptr; + } + + auto operator=(Query&& source) -> Query& { + _statement = source._statement; + _input = source._input; + source._statement = nullptr; + source._input = 0; + return *this; + } + + auto& bind(uint column, nullptr_t) { sqlite3_bind_null(_statement, 1 + column); return *this; } + auto& bind(uint column, bool value) { sqlite3_bind_int(_statement, 1 + column, value); return *this; } + auto& bind(uint column, int32_t value) { sqlite3_bind_int(_statement, 1 + column, value); return *this; } + auto& bind(uint column, uint32_t value) { sqlite3_bind_int(_statement, 1 + column, value); return *this; } + auto& bind(uint column, int64_t value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, uint64_t value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, intmax value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, uintmax value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, nall::boolean value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, nall::integer value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, nall::natural value) { sqlite3_bind_int64(_statement, 1 + column, value); return *this; } + auto& bind(uint column, double value) { sqlite3_bind_double(_statement, 1 + column, value); return *this; } + auto& bind(uint column, const nall::string& value) { sqlite3_bind_text(_statement, 1 + column, value.data(), value.size(), SQLITE_TRANSIENT); return *this; } + auto& bind(uint column, const vector& value) { sqlite3_bind_blob(_statement, 1 + column, value.data(), value.size(), SQLITE_TRANSIENT); return *this; } + + auto& bind(nullptr_t) { return bind(_input++, nullptr); } + auto& bind(bool value) { return bind(_input++, value); } + auto& bind(int32_t value) { return bind(_input++, value); } + auto& bind(uint32_t value) { return bind(_input++, value); } + auto& bind(int64_t value) { return bind(_input++, value); } + auto& bind(uint64_t value) { return bind(_input++, value); } + auto& bind(intmax value) { return bind(_input++, value); } + auto& bind(uintmax value) { return bind(_input++, value); } + auto& bind(nall::boolean value) { return bind(_input++, value); } + auto& bind(nall::integer value) { return bind(_input++, value); } + auto& bind(nall::natural value) { return bind(_input++, value); } + auto& bind(double value) { return bind(_input++, value); } + auto& bind(const nall::string& value) { return bind(_input++, value); } + auto& bind(const vector& value) { return bind(_input++, value); } + + auto step() -> bool { + _stepped = true; + return sqlite3_step(_statement) == SQLITE_ROW; + } + + struct Iterator { + Iterator(Query& query, bool finished) : query(query), finished(finished) {} + auto operator*() -> Statement { return query._statement; } + auto operator!=(const Iterator& source) const -> bool { return finished != source.finished; } + auto operator++() -> Iterator& { finished = !query.step(); return *this; } + + protected: + Query& query; + bool finished = false; + }; + + auto begin() -> Iterator { return Iterator(*this, !step()); } + auto end() -> Iterator { return Iterator(*this, true); } + + private: + auto statement() -> sqlite3_stmt* override { + if(!_stepped) step(); + return _statement; + } + + uint _input = 0; + bool _stepped = false; + }; + + SQLite3() = default; + SQLite3(const string& filename) { open(filename); } + ~SQLite3() { close(); } + + explicit operator bool() const { return _database; } + + auto open(const string& filename) -> bool { + close(); + sqlite3_open(filename, &_database); + return _database; + } + + auto close() -> void { + sqlite3_close(_database); + _database = nullptr; + } + + template auto execute(const string& statement, P&&... p) -> Query { + if(!_database) return {nullptr}; + + sqlite3_stmt* _statement = nullptr; + sqlite3_prepare_v2(_database, statement.data(), statement.size(), &_statement, nullptr); + if(!_statement) { + if(_debug) print("[sqlite3_prepare_v2] ", sqlite3_errmsg(_database), "\n"); + return {nullptr}; + } + + Query query{_statement}; + bind(query, forward

(p)...); + return query; + } + + auto lastInsertID() const -> uint64_t { + return _database ? sqlite3_last_insert_rowid(_database) : 0; + } + + auto setDebug(bool debug = true) -> void { + _debug = debug; + } + +protected: + auto bind(Query&) -> void {} + template auto bind(Query& query, const T& value, P&&... p) -> void { + query.bind(value); + bind(query, forward

(p)...); + } + + bool _debug = false; + sqlite3* _database = nullptr; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/base.hpp b/roms/snes-test-roms/bass-untech/nall/decode/base.hpp new file mode 100644 index 00000000..d20f1a5e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/base.hpp @@ -0,0 +1,37 @@ +#pragma once + +#include + +namespace nall::Decode { + +template inline auto Base(const string& value) -> T { + static const string format = + Bits == 2 ? "01" + : Bits == 8 ? "01234567" + : Bits == 10 ? "0123456789" + : Bits == 16 ? "0123456789abcdef" + : Bits == 32 ? "0123456789abcdefghijklmnopqrstuv" + : Bits == 34 ? "023456789abcdefghijkmnopqrstuvwxyz" //1l + : Bits == 36 ? "0123456789abcdefghijklmnopqrstuvwxyz" + : Bits == 57 ? "23456789ABCDEFGHJKLMNPQRSTUVWXYZabcdefghijkmnopqrstuvwxyz" //01IOl + : Bits == 62 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz" + : Bits == 64 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz{}" + : Bits == 85 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz!#$%()+,-.:;=@[]^_`{|}~" //\ "&'*/<>? + : ""; + static bool initialized = false; + static uint8_t lookup[256] = {0}; + if(!initialized) { + initialized = true; + for(uint n : range(format.size())) { + lookup[format[n]] = n; + } + } + + T result = 0; + for(auto byte : value) { + result = result * Bits + lookup[byte]; + } + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/base64.hpp b/roms/snes-test-roms/bass-untech/nall/decode/base64.hpp new file mode 100644 index 00000000..a613d346 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/base64.hpp @@ -0,0 +1,47 @@ +#pragma once + +namespace nall::Decode { + +inline auto Base64(const string& text) -> vector { + static bool initialized = false; + static uint8_t lookup[256] = {0}; + if(!initialized) { + initialized = true; + for(uint n : range(26)) lookup['A' + n] = n; + for(uint n : range(26)) lookup['a' + n] = n + 26; + for(uint n : range(10)) lookup['0' + n] = n + 52; + lookup['+'] = lookup['-'] = 62; + lookup['/'] = lookup['_'] = 63; + } + + vector result; + uint8_t buffer, output; + for(uint n : range(text.size())) { + uint8_t buffer = lookup[text[n]]; + + switch(n & 3) { + case 0: + output = buffer << 2; + break; + + case 1: + result.append(output | buffer >> 4); + output = (buffer & 15) << 4; + break; + + case 2: + result.append(output | buffer >> 2); + output = (buffer & 3) << 6; + break; + + case 3: + result.append(output | buffer); + break; + } + } + + if(text.size() & 3) result.append(output | buffer); + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/bmp.hpp b/roms/snes-test-roms/bass-untech/nall/decode/bmp.hpp new file mode 100644 index 00000000..fcfcf407 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/bmp.hpp @@ -0,0 +1,76 @@ +#pragma once + +namespace nall::Decode { + +struct BMP { + BMP() = default; + BMP(const string& filename) { load(filename); } + BMP(const uint8_t* data, uint size) { load(data, size); } + + explicit operator bool() const { return _data; } + + auto reset() -> void { + if(_data) { delete[] _data; _data = nullptr; } + } + + auto data() -> uint32_t* { return _data; } + auto data() const -> const uint32_t* { return _data; } + auto width() const -> uint { return _width; } + auto height() const -> uint { return _height; } + + auto load(const string& filename) -> bool { + auto buffer = file::read(filename); + return load(buffer.data(), buffer.size()); + } + + auto load(const uint8_t* data, uint size) -> bool { + if(size < 0x36) return false; + const uint8_t* p = data; + if(read(p, 2) != 0x4d42) return false; //signature + read(p, 8); + uint offset = read(p, 4); + if(read(p, 4) != 40) return false; //DIB size + int width = (int32_t)read(p, 4); + if(width < 0) width = -width; + int height = (int32_t)read(p, 4); + bool flip = height >= 0; + if(height < 0) height = -height; + read(p, 2); + uint bitsPerPixel = read(p, 2); + if(bitsPerPixel != 24 && bitsPerPixel != 32) return false; + if(read(p, 4) != 0) return false; //compression type + + _width = width; + _height = height; + _data = new uint32_t[width * height]; + + uint bytesPerPixel = bitsPerPixel / 8; + uint alignedWidth = width * bytesPerPixel; + uint paddingLength = 0; + while(alignedWidth % 4) alignedWidth++, paddingLength++; + + p = data + offset; + for(auto y : range(height)) { + uint32_t* output = flip ? _data + (height - 1 - y) * width : _data + y * width; + for(auto x : range(width)) { + *output++ = read(p, bytesPerPixel) | (bitsPerPixel == 24 ? 255u << 24 : 0); + } + if(paddingLength) read(p, paddingLength); + } + + return true; + } + +private: + uint32_t* _data = nullptr; + uint _width = 0; + uint _height = 0; + + auto read(const uint8_t*& buffer, uint length) -> uint64_t { + uint64_t result = 0; + for(uint n : range(length)) result |= (uint64_t)*buffer++ << (n << 3); + return result; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/bwt.hpp b/roms/snes-test-roms/bass-untech/nall/decode/bwt.hpp new file mode 100644 index 00000000..5aeb1f8c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/bwt.hpp @@ -0,0 +1,47 @@ +#pragma once + +//burrows-wheeler transform + +#include + +namespace nall::Decode { + +inline auto BWT(array_view input) -> vector { + vector output; + + uint size = 0; + for(uint byte : range(8)) size |= *input++ << byte * 8; + output.resize(size); + + uint I = 0; + for(uint byte : range(8)) I |= *input++ << byte * 8; + + auto suffixes = SuffixArray(input); + + auto L = input; + auto F = new uint8_t[size]; + for(uint offset : range(size)) F[offset] = L[suffixes[offset + 1]]; + + uint64_t K[256] = {}; + auto C = new int[size]; + for(uint i : range(size)) { + C[i] = K[L[i]]; + K[L[i]]++; + } + + int M[256]; + memory::fill(M, 256, -1); + for(uint i : range(size)) { + if(M[F[i]] == -1) M[F[i]] = i; + } + + uint i = I; + for(uint j : reverse(range(size))) { + output[j] = L[i]; + i = C[i] + M[L[i]]; + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/cue.hpp b/roms/snes-test-roms/bass-untech/nall/decode/cue.hpp new file mode 100644 index 00000000..0c22d274 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/cue.hpp @@ -0,0 +1,228 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall::Decode { + +struct CUE { + struct Index { + auto sectorCount() const -> uint; + + int number; //01-99 + int lba = -1; + int end = -1; + }; + + struct Track { + auto sectorCount() const -> uint; + auto sectorSize() const -> uint; + + int number; //01-99 + string type; + vector indices; + maybe pregap; + maybe postgap; + }; + + struct File { + auto sectorCount() const -> uint; + auto scan(const string& pathname) -> bool; + + string name; + string type; + vector tracks; + }; + + auto load(const string& location) -> bool; + auto sectorCount() const -> uint; + + vector files; + +private: + auto loadFile(vector& lines, uint& offset) -> File; + auto loadTrack(vector& lines, uint& offset) -> Track; + auto loadIndex(vector& lines, uint& offset) -> Index; + auto toLBA(const string& msf) -> uint; +}; + +inline auto CUE::load(const string& location) -> bool { + auto lines = string::read(location).replace("\r", "").split("\n"); + + uint offset = 0; + while(offset < lines.size()) { + lines[offset].strip(); + if(lines[offset].ibeginsWith("FILE ")) { + auto file = loadFile(lines, offset); + if(!file.tracks) continue; + files.append(file); + continue; + } + offset++; + } + + if(!files) return false; + if(!files.first().tracks) return false; + if(!files.first().tracks.first().indices) return false; + + for(auto& file : files) { + maybe previous; + for(auto& track : file.tracks) { + for(auto& index : track.indices) { + if(previous) previous->end = index.lba - 1; + previous = index; + } + } + } + + for(auto& file : files) { + if(!file.scan(Location::path(location))) return false; + } + + return true; +} + +inline auto CUE::loadFile(vector& lines, uint& offset) -> File { + File file; + + lines[offset].itrimLeft("FILE ", 1L).strip(); + file.type = lines[offset].split(" ").last().strip().downcase(); + lines[offset].itrimRight(file.type, 1L).strip(); + file.name = lines[offset].trim("\"", "\"", 1L); + offset++; + + while(offset < lines.size()) { + lines[offset].strip(); + if(lines[offset].ibeginsWith("FILE ")) break; + if(lines[offset].ibeginsWith("TRACK ")) { + auto track = loadTrack(lines, offset); + if(!track.indices) continue; + file.tracks.append(track); + continue; + } + offset++; + } + + return file; +} + +inline auto CUE::loadTrack(vector& lines, uint& offset) -> Track { + Track track; + + lines[offset].itrimLeft("TRACK ", 1L).strip(); + track.type = lines[offset].split(" ").last().strip().downcase(); + lines[offset].itrimRight(track.type, 1L).strip(); + track.number = lines[offset].natural(); + offset++; + + while(offset < lines.size()) { + lines[offset].strip(); + if(lines[offset].ibeginsWith("FILE ")) break; + if(lines[offset].ibeginsWith("TRACK ")) break; + if(lines[offset].ibeginsWith("INDEX ")) { + auto index = loadIndex(lines, offset); + track.indices.append(index); + continue; + } + if(lines[offset].ibeginsWith("PREGAP ")) { + track.pregap = toLBA(lines[offset++].itrimLeft("PREGAP ", 1L)); + continue; + } + if(lines[offset].ibeginsWith("POSTGAP ")) { + track.postgap = toLBA(lines[offset++].itrimLeft("POSTGAP ", 1L)); + continue; + } + offset++; + } + + if(track.number > 99) return {}; + return track; +} + +inline auto CUE::loadIndex(vector& lines, uint& offset) -> Index { + Index index; + + lines[offset].itrimLeft("INDEX ", 1L); + string sector = lines[offset].split(" ").last().strip(); + lines[offset].itrimRight(sector, 1L).strip(); + index.number = lines[offset].natural(); + index.lba = toLBA(sector); + offset++; + + if(index.number > 99) return {}; + return index; +} + +inline auto CUE::toLBA(const string& msf) -> uint { + uint m = msf.split(":")(0).natural(); + uint s = msf.split(":")(1).natural(); + uint f = msf.split(":")(2).natural(); + return m * 60 * 75 + s * 75 + f; +} + +inline auto CUE::sectorCount() const -> uint { + uint count = 0; + for(auto& file : files) count += file.sectorCount(); + return count; +} + +inline auto CUE::File::scan(const string& pathname) -> bool { + string location = {Location::path(pathname), name}; + if(!file::exists(location)) return false; + + uint64_t size = 0; + + if(type == "binary") { + size = file::size(location); + } else if(type == "wave") { + Decode::WAV wav; + if(!wav.open(location)) return false; + if(wav.channels != 2) return false; + if(wav.frequency != 44100) return false; + if(wav.bitrate != 16) return false; + size = wav.size(); + } else { + return false; + } + + for(auto& track : tracks) { + for(auto& index : track.indices) { + if(index.end >= 0) { + size -= track.sectorSize() * index.sectorCount(); + } else { + index.end = index.lba + size / track.sectorSize() - 1; + } + } + } + + return true; +} + +inline auto CUE::File::sectorCount() const -> uint { + uint count = 0; + for(auto& track : tracks) count += track.sectorCount(); + return count; +} + +inline auto CUE::Track::sectorCount() const -> uint { + uint count = 0; + for(auto& index : indices) count += index.sectorCount(); + return count; +} + +inline auto CUE::Track::sectorSize() const -> uint { + if(type == "mode1/2048") return 2048; + if(type == "mode1/2352") return 2352; + if(type == "mode2/2352") return 2352; + if(type == "audio" ) return 2352; + return 0; +} + +inline auto CUE::Index::sectorCount() const -> uint { + if(end < 0) return 0; + return end - lba + 1; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/gzip.hpp b/roms/snes-test-roms/bass-untech/nall/decode/gzip.hpp new file mode 100644 index 00000000..20f754cd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/gzip.hpp @@ -0,0 +1,78 @@ +#pragma once + +#include +#include + +namespace nall::Decode { + +struct GZIP { + inline ~GZIP(); + + inline auto decompress(const string& filename) -> bool; + inline auto decompress(const uint8_t* data, uint size) -> bool; + + string filename; + uint8_t* data = nullptr; + uint size = 0; +}; + +GZIP::~GZIP() { + if(data) delete[] data; +} + +auto GZIP::decompress(const string& filename) -> bool { + if(auto memory = file::read(filename)) { + return decompress(memory.data(), memory.size()); + } + return false; +} + +auto GZIP::decompress(const uint8_t* data, uint size) -> bool { + if(size < 18) return false; + if(data[0] != 0x1f) return false; + if(data[1] != 0x8b) return false; + uint cm = data[2]; + uint flg = data[3]; + uint mtime = data[4]; + mtime |= data[5] << 8; + mtime |= data[6] << 16; + mtime |= data[7] << 24; + uint xfl = data[8]; + uint os = data[9]; + uint p = 10; + uint isize = data[size - 4]; + isize |= data[size - 3] << 8; + isize |= data[size - 2] << 16; + isize |= data[size - 1] << 24; + filename = ""; + + if(flg & 0x04) { //FEXTRA + uint xlen = data[p + 0]; + xlen |= data[p + 1] << 8; + p += 2 + xlen; + } + + if(flg & 0x08) { //FNAME + char buffer[PATH_MAX]; + for(uint n = 0; n < PATH_MAX; n++, p++) { + buffer[n] = data[p]; + if(data[p] == 0) break; + } + if(data[p++]) return false; + filename = buffer; + } + + if(flg & 0x10) { //FCOMMENT + while(data[p++]); + } + + if(flg & 0x02) { //FHCRC + p += 2; + } + + this->size = isize; + this->data = new uint8_t[this->size]; + return inflate(this->data, this->size, data + p, size - p - 8); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/html.hpp b/roms/snes-test-roms/bass-untech/nall/decode/html.hpp new file mode 100644 index 00000000..ccec3e8d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/html.hpp @@ -0,0 +1,40 @@ +#pragma once + +namespace nall::Decode { + +inline auto HTML(const string& input) -> string { + string output; + for(uint n = 0; n < input.size();) { + if(input[n] == '&') { + if(input(n + 1) == 'a' && input(n + 2) == 'm' && input(n + 3) == 'p' && input(n + 4) == ';') { + output.append('&'); + n += 5; + continue; + } + if(input(n + 1) == 'l' && input(n + 2) == 't' && input(n + 3) == ';') { + output.append('<'); + n += 4; + continue; + } + if(input(n + 1) == 'g' && input(n + 2) == 't' && input(n + 3) == ';') { + output.append('>'); + n += 4; + continue; + } + if(input(n + 1) == 'q' && input(n + 2) == 'u' && input(n + 3) == 'o' && input(n + 4) == 't' && input(n + 5) == ';') { + output.append('"'); + n += 6; + continue; + } + if(input(n + 1) == 'a' && input(n + 2) == 'p' && input(n + 3) == 'o' && input(n + 4) == 's' && input(n + 5) == ';') { + output.append('\''); + n += 6; + continue; + } + } + output.append(input[n++]); + } + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/huffman.hpp b/roms/snes-test-roms/bass-untech/nall/decode/huffman.hpp new file mode 100644 index 00000000..cb8c3929 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/huffman.hpp @@ -0,0 +1,36 @@ +#pragma once + +namespace nall::Decode { + +inline auto Huffman(array_view input) -> vector { + vector output; + + uint size = 0; + for(uint byte : range(8)) size |= *input++ << byte * 8; + output.reserve(size); + + uint byte = 0, bits = 0; + auto read = [&]() -> bool { + if(bits == 0) bits = 8, byte = *input++; + return byte >> --bits & 1; + }; + + uint nodes[256][2] = {}; + for(uint offset : range(256)) { + for(uint index : range(9)) nodes[offset][0] = nodes[offset][0] << 1 | read(); + for(uint index : range(9)) nodes[offset][1] = nodes[offset][1] << 1 | read(); + } + + uint node = 511; + while(output.size() < size) { + node = nodes[node - 256][read()]; + if(node < 256) { + output.append(node); + node = 511; + } + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/inflate.hpp b/roms/snes-test-roms/bass-untech/nall/decode/inflate.hpp new file mode 100644 index 00000000..0f659b70 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/inflate.hpp @@ -0,0 +1,349 @@ +#pragma once + +//a bad implementation of inflate from zlib/minizip +//todo: replace with Talarubi's version + +#include + +namespace nall::Decode { + +namespace puff { + inline auto puff( + unsigned char* dest, unsigned long* destlen, + unsigned char* source, unsigned long* sourcelen + ) -> int; +} + +inline auto inflate( + uint8_t* target, uint targetLength, + const uint8_t* source, uint sourceLength +) -> bool { + unsigned long tl = targetLength, sl = sourceLength; + int result = puff::puff((unsigned char*)target, &tl, (unsigned char*)source, &sl); + return result == 0; +} + +namespace puff { + +enum : uint { + MAXBITS = 15, + MAXLCODES = 286, + MAXDCODES = 30, + FIXLCODES = 288, + MAXCODES = MAXLCODES + MAXDCODES, +}; + +struct state { + unsigned char* out; + unsigned long outlen; + unsigned long outcnt; + + unsigned char* in; + unsigned long inlen; + unsigned long incnt; + int bitbuf; + int bitcnt; + + jmp_buf env; +}; + +struct huffman { + short* count; + short* symbol; +}; + +inline auto bits(state* s, int need) -> int { + long val; + + val = s->bitbuf; + while(s->bitcnt < need) { + if(s->incnt == s->inlen) longjmp(s->env, 1); + val |= (long)(s->in[s->incnt++]) << s->bitcnt; + s->bitcnt += 8; + } + + s->bitbuf = (int)(val >> need); + s->bitcnt -= need; + + return (int)(val & ((1L << need) - 1)); +} + +inline auto stored(state* s) -> int { + uint len; + + s->bitbuf = 0; + s->bitcnt = 0; + + if(s->incnt + 4 > s->inlen) return 2; + len = s->in[s->incnt++]; + len |= s->in[s->incnt++] << 8; + if(s->in[s->incnt++] != (~len & 0xff) || + s->in[s->incnt++] != ((~len >> 8) & 0xff) + ) return 2; + + if(s->incnt + len > s->inlen) return 2; + if(s->out != nullptr) { + if(s->outcnt + len > s->outlen) return 1; + while(len--) s->out[s->outcnt++] = s->in[s->incnt++]; + } else { + s->outcnt += len; + s->incnt += len; + } + + return 0; +} + +inline auto decode(state* s, huffman* h) -> int { + int len, code, first, count, index, bitbuf, left; + short* next; + + bitbuf = s->bitbuf; + left = s->bitcnt; + code = first = index = 0; + len = 1; + next = h->count + 1; + while(true) { + while(left--) { + code |= bitbuf & 1; + bitbuf >>= 1; + count = *next++; + if(code - count < first) { + s->bitbuf = bitbuf; + s->bitcnt = (s->bitcnt - len) & 7; + return h->symbol[index + (code - first)]; + } + index += count; + first += count; + first <<= 1; + code <<= 1; + len++; + } + left = (MAXBITS + 1) - len; + if(left == 0) break; + if(s->incnt == s->inlen) longjmp(s->env, 1); + bitbuf = s->in[s->incnt++]; + if(left > 8) left = 8; + } + + return -10; +} + +inline auto construct(huffman* h, short* length, int n) -> int { + int symbol, len, left; + short offs[MAXBITS + 1]; + + for(len = 0; len <= MAXBITS; len++) h->count[len] = 0; + for(symbol = 0; symbol < n; symbol++) h->count[length[symbol]]++; + if(h->count[0] == n) return 0; + + left = 1; + for(len = 1; len <= MAXBITS; len++) { + left <<= 1; + left -= h->count[len]; + if(left < 0) return left; + } + + offs[1] = 0; + for(len = 1; len < MAXBITS; len++) offs[len + 1] = offs[len] + h->count[len]; + + for(symbol = 0; symbol < n; symbol++) { + if(length[symbol] != 0) h->symbol[offs[length[symbol]]++] = symbol; + } + + return left; +} + +inline auto codes(state* s, huffman* lencode, huffman* distcode) -> int { + int symbol, len; + uint dist; + static const short lens[29] = { + 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 15, 17, 19, 23, 27, 31, + 35, 43, 51, 59, 67, 83, 99, 115, 131, 163, 195, 227, 258 + }; + static const short lext[29] = { + 0, 0, 0, 0, 0, 0, 0, 0, 1, 1, 1, 1, 2, 2, 2, 2, + 3, 3, 3, 3, 4, 4, 4, 4, 5, 5, 5, 5, 0 + }; + static const short dists[30] = { + 1, 2, 3, 4, 5, 7, 9, 13, 17, 25, 33, 49, 65, 97, 129, 193, + 257, 385, 513, 769, 1025, 1537, 2049, 3073, 4097, 6145, + 8193, 12289, 16385, 24577 + }; + static const short dext[30] = { + 0, 0, 0, 0, 1, 1, 2, 2, 3, 3, 4, 4, 5, 5, 6, 6, + 7, 7, 8, 8, 9, 9, 10, 10, 11, 11, + 12, 12, 13, 13 + }; + + do { + symbol = decode(s, lencode); + if(symbol < 0) return symbol; + if(symbol < 256) { + if(s->out != nullptr) { + if(s->outcnt == s->outlen) return 1; + s->out[s->outcnt] = symbol; + } + s->outcnt++; + } else if(symbol > 256) { + symbol -= 257; + if(symbol >= 29) return -10; + len = lens[symbol] + bits(s, lext[symbol]); + + symbol = decode(s, distcode); + if(symbol < 0) return symbol; + dist = dists[symbol] + bits(s, dext[symbol]); + #ifndef INFLATE_ALLOW_INVALID_DISTANCE_TOO_FAR + if(dist > s->outcnt) return -11; + #endif + + if(s->out != nullptr) { + if(s->outcnt + len > s->outlen) return 1; + while(len--) { + s->out[s->outcnt] = + #ifdef INFLATE_ALLOW_INVALID_DISTANCE_TOO_FAR + dist > s->outcnt ? 0 : + #endif + s->out[s->outcnt - dist]; + s->outcnt++; + } + } else { + s->outcnt += len; + } + } + } while(symbol != 256); + + return 0; +} + +inline auto fixed(state* s) -> int { + static int virgin = 1; + static short lencnt[MAXBITS + 1], lensym[FIXLCODES]; + static short distcnt[MAXBITS + 1], distsym[MAXDCODES]; + static huffman lencode, distcode; + + if(virgin) { + int symbol = 0; + short lengths[FIXLCODES]; + + lencode.count = lencnt; + lencode.symbol = lensym; + distcode.count = distcnt; + distcode.symbol = distsym; + + for(; symbol < 144; symbol++) lengths[symbol] = 8; + for(; symbol < 256; symbol++) lengths[symbol] = 9; + for(; symbol < 280; symbol++) lengths[symbol] = 7; + for(; symbol < FIXLCODES; symbol++) lengths[symbol] = 8; + construct(&lencode, lengths, FIXLCODES); + + for(symbol = 0; symbol < MAXDCODES; symbol++) lengths[symbol] = 5; + construct(&distcode, lengths, MAXDCODES); + + virgin = 0; + } + + return codes(s, &lencode, &distcode); +} + +inline auto dynamic(state* s) -> int { + int nlen, ndist, ncode, index, err; + short lengths[MAXCODES]; + short lencnt[MAXBITS + 1], lensym[MAXLCODES]; + short distcnt[MAXBITS + 1], distsym[MAXDCODES]; + huffman lencode, distcode; + static const short order[19] = { + 16, 17, 18, 0, 8, 7, 9, 6, 10, 5, 11, 4, 12, 3, 13, 2, 14, 1, 15 + }; + + lencode.count = lencnt; + lencode.symbol = lensym; + distcode.count = distcnt; + distcode.symbol = distsym; + + nlen = bits(s, 5) + 257; + ndist = bits(s, 5) + 1; + ncode = bits(s, 4) + 4; + if(nlen > MAXLCODES || ndist > MAXDCODES) return -3; + + for(index = 0; index < ncode; index++) lengths[order[index]] = bits(s, 3); + for(; index < 19; index++) lengths[order[index]] = 0; + + err = construct(&lencode, lengths, 19); + if(err != 0) return -4; + + index = 0; + while(index < nlen + ndist) { + int symbol, len; + + symbol = decode(s, &lencode); + if(symbol < 16) { + lengths[index++] = symbol; + } else { + len = 0; + if(symbol == 16) { + if(index == 0) return -5; + len = lengths[index - 1]; + symbol = 3 + bits(s, 2); + } else if(symbol == 17) { + symbol = 3 + bits(s, 3); + } else { + symbol = 11 + bits(s, 7); + } + if(index + symbol > nlen + ndist) return -6; + while(symbol--) lengths[index++] = len; + } + } + + if(lengths[256] == 0) return -9; + + err = construct(&lencode, lengths, nlen); + if(err < 0 || (err > 0 && nlen - lencode.count[0] != 1)) return -7; + + err = construct(&distcode, lengths + nlen, ndist); + if(err < 0 || (err > 0 && ndist - distcode.count[0] != 1)) return -8; + + return codes(s, &lencode, &distcode); +} + +inline auto puff( + unsigned char* dest, unsigned long* destlen, + unsigned char* source, unsigned long* sourcelen +) -> int { + state s; + int last, type, err; + + s.out = dest; + s.outlen = *destlen; + s.outcnt = 0; + + s.in = source; + s.inlen = *sourcelen; + s.incnt = 0; + s.bitbuf = 0; + s.bitcnt = 0; + + if(setjmp(s.env) != 0) { + err = 2; + } else { + do { + last = bits(&s, 1); + type = bits(&s, 2); + err = type == 0 ? stored(&s) + : type == 1 ? fixed(&s) + : type == 2 ? dynamic(&s) + : -1; + if(err != 0) break; + } while(!last); + } + + if(err <= 0) { + *destlen = s.outcnt; + *sourcelen = s.incnt; + } + + return err; +} + +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/lzsa.hpp b/roms/snes-test-roms/bass-untech/nall/decode/lzsa.hpp new file mode 100644 index 00000000..a0e9c9c4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/lzsa.hpp @@ -0,0 +1,72 @@ +#pragma once + +#include + +namespace nall::Decode { + +inline auto LZSA(array_view input) -> vector { + vector output; + uint index = 0; + + uint size = 0; + for(uint byte : range(8)) size |= *input++ << byte * 8; + output.resize(size); + + auto load = [&]() -> vector { + uint size = 0; + for(uint byte : range(8)) size |= *input++ << byte * 8; + vector buffer; + buffer.reserve(size); + while(size--) buffer.append(*input++); + return buffer; + }; + + auto flags = Decode::Huffman(load()); + auto literals = Decode::Huffman(load()); + auto lengths = Decode::Huffman(load()); + auto offsets = Decode::Huffman(load()); + + auto flagData = flags.data(); + uint byte = 0, bits = 0; + auto flagRead = [&]() -> bool { + if(bits == 0) bits = 8, byte = *flagData++; + return byte >> --bits & 1; + }; + + auto literalData = literals.data(); + auto literalRead = [&]() -> uint8_t { + return *literalData++; + }; + + auto lengthData = lengths.data(); + auto lengthRead = [&]() -> uint64_t { + uint byte = *lengthData++, bytes = 1; + while(!(byte & 1)) byte >>= 1, bytes++; + uint length = byte >> 1, shift = 8 - bytes; + while(--bytes) length |= *lengthData++ << shift, shift += 8; + return length; + }; + + auto offsetData = offsets.data(); + auto offsetRead = [&]() -> uint { + uint offset = 0; + offset |= *offsetData++ << 0; if(index < 1 << 8) return offset; + offset |= *offsetData++ << 8; if(index < 1 << 16) return offset; + offset |= *offsetData++ << 16; if(index < 1 << 24) return offset; + offset |= *offsetData++ << 24; return offset; + }; + + while(index < size) { + if(!flagRead()) { + output[index++] = literalRead(); + } else { + uint length = lengthRead() + 6; + uint offset = index - offsetRead(); + while(length--) output[index++] = output[offset++]; + } + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/mtf.hpp b/roms/snes-test-roms/bass-untech/nall/decode/mtf.hpp new file mode 100644 index 00000000..d70e1683 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/mtf.hpp @@ -0,0 +1,25 @@ +#pragma once + +//move to front + +namespace nall::Decode { + +inline auto MTF(array_view input) -> vector { + vector output; + output.resize(input.size()); + + uint8_t order[256]; + for(uint n : range(256)) order[n] = n; + + for(uint offset : range(input.size())) { + uint data = input[offset]; + uint value = order[data]; + output[offset] = value; + memory::move(&order[1], &order[0], data); + order[0] = value; + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/png.hpp b/roms/snes-test-roms/bass-untech/nall/decode/png.hpp new file mode 100644 index 00000000..775f84d4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/png.hpp @@ -0,0 +1,332 @@ +#pragma once + +#include +#include + +namespace nall::Decode { + +struct PNG { + PNG(); + ~PNG(); + + auto load(const string& filename) -> bool; + auto load(const uint8_t* sourceData, uint sourceSize) -> bool; + auto readbits(const uint8_t*& data) -> uint; + + struct Info { + uint width; + uint height; + uint bitDepth; + //colorType: + //0 = L (luma) + //2 = R,G,B + //3 = P (palette) + //4 = L,A + //6 = R,G,B,A + uint colorType; + uint compressionMethod; + uint filterType; + uint interlaceMethod; + + uint bytesPerPixel; + uint pitch; + + uint8_t palette[256][3]; + } info; + + uint8_t* data = nullptr; + uint size = 0; + + uint bitpos = 0; + +protected: + enum class FourCC : uint { + IHDR = 0x49484452, + PLTE = 0x504c5445, + IDAT = 0x49444154, + IEND = 0x49454e44, + }; + + auto interlace(uint pass, uint index) -> uint; + auto inflateSize() -> uint; + auto deinterlace(const uint8_t*& inputData, uint pass) -> bool; + auto filter(uint8_t* outputData, const uint8_t* inputData, uint width, uint height) -> bool; + auto read(const uint8_t* data, uint length) -> uint; +}; + +inline PNG::PNG() { +} + +inline PNG::~PNG() { + if(data) delete[] data; +} + +inline auto PNG::load(const string& filename) -> bool { + if(auto memory = file::read(filename)) { + return load(memory.data(), memory.size()); + } + return false; +} + +inline auto PNG::load(const uint8_t* sourceData, uint sourceSize) -> bool { + if(sourceSize < 8) return false; + if(read(sourceData + 0, 4) != 0x89504e47) return false; + if(read(sourceData + 4, 4) != 0x0d0a1a0a) return false; + + uint8_t* compressedData = nullptr; + uint compressedSize = 0; + + uint offset = 8; + while(offset < sourceSize) { + uint length = read(sourceData + offset + 0, 4); + uint fourCC = read(sourceData + offset + 4, 4); + uint checksum = read(sourceData + offset + 8 + length, 4); + + if(fourCC == (uint)FourCC::IHDR) { + info.width = read(sourceData + offset + 8, 4); + info.height = read(sourceData + offset + 12, 4); + info.bitDepth = read(sourceData + offset + 16, 1); + info.colorType = read(sourceData + offset + 17, 1); + info.compressionMethod = read(sourceData + offset + 18, 1); + info.filterType = read(sourceData + offset + 19, 1); + info.interlaceMethod = read(sourceData + offset + 20, 1); + + if(info.bitDepth == 0 || info.bitDepth > 16) return false; + if(info.bitDepth & (info.bitDepth - 1)) return false; //not a power of two + if(info.compressionMethod != 0) return false; + if(info.filterType != 0) return false; + if(info.interlaceMethod != 0 && info.interlaceMethod != 1) return false; + + switch(info.colorType) { + case 0: info.bytesPerPixel = info.bitDepth * 1; break; //L + case 2: info.bytesPerPixel = info.bitDepth * 3; break; //R,G,B + case 3: info.bytesPerPixel = info.bitDepth * 1; break; //P + case 4: info.bytesPerPixel = info.bitDepth * 2; break; //L,A + case 6: info.bytesPerPixel = info.bitDepth * 4; break; //R,G,B,A + default: return false; + } + + if(info.colorType == 2 || info.colorType == 4 || info.colorType == 6) { + if(info.bitDepth != 8 && info.bitDepth != 16) return false; + } + if(info.colorType == 3 && info.bitDepth == 16) return false; + + info.bytesPerPixel = (info.bytesPerPixel + 7) / 8; + info.pitch = (int)info.width * info.bytesPerPixel; + } + + if(fourCC == (uint)FourCC::PLTE) { + if(length % 3) return false; + for(uint n = 0, p = offset + 8; n < length / 3; n++) { + info.palette[n][0] = sourceData[p++]; + info.palette[n][1] = sourceData[p++]; + info.palette[n][2] = sourceData[p++]; + } + } + + if(fourCC == (uint)FourCC::IDAT) { + compressedData = (uint8_t*)realloc(compressedData, compressedSize + length); + memcpy(compressedData + compressedSize, sourceData + offset + 8, length); + compressedSize += length; + } + + if(fourCC == (uint)FourCC::IEND) { + break; + } + + offset += 4 + 4 + length + 4; + } + + uint interlacedSize = inflateSize(); + auto interlacedData = new uint8_t[interlacedSize]; + + bool result = inflate(interlacedData, interlacedSize, compressedData + 2, compressedSize - 6); + free(compressedData); + + if(result == false) { + delete[] interlacedData; + return false; + } + + size = info.width * info.height * info.bytesPerPixel; + data = new uint8_t[size]; + + if(info.interlaceMethod == 0) { + if(filter(data, interlacedData, info.width, info.height) == false) { + delete[] interlacedData; + delete[] data; + data = nullptr; + return false; + } + } else { + const uint8_t* passData = interlacedData; + for(uint pass = 0; pass < 7; pass++) { + if(deinterlace(passData, pass) == false) { + delete[] interlacedData; + delete[] data; + data = nullptr; + return false; + } + } + } + + delete[] interlacedData; + return true; +} + +inline auto PNG::interlace(uint pass, uint index) -> uint { + static const uint data[7][4] = { + //x-distance, y-distance, x-origin, y-origin + {8, 8, 0, 0}, + {8, 8, 4, 0}, + {4, 8, 0, 4}, + {4, 4, 2, 0}, + {2, 4, 0, 2}, + {2, 2, 1, 0}, + {1, 2, 0, 1}, + }; + return data[pass][index]; +} + +inline auto PNG::inflateSize() -> uint { + if(info.interlaceMethod == 0) { + return info.width * info.height * info.bytesPerPixel + info.height; + } + + uint size = 0; + for(uint pass = 0; pass < 7; pass++) { + uint xd = interlace(pass, 0), yd = interlace(pass, 1); + uint xo = interlace(pass, 2), yo = interlace(pass, 3); + uint width = (info.width + (xd - xo - 1)) / xd; + uint height = (info.height + (yd - yo - 1)) / yd; + if(width == 0 || height == 0) continue; + size += width * height * info.bytesPerPixel + height; + } + return size; +} + +inline auto PNG::deinterlace(const uint8_t*& inputData, uint pass) -> bool { + uint xd = interlace(pass, 0), yd = interlace(pass, 1); + uint xo = interlace(pass, 2), yo = interlace(pass, 3); + uint width = (info.width + (xd - xo - 1)) / xd; + uint height = (info.height + (yd - yo - 1)) / yd; + if(width == 0 || height == 0) return true; + + uint outputSize = width * height * info.bytesPerPixel; + auto outputData = new uint8_t[outputSize]; + bool result = filter(outputData, inputData, width, height); + + const uint8_t* rd = outputData; + for(uint y = yo; y < info.height; y += yd) { + uint8_t* wr = data + y * info.pitch; + for(uint x = xo; x < info.width; x += xd) { + for(uint b = 0; b < info.bytesPerPixel; b++) { + wr[x * info.bytesPerPixel + b] = *rd++; + } + } + } + + inputData += outputSize + height; + delete[] outputData; + return result; +} + +inline auto PNG::filter(uint8_t* outputData, const uint8_t* inputData, uint width, uint height) -> bool { + uint8_t* wr = outputData; + const uint8_t* rd = inputData; + int bpp = info.bytesPerPixel, pitch = width * bpp; + for(int y = 0; y < height; y++) { + uint8_t filter = *rd++; + + switch(filter) { + case 0x00: //None + for(int x = 0; x < pitch; x++) { + wr[x] = rd[x]; + } + break; + + case 0x01: //Subtract + for(int x = 0; x < pitch; x++) { + wr[x] = rd[x] + (x - bpp < 0 ? 0 : wr[x - bpp]); + } + break; + + case 0x02: //Above + for(int x = 0; x < pitch; x++) { + wr[x] = rd[x] + (y - 1 < 0 ? 0 : wr[x - pitch]); + } + break; + + case 0x03: //Average + for(int x = 0; x < pitch; x++) { + short a = x - bpp < 0 ? 0 : wr[x - bpp]; + short b = y - 1 < 0 ? 0 : wr[x - pitch]; + + wr[x] = rd[x] + (uint8_t)((a + b) / 2); + } + break; + + case 0x04: //Paeth + for(int x = 0; x < pitch; x++) { + short a = x - bpp < 0 ? 0 : wr[x - bpp]; + short b = y - 1 < 0 ? 0 : wr[x - pitch]; + short c = x - bpp < 0 || y - 1 < 0 ? 0 : wr[x - pitch - bpp]; + + short p = a + b - c; + short pa = p > a ? p - a : a - p; + short pb = p > b ? p - b : b - p; + short pc = p > c ? p - c : c - p; + + auto paeth = (uint8_t)((pa <= pb && pa <= pc) ? a : (pb <= pc) ? b : c); + + wr[x] = rd[x] + paeth; + } + break; + + default: //Invalid + return false; + } + + rd += pitch; + wr += pitch; + } + + return true; +} + +inline auto PNG::read(const uint8_t* data, uint length) -> uint { + uint result = 0; + while(length--) result = (result << 8) | (*data++); + return result; +} + +inline auto PNG::readbits(const uint8_t*& data) -> uint { + uint result = 0; + switch(info.bitDepth) { + case 1: + result = (*data >> bitpos) & 1; + bitpos++; + if(bitpos == 8) { data++; bitpos = 0; } + break; + case 2: + result = (*data >> bitpos) & 3; + bitpos += 2; + if(bitpos == 8) { data++; bitpos = 0; } + break; + case 4: + result = (*data >> bitpos) & 15; + bitpos += 4; + if(bitpos == 8) { data++; bitpos = 0; } + break; + case 8: + result = *data++; + break; + case 16: + result = (data[0] << 8) | (data[1] << 0); + data += 2; + break; + } + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/rle.hpp b/roms/snes-test-roms/bass-untech/nall/decode/rle.hpp new file mode 100644 index 00000000..4a6c67ca --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/rle.hpp @@ -0,0 +1,44 @@ +#pragma once + +namespace nall::Decode { + +template //S = word size; M = match length +inline auto RLE(array_view input) -> vector { + vector output; + + auto load = [&]() -> uint8_t { + return input ? *input++ : 0; + }; + + uint base = 0; + uint64_t size = 0; + for(uint byte : range(8)) size |= load() << byte * 8; + output.resize(size); + + auto read = [&]() -> uint64_t { + uint64_t value = 0; + for(uint byte : range(S)) value |= load() << byte * 8; + return value; + }; + + auto write = [&](uint64_t value) -> void { + if(base >= size) return; + for(uint byte : range(S)) output[base++] = value >> byte * 8; + }; + + while(base < size) { + auto byte = load(); + if(byte < 128) { + byte++; + while(byte--) write(read()); + } else { + auto value = read(); + byte = (byte & 127) + M; + while(byte--) write(value); + } + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/url.hpp b/roms/snes-test-roms/bass-untech/nall/decode/url.hpp new file mode 100644 index 00000000..56526c92 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/url.hpp @@ -0,0 +1,39 @@ +#pragma once + +namespace nall::Decode { + +//returns empty string on malformed content +inline auto URL(string_view input) -> string { + string output; + for(uint n = 0; n < input.size();) { + char c = input[n]; + + //unreserved characters + if(c >= 'A' && c <= 'Z') { output.append(c); n++; continue; } + if(c >= 'a' && c <= 'z') { output.append(c); n++; continue; } + if(c >= '0' && c <= '9') { output.append(c); n++; continue; } + if(c == '-' || c == '_' || c == '.' || c == '~') { output.append(c); n++; continue; } + + //special characters + if(c == '+') { output.append(' '); n++; continue; } + + //reserved characters + if(c != '%' || n + 2 >= input.size()) return ""; + char hi = input[n + 1]; + char lo = input[n + 2]; + if(hi >= '0' && hi <= '9') hi -= '0'; + else if(hi >= 'A' && hi <= 'F') hi -= 'A' - 10; + else if(hi >= 'a' && hi <= 'f') hi -= 'a' - 10; + else return ""; + if(lo >= '0' && lo <= '9') lo -= '0'; + else if(lo >= 'A' && lo <= 'F') lo -= 'A' - 10; + else if(lo >= 'a' && lo <= 'f') lo -= 'a' - 10; + else return ""; + char byte = hi * 16 + lo; + output.append(byte); + n += 3; + } + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/wav.hpp b/roms/snes-test-roms/bass-untech/nall/decode/wav.hpp new file mode 100644 index 00000000..7805e07d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/wav.hpp @@ -0,0 +1,93 @@ +#pragma once + +#include +#include + +namespace nall::Decode { + +struct WAV { + auto open(const string& filename) -> bool; + auto close() -> void; + auto read() -> uint64_t; + auto end() const -> bool; + auto size() const -> uint64_t; + + file_buffer fp; + uint channels = 0; + uint frequency = 0; + uint bitrate = 0; + uint samples = 0; + uint headerSize = 0; +}; + +inline auto WAV::open(const string& filename) -> bool { + close(); + + if(fp = file::open(filename, file::mode::read)) { + if(fp.read() != 'R') return false; + if(fp.read() != 'I') return false; + if(fp.read() != 'F') return false; + if(fp.read() != 'F') return false; + + uint32_t chunkSize = fp.readl(4); + + if(fp.read() != 'W') return false; + if(fp.read() != 'A') return false; + if(fp.read() != 'V') return false; + if(fp.read() != 'E') return false; + + if(fp.read() != 'f') return false; + if(fp.read() != 'm') return false; + if(fp.read() != 't') return false; + if(fp.read() != ' ') return false; + + uint32_t subchunkSize = fp.readl(4); + if(subchunkSize != 16) return false; + + uint16_t format = fp.readl(2); + if(format != 1) return false; //only PCM is supported + + channels = fp.readl(2); + frequency = fp.readl(4); + uint32_t byteRate = fp.readl(4); + uint16_t blockAlign = fp.readl(2); + bitrate = fp.readl(2); + + //todo: handle LIST chunk better than this + while(!fp.end() && fp.read() != 'd'); + while(!fp.end() && fp.read() != 'a'); + while(!fp.end() && fp.read() != 't'); + while(!fp.end() && fp.read() != 'a'); + if(fp.end()) return false; + + uint32_t dataSize = fp.readl(4); + uint32_t remaining = fp.size() - fp.offset(); + samples = remaining / (bitrate / 8) / channels; + headerSize = fp.offset(); + return true; + } + + return false; +} + +inline auto WAV::close() -> void { + fp.close(); + channels = 0; + frequency = 0; + bitrate = 0; + samples = 0; +} + +inline auto WAV::read() -> uint64_t { + return fp.readl((bitrate / 8) * channels); +} + +inline auto WAV::end() const -> bool { + return fp.end(); +} + +inline auto WAV::size() const -> uint64_t { + return samples * (bitrate / 8) * channels; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/decode/zip.hpp b/roms/snes-test-roms/bass-untech/nall/decode/zip.hpp new file mode 100644 index 00000000..316009dd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/decode/zip.hpp @@ -0,0 +1,136 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall::Decode { + +struct ZIP { + struct File { + string name; + const uint8_t* data; + uint size; + uint csize; + uint cmode; //0 = uncompressed, 8 = deflate + uint crc32; + time_t timestamp; + }; + + ~ZIP() { + close(); + } + + auto open(const string& filename) -> bool { + close(); + if(fm.open(filename, file::mode::read) == false) return false; + if(open(fm.data(), fm.size()) == false) { + fm.close(); + return false; + } + return true; + } + + auto open(const uint8_t* data, uint size) -> bool { + if(size < 22) return false; + + filedata = data; + filesize = size; + + file.reset(); + + const uint8_t* footer = data + size - 22; + while(true) { + if(footer <= data + 22) return false; + if(read(footer, 4) == 0x06054b50) { + uint commentlength = read(footer + 20, 2); + if(footer + 22 + commentlength == data + size) break; + } + footer--; + } + const uint8_t* directory = data + read(footer + 16, 4); + + while(true) { + uint signature = read(directory + 0, 4); + if(signature != 0x02014b50) break; + + File file; + file.cmode = read(directory + 10, 2); + file.crc32 = read(directory + 16, 4); + file.csize = read(directory + 20, 4); + file.size = read(directory + 24, 4); + + uint16_t dosTime = read(directory + 12, 2); + uint16_t dosDate = read(directory + 14, 2); + tm info = {}; + info.tm_sec = (dosTime >> 0 & 31) << 1; + info.tm_min = (dosTime >> 5 & 63); + info.tm_hour = (dosTime >> 11 & 31); + info.tm_mday = (dosDate >> 0 & 31); + info.tm_mon = (dosDate >> 5 & 15) - 1; + info.tm_year = (dosDate >> 9 & 127) + 80; + info.tm_isdst = -1; + file.timestamp = mktime(&info); + + uint namelength = read(directory + 28, 2); + uint extralength = read(directory + 30, 2); + uint commentlength = read(directory + 32, 2); + + char* filename = new char[namelength + 1]; + memcpy(filename, directory + 46, namelength); + filename[namelength] = 0; + file.name = filename; + delete[] filename; + + uint offset = read(directory + 42, 4); + uint offsetNL = read(data + offset + 26, 2); + uint offsetEL = read(data + offset + 28, 2); + file.data = data + offset + 30 + offsetNL + offsetEL; + + directory += 46 + namelength + extralength + commentlength; + + this->file.append(file); + } + + return true; + } + + auto extract(File& file) -> vector { + vector buffer; + + if(file.cmode == 0) { + buffer.resize(file.size); + memcpy(buffer.data(), file.data, file.size); + } + + if(file.cmode == 8) { + buffer.resize(file.size); + if(inflate(buffer.data(), buffer.size(), file.data, file.csize) == false) { + buffer.reset(); + } + } + + return buffer; + } + + auto close() -> void { + if(fm) fm.close(); + } + +protected: + file_map fm; + const uint8_t* filedata; + uint filesize; + + auto read(const uint8_t* data, uint size) -> uint { + uint result = 0, shift = 0; + while(size--) { result |= *data++ << shift; shift += 8; } + return result; + } + +public: + vector file; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/directory.hpp b/roms/snes-test-roms/bass-untech/nall/directory.hpp new file mode 100644 index 00000000..7dc6b8ff --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/directory.hpp @@ -0,0 +1,353 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +#if defined(PLATFORM_WINDOWS) + #include +#else + #include + #include + #include +#endif + +namespace nall { + +struct directory : inode { + directory() = delete; + + static auto copy(const string& source, const string& target) -> bool; //recursive + static auto create(const string& pathname, uint permissions = 0755) -> bool; //recursive + static auto remove(const string& pathname) -> bool; //recursive + static auto exists(const string& pathname) -> bool; + + static auto folders(const string& pathname, const string& pattern = "*") -> vector { + auto folders = directory::ufolders(pathname, pattern); + folders.sort(); + for(auto& folder : folders) folder.append("/"); //must append after sorting + return folders; + } + + static auto files(const string& pathname, const string& pattern = "*") -> vector { + auto files = directory::ufiles(pathname, pattern); + files.sort(); + return files; + } + + static auto contents(const string& pathname, const string& pattern = "*") -> vector { + auto folders = directory::ufolders(pathname); //pattern search of contents should only filter files + folders.sort(); + for(auto& folder : folders) folder.append("/"); //must append after sorting + auto files = directory::ufiles(pathname, pattern); + files.sort(); + for(auto& file : files) folders.append(file); + return folders; + } + + static auto ifolders(const string& pathname, const string& pattern = "*") -> vector { + auto folders = ufolders(pathname, pattern); + folders.isort(); + for(auto& folder : folders) folder.append("/"); //must append after sorting + return folders; + } + + static auto ifiles(const string& pathname, const string& pattern = "*") -> vector { + auto files = ufiles(pathname, pattern); + files.isort(); + return files; + } + + static auto icontents(const string& pathname, const string& pattern = "*") -> vector { + auto folders = directory::ufolders(pathname); //pattern search of contents should only filter files + folders.isort(); + for(auto& folder : folders) folder.append("/"); //must append after sorting + auto files = directory::ufiles(pathname, pattern); + files.isort(); + for(auto& file : files) folders.append(file); + return folders; + } + + static auto rcontents(const string& pathname, const string& pattern = "*") -> vector { + vector contents; + function + recurse = [&](const string& basename, const string& pathname, const string& pattern) { + for(auto& folder : directory::ufolders(pathname)) { + contents.append(string{pathname, folder, "/"}.trimLeft(basename, 1L)); + recurse(basename, {pathname, folder, "/"}, pattern); + } + for(auto& file : directory::ufiles(pathname, pattern)) { + contents.append(string{pathname, file}.trimLeft(basename, 1L)); + } + }; + for(auto& folder : directory::ufolders(pathname)) { + contents.append({folder, "/"}); + recurse(pathname, {pathname, folder, "/"}, pattern); + } + for(auto& file : directory::ufiles(pathname, pattern)) { + contents.append(file); + } + contents.sort(); + return contents; + } + + static auto ircontents(const string& pathname, const string& pattern = "*") -> vector { + vector contents; + function + recurse = [&](const string& basename, const string& pathname, const string& pattern) { + for(auto& folder : directory::ufolders(pathname)) { + contents.append(string{pathname, folder, "/"}.trimLeft(basename, 1L)); + recurse(basename, {pathname, folder, "/"}, pattern); + } + for(auto& file : directory::ufiles(pathname, pattern)) { + contents.append(string{pathname, file}.trimLeft(basename, 1L)); + } + }; + for(auto& folder : directory::ufolders(pathname)) { + contents.append({folder, "/"}); + recurse(pathname, {pathname, folder, "/"}, pattern); + } + for(auto& file : directory::ufiles(pathname, pattern)) { + contents.append(file); + } + contents.isort(); + return contents; + } + + static auto rfolders(const string& pathname, const string& pattern = "*") -> vector { + vector folders; + for(auto& folder : rcontents(pathname, pattern)) { + if(directory::exists({pathname, folder})) folders.append(folder); + } + return folders; + } + + static auto irfolders(const string& pathname, const string& pattern = "*") -> vector { + vector folders; + for(auto& folder : ircontents(pathname, pattern)) { + if(directory::exists({pathname, folder})) folders.append(folder); + } + return folders; + } + + static auto rfiles(const string& pathname, const string& pattern = "*") -> vector { + vector files; + for(auto& file : rcontents(pathname, pattern)) { + if(file::exists({pathname, file})) files.append(file); + } + return files; + } + + static auto irfiles(const string& pathname, const string& pattern = "*") -> vector { + vector files; + for(auto& file : ircontents(pathname, pattern)) { + if(file::exists({pathname, file})) files.append(file); + } + return files; + } + +private: + //internal functions; these return unsorted lists + static auto ufolders(const string& pathname, const string& pattern = "*") -> vector; + static auto ufiles(const string& pathname, const string& pattern = "*") -> vector; +}; + +inline auto directory::copy(const string& source, const string& target) -> bool { + bool result = true; + if(!directory::exists(source)) return result = false; + if(!directory::create(target)) return result = false; + for(auto& name : directory::folders(source)) { + if(!directory::copy({source, name}, {target, name})) result = false; + } + for(auto& name : directory::files(source)) { + if(!file::copy({source, name}, {target, name})) result = false; + } + return result; +} + +#if defined(PLATFORM_WINDOWS) + inline auto directory::create(const string& pathname, uint permissions) -> bool { + string path; + auto list = string{pathname}.transform("\\", "/").trimRight("/").split("/"); + bool result = true; + for(auto& part : list) { + path.append(part, "/"); + if(directory::exists(path)) continue; + result &= (_wmkdir(utf16_t(path)) == 0); + } + return result; + } + + inline auto directory::remove(const string& pathname) -> bool { + if(!pathname || pathname == "/" || pathname.match("?:") || pathname.match("?:/")) return false; //safeguard + auto list = directory::contents(pathname); + for(auto& name : list) { + if(name.endsWith("/")) directory::remove({pathname, name}); + else file::remove({pathname, name}); + } + return _wrmdir(utf16_t(pathname)) == 0; + } + + inline auto directory::exists(const string& pathname) -> bool { + if(!pathname) return false; + string name = pathname; + name.trim("\"", "\""); + DWORD result = GetFileAttributes(utf16_t(name)); + if(result == INVALID_FILE_ATTRIBUTES) return false; + return (result & FILE_ATTRIBUTE_DIRECTORY); + } + + inline auto directory::ufolders(const string& pathname, const string& pattern) -> vector { + if(!pathname) { + //special root pseudo-folder (return list of drives) + wchar_t drives[PATH_MAX] = {0}; + GetLogicalDriveStrings(PATH_MAX, drives); + wchar_t* p = drives; + while(*p || *(p + 1)) { + if(!*p) *p = ';'; + *p++; + } + return string{(const char*)utf8_t(drives)}.replace("\\", "/").split(";"); + } + + vector list; + string path = pathname; + path.transform("/", "\\"); + if(!path.endsWith("\\")) path.append("\\"); + path.append("*"); + HANDLE handle; + WIN32_FIND_DATA data; + handle = FindFirstFile(utf16_t(path), &data); + if(handle != INVALID_HANDLE_VALUE) { + if(wcscmp(data.cFileName, L".") && wcscmp(data.cFileName, L"..")) { + if(data.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) { + string name = (const char*)utf8_t(data.cFileName); + if(name.match(pattern)) list.append(name); + } + } + while(FindNextFile(handle, &data) != false) { + if(wcscmp(data.cFileName, L".") && wcscmp(data.cFileName, L"..")) { + if(data.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) { + string name = (const char*)utf8_t(data.cFileName); + if(name.match(pattern)) list.append(name); + } + } + } + FindClose(handle); + } + return list; + } + + inline auto directory::ufiles(const string& pathname, const string& pattern) -> vector { + if(!pathname) return {}; + + vector list; + string path = pathname; + path.transform("/", "\\"); + if(!path.endsWith("\\")) path.append("\\"); + path.append("*"); + HANDLE handle; + WIN32_FIND_DATA data; + handle = FindFirstFile(utf16_t(path), &data); + if(handle != INVALID_HANDLE_VALUE) { + if((data.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0) { + string name = (const char*)utf8_t(data.cFileName); + if(name.match(pattern)) list.append(name); + } + while(FindNextFile(handle, &data) != false) { + if((data.dwFileAttributes & FILE_ATTRIBUTE_DIRECTORY) == 0) { + string name = (const char*)utf8_t(data.cFileName); + if(name.match(pattern)) list.append(name); + } + } + FindClose(handle); + } + return list; + } +#else + inline auto directoryIsFolder(DIR* dp, struct dirent* ep) -> bool { + if(ep->d_type == DT_DIR) return true; + if(ep->d_type == DT_LNK || ep->d_type == DT_UNKNOWN) { + //symbolic links must be resolved to determine type + struct stat sp = {0}; + fstatat(dirfd(dp), ep->d_name, &sp, 0); + return S_ISDIR(sp.st_mode); + } + return false; + } + + inline auto directory::create(const string& pathname, uint permissions) -> bool { + string path; + auto list = string{pathname}.trimRight("/").split("/"); + bool result = true; + for(auto& part : list) { + path.append(part, "/"); + if(directory::exists(path)) continue; + result &= (mkdir(path, permissions) == 0); + } + return result; + } + + inline auto directory::remove(const string& pathname) -> bool { + if(!pathname || pathname == "/") return false; //safeguard + auto list = directory::contents(pathname); + for(auto& name : list) { + if(name.endsWith("/")) directory::remove({pathname, name}); + else file::remove({pathname, name}); + } + return rmdir(pathname) == 0; + } + + inline auto directory::exists(const string& pathname) -> bool { + if(!pathname) return false; + struct stat data; + if(stat(pathname, &data) != 0) return false; + return S_ISDIR(data.st_mode); + } + + inline auto directory::ufolders(const string& pathname, const string& pattern) -> vector { + if(!pathname) return vector{"/"}; + + vector list; + DIR* dp; + struct dirent* ep; + dp = opendir(pathname); + if(dp) { + while(ep = readdir(dp)) { + if(!strcmp(ep->d_name, ".")) continue; + if(!strcmp(ep->d_name, "..")) continue; + if(!directoryIsFolder(dp, ep)) continue; + string name{ep->d_name}; + if(name.match(pattern)) list.append(std::move(name)); + } + closedir(dp); + } + return list; + } + + inline auto directory::ufiles(const string& pathname, const string& pattern) -> vector { + if(!pathname) return {}; + + vector list; + DIR* dp; + struct dirent* ep; + dp = opendir(pathname); + if(dp) { + while(ep = readdir(dp)) { + if(!strcmp(ep->d_name, ".")) continue; + if(!strcmp(ep->d_name, "..")) continue; + if(directoryIsFolder(dp, ep)) continue; + string name{ep->d_name}; + if(name.match(pattern)) list.append(std::move(name)); + } + closedir(dp); + } + return list; + } +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dl.hpp b/roms/snes-test-roms/bass-untech/nall/dl.hpp new file mode 100644 index 00000000..8116d349 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dl.hpp @@ -0,0 +1,126 @@ +#pragma once + +//dynamic linking support + +#include +#include +#include +#include +#include + +#if defined(PLATFORM_WINDOWS) + #include +#else + #include +#endif + +namespace nall { + +struct library { + library() = default; + ~library() { close(); } + + library& operator=(const library&) = delete; + library(const library&) = delete; + + explicit operator bool() const { return open(); } + auto open() const -> bool { return handle; } + auto open(const string&, const string& = "") -> bool; + auto openAbsolute(const string&) -> bool; + auto sym(const string&) -> void*; + auto close() -> void; + +private: + uintptr handle = 0; +}; + +#if defined(PLATFORM_LINUX) || defined(PLATFORM_BSD) +inline auto library::open(const string& name, const string& path) -> bool { + if(handle) close(); + if(path) handle = (uintptr)dlopen(string(path, "lib", name, ".so"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string(Path::user(), ".local/lib/lib", name, ".so"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string("/usr/local/lib/lib", name, ".so"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string("lib", name, ".so"), RTLD_LAZY); + return handle; +} + +inline auto library::openAbsolute(const string& name) -> bool { + if(handle) close(); + handle = (uintptr)dlopen(name, RTLD_LAZY); + return handle; +} + +inline auto library::sym(const string& name) -> void* { + if(!handle) return nullptr; + return dlsym((void*)handle, name); +} + +inline auto library::close() -> void { + if(!handle) return; + dlclose((void*)handle); + handle = 0; +} +#elif defined(PLATFORM_MACOS) +inline auto library::open(const string& name, const string& path) -> bool { + if(handle) close(); + if(path) handle = (uintptr)dlopen(string(path, "lib", name, ".dylib"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string(Path::user(), ".local/lib/lib", name, ".dylib"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string("/usr/local/lib/lib", name, ".dylib"), RTLD_LAZY); + if(!handle) handle = (uintptr)dlopen(string("lib", name, ".dylib"), RTLD_LAZY); + return handle; +} + +inline auto library::openAbsolute(const string& name) -> bool { + if(handle) close(); + handle = (uintptr)dlopen(name, RTLD_LAZY); + return handle; +} + +inline auto library::sym(const string& name) -> void* { + if(!handle) return nullptr; + return dlsym((void*)handle, name); +} + +inline auto library::close() -> void { + if(!handle) return; + dlclose((void*)handle); + handle = 0; +} +#elif defined(PLATFORM_WINDOWS) +inline auto library::open(const string& name, const string& path) -> bool { + if(handle) close(); + if(path) { + string filepath = {path, name, ".dll"}; + handle = (uintptr)LoadLibraryW(utf16_t(filepath)); + } + if(!handle) { + string filepath = {name, ".dll"}; + handle = (uintptr)LoadLibraryW(utf16_t(filepath)); + } + return handle; +} + +inline auto library::openAbsolute(const string& name) -> bool { + if(handle) close(); + handle = (uintptr)LoadLibraryW(utf16_t(name)); + return handle; +} + +inline auto library::sym(const string& name) -> void* { + if(!handle) return nullptr; + return (void*)GetProcAddress((HMODULE)handle, name); +} + +inline auto library::close() -> void { + if(!handle) return; + FreeLibrary((HMODULE)handle); + handle = 0; +} +#else +inline auto library::open(const string&, const string&) -> bool { return false; } +inline auto library::openAbsolute(const string&) -> bool { return false; } +inline auto library::sym(const string&) -> void* { return nullptr; } +inline auto library::close() -> void {} +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dsp/dsp.hpp b/roms/snes-test-roms/bass-untech/nall/dsp/dsp.hpp new file mode 100644 index 00000000..f8bf82e2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dsp/dsp.hpp @@ -0,0 +1,5 @@ +#pragma once + +namespace nall::DSP { + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dsp/iir/biquad.hpp b/roms/snes-test-roms/bass-untech/nall/dsp/iir/biquad.hpp new file mode 100644 index 00000000..c36273b2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dsp/iir/biquad.hpp @@ -0,0 +1,164 @@ +#pragma once + +#include + +//transposed direct form II biquadratic second-order IIR filter + +namespace nall::DSP::IIR { + +struct Biquad { + enum class Type : uint { + LowPass, + HighPass, + BandPass, + Notch, + Peak, + LowShelf, + HighShelf, + }; + + auto reset(Type type, double cutoffFrequency, double samplingFrequency, double quality, double gain = 0.0) -> void; + auto process(double in) -> double; //normalized sample (-1.0 to +1.0) + + static auto shelf(double gain, double slope) -> double; + static auto butterworth(uint order, uint phase) -> double; + +private: + Type type; + double cutoffFrequency; + double samplingFrequency; + double quality; //frequency response quality + double gain; //peak gain + double a0, a1, a2, b1, b2; //coefficients + double z1, z2; //second-order IIR +}; + +inline auto Biquad::reset(Type type, double cutoffFrequency, double samplingFrequency, double quality, double gain) -> void { + this->type = type; + this->cutoffFrequency = cutoffFrequency; + this->samplingFrequency = samplingFrequency; + this->quality = quality; + this->gain = gain; + + z1 = 0.0; + z2 = 0.0; + + double v = pow(10, fabs(gain) / 20.0); + double k = tan(Math::Pi * cutoffFrequency / samplingFrequency); + double q = quality; + double n = 0.0; + + switch(type) { + + case Type::LowPass: + n = 1 / (1 + k / q + k * k); + a0 = k * k * n; + a1 = 2 * a0; + a2 = a0; + b1 = 2 * (k * k - 1) * n; + b2 = (1 - k / q + k * k) * n; + break; + + case Type::HighPass: + n = 1 / (1 + k / q + k * k); + a0 = 1 * n; + a1 = -2 * a0; + a2 = a0; + b1 = 2 * (k * k - 1) * n; + b2 = (1 - k / q + k * k) * n; + break; + + case Type::BandPass: + n = 1 / (1 + k / q + k * k); + a0 = k / q * n; + a1 = 0; + a2 = -a0; + b1 = 2 * (k * k - 1) * n; + b2 = (1 - k / q + k * k) * n; + break; + + case Type::Notch: + n = 1 / (1 + k / q + k * k); + a0 = (1 + k * k) * n; + a1 = 2 * (k * k - 1) * n; + a2 = a0; + b1 = a1; + b2 = (1 - k / q + k * k) * n; + break; + + case Type::Peak: + if(gain >= 0) { + n = 1 / (1 + 1 / q * k + k * k); + a0 = (1 + v / q * k + k * k) * n; + a1 = 2 * (k * k - 1) * n; + a2 = (1 - v / q * k + k * k) * n; + b1 = a1; + b2 = (1 - 1 / q * k + k * k) * n; + } else { + n = 1 / (1 + v / q * k + k * k); + a0 = (1 + 1 / q * k + k * k) * n; + a1 = 2 * (k * k - 1) * n; + a2 = (1 - 1 / q * k + k * k) * n; + b1 = a1; + b2 = (1 - v / q * k + k * k) * n; + } + break; + + case Type::LowShelf: + if(gain >= 0) { + n = 1 / (1 + k / q + k * k); + a0 = (1 + sqrt(v) / q * k + v * k * k) * n; + a1 = 2 * (v * k * k - 1) * n; + a2 = (1 - sqrt(v) / q * k + v * k * k) * n; + b1 = 2 * (k * k - 1) * n; + b2 = (1 - k / q + k * k) * n; + } else { + n = 1 / (1 + sqrt(v) / q * k + v * k * k); + a0 = (1 + k / q + k * k) * n; + a1 = 2 * (k * k - 1) * n; + a2 = (1 - k / q + k * k) * n; + b1 = 2 * (v * k * k - 1) * n; + b2 = (1 - sqrt(v) / q * k + v * k * k) * n; + } + break; + + case Type::HighShelf: + if(gain >= 0) { + n = 1 / (1 + k / q + k * k); + a0 = (v + sqrt(v) / q * k + k * k) * n; + a1 = 2 * (k * k - v) * n; + a2 = (v - sqrt(v) / q * k + k * k) * n; + b1 = 2 * (k * k - 1) * n; + b2 = (1 - k / q + k * k) * n; + } else { + n = 1 / (v + sqrt(v) / q * k + k * k); + a0 = (1 + k / q + k * k) * n; + a1 = 2 * (k * k - 1) * n; + a2 = (1 - k / q + k * k) * n; + b1 = 2 * (k * k - v) * n; + b2 = (v - sqrt(v) / q * k + k * k) * n; + } + break; + + } +} + +inline auto Biquad::process(double in) -> double { + double out = in * a0 + z1; + z1 = in * a1 + z2 - b1 * out; + z2 = in * a2 - b2 * out; + return out; +} + +//compute Q values for low-shelf and high-shelf filtering +inline auto Biquad::shelf(double gain, double slope) -> double { + double a = pow(10, gain / 40); + return 1 / sqrt((a + 1 / a) * (1 / slope - 1) + 2); +} + +//compute Q values for Nth-order butterworth filtering +inline auto Biquad::butterworth(uint order, uint phase) -> double { + return -0.5 / cos(Math::Pi * (phase + order + 0.5) / order); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dsp/iir/dc-removal.hpp b/roms/snes-test-roms/bass-untech/nall/dsp/iir/dc-removal.hpp new file mode 100644 index 00000000..fcd41303 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dsp/iir/dc-removal.hpp @@ -0,0 +1,29 @@ +#pragma once + +#include + +//DC offset removal IIR filter + +namespace nall::DSP::IIR { + +struct DCRemoval { + auto reset() -> void; + auto process(double in) -> double; //normalized sample (-1.0 to +1.0) + +private: + double x; + double y; +}; + +inline auto DCRemoval::reset() -> void { + x = 0.0; + y = 0.0; +} + +inline auto DCRemoval::process(double in) -> double { + x = 0.999 * x + in - y; + y = in; + return x; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dsp/iir/one-pole.hpp b/roms/snes-test-roms/bass-untech/nall/dsp/iir/one-pole.hpp new file mode 100644 index 00000000..0498d685 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dsp/iir/one-pole.hpp @@ -0,0 +1,46 @@ +#pragma once + +#include + +//one-pole first-order IIR filter + +namespace nall::DSP::IIR { + +struct OnePole { + enum class Type : uint { + LowPass, + HighPass, + }; + + auto reset(Type type, double cutoffFrequency, double samplingFrequency) -> void; + auto process(double in) -> double; //normalized sample (-1.0 to +1.0) + +private: + Type type; + double cutoffFrequency; + double samplingFrequency; + double a0, b1; //coefficients + double z1; //first-order IIR +}; + +inline auto OnePole::reset(Type type, double cutoffFrequency, double samplingFrequency) -> void { + this->type = type; + this->cutoffFrequency = cutoffFrequency; + this->samplingFrequency = samplingFrequency; + + z1 = 0.0; + double x = cos(2.0 * Math::Pi * cutoffFrequency / samplingFrequency); + if(type == Type::LowPass) { + b1 = +2.0 - x - sqrt((+2.0 - x) * (+2.0 - x) - 1); + a0 = 1.0 - b1; + } else { + b1 = -2.0 - x + sqrt((-2.0 - x) * (-2.0 - x) - 1); + a0 = 1.0 + b1; + } +} + +inline auto OnePole::process(double in) -> double { + return z1 = in * a0 + z1 * b1; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/dsp/resampler/cubic.hpp b/roms/snes-test-roms/bass-untech/nall/dsp/resampler/cubic.hpp new file mode 100644 index 00000000..995239e4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/dsp/resampler/cubic.hpp @@ -0,0 +1,84 @@ +#pragma once + +#include +#include +#include + +namespace nall::DSP::Resampler { + +struct Cubic { + auto inputFrequency() const -> double { return _inputFrequency; } + auto outputFrequency() const -> double { return _outputFrequency; } + + auto reset(double inputFrequency, double outputFrequency = 0, uint queueSize = 0) -> void; + auto setInputFrequency(double inputFrequency) -> void; + auto pending() const -> bool; + auto read() -> double; + auto write(double sample) -> void; + auto serialize(serializer&) -> void; + +private: + double _inputFrequency; + double _outputFrequency; + + double _ratio; + double _fraction; + double _history[4]; + queue _samples; +}; + +inline auto Cubic::reset(double inputFrequency, double outputFrequency, uint queueSize) -> void { + _inputFrequency = inputFrequency; + _outputFrequency = outputFrequency ? outputFrequency : _inputFrequency; + + _ratio = _inputFrequency / _outputFrequency; + _fraction = 0.0; + for(auto& sample : _history) sample = 0.0; + _samples.resize(queueSize ? queueSize : _outputFrequency * 0.02); //default to 20ms max queue size +} + +inline auto Cubic::setInputFrequency(double inputFrequency) -> void { + _inputFrequency = inputFrequency; + _ratio = _inputFrequency / _outputFrequency; +} + +inline auto Cubic::pending() const -> bool { + return _samples.pending(); +} + +inline auto Cubic::read() -> double { + return _samples.read(); +} + +inline auto Cubic::write(double sample) -> void { + auto& mu = _fraction; + auto& s = _history; + + s[0] = s[1]; + s[1] = s[2]; + s[2] = s[3]; + s[3] = sample; + + while(mu <= 1.0) { + double A = s[3] - s[2] - s[0] + s[1]; + double B = s[0] - s[1] - A; + double C = s[2] - s[0]; + double D = s[1]; + + _samples.write(A * mu * mu * mu + B * mu * mu + C * mu + D); + mu += _ratio; + } + + mu -= 1.0; +} + +inline auto Cubic::serialize(serializer& s) -> void { + s(_inputFrequency); + s(_outputFrequency); + s(_ratio); + s(_fraction); + s(_history); + s(_samples); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/elliptic-curve/curve25519.hpp b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/curve25519.hpp new file mode 100644 index 00000000..8aed8359 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/curve25519.hpp @@ -0,0 +1,57 @@ +#pragma once + +#if defined(EC_REFERENCE) + #include +#else + #include +#endif + +namespace nall::EllipticCurve { + +struct Curve25519 { + auto sharedKey(uint256_t secretKey, uint256_t basepoint = 9) const -> uint256_t { + secretKey &= (1_u256 << 254) - 8; + secretKey |= (1_u256 << 254); + basepoint &= ~0_u256 >> 1; + + point p = scalarMultiply(basepoint % P, secretKey); + field k = p.x * reciprocal(p.z); + return k(); + } + +private: + using field = Modulo25519; + struct point { field x, z; }; + const BarrettReduction<256> P = BarrettReduction<256>{EllipticCurve::P}; + + auto montgomeryDouble(point p) const -> point { + field a = square(p.x + p.z); + field b = square(p.x - p.z); + field c = a - b; + field d = a + c * 121665; + return {a * b, c * d}; + } + + auto montgomeryAdd(point p, point q, field b) const -> point { + return { + square(p.x * q.x - p.z * q.z), + square(p.x * q.z - p.z * q.x) * b + }; + } + + auto scalarMultiply(field b, uint256_t exponent) const -> point { + point p{1, 0}, q{b, 1}; + for(uint bit : reverse(range(255))) { + bool condition = exponent >> bit & 1; + cswap(condition, p.x, q.x); + cswap(condition, p.z, q.z); + q = montgomeryAdd(p, q, b); + p = montgomeryDouble(p); + cswap(condition, p.x, q.x); + cswap(condition, p.z, q.z); + } + return p; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/elliptic-curve/ed25519.hpp b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/ed25519.hpp new file mode 100644 index 00000000..50110426 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/ed25519.hpp @@ -0,0 +1,144 @@ +#pragma once + +#include +#if defined(EC_REFERENCE) + #include +#else + #include +#endif + +namespace nall::EllipticCurve { + +static const uint256_t L = (1_u256 << 252) + 27742317777372353535851937790883648493_u256; + +struct Ed25519 { + auto publicKey(uint256_t privateKey) const -> uint256_t { + return compress(scalarMultiply(B, clamp(hash(privateKey)) % L)); + } + + auto sign(array_view message, uint256_t privateKey) const -> uint512_t { + uint512_t H = hash(privateKey); + uint256_t a = clamp(H) % L; + uint256_t A = compress(scalarMultiply(B, a)); + + uint512_t r = hash(upper(H), message) % L; + uint256_t R = compress(scalarMultiply(B, r)); + + uint512_t k = hash(R, A, message) % L; + uint256_t S = (k * a + r) % L; + + return uint512_t(S) << 256 | R; + } + + auto verify(array_view message, uint512_t signature, uint256_t publicKey) const -> bool { + auto R = decompress(lower(signature)); + auto A = decompress(publicKey); + if(!R || !A) return false; + + uint256_t S = upper(signature) % L; + uint512_t r = hash(lower(signature), publicKey, message) % L; + + auto p = scalarMultiply(B, S); + auto q = edwardsAdd(R(), scalarMultiply(A(), r)); + if(!onCurve(p) || !onCurve(q)) return false; + if(p.x * q.z - q.x * p.z) return false; + if(p.y * q.z - q.y * p.z) return false; + return true; + } + +private: + using field = Modulo25519; + struct point { field x, y, z, t; }; + const field D = -field(121665) * reciprocal(field(121666)); + const point B = *decompress((field(4) * reciprocal(field(5)))()); + const BarrettReduction<256> L = BarrettReduction<256>{EllipticCurve::L}; + + auto input(Hash::SHA512&) const -> void {} + + template auto input(Hash::SHA512& hash, uint256_t value, P&&... p) const -> void { + for(uint byte : range(32)) hash.input(uint8_t(value >> byte * 8)); + input(hash, forward

(p)...); + } + + template auto input(Hash::SHA512& hash, array_view value, P&&... p) const -> void { + hash.input(value); + input(hash, forward

(p)...); + } + + template auto hash(P&&... p) const -> uint512_t { + Hash::SHA512 hash; + input(hash, forward

(p)...); + uint512_t result; + for(auto byte : reverse(hash.output())) result = result << 8 | byte; + return result; + } + + auto clamp(uint256_t p) const -> uint256_t { + p &= (1_u256 << 254) - 8; + p |= (1_u256 << 254); + return p; + } + + auto onCurve(point p) const -> bool { + if(!p.z) return false; + if(p.x * p.y - p.z * p.t) return false; + if(square(p.y) - square(p.x) - square(p.z) - square(p.t) * D) return false; + return true; + } + + auto decompress(uint256_t c) const -> maybe { + field y = c & ~0_u256 >> 1; + field x = squareRoot((square(y) - 1) * reciprocal(D * square(y) + 1)); + if(c >> 255) x = -x; + point p{x, y, 1, x * y}; + if(!onCurve(p)) return nothing; + return p; + } + + auto compress(point p) const -> uint256_t { + field r = reciprocal(p.z); + field x = p.x * r; + field y = p.y * r; + return (x & 1) << 255 | (y & ~0_u256 >> 1); + } + + auto edwardsDouble(point p) const -> point { + field a = square(p.x); + field b = square(p.y); + field c = square(p.z); + field d = -a; + field e = square(p.x + p.y) - a - b; + field g = d + b; + field f = g - (c + c); + field h = d - b; + return {e * f, g * h, f * g, e * h}; + } + + auto edwardsAdd(point p, point q) const -> point { + field a = (p.y - p.x) * (q.y - q.x); + field b = (p.y + p.x) * (q.y + q.x); + field c = (p.t + p.t) * q.t * D; + field d = (p.z + p.z) * q.z; + field e = b - a; + field f = d - c; + field g = d + c; + field h = b + a; + return {e * f, g * h, f * g, e * h}; + } + + auto scalarMultiply(point q, uint256_t exponent) const -> point { + point p{0, 1, 1, 0}, c; + for(uint bit : reverse(range(253))) { + p = edwardsDouble(p); + c = edwardsAdd(p, q); + bool condition = exponent >> bit & 1; + cmove(condition, p.x, c.x); + cmove(condition, p.y, c.y); + cmove(condition, p.z, c.z); + cmove(condition, p.t, c.t); + } + return p; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-optimized.hpp b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-optimized.hpp new file mode 100644 index 00000000..261cdf51 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-optimized.hpp @@ -0,0 +1,218 @@ +#pragma once + +#include + +namespace nall::EllipticCurve { + +static const uint256_t P = (1_u256 << 255) - 19; + +#define Mask ((1ull << 51) - 1) + +struct Modulo25519 { + Modulo25519() = default; + Modulo25519(const Modulo25519&) = default; + Modulo25519(uint64_t a, uint64_t b = 0, uint64_t c = 0, uint64_t d = 0, uint64_t e = 0) : l{a, b, c, d, e} {} + Modulo25519(uint256_t n); + + explicit operator bool() const { return (bool)operator()(); } + auto operator[](uint index) -> uint64_t& { return l[index]; } + auto operator[](uint index) const -> uint64_t { return l[index]; } + auto operator()() const -> uint256_t; + +private: + uint64_t l[5]; //51-bits per limb; 255-bits total +}; + +inline Modulo25519::Modulo25519(uint256_t n) { + l[0] = n >> 0 & Mask; + l[1] = n >> 51 & Mask; + l[2] = n >> 102 & Mask; + l[3] = n >> 153 & Mask; + l[4] = n >> 204 & Mask; +} + +inline auto Modulo25519::operator()() const -> uint256_t { + Modulo25519 o = *this; + + o[1] += (o[0] >> 51); o[0] &= Mask; + o[2] += (o[1] >> 51); o[1] &= Mask; + o[3] += (o[2] >> 51); o[2] &= Mask; + o[4] += (o[3] >> 51); o[3] &= Mask; + o[0] += 19 * (o[4] >> 51); o[4] &= Mask; + + o[1] += (o[0] >> 51); o[0] &= Mask; + o[2] += (o[1] >> 51); o[1] &= Mask; + o[3] += (o[2] >> 51); o[2] &= Mask; + o[4] += (o[3] >> 51); o[3] &= Mask; + o[0] += 19 * (o[4] >> 51); o[4] &= Mask; + + o[0] += 19; + o[1] += (o[0] >> 51); o[0] &= Mask; + o[2] += (o[1] >> 51); o[1] &= Mask; + o[3] += (o[2] >> 51); o[2] &= Mask; + o[4] += (o[3] >> 51); o[3] &= Mask; + o[0] += 19 * (o[4] >> 51); o[4] &= Mask; + + o[0] += Mask - 18; + o[1] += Mask; + o[2] += Mask; + o[3] += Mask; + o[4] += Mask; + + o[1] += o[0] >> 51; o[0] &= Mask; + o[2] += o[1] >> 51; o[1] &= Mask; + o[3] += o[2] >> 51; o[2] &= Mask; + o[4] += o[3] >> 51; o[3] &= Mask; + o[4] &= Mask; + + return (uint256_t)o[0] << 0 | (uint256_t)o[1] << 51 | (uint256_t)o[2] << 102 | (uint256_t)o[3] << 153 | (uint256_t)o[4] << 204; +} + +inline auto cmove(bool move, Modulo25519& l, const Modulo25519& r) -> void { + uint64_t mask = -move; + l[0] ^= mask & (l[0] ^ r[0]); + l[1] ^= mask & (l[1] ^ r[1]); + l[2] ^= mask & (l[2] ^ r[2]); + l[3] ^= mask & (l[3] ^ r[3]); + l[4] ^= mask & (l[4] ^ r[4]); +} + +inline auto cswap(bool swap, Modulo25519& l, Modulo25519& r) -> void { + uint64_t mask = -swap, x; + x = mask & (l[0] ^ r[0]); l[0] ^= x; r[0] ^= x; + x = mask & (l[1] ^ r[1]); l[1] ^= x; r[1] ^= x; + x = mask & (l[2] ^ r[2]); l[2] ^= x; r[2] ^= x; + x = mask & (l[3] ^ r[3]); l[3] ^= x; r[3] ^= x; + x = mask & (l[4] ^ r[4]); l[4] ^= x; r[4] ^= x; +} + +inline auto operator-(const Modulo25519& l) -> Modulo25519 { //P - l + Modulo25519 o; + uint64_t c; + o[0] = 0xfffffffffffda - l[0]; c = o[0] >> 51; o[0] &= Mask; + o[1] = 0xffffffffffffe - l[1] + c; c = o[1] >> 51; o[1] &= Mask; + o[2] = 0xffffffffffffe - l[2] + c; c = o[2] >> 51; o[2] &= Mask; + o[3] = 0xffffffffffffe - l[3] + c; c = o[3] >> 51; o[3] &= Mask; + o[4] = 0xffffffffffffe - l[4] + c; c = o[4] >> 51; o[4] &= Mask; + o[0] += c * 19; + return o; +} + +inline auto operator+(const Modulo25519& l, const Modulo25519& r) -> Modulo25519 { + Modulo25519 o; + uint64_t c; + o[0] = l[0] + r[0]; c = o[0] >> 51; o[0] &= Mask; + o[1] = l[1] + r[1] + c; c = o[1] >> 51; o[1] &= Mask; + o[2] = l[2] + r[2] + c; c = o[2] >> 51; o[2] &= Mask; + o[3] = l[3] + r[3] + c; c = o[3] >> 51; o[3] &= Mask; + o[4] = l[4] + r[4] + c; c = o[4] >> 51; o[4] &= Mask; + o[0] += c * 19; + return o; +} + +inline auto operator-(const Modulo25519& l, const Modulo25519& r) -> Modulo25519 { + Modulo25519 o; + uint64_t c; + o[0] = l[0] + 0x1fffffffffffb4 - r[0]; c = o[0] >> 51; o[0] &= Mask; + o[1] = l[1] + 0x1ffffffffffffc - r[1] + c; c = o[1] >> 51; o[1] &= Mask; + o[2] = l[2] + 0x1ffffffffffffc - r[2] + c; c = o[2] >> 51; o[2] &= Mask; + o[3] = l[3] + 0x1ffffffffffffc - r[3] + c; c = o[3] >> 51; o[3] &= Mask; + o[4] = l[4] + 0x1ffffffffffffc - r[4] + c; c = o[4] >> 51; o[4] &= Mask; + o[0] += c * 19; + return o; +} + +inline auto operator*(const Modulo25519& l, uint64_t scalar) -> Modulo25519 { + Modulo25519 o; + uint128_t a; + a = (uint128_t)l[0] * scalar; o[0] = a & Mask; + a = (uint128_t)l[1] * scalar + (a >> 51 & Mask); o[1] = a & Mask; + a = (uint128_t)l[2] * scalar + (a >> 51 & Mask); o[2] = a & Mask; + a = (uint128_t)l[3] * scalar + (a >> 51 & Mask); o[3] = a & Mask; + a = (uint128_t)l[4] * scalar + (a >> 51 & Mask); o[4] = a & Mask; + o[0] += (a >> 51) * 19; + return o; +} + +inline auto operator*(const Modulo25519& l, Modulo25519 r) -> Modulo25519 { + uint128_t t[] = { + (uint128_t)r[0] * l[0], + (uint128_t)r[0] * l[1] + (uint128_t)r[1] * l[0], + (uint128_t)r[0] * l[2] + (uint128_t)r[1] * l[1] + (uint128_t)r[2] * l[0], + (uint128_t)r[0] * l[3] + (uint128_t)r[1] * l[2] + (uint128_t)r[2] * l[1] + (uint128_t)r[3] * l[0], + (uint128_t)r[0] * l[4] + (uint128_t)r[1] * l[3] + (uint128_t)r[2] * l[2] + (uint128_t)r[3] * l[1] + (uint128_t)r[4] * l[0] + }; + + r[1] *= 19, r[2] *= 19, r[3] *= 19, r[4] *= 19; + + t[0] += (uint128_t)r[4] * l[1] + (uint128_t)r[3] * l[2] + (uint128_t)r[2] * l[3] + (uint128_t)r[1] * l[4]; + t[1] += (uint128_t)r[4] * l[2] + (uint128_t)r[3] * l[3] + (uint128_t)r[2] * l[4]; + t[2] += (uint128_t)r[4] * l[3] + (uint128_t)r[3] * l[4]; + t[3] += (uint128_t)r[4] * l[4]; + + uint64_t c; r[0] = t[0] & Mask; c = (uint64_t)(t[0] >> 51); + t[1] += c; r[1] = t[1] & Mask; c = (uint64_t)(t[1] >> 51); + t[2] += c; r[2] = t[2] & Mask; c = (uint64_t)(t[2] >> 51); + t[3] += c; r[3] = t[3] & Mask; c = (uint64_t)(t[3] >> 51); + t[4] += c; r[4] = t[4] & Mask; c = (uint64_t)(t[4] >> 51); + + r[0] += c * 19; c = r[0] >> 51; r[0] &= Mask; + r[1] += c; c = r[1] >> 51; r[1] &= Mask; + r[2] += c; + return r; +} + +inline auto operator&(const Modulo25519& lhs, uint256_t rhs) -> uint256_t { + return lhs() & rhs; +} + +inline auto square(const Modulo25519& lhs) -> Modulo25519 { + Modulo25519 r{lhs}; + Modulo25519 d{r[0] * 2, r[1] * 2, r[2] * 2 * 19, r[4] * 19, r[4] * 19 * 2}; + + uint128_t t[5]; + t[0] = (uint128_t)r[0] * r[0] + (uint128_t)d[4] * r[1] + (uint128_t)d[2] * r[3]; + t[1] = (uint128_t)d[0] * r[1] + (uint128_t)d[4] * r[2] + (uint128_t)r[3] * r[3] * 19; + t[2] = (uint128_t)d[0] * r[2] + (uint128_t)r[1] * r[1] + (uint128_t)d[4] * r[3]; + t[3] = (uint128_t)d[0] * r[3] + (uint128_t)d[1] * r[2] + (uint128_t)r[4] * d[3]; + t[4] = (uint128_t)d[0] * r[4] + (uint128_t)d[1] * r[3] + (uint128_t)r[2] * r[2]; + + uint64_t c; r[0] = t[0] & Mask; c = (uint64_t)(t[0] >> 51); + t[1] += c; r[1] = t[1] & Mask; c = (uint64_t)(t[1] >> 51); + t[2] += c; r[2] = t[2] & Mask; c = (uint64_t)(t[2] >> 51); + t[3] += c; r[3] = t[3] & Mask; c = (uint64_t)(t[3] >> 51); + t[4] += c; r[4] = t[4] & Mask; c = (uint64_t)(t[4] >> 51); + + r[0] += c * 19; c = r[0] >> 51; r[0] &= Mask; + r[1] += c; c = r[1] >> 51; r[1] &= Mask; + r[2] += c; + return r; +} + +inline auto exponentiate(const Modulo25519& lhs, uint256_t exponent) -> Modulo25519 { + Modulo25519 x = 1, y; + for(uint bit : reverse(range(256))) { + x = square(x); + y = x * lhs; + cmove(exponent >> bit & 1, x, y); + } + return x; +} + +inline auto reciprocal(const Modulo25519& lhs) -> Modulo25519 { + return exponentiate(lhs, P - 2); +} + +inline auto squareRoot(const Modulo25519& lhs) -> Modulo25519 { + static const Modulo25519 I = exponentiate(Modulo25519(2), P - 1 >> 2); //I == sqrt(-1) + Modulo25519 x = exponentiate(lhs, P + 3 >> 3); + Modulo25519 y = x * I; + cmove(bool(square(x) - lhs), x, y); + y = -x; + cmove(x & 1, x, y); + return x; +} + +#undef Mask + +} diff --git a/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-reference.hpp b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-reference.hpp new file mode 100644 index 00000000..9565dabc --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/elliptic-curve/modulo25519-reference.hpp @@ -0,0 +1,84 @@ +#pragma once + +//warning: this implementation leaks side-channel information +//use modulo25519-optimized.hpp in production + +#include + +namespace nall::EllipticCurve { + +static const uint256_t P = (1_u256 << 255) - 19; + +struct Modulo25519 { + Modulo25519() = default; + Modulo25519(const Modulo25519& source) : value(source.value) {} + template Modulo25519(const T& value) : value(value) {} + explicit operator bool() const { return (bool)value; } + auto operator()() const -> uint256_t { return value; } + +private: + uint256_t value; +}; + +inline auto operator-(const Modulo25519& lhs) -> Modulo25519 { + return P - lhs(); +} + +inline auto operator+(const Modulo25519& lhs, const Modulo25519& rhs) -> Modulo25519 { + uint512_t value = (uint512_t)lhs() + rhs(); + if(value >= P) value -= P; + return value; +} + +inline auto operator-(const Modulo25519& lhs, const Modulo25519& rhs) -> Modulo25519 { + uint512_t value = (uint512_t)lhs(); + if(value < rhs()) value += P; + return uint256_t(value - rhs()); +} + +inline auto operator*(const Modulo25519& lhs, const Modulo25519& rhs) -> Modulo25519 { + static const BarrettReduction<256> P{EllipticCurve::P}; + uint256_t hi, lo; + mul(lhs(), rhs(), hi, lo); + return uint512_t{hi, lo} % P; +} + +inline auto operator&(const Modulo25519& lhs, uint256_t rhs) -> uint256_t { + return lhs() & rhs; +} + +inline auto square(const Modulo25519& lhs) -> Modulo25519 { + static const BarrettReduction<256> P{EllipticCurve::P}; + uint256_t hi, lo; + square(lhs(), hi, lo); + return uint512_t{hi, lo} % P; +} + +inline auto exponentiate(const Modulo25519& lhs, uint256_t exponent) -> Modulo25519 { + if(exponent == 0) return 1; + Modulo25519 value = square(exponentiate(lhs, exponent >> 1)); + if(exponent & 1) value = value * lhs; + return value; +} + +inline auto reciprocal(const Modulo25519& lhs) -> Modulo25519 { + return exponentiate(lhs, P - 2); +} + +inline auto squareRoot(const Modulo25519& lhs) -> Modulo25519 { + static const Modulo25519 I = exponentiate(Modulo25519(2), P - 1 >> 2); //I = sqrt(-1) + Modulo25519 value = exponentiate(lhs, P + 3 >> 3); + if(square(value) - lhs) value = value * I; + if(value & 1) value = -value; + return value; +} + +inline auto cmove(bool condition, Modulo25519& lhs, const Modulo25519& rhs) -> void { + if(condition) lhs = rhs; +} + +inline auto cswap(bool condition, Modulo25519& lhs, Modulo25519& rhs) -> void { + if(condition) swap(lhs, rhs); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/emulation/21fx.hpp b/roms/snes-test-roms/bass-untech/nall/emulation/21fx.hpp new file mode 100644 index 00000000..7a663df0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/emulation/21fx.hpp @@ -0,0 +1,140 @@ +#pragma once + +#include +#include +using namespace nall; + +using int8 = Integer< 8>; +using int16 = Integer<16>; +using int24 = Integer<24>; +using int32 = Integer<32>; +using int64 = Integer<64>; + +using uint8 = Natural< 8>; +using uint16 = Natural<16>; +using uint24 = Natural<24>; +using uint32 = Natural<32>; +using uint64 = Natural<64>; + +struct FX { + auto open(Arguments& arguments) -> bool; + auto close() -> void; + auto readable() -> bool; + auto read() -> uint8_t; + auto writable() -> bool; + auto write(uint8_t data) -> void; + + auto read(uint offset, uint length) -> vector; + auto write(uint offset, const void* buffer, uint length) -> void; + auto write(uint offset, const vector& buffer) -> void { write(offset, buffer.data(), buffer.size()); } + auto execute(uint offset) -> void; + + auto read(uint offset) -> uint8_t; + auto write(uint offset, uint8_t data) -> void; + + serial device; +}; + +inline auto FX::open(Arguments& arguments) -> bool { + //device name override support + string name; + arguments.take("--device", name); + if(!device.open(name)) { + print("[21fx] error: unable to open hardware device\n"); + return false; + } + + //flush the device (to clear floating inputs) + while(true) { + while(readable()) read(); + auto iplrom = read(0x2184, 122); + auto sha256 = Hash::SHA256(iplrom).digest(); + if(sha256 == "41b79712a4a2d16d39894ae1b38cde5c41dad22eadc560df631d39f13df1e4b9") break; + } + + return true; +} + +inline auto FX::close() -> void { + device.close(); +} + +inline auto FX::readable() -> bool { + return device.readable(); +} + +//1000ns delay avoids burning CPU core at 100%; does not slow down max transfer rate at all +inline auto FX::read() -> uint8_t { + while(!readable()) usleep(1000); + uint8_t buffer[1] = {0}; + device.read(buffer, 1); + return buffer[0]; +} + +inline auto FX::writable() -> bool { + return device.writable(); +} + +inline auto FX::write(uint8_t data) -> void { + while(!writable()) usleep(1000); + uint8_t buffer[1] = {data}; + device.write(buffer, 1); +} + +// + +inline auto FX::read(uint offset, uint length) -> vector { + write(0x21); + write(0x66); + write(0x78); + write(offset >> 16); + write(offset >> 8); + write(offset >> 0); + write(0x01); + write(length >> 8); + write(length >> 0); + write(0x00); + + vector buffer; + while(length--) buffer.append(read()); + return buffer; +} + +inline auto FX::write(uint offset, const void* data, uint length) -> void { + write(0x21); + write(0x66); + write(0x78); + write(offset >> 16); + write(offset >> 8); + write(offset >> 0); + write(0x01); + write(length >> 8); + write(length >> 0); + write(0x01); + + auto buffer = (uint8_t*)data; + for(auto n : range(length)) write(buffer[n]); + write(0x00); +} + +inline auto FX::execute(uint offset) -> void { + write(0x21); + write(0x66); + write(0x78); + write(offset >> 16); + write(offset >> 8); + write(offset >> 0); + write(0x00); +} + +// + +inline auto FX::read(uint offset) -> uint8_t { + auto buffer = read(offset, 1); + return buffer[0]; +} + +inline auto FX::write(uint offset, uint8_t data) -> void { + vector buffer = {data}; + write(offset, buffer); +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/base.hpp b/roms/snes-test-roms/bass-untech/nall/encode/base.hpp new file mode 100644 index 00000000..ac55486e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/base.hpp @@ -0,0 +1,38 @@ +#pragma once + +//required bytes: ceil(bits / log2(base)) +//base57 => 128=22, 256=44, 512=88 +//base62 => 128=22, 256=43, 512=86 +//base64 => 128=22, 256=43, 512=86 + +#include + +namespace nall::Encode { + +template inline auto Base(T value) -> string { + static const string format = + Bits == 2 ? "01" + : Bits == 8 ? "01234567" + : Bits == 10 ? "0123456789" + : Bits == 16 ? "0123456789abcdef" + : Bits == 32 ? "0123456789abcdefghijklmnopqrstuv" + : Bits == 34 ? "023456789abcdefghijkmnopqrstuvwxyz" //1l + : Bits == 36 ? "0123456789abcdefghijklmnopqrstuvwxyz" + : Bits == 57 ? "23456789ABCDEFGHJKLMNPQRSTUVWXYZabcdefghijkmnopqrstuvwxyz" //01IOl + : Bits == 62 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz" + : Bits == 64 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz{}" + : Bits == 85 ? "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZabcdefghijklmnopqrstuvwxyz!#$%()+,-.:;=@[]^_`{|}~" //\ "&'*/<>? + : ""; + static const uint size = ceil(sizeof(T) * 8 / log2(Bits)); + + string result; + result.resize(size); + char* data = result.get() + size; + for(auto byte : result) { + *--data = format[value % Bits]; + value /= Bits; + } + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/base64.hpp b/roms/snes-test-roms/bass-untech/nall/encode/base64.hpp new file mode 100644 index 00000000..a1d518cf --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/base64.hpp @@ -0,0 +1,68 @@ +#pragma once + +namespace nall::Encode { + +inline auto Base64(const void* vdata, uint size, const string& format = "MIME") -> string { + static bool initialized = false; + static char lookup[65] = {0}; + if(!initialized) { + initialized = true; + for(uint n : range(26)) lookup[n + 0] = 'A' + n; + for(uint n : range(26)) lookup[n + 26] = 'a' + n; + for(uint n : range(10)) lookup[n + 52] = '0' + n; + } + + if(format == "MIME") { + lookup[62] = '+'; + lookup[63] = '/'; + lookup[64] = '='; + } else if(format == "URI") { + lookup[62] = '-'; + lookup[63] = '_'; + lookup[64] = 0; + } else return ""; + + auto data = (const uint8_t*)vdata; + uint overflow = (3 - (size % 3)) % 3; //bytes to round to nearest multiple of 3 + string result; + uint8_t buffer; + for(uint n : range(size)) { + switch(n % 3) { + case 0: + buffer = data[n] >> 2; + result.append(lookup[buffer]); + buffer = (data[n] & 3) << 4; + break; + + case 1: + buffer |= data[n] >> 4; + result.append(lookup[buffer]); + buffer = (data[n] & 15) << 2; + break; + + case 2: + buffer |= data[n] >> 6; + result.append(lookup[buffer]); + buffer = (data[n] & 63); + result.append(lookup[buffer]); + break; + } + } + + if(overflow) result.append(lookup[buffer]); + if(lookup[64]) { + while(result.size() % 4) result.append(lookup[64]); + } + + return result; +} + +inline auto Base64(const vector& buffer, const string& format = "MIME") -> string { + return Base64(buffer.data(), buffer.size(), format); +} + +inline auto Base64(const string& text, const string& format = "MIME") -> string { + return Base64(text.data(), text.size(), format); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/bmp.hpp b/roms/snes-test-roms/bass-untech/nall/encode/bmp.hpp new file mode 100644 index 00000000..1ccc9304 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/bmp.hpp @@ -0,0 +1,47 @@ +#pragma once + +namespace nall::Encode { + +struct BMP { + static auto create(const string& filename, const void* data, uint pitch, uint width, uint height, bool alpha) -> bool { + auto fp = file::open(filename, file::mode::write); + if(!fp) return false; + + uint bitsPerPixel = alpha ? 32 : 24; + uint bytesPerPixel = bitsPerPixel / 8; + uint alignedWidth = width * bytesPerPixel; + uint paddingLength = 0; + uint imageSize = alignedWidth * height; + uint fileSize = 0x36 + imageSize; + while(alignedWidth % 4) alignedWidth++, paddingLength++; + + fp.writel(0x4d42, 2); //signature + fp.writel(fileSize, 4); //file size + fp.writel(0, 2); //reserved + fp.writel(0, 2); //reserved + fp.writel(0x36, 4); //offset + + fp.writel(40, 4); //DIB size + fp.writel(width, 4); //width + fp.writel(-height, 4); //height + fp.writel(1, 2); //color planes + fp.writel(bitsPerPixel, 2); //bits per pixel + fp.writel(0, 4); //compression method (BI_RGB) + fp.writel(imageSize, 4); //image data size + fp.writel(3780, 4); //horizontal resolution + fp.writel(3780, 4); //vertical resolution + fp.writel(0, 4); //palette size + fp.writel(0, 4); //important color count + + pitch >>= 2; + for(auto y : range(height)) { + auto p = (const uint32_t*)data + y * pitch; + for(auto x : range(width)) fp.writel(*p++, bytesPerPixel); + if(paddingLength) fp.writel(0, paddingLength); + } + + return true; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/bwt.hpp b/roms/snes-test-roms/bass-untech/nall/encode/bwt.hpp new file mode 100644 index 00000000..84e00d9c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/bwt.hpp @@ -0,0 +1,86 @@ +#pragma once + +//burrows-wheeler transform + +#include + +namespace nall::Encode { + +/* + A standard suffix array cannot produce a proper burrows-wheeler transform, due to rotations. + + Take the input string, "nall", this gives us: + nall + alln + llna + lnal + + If we suffix sort this, we produce: + all => alln + l => lnal + ll => llna + nall => nall + + If we sort this, we produce: + alln + llna + lnal + nall + + Thus, suffix sorting gives us "nlal" as the last column instead of "nall". + This is because BWT rotates the input string, whereas suffix arrays sort the input string. + + Adding a 256th character terminator before sorting will not produce the desired result, either. + A more complicated string such as "mississippi" will sort as "ssmppissiii" with terminator=256, + and as "ipssmpissii" with terminator=0, alphabet=1..256, whereas we want "pssmipissii". + + Performing a merge sort to use a specialized comparison function that wraps suffixes is too slow at O(n log n). + + Producing a custom induced sort to handle rotations would be incredibly complicated, + owing to the recursive nature of induced sorting, among other things. + + So instead, a temporary array is produced that contains the input suffix twice. + This is then fed into the suffix array sort, and the doubled matches are filtered out. + After this point, suffixes are sorted in their mirrored form, and the correct result can be derived + + The result of this is an O(2n) algorithm, which vastly outperforms a naive O(n log n) algorithm, + but is still far from ideal. However, this will have to do until a better solution is devised. + + Although to be fair, BWT is inferior to the bijective BWT anyway, so it may not be worth the effort. +*/ + +inline auto BWT(array_view input) -> vector { + auto size = input.size(); + vector output; + output.reserve(8 + 8 + size); + for(uint byte : range(8)) output.append(size >> byte * 8); + for(uint byte : range(8)) output.append(0x00); + + vector buffer; + buffer.reserve(2 * size); + for(uint offset : range(size)) buffer.append(input[offset]); + for(uint offset : range(size)) buffer.append(input[offset]); + + auto suffixes = SuffixArray(buffer); + + vector prefixes; + prefixes.reserve(size); + + for(uint offset : range(2 * size + 1)) { + uint suffix = suffixes[offset]; + if(suffix >= size) continue; //beyond the bounds of the original input string + prefixes.append(suffix); + } + + uint64_t root = 0; + for(uint offset : range(size)) { + uint suffix = prefixes[offset]; + if(suffix == 0) root = offset, suffix = size; + output.append(input[--suffix]); + } + for(uint byte : range(8)) output[8 + byte] = root >> byte * 8; + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/html.hpp b/roms/snes-test-roms/bass-untech/nall/encode/html.hpp new file mode 100644 index 00000000..6e4fd04b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/html.hpp @@ -0,0 +1,18 @@ +#pragma once + +namespace nall::Encode { + +inline auto HTML(const string& input) -> string { + string output; + for(char c : input) { + if(c == '&' ) { output.append("&" ); continue; } + if(c == '<' ) { output.append("<" ); continue; } + if(c == '>' ) { output.append(">" ); continue; } + if(c == '"' ) { output.append("""); continue; } + if(c == '\'') { output.append("'"); continue; } + output.append(c); + } + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/huffman.hpp b/roms/snes-test-roms/bass-untech/nall/encode/huffman.hpp new file mode 100644 index 00000000..18aa25f1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/huffman.hpp @@ -0,0 +1,84 @@ +#pragma once + +namespace nall::Encode { + +inline auto Huffman(array_view input) -> vector { + vector output; + for(uint byte : range(8)) output.append(input.size() >> byte * 8); + + struct Node { + uint frequency = 0; + uint parent = 0; + uint lhs = 0; + uint rhs = 0; + }; + array nodes; + for(uint offset : range(input.size())) nodes[input[offset]].frequency++; + + uint count = 0; + for(uint offset : range(511)) { + if(nodes[offset].frequency) count++; + else nodes[offset].parent = 511; + } + + auto minimum = [&] { + uint frequency = ~0, minimum = 511; + for(uint index : range(511)) { + if(!nodes[index].parent && nodes[index].frequency && nodes[index].frequency < frequency) { + frequency = nodes[index].frequency; + minimum = index; + } + } + return minimum; + }; + + //group the least two frequently used nodes until only one node remains + uint index = 256; + for(uint remaining = max(2, count); remaining >= 2; remaining--) { + uint lhs = minimum(); + nodes[lhs].parent = index; + uint rhs = minimum(); + nodes[rhs].parent = index; + if(remaining == 2) index = nodes[lhs].parent = nodes[rhs].parent = 511; + nodes[index].lhs = lhs; + nodes[index].rhs = rhs; + nodes[index].parent = 0; + nodes[index].frequency = nodes[lhs].frequency + nodes[rhs].frequency; + index++; + } + + uint byte = 0, bits = 0; + auto write = [&](bool bit) { + byte = byte << 1 | bit; + if(++bits == 8) output.append(byte), bits = 0; + }; + + //only the upper half of the table is needed for decompression + //the first 256 nodes are always treated as leaf nodes + for(uint offset : range(256)) { + for(uint index : reverse(range(9))) write(nodes[256 + offset].lhs >> index & 1); + for(uint index : reverse(range(9))) write(nodes[256 + offset].rhs >> index & 1); + } + + for(uint byte : input) { + uint node = byte, length = 0; + uint256_t sequence = 0; + //traversing the array produces the bitstream in reverse order + do { + uint parent = nodes[node].parent; + bool bit = nodes[nodes[node].parent].rhs == node; + sequence = sequence << 1 | bit; + length++; + node = parent; + } while(node != 511); + //output the generated bits in the correct order + for(uint index : range(length)) { + write(sequence >> index & 1); + } + } + while(bits) write(0); + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/lzsa.hpp b/roms/snes-test-roms/bass-untech/nall/encode/lzsa.hpp new file mode 100644 index 00000000..2ca59b6e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/lzsa.hpp @@ -0,0 +1,86 @@ +#pragma once + +#include +#include +#include +#include +#include + +namespace nall::Encode { + +inline auto LZSA(array_view input) -> vector { + vector output; + for(uint byte : range(8)) output.append(input.size() >> byte * 8); + + auto suffixArray = SuffixArray(input).lpf(); + uint index = 0; + vector flags; + vector literals; + vector stringLengths; + vector stringOffsets; + + uint byte = 0, bits = 0; + auto flagWrite = [&](bool bit) { + byte = byte << 1 | bit; + if(++bits == 8) flags.append(byte), bits = 0; + }; + + auto literalWrite = [&](uint8_t literal) { + literals.append(literal); + }; + + auto lengthWrite = [&](uint64_t length) { + if(length < 1 << 7) length = length << 1 | 0b1; + else if(length < 1 << 14) length = length << 2 | 0b10; + else if(length < 1 << 21) length = length << 3 | 0b100; + else if(length < 1 << 28) length = length << 4 | 0b1000; + else /*length < 1 << 35*/length = length << 5 | 0b10000; + while(length) stringLengths.append(length), length >>= 8; + }; + + auto offsetWrite = [&](uint offset) { + stringOffsets.append(offset >> 0); if(index < 1 << 8) return; + stringOffsets.append(offset >> 8); if(index < 1 << 16) return; + stringOffsets.append(offset >> 16); if(index < 1 << 24) return; + stringOffsets.append(offset >> 24); + }; + + while(index < input.size()) { + int length, offset; + suffixArray.previous(length, offset, index); + +/* for(uint ahead = 1; ahead <= 2; ahead++) { + int aheadLength, aheadOffset; + suffixArray.previous(aheadLength, aheadOffset, index + ahead); + if(aheadLength > length && aheadOffset >= 0) { + length = 0; + break; + } + } */ + + if(length < 6 || offset < 0) { + flagWrite(0); + literalWrite(input[index++]); + } else { + flagWrite(1); + lengthWrite(length - 6); + offsetWrite(index - offset); + index += length; + } + } + while(bits) flagWrite(0); + + auto save = [&](const vector& buffer) { + for(uint byte : range(8)) output.append(buffer.size() >> byte * 8); + output.append(buffer); + }; + + save(Encode::Huffman(flags)); + save(Encode::Huffman(literals)); + save(Encode::Huffman(stringLengths)); + save(Encode::Huffman(stringOffsets)); + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/mtf.hpp b/roms/snes-test-roms/bass-untech/nall/encode/mtf.hpp new file mode 100644 index 00000000..42f24b19 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/mtf.hpp @@ -0,0 +1,30 @@ +#pragma once + +//move to front + +namespace nall::Encode { + +inline auto MTF(array_view input) -> vector { + vector output; + output.resize(input.size()); + + uint8_t order[256]; + for(uint n : range(256)) order[n] = n; + + for(uint offset : range(input.size())) { + uint data = input[offset]; + for(uint index : range(256)) { + uint value = order[index]; + if(value == data) { + output[offset] = index; + memory::move(&order[1], &order[0], index); + order[0] = value; + break; + } + } + } + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/png.hpp b/roms/snes-test-roms/bass-untech/nall/encode/png.hpp new file mode 100644 index 00000000..6f2233f9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/png.hpp @@ -0,0 +1,189 @@ +#pragma once + +#include +#include +#include + +namespace nall::Encode { + +//this encodes an array of pixels into an uncompressed PNG image file. +//if optipng or pngcrush are installed, the resulting PNG file will be quickly compressed. +//if nall gains a deflate implementation one day, then this can be improved to offer integrated compression. + +struct PNG { + static auto RGB8 (const string& filename, const void* data, uint pitch, uint width, uint height) -> bool; + static auto RGBA8(const string& filename, const void* data, uint pitch, uint width, uint height) -> bool; + +private: + auto compress(const string& filename) -> bool; + auto open(const string& filename) -> bool; + auto close() -> void; + auto header() -> void; + auto footer() -> void; + auto information(uint width, uint height, uint depth, uint type) -> void; + auto dataHeader(uint width, uint height, uint bitsPerPixel) -> void; + auto dataLine(bool lastLine) -> void; + auto dataFooter() -> void; + auto write(uint8_t data) -> void; + auto adler(uint8_t data) -> void; + + file_buffer fp; + Hash::CRC32 crc32; + uint16_t adler1 = 1; + uint16_t adler2 = 0; + uint16_t bytesPerLine = 0; +}; + +inline auto PNG::RGB8(const string& filename, const void* data, uint pitch, uint width, uint height) -> bool { + PNG png; + if(!png.open(filename)) return false; + + png.header(); + png.information(width, height, 8, 2); + png.dataHeader(width, height, 24); + for(uint y : range(height)) { + const auto input = (const uint32_t*)data + y * (pitch >> 2); + png.dataLine(y == height - 1); + for(uint x : range(width)) { + auto pixel = input[x]; //RGB + png.adler(pixel >> 16); //R + png.adler(pixel >> 8); //G + png.adler(pixel >> 0); //B + } + } + png.dataFooter(); + png.footer(); + png.close(); + png.compress(filename); + return true; +} + +inline auto PNG::RGBA8(const string& filename, const void* data, uint pitch, uint width, uint height) -> bool { + PNG png; + if(!png.open(filename)) return false; + + png.header(); + png.information(width, height, 8, 6); + png.dataHeader(width, height, 32); + for(uint y : range(height)) { + const auto input = (const uint32_t*)data + y * (pitch >> 2); + png.dataLine(y == height - 1); + for(uint x : range(width)) { + auto pixel = input[x]; //ARGB + png.adler(pixel >> 16); //R + png.adler(pixel >> 8); //G + png.adler(pixel >> 0); //B + png.adler(pixel >> 24); //A + } + } + png.dataFooter(); + png.footer(); + png.close(); + png.compress(filename); + return true; +} + +inline auto PNG::compress(const string& filename) -> bool { + auto size = file::size(filename); + execute("optipng", "-o1", filename); + if(file::size(filename) < size) return true; + execute("pngcrush", "-ow", "-l", "1", filename); + if(file::size(filename) < size) return true; + return false; +} + +inline auto PNG::open(const string& filename) -> bool { + fp = file::open(filename, file::mode::write); + return (bool)fp; +} + +inline auto PNG::close() -> void { + fp.close(); +} + +inline auto PNG::header() -> void { + fp.write(0x89); + fp.write('P'); + fp.write('N'); + fp.write('G'); + fp.write(0x0d); + fp.write(0x0a); + fp.write(0x1a); + fp.write(0x0a); +} + +inline auto PNG::footer() -> void { + fp.writem(0, 4L); + crc32.reset(); + write('I'); + write('E'); + write('N'); + write('D'); + fp.writem(crc32.value(), 4L); +} + +inline auto PNG::information(uint width, uint height, uint depth, uint type) -> void { + fp.writem(13, 4L); + crc32.reset(); + write('I'); + write('H'); + write('D'); + write('R'); + write(width >> 24); + write(width >> 16); + write(width >> 8); + write(width >> 0); + write(height >> 24); + write(height >> 16); + write(height >> 8); + write(height >> 0); + write(depth); + write(type); + write(0x00); //no compression + write(0x00); //no filter + write(0x00); //no interlace + fp.writem(crc32.value(), 4L); +} + +inline auto PNG::dataHeader(uint width, uint height, uint bitsPerPixel) -> void { + bytesPerLine = 1 + width * (bitsPerPixel / 8); + uint idatSize = 2 + height * (5 + bytesPerLine) + 4; + fp.writem(idatSize, 4L); + crc32.reset(); + write('I'); + write('D'); + write('A'); + write('T'); + write(0x78); + write(0xda); +} + +inline auto PNG::dataLine(bool lastLine) -> void { + write(lastLine); + write( bytesPerLine >> 0); + write( bytesPerLine >> 8); + write(~bytesPerLine >> 0); + write(~bytesPerLine >> 8); + adler(0x00); //no filter +} + +inline auto PNG::dataFooter() -> void { + write(adler2 >> 8); + write(adler2 >> 0); + write(adler1 >> 8); + write(adler1 >> 0); + fp.writem(crc32.value(), 4L); +} + +inline auto PNG::write(uint8_t data) -> void { + fp.write(data); + crc32.input(data); +} + +inline auto PNG::adler(uint8_t data) -> void { + write(data); + adler1 = (adler1 + data ) % 65521; + adler2 = (adler2 + adler1) % 65521; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/rle.hpp b/roms/snes-test-roms/bass-untech/nall/encode/rle.hpp new file mode 100644 index 00000000..da88fff9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/rle.hpp @@ -0,0 +1,56 @@ +#pragma once + +namespace nall::Encode { + +template //S = word size; M = match length +inline auto RLE(array_view input) -> vector { + vector output; + for(uint byte : range(8)) output.append(input.size() >> byte * 8); + + uint base = 0; + uint skip = 0; + + auto load = [&](uint offset) -> uint8_t { + return input(offset); + }; + + auto read = [&](uint offset) -> uint64_t { + uint64_t value = 0; + for(uint byte : range(S)) value |= load(offset + byte) << byte * 8; + return value; + }; + + auto write = [&](uint64_t value) -> void { + for(uint byte : range(S)) output.append(value >> byte * 8); + }; + + auto flush = [&] { + output.append(skip - 1); + do { + write(read(base)); + base += S; + } while(--skip); + }; + + while(base + S * skip < input.size()) { + uint same = 1; + for(uint offset = base + S * (skip + 1); offset < input.size(); offset += S) { + if(read(offset) != read(base + S * skip)) break; + if(++same == 127 + M) break; + } + + if(same < M) { + if(++skip == 128) flush(); + } else { + if(skip) flush(); + output.append(128 | same - M); + write(read(base)); + base += S * same; + } + } + if(skip) flush(); + + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/url.hpp b/roms/snes-test-roms/bass-untech/nall/encode/url.hpp new file mode 100644 index 00000000..1f422e5d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/url.hpp @@ -0,0 +1,27 @@ +#pragma once + +namespace nall::Encode { + +inline auto URL(string_view input) -> string { + string output; + for(auto c : input) { + //unreserved characters + if(c >= 'A' && c <= 'Z') { output.append(c); continue; } + if(c >= 'a' && c <= 'z') { output.append(c); continue; } + if(c >= '0' && c <= '9') { output.append(c); continue; } + if(c == '-' || c == '_' || c == '.' || c == '~') { output.append(c); continue; } + + //special characters + if(c == ' ') { output.append('+'); continue; } + + //reserved characters + uint hi = (c >> 4) & 15; + uint lo = (c >> 0) & 15; + output.append('%'); + output.append((char)(hi < 10 ? ('0' + hi) : ('a' + hi - 10))); + output.append((char)(lo < 10 ? ('0' + lo) : ('a' + lo - 10))); + } + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/wav.hpp b/roms/snes-test-roms/bass-untech/nall/encode/wav.hpp new file mode 100644 index 00000000..1b424855 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/wav.hpp @@ -0,0 +1,52 @@ +#pragma once + +namespace nall::Encode { + +struct WAV { + static auto stereo_16bit(const string& filename, array_view left, array_view right, uint frequency) -> bool { + if(left.size() != right.size()) return false; + static uint channels = 2; + static uint bits = 16; + static uint samples = left.size(); + + file_buffer fp; + if(!fp.open(filename, file::mode::write)) return false; + + fp.write('R'); + fp.write('I'); + fp.write('F'); + fp.write('F'); + fp.writel(4 + (8 + 16) + (8 + samples * 4), 4); + + fp.write('W'); + fp.write('A'); + fp.write('V'); + fp.write('E'); + + fp.write('f'); + fp.write('m'); + fp.write('t'); + fp.write(' '); + fp.writel(16, 4); + fp.writel(1, 2); + fp.writel(channels, 2); + fp.writel(frequency, 4); + fp.writel(frequency * channels * bits, 4); + fp.writel(channels * bits, 2); + fp.writel(bits, 2); + + fp.write('d'); + fp.write('a'); + fp.write('t'); + fp.write('a'); + fp.writel(samples * 4, 4); + for(uint sample : range(samples)) { + fp.writel(left[sample], 2); + fp.writel(right[sample], 2); + } + + return true; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/encode/zip.hpp b/roms/snes-test-roms/bass-untech/nall/encode/zip.hpp new file mode 100644 index 00000000..b98376d7 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/encode/zip.hpp @@ -0,0 +1,101 @@ +#pragma once + +//creates uncompressed ZIP archives + +#include +#include + +namespace nall::Encode { + +struct ZIP { + ZIP(const string& filename) { + fp.open(filename, file::mode::write); + timestamp = time(nullptr); + } + + //append path: append("path/"); + //append file: append("path/file", data, size); + auto append(string filename, const uint8_t* data = nullptr, uint size = 0u, time_t timestamp = 0) -> void { + filename.transform("\\", "/"); + if(!timestamp) timestamp = this->timestamp; + uint32_t checksum = Hash::CRC32({data, size}).digest().hex(); + directory.append({filename, timestamp, checksum, size, (uint32_t)fp.offset()}); + + fp.writel(0x04034b50, 4); //signature + fp.writel(0x0014, 2); //minimum version (2.0) + fp.writel(0x0000, 2); //general purpose bit flags + fp.writel(0x0000, 2); //compression method (0 = uncompressed) + fp.writel(makeTime(timestamp), 2); + fp.writel(makeDate(timestamp), 2); + fp.writel(checksum, 4); + fp.writel(size, 4); //compressed size + fp.writel(size, 4); //uncompressed size + fp.writel(filename.length(), 2); //file name length + fp.writel(0x0000, 2); //extra field length + fp.print(filename); //file name + + fp.write({data, size}); //file data + } + + ~ZIP() { + //central directory + uint baseOffset = fp.offset(); + for(auto& entry : directory) { + fp.writel(0x02014b50, 4); //signature + fp.writel(0x0014, 2); //version made by (2.0) + fp.writel(0x0014, 2); //version needed to extract (2.0) + fp.writel(0x0000, 2); //general purpose bit flags + fp.writel(0x0000, 2); //compression method (0 = uncompressed) + fp.writel(makeTime(entry.timestamp), 2); + fp.writel(makeDate(entry.timestamp), 2); + fp.writel(entry.checksum, 4); + fp.writel(entry.size, 4); //compressed size + fp.writel(entry.size, 4); //uncompressed size + fp.writel(entry.filename.length(), 2); //file name length + fp.writel(0x0000, 2); //extra field length + fp.writel(0x0000, 2); //file comment length + fp.writel(0x0000, 2); //disk number start + fp.writel(0x0000, 2); //internal file attributes + fp.writel(0x00000000, 4); //external file attributes + fp.writel(entry.offset, 4); //relative offset of file header + fp.print(entry.filename); + } + uint finishOffset = fp.offset(); + + //end of central directory + fp.writel(0x06054b50, 4); //signature + fp.writel(0x0000, 2); //number of this disk + fp.writel(0x0000, 2); //disk where central directory starts + fp.writel(directory.size(), 2); //number of central directory records on this disk + fp.writel(directory.size(), 2); //total number of central directory records + fp.writel(finishOffset - baseOffset, 4); //size of central directory + fp.writel(baseOffset, 4); //offset of central directory + fp.writel(0x0000, 2); //comment length + + fp.close(); + } + +protected: + auto makeTime(time_t timestamp) -> uint16_t { + tm* info = localtime(×tamp); + return (info->tm_hour << 11) | (info->tm_min << 5) | (info->tm_sec >> 1); + } + + auto makeDate(time_t timestamp) -> uint16_t { + tm* info = localtime(×tamp); + return ((info->tm_year - 80) << 9) | ((1 + info->tm_mon) << 5) + (info->tm_mday); + } + + file_buffer fp; + time_t timestamp; + struct entry_t { + string filename; + time_t timestamp; + uint32_t checksum; + uint32_t size; + uint32_t offset; + }; + vector directory; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/endian.hpp b/roms/snes-test-roms/bass-untech/nall/endian.hpp new file mode 100644 index 00000000..7a01b9a1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/endian.hpp @@ -0,0 +1,43 @@ +#pragma once + +#include + +#if defined(ENDIAN_LSB) + //little-endian: uint8_t[] { 0x01, 0x02, 0x03, 0x04 } == 0x04030201 + #define order_lsb1(a) a + #define order_lsb2(a,b) a,b + #define order_lsb3(a,b,c) a,b,c + #define order_lsb4(a,b,c,d) a,b,c,d + #define order_lsb5(a,b,c,d,e) a,b,c,d,e + #define order_lsb6(a,b,c,d,e,f) a,b,c,d,e,f + #define order_lsb7(a,b,c,d,e,f,g) a,b,c,d,e,f,g + #define order_lsb8(a,b,c,d,e,f,g,h) a,b,c,d,e,f,g,h + #define order_msb1(a) a + #define order_msb2(a,b) b,a + #define order_msb3(a,b,c) c,b,a + #define order_msb4(a,b,c,d) d,c,b,a + #define order_msb5(a,b,c,d,e) e,d,c,b,a + #define order_msb6(a,b,c,d,e,f) f,e,d,c,b,a + #define order_msb7(a,b,c,d,e,f,g) g,f,e,d,c,b,a + #define order_msb8(a,b,c,d,e,f,g,h) h,g,f,e,d,c,b,a +#elif defined(ENDIAN_MSB) + //big-endian: uint8_t[] { 0x01, 0x02, 0x03, 0x04 } == 0x01020304 + #define order_lsb1(a) a + #define order_lsb2(a,b) b,a + #define order_lsb3(a,b,c) c,b,a + #define order_lsb4(a,b,c,d) d,c,b,a + #define order_lsb5(a,b,c,d,e) e,d,c,b,a + #define order_lsb6(a,b,c,d,e,f) f,e,d,c,b,a + #define order_lsb7(a,b,c,d,e,f,g) g,f,e,d,c,b,a + #define order_lsb8(a,b,c,d,e,f,g,h) h,g,f,e,d,c,b,a + #define order_msb1(a) a + #define order_msb2(a,b) a,b + #define order_msb3(a,b,c) a,b,c + #define order_msb4(a,b,c,d) a,b,c,d + #define order_msb5(a,b,c,d,e) a,b,c,d,e + #define order_msb6(a,b,c,d,e,f) a,b,c,d,e,f + #define order_msb7(a,b,c,d,e,f,g) a,b,c,d,e,f,g + #define order_msb8(a,b,c,d,e,f,g,h) a,b,c,d,e,f,g,h +#else + #error "Unknown endian. Please specify in nall/intrinsics.hpp" +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/file-buffer.hpp b/roms/snes-test-roms/bass-untech/nall/file-buffer.hpp new file mode 100644 index 00000000..1ee6b528 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/file-buffer.hpp @@ -0,0 +1,248 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nall { + +//on Windows (at least for 7 and earlier), FILE* is not buffered +//thus, reading/writing one byte at a time will be dramatically slower +//on all other OSes, FILE* is buffered +//in order to ensure good performance, file_buffer implements its own buffer +//this speeds up Windows substantially, without harming performance elsewhere much + +struct file_buffer { + struct mode { enum : uint { read, write, modify, append }; }; + struct index { enum : uint { absolute, relative }; }; + + file_buffer(const file_buffer&) = delete; + auto operator=(const file_buffer&) -> file_buffer& = delete; + + file_buffer() = default; + file_buffer(const string& filename, uint mode) { open(filename, mode); } + + file_buffer(file_buffer&& source) { operator=(move(source)); } + + ~file_buffer() { close(); } + + auto operator=(file_buffer&& source) -> file_buffer& { + buffer = source.buffer; + bufferOffset = source.bufferOffset; + bufferDirty = source.bufferDirty; + fileHandle = source.fileHandle; + fileOffset = source.fileOffset; + fileSize = source.fileSize; + fileMode = source.fileMode; + + source.bufferOffset = -1; + source.bufferDirty = false; + source.fileHandle = nullptr; + source.fileOffset = 0; + source.fileSize = 0; + source.fileMode = mode::read; + + return *this; + } + + explicit operator bool() const { + return (bool)fileHandle; + } + + auto read() -> uint8_t { + if(!fileHandle) return 0; //file not open + if(fileOffset >= fileSize) return 0; //cannot read past end of file + bufferSynchronize(); + return buffer[fileOffset++ & buffer.size() - 1]; + } + + template auto readl(uint length = 1) -> T { + T data = 0; + for(uint n : range(length)) { + data |= (T)read() << n * 8; + } + return data; + } + + template auto readm(uint length = 1) -> T { + T data = 0; + while(length--) { + data <<= 8; + data |= read(); + } + return data; + } + + auto reads(uint length) -> string { + string result; + result.resize(length); + for(auto& byte : result) byte = read(); + return result; + } + + auto read(array_span memory) -> void { + for(auto& byte : memory) byte = read(); + } + + auto write(uint8_t data) -> void { + if(!fileHandle) return; //file not open + if(fileMode == mode::read) return; //writes not permitted + bufferSynchronize(); + buffer[fileOffset++ & buffer.size() - 1] = data; + bufferDirty = true; + if(fileOffset > fileSize) fileSize = fileOffset; + } + + template auto writel(T data, uint length = 1) -> void { + while(length--) { + write(uint8_t(data)); + data >>= 8; + } + } + + template auto writem(T data, uint length = 1) -> void { + for(uint n : reverse(range(length))) { + write(uint8_t(data >> n * 8)); + } + } + + auto writes(const string& s) -> void { + for(auto& byte : s) write(byte); + } + + auto write(array_view memory) -> void { + for(auto& byte : memory) write(byte); + } + + template auto print(P&&... p) -> void { + string s{forward

(p)...}; + for(auto& byte : s) write(byte); + } + + auto flush() -> void { + bufferFlush(); + fflush(fileHandle); + } + + auto seek(int64_t offset, uint index_ = index::absolute) -> void { + if(!fileHandle) return; + bufferFlush(); + + int64_t seekOffset = fileOffset; + switch(index_) { + case index::absolute: seekOffset = offset; break; + case index::relative: seekOffset += offset; break; + } + + if(seekOffset < 0) seekOffset = 0; //cannot seek before start of file + if(seekOffset > fileSize) { + if(fileMode == mode::read) { //cannot seek past end of file + seekOffset = fileSize; + } else { //pad file to requested location + fileOffset = fileSize; + while(fileSize < seekOffset) write(0); + } + } + + fileOffset = seekOffset; + } + + auto offset() const -> uint64_t { + if(!fileHandle) return 0; + return fileOffset; + } + + auto size() const -> uint64_t { + if(!fileHandle) return 0; + return fileSize; + } + + auto truncate(uint64_t size) -> bool { + if(!fileHandle) return false; + #if defined(API_POSIX) + return ftruncate(fileno(fileHandle), size) == 0; + #elif defined(API_WINDOWS) + return _chsize(fileno(fileHandle), size) == 0; + #endif + } + + auto end() const -> bool { + if(!fileHandle) return true; + return fileOffset >= fileSize; + } + + auto open(const string& filename, uint mode_) -> bool { + close(); + + switch(fileMode = mode_) { + #if defined(API_POSIX) + case mode::read: fileHandle = fopen(filename, "rb" ); break; + case mode::write: fileHandle = fopen(filename, "wb+"); break; //need read permission for buffering + case mode::modify: fileHandle = fopen(filename, "rb+"); break; + case mode::append: fileHandle = fopen(filename, "wb+"); break; + #elif defined(API_WINDOWS) + case mode::read: fileHandle = _wfopen(utf16_t(filename), L"rb" ); break; + case mode::write: fileHandle = _wfopen(utf16_t(filename), L"wb+"); break; + case mode::modify: fileHandle = _wfopen(utf16_t(filename), L"rb+"); break; + case mode::append: fileHandle = _wfopen(utf16_t(filename), L"wb+"); break; + #endif + } + if(!fileHandle) return false; + + bufferOffset = -1; + fileOffset = 0; + fseek(fileHandle, 0, SEEK_END); + fileSize = ftell(fileHandle); + fseek(fileHandle, 0, SEEK_SET); + return true; + } + + auto close() -> void { + if(!fileHandle) return; + bufferFlush(); + fclose(fileHandle); + fileHandle = nullptr; + } + +private: + array buffer; + int bufferOffset = -1; + bool bufferDirty = false; + FILE* fileHandle = nullptr; + uint64_t fileOffset = 0; + uint64_t fileSize = 0; + uint fileMode = mode::read; + + auto bufferSynchronize() -> void { + if(!fileHandle) return; + if(bufferOffset == (fileOffset & ~(buffer.size() - 1))) return; + + bufferFlush(); + bufferOffset = fileOffset & ~(buffer.size() - 1); + fseek(fileHandle, bufferOffset, SEEK_SET); + uint64_t length = bufferOffset + buffer.size() <= fileSize ? buffer.size() : fileSize & buffer.size() - 1; + if(length) (void)fread(buffer.data(), 1, length, fileHandle); + } + + auto bufferFlush() -> void { + if(!fileHandle) return; //file not open + if(fileMode == mode::read) return; //buffer cannot be written to + if(bufferOffset < 0) return; //buffer unused + if(!bufferDirty) return; //buffer unmodified since read + + fseek(fileHandle, bufferOffset, SEEK_SET); + uint64_t length = bufferOffset + buffer.size() <= fileSize ? buffer.size() : fileSize & buffer.size() - 1; + if(length) (void)fwrite(buffer.data(), 1, length, fileHandle); + bufferOffset = -1; + bufferDirty = false; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/file-map.hpp b/roms/snes-test-roms/bass-untech/nall/file-map.hpp new file mode 100644 index 00000000..647a823b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/file-map.hpp @@ -0,0 +1,225 @@ +#pragma once + +#include +#include + +#include +#include +#if defined(PLATFORM_WINDOWS) + #include +#else + #include + #include + #include + #include + #include +#endif + +#if !defined(MAP_NORESERVE) + //not supported on FreeBSD; flag removed in 11.0 + #define MAP_NORESERVE 0 +#endif + +namespace nall { + +struct file_map { + struct mode { enum : uint { read, write, modify, append }; }; + + file_map(const file_map&) = delete; + auto operator=(const file_map&) = delete; + + file_map() = default; + file_map(file_map&& source) { operator=(move(source)); } + file_map(const string& filename, uint mode) { open(filename, mode); } + + ~file_map() { close(); } + + explicit operator bool() const { return _open; } + auto size() const -> uint64_t { return _size; } + auto data() -> uint8_t* { return _data; } + auto data() const -> const uint8_t* { return _data; } + +//auto operator=(file_map&& source) -> file_map&; +//auto open(const string& filename, uint mode) -> bool; +//auto close() -> void; + +private: + bool _open = false; //zero-byte files return _data = nullptr, _size = 0 + uint8_t* _data = nullptr; + uint64_t _size = 0; + + #if defined(API_WINDOWS) + + HANDLE _file = INVALID_HANDLE_VALUE; + HANDLE _map = INVALID_HANDLE_VALUE; + +public: + auto operator=(file_map&& source) -> file_map& { + _open = source._open; + _data = source._data; + _size = source._size; + _file = source._file; + _map = source._map; + + source._open = false; + source._data = nullptr; + source._size = 0; + source._file = INVALID_HANDLE_VALUE; + source._map = INVALID_HANDLE_VALUE; + + return *this; + } + + auto open(const string& filename, uint mode_) -> bool { + close(); + if(file::exists(filename) && file::size(filename) == 0) return _open = true; + + int desiredAccess, creationDisposition, protection, mapAccess; + + switch(mode_) { + default: return false; + case mode::read: + desiredAccess = GENERIC_READ; + creationDisposition = OPEN_EXISTING; + protection = PAGE_READONLY; + mapAccess = FILE_MAP_READ; + break; + case mode::write: + //write access requires read access + desiredAccess = GENERIC_WRITE; + creationDisposition = CREATE_ALWAYS; + protection = PAGE_READWRITE; + mapAccess = FILE_MAP_ALL_ACCESS; + break; + case mode::modify: + desiredAccess = GENERIC_READ | GENERIC_WRITE; + creationDisposition = OPEN_EXISTING; + protection = PAGE_READWRITE; + mapAccess = FILE_MAP_ALL_ACCESS; + break; + case mode::append: + desiredAccess = GENERIC_READ | GENERIC_WRITE; + creationDisposition = CREATE_NEW; + protection = PAGE_READWRITE; + mapAccess = FILE_MAP_ALL_ACCESS; + break; + } + + _file = CreateFileW(utf16_t(filename), desiredAccess, FILE_SHARE_READ, nullptr, + creationDisposition, FILE_ATTRIBUTE_NORMAL, nullptr); + if(_file == INVALID_HANDLE_VALUE) return false; + + _size = GetFileSize(_file, nullptr); + + _map = CreateFileMapping(_file, nullptr, protection, 0, _size, nullptr); + if(_map == INVALID_HANDLE_VALUE) { + CloseHandle(_file); + _file = INVALID_HANDLE_VALUE; + return false; + } + + _data = (uint8_t*)MapViewOfFile(_map, mapAccess, 0, 0, _size); + return _open = true; + } + + auto close() -> void { + if(_data) { + UnmapViewOfFile(_data); + _data = nullptr; + } + + if(_map != INVALID_HANDLE_VALUE) { + CloseHandle(_map); + _map = INVALID_HANDLE_VALUE; + } + + if(_file != INVALID_HANDLE_VALUE) { + CloseHandle(_file); + _file = INVALID_HANDLE_VALUE; + } + + _open = false; + } + + #else + + int _fd = -1; + +public: + auto operator=(file_map&& source) -> file_map& { + _open = source._open; + _data = source._data; + _size = source._size; + _fd = source._fd; + + source._open = false; + source._data = nullptr; + source._size = 0; + source._fd = -1; + + return *this; + } + + auto open(const string& filename, uint mode_) -> bool { + close(); + if(file::exists(filename) && file::size(filename) == 0) return _open = true; + + int openFlags = 0; + int mmapFlags = 0; + + switch(mode_) { + default: return false; + case mode::read: + openFlags = O_RDONLY; + mmapFlags = PROT_READ; + break; + case mode::write: + openFlags = O_RDWR | O_CREAT; //mmap() requires read access + mmapFlags = PROT_WRITE; + break; + case mode::modify: + openFlags = O_RDWR; + mmapFlags = PROT_READ | PROT_WRITE; + break; + case mode::append: + openFlags = O_RDWR | O_CREAT; + mmapFlags = PROT_READ | PROT_WRITE; + break; + } + + _fd = ::open(filename, openFlags, S_IRUSR | S_IWUSR | S_IRGRP | S_IWGRP); + if(_fd < 0) return false; + + struct stat _stat; + fstat(_fd, &_stat); + _size = _stat.st_size; + + _data = (uint8_t*)mmap(nullptr, _size, mmapFlags, MAP_SHARED | MAP_NORESERVE, _fd, 0); + if(_data == MAP_FAILED) { + _data = nullptr; + ::close(_fd); + _fd = -1; + return false; + } + + return _open = true; + } + + auto close() -> void { + if(_data) { + munmap(_data, _size); + _data = nullptr; + } + + if(_fd >= 0) { + ::close(_fd); + _fd = -1; + } + + _open = false; + } + + #endif +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/file.hpp b/roms/snes-test-roms/bass-untech/nall/file.hpp new file mode 100644 index 00000000..307952f0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/file.hpp @@ -0,0 +1,104 @@ +#pragma once + +#include + +namespace nall { + +struct file : inode { + struct mode { enum : uint { read, write, modify, append }; }; + struct index { enum : uint { absolute, relative }; }; + + file() = delete; + + static auto open(const string& filename, uint mode) -> file_buffer { + return file_buffer{filename, mode}; + } + + static auto copy(const string& sourcename, const string& targetname) -> bool { + if(sourcename == targetname) return true; + if(auto reader = file::open(sourcename, mode::read)) { + if(auto writer = file::open(targetname, mode::write)) { + for(uint64_t n : range(reader.size())) writer.write(reader.read()); + return true; + } + } + return false; + } + + //attempt to rename file first + //this will fail if paths point to different file systems; fall back to copy+remove in this case + static auto move(const string& sourcename, const string& targetname) -> bool { + if(sourcename == targetname) return true; + if(rename(sourcename, targetname)) return true; + if(!writable(sourcename)) return false; + if(copy(sourcename, targetname)) return remove(sourcename), true; + return false; + } + + static auto truncate(const string& filename, uint64_t size) -> bool { + #if defined(API_POSIX) + return ::truncate(filename, size) == 0; + #elif defined(API_WINDOWS) + if(auto fp = _wfopen(utf16_t(filename), L"rb+")) { + bool result = _chsize(fileno(fp), size) == 0; + fclose(fp); + return result; + } + return false; + #endif + } + + //returns false if specified filename is a directory + static auto exists(const string& filename) -> bool { + #if defined(API_POSIX) + struct stat data; + if(stat(filename, &data) != 0) return false; + #elif defined(API_WINDOWS) + struct __stat64 data; + if(_wstat64(utf16_t(filename), &data) != 0) return false; + #endif + return !(data.st_mode & S_IFDIR); + } + + static auto size(const string& filename) -> uint64_t { + #if defined(API_POSIX) + struct stat data; + stat(filename, &data); + #elif defined(API_WINDOWS) + struct __stat64 data; + _wstat64(utf16_t(filename), &data); + #endif + return S_ISREG(data.st_mode) ? data.st_size : 0u; + } + + static auto read(const string& filename) -> vector { + vector memory; + if(auto fp = file::open(filename, mode::read)) { + memory.resize(fp.size()); + fp.read(memory); + } + return memory; + } + + static auto read(const string& filename, array_span memory) -> bool { + if(auto fp = file::open(filename, mode::read)) return fp.read(memory), true; + return false; + } + + static auto write(const string& filename, array_view memory) -> bool { + if(auto fp = file::open(filename, mode::write)) return fp.write(memory), true; + return false; + } + + //create an empty file (will replace existing files) + static auto create(const string& filename) -> bool { + if(auto fp = file::open(filename, mode::write)) return true; + return false; + } + + static auto sha256(const string& filename) -> string { + return Hash::SHA256(read(filename)).digest(); + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/function.hpp b/roms/snes-test-roms/bass-untech/nall/function.hpp new file mode 100644 index 00000000..3b59e05c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/function.hpp @@ -0,0 +1,78 @@ +#pragma once + +#include + +namespace nall { + +template struct function; + +template struct function R> { + using cast = auto (*)(P...) -> R; + + //value = true if auto L::operator()(P...) -> R exists + template struct is_compatible { + template static auto exists(T*) -> const typename is_same().operator()(declval

()...))>::type; + template static auto exists(...) -> const false_type; + static constexpr bool value = decltype(exists(0))::value; + }; + + function() {} + function(const function& source) { operator=(source); } + function(auto (*function)(P...) -> R) { callback = new global(function); } + template function(auto (C::*function)(P...) -> R, C* object) { callback = new member(function, object); } + template function(auto (C::*function)(P...) const -> R, C* object) { callback = new member((auto (C::*)(P...) -> R)function, object); } + template::value>> function(const L& object) { callback = new lambda(object); } + explicit function(void* function) { if(function) callback = new global((auto (*)(P...) -> R)function); } + ~function() { if(callback) delete callback; } + + explicit operator bool() const { return callback; } + auto operator()(P... p) const -> R { return (*callback)(forward

(p)...); } + auto reset() -> void { if(callback) { delete callback; callback = nullptr; } } + + auto operator=(const function& source) -> function& { + if(this != &source) { + if(callback) { delete callback; callback = nullptr; } + if(source.callback) callback = source.callback->copy(); + } + return *this; + } + + auto operator=(void* source) -> function& { + if(callback) { delete callback; callback = nullptr; } + callback = new global((auto (*)(P...) -> R)source); + return *this; + } + +private: + struct container { + virtual auto operator()(P... p) const -> R = 0; + virtual auto copy() const -> container* = 0; + virtual ~container() = default; + }; + + container* callback = nullptr; + + struct global : container { + auto (*function)(P...) -> R; + auto operator()(P... p) const -> R { return function(forward

(p)...); } + auto copy() const -> container* { return new global(function); } + global(auto (*function)(P...) -> R) : function(function) {} + }; + + template struct member : container { + auto (C::*function)(P...) -> R; + C* object; + auto operator()(P... p) const -> R { return (object->*function)(forward

(p)...); } + auto copy() const -> container* { return new member(function, object); } + member(auto (C::*function)(P...) -> R, C* object) : function(function), object(object) {} + }; + + template struct lambda : container { + mutable L object; + auto operator()(P... p) const -> R { return object(forward

(p)...); } + auto copy() const -> container* { return new lambda(object); } + lambda(const L& object) : object(object) {} + }; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/galois-field.hpp b/roms/snes-test-roms/bass-untech/nall/galois-field.hpp new file mode 100644 index 00000000..38f22697 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/galois-field.hpp @@ -0,0 +1,70 @@ +#pragma once + +//table-driven galois field modulo 2 +//do not use with GF(2^17) or larger + +namespace nall { + +template +struct GaloisField { + using type = GaloisField; + + GaloisField(uint x = 0) : x(x) {} + operator field() const { return x; } + + auto operator^(field y) const -> type { return x ^ y; } + auto operator+(field y) const -> type { return x ^ y; } + auto operator-(field y) const -> type { return x ^ y; } + auto operator*(field y) const -> type { return x && y ? exp(log(x) + log(y)) : 0; } + auto operator/(field y) const -> type { return x && y ? exp(log(x) + Elements - log(y)) : 0; } + + auto& operator =(field y) { return x = y, *this; } + auto& operator^=(field y) { return x = operator^(y), *this; } + auto& operator+=(field y) { return x = operator^(y), *this; } + auto& operator-=(field y) { return x = operator^(y), *this; } + auto& operator*=(field y) { return x = operator*(y), *this; } + auto& operator/=(field y) { return x = operator/(y), *this; } + + auto pow(field y) const -> type { return exp(log(x) * y); } + auto inv() const -> type { return exp(Elements - log(x)); } // 1/x + + static auto log(uint x) -> uint { + enum : uint { Size = bit::round(Elements), Mask = Size - 1 }; + static array log = [] { + uint shift = 0, polynomial = Polynomial; + while(polynomial >>= 1) shift++; + shift--; + + array log; + field x = 1; + for(uint n : range(Elements)) { + log[x] = n; + x = x << 1 ^ (x >> shift ? Polynomial : 0); + } + log[0] = 0; //-inf (undefined) + return log; + }(); + return log[x & Mask]; + } + + static auto exp(uint x) -> uint { + static array exp = [] { + uint shift = 0, polynomial = Polynomial; + while(polynomial >>= 1) shift++; + shift--; + + array exp; + field x = 1; + for(uint n : range(Elements)) { + exp[n] = x; + x = x << 1 ^ (x >> shift ? Polynomial : 0); + } + return exp; + }(); + return exp[x % Elements]; + } + + field x; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/crc16.hpp b/roms/snes-test-roms/bass-untech/nall/hash/crc16.hpp new file mode 100644 index 00000000..8058a40b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/crc16.hpp @@ -0,0 +1,55 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct CRC16 : Hash { + using Hash::input; + + CRC16(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + checksum = ~0; + } + + auto input(uint8_t value) -> void override { + checksum = (checksum >> 8) ^ table(checksum ^ value); + } + + auto output() const -> vector override { + vector result; + for(auto n : reverse(range(2))) result.append(~checksum >> n * 8); + return result; + } + + auto value() const -> uint16_t { + return ~checksum; + } + +private: + static auto table(uint8_t index) -> uint16_t { + static uint16_t table[256] = {0}; + static bool initialized = false; + + if(!initialized) { + initialized = true; + for(auto index : range(256)) { + uint16_t crc = index; + for(auto bit : range(8)) { + crc = (crc >> 1) ^ (crc & 1 ? 0x8408 : 0); + } + table[index] = crc; + } + } + + return table[index]; + } + + uint16_t checksum = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/crc32.hpp b/roms/snes-test-roms/bass-untech/nall/hash/crc32.hpp new file mode 100644 index 00000000..39318713 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/crc32.hpp @@ -0,0 +1,55 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct CRC32 : Hash { + using Hash::input; + + CRC32(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + checksum = ~0; + } + + auto input(uint8_t value) -> void override { + checksum = (checksum >> 8) ^ table(checksum ^ value); + } + + auto output() const -> vector { + vector result; + for(auto n : reverse(range(4))) result.append(~checksum >> n * 8); + return result; + } + + auto value() const -> uint32_t { + return ~checksum; + } + +private: + static auto table(uint8_t index) -> uint32_t { + static uint32_t table[256] = {0}; + static bool initialized = false; + + if(!initialized) { + initialized = true; + for(auto index : range(256)) { + uint32_t crc = index; + for(auto bit : range(8)) { + crc = (crc >> 1) ^ (crc & 1 ? 0xedb8'8320 : 0); + } + table[index] = crc; + } + } + + return table[index]; + } + + uint32_t checksum = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/crc64.hpp b/roms/snes-test-roms/bass-untech/nall/hash/crc64.hpp new file mode 100644 index 00000000..7364b0d8 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/crc64.hpp @@ -0,0 +1,55 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct CRC64 : Hash { + using Hash::input; + + CRC64(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + checksum = ~0; + } + + auto input(uint8_t value) -> void override { + checksum = (checksum >> 8) ^ table(checksum ^ value); + } + + auto output() const -> vector { + vector result; + for(auto n : reverse(range(8))) result.append(~checksum >> n * 8); + return result; + } + + auto value() const -> uint64_t { + return ~checksum; + } + +private: + static auto table(uint8_t index) -> uint64_t { + static uint64_t table[256] = {0}; + static bool initialized = false; + + if(!initialized) { + initialized = true; + for(auto index : range(256)) { + uint64_t crc = index; + for(auto bit : range(8)) { + crc = (crc >> 1) ^ (crc & 1 ? 0xc96c'5795'd787'0f42 : 0); + } + table[index] = crc; + } + } + + return table[index]; + } + + uint64_t checksum = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/hash.hpp b/roms/snes-test-roms/bass-untech/nall/hash/hash.hpp new file mode 100644 index 00000000..4565fe3d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/hash.hpp @@ -0,0 +1,47 @@ +#pragma once + +#include +#include +#include + +//cannot use constructor inheritance due to needing to call virtual reset(); +//instead, define a macro to reduce boilerplate code in every Hash subclass +#define nallHash(Name) \ + Name() { reset(); } \ + Name(const void* data, uint64_t size) : Name() { input(data, size); } \ + Name(const vector& data) : Name() { input(data); } \ + Name(const string& data) : Name() { input(data); } \ + using Hash::input; \ + +namespace nall::Hash { + +struct Hash { + virtual auto reset() -> void = 0; + virtual auto input(uint8_t data) -> void = 0; + virtual auto output() const -> vector = 0; + + auto input(array_view data) -> void { + for(auto byte : data) input(byte); + } + + auto input(const void* data, uint64_t size) -> void { + auto p = (const uint8_t*)data; + while(size--) input(*p++); + } + + auto input(const vector& data) -> void { + for(auto byte : data) input(byte); + } + + auto input(const string& data) -> void { + for(auto byte : data) input(byte); + } + + auto digest() const -> string { + string result; + for(auto n : output()) result.append(hex(n, 2L)); + return result; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/sha224.hpp b/roms/snes-test-roms/bass-untech/nall/hash/sha224.hpp new file mode 100644 index 00000000..6bcf7858 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/sha224.hpp @@ -0,0 +1,106 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct SHA224 : Hash { + using Hash::input; + + SHA224(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + for(auto& n : queue) n = 0; + for(auto& n : w) n = 0; + for(auto n : range(8)) h[n] = square(n); + queued = length = 0; + } + + auto input(uint8_t value) -> void override { + byte(value); + length++; + } + + auto output() const -> vector override { + SHA224 self(*this); + self.finish(); + vector result; + for(auto h : range(7)) { + for(auto n : reverse(range(4))) result.append(self.h[h] >> n * 8); + } + return result; + } + + auto value() const -> uint256_t { + uint256_t value = 0; + for(auto byte : output()) value = value << 8 | byte; + return value; + } + +private: + auto byte(uint8_t value) -> void { + uint32_t shift = (3 - (queued & 3)) * 8; + queue[queued >> 2] &= ~(0xff << shift); + queue[queued >> 2] |= (value << shift); + if(++queued == 64) block(), queued = 0; + } + + auto block() -> void { + for(auto n : range(16)) w[n] = queue[n]; + for(auto n : range(16, 64)) { + uint32_t a = ror(w[n - 15], 7) ^ ror(w[n - 15], 18) ^ (w[n - 15] >> 3); + uint32_t b = ror(w[n - 2], 17) ^ ror(w[n - 2], 19) ^ (w[n - 2] >> 10); + w[n] = w[n - 16] + w[n - 7] + a + b; + } + uint32_t t[8]; + for(auto n : range(8)) t[n] = h[n]; + for(auto n : range(64)) { + uint32_t a = ror(t[0], 2) ^ ror(t[0], 13) ^ ror(t[0], 22); + uint32_t b = ror(t[4], 6) ^ ror(t[4], 11) ^ ror(t[4], 25); + uint32_t c = (t[0] & t[1]) ^ (t[0] & t[2]) ^ (t[1] & t[2]); + uint32_t d = (t[4] & t[5]) ^ (~t[4] & t[6]); + uint32_t e = t[7] + w[n] + cube(n) + b + d; + t[7] = t[6]; t[6] = t[5]; t[5] = t[4]; t[4] = t[3] + e; + t[3] = t[2]; t[2] = t[1]; t[1] = t[0]; t[0] = a + c + e; + } + for(auto n : range(8)) h[n] += t[n]; + } + + auto finish() -> void { + byte(0x80); + while(queued != 56) byte(0x00); + for(auto n : range(8)) byte(length * 8 >> (7 - n) * 8); + } + + auto square(uint n) -> uint32_t { + static const uint32_t value[8] = { + 0xc1059ed8, 0x367cd507, 0x3070dd17, 0xf70e5939, 0xffc00b31, 0x68581511, 0x64f98fa7, 0xbefa4fa4, + }; + return value[n]; + } + + auto cube(uint n) -> uint32_t { + static const uint32_t value[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2, + }; + return value[n]; + } + + uint32_t queue[16] = {0}; + uint32_t w[64] = {0}; + uint32_t h[8] = {0}; + uint32_t queued = 0; + uint64_t length = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/sha256.hpp b/roms/snes-test-roms/bass-untech/nall/hash/sha256.hpp new file mode 100644 index 00000000..27f42a04 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/sha256.hpp @@ -0,0 +1,106 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct SHA256 : Hash { + using Hash::input; + + SHA256(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + for(auto& n : queue) n = 0; + for(auto& n : w) n = 0; + for(auto n : range(8)) h[n] = square(n); + queued = length = 0; + } + + auto input(uint8_t value) -> void override { + byte(value); + length++; + } + + auto output() const -> vector override { + SHA256 self(*this); + self.finish(); + vector result; + for(auto h : self.h) { + for(auto n : reverse(range(4))) result.append(h >> n * 8); + } + return result; + } + + auto value() const -> uint256_t { + uint256_t value = 0; + for(auto byte : output()) value = value << 8 | byte; + return value; + } + +private: + auto byte(uint8_t value) -> void { + uint32_t shift = (3 - (queued & 3)) * 8; + queue[queued >> 2] &= ~(0xff << shift); + queue[queued >> 2] |= (value << shift); + if(++queued == 64) block(), queued = 0; + } + + auto block() -> void { + for(auto n : range(16)) w[n] = queue[n]; + for(auto n : range(16, 64)) { + uint32_t a = ror(w[n - 15], 7) ^ ror(w[n - 15], 18) ^ (w[n - 15] >> 3); + uint32_t b = ror(w[n - 2], 17) ^ ror(w[n - 2], 19) ^ (w[n - 2] >> 10); + w[n] = w[n - 16] + w[n - 7] + a + b; + } + uint32_t t[8]; + for(auto n : range(8)) t[n] = h[n]; + for(auto n : range(64)) { + uint32_t a = ror(t[0], 2) ^ ror(t[0], 13) ^ ror(t[0], 22); + uint32_t b = ror(t[4], 6) ^ ror(t[4], 11) ^ ror(t[4], 25); + uint32_t c = (t[0] & t[1]) ^ (t[0] & t[2]) ^ (t[1] & t[2]); + uint32_t d = (t[4] & t[5]) ^ (~t[4] & t[6]); + uint32_t e = t[7] + w[n] + cube(n) + b + d; + t[7] = t[6]; t[6] = t[5]; t[5] = t[4]; t[4] = t[3] + e; + t[3] = t[2]; t[2] = t[1]; t[1] = t[0]; t[0] = a + c + e; + } + for(auto n : range(8)) h[n] += t[n]; + } + + auto finish() -> void { + byte(0x80); + while(queued != 56) byte(0x00); + for(auto n : range(8)) byte(length * 8 >> (7 - n) * 8); + } + + auto square(uint n) -> uint32_t { + static const uint32_t value[8] = { + 0x6a09e667, 0xbb67ae85, 0x3c6ef372, 0xa54ff53a, 0x510e527f, 0x9b05688c, 0x1f83d9ab, 0x5be0cd19, + }; + return value[n]; + } + + auto cube(uint n) -> uint32_t { + static const uint32_t value[64] = { + 0x428a2f98, 0x71374491, 0xb5c0fbcf, 0xe9b5dba5, 0x3956c25b, 0x59f111f1, 0x923f82a4, 0xab1c5ed5, + 0xd807aa98, 0x12835b01, 0x243185be, 0x550c7dc3, 0x72be5d74, 0x80deb1fe, 0x9bdc06a7, 0xc19bf174, + 0xe49b69c1, 0xefbe4786, 0x0fc19dc6, 0x240ca1cc, 0x2de92c6f, 0x4a7484aa, 0x5cb0a9dc, 0x76f988da, + 0x983e5152, 0xa831c66d, 0xb00327c8, 0xbf597fc7, 0xc6e00bf3, 0xd5a79147, 0x06ca6351, 0x14292967, + 0x27b70a85, 0x2e1b2138, 0x4d2c6dfc, 0x53380d13, 0x650a7354, 0x766a0abb, 0x81c2c92e, 0x92722c85, + 0xa2bfe8a1, 0xa81a664b, 0xc24b8b70, 0xc76c51a3, 0xd192e819, 0xd6990624, 0xf40e3585, 0x106aa070, + 0x19a4c116, 0x1e376c08, 0x2748774c, 0x34b0bcb5, 0x391c0cb3, 0x4ed8aa4a, 0x5b9cca4f, 0x682e6ff3, + 0x748f82ee, 0x78a5636f, 0x84c87814, 0x8cc70208, 0x90befffa, 0xa4506ceb, 0xbef9a3f7, 0xc67178f2, + }; + return value[n]; + } + + uint32_t queue[16] = {0}; + uint32_t w[64] = {0}; + uint32_t h[8] = {0}; + uint32_t queued = 0; + uint64_t length = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/sha384.hpp b/roms/snes-test-roms/bass-untech/nall/hash/sha384.hpp new file mode 100644 index 00000000..09dbbdb1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/sha384.hpp @@ -0,0 +1,119 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct SHA384 : Hash { + using Hash::input; + + SHA384(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + for(auto& n : queue) n = 0; + for(auto& n : w) n = 0; + for(auto n : range(8)) h[n] = square(n); + queued = length = 0; + } + + auto input(uint8_t data) -> void override { + byte(data); + length++; + } + + auto output() const -> vector override { + SHA384 self(*this); + self.finish(); + vector result; + for(auto h : range(6)) { + for(auto n : reverse(range(8))) result.append(self.h[h] >> n * 8); + } + return result; + } + + auto value() const -> uint512_t { + uint512_t value = 0; + for(auto byte : output()) value = value << 8 | byte; + return value; + } + +private: + auto byte(uint8_t data) -> void { + uint64_t shift = (7 - (queued & 7)) * 8; + queue[queued >> 3] &=~((uint64_t)0xff << shift); + queue[queued >> 3] |= ((uint64_t)data << shift); + if(++queued == 128) block(), queued = 0; + } + + auto block() -> void { + for(auto n : range(16)) w[n] = queue[n]; + for(auto n : range(16, 80)) { + uint64_t a = ror(w[n - 15], 1) ^ ror(w[n - 15], 8) ^ (w[n - 15] >> 7); + uint64_t b = ror(w[n - 2], 19) ^ ror(w[n - 2], 61) ^ (w[n - 2] >> 6); + w[n] = w[n - 16] + w[n - 7] + a + b; + } + uint64_t t[8]; + for(auto n : range(8)) t[n] = h[n]; + for(auto n : range(80)) { + uint64_t a = ror(t[0], 28) ^ ror(t[0], 34) ^ ror(t[0], 39); + uint64_t b = ror(t[4], 14) ^ ror(t[4], 18) ^ ror(t[4], 41); + uint64_t c = (t[0] & t[1]) ^ (t[0] & t[2]) ^ (t[1] & t[2]); + uint64_t d = (t[4] & t[5]) ^ (~t[4] & t[6]); + uint64_t e = t[7] + w[n] + cube(n) + b + d; + t[7] = t[6]; t[6] = t[5]; t[5] = t[4]; t[4] = t[3] + e; + t[3] = t[2]; t[2] = t[1]; t[1] = t[0]; t[0] = a + c + e; + } + for(auto n : range(8)) h[n] += t[n]; + } + + auto finish() -> void { + byte(0x80); + while(queued != 112) byte(0x00); + for(auto n : range(16)) byte(length * 8 >> (15 - n) * 8); + } + + auto square(uint n) -> uint64_t { + static const uint64_t data[8] = { + 0xcbbb9d5dc1059ed8, 0x629a292a367cd507, 0x9159015a3070dd17, 0x152fecd8f70e5939, + 0x67332667ffc00b31, 0x8eb44a8768581511, 0xdb0c2e0d64f98fa7, 0x47b5481dbefa4fa4, + }; + return data[n]; + } + + auto cube(uint n) -> uint64_t { + static const uint64_t data[80] = { + 0x428a2f98d728ae22, 0x7137449123ef65cd, 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc, + 0x3956c25bf348b538, 0x59f111f1b605d019, 0x923f82a4af194f9b, 0xab1c5ed5da6d8118, + 0xd807aa98a3030242, 0x12835b0145706fbe, 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2, + 0x72be5d74f27b896f, 0x80deb1fe3b1696b1, 0x9bdc06a725c71235, 0xc19bf174cf692694, + 0xe49b69c19ef14ad2, 0xefbe4786384f25e3, 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65, + 0x2de92c6f592b0275, 0x4a7484aa6ea6e483, 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5, + 0x983e5152ee66dfab, 0xa831c66d2db43210, 0xb00327c898fb213f, 0xbf597fc7beef0ee4, + 0xc6e00bf33da88fc2, 0xd5a79147930aa725, 0x06ca6351e003826f, 0x142929670a0e6e70, + 0x27b70a8546d22ffc, 0x2e1b21385c26c926, 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df, + 0x650a73548baf63de, 0x766a0abb3c77b2a8, 0x81c2c92e47edaee6, 0x92722c851482353b, + 0xa2bfe8a14cf10364, 0xa81a664bbc423001, 0xc24b8b70d0f89791, 0xc76c51a30654be30, + 0xd192e819d6ef5218, 0xd69906245565a910, 0xf40e35855771202a, 0x106aa07032bbd1b8, + 0x19a4c116b8d2d0c8, 0x1e376c085141ab53, 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8, + 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb, 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3, + 0x748f82ee5defb2fc, 0x78a5636f43172f60, 0x84c87814a1f0ab72, 0x8cc702081a6439ec, + 0x90befffa23631e28, 0xa4506cebde82bde9, 0xbef9a3f7b2c67915, 0xc67178f2e372532b, + 0xca273eceea26619c, 0xd186b8c721c0c207, 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178, + 0x06f067aa72176fba, 0x0a637dc5a2c898a6, 0x113f9804bef90dae, 0x1b710b35131c471b, + 0x28db77f523047d84, 0x32caab7b40c72493, 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c, + 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a, 0x5fcb6fab3ad6faec, 0x6c44198c4a475817, + }; + return data[n]; + } + + uint64_t queue[16] = {0}; + uint64_t w[80] = {0}; + uint64_t h[8] = {0}; + uint64_t queued = 0; + uint128_t length = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hash/sha512.hpp b/roms/snes-test-roms/bass-untech/nall/hash/sha512.hpp new file mode 100644 index 00000000..f76d2d52 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hash/sha512.hpp @@ -0,0 +1,119 @@ +#pragma once + +#include + +namespace nall::Hash { + +struct SHA512 : Hash { + using Hash::input; + + SHA512(array_view buffer = {}) { + reset(); + input(buffer); + } + + auto reset() -> void override { + for(auto& n : queue) n = 0; + for(auto& n : w) n = 0; + for(auto n : range(8)) h[n] = square(n); + queued = length = 0; + } + + auto input(uint8_t data) -> void override { + byte(data); + length++; + } + + auto output() const -> vector override { + SHA512 self(*this); + self.finish(); + vector result; + for(auto h : self.h) { + for(auto n : reverse(range(8))) result.append(h >> n * 8); + } + return result; + } + + auto value() const -> uint512_t { + uint512_t value = 0; + for(auto byte : output()) value = value << 8 | byte; + return value; + } + +private: + auto byte(uint8_t data) -> void { + uint64_t shift = (7 - (queued & 7)) * 8; + queue[queued >> 3] &=~((uint64_t)0xff << shift); + queue[queued >> 3] |= ((uint64_t)data << shift); + if(++queued == 128) block(), queued = 0; + } + + auto block() -> void { + for(auto n : range(16)) w[n] = queue[n]; + for(auto n : range(16, 80)) { + uint64_t a = ror(w[n - 15], 1) ^ ror(w[n - 15], 8) ^ (w[n - 15] >> 7); + uint64_t b = ror(w[n - 2], 19) ^ ror(w[n - 2], 61) ^ (w[n - 2] >> 6); + w[n] = w[n - 16] + w[n - 7] + a + b; + } + uint64_t t[8]; + for(auto n : range(8)) t[n] = h[n]; + for(auto n : range(80)) { + uint64_t a = ror(t[0], 28) ^ ror(t[0], 34) ^ ror(t[0], 39); + uint64_t b = ror(t[4], 14) ^ ror(t[4], 18) ^ ror(t[4], 41); + uint64_t c = (t[0] & t[1]) ^ (t[0] & t[2]) ^ (t[1] & t[2]); + uint64_t d = (t[4] & t[5]) ^ (~t[4] & t[6]); + uint64_t e = t[7] + w[n] + cube(n) + b + d; + t[7] = t[6]; t[6] = t[5]; t[5] = t[4]; t[4] = t[3] + e; + t[3] = t[2]; t[2] = t[1]; t[1] = t[0]; t[0] = a + c + e; + } + for(auto n : range(8)) h[n] += t[n]; + } + + auto finish() -> void { + byte(0x80); + while(queued != 112) byte(0x00); + for(auto n : range(16)) byte(length * 8 >> (15 - n) * 8); + } + + auto square(uint n) -> uint64_t { + static const uint64_t data[8] = { + 0x6a09e667f3bcc908, 0xbb67ae8584caa73b, 0x3c6ef372fe94f82b, 0xa54ff53a5f1d36f1, + 0x510e527fade682d1, 0x9b05688c2b3e6c1f, 0x1f83d9abfb41bd6b, 0x5be0cd19137e2179, + }; + return data[n]; + } + + auto cube(uint n) -> uint64_t { + static const uint64_t data[80] = { + 0x428a2f98d728ae22, 0x7137449123ef65cd, 0xb5c0fbcfec4d3b2f, 0xe9b5dba58189dbbc, + 0x3956c25bf348b538, 0x59f111f1b605d019, 0x923f82a4af194f9b, 0xab1c5ed5da6d8118, + 0xd807aa98a3030242, 0x12835b0145706fbe, 0x243185be4ee4b28c, 0x550c7dc3d5ffb4e2, + 0x72be5d74f27b896f, 0x80deb1fe3b1696b1, 0x9bdc06a725c71235, 0xc19bf174cf692694, + 0xe49b69c19ef14ad2, 0xefbe4786384f25e3, 0x0fc19dc68b8cd5b5, 0x240ca1cc77ac9c65, + 0x2de92c6f592b0275, 0x4a7484aa6ea6e483, 0x5cb0a9dcbd41fbd4, 0x76f988da831153b5, + 0x983e5152ee66dfab, 0xa831c66d2db43210, 0xb00327c898fb213f, 0xbf597fc7beef0ee4, + 0xc6e00bf33da88fc2, 0xd5a79147930aa725, 0x06ca6351e003826f, 0x142929670a0e6e70, + 0x27b70a8546d22ffc, 0x2e1b21385c26c926, 0x4d2c6dfc5ac42aed, 0x53380d139d95b3df, + 0x650a73548baf63de, 0x766a0abb3c77b2a8, 0x81c2c92e47edaee6, 0x92722c851482353b, + 0xa2bfe8a14cf10364, 0xa81a664bbc423001, 0xc24b8b70d0f89791, 0xc76c51a30654be30, + 0xd192e819d6ef5218, 0xd69906245565a910, 0xf40e35855771202a, 0x106aa07032bbd1b8, + 0x19a4c116b8d2d0c8, 0x1e376c085141ab53, 0x2748774cdf8eeb99, 0x34b0bcb5e19b48a8, + 0x391c0cb3c5c95a63, 0x4ed8aa4ae3418acb, 0x5b9cca4f7763e373, 0x682e6ff3d6b2b8a3, + 0x748f82ee5defb2fc, 0x78a5636f43172f60, 0x84c87814a1f0ab72, 0x8cc702081a6439ec, + 0x90befffa23631e28, 0xa4506cebde82bde9, 0xbef9a3f7b2c67915, 0xc67178f2e372532b, + 0xca273eceea26619c, 0xd186b8c721c0c207, 0xeada7dd6cde0eb1e, 0xf57d4f7fee6ed178, + 0x06f067aa72176fba, 0x0a637dc5a2c898a6, 0x113f9804bef90dae, 0x1b710b35131c471b, + 0x28db77f523047d84, 0x32caab7b40c72493, 0x3c9ebe0a15c9bebc, 0x431d67c49c100d4c, + 0x4cc5d4becb3e42b6, 0x597f299cfc657e2a, 0x5fcb6fab3ad6faec, 0x6c44198c4a475817, + }; + return data[n]; + } + + uint64_t queue[16] = {0}; + uint64_t w[80] = {0}; + uint64_t h[8] = {0}; + uint64_t queued = 0; + uint128_t length = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hashset.hpp b/roms/snes-test-roms/bass-untech/nall/hashset.hpp new file mode 100644 index 00000000..6812eafc --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hashset.hpp @@ -0,0 +1,133 @@ +#pragma once + +//hashset +// +//search: O(1) average; O(n) worst +//insert: O(1) average; O(n) worst +//remove: O(1) average; O(n) worst +// +//requirements: +// auto T::hash() const -> uint; +// auto T::operator==(const T&) const -> bool; + +namespace nall { + +template +struct hashset { + hashset() = default; + hashset(uint length) : length(bit::round(length)) {} + hashset(const hashset& source) { operator=(source); } + hashset(hashset&& source) { operator=(move(source)); } + ~hashset() { reset(); } + + auto operator=(const hashset& source) -> hashset& { + reset(); + if(source.pool) { + for(uint n : range(source.count)) { + insert(*source.pool[n]); + } + } + return *this; + } + + auto operator=(hashset&& source) -> hashset& { + reset(); + pool = source.pool; + length = source.length; + count = source.count; + source.pool = nullptr; + source.length = 8; + source.count = 0; + return *this; + } + + explicit operator bool() const { return count; } + auto capacity() const -> uint { return length; } + auto size() const -> uint { return count; } + + auto reset() -> void { + if(pool) { + for(uint n : range(length)) { + if(pool[n]) { + delete pool[n]; + pool[n] = nullptr; + } + } + delete pool; + pool = nullptr; + } + length = 8; + count = 0; + } + + auto reserve(uint size) -> void { + //ensure all items will fit into pool (with <= 50% load) and amortize growth + size = bit::round(max(size, count << 1)); + T** copy = new T*[size](); + + if(pool) { + for(uint n : range(length)) { + if(pool[n]) { + uint hash = (*pool[n]).hash() & (size - 1); + while(copy[hash]) if(++hash >= size) hash = 0; + copy[hash] = pool[n]; + pool[n] = nullptr; + } + } + } + + delete pool; + pool = copy; + length = size; + } + + auto find(const T& value) -> maybe { + if(!pool) return nothing; + + uint hash = value.hash() & (length - 1); + while(pool[hash]) { + if(value == *pool[hash]) return *pool[hash]; + if(++hash >= length) hash = 0; + } + + return nothing; + } + + auto insert(const T& value) -> maybe { + if(!pool) pool = new T*[length](); + + //double pool size when load is >= 50% + if(count >= (length >> 1)) reserve(length << 1); + count++; + + uint hash = value.hash() & (length - 1); + while(pool[hash]) if(++hash >= length) hash = 0; + pool[hash] = new T(value); + + return *pool[hash]; + } + + auto remove(const T& value) -> bool { + if(!pool) return false; + + uint hash = value.hash() & (length - 1); + while(pool[hash]) { + if(value == *pool[hash]) { + delete pool[hash]; + pool[hash] = nullptr; + count--; + return true; + } + if(++hash >= length) hash = 0; + } + + return false; + } + +protected: + T** pool = nullptr; + uint length = 8; //length of pool + uint count = 0; //number of objects inside of the pool +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/hid.hpp b/roms/snes-test-roms/bass-untech/nall/hid.hpp new file mode 100644 index 00000000..0f22ad2b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/hid.hpp @@ -0,0 +1,122 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall::HID { + +struct Input { + Input(const string& name) : _name(name) {} + + auto name() const -> string { return _name; } + auto value() const -> int16_t { return _value; } + auto setValue(int16_t value) -> void { _value = value; } + +private: + string _name; + int16_t _value = 0; + friend class Group; +}; + +struct Group : vector { + Group(const string& name) : _name(name) {} + + auto name() const -> string { return _name; } + auto input(uint id) -> Input& { return operator[](id); } + auto append(const string& name) -> void { vector::append(Input{name}); } + + auto find(const string& name) const -> maybe { + for(auto id : range(size())) { + if(operator[](id)._name == name) return id; + } + return nothing; + } + +private: + string _name; + friend class Device; +}; + +struct Device : vector { + Device(const string& name) : _name(name) {} + virtual ~Device() = default; + + //id => {pathID}-{vendorID}-{productID} + auto pathID() const -> uint32_t { return (uint32_t)(_id >> 32); } //32-63 + auto vendorID() const -> uint16_t { return (uint16_t)(_id >> 16); } //16-31 + auto productID() const -> uint16_t { return (uint16_t)(_id >> 0); } // 0-15 + + auto setPathID (uint32_t pathID ) -> void { _id = (uint64_t)pathID << 32 | vendorID() << 16 | productID() << 0; } + auto setVendorID (uint16_t vendorID ) -> void { _id = (uint64_t)pathID() << 32 | vendorID << 16 | productID() << 0; } + auto setProductID(uint16_t productID) -> void { _id = (uint64_t)pathID() << 32 | vendorID() << 16 | productID << 0; } + + virtual auto isNull() const -> bool { return false; } + virtual auto isKeyboard() const -> bool { return false; } + virtual auto isMouse() const -> bool { return false; } + virtual auto isJoypad() const -> bool { return false; } + + auto name() const -> string { return _name; } + auto id() const -> uint64_t { return _id; } + auto setID(uint64_t id) -> void { _id = id; } + auto group(uint id) -> Group& { return operator[](id); } + auto append(const string& name) -> void { vector::append(Group{name}); } + + auto find(const string& name) const -> maybe { + for(auto id : range(size())) { + if(operator[](id)._name == name) return id; + } + return nothing; + } + +private: + string _name; + uint64_t _id = 0; +}; + +struct Null : Device { + enum : uint16_t { GenericVendorID = 0x0000, GenericProductID = 0x0000 }; + + Null() : Device("Null") {} + auto isNull() const -> bool { return true; } +}; + +struct Keyboard : Device { + enum : uint16_t { GenericVendorID = 0x0000, GenericProductID = 0x0001 }; + enum GroupID : uint { Button }; + + Keyboard() : Device("Keyboard") { append("Button"); } + auto isKeyboard() const -> bool { return true; } + auto buttons() -> Group& { return group(GroupID::Button); } +}; + +struct Mouse : Device { + enum : uint16_t { GenericVendorID = 0x0000, GenericProductID = 0x0002 }; + enum GroupID : uint { Axis, Button }; + + Mouse() : Device("Mouse") { append("Axis"), append("Button"); } + auto isMouse() const -> bool { return true; } + auto axes() -> Group& { return group(GroupID::Axis); } + auto buttons() -> Group& { return group(GroupID::Button); } +}; + +struct Joypad : Device { + enum : uint16_t { GenericVendorID = 0x0000, GenericProductID = 0x0003 }; + enum GroupID : uint { Axis, Hat, Trigger, Button }; + + Joypad() : Device("Joypad") { append("Axis"), append("Hat"), append("Trigger"), append("Button"); } + auto isJoypad() const -> bool { return true; } + auto axes() -> Group& { return group(GroupID::Axis); } + auto hats() -> Group& { return group(GroupID::Hat); } + auto triggers() -> Group& { return group(GroupID::Trigger); } + auto buttons() -> Group& { return group(GroupID::Button); } + + auto rumble() const -> bool { return _rumble; } + auto setRumble(bool rumble) -> void { _rumble = rumble; } + +private: + bool _rumble = false; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/client.hpp b/roms/snes-test-roms/bass-untech/nall/http/client.hpp new file mode 100644 index 00000000..cc0eca94 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/client.hpp @@ -0,0 +1,56 @@ +#pragma once + +#include + +namespace nall::HTTP { + +struct Client : Role { + auto open(const string& hostname, uint port = 80) -> bool; + auto upload(const Request& request) -> bool; + auto download(const Request& request) -> Response; + auto close() -> void; + ~Client() { close(); } + +private: + int fd = -1; + addrinfo* info = nullptr; +}; + +inline auto Client::open(const string& hostname, uint port) -> bool { + addrinfo hint = {0}; + hint.ai_family = AF_UNSPEC; + hint.ai_socktype = SOCK_STREAM; + hint.ai_flags = AI_ADDRCONFIG; + + if(getaddrinfo(hostname, string{port}, &hint, &info) != 0) return close(), false; + + fd = socket(info->ai_family, info->ai_socktype, info->ai_protocol); + if(fd < 0) return close(), false; + + if(connect(fd, info->ai_addr, info->ai_addrlen) < 0) return close(), false; + return true; +} + +inline auto Client::upload(const Request& request) -> bool { + return Role::upload(fd, request); +} + +inline auto Client::download(const Request& request) -> Response { + Response response(request); + Role::download(fd, response); + return response; +} + +inline auto Client::close() -> void { + if(fd) { + ::close(fd); + fd = -1; + } + + if(info) { + freeaddrinfo(info); + info = nullptr; + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/message.hpp b/roms/snes-test-roms/bass-untech/nall/http/message.hpp new file mode 100644 index 00000000..e4c543d1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/message.hpp @@ -0,0 +1,104 @@ +#pragma once + +//httpMessage: base class for httpRequest and httpResponse +//provides shared functionality + +namespace nall::HTTP { + +struct Variable { + string name; + string value; +}; + +struct SharedVariable { + SharedVariable(const nall::string& name = "", const nall::string& value = "") : shared(new Variable{name, value}) {} + + explicit operator bool() const { return (bool)shared->name; } + auto operator()() const { return shared->value; } + auto& operator=(const nall::string& value) { shared->value = value; return *this; } + + auto name() const { return shared->name; } + auto value() const { return shared->value; } + auto string() const { return nall::string{shared->value}.strip().replace("\r", ""); } + auto boolean() const { return string() == "true"; } + auto integer() const { return string().integer(); } + auto natural() const { return string().natural(); } + auto real() const { return string().real(); } + + auto& setName(const nall::string& name) { shared->name = name; return *this; } + auto& setValue(const nall::string& value = "") { shared->value = value; return *this; } + + shared_pointer shared; +}; + +struct Variables { + auto operator[](const string& name) const -> SharedVariable { + for(auto& variable : variables) { + if(variable.shared->name.iequals(name)) return variable; + } + return {}; + } + + auto operator()(const string& name) -> SharedVariable { + for(auto& variable : variables) { + if(variable.shared->name.iequals(name)) return variable; + } + return append(name); + } + + auto find(const string& name) const -> vector { + vector result; + for(auto& variable : variables) { + if(variable.shared->name.iequals(name)) result.append(variable); + } + return result; + } + + auto assign(const string& name, const string& value = "") -> SharedVariable { + for(auto& variable : variables) { + if(variable.shared->name.iequals(name)) { + variable.shared->value = value; + return variable; + } + } + return append(name, value); + } + + auto append(const string& name, const string& value = "") -> SharedVariable { + SharedVariable variable{name, value}; + variables.append(variable); + return variable; + } + + auto remove(const string& name) -> void { + for(auto n : reverse(range(variables.size()))) { + if(variables[n].shared->name.iequals(name)) variables.remove(n); + } + } + + auto size() const { return variables.size(); } + auto begin() const { return variables.begin(); } + auto end() const { return variables.end(); } + auto begin() { return variables.begin(); } + auto end() { return variables.end(); } + + vector variables; +}; + +struct Message { + using type = Message; + + virtual auto head(const function& callback) const -> bool = 0; + virtual auto setHead() -> bool = 0; + + virtual auto body(const function& callback) const -> bool = 0; + virtual auto setBody() -> bool = 0; + + Variables header; + +//private: + string _head; + string _body; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/request.hpp b/roms/snes-test-roms/bass-untech/nall/http/request.hpp new file mode 100644 index 00000000..ff1c615e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/request.hpp @@ -0,0 +1,184 @@ +#pragma once + +#include +#include +#include + +namespace nall::HTTP { + +struct Request : Message { + using type = Request; + + enum class RequestType : uint { None, Head, Get, Post }; + + explicit operator bool() const { return requestType() != RequestType::None; } + + auto head(const function& callback) const -> bool override; + auto setHead() -> bool override; + + auto body(const function& callback) const -> bool override; + auto setBody() -> bool override; + + auto ipv4() const -> bool { return _ipv6 == false; } + auto ipv6() const -> bool { return _ipv6 == true; } + auto ip() const -> string { return _ip; } + + auto requestType() const -> RequestType { return _requestType; } + auto setRequestType(RequestType value) -> void { _requestType = value; } + + auto path() const -> string { return _path; } + auto setPath(const string& value) -> void { _path = value; } + + Variables cookie; + Variables get; + Variables post; + +//private: + bool _ipv6 = false; + string _ip; + RequestType _requestType = RequestType::None; + string _path; +}; + +inline auto Request::head(const function& callback) const -> bool { + if(!callback) return false; + string output; + + string request = path(); + if(get.size()) { + request.append("?"); + for(auto& variable : get) { + request.append(Encode::URL(variable.name()), "=", Encode::URL(variable.value()), "&"); + } + request.trimRight("&", 1L); + } + + switch(requestType()) { + case RequestType::Head: output.append("HEAD ", request, " HTTP/1.1\r\n"); break; + case RequestType::Get : output.append("GET ", request, " HTTP/1.1\r\n"); break; + case RequestType::Post: output.append("POST ", request, " HTTP/1.1\r\n"); break; + default: return false; + } + + for(auto& variable : header) { + output.append(variable.name(), ": ", variable.value(), "\r\n"); + } + output.append("\r\n"); + + return callback(output.data(), output.size()); +} + +inline auto Request::setHead() -> bool { + auto headers = _head.split("\n"); + string request = headers.takeLeft().trimRight("\r", 1L); + string requestHost; + + if(request.iendsWith(" HTTP/1.0")) request.itrimRight(" HTTP/1.0", 1L); + else if(request.iendsWith(" HTTP/1.1")) request.itrimRight(" HTTP/1.1", 1L); + else return false; + + if(request.ibeginsWith("HEAD ")) request.itrimLeft("HEAD ", 1L), setRequestType(RequestType::Head); + else if(request.ibeginsWith("GET " )) request.itrimLeft("GET ", 1L), setRequestType(RequestType::Get ); + else if(request.ibeginsWith("POST ")) request.itrimLeft("POST ", 1L), setRequestType(RequestType::Post); + else return false; + + //decode absolute URIs + request.strip().itrimLeft("http://", 1L); + if(!request.beginsWith("/")) { + auto components = request.split("/", 1L); + requestHost = components(0); + request = {"/", components(1)}; + } + + auto components = request.split("?", 1L); + setPath(components(0)); + + if(auto queryString = components(1)) { + for(auto& block : queryString.split("&")) { + auto p = block.split("=", 1L); + auto name = Decode::URL(p(0)); + auto value = Decode::URL(p(1)); + if(name) get.append(name, value); + } + } + + for(auto& header : headers) { + if(header.beginsWith(" ") || header.beginsWith("\t")) continue; + auto part = header.split(":", 1L).strip(); + if(!part[0] || part.size() != 2) continue; + this->header.append(part[0], part[1]); + + if(part[0].iequals("Cookie")) { + for(auto& block : part[1].split(";")) { + auto p = block.split("=", 1L).strip(); + auto name = p(0); + auto value = p(1).trim("\"", "\"", 1L); + if(name) cookie.append(name, value); + } + } + } + + if(requestHost) header.assign("Host", requestHost); //request URI overrides host header + return true; +} + +inline auto Request::body(const function& callback) const -> bool { + if(!callback) return false; + + if(_body) { + return callback(_body.data(), _body.size()); + } + + return true; +} + +inline auto Request::setBody() -> bool { + if(requestType() == RequestType::Post) { + auto contentType = header["Content-Type"].value(); + if(contentType.iequals("application/x-www-form-urlencoded")) { + for(auto& block : _body.split("&")) { + auto p = block.trimRight("\r").split("=", 1L); + auto name = Decode::URL(p(0)); + auto value = Decode::URL(p(1)); + if(name) post.append(name, value); + } + } else if(contentType.imatch("multipart/form-data; boundary=?*")) { + auto boundary = contentType.itrimLeft("multipart/form-data; boundary=", 1L).trim("\"", "\"", 1L); + auto blocks = _body.split({"--", boundary}, 1024L); //limit blocks to prevent memory exhaustion + for(auto& block : blocks) block.trim("\r\n", "\r\n", 1L); + if(blocks.size() < 2 || (blocks.takeLeft(), !blocks.takeRight().beginsWith("--"))) return false; + for(auto& block : blocks) { + string name; + string filename; + string contentType; + + auto segments = block.split("\r\n\r\n", 1L); + for(auto& segment : segments(0).split("\r\n")) { + auto statement = segment.split(":", 1L); + if(statement(0).ibeginsWith("Content-Disposition")) { + for(auto& component : statement(1).split(";")) { + auto part = component.split("=", 1L).strip(); + if(part(0).iequals("name")) { + name = part(1).trim("\"", "\"", 1L); + } else if(part(0).iequals("filename")) { + filename = part(1).trim("\"", "\"", 1L); + } + } + } else if(statement(0).ibeginsWith("Content-Type")) { + contentType = statement(1).strip(); + } + } + + if(name) { + post.append(name, segments(1)); + post.append({name, ".filename"}, filename); + post.append({name, ".content-type"}, contentType); + } + } + } + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/response.hpp b/roms/snes-test-roms/bass-untech/nall/http/response.hpp new file mode 100644 index 00000000..6aa3e347 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/response.hpp @@ -0,0 +1,290 @@ +#pragma once + +#include + +namespace nall::HTTP { + +struct Response : Message { + using type = Response; + + Response() = default; + Response(const Request& request) { setRequest(request); } + + explicit operator bool() const { return responseType() != 0; } + auto operator()(uint responseType) -> type& { return setResponseType(responseType); } + + auto head(const function& callback) const -> bool override; + auto setHead() -> bool override; + + auto body(const function& callback) const -> bool override; + auto setBody() -> bool override; + + auto request() const -> const Request* { return _request; } + auto setRequest(const Request& value) -> type& { _request = &value; return *this; } + + auto responseType() const -> uint { return _responseType; } + auto setResponseType(uint value) -> type& { _responseType = value; return *this; } + + auto hasData() const -> bool { return (bool)_data; } + auto data() const -> const vector& { return _data; } + auto setData(const vector& value) -> type&; + + auto hasFile() const -> bool { return (bool)_file; } + auto file() const -> const string& { return _file; } + auto setFile(const string& value) -> type&; + + auto hasText() const -> bool { return (bool)_text; } + auto text() const -> const string& { return _text; } + auto setText(const string& value) -> type&; + + auto hasBody() const -> bool; + auto findContentLength() const -> uint; + auto findContentType() const -> string; + auto findContentType(const string& suffix) const -> string; + auto findResponseType() const -> string; + auto findResponseTypeVerbose() const -> string; + auto setFileETag() -> void; + + const Request* _request = nullptr; + uint _responseType = 0; + vector _data; + string _file; + string _text; +}; + +inline auto Response::head(const function& callback) const -> bool { + if(!callback) return false; + string output; + + if(auto request = this->request()) { + if(auto eTag = header["ETag"]) { + if(eTag.value() == request->header["If-None-Match"].value()) { + output.append("HTTP/1.1 304 Not Modified\r\n"); + output.append("Connection: close\r\n"); + output.append("\r\n"); + return callback(output.data(), output.size()); + } + } + } + + output.append("HTTP/1.1 ", findResponseType(), "\r\n"); + for(auto& variable : header) { + output.append(variable.name(), ": ", variable.value(), "\r\n"); + } + if(hasBody()) { + if(!header["Content-Length"] && !header["Transfer-Encoding"].value().iequals("chunked")) { + output.append("Content-Length: ", findContentLength(), "\r\n"); + } + if(!header["Content-Type"]) { + output.append("Content-Type: ", findContentType(), "\r\n"); + } + } + if(!header["Connection"]) { + output.append("Connection: close\r\n"); + } + output.append("\r\n"); + + return callback(output.data(), output.size()); +} + +inline auto Response::setHead() -> bool { + auto headers = _head.split("\n"); + string response = headers.takeLeft().trimRight("\r"); + + if(response.ibeginsWith("HTTP/1.0 ")) response.itrimLeft("HTTP/1.0 ", 1L); + else if(response.ibeginsWith("HTTP/1.1 ")) response.itrimLeft("HTTP/1.1 ", 1L); + else return false; + + setResponseType(response.natural()); + + for(auto& header : headers) { + if(header.beginsWith(" ") || header.beginsWith("\t")) continue; + auto variable = header.split(":", 1L).strip(); + if(variable.size() != 2) continue; + this->header.append(variable[0], variable[1]); + } + + return true; +} + +inline auto Response::body(const function& callback) const -> bool { + if(!callback) return false; + if(!hasBody()) return true; + bool chunked = header["Transfer-Encoding"].value() == "chunked"; + + if(chunked) { + string prefix = {hex(findContentLength()), "\r\n"}; + if(!callback(prefix.data(), prefix.size())) return false; + } + + if(_body) { + if(!callback(_body.data(), _body.size())) return false; + } else if(hasData()) { + if(!callback(data().data(), data().size())) return false; + } else if(hasFile()) { + file_map map(file(), file_map::mode::read); + if(!callback(map.data(), map.size())) return false; + } else if(hasText()) { + if(!callback(text().data(), text().size())) return false; + } else { + string response = findResponseType(); + if(!callback(response.data(), response.size())) return false; + } + + if(chunked) { + string suffix = {"\r\n0\r\n\r\n"}; + if(!callback(suffix.data(), suffix.size())) return false; + } + + return true; +} + +inline auto Response::setBody() -> bool { + return true; +} + +inline auto Response::hasBody() const -> bool { + if(auto request = this->request()) { + if(request->requestType() == Request::RequestType::Head) return false; + } + if(responseType() == 301) return false; + if(responseType() == 302) return false; + if(responseType() == 303) return false; + if(responseType() == 304) return false; + if(responseType() == 307) return false; + return true; +} + +inline auto Response::findContentLength() const -> uint { + if(auto contentLength = header["Content-Length"]) return contentLength.value().natural(); + if(_body) return _body.size(); + if(hasData()) return data().size(); + if(hasFile()) return file::size(file()); + if(hasText()) return text().size(); + return findResponseType().size(); +} + +inline auto Response::findContentType() const -> string { + if(auto contentType = header["Content-Type"]) return contentType.value(); + if(hasData()) return "application/octet-stream"; + if(hasFile()) return findContentType(Location::suffix(file())); + return "text/html; charset=utf-8"; +} + +inline auto Response::findContentType(const string& s) const -> string { + if(s == ".7z" ) return "application/x-7z-compressed"; + if(s == ".avi" ) return "video/avi"; + if(s == ".bml" ) return "text/plain; charset=utf-8"; + if(s == ".bz2" ) return "application/x-bzip2"; + if(s == ".c" ) return "text/plain; charset=utf-8"; + if(s == ".cpp" ) return "text/plain; charset=utf-8"; + if(s == ".css" ) return "text/css; charset=utf-8"; + if(s == ".gif" ) return "image/gif"; + if(s == ".gz" ) return "application/gzip"; + if(s == ".h" ) return "text/plain; charset=utf-8"; + if(s == ".hpp" ) return "text/plain; charset=utf-8"; + if(s == ".htm" ) return "text/html; charset=utf-8"; + if(s == ".html") return "text/html; charset=utf-8"; + if(s == ".ico" ) return "image/x-icon"; + if(s == ".jpg" ) return "image/jpeg"; + if(s == ".jpeg") return "image/jpeg"; + if(s == ".js" ) return "application/javascript"; + if(s == ".mka" ) return "audio/x-matroska"; + if(s == ".mkv" ) return "video/x-matroska"; + if(s == ".mp3" ) return "audio/mpeg"; + if(s == ".mp4" ) return "video/mp4"; + if(s == ".mpeg") return "video/mpeg"; + if(s == ".mpg" ) return "video/mpeg"; + if(s == ".ogg" ) return "audio/ogg"; + if(s == ".pdf" ) return "application/pdf"; + if(s == ".png" ) return "image/png"; + if(s == ".rar" ) return "application/x-rar-compressed"; + if(s == ".svg" ) return "image/svg+xml"; + if(s == ".tar" ) return "application/x-tar"; + if(s == ".txt" ) return "text/plain; charset=utf-8"; + if(s == ".wav" ) return "audio/vnd.wave"; + if(s == ".webm") return "video/webm"; + if(s == ".xml" ) return "text/xml; charset=utf-8"; + if(s == ".xz" ) return "application/x-xz"; + if(s == ".zip" ) return "application/zip"; + return "application/octet-stream"; //binary +} + +inline auto Response::findResponseType() const -> string { + switch(responseType()) { + case 200: return "200 OK"; + case 301: return "301 Moved Permanently"; + case 302: return "302 Found"; + case 303: return "303 See Other"; + case 304: return "304 Not Modified"; + case 307: return "307 Temporary Redirect"; + case 400: return "400 Bad Request"; + case 403: return "403 Forbidden"; + case 404: return "404 Not Found"; + case 500: return "500 Internal Server Error"; + case 501: return "501 Not Implemented"; + case 503: return "503 Service Unavailable"; + } + return "501 Not Implemented"; +} + +inline auto Response::findResponseTypeVerbose() const -> string { + switch(responseType()) { + case 400: return "The server was unable to understand your request."; + case 403: return "You are not authorized to access this resource."; + case 404: return "The requested content could not be found."; + case 500: return "The server has encountered an error."; + case 501: return "The requested feature has not been implemented."; + case 503: return "The requested service is not currently available."; + } + return findResponseType(); //fallback for uncommon responses +} + +inline auto Response::setData(const vector& value) -> type& { + _data = value; + header.assign("Content-Length", value.size()); + return *this; +} + +inline auto Response::setFile(const string& value) -> type& { + //block path escalation exploits ("../" and "..\" in the file location) + bool valid = true; + for(uint n : range(value.size())) { + if(value(n + 0, '\0') != '.') continue; + if(value(n + 1, '\0') != '.') continue; + if(value(n + 2, '\0') != '/' && value(n + 2, '\0') != '\\') continue; + valid = false; + break; + } + if(!valid) return *this; + + //cache images for seven days + auto suffix = Location::suffix(value); + uint maxAge = 0; + if(suffix == ".svg" + || suffix == ".ico" + || suffix == ".png" + || suffix == ".gif" + || suffix == ".jpg" + || suffix == ".jpeg") { + maxAge = 7 * 24 * 60 * 60; + } + + _file = value; + header.assign("Content-Length", file::size(value)); + header.assign("ETag", {"\"", chrono::utc::datetime(file::timestamp(value, file::time::modify)), "\""}); + if(maxAge == 0) { + header.assign("Cache-Control", {"public"}); + } else { + header.assign("Cache-Control", {"public, max-age=", maxAge}); + } + return *this; +} + +inline auto Response::setText(const string& value) -> type& { + _text = value; + header.assign("Content-Length", value.size()); + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/role.hpp b/roms/snes-test-roms/bass-untech/nall/http/role.hpp new file mode 100644 index 00000000..ecdf0dbf --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/role.hpp @@ -0,0 +1,158 @@ +#pragma once + +//Role: base class for Client and Server +//provides shared functionality + +#include +#include + +namespace nall::HTTP { + +struct Role { + struct Settings { + int connectionLimit = 1 * 1024; //server + int headSizeLimit = 16 * 1024; //client, server + int bodySizeLimit = 65536 * 1024; //client, server + int chunkSize = 32 * 1024; //client, server + int threadStackSize = 128 * 1024; //server + int timeoutReceive = 15 * 1000; //server + int timeoutSend = 15 * 1000; //server + } settings; + + auto configure(const string& parameters) -> bool; + auto download(int fd, Message& message) -> bool; + auto upload(int fd, const Message& message) -> bool; +}; + +inline auto Role::configure(const string& parameters) -> bool { + auto document = BML::unserialize(parameters); + for(auto parameter : document) { + auto name = parameter.name(); + auto value = parameter.integer(); + + if(0); + else if(name == "connectionLimit") settings.connectionLimit = value; + else if(name == "headSizeLimit") settings.headSizeLimit = value; + else if(name == "bodySizeLimit") settings.bodySizeLimit = value; + else if(name == "chunkSize") settings.chunkSize = value; + else if(name == "threadStackSize") settings.threadStackSize = value; + else if(name == "timeoutReceive") settings.timeoutReceive = value; + else if(name == "timeoutSend") settings.timeoutSend = value; + } + return true; +} + +inline auto Role::download(int fd, Message& message) -> bool { + auto& head = message._head; + auto& body = message._body; + string chunk; + uint8_t packet[settings.chunkSize], *p = nullptr; + + head.reset(), head.reserve(4095); + body.reset(), body.reserve(4095); + + bool headReceived = false; + bool chunked = false; + bool chunkReceived = false; + bool chunkFooterReceived = true; + int length = 0; + int chunkLength = 0; + int contentLength = 0; + + while(true) { + if(auto limit = settings.headSizeLimit) if(head.size() >= limit) return false; + if(auto limit = settings.bodySizeLimit) if(body.size() >= limit) return false; + + if(headReceived && !chunked && body.size() >= contentLength) { + body.resize(contentLength); + break; + } + + if(length == 0) { + length = recv(fd, packet, settings.chunkSize, MSG_NOSIGNAL); + if(length <= 0) return false; + p = packet; + } + + if(!headReceived) { + head.append((char)*p++); + --length; + + if(head.endsWith("\r\n\r\n") || head.endsWith("\n\n")) { + headReceived = true; + if(!message.setHead()) return false; + chunked = message.header["Transfer-Encoding"].value().iequals("chunked"); + contentLength = message.header["Content-Length"].value().natural(); + } + + continue; + } + + if(chunked && !chunkReceived) { + char n = *p++; + --length; + + if(!chunkFooterReceived) { + if(n == '\n') chunkFooterReceived = true; + continue; + } + + chunk.append(n); + + if(chunk.endsWith("\r\n") || chunk.endsWith("\n")) { + chunkReceived = true; + chunkLength = chunk.hex(); + if(chunkLength == 0) break; + chunk.reset(); + } + + continue; + } + + if(!chunked) { + body.resize(body.size() + length); + memory::copy(body.get() + body.size() - length, p, length); + + p += length; + length = 0; + } else { + int transferLength = min(length, chunkLength); + body.resize(body.size() + transferLength); + memory::copy(body.get() + body.size() - transferLength, p, transferLength); + + p += transferLength; + length -= transferLength; + chunkLength -= transferLength; + + if(chunkLength == 0) { + chunkReceived = false; + chunkFooterReceived = false; + } + } + } + + if(!message.setBody()) return false; + return true; +} + +inline auto Role::upload(int fd, const Message& message) -> bool { + auto transfer = [&](const uint8_t* data, uint size) -> bool { + while(size) { + int length = send(fd, data, min(size, settings.chunkSize), MSG_NOSIGNAL); + if(length < 0) return false; + data += length; + size -= length; + } + return true; + }; + + if(message.head([&](const uint8_t* data, uint size) -> bool { return transfer(data, size); })) { + if(message.body([&](const uint8_t* data, uint size) -> bool { return transfer(data, size); })) { + return true; + } + } + + return false; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/http/server.hpp b/roms/snes-test-roms/bass-untech/nall/http/server.hpp new file mode 100644 index 00000000..13c8ec0f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/http/server.hpp @@ -0,0 +1,226 @@ +#pragma once + +#include +#include + +namespace nall::HTTP { + +struct Server : Role, service { + auto open(uint port = 8080, const string& serviceName = "", const string& command = "") -> bool; + auto main(const function& function = {}) -> void; + auto scan() -> string; + auto close() -> void; + ~Server() { close(); } + +private: + function callback; + std::atomic connections{0}; + + int fd4 = -1; + int fd6 = -1; + struct sockaddr_in addrin4 = {0}; + struct sockaddr_in6 addrin6 = {0}; + + auto ipv4() const -> bool { return fd4 >= 0; } + auto ipv6() const -> bool { return fd6 >= 0; } + + auto ipv4_close() -> void { if(fd4 >= 0) ::close(fd4); fd4 = -1; } + auto ipv6_close() -> void { if(fd6 >= 0) ::close(fd6); fd6 = -1; } + + auto ipv4_scan() -> bool; + auto ipv6_scan() -> bool; +}; + +inline auto Server::open(uint port, const string& serviceName, const string& command) -> bool { + if(serviceName) { + if(!service::command(serviceName, command)) return false; + } + + fd4 = socket(AF_INET, SOCK_STREAM, 0); + fd6 = socket(AF_INET6, SOCK_STREAM, 0); + if(!ipv4() && !ipv6()) return false; + + { + #if defined(SO_RCVTIMEO) + if(settings.timeoutReceive) { + struct timeval rcvtimeo; + rcvtimeo.tv_sec = settings.timeoutReceive / 1000; + rcvtimeo.tv_usec = settings.timeoutReceive % 1000 * 1000; + if(ipv4()) setsockopt(fd4, SOL_SOCKET, SO_RCVTIMEO, &rcvtimeo, sizeof(struct timeval)); + if(ipv6()) setsockopt(fd6, SOL_SOCKET, SO_RCVTIMEO, &rcvtimeo, sizeof(struct timeval)); + } + #endif + + #if defined(SO_SNDTIMEO) + if(settings.timeoutSend) { + struct timeval sndtimeo; + sndtimeo.tv_sec = settings.timeoutSend / 1000; + sndtimeo.tv_usec = settings.timeoutSend % 1000 * 1000; + if(ipv4()) setsockopt(fd4, SOL_SOCKET, SO_SNDTIMEO, &sndtimeo, sizeof(struct timeval)); + if(ipv6()) setsockopt(fd6, SOL_SOCKET, SO_SNDTIMEO, &sndtimeo, sizeof(struct timeval)); + } + #endif + + #if defined(SO_NOSIGPIPE) //BSD, OSX + int nosigpipe = 1; + if(ipv4()) setsockopt(fd4, SOL_SOCKET, SO_NOSIGPIPE, &nosigpipe, sizeof(int)); + if(ipv6()) setsockopt(fd6, SOL_SOCKET, SO_NOSIGPIPE, &nosigpipe, sizeof(int)); + #endif + + #if defined(SO_REUSEADDR) //BSD, Linux, OSX + int reuseaddr = 1; + if(ipv4()) setsockopt(fd4, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, sizeof(int)); + if(ipv6()) setsockopt(fd6, SOL_SOCKET, SO_REUSEADDR, &reuseaddr, sizeof(int)); + #endif + + #if defined(SO_REUSEPORT) //BSD, OSX + int reuseport = 1; + if(ipv4()) setsockopt(fd4, SOL_SOCKET, SO_REUSEPORT, &reuseport, sizeof(int)); + if(ipv6()) setsockopt(fd6, SOL_SOCKET, SO_REUSEPORT, &reuseport, sizeof(int)); + #endif + } + + addrin4.sin_family = AF_INET; + addrin4.sin_addr.s_addr = htonl(INADDR_ANY); + addrin4.sin_port = htons(port); + + addrin6.sin6_family = AF_INET6; + addrin6.sin6_addr = in6addr_any; + addrin6.sin6_port = htons(port); + + if(bind(fd4, (struct sockaddr*)&addrin4, sizeof(addrin4)) < 0 || listen(fd4, SOMAXCONN) < 0) ipv4_close(); + if(bind(fd6, (struct sockaddr*)&addrin6, sizeof(addrin6)) < 0 || listen(fd6, SOMAXCONN) < 0) ipv6_close(); + return ipv4() || ipv6(); +} + +inline auto Server::main(const function& function) -> void { + callback = function; +} + +inline auto Server::scan() -> string { + if(auto command = service::receive()) return command; + if(connections >= settings.connectionLimit) return "busy"; + if(ipv4() && ipv4_scan()) return "ok"; + if(ipv6() && ipv6_scan()) return "ok"; + return "idle"; +} + +inline auto Server::ipv4_scan() -> bool { + struct pollfd query = {0}; + query.fd = fd4; + query.events = POLLIN; + poll(&query, 1, 0); + + if(query.fd == fd4 && query.revents & POLLIN) { + ++connections; + + thread::create([&](uintptr) { + thread::detach(); + + int clientfd = -1; + struct sockaddr_in settings = {0}; + socklen_t socklen = sizeof(sockaddr_in); + + clientfd = accept(fd4, (struct sockaddr*)&settings, &socklen); + if(clientfd < 0) return; + + uint32_t ip = ntohl(settings.sin_addr.s_addr); + + Request request; + request._ipv6 = false; + request._ip = { + (uint8_t)(ip >> 24), ".", + (uint8_t)(ip >> 16), ".", + (uint8_t)(ip >> 8), ".", + (uint8_t)(ip >> 0) + }; + + if(download(clientfd, request) && callback) { + auto response = callback(request); + upload(clientfd, response); + } else { + upload(clientfd, Response()); //"501 Not Implemented" + } + + ::close(clientfd); + --connections; + }, 0, settings.threadStackSize); + + return true; + } + + return false; +} + +inline auto Server::ipv6_scan() -> bool { + struct pollfd query = {0}; + query.fd = fd6; + query.events = POLLIN; + poll(&query, 1, 0); + + if(query.fd == fd6 && query.revents & POLLIN) { + ++connections; + + thread::create([&](uintptr) { + thread::detach(); + + int clientfd = -1; + struct sockaddr_in6 settings = {0}; + socklen_t socklen = sizeof(sockaddr_in6); + + clientfd = accept(fd6, (struct sockaddr*)&settings, &socklen); + if(clientfd < 0) return; + + uint8_t* ip = settings.sin6_addr.s6_addr; + uint16_t ipSegment[8]; + for(auto n : range(8)) ipSegment[n] = ip[n * 2 + 0] * 256 + ip[n * 2 + 1]; + + Request request; + request._ipv6 = true; + //RFC5952 IPv6 encoding: the first longest 2+ consecutive zero-sequence is compressed to "::" + int zeroOffset = -1; + int zeroLength = 0; + int zeroCounter = 0; + for(auto n : range(8)) { + uint16_t value = ipSegment[n]; + if(value == 0) zeroCounter++; + if(zeroCounter > zeroLength) { + zeroLength = zeroCounter; + zeroOffset = 1 + n - zeroLength; + } + if(value != 0) zeroCounter = 0; + } + if(zeroLength == 1) zeroOffset = -1; + for(uint n = 0; n < 8;) { + if(n == zeroOffset) { + request._ip.append(n == 0 ? "::" : ":"); + n += zeroLength; + } else { + uint16_t value = ipSegment[n]; + request._ip.append(hex(value), n++ != 7 ? ":" : ""); + } + } + + if(download(clientfd, request) && callback) { + auto response = callback(request); + upload(clientfd, response); + } else { + upload(clientfd, Response()); //"501 Not Implemented" + } + + ::close(clientfd); + --connections; + }, 0, settings.threadStackSize); + + return true; + } + + return false; +} + +inline auto Server::close() -> void { + ipv4_close(); + ipv6_close(); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image.hpp b/roms/snes-test-roms/bass-untech/nall/image.hpp new file mode 100644 index 00000000..b94a9d2c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image.hpp @@ -0,0 +1,169 @@ +#pragma once + +#include + +#include +#include +#include +#include +#include + +namespace nall { + +struct image { + enum class blend : uint { + add, + sourceAlpha, //color = sourceColor * sourceAlpha + targetColor * (1 - sourceAlpha) + sourceColor, //color = sourceColor + targetAlpha, //color = targetColor * targetAlpha + sourceColor * (1 - targetAlpha) + targetColor, //color = targetColor + }; + + struct channel { + channel(uint64_t mask, uint depth, uint shift) : _mask(mask), _depth(depth), _shift(shift) { + } + + auto operator==(const channel& source) const -> bool { + return _mask == source._mask && _depth == source._depth && _shift == source._shift; + } + + auto operator!=(const channel& source) const -> bool { + return !operator==(source); + } + + auto mask() const { return _mask; } + auto depth() const { return _depth; } + auto shift() const { return _shift; } + + private: + uint64_t _mask; + uint _depth; + uint _shift; + }; + + //core.hpp + image(const image& source); + image(image&& source); + image(bool endian, uint depth, uint64_t alphaMask, uint64_t redMask, uint64_t greenMask, uint64_t blueMask); + image(const string& filename); + image(const void* data, uint size); + image(const vector& buffer); + template image(const uint8_t (&Name)[Size]); + image(); + ~image(); + + auto operator=(const image& source) -> image&; + auto operator=(image&& source) -> image&; + + explicit operator bool() const; + auto operator==(const image& source) const -> bool; + auto operator!=(const image& source) const -> bool; + + auto read(const uint8_t* data) const -> uint64_t; + auto write(uint8_t* data, uint64_t value) const -> void; + + auto free() -> void; + auto load(const string& filename) -> bool; + auto copy(const void* data, uint pitch, uint width, uint height) -> void; + auto allocate(uint width, uint height) -> void; + + //fill.hpp + auto fill(uint64_t color = 0) -> void; + auto gradient(uint64_t a, uint64_t b, uint64_t c, uint64_t d) -> void; + auto gradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY, function callback) -> void; + auto crossGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto diamondGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto horizontalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto radialGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto sphericalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto squareGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + auto verticalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void; + + //scale.hpp + auto scale(uint width, uint height, bool linear = true) -> void; + + //blend.hpp + auto impose(blend mode, uint targetX, uint targetY, image source, uint x, uint y, uint width, uint height) -> void; + + //utility.hpp + auto shrink(uint64_t transparentColor = 0) -> void; + auto crop(uint x, uint y, uint width, uint height) -> bool; + auto alphaBlend(uint64_t alphaColor) -> void; + auto alphaMultiply() -> void; + auto transform(const image& source = {}) -> void; + auto transform(bool endian, uint depth, uint64_t alphaMask, uint64_t redMask, uint64_t greenMask, uint64_t blueMask) -> void; + + //static.hpp + static auto bitDepth(uint64_t color) -> uint; + static auto bitShift(uint64_t color) -> uint; + static auto normalize(uint64_t color, uint sourceDepth, uint targetDepth) -> uint64_t; + + //access + auto data() { return _data; } + auto data() const { return _data; } + auto width() const { return _width; } + auto height() const { return _height; } + + auto endian() const { return _endian; } + auto depth() const { return _depth; } + auto stride() const { return (_depth + 7) >> 3; } + + auto pitch() const { return _width * stride(); } + auto size() const { return _height * pitch(); } + + auto alpha() const { return _alpha; } + auto red() const { return _red; } + auto green() const { return _green; } + auto blue() const { return _blue; } + +private: + //core.hpp + auto allocate(uint width, uint height, uint stride) -> uint8_t*; + + //scale.hpp + auto scaleLinearWidth(uint width) -> void; + auto scaleLinearHeight(uint height) -> void; + auto scaleLinear(uint width, uint height) -> void; + auto scaleNearest(uint width, uint height) -> void; + + //load.hpp + auto loadBMP(const string& filename) -> bool; + auto loadBMP(const uint8_t* data, uint size) -> bool; + auto loadPNG(const string& filename) -> bool; + auto loadPNG(const uint8_t* data, uint size) -> bool; + + //interpolation.hpp + auto isplit(uint64_t* component, uint64_t color) -> void; + auto imerge(const uint64_t* component) -> uint64_t; + auto interpolate1f(uint64_t a, uint64_t b, double x) -> uint64_t; + auto interpolate1f(uint64_t a, uint64_t b, uint64_t c, uint64_t d, double x, double y) -> uint64_t; + auto interpolate1i(int64_t a, int64_t b, uint32_t x) -> uint64_t; + auto interpolate1i(int64_t a, int64_t b, int64_t c, int64_t d, uint32_t x, uint32_t y) -> uint64_t; + auto interpolate4f(uint64_t a, uint64_t b, double x) -> uint64_t; + auto interpolate4f(uint64_t a, uint64_t b, uint64_t c, uint64_t d, double x, double y) -> uint64_t; + auto interpolate4i(uint64_t a, uint64_t b, uint32_t x) -> uint64_t; + auto interpolate4i(uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint32_t x, uint32_t y) -> uint64_t; + + uint8_t* _data = nullptr; + uint _width = 0; + uint _height = 0; + + bool _endian = 0; //0 = lsb, 1 = msb + uint _depth = 32; + + channel _alpha{255u << 24, 8, 24}; + channel _red {255u << 16, 8, 16}; + channel _green{255u << 8, 8, 8}; + channel _blue {255u << 0, 8, 0}; +}; + +} + +#include +#include +#include +#include +#include +#include +#include +#include diff --git a/roms/snes-test-roms/bass-untech/nall/image/blend.hpp b/roms/snes-test-roms/bass-untech/nall/image/blend.hpp new file mode 100644 index 00000000..2898fceb --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/blend.hpp @@ -0,0 +1,71 @@ +#pragma once + +namespace nall { + +inline auto image::impose(blend mode, uint targetX, uint targetY, image source, uint sourceX, uint sourceY, uint sourceWidth, uint sourceHeight) -> void { + source.transform(_endian, _depth, _alpha.mask(), _red.mask(), _green.mask(), _blue.mask()); + + for(uint y = 0; y < sourceHeight; y++) { + const uint8_t* sp = source._data + source.pitch() * (sourceY + y) + source.stride() * sourceX; + uint8_t* dp = _data + pitch() * (targetY + y) + stride() * targetX; + for(uint x = 0; x < sourceWidth; x++) { + uint64_t sourceColor = source.read(sp); + uint64_t targetColor = read(dp); + + int64_t sa = (sourceColor & _alpha.mask()) >> _alpha.shift(); + int64_t sr = (sourceColor & _red.mask() ) >> _red.shift(); + int64_t sg = (sourceColor & _green.mask()) >> _green.shift(); + int64_t sb = (sourceColor & _blue.mask() ) >> _blue.shift(); + + int64_t da = (targetColor & _alpha.mask()) >> _alpha.shift(); + int64_t dr = (targetColor & _red.mask() ) >> _red.shift(); + int64_t dg = (targetColor & _green.mask()) >> _green.shift(); + int64_t db = (targetColor & _blue.mask() ) >> _blue.shift(); + + uint64_t a, r, g, b; + + switch(mode) { + case blend::add: + a = max(sa, da); + r = min(_red.mask() >> _red.shift(), ((sr * sa) >> _alpha.depth()) + ((dr * da) >> _alpha.depth())); + g = min(_green.mask() >> _green.shift(), ((sg * sa) >> _alpha.depth()) + ((dg * da) >> _alpha.depth())); + b = min(_blue.mask() >> _blue.shift(), ((sb * sa) >> _alpha.depth()) + ((db * da) >> _alpha.depth())); + break; + + case blend::sourceAlpha: + a = max(sa, da); + r = dr + (((sr - dr) * sa) >> _alpha.depth()); + g = dg + (((sg - dg) * sa) >> _alpha.depth()); + b = db + (((sb - db) * sa) >> _alpha.depth()); + break; + + case blend::sourceColor: + a = sa; + r = sr; + g = sg; + b = sb; + break; + + case blend::targetAlpha: + a = max(sa, da); + r = sr + (((dr - sr) * da) >> _alpha.depth()); + g = sg + (((dg - sg) * da) >> _alpha.depth()); + b = sb + (((db - sb) * da) >> _alpha.depth()); + break; + + case blend::targetColor: + a = da; + r = dr; + g = dg; + b = db; + break; + } + + write(dp, (a << _alpha.shift()) | (r << _red.shift()) | (g << _green.shift()) | (b << _blue.shift())); + sp += source.stride(); + dp += stride(); + } + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/core.hpp b/roms/snes-test-roms/bass-untech/nall/image/core.hpp new file mode 100644 index 00000000..1fd38ff6 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/core.hpp @@ -0,0 +1,173 @@ +#pragma once + +namespace nall { + +inline image::image(const image& source) { + operator=(source); +} + +inline image::image(image&& source) { + operator=(forward(source)); +} + +inline image::image(bool endian, uint depth, uint64_t alphaMask, uint64_t redMask, uint64_t greenMask, uint64_t blueMask) { + _endian = endian; + _depth = depth; + + _alpha = {alphaMask, bitDepth(alphaMask), bitShift(alphaMask)}; + _red = {redMask, bitDepth(redMask), bitShift(redMask )}; + _green = {greenMask, bitDepth(greenMask), bitShift(greenMask)}; + _blue = {blueMask, bitDepth(blueMask), bitShift(blueMask )}; +} + +inline image::image(const string& filename) { + load(filename); +} + +inline image::image(const void* data_, uint size) { + auto data = (const uint8_t*)data_; + if(size < 4); + else if(data[0] == 'B' && data[1] == 'M') loadBMP(data, size); + else if(data[1] == 'P' && data[2] == 'N' && data[3] == 'G') loadPNG(data, size); +} + +inline image::image(const vector& buffer) : image(buffer.data(), buffer.size()) { +} + +template inline image::image(const uint8_t (&Name)[Size]) : image(Name, Size) { +} + +inline image::image() { +} + +inline image::~image() { + free(); +} + +inline auto image::operator=(const image& source) -> image& { + if(this == &source) return *this; + free(); + + _width = source._width; + _height = source._height; + + _endian = source._endian; + _depth = source._depth; + + _alpha = source._alpha; + _red = source._red; + _green = source._green; + _blue = source._blue; + + _data = allocate(_width, _height, stride()); + memory::copy(_data, source._data, source.size()); + return *this; +} + +inline auto image::operator=(image&& source) -> image& { + if(this == &source) return *this; + free(); + + _width = source._width; + _height = source._height; + + _endian = source._endian; + _depth = source._depth; + + _alpha = source._alpha; + _red = source._red; + _green = source._green; + _blue = source._blue; + + _data = source._data; + source._data = nullptr; + return *this; +} + +inline image::operator bool() const { + return _data && _width && _height; +} + +inline auto image::operator==(const image& source) const -> bool { + if(_width != source._width) return false; + if(_height != source._height) return false; + + if(_endian != source._endian) return false; + if(_depth != source._depth) return false; + + if(_alpha != source._alpha) return false; + if(_red != source._red) return false; + if(_green != source._green) return false; + if(_blue != source._blue) return false; + + return memory::compare(_data, source._data, size()) == 0; +} + +inline auto image::operator!=(const image& source) const -> bool { + return !operator==(source); +} + +inline auto image::read(const uint8_t* data) const -> uint64_t { + uint64_t result = 0; + if(_endian == 0) { + for(int n = stride() - 1; n >= 0; n--) result = (result << 8) | data[n]; + } else { + for(int n = 0; n < stride(); n++) result = (result << 8) | data[n]; + } + return result; +} + +inline auto image::write(uint8_t* data, uint64_t value) const -> void { + if(_endian == 0) { + for(int n = 0; n < stride(); n++) { + data[n] = value; + value >>= 8; + } + } else { + for(int n = stride() - 1; n >= 0; n--) { + data[n] = value; + value >>= 8; + } + } +} + +inline auto image::free() -> void { + if(_data) delete[] _data; + _data = nullptr; +} + +inline auto image::load(const string& filename) -> bool { + if(loadBMP(filename) == true) return true; + if(loadPNG(filename) == true) return true; + return false; +} + +//assumes image and data are in the same format; pitch is adapted to image +inline auto image::copy(const void* data, uint pitch, uint width, uint height) -> void { + allocate(width, height); + for(uint y : range(height)) { + auto input = (const uint8_t*)data + y * pitch; + auto output = (uint8_t*)_data + y * this->pitch(); + memory::copy(output, input, width * stride()); + } +} + +inline auto image::allocate(uint width, uint height) -> void { + if(_data && _width == width && _height == height) return; + free(); + _width = width; + _height = height; + _data = allocate(_width, _height, stride()); +} + +//private +inline auto image::allocate(uint width, uint height, uint stride) -> uint8_t* { + //allocate 1x1 larger than requested; so that linear interpolation does not require bounds-checking + uint size = width * height * stride; + uint padding = width * stride + stride; + auto data = new uint8_t[size + padding]; + memory::fill(data + size, padding); + return data; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/fill.hpp b/roms/snes-test-roms/bass-untech/nall/image/fill.hpp new file mode 100644 index 00000000..a2ba2a74 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/fill.hpp @@ -0,0 +1,84 @@ +#pragma once + +namespace nall { + +inline auto image::fill(uint64_t color) -> void { + for(uint y = 0; y < _height; y++) { + uint8_t* dp = _data + pitch() * y; + for(uint x = 0; x < _width; x++) { + write(dp, color); + dp += stride(); + } + } +} + +inline auto image::gradient(uint64_t a, uint64_t b, uint64_t c, uint64_t d) -> void { + for(uint y = 0; y < _height; y++) { + uint8_t* dp = _data + pitch() * y; + double muY = (double)y / (double)_height; + for(uint x = 0; x < _width; x++) { + double muX = (double)x / (double)_width; + write(dp, interpolate4f(a, b, c, d, muX, muY)); + dp += stride(); + } + } +} + +inline auto image::gradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY, function callback) -> void { + for(int y = 0; y < _height; y++) { + uint8_t* dp = _data + pitch() * y; + double py = max(-radiusY, min(+radiusY, y - centerY)) * 1.0 / radiusY; + for(int x = 0; x < _width; x++) { + double px = max(-radiusX, min(+radiusX, x - centerX)) * 1.0 / radiusX; + double mu = max(0.0, min(1.0, callback(px, py))); + if(mu != mu) mu = 1.0; //NaN + write(dp, interpolate4f(a, b, mu)); + dp += stride(); + } + } +} + +inline auto image::crossGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + x = fabs(x), y = fabs(y); + return min(x, y) * min(x, y); + }); +} + +inline auto image::diamondGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return fabs(x) + fabs(y); + }); +} + +inline auto image::horizontalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return fabs(x); + }); +} + +inline auto image::radialGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return sqrt(x * x + y * y); + }); +} + +inline auto image::sphericalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return x * x + y * y; + }); +} + +inline auto image::squareGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return max(fabs(x), fabs(y)); + }); +} + +inline auto image::verticalGradient(uint64_t a, uint64_t b, int radiusX, int radiusY, int centerX, int centerY) -> void { + return gradient(a, b, radiusX, radiusY, centerX, centerY, [](double x, double y) -> double { + return fabs(y); + }); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/interpolation.hpp b/roms/snes-test-roms/bass-untech/nall/image/interpolation.hpp new file mode 100644 index 00000000..a88e6c21 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/interpolation.hpp @@ -0,0 +1,62 @@ +#pragma once + +namespace nall { + +inline auto image::isplit(uint64_t* c, uint64_t color) -> void { + c[0] = (color & _alpha.mask()) >> _alpha.shift(); + c[1] = (color & _red.mask() ) >> _red.shift(); + c[2] = (color & _green.mask()) >> _green.shift(); + c[3] = (color & _blue.mask() ) >> _blue.shift(); +} + +inline auto image::imerge(const uint64_t* c) -> uint64_t { + return c[0] << _alpha.shift() | c[1] << _red.shift() | c[2] << _green.shift() | c[3] << _blue.shift(); +} + +inline auto image::interpolate1f(uint64_t a, uint64_t b, double x) -> uint64_t { + return a * (1.0 - x) + b * x; +} + +inline auto image::interpolate1f(uint64_t a, uint64_t b, uint64_t c, uint64_t d, double x, double y) -> uint64_t { + return a * (1.0 - x) * (1.0 - y) + b * x * (1.0 - y) + c * (1.0 - x) * y + d * x * y; +} + +inline auto image::interpolate1i(int64_t a, int64_t b, uint32_t x) -> uint64_t { + return a + (((b - a) * x) >> 32); //a + (b - a) * x +} + +inline auto image::interpolate1i(int64_t a, int64_t b, int64_t c, int64_t d, uint32_t x, uint32_t y) -> uint64_t { + a = a + (((b - a) * x) >> 32); //a + (b - a) * x + c = c + (((d - c) * x) >> 32); //c + (d - c) * x + return a + (((c - a) * y) >> 32); //a + (c - a) * y +} + +inline auto image::interpolate4f(uint64_t a, uint64_t b, double x) -> uint64_t { + uint64_t o[4], pa[4], pb[4]; + isplit(pa, a), isplit(pb, b); + for(uint n = 0; n < 4; n++) o[n] = interpolate1f(pa[n], pb[n], x); + return imerge(o); +} + +inline auto image::interpolate4f(uint64_t a, uint64_t b, uint64_t c, uint64_t d, double x, double y) -> uint64_t { + uint64_t o[4], pa[4], pb[4], pc[4], pd[4]; + isplit(pa, a), isplit(pb, b), isplit(pc, c), isplit(pd, d); + for(uint n = 0; n < 4; n++) o[n] = interpolate1f(pa[n], pb[n], pc[n], pd[n], x, y); + return imerge(o); +} + +inline auto image::interpolate4i(uint64_t a, uint64_t b, uint32_t x) -> uint64_t { + uint64_t o[4], pa[4], pb[4]; + isplit(pa, a), isplit(pb, b); + for(uint n = 0; n < 4; n++) o[n] = interpolate1i(pa[n], pb[n], x); + return imerge(o); +} + +inline auto image::interpolate4i(uint64_t a, uint64_t b, uint64_t c, uint64_t d, uint32_t x, uint32_t y) -> uint64_t { + uint64_t o[4], pa[4], pb[4], pc[4], pd[4]; + isplit(pa, a), isplit(pb, b), isplit(pc, c), isplit(pd, d); + for(uint n = 0; n < 4; n++) o[n] = interpolate1i(pa[n], pb[n], pc[n], pd[n], x, y); + return imerge(o); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/load.hpp b/roms/snes-test-roms/bass-untech/nall/image/load.hpp new file mode 100644 index 00000000..8733dac2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/load.hpp @@ -0,0 +1,99 @@ +#pragma once + +namespace nall { + +inline auto image::loadBMP(const string& filename) -> bool { + if(!file::exists(filename)) return false; + auto buffer = file::read(filename); + return loadBMP(buffer.data(), buffer.size()); +} + +inline auto image::loadBMP(const uint8_t* bmpData, uint bmpSize) -> bool { + Decode::BMP source; + if(!source.load(bmpData, bmpSize)) return false; + + allocate(source.width(), source.height()); + const uint32_t* sp = source.data(); + uint8_t* dp = _data; + + for(uint y = 0; y < _height; y++) { + for(uint x = 0; x < _width; x++) { + uint32_t color = *sp++; + uint64_t a = normalize((uint8_t)(color >> 24), 8, _alpha.depth()); + uint64_t r = normalize((uint8_t)(color >> 16), 8, _red.depth()); + uint64_t g = normalize((uint8_t)(color >> 8), 8, _green.depth()); + uint64_t b = normalize((uint8_t)(color >> 0), 8, _blue.depth()); + write(dp, (a << _alpha.shift()) | (r << _red.shift()) | (g << _green.shift()) | (b << _blue.shift())); + dp += stride(); + } + } + + return true; +} + +inline auto image::loadPNG(const string& filename) -> bool { + if(!file::exists(filename)) return false; + auto buffer = file::read(filename); + return loadPNG(buffer.data(), buffer.size()); +} + +inline auto image::loadPNG(const uint8_t* pngData, uint pngSize) -> bool { + Decode::PNG source; + if(!source.load(pngData, pngSize)) return false; + + allocate(source.info.width, source.info.height); + const uint8_t* sp = source.data; + uint8_t* dp = _data; + + auto decode = [&]() -> uint64_t { + uint64_t p, r, g, b, a; + + switch(source.info.colorType) { + case 0: //L + r = g = b = source.readbits(sp); + a = (1 << source.info.bitDepth) - 1; + break; + case 2: //R,G,B + r = source.readbits(sp); + g = source.readbits(sp); + b = source.readbits(sp); + a = (1 << source.info.bitDepth) - 1; + break; + case 3: //P + p = source.readbits(sp); + r = source.info.palette[p][0]; + g = source.info.palette[p][1]; + b = source.info.palette[p][2]; + a = (1 << source.info.bitDepth) - 1; + break; + case 4: //L,A + r = g = b = source.readbits(sp); + a = source.readbits(sp); + break; + case 6: //R,G,B,A + r = source.readbits(sp); + g = source.readbits(sp); + b = source.readbits(sp); + a = source.readbits(sp); + break; + } + + a = normalize(a, source.info.bitDepth, _alpha.depth()); + r = normalize(r, source.info.bitDepth, _red.depth()); + g = normalize(g, source.info.bitDepth, _green.depth()); + b = normalize(b, source.info.bitDepth, _blue.depth()); + + return (a << _alpha.shift()) | (r << _red.shift()) | (g << _green.shift()) | (b << _blue.shift()); + }; + + for(uint y = 0; y < _height; y++) { + for(uint x = 0; x < _width; x++) { + write(dp, decode()); + dp += stride(); + } + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/scale.hpp b/roms/snes-test-roms/bass-untech/nall/image/scale.hpp new file mode 100644 index 00000000..21a461c9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/scale.hpp @@ -0,0 +1,177 @@ +#pragma once + +namespace nall { + +inline auto image::scale(uint outputWidth, uint outputHeight, bool linear) -> void { + if(!_data) return; + if(_width == outputWidth && _height == outputHeight) return; //no scaling necessary + if(linear == false) return scaleNearest(outputWidth, outputHeight); + + if(_width == outputWidth ) return scaleLinearHeight(outputHeight); + if(_height == outputHeight) return scaleLinearWidth(outputWidth); + + //find fastest scaling method, based on number of interpolation operations required + //magnification usually benefits from two-pass linear interpolation + //minification usually benefits from one-pass bilinear interpolation + uint d1wh = ((_width * outputWidth ) + (outputWidth * outputHeight)) * 1; + uint d1hw = ((_height * outputHeight) + (outputWidth * outputHeight)) * 1; + uint d2wh = (outputWidth * outputHeight) * 3; + + if(d1wh <= d1hw && d1wh <= d2wh) return scaleLinearWidth(outputWidth), scaleLinearHeight(outputHeight); + if(d1hw <= d2wh) return scaleLinearHeight(outputHeight), scaleLinearWidth(outputWidth); + return scaleLinear(outputWidth, outputHeight); +} + +inline auto image::scaleLinearWidth(uint outputWidth) -> void { + uint8_t* outputData = allocate(outputWidth, _height, stride()); + uint outputPitch = outputWidth * stride(); + uint64_t xstride = ((uint64_t)(_width - 1) << 32) / max(1u, outputWidth - 1); + + for(uint y = 0; y < _height; y++) { + uint64_t xfraction = 0; + + const uint8_t* sp = _data + pitch() * y; + uint8_t* dp = outputData + outputPitch * y; + + uint64_t a = read(sp); + uint64_t b = read(sp + stride()); + sp += stride(); + + uint x = 0; + while(true) { + while(xfraction < 0x100000000 && x++ < outputWidth) { + write(dp, interpolate4i(a, b, xfraction)); + dp += stride(); + xfraction += xstride; + } + if(x >= outputWidth) break; + + sp += stride(); + a = b; + b = read(sp); + xfraction -= 0x100000000; + } + } + + free(); + _data = outputData; + _width = outputWidth; +} + +inline auto image::scaleLinearHeight(uint outputHeight) -> void { + uint8_t* outputData = allocate(_width, outputHeight, stride()); + uint64_t ystride = ((uint64_t)(_height - 1) << 32) / max(1u, outputHeight - 1); + + for(uint x = 0; x < _width; x++) { + uint64_t yfraction = 0; + + const uint8_t* sp = _data + stride() * x; + uint8_t* dp = outputData + stride() * x; + + uint64_t a = read(sp); + uint64_t b = read(sp + pitch()); + sp += pitch(); + + uint y = 0; + while(true) { + while(yfraction < 0x100000000 && y++ < outputHeight) { + write(dp, interpolate4i(a, b, yfraction)); + dp += pitch(); + yfraction += ystride; + } + if(y >= outputHeight) break; + + sp += pitch(); + a = b; + b = read(sp); + yfraction -= 0x100000000; + } + } + + free(); + _data = outputData; + _height = outputHeight; +} + +inline auto image::scaleLinear(uint outputWidth, uint outputHeight) -> void { + uint8_t* outputData = allocate(outputWidth, outputHeight, stride()); + uint outputPitch = outputWidth * stride(); + + uint64_t xstride = ((uint64_t)(_width - 1) << 32) / max(1u, outputWidth - 1); + uint64_t ystride = ((uint64_t)(_height - 1) << 32) / max(1u, outputHeight - 1); + + for(uint y = 0; y < outputHeight; y++) { + uint64_t yfraction = ystride * y; + uint64_t xfraction = 0; + + const uint8_t* sp = _data + pitch() * (yfraction >> 32); + uint8_t* dp = outputData + outputPitch * y; + + uint64_t a = read(sp); + uint64_t b = read(sp + stride()); + uint64_t c = read(sp + pitch()); + uint64_t d = read(sp + pitch() + stride()); + sp += stride(); + + uint x = 0; + while(true) { + while(xfraction < 0x100000000 && x++ < outputWidth) { + write(dp, interpolate4i(a, b, c, d, xfraction, yfraction)); + dp += stride(); + xfraction += xstride; + } + if(x >= outputWidth) break; + + sp += stride(); + a = b; + c = d; + b = read(sp); + d = read(sp + pitch()); + xfraction -= 0x100000000; + } + } + + free(); + _data = outputData; + _width = outputWidth; + _height = outputHeight; +} + +inline auto image::scaleNearest(uint outputWidth, uint outputHeight) -> void { + uint8_t* outputData = allocate(outputWidth, outputHeight, stride()); + uint outputPitch = outputWidth * stride(); + + uint64_t xstride = ((uint64_t)_width << 32) / outputWidth; + uint64_t ystride = ((uint64_t)_height << 32) / outputHeight; + + for(uint y = 0; y < outputHeight; y++) { + uint64_t yfraction = ystride * y; + uint64_t xfraction = 0; + + const uint8_t* sp = _data + pitch() * (yfraction >> 32); + uint8_t* dp = outputData + outputPitch * y; + + uint64_t a = read(sp); + + uint x = 0; + while(true) { + while(xfraction < 0x100000000 && x++ < outputWidth) { + write(dp, a); + dp += stride(); + xfraction += xstride; + } + if(x >= outputWidth) break; + + sp += stride(); + a = read(sp); + xfraction -= 0x100000000; + } + } + + free(); + _data = outputData; + _width = outputWidth; + _height = outputHeight; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/static.hpp b/roms/snes-test-roms/bass-untech/nall/image/static.hpp new file mode 100644 index 00000000..5bd2ded4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/static.hpp @@ -0,0 +1,28 @@ +#pragma once + +namespace nall { + +inline auto image::bitDepth(uint64_t color) -> uint { + uint depth = 0; + if(color) while((color & 1) == 0) color >>= 1; + while((color & 1) == 1) { color >>= 1; depth++; } + return depth; +} + +inline auto image::bitShift(uint64_t color) -> uint { + uint shift = 0; + if(color) while((color & 1) == 0) { color >>= 1; shift++; } + return shift; +} + +inline auto image::normalize(uint64_t color, uint sourceDepth, uint targetDepth) -> uint64_t { + if(sourceDepth == 0 || targetDepth == 0) return 0; + while(sourceDepth < targetDepth) { + color = (color << sourceDepth) | color; + sourceDepth += sourceDepth; + } + if(targetDepth < sourceDepth) color >>= (sourceDepth - targetDepth); + return color; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/image/utility.hpp b/roms/snes-test-roms/bass-untech/nall/image/utility.hpp new file mode 100644 index 00000000..a7b0151d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/image/utility.hpp @@ -0,0 +1,179 @@ +#pragma once + +namespace nall { + +//scan all four sides of the image for fully transparent pixels, and then crop them +//imagine an icon centered on a transparent background: this function removes the bordering +//this certainly won't win any speed awards, but nall::image is meant to be correct and simple, not fast +inline auto image::shrink(uint64_t transparentColor) -> void { + //top + { uint padding = 0; + for(uint y : range(_height)) { + const uint8_t* sp = _data + pitch() * y; + bool found = false; + for(uint x : range(_width)) { + if(read(sp) != transparentColor) { found = true; break; } + sp += stride(); + } + if(found) break; + padding++; + } + crop(0, padding, _width, _height - padding); + } + + //bottom + { uint padding = 0; + for(uint y : reverse(range(_height))) { + const uint8_t* sp = _data + pitch() * y; + bool found = false; + for(uint x : range(_width)) { + if(read(sp) != transparentColor) { found = true; break; } + sp += stride(); + } + if(found) break; + padding++; + } + crop(0, 0, _width, _height - padding); + } + + //left + { uint padding = 0; + for(uint x : range(_width)) { + const uint8_t* sp = _data + stride() * x; + bool found = false; + for(uint y : range(_height)) { + if(read(sp) != transparentColor) { found = true; break; } + sp += pitch(); + } + if(found) break; + padding++; + } + crop(padding, 0, _width - padding, _height); + } + + //right + { uint padding = 0; + for(uint x : reverse(range(_width))) { + const uint8_t* sp = _data + stride() * x; + bool found = false; + for(uint y : range(_height)) { + if(read(sp) != transparentColor) { found = true; break; } + sp += pitch(); + } + if(found) break; + padding++; + } + crop(0, 0, _width - padding, _height); + } +} + +inline auto image::crop(uint outputX, uint outputY, uint outputWidth, uint outputHeight) -> bool { + if(outputX + outputWidth > _width) return false; + if(outputY + outputHeight > _height) return false; + + uint8_t* outputData = allocate(outputWidth, outputHeight, stride()); + uint outputPitch = outputWidth * stride(); + + for(uint y = 0; y < outputHeight; y++) { + const uint8_t* sp = _data + pitch() * (outputY + y) + stride() * outputX; + uint8_t* dp = outputData + outputPitch * y; + for(uint x = 0; x < outputWidth; x++) { + write(dp, read(sp)); + sp += stride(); + dp += stride(); + } + } + + delete[] _data; + _data = outputData; + _width = outputWidth; + _height = outputHeight; + return true; +} + +inline auto image::alphaBlend(uint64_t alphaColor) -> void { + uint64_t alphaR = (alphaColor & _red.mask() ) >> _red.shift(); + uint64_t alphaG = (alphaColor & _green.mask()) >> _green.shift(); + uint64_t alphaB = (alphaColor & _blue.mask() ) >> _blue.shift(); + + for(uint y = 0; y < _height; y++) { + uint8_t* dp = _data + pitch() * y; + for(uint x = 0; x < _width; x++) { + uint64_t color = read(dp); + + uint64_t colorA = (color & _alpha.mask()) >> _alpha.shift(); + uint64_t colorR = (color & _red.mask() ) >> _red.shift(); + uint64_t colorG = (color & _green.mask()) >> _green.shift(); + uint64_t colorB = (color & _blue.mask() ) >> _blue.shift(); + double alphaScale = (double)colorA / (double)((1 << _alpha.depth()) - 1); + + colorA = (1 << _alpha.depth()) - 1; + colorR = (colorR * alphaScale) + (alphaR * (1.0 - alphaScale)); + colorG = (colorG * alphaScale) + (alphaG * (1.0 - alphaScale)); + colorB = (colorB * alphaScale) + (alphaB * (1.0 - alphaScale)); + + write(dp, (colorA << _alpha.shift()) | (colorR << _red.shift()) | (colorG << _green.shift()) | (colorB << _blue.shift())); + dp += stride(); + } + } +} + +inline auto image::alphaMultiply() -> void { + uint divisor = (1 << _alpha.depth()) - 1; + + for(uint y = 0; y < _height; y++) { + uint8_t* dp = _data + pitch() * y; + for(uint x = 0; x < _width; x++) { + uint64_t color = read(dp); + + uint64_t colorA = (color & _alpha.mask()) >> _alpha.shift(); + uint64_t colorR = (color & _red.mask() ) >> _red.shift(); + uint64_t colorG = (color & _green.mask()) >> _green.shift(); + uint64_t colorB = (color & _blue.mask() ) >> _blue.shift(); + + colorR = (colorR * colorA) / divisor; + colorG = (colorG * colorA) / divisor; + colorB = (colorB * colorA) / divisor; + + write(dp, (colorA << _alpha.shift()) | (colorR << _red.shift()) | (colorG << _green.shift()) | (colorB << _blue.shift())); + dp += stride(); + } + } +} + +inline auto image::transform(const image& source) -> void { + return transform(source._endian, source._depth, source._alpha.mask(), source._red.mask(), source._green.mask(), source._blue.mask()); +} + +inline auto image::transform(bool outputEndian, uint outputDepth, uint64_t outputAlphaMask, uint64_t outputRedMask, uint64_t outputGreenMask, uint64_t outputBlueMask) -> void { + if(_endian == outputEndian && _depth == outputDepth && _alpha.mask() == outputAlphaMask && _red.mask() == outputRedMask && _green.mask() == outputGreenMask && _blue.mask() == outputBlueMask) return; + + image output(outputEndian, outputDepth, outputAlphaMask, outputRedMask, outputGreenMask, outputBlueMask); + output.allocate(_width, _height); + + for(uint y = 0; y < _height; y++) { + const uint8_t* sp = _data + pitch() * y; + uint8_t* dp = output._data + output.pitch() * y; + for(uint x = 0; x < _width; x++) { + uint64_t color = read(sp); + sp += stride(); + + uint64_t a = (color & _alpha.mask()) >> _alpha.shift(); + uint64_t r = (color & _red.mask() ) >> _red.shift(); + uint64_t g = (color & _green.mask()) >> _green.shift(); + uint64_t b = (color & _blue.mask() ) >> _blue.shift(); + + a = normalize(a, _alpha.depth(), output._alpha.depth()); + r = normalize(r, _red.depth(), output._red.depth()); + g = normalize(g, _green.depth(), output._green.depth()); + b = normalize(b, _blue.depth(), output._blue.depth()); + + output.write(dp, (a << output._alpha.shift()) | (r << output._red.shift()) | (g << output._green.shift()) | (b << output._blue.shift())); + dp += output.stride(); + } + } + + operator=(move(output)); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/induced-sort.hpp b/roms/snes-test-roms/bass-untech/nall/induced-sort.hpp new file mode 100644 index 00000000..c544a893 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/induced-sort.hpp @@ -0,0 +1,176 @@ +#pragma once + +//suffix array construction via induced sorting +//many thanks to Screwtape for the thorough explanation of this algorithm +//this implementation would not be possible without his help + +namespace nall { + +//note that induced_sort will return an array of size+1 characters, +//where the first character is the empty suffix, equal to size + +template +inline auto induced_sort(array_view data, const uint characters = 256) -> vector { + const uint size = data.size(); + if(size == 0) return vector{0}; //required to avoid out-of-bounds accesses + if(size == 1) return vector{1, 0}; //not strictly necessary; but more performant + + vector types; //0 = S-suffix (sort before next suffix), 1 = L-suffix (sort after next suffix) + types.resize(size + 1); + + types[size - 0] = 0; //empty suffix is always S-suffix + types[size - 1] = 1; //last suffix is always L-suffix compared to empty suffix + for(uint n : reverse(range(size - 1))) { + if(data[n] < data[n + 1]) { + types[n] = 0; //this suffix is smaller than the one after it + } else if(data[n] > data[n + 1]) { + types[n] = 1; //this suffix is larger than the one after it + } else { + types[n] = types[n + 1]; //this suffix will be the same as the one after it + } + } + + //left-most S-suffix + auto isLMS = [&](int n) -> bool { + if(n == 0) return 0; //no character to the left of the first suffix + return !types[n] && types[n - 1]; //true if this is the start of a new S-suffix + }; + + //test if two LMS-substrings are equal + auto isEqual = [&](int lhs, int rhs) -> bool { + if(lhs == size || rhs == size) return false; //no other suffix can be equal to the empty suffix + + for(uint n = 0;; n++) { + bool lhsLMS = isLMS(lhs + n); + bool rhsLMS = isLMS(rhs + n); + if(n && lhsLMS && rhsLMS) return true; //substrings are identical + if(lhsLMS != rhsLMS) return false; //length mismatch: substrings cannot be identical + if(data[lhs + n] != data[rhs + n]) return false; //character mismatch: substrings are different + } + }; + + //determine the sizes of each bucket: one bucket per character + vector counts; + counts.resize(characters); + for(uint n : range(size)) counts[data[n]]++; + + //bucket sorting start offsets + vector heads; + heads.resize(characters); + + uint headOffset; + auto getHeads = [&] { + headOffset = 1; + for(uint n : range(characters)) { + heads[n] = headOffset; + headOffset += counts[n]; + } + }; + + //bucket sorting end offsets + vector tails; + tails.resize(characters); + + uint tailOffset; + auto getTails = [&] { + tailOffset = 1; + for(uint n : range(characters)) { + tailOffset += counts[n]; + tails[n] = tailOffset - 1; + } + }; + + //inaccurate LMS bucket sort + vector suffixes; + suffixes.resize(size + 1, (int)-1); + + getTails(); + for(uint n : range(size)) { + if(!isLMS(n)) continue; //skip non-LMS-suffixes + suffixes[tails[data[n]]--] = n; //advance from the tail of the bucket + } + + suffixes[0] = size; //the empty suffix is always an LMS-suffix, and is the first suffix + + //sort all L-suffixes to the left of LMS-suffixes + auto sortL = [&] { + getHeads(); + for(uint n : range(size + 1)) { + if(suffixes[n] == -1) continue; //offsets may not be known yet here ... + auto l = suffixes[n] - 1; + if(l < 0 || !types[l]) continue; //skip S-suffixes + suffixes[heads[data[l]]++] = l; //advance from the head of the bucket + } + }; + + auto sortS = [&] { + getTails(); + for(uint n : reverse(range(size + 1))) { + auto l = suffixes[n] - 1; + if(l < 0 || types[l]) continue; //skip L-suffixes + suffixes[tails[data[l]]--] = l; //advance from the tail of the bucket + } + }; + + sortL(); + sortS(); + + //analyze data for the summary suffix array + vector names; + names.resize(size + 1, (int)-1); + + uint currentName = 0; //keep a count to tag each unique LMS-substring with unique IDs + auto lastLMSOffset = suffixes[0]; //location in the original data of the last checked LMS suffix + names[lastLMSOffset] = currentName; //the first LMS-substring is always the empty suffix entry, at position 0 + + for(uint n : range(1, size + 1)) { + auto offset = suffixes[n]; + if(!isLMS(offset)) continue; //only LMS suffixes are important + + //if this LMS suffix starts with a different LMS substring than the last suffix observed ... + if(!isEqual(lastLMSOffset, offset)) currentName++; //then it gets a new name + lastLMSOffset = offset; //keep track of the new most-recent LMS suffix + names[lastLMSOffset] = currentName; //store the LMS suffix name where the suffix appears at in the original data + } + + vector summaryOffsets; + vector summaryData; + for(uint n : range(size + 1)) { + if(names[n] == -1) continue; + summaryOffsets.append(n); + summaryData.append(names[n]); + } + uint summaryCharacters = currentName + 1; //zero-indexed, so the total unique characters is currentName + 1 + + //make the summary suffix array + vector summaries; + if(summaryData.size() == summaryCharacters) { + //simple bucket sort when every character in summaryData appears only once + summaries.resize(summaryData.size() + 1, (int)-1); + summaries[0] = summaryData.size(); //always include the empty suffix at the beginning + for(int x : range(summaryData.size())) { + int y = summaryData[x]; + summaries[y + 1] = x; + } + } else { + //recurse until every character in summaryData is unique ... + summaries = induced_sort({summaryData.data(), summaryData.size()}, summaryCharacters); + } + + suffixes.fill(-1); //reuse existing buffer for accurate sort + + //accurate LMS sort + getTails(); + for(uint n : reverse(range(2, summaries.size()))) { + auto index = summaryOffsets[summaries[n]]; + suffixes[tails[data[index]]--] = index; //advance from the tail of the bucket + } + suffixes[0] = size; //always include the empty suffix at the beginning + + sortL(); + sortS(); + + return suffixes; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/inline-if.hpp b/roms/snes-test-roms/bass-untech/nall/inline-if.hpp new file mode 100644 index 00000000..b7b7a865 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/inline-if.hpp @@ -0,0 +1,11 @@ +#pragma once +#warning "these defines break if statements with multiple parameters to templates" + +#define if1(statement) if(statement) +#define if2(condition, false) ([&](auto&& value) -> decltype(condition) { \ + return (bool)value ? value : (decltype(condition))false; \ +})(condition) +#define if3(condition, true, false) ((condition) ? (true) : (decltype(true))(false)) +#define if4(type, condition, true, false) ((condition) ? (type)(true) : (type)(false)) +#define if_(_1, _2, _3, _4, name, ...) name +#define if(...) if_(__VA_ARGS__, if4, if3, if2, if1)(__VA_ARGS__) diff --git a/roms/snes-test-roms/bass-untech/nall/inode.hpp b/roms/snes-test-roms/bass-untech/nall/inode.hpp new file mode 100644 index 00000000..89bebb24 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/inode.hpp @@ -0,0 +1,163 @@ +#pragma once + +//generic abstraction layer for common storage operations against both files and directories +//these functions are not recursive; use directory::create() and directory::remove() for recursion + +#include +#include + +namespace nall { + +struct inode { + enum class time : uint { create, modify, access }; + + inode() = delete; + inode(const inode&) = delete; + auto operator=(const inode&) -> inode& = delete; + + static auto exists(const string& name) -> bool { + return access(name, F_OK) == 0; + } + + static auto readable(const string& name) -> bool { + return access(name, R_OK) == 0; + } + + static auto writable(const string& name) -> bool { + return access(name, W_OK) == 0; + } + + static auto executable(const string& name) -> bool { + return access(name, X_OK) == 0; + } + + static auto hidden(const string& name) -> bool { + #if defined(PLATFORM_WINDOWS) + auto attributes = GetFileAttributes(utf16_t(name)); + return attributes & FILE_ATTRIBUTE_HIDDEN; + #else + //todo: is this really the best way to do this? stat doesn't have S_ISHIDDEN ... + return name.split("/").last().beginsWith("."); + #endif + } + + static auto mode(const string& name) -> uint { + struct stat data{}; + stat(name, &data); + return data.st_mode; + } + + static auto uid(const string& name) -> uint { + struct stat data{}; + stat(name, &data); + return data.st_uid; + } + + static auto gid(const string& name) -> uint { + struct stat data{}; + stat(name, &data); + return data.st_gid; + } + + static auto owner(const string& name) -> string { + #if !defined(PLATFORM_WINDOWS) + struct passwd* pw = getpwuid(uid(name)); + if(pw && pw->pw_name) return pw->pw_name; + #endif + return {}; + } + + static auto group(const string& name) -> string { + #if !defined(PLATFORM_WINDOWS) + struct group* gr = getgrgid(gid(name)); + if(gr && gr->gr_name) return gr->gr_name; + #endif + return {}; + } + + static auto timestamp(const string& name, time mode = time::modify) -> uint64_t { + struct stat data{}; + stat(name, &data); + switch(mode) { + #if defined(PLATFORM_WINDOWS) + //on Windows, the last status change time (ctime) holds the file creation time instead + case time::create: return data.st_ctime; + #elif defined(PLATFORM_BSD) || defined(PLATFORM_MACOS) + //st_birthtime may return -1 or st_atime if it is not supported by the file system + //the best that can be done in this case is to return st_mtime if it's older + case time::create: return min((uint)data.st_birthtime, (uint)data.st_mtime); + #else + //Linux simply doesn't support file creation time at all + //this is also our fallback case for unsupported operating systems + case time::create: return data.st_mtime; + #endif + case time::modify: return data.st_mtime; + //for performance reasons, last access time is usually not enabled on various filesystems + //ensure that the last access time is not older than the last modify time (eg for NTFS) + case time::access: return max((uint)data.st_atime, data.st_mtime); + } + return 0; + } + + static auto setMode(const string& name, uint mode) -> bool { + #if !defined(PLATFORM_WINDOWS) + return chmod(name, mode) == 0; + #else + return _wchmod(utf16_t(name), (mode & 0400 ? _S_IREAD : 0) | (mode & 0200 ? _S_IWRITE : 0)) == 0; + #endif + } + + static auto setOwner(const string& name, const string& owner) -> bool { + #if !defined(PLATFORM_WINDOWS) + struct passwd* pwd = getpwnam(owner); + if(!pwd) return false; + return chown(name, pwd->pw_uid, inode::gid(name)) == 0; + #else + return true; + #endif + } + + static auto setGroup(const string& name, const string& group) -> bool { + #if !defined(PLATFORM_WINDOWS) + struct group* grp = getgrnam(group); + if(!grp) return false; + return chown(name, inode::uid(name), grp->gr_gid) == 0; + #else + return true; + #endif + } + + static auto setTimestamp(const string& name, uint64_t value, time mode = time::modify) -> bool { + struct utimbuf timeBuffer; + timeBuffer.modtime = mode == time::modify ? value : inode::timestamp(name, time::modify); + timeBuffer.actime = mode == time::access ? value : inode::timestamp(name, time::access); + return utime(name, &timeBuffer) == 0; + } + + //returns true if 'name' already exists + static auto create(const string& name, uint permissions = 0755) -> bool { + if(exists(name)) return true; + if(name.endsWith("/")) return mkdir(name, permissions) == 0; + int fd = open(name, O_CREAT | O_EXCL, permissions); + if(fd < 0) return false; + return close(fd), true; + } + + //returns false if 'name' and 'targetname' are on different file systems (requires copy) + static auto rename(const string& name, const string& targetname) -> bool { + return ::rename(name, targetname) == 0; + } + + //returns false if 'name' is a directory that is not empty + static auto remove(const string& name) -> bool { + #if defined(PLATFORM_WINDOWS) + if(name.endsWith("/")) return _wrmdir(utf16_t(name)) == 0; + return _wunlink(utf16_t(name)) == 0; + #else + if(name.endsWith("/")) return rmdir(name) == 0; + return unlink(name) == 0; + #endif + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/instance.hpp b/roms/snes-test-roms/bass-untech/nall/instance.hpp new file mode 100644 index 00000000..a3cbcedc --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/instance.hpp @@ -0,0 +1,39 @@ +#pragma once + +namespace nall { + +template +struct Instance { + ~Instance() { + destruct(); + } + + auto operator()() -> T& { + return instance.object; + } + + template + auto construct(P&&... p) { + if(constructed) return; + constructed = true; + new((void*)(&instance.object)) T(forward

(p)...); + } + + auto destruct() -> void { + if(!constructed) return; + constructed = false; + instance.object.~T(); + } + +private: + bool constructed = false; + union Union { + Union() {} + ~Union() {} + + T object; + char storage[sizeof(T)]; + } instance; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/interpolation.hpp b/roms/snes-test-roms/bass-untech/nall/interpolation.hpp new file mode 100644 index 00000000..007f2ec2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/interpolation.hpp @@ -0,0 +1,56 @@ +#pragma once + +namespace nall { + +struct Interpolation { + static inline auto Nearest(double mu, double a, double b, double c, double d) -> double { + return (mu <= 0.5 ? b : c); + } + + static inline auto Sublinear(double mu, double a, double b, double c, double d) -> double { + mu = ((mu - 0.5) * 2.0) + 0.5; + if(mu < 0) mu = 0; + if(mu > 1) mu = 1; + return b * (1.0 - mu) + c * mu; + } + + static inline auto Linear(double mu, double a, double b, double c, double d) -> double { + return b * (1.0 - mu) + c * mu; + } + + static inline auto Cosine(double mu, double a, double b, double c, double d) -> double { + mu = (1.0 - cos(mu * Math::Pi)) / 2.0; + return b * (1.0 - mu) + c * mu; + } + + static inline auto Cubic(double mu, double a, double b, double c, double d) -> double { + double A = d - c - a + b; + double B = a - b - A; + double C = c - a; + double D = b; + return A * (mu * mu * mu) + B * (mu * mu) + C * mu + D; + } + + static inline auto Hermite(double mu1, double a, double b, double c, double d) -> double { + const double tension = 0.0; //-1 = low, 0 = normal, +1 = high + const double bias = 0.0; //-1 = left, 0 = even, +1 = right + double mu2, mu3, m0, m1, a0, a1, a2, a3; + + mu2 = mu1 * mu1; + mu3 = mu2 * mu1; + + m0 = (b - a) * (1.0 + bias) * (1.0 - tension) / 2.0; + m0 += (c - b) * (1.0 - bias) * (1.0 - tension) / 2.0; + m1 = (c - b) * (1.0 + bias) * (1.0 - tension) / 2.0; + m1 += (d - c) * (1.0 - bias) * (1.0 - tension) / 2.0; + + a0 = +2 * mu3 - 3 * mu2 + 1; + a1 = mu3 - 2 * mu2 + mu1; + a2 = mu3 - mu2; + a3 = -2 * mu3 + 3 * mu2; + + return (a0 * b) + (a1 * m0) + (a2 * m1) + (a3 * c); + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/intrinsics.hpp b/roms/snes-test-roms/bass-untech/nall/intrinsics.hpp new file mode 100644 index 00000000..67a4da22 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/intrinsics.hpp @@ -0,0 +1,204 @@ +#pragma once + +namespace nall { + using uint = unsigned; + + enum class Compiler : uint { Clang, GCC, Microsoft, Unknown }; + enum class Platform : uint { Windows, MacOS, Linux, BSD, Android, Unknown }; + enum class API : uint { Windows, Posix, Unknown }; + enum class DisplayServer : uint { Windows, Quartz, Xorg, Unknown }; + enum class Architecture : uint { x86, amd64, ARM32, ARM64, PPC32, PPC64, Unknown }; + enum class Endian : uint { LSB, MSB, Unknown }; + enum class Build : uint { Debug, Stable, Minified, Release, Optimized }; + + static inline constexpr auto compiler() -> Compiler; + static inline constexpr auto platform() -> Platform; + static inline constexpr auto api() -> API; + static inline constexpr auto display() -> DisplayServer; + static inline constexpr auto architecture() -> Architecture; + static inline constexpr auto endian() -> Endian; + static inline constexpr auto build() -> Build; +} + +/* Compiler detection */ + +namespace nall { + +#if defined(__clang__) + #define COMPILER_CLANG + constexpr auto compiler() -> Compiler { return Compiler::Clang; } + + #pragma clang diagnostic warning "-Wreturn-type" + #pragma clang diagnostic ignored "-Wunused-result" + #pragma clang diagnostic ignored "-Wunknown-pragmas" + #pragma clang diagnostic ignored "-Wempty-body" + #pragma clang diagnostic ignored "-Wparentheses" + #pragma clang diagnostic ignored "-Wswitch" + #pragma clang diagnostic ignored "-Wswitch-bool" + #pragma clang diagnostic ignored "-Wtautological-compare" + #pragma clang diagnostic ignored "-Wabsolute-value" + #pragma clang diagnostic ignored "-Wshift-count-overflow" + #pragma clang diagnostic ignored "-Wtrigraphs" + + //temporary + #pragma clang diagnostic ignored "-Winconsistent-missing-override" +//#pragma clang diagnostic error "-Wdeprecated-declarations" +#elif defined(__GNUC__) + #define COMPILER_GCC + constexpr auto compiler() -> Compiler { return Compiler::GCC; } + + #pragma GCC diagnostic warning "-Wreturn-type" + #pragma GCC diagnostic ignored "-Wunused-result" + #pragma GCC diagnostic ignored "-Wunknown-pragmas" + #pragma GCC diagnostic ignored "-Wpragmas" + #pragma GCC diagnostic ignored "-Wswitch-bool" + #pragma GCC diagnostic ignored "-Wtrigraphs" +#elif defined(_MSC_VER) + #define COMPILER_MICROSOFT + constexpr auto compiler() -> Compiler { return Compiler::Microsoft; } + + #pragma warning(disable:4996) //libc "deprecation" warnings +#else + #warning "unable to detect compiler" + #define COMPILER_UNKNOWN + constexpr auto compiler() -> Compiler { return Compiler::Unknown; } +#endif + +} + +/* Platform detection */ + +namespace nall { + +#if defined(_WIN32) + #define PLATFORM_WINDOWS + #define API_WINDOWS + #define DISPLAY_WINDOWS + constexpr auto platform() -> Platform { return Platform::Windows; } + constexpr auto api() -> API { return API::Windows; } + constexpr auto display() -> DisplayServer { return DisplayServer::Windows; } +#elif defined(__APPLE__) + #define PLATFORM_MACOS + #define API_POSIX + #define DISPLAY_QUARTZ + constexpr auto platform() -> Platform { return Platform::MacOS; } + constexpr auto api() -> API { return API::Posix; } + constexpr auto display() -> DisplayServer { return DisplayServer::Quartz; } +#elif defined(__ANDROID__) + #define PLATFORM_ANDROID + #define API_POSIX + #define DISPLAY_UNKNOWN + constexpr auto platform() -> Platform { return Platform::Android; } + constexpr auto api() -> API { return API::Posix; } + constexpr auto display() -> DisplayServer { return DisplayServer::Unknown; } +#elif defined(linux) || defined(__linux__) + #define PLATFORM_LINUX + #define API_POSIX + #define DISPLAY_XORG + constexpr auto platform() -> Platform { return Platform::Linux; } + constexpr auto api() -> API { return API::Posix; } + constexpr auto display() -> DisplayServer { return DisplayServer::Xorg; } +#elif defined(__FreeBSD__) || defined(__FreeBSD_kernel__) || defined(__NetBSD__) || defined(__OpenBSD__) + #define PLATFORM_BSD + #define API_POSIX + #define DISPLAY_XORG + constexpr auto platform() -> Platform { return Platform::BSD; } + constexpr auto api() -> API { return API::Posix; } + constexpr auto display() -> DisplayServer { return DisplayServer::Xorg; } +#else + #warning "unable to detect platform" + #define PLATFORM_UNKNOWN + #define API_UNKNOWN + #define DISPLAY_UNKNOWN + constexpr auto platform() -> Platform { return Platform::Unknown; } + constexpr auto api() -> API { return API::Unknown; } + constexpr auto display() -> DisplayServer { return DisplayServer::Unknown; } +#endif + +} + +#if defined(PLATFORM_MACOS) + #include +#elif defined(PLATFORM_LINUX) + #include +#elif defined(PLATFORM_BSD) + #include +#endif + +/* Architecture detection */ + +namespace nall { + +#if defined(__i386__) || defined(_M_IX86) + #define ARCHITECTURE_X86 + constexpr auto architecture() -> Architecture { return Architecture::x86; } +#elif defined(__amd64__) || defined(_M_AMD64) + #define ARCHITECTURE_AMD64 + constexpr auto architecture() -> Architecture { return Architecture::amd64; } +#elif defined(__aarch64__) + #define ARCHITECTURE_ARM64 + constexpr auto architecture() -> Architecture { return Architecture::ARM64; } +#elif defined(__arm__) + #define ARCHITECTURE_ARM32 + constexpr auto architecture() -> Architecture { return Architecture::ARM32; } +#elif defined(__ppc64__) || defined(_ARCH_PPC64) + #define ARCHITECTURE_PPC64 + constexpr auto architecture() -> Architecture { return Architecture::PPC64; } +#elif defined(__ppc__) || defined(_ARCH_PPC) || defined(_M_PPC) + #define ARCHITECTURE_PPC32 + constexpr auto architecture() -> Architecture { return Architecture::PPC32; } +#else + #warning "unable to detect architecture" + #define ARCHITECTURE_UNKNOWN + constexpr auto architecture() -> Architecture { return Architecture::Unknown; } +#endif + +} + +/* Endian detection */ + +namespace nall { + +#if (defined(__BYTE_ORDER) && defined(__LITTLE_ENDIAN) && __BYTE_ORDER == __LITTLE_ENDIAN) || defined(__LITTLE_ENDIAN__) || defined(__i386__) || defined(__amd64__) || defined(_M_IX86) || defined(_M_AMD64) + #define ENDIAN_LSB + constexpr auto endian() -> Endian { return Endian::LSB; } +#elif (defined(__BYTE_ORDER) && defined(__BIG_ENDIAN) && __BYTE_ORDER == __BIG_ENDIAN) || defined(__BIG_ENDIAN__) || defined(__powerpc__) || defined(_M_PPC) + #define ENDIAN_MSB + constexpr auto endian() -> Endian { return Endian::MSB; } +#else + #warning "unable to detect endian" + #define ENDIAN_UNKNOWN + constexpr auto endian() -> Endian { return Endian::Unknown; } +#endif + +} + +/* Build optimization level detection */ + +#undef DEBUG +#undef NDEBUG + +namespace nall { + +#if defined(BUILD_DEBUG) + #define DEBUG + constexpr auto build() -> Build { return Build::Debug; } +#elif defined(BUILD_STABLE) + #define DEBUG + constexpr auto build() -> Build { return Build::Stable; } +#elif defined(BUILD_MINIFIED) + #define NDEBUG + constexpr auto build() -> Build { return Build::Minified; } +#elif defined(BUILD_RELEASE) + #define NDEBUG + constexpr auto build() -> Build { return Build::Release; } +#elif defined(BUILD_OPTIMIZED) + #define NDEBUG + constexpr auto build() -> Build { return Build::Optimized; } +#else + //default to debug mode + #define DEBUG + constexpr auto build() -> Build { return Build::Debug; } +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/iterator.hpp b/roms/snes-test-roms/bass-untech/nall/iterator.hpp new file mode 100644 index 00000000..6c2625e9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/iterator.hpp @@ -0,0 +1,79 @@ +#pragma once + +namespace nall { + +template struct iterator { + iterator(T* self, uint64_t offset) : _self(self), _offset(offset) {} + auto operator*() -> T& { return _self[_offset]; } + auto operator!=(const iterator& source) const -> bool { return _offset != source._offset; } + auto operator++() -> iterator& { return _offset++, *this; } + auto offset() const -> uint64_t { return _offset; } + +private: + T* _self; + uint64_t _offset; +}; + +template struct iterator_const { + iterator_const(const T* self, uint64_t offset) : _self(self), _offset(offset) {} + auto operator*() -> const T& { return _self[_offset]; } + auto operator!=(const iterator_const& source) const -> bool { return _offset != source._offset; } + auto operator++() -> iterator_const& { return _offset++, *this; } + auto offset() const -> uint64_t { return _offset; } + +private: + const T* _self; + uint64_t _offset; +}; + +template struct reverse_iterator { + reverse_iterator(T* self, uint64_t offset) : _self(self), _offset(offset) {} + auto operator*() -> T& { return _self[_offset]; } + auto operator!=(const reverse_iterator& source) const -> bool { return _offset != source._offset; } + auto operator++() -> reverse_iterator& { return _offset--, *this; } + auto offset() const -> uint64_t { return _offset; } + +private: + T* _self; + uint64_t _offset; +}; + +template struct reverse_iterator_const { + reverse_iterator_const(const T* self, uint64_t offset) : _self(self), _offset(offset) {} + auto operator*() -> const T& { return _self[_offset]; } + auto operator!=(const reverse_iterator_const& source) const -> bool { return _offset != source._offset; } + auto operator++() -> reverse_iterator_const& { return _offset--, *this; } + auto offset() const -> uint64_t { return _offset; } + +private: + const T* _self; + uint64_t _offset; +}; + +//std::rbegin(), std::rend() is missing from GCC 4.9; which I still target + +template auto rbegin(T (&array)[Size]) { return reverse_iterator{array, Size - 1}; } +template auto rend(T (&array)[Size]) { return reverse_iterator{array, (uint64_t)-1}; } + +template auto rbegin(T& self) { return self.rbegin(); } +template auto rend(T& self) { return self.rend(); } + +template struct reverse_wrapper { + auto begin() { return rbegin(_self); } + auto end() { return rend(_self); } + + auto begin() const { return rbegin(_self); } + auto end() const { return rend(_self); } + + T _self; +}; + +template auto reverse(T& object) -> reverse_wrapper { + return {object}; +} + +template auto reverse(T&& object) -> reverse_wrapper { + return {object}; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/literals.hpp b/roms/snes-test-roms/bass-untech/nall/literals.hpp new file mode 100644 index 00000000..304823be --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/literals.hpp @@ -0,0 +1,20 @@ +#pragma once + +namespace nall { + +inline constexpr auto operator"" _Kibit(unsigned long long value) { return value * 1024 / 8; } +inline constexpr auto operator"" _Mibit(unsigned long long value) { return value * 1024 * 1024 / 8; } +inline constexpr auto operator"" _Gibit(unsigned long long value) { return value * 1024 * 1024 * 1024 / 8; } +inline constexpr auto operator"" _Tibit(unsigned long long value) { return value * 1024 * 1024 * 1024 * 1024 / 8; } + +inline constexpr auto operator"" _KiB(unsigned long long value) { return value * 1024; } +inline constexpr auto operator"" _MiB(unsigned long long value) { return value * 1024 * 1024; } +inline constexpr auto operator"" _GiB(unsigned long long value) { return value * 1024 * 1024 * 1024; } +inline constexpr auto operator"" _TiB(unsigned long long value) { return value * 1024 * 1024 * 1024 * 1024; } + +inline constexpr auto operator"" _KHz(unsigned long long value) { return value * 1000; } +inline constexpr auto operator"" _MHz(unsigned long long value) { return value * 1000 * 1000; } +inline constexpr auto operator"" _GHz(unsigned long long value) { return value * 1000 * 1000 * 1000; } +inline constexpr auto operator"" _THz(unsigned long long value) { return value * 1000 * 1000 * 1000 * 1000; } + +} diff --git a/roms/snes-test-roms/bass-untech/nall/locale.hpp b/roms/snes-test-roms/bass-untech/nall/locale.hpp new file mode 100644 index 00000000..6fb9f173 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/locale.hpp @@ -0,0 +1,87 @@ +#pragma once + +namespace nall { + +struct Locale { + struct Dictionary { + string location; + string language; + Markup::Node document; + }; + + auto scan(string pathname) -> void { + dictionaries.reset(); + selected.reset(); + for(auto filename : directory::icontents(pathname, "*.bml")) { + Dictionary dictionary; + dictionary.location = {pathname, filename}; + dictionary.document = BML::unserialize(string::read(dictionary.location)); + dictionary.language = dictionary.document["locale/language"].text(); + dictionaries.append(dictionary); + } + } + + auto available() const -> vector { + vector result; + for(auto& dictionary : dictionaries) { + result.append(dictionary.language); + } + return result; + } + + auto select(string option) -> bool { + selected.reset(); + for(auto& dictionary : dictionaries) { + if(option == Location::prefix(dictionary.location) || option == dictionary.language) { + selected = dictionary; + return true; + } + } + return false; + } + + template + auto operator()(string ns, string input, P&&... p) const -> string { + vector arguments{forward

(p)...}; + if(selected) { + for(auto node : selected().document) { + if(node.name() == "namespace" && node.text() == ns) { + for(auto map : node) { + if(map.name() == "map" && map["input"].text() == input) { + input = map["value"].text(); + break; + } + } + } + } + } + for(uint index : range(arguments.size())) { + input.replace({"{", index, "}"}, arguments[index]); + } + return input; + } + + struct Namespace { + Namespace(Locale& _locale, string _namespace) : _locale(_locale), _namespace(_namespace) {} + + template + auto operator()(string input, P&&... p) const -> string { + return _locale(_namespace, input, forward

(p)...); + } + + template + auto tr(string input, P&&... p) const -> string { + return _locale(_namespace, input, forward

(p)...); + } + + private: + Locale& _locale; + string _namespace; + }; + +private: + vector dictionaries; + maybe selected; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/location.hpp b/roms/snes-test-roms/bass-untech/nall/location.hpp new file mode 100644 index 00000000..7aeb8b07 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/location.hpp @@ -0,0 +1,78 @@ +#pragma once + +#include + +namespace nall::Location { + +// (/parent/child.type/) +// (/parent/child.type/)name.type +inline auto path(string_view self) -> string { + const char* p = self.data() + self.size() - 1; + for(int offset = self.size() - 1; offset >= 0; offset--, p--) { + if(*p == '/') return slice(self, 0, offset + 1); + } + return ""; //no path found +} + +// /parent/child.type/() +// /parent/child.type/(name.type) +inline auto file(string_view self) -> string { + const char* p = self.data() + self.size() - 1; + for(int offset = self.size() - 1; offset >= 0; offset--, p--) { + if(*p == '/') return slice(self, offset + 1); + } + return self; //no path found +} + +// (/parent/)child.type/ +// (/parent/child.type/)name.type +inline auto dir(string_view self) -> string { + const char* p = self.data() + self.size() - 1, *last = p; + for(int offset = self.size() - 1; offset >= 0; offset--, p--) { + if(*p == '/' && p == last) continue; + if(*p == '/') return slice(self, 0, offset + 1); + } + return ""; //no path found +} + +// /parent/(child.type/) +// /parent/child.type/(name.type) +inline auto base(string_view self) -> string { + const char* p = self.data() + self.size() - 1, *last = p; + for(int offset = self.size() - 1; offset >= 0; offset--, p--) { + if(*p == '/' && p == last) continue; + if(*p == '/') return slice(self, offset + 1); + } + return self; //no path found +} + +// /parent/(child).type/ +// /parent/child.type/(name).type +inline auto prefix(string_view self) -> string { + const char* p = self.data() + self.size() - 1, *last = p; + for(int offset = self.size() - 1, suffix = -1; offset >= 0; offset--, p--) { + if(*p == '/' && p == last) continue; + if(*p == '/') return slice(self, offset + 1, (suffix >= 0 ? suffix : self.size()) - offset - 1).trimRight("/"); + if(*p == '.' && suffix == -1) { suffix = offset; continue; } + if(offset == 0) return slice(self, offset, suffix).trimRight("/"); + } + return ""; //no prefix found +} + +// /parent/child(.type)/ +// /parent/child.type/name(.type) +inline auto suffix(string_view self) -> string { + const char* p = self.data() + self.size() - 1, *last = p; + for(int offset = self.size() - 1; offset >= 0; offset--, p--) { + if(*p == '/' && p == last) continue; + if(*p == '/') break; + if(*p == '.') return slice(self, offset).trimRight("/"); + } + return ""; //no suffix found +} + +inline auto notsuffix(string_view self) -> string { + return {path(self), prefix(self)}; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/mac/poly1305.hpp b/roms/snes-test-roms/bass-untech/nall/mac/poly1305.hpp new file mode 100644 index 00000000..befbf46e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/mac/poly1305.hpp @@ -0,0 +1,122 @@ +#pragma once + +#include + +namespace nall::MAC { + +struct Poly1305 { + auto authenticate(array_view memory, uint256_t nonce) -> uint128_t { + initialize(nonce); + process(memory.data(), memory.size()); + return finish(); + } + + auto initialize(uint256_t key) -> void { + uint64_t t0 = key >> 0; + uint64_t t1 = key >> 64; + pad[0] = key >> 128; + pad[1] = key >> 192; + + r[0] = (t0 ) & 0xffc0fffffff; + r[1] = (t0 >> 44 | t1 << 20) & 0xfffffc0ffff; + r[2] = ( t1 >> 24) & 0x00ffffffc0f; + + h[0] = 0, h[1] = 0, h[2] = 0; + offset = 0; + } + + auto process(const uint8_t* data, uint64_t size) -> void { + while(size--) { + buffer[offset++] = *data++; + if(offset >= 16) { + block(); + offset = 0; + } + } + } + + auto finish() -> uint128_t { + if(offset) { + buffer[offset++] = 1; + while(offset < 16) buffer[offset++] = 0; + block(true); + } + + uint64_t h0 = h[0], h1 = h[1], h2 = h[2]; + + uint64_t c = h1 >> 44; h1 &= 0xfffffffffff; + h2 += c; c = h2 >> 42; h2 &= 0x3ffffffffff; + h0 += c * 5; c = h0 >> 44; h0 &= 0xfffffffffff; + h1 += c; c = h1 >> 44; h1 &= 0xfffffffffff; + h2 += c; c = h2 >> 42; h2 &= 0x3ffffffffff; + h0 += c * 5; c = h0 >> 44; h0 &= 0xfffffffffff; + h1 += c; + + uint64_t g0 = h0 + 5; c = g0 >> 44; g0 &= 0xfffffffffff; + uint64_t g1 = h1 + c; c = g1 >> 44; g1 &= 0xfffffffffff; + uint64_t g2 = h2 + c - (1ull << 42); + + c = (g2 >> 63) - 1; + g0 &= c, g1 &= c, g2 &= c; + c = ~c; + h0 = (h0 & c) | g0; + h1 = (h1 & c) | g1; + h2 = (h2 & c) | g2; + + uint64_t t0 = pad[0], t1 = pad[1]; + + h0 += ((t0 ) & 0xfffffffffff) ; c = h0 >> 44; h0 &= 0xfffffffffff; + h1 += ((t0 >> 44 | t1 << 20) & 0xfffffffffff) + c; c = h1 >> 44; h1 &= 0xfffffffffff; + h2 += (( t1 >> 24) & 0x3ffffffffff) + c; h2 &= 0x3ffffffffff; + + h0 = (h0 >> 0 | h1 << 44); + h1 = (h1 >> 20 | h2 << 24); + + r[0] = 0, r[1] = 0, r[2] = 0; + h[0] = 0, h[1] = 0, h[2] = 0; + pad[0] = 0, pad[1] = 0; + memory::fill(buffer, sizeof(buffer)); + offset = 0; + + return uint128_t(h1) << 64 | h0; + } + +private: + auto block(bool last = false) -> void { + uint64_t r0 = r[0], r1 = r[1], r2 = r[2]; + uint64_t h0 = h[0], h1 = h[1], h2 = h[2]; + + uint64_t s1 = r1 * 20; + uint64_t s2 = r2 * 20; + + uint64_t t0 = memory::readl<8>(buffer + 0); + uint64_t t1 = memory::readl<8>(buffer + 8); + + h0 += ((t0 ) & 0xfffffffffff); + h1 += ((t0 >> 44 | t1 << 20) & 0xfffffffffff); + h2 += (( t1 >> 24) & 0x3ffffffffff) | (last ? 0 : 1ull << 40); + + uint128_t d, d0, d1, d2; + d0 = (uint128_t)h0 * r0; d = (uint128_t)h1 * s2; d0 += d; d = (uint128_t)h2 * s1; d0 += d; + d1 = (uint128_t)h0 * r1; d = (uint128_t)h1 * r0; d1 += d; d = (uint128_t)h2 * s2; d1 += d; + d2 = (uint128_t)h0 * r2; d = (uint128_t)h1 * r1; d2 += d; d = (uint128_t)h2 * r0; d2 += d; + + uint64_t c = (uint64_t)(d0 >> 44); h0 = (uint64_t)d0 & 0xfffffffffff; + d1 += c; c = (uint64_t)(d1 >> 44); h1 = (uint64_t)d1 & 0xfffffffffff; + d2 += c; c = (uint64_t)(d2 >> 42); h2 = (uint64_t)d2 & 0x3ffffffffff; + + h0 += c * 5; c = h0 >> 44; h0 &= 0xfffffffffff; + h1 += c; + + h[0] = h0, h[1] = h1, h[2] = h2; + } + + uint64_t r[3]; + uint64_t h[3]; + uint64_t pad[2]; + + uint8_t buffer[16]; + uint offset; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/macos/guard.hpp b/roms/snes-test-roms/bass-untech/nall/macos/guard.hpp new file mode 100644 index 00000000..96cd4d69 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/macos/guard.hpp @@ -0,0 +1,15 @@ +#ifndef NALL_MACOS_GUARD_HPP +#define NALL_MACOS_GUARD_HPP + +#define Boolean CocoaBoolean +#define decimal CocoaDecimal +#define DEBUG CocoaDebug + +#else +#undef NALL_MACOS_GUARD_HPP + +#undef Boolean +#undef decimal +#undef DEBUG + +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/main.hpp b/roms/snes-test-roms/bass-untech/nall/main.hpp new file mode 100644 index 00000000..8ba1462d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/main.hpp @@ -0,0 +1,42 @@ +#pragma once + +#include +#include +#include + +namespace nall { + auto main(Arguments arguments) -> void; + + auto main(int argc, char** argv) -> int { + #if defined(PLATFORM_WINDOWS) + CoInitialize(0); + WSAData wsaData{0}; + WSAStartup(MAKEWORD(2, 2), &wsaData); + _setmode(_fileno(stdin ), O_BINARY); + _setmode(_fileno(stdout), O_BINARY); + _setmode(_fileno(stderr), O_BINARY); + #endif + + main(move(Arguments{argc, argv})); + + #if !defined(PLATFORM_WINDOWS) + //when a program is running, input on the terminal queues in stdin + //when terminating the program, the shell proceeds to try and execute all stdin data + //this is annoying behavior: this code tries to minimize the impact as much as it can + //we can flush all of stdin up to the last line feed, preventing spurious commands from executing + //however, even with setvbuf(_IONBF), we can't stop the last line from echoing to the terminal + auto flags = fcntl(fileno(stdin), F_GETFL, 0); + fcntl(fileno(stdin), F_SETFL, flags | O_NONBLOCK); //don't allow read() to block when empty + char buffer[4096], data = false; + while(read(fileno(stdin), buffer, sizeof(buffer)) > 0) data = true; + fcntl(fileno(stdin), F_SETFL, flags); //restore original flags for the terminal + if(data) putchar('\r'); //ensures PS1 is printed at the start of the line + #endif + + return EXIT_SUCCESS; + } +} + +auto main(int argc, char** argv) -> int { + return nall::main(argc, argv); +} diff --git a/roms/snes-test-roms/bass-untech/nall/map.hpp b/roms/snes-test-roms/bass-untech/nall/map.hpp new file mode 100644 index 00000000..58b1e11b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/map.hpp @@ -0,0 +1,58 @@ +#pragma once + +#include + +namespace nall { + +template struct map { + struct node_t { + T key; + U value; + node_t() = default; + node_t(const T& key) : key(key) {} + node_t(const T& key, const U& value) : key(key), value(value) {} + auto operator< (const node_t& source) const -> bool { return key < source.key; } + auto operator==(const node_t& source) const -> bool { return key == source.key; } + }; + + auto find(const T& key) const -> maybe { + if(auto node = root.find({key})) return node().value; + return nothing; + } + + auto insert(const T& key, const U& value) -> void { root.insert({key, value}); } + auto remove(const T& key) -> void { root.remove({key}); } + auto size() const -> unsigned { return root.size(); } + auto reset() -> void { root.reset(); } + + auto begin() -> typename set::iterator { return root.begin(); } + auto end() -> typename set::iterator { return root.end(); } + + auto begin() const -> const typename set::iterator { return root.begin(); } + auto end() const -> const typename set::iterator { return root.end(); } + +protected: + set root; +}; + +template struct bimap { + auto find(const T& key) const -> maybe { return tmap.find(key); } + auto find(const U& key) const -> maybe { return umap.find(key); } + auto insert(const T& key, const U& value) -> void { tmap.insert(key, value); umap.insert(value, key); } + auto remove(const T& key) -> void { if(auto p = tmap.find(key)) { umap.remove(p().value); tmap.remove(key); } } + auto remove(const U& key) -> void { if(auto p = umap.find(key)) { tmap.remove(p().value); umap.remove(key); } } + auto size() const -> unsigned { return tmap.size(); } + auto reset() -> void { tmap.reset(); umap.reset(); } + + auto begin() -> typename set::node_t>::iterator { return tmap.begin(); } + auto end() -> typename set::node_t>::iterator { return tmap.end(); } + + auto begin() const -> const typename set::node_t>::iterator { return tmap.begin(); } + auto end() const -> const typename set::node_t>::iterator { return tmap.end(); } + +protected: + map tmap; + map umap; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/matrix-multiply.hpp b/roms/snes-test-roms/bass-untech/nall/matrix-multiply.hpp new file mode 100644 index 00000000..a82d8ea2 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/matrix-multiply.hpp @@ -0,0 +1,36 @@ +#pragma once + +//matrix multiplication primitives +//used in: ruby/opengl/quark + +namespace nall { + +template inline auto MatrixMultiply( +T* output, +const T* xdata, uint xrows, uint xcols, +const T* ydata, uint yrows, uint ycols +) -> void { + if(xcols != yrows) return; + + for(uint y : range(xrows)) { + for(uint x : range(ycols)) { + T sum = 0; + for(uint z : range(xcols)) { + sum += xdata[y * xcols + z] * ydata[z * ycols + x]; + } + *output++ = sum; + } + } +} + +template inline auto MatrixMultiply( +const T* xdata, uint xrows, uint xcols, +const T* ydata, uint yrows, uint ycols +) -> vector { + vector output; + output.resize(xrows * ycols); + MatrixMultiply(output.data(), xdata, xrows, xcols, ydata, yrows, ycols); + return output; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/matrix.hpp b/roms/snes-test-roms/bass-untech/nall/matrix.hpp new file mode 100644 index 00000000..e266df6a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/matrix.hpp @@ -0,0 +1,213 @@ +#pragma once + +namespace nall { + +template +struct Matrix { + static_assert(Rows > 0 && Cols > 0); + + Matrix() = default; + Matrix(const Matrix&) = default; + Matrix(const initializer_list& source) { + uint index = 0; + for(auto& value : source) { + if(index >= Rows * Cols) break; + values[index / Cols][index % Cols] = value; + } + } + + operator array_span() { return {values, Rows * Cols}; } + operator array_view() const { return {values, Rows * Cols}; } + + //1D matrices (for polynomials, etc) + auto operator[](uint row) -> T& { return values[row][0]; } + auto operator[](uint row) const -> T { return values[row][0]; } + + //2D matrices + auto operator()(uint row, uint col) -> T& { return values[row][col]; } + auto operator()(uint row, uint col) const -> T { return values[row][col]; } + + //operators + auto operator+() const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = +target(row, col); + } + } + return result; + } + + auto operator-() const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = -target(row, col); + } + } + return result; + } + + auto operator+(const Matrix& source) const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = target(row, col) + source(row, col); + } + } + return result; + } + + auto operator-(const Matrix& source) const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = target(row, col) - source(row, col); + } + } + return result; + } + + auto operator*(T source) const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = target(row, col) * source; + } + } + return result; + } + + auto operator/(T source) const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = target(row, col) / source; + } + } + return result; + } + + //warning: matrix multiplication is not commutative! + template + auto operator*(const Matrix& source) const -> Matrix { + static_assert(Cols == SourceRows); + Matrix result; + for(uint y : range(Rows)) { + for(uint x : range(SourceCols)) { + T sum{}; + for(uint z : range(Cols)) { + sum += target(y, z) * source(z, x); + } + result(y, x) = sum; + } + } + return result; + } + + template + auto operator/(const Matrix& source) const -> maybe> { + static_assert(Cols == SourceRows && SourceRows == SourceCols); + if(auto inverted = source.invert()) return operator*(inverted()); + return {}; + } + + auto& operator+=(const Matrix& source) { return *this = operator+(source); } + auto& operator-=(const Matrix& source) { return *this = operator-(source); } + auto& operator*=(T source) { return *this = operator*(source); } + auto& operator/=(T source) { return *this = operator/(source); } + template + auto& operator*=(const Matrix& source) { return *this = operator*(source); } + //matrix division is not always possible (when matrix cannot be inverted), so operator/= is not provided + + //algorithm: Gauss-Jordan + auto invert() const -> maybe { + static_assert(Rows == Cols); + Matrix source = *this; + Matrix result = identity(); + + const auto add = [&](uint targetRow, uint sourceRow, T factor = 1) { + for(uint col : range(Cols)) { + result(targetRow, col) += result(sourceRow, col) * factor; + source(targetRow, col) += source(sourceRow, col) * factor; + } + }; + + const auto sub = [&](uint targetRow, uint sourceRow, T factor = 1) { + for(uint col : range(Cols)) { + result(targetRow, col) -= result(sourceRow, col) * factor; + source(targetRow, col) -= source(sourceRow, col) * factor; + } + }; + + const auto mul = [&](uint row, T factor) { + for(uint col : range(Cols)) { + result(row, col) *= factor; + source(row, col) *= factor; + } + }; + + for(uint i : range(Cols)) { + if(source(i, i) == 0) { + for(uint row : range(Rows)) { + if(source(row, i) != 0) { + add(i, row); + break; + } + } + //matrix is not invertible: + if(source(i, i) == 0) return {}; + } + + mul(i, T{1} / source(i, i)); + for(uint row : range(Rows)) { + if(row == i) continue; + sub(row, i, source(row, i)); + } + } + + return result; + } + + auto transpose() const -> Matrix { + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(col, row) = target(row, col); + } + } + return result; + } + + static auto identity() -> Matrix { + static_assert(Rows == Cols); + Matrix result; + for(uint row : range(Rows)) { + for(uint col : range(Cols)) { + result(row, col) = row == col; + } + } + return result; + } + + //debugging function: do not use in production code + template + auto _print() const -> void { + for(uint row : range(Rows)) { + nall::print("[ "); + for(uint col : range(Cols)) { + nall::print(pad(target(row, col), Pad, ' '), " "); + } + nall::print("]\n"); + } + } + +protected: + //same as operator(), but with easier to read syntax inside Matrix class + auto target(uint row, uint col) -> T& { return values[row][col]; } + auto target(uint row, uint col) const -> T { return values[row][col]; } + + T values[Rows][Cols]{}; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/maybe.hpp b/roms/snes-test-roms/bass-untech/nall/maybe.hpp new file mode 100644 index 00000000..aaec4e68 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/maybe.hpp @@ -0,0 +1,91 @@ +#pragma once + +namespace nall { + +struct nothing_t {}; +static nothing_t nothing; +struct else_t {}; + +template +struct maybe { + maybe() {} + maybe(nothing_t) {} + maybe(const T& source) { operator=(source); } + maybe(T&& source) { operator=(move(source)); } + maybe(const maybe& source) { operator=(source); } + maybe(maybe&& source) { operator=(move(source)); } + ~maybe() { reset(); } + + auto operator=(nothing_t) -> maybe& { reset(); return *this; } + auto operator=(const T& source) -> maybe& { reset(); _valid = true; new(&_value.t) T(source); return *this; } + auto operator=(T&& source) -> maybe& { reset(); _valid = true; new(&_value.t) T(move(source)); return *this; } + + auto operator=(const maybe& source) -> maybe& { + if(this == &source) return *this; + reset(); + if(_valid = source._valid) new(&_value.t) T(source.get()); + return *this; + } + + auto operator=(maybe&& source) -> maybe& { + if(this == &source) return *this; + reset(); + if(_valid = source._valid) new(&_value.t) T(move(source.get())); + return *this; + } + + explicit operator bool() const { return _valid; } + auto reset() -> void { if(_valid) { _value.t.~T(); _valid = false; } } + auto data() -> T* { return _valid ? &_value.t : nullptr; } + auto get() -> T& { assert(_valid); return _value.t; } + + auto data() const -> const T* { return ((maybe*)this)->data(); } + auto get() const -> const T& { return ((maybe*)this)->get(); } + auto operator->() -> T* { return data(); } + auto operator->() const -> const T* { return data(); } + auto operator*() -> T& { return get(); } + auto operator*() const -> const T& { return get(); } + auto operator()() -> T& { return get(); } + auto operator()() const -> const T& { return get(); } + auto operator()(const T& invalid) const -> const T& { return _valid ? get() : invalid; } + +private: + union U { + T t; + U() {} + ~U() {} + } _value; + bool _valid = false; +}; + +template +struct maybe { + maybe() : _value(nullptr) {} + maybe(nothing_t) : _value(nullptr) {} + maybe(const T& source) : _value((T*)&source) {} + maybe(const maybe& source) : _value(source._value) {} + + auto operator=(nothing_t) -> maybe& { _value = nullptr; return *this; } + auto operator=(const T& source) -> maybe& { _value = (T*)&source; return *this; } + auto operator=(const maybe& source) -> maybe& { _value = source._value; return *this; } + + explicit operator bool() const { return _value; } + auto reset() -> void { _value = nullptr; } + auto data() -> T* { return _value; } + auto get() -> T& { assert(_value); return *_value; } + + auto data() const -> const T* { return ((maybe*)this)->data(); } + auto get() const -> const T& { return ((maybe*)this)->get(); } + auto operator->() -> T* { return data(); } + auto operator->() const -> const T* { return data(); } + auto operator*() -> T& { return get(); } + auto operator*() const -> const T& { return get(); } + auto operator()() -> T& { return get(); } + auto operator()() const -> const T& { return get(); } + auto operator()(const T& invalid) const -> const T& { return _value ? get() : invalid; } + +private: + T* _value; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/memory.hpp b/roms/snes-test-roms/bass-untech/nall/memory.hpp new file mode 100644 index 00000000..7537785a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/memory.hpp @@ -0,0 +1,163 @@ +#pragma once + +#include +#include + +namespace nall::memory { + template auto allocate(uint size) -> T*; + template auto allocate(uint size, const T& value) -> T*; + + template auto resize(void* target, uint size) -> T*; + + auto free(void* target) -> void; + + template auto compare(const void* target, uint capacity, const void* source, uint size) -> int; + template auto compare(const void* target, const void* source, uint size) -> int; + + template auto icompare(const void* target, uint capacity, const void* source, uint size) -> int; + template auto icompare(const void* target, const void* source, uint size) -> int; + + template auto copy(void* target, uint capacity, const void* source, uint size) -> T*; + template auto copy(void* target, const void* source, uint size) -> T*; + + template auto move(void* target, uint capacity, const void* source, uint size) -> T*; + template auto move(void* target, const void* source, uint size) -> T*; + + template auto fill(void* target, uint capacity, const T& value = {}) -> T*; + + template auto assign(T* target) -> void {} + template auto assign(T* target, const U& value, P&&... p) -> void; + + template auto readl(const void* source) -> T; + template auto readm(const void* source) -> T; + + template auto writel(void* target, T data) -> void; + template auto writem(void* target, T data) -> void; +} + +namespace nall::memory { + +//implementation notes: +//memcmp, memcpy, memmove have terrible performance on small block sizes (FreeBSD 10.0-amd64) +//as this library is used extensively by nall/string, and most strings tend to be small, +//this library hand-codes these functions instead. surprisingly, it's a substantial speedup + +template auto allocate(uint size) -> T* { + return (T*)malloc(size * sizeof(T)); +} + +template auto allocate(uint size, const T& value) -> T* { + auto result = allocate(size); + if(result) fill(result, size, value); + return result; +} + +template auto resize(void* target, uint size) -> T* { + return (T*)realloc(target, size * sizeof(T)); +} + +inline auto free(void* target) -> void { + ::free(target); +} + +template auto compare(const void* target, uint capacity, const void* source, uint size) -> int { + auto t = (uint8_t*)target; + auto s = (uint8_t*)source; + auto l = min(capacity, size) * sizeof(T); + while(l--) { + auto x = *t++; + auto y = *s++; + if(x != y) return x - y; + } + if(capacity == size) return 0; + return -(capacity < size); +} + +template auto compare(const void* target, const void* source, uint size) -> int { + return compare(target, size, source, size); +} + +template auto icompare(const void* target, uint capacity, const void* source, uint size) -> int { + auto t = (uint8_t*)target; + auto s = (uint8_t*)source; + auto l = min(capacity, size) * sizeof(T); + while(l--) { + auto x = *t++; + auto y = *s++; + if(x - 'A' < 26) x += 32; + if(y - 'A' < 26) y += 32; + if(x != y) return x - y; + } + return -(capacity < size); +} + +template auto icompare(const void* target, const void* source, uint size) -> int { + return icompare(target, size, source, size); +} + +template auto copy(void* target, uint capacity, const void* source, uint size) -> T* { + auto t = (uint8_t*)target; + auto s = (uint8_t*)source; + auto l = min(capacity, size) * sizeof(T); + while(l--) *t++ = *s++; + return (T*)target; +} + +template auto copy(void* target, const void* source, uint size) -> T* { + return copy(target, size, source, size); +} + +template auto move(void* target, uint capacity, const void* source, uint size) -> T* { + auto t = (uint8_t*)target; + auto s = (uint8_t*)source; + auto l = min(capacity, size) * sizeof(T); + if(t < s) { + while(l--) *t++ = *s++; + } else { + t += l; + s += l; + while(l--) *--t = *--s; + } + return (T*)target; +} + +template auto move(void* target, const void* source, uint size) -> T* { + return move(target, size, source, size); +} + +template auto fill(void* target, uint capacity, const T& value) -> T* { + auto t = (T*)target; + while(capacity--) *t++ = value; + return (T*)target; +} + +template auto assign(T* target, const U& value, P&&... p) -> void { + *target++ = value; + assign(target, forward

(p)...); +} + +template auto readl(const void* source) -> T { + auto p = (const uint8_t*)source; + T data = 0; + for(uint n = 0; n < size; n++) data |= T(*p++) << n * 8; + return data; +} + +template auto readm(const void* source) -> T { + auto p = (const uint8_t*)source; + T data = 0; + for(int n = size - 1; n >= 0; n--) data |= T(*p++) << n * 8; + return data; +} + +template auto writel(void* target, T data) -> void { + auto p = (uint8_t*)target; + for(uint n = 0; n < size; n++) *p++ = data >> n * 8; +} + +template auto writem(void* target, T data) -> void { + auto p = (uint8_t*)target; + for(int n = size - 1; n >= 0; n--) *p++ = data >> n * 8; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/merge-sort.hpp b/roms/snes-test-roms/bass-untech/nall/merge-sort.hpp new file mode 100644 index 00000000..5c1175b8 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/merge-sort.hpp @@ -0,0 +1,82 @@ +#pragma once + +#include +#include + +//class: merge sort +//average: O(n log n) +//worst: O(n log n) +//memory: O(n) +//stack: O(log n) +//stable?: yes + +//note: merge sort was chosen over quick sort, because: +//* it is a stable sort +//* it lacks O(n^2) worst-case overhead +//* it usually runs faster than quick sort anyway + +//note: insertion sort is generally more performant than selection sort +#define NALL_MERGE_SORT_INSERTION +//#define NALL_MERGE_SORT_SELECTION + +namespace nall { + +template auto sort(T list[], uint size, const Comparator& lessthan) -> void { + if(size <= 1) return; //nothing to sort + + //sort smaller blocks using an O(n^2) algorithm (which for small sizes, increases performance) + if(size < 64) { + //insertion sort requires a copy (via move construction) + #if defined(NALL_MERGE_SORT_INSERTION) + for(int i = 1, j; i < size; i++) { + T copy(move(list[i])); + for(j = i - 1; j >= 0; j--) { + if(!lessthan(copy, list[j])) break; + list[j + 1] = move(list[j]); + } + list[j + 1] = move(copy); + } + //selection sort requires a swap + #elif defined(NALL_MERGE_SORT_SELECTION) + for(uint i = 0; i < size; i++) { + uint min = i; + for(uint j = i + 1; j < size; j++) { + if(lessthan(list[j], list[min])) min = j; + } + if(min != i) swap(list[i], list[min]); + } + #endif + return; + } + + //split list in half and recursively sort both + uint middle = size / 2; + sort(list, middle, lessthan); + sort(list + middle, size - middle, lessthan); + + //left and right are sorted here; perform merge sort + //use placement new to avoid needing T to be default-constructable + auto buffer = memory::allocate(size); + uint offset = 0, left = 0, right = middle; + while(left < middle && right < size) { + if(!lessthan(list[right], list[left])) { + new(buffer + offset++) T(move(list[left++])); + } else { + new(buffer + offset++) T(move(list[right++])); + } + } + while(left < middle) new(buffer + offset++) T(move(list[left++])); + while(right < size ) new(buffer + offset++) T(move(list[right++])); + + for(uint i = 0; i < size; i++) { + list[i] = move(buffer[i]); + buffer[i].~T(); + } + memory::free(buffer); +} + +template auto sort(T list[], uint size) -> void { + return sort(list, size, [](const T& l, const T& r) { return l < r; }); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/nall.hpp b/roms/snes-test-roms/bass-untech/nall/nall.hpp new file mode 100644 index 00000000..eb67299e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/nall.hpp @@ -0,0 +1,92 @@ +#pragma once + +//include the most common nall headers with one statement +//does not include the most obscure components with high cost and low usage + +#include + +#include +#include +//#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include //todo: compilation errors when included earlier +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(PLATFORM_WINDOWS) + #include + #include +#endif + +#if defined(API_POSIX) + #include +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/path.hpp b/roms/snes-test-roms/bass-untech/nall/path.hpp new file mode 100644 index 00000000..5506f7f0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/path.hpp @@ -0,0 +1,155 @@ +#pragma once + +#include + +namespace nall::Path { + +inline auto active() -> string { + char path[PATH_MAX] = ""; + (void)getcwd(path, PATH_MAX); + string result = path; + if(!result) result = "."; + result.transform("\\", "/"); + if(!result.endsWith("/")) result.append("/"); + return result; +} + +inline auto real(string_view name) -> string { + string result; + char path[PATH_MAX] = ""; + if(::realpath(name, path)) result = Location::path(string{path}.transform("\\", "/")); + if(!result) return active(); + result.transform("\\", "/"); + if(!result.endsWith("/")) result.append("/"); + return result; +} + +inline auto program() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + GetModuleFileName(nullptr, path, PATH_MAX); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + return Path::real(result); + #else + Dl_info info; + dladdr((void*)&program, &info); + return Path::real(info.dli_fname); + #endif +} + +// / +// c:/ +inline auto root() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + SHGetFolderPathW(nullptr, CSIDL_WINDOWS | CSIDL_FLAG_CREATE, nullptr, 0, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + return slice(result, 0, 3); + #else + return "/"; + #endif +} + +// /home/username/ +// c:/users/username/ +inline auto user() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + SHGetFolderPathW(nullptr, CSIDL_PROFILE | CSIDL_FLAG_CREATE, nullptr, 0, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + #else + struct passwd* userinfo = getpwuid(getuid()); + string result = userinfo->pw_dir; + #endif + if(!result) result = "."; + if(!result.endsWith("/")) result.append("/"); + return result; +} + +// /home/username/Desktop/ +// c:/users/username/Desktop/ +inline auto desktop(string_view name = {}) -> string { + return {user(), "Desktop/", name}; +} + +//todo: MacOS uses the same location for userData() and userSettings() +//... is there a better option here? + +// /home/username/.config/ +// ~/Library/Application Support/ +// c:/users/username/appdata/roaming/ +inline auto userSettings() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + SHGetFolderPathW(nullptr, CSIDL_APPDATA | CSIDL_FLAG_CREATE, nullptr, 0, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + #elif defined(PLATFORM_MACOS) + string result = {Path::user(), "Library/Application Support/"}; + #else + string result = {Path::user(), ".config/"}; + #endif + if(!result) result = "."; + if(!result.endsWith("/")) result.append("/"); + return result; +} + +// /home/username/.local/share/ +// ~/Library/Application Support/ +// c:/users/username/appdata/local/ +inline auto userData() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + SHGetFolderPathW(nullptr, CSIDL_LOCAL_APPDATA | CSIDL_FLAG_CREATE, nullptr, 0, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + #elif defined(PLATFORM_MACOS) + string result = {Path::user(), "Library/Application Support/"}; + #else + string result = {Path::user(), ".local/share/"}; + #endif + if(!result) result = "."; + if(!result.endsWith("/")) result.append("/"); + return result; +} + +// /usr/share +// /Library/Application Support/ +// c:/ProgramData/ +inline auto sharedData() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + SHGetFolderPathW(nullptr, CSIDL_COMMON_APPDATA | CSIDL_FLAG_CREATE, nullptr, 0, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + #elif defined(PLATFORM_MACOS) + string result = "/Library/Application Support/"; + #else + string result = "/usr/share/"; + #endif + if(!result) result = "."; + if(!result.endsWith("/")) result.append("/"); + return result; +} + +// /tmp +// c:/users/username/AppData/Local/Temp/ +inline auto temporary() -> string { + #if defined(PLATFORM_WINDOWS) + wchar_t path[PATH_MAX] = L""; + GetTempPathW(PATH_MAX, path); + string result = (const char*)utf8_t(path); + result.transform("\\", "/"); + #elif defined(P_tmpdir) + string result = P_tmpdir; + #else + string result = "/tmp/"; + #endif + if(!result.endsWith("/")) result.append("/"); + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/platform.hpp b/roms/snes-test-roms/bass-untech/nall/platform.hpp new file mode 100644 index 00000000..14d61cb0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/platform.hpp @@ -0,0 +1,184 @@ +#pragma once + +#include +#include + +namespace Math { + static const long double e = 2.71828182845904523536; + static const long double Pi = 3.14159265358979323846; +} + +#if defined(PLATFORM_WINDOWS) + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include +#endif + +#include +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include + +#if !defined(PLATFORM_WINDOWS) + #include + #include + #include + #include + #include + #include + #include + #include + #include + #include +#endif + +#if defined(ARCHITECTURE_X86) || defined(ARCHITECTURE_AMD64) + #include +#endif + +#if defined(COMPILER_MICROSOFT) + #define va_copy(dest, src) ((dest) = (src)) +#endif + +#if defined(PLATFORM_WINDOWS) + #undef IN + #undef OUT + #undef interface + #define dllexport __declspec(dllexport) + #define MSG_NOSIGNAL 0 + + extern "C" { + using pollfd = WSAPOLLFD; + } + + inline auto access(const char* path, int amode) -> int { return _waccess(nall::utf16_t(path), amode); } + inline auto getcwd(char* buf, size_t size) -> char* { wchar_t wpath[PATH_MAX] = L""; if(!_wgetcwd(wpath, size)) return nullptr; strcpy(buf, nall::utf8_t(wpath)); return buf; } + inline auto mkdir(const char* path, int mode) -> int { return _wmkdir(nall::utf16_t(path)); } + inline auto poll(struct pollfd fds[], unsigned long nfds, int timeout) -> int { return WSAPoll(fds, nfds, timeout); } + inline auto putenv(const char* value) -> int { return _wputenv(nall::utf16_t(value)); } + inline auto realpath(const char* file_name, char* resolved_name) -> char* { wchar_t wfile_name[PATH_MAX] = L""; if(!_wfullpath(wfile_name, nall::utf16_t(file_name), PATH_MAX)) return nullptr; strcpy(resolved_name, nall::utf8_t(wfile_name)); return resolved_name; } + inline auto rename(const char* oldname, const char* newname) -> int { return _wrename(nall::utf16_t(oldname), nall::utf16_t(newname)); } + + namespace nall { + //network functions take void*, not char*. this allows them to be used without casting + + inline auto recv(int socket, void* buffer, size_t length, int flags) -> ssize_t { + return ::recv(socket, (char*)buffer, length, flags); + } + + inline auto send(int socket, const void* buffer, size_t length, int flags) -> ssize_t { + return ::send(socket, (const char*)buffer, length, flags); + } + + inline auto setsockopt(int socket, int level, int option_name, const void* option_value, socklen_t option_len) -> int { + return ::setsockopt(socket, level, option_name, (const char*)option_value, option_len); + } + } +#else + #define dllexport +#endif + +#undef bswap16 +#undef bswap32 +#undef bswap64 +#undef bswap128 +#undef likely +#undef unlikely +#if defined(COMPILER_CLANG) || defined(COMPILER_GCC) + #define bswap16(value) __builtin_bswap16(value) + #define bswap32(value) __builtin_bswap32(value) + #define bswap64(value) __builtin_bswap64(value) + #if defined(__SIZEOF_INT128__) + inline auto bswap128(uint128_t value) -> uint128_t { + #if defined(__SSSE3__) + static const __m128i shuffle = _mm_setr_epi8(15, 14, 13, 12, 11, 10, 9, 8, 7, 6, 5, 4, 3, 2, 1, 0); + return reinterpret_cast(_mm_shuffle_epi8(reinterpret_cast<__m128i>(value), shuffle)); + #else + return (uint128_t)__builtin_bswap64(value) << 64 | __builtin_bswap64(value >> 64); + #endif + } + #endif + #define likely(expression) __builtin_expect(bool(expression), true) + #define unlikely(expression) __builtin_expect(bool(expression), false) +#else + inline auto bswap16(uint16_t value) -> uint16_t { + return value << 8 | value >> 8; + } + inline auto bswap32(uint32_t value) -> uint32_t { + return (uint32_t)bswap16(value) << 16 | bswap16(value >> 16); + } + inline auto bswap64(uint64_t value) -> uint64_t { + return (uint64_t)bswap32(value) << 32 | bswap32(value >> 32); + } + #if defined(__SIZEOF_INT128__) + inline auto bswap128(uint128_t value) -> uint128_t { + return (uint128_t)bswap64(value) << 64 | bswap64(value >> 64); + } + #endif + #define likely(expression) expression + #define unlikely(expression) expression +#endif + +//notify the processor/operating system that this thread is currently awaiting an event (eg a spinloop) +//calling this function aims to avoid consuming 100% CPU resources on the active thread during spinloops +inline auto spinloop() -> void { + #if defined(COMPILER_CLANG) || defined(COMPILER_GCC) + #if defined(ARCHITECTURE_X86) || defined(ARCHITECTURE_AMD64) + __builtin_ia32_pause(); + return; + #endif + #endif + usleep(1); +} + +#if defined(PLATFORM_MACOS) + #define MSG_NOSIGNAL 0 +#endif + +#if defined(COMPILER_CLANG) || defined(COMPILER_GCC) + #define noinline __attribute__((noinline)) + #define alwaysinline inline __attribute__((always_inline)) +#elif defined(COMPILER_MICROSOFT) + #define noinline __declspec(noinline) + #define alwaysinline inline __forceinline +#else + #define noinline + #define alwaysinline inline +#endif + +//P0627: [[unreachable]] -- impossible to simulate with identical syntax, must omit brackets ... +#if defined(COMPILER_CLANG) || defined(COMPILER_GCC) + #define unreachable __builtin_unreachable() +#else + #define unreachable throw +#endif + +#define export $export +#define register $register diff --git a/roms/snes-test-roms/bass-untech/nall/pointer.hpp b/roms/snes-test-roms/bass-untech/nall/pointer.hpp new file mode 100644 index 00000000..0e96ddb0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/pointer.hpp @@ -0,0 +1,34 @@ +#pragma once + +namespace nall { + +template +struct pointer { + explicit operator bool() const { return value; } + + pointer() = default; + pointer(T* source) { value = source; } + pointer(const pointer& source) { value = source.value; } + + auto& operator=(T* source) { value = source; return *this; } + auto& operator=(const pointer& source) { value = source.value; return *this; } + + auto operator()() -> T* { return value; } + auto operator()() const -> const T* { return value; } + + auto operator->() -> T* { return value; } + auto operator->() const -> const T* { return value; } + + auto operator*() -> T& { return *value; } + auto operator*() const -> const T& { return *value; } + + auto reset() -> void { value = nullptr; } + + auto data() -> T* { return value; } + auto data() const -> const T* { return value; } + +private: + T* value = nullptr; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/posix/service.hpp b/roms/snes-test-roms/bass-untech/nall/posix/service.hpp new file mode 100644 index 00000000..4d71c6f4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/posix/service.hpp @@ -0,0 +1,114 @@ +#pragma once + +#include + +namespace nall { + +struct service { + explicit operator bool() const; + auto command(const string& name, const string& command) -> bool; + auto receive() -> string; + auto name() const -> string; + auto stop() const -> bool; + +private: + shared_memory shared; + string _name; + bool _stop = false; +}; + +inline service::operator bool() const { + return (bool)shared; +} + +//returns true on new service process creation (false is not necessarily an error) +inline auto service::command(const string& name, const string& command) -> bool { + if(!name) return false; + if(!command) return print("[{0}] usage: {service} command\n" + "commands:\n" + " status : query whether service is running\n" + " start : start service if it is not running\n" + " stop : stop service if it is running\n" + " remove : remove semaphore lock if service crashed\n" + " {value} : send custom command to service\n" + "", string_format{name}), false; + + if(shared.open(name, 4096)) { + if(command == "start") { + print("[{0}] already started\n", string_format{name}); + } else if(command == "status") { + print("[{0}] running\n", string_format{name}); + } + if(auto data = shared.acquire()) { + if(command == "stop") print("[{0}] stopped\n", string_format{name}); + memory::copy(data, 4096, command.data(), command.size()); + shared.release(); + } + if(command == "remove") { + shared.remove(); + print("[{0}] removed\n", string_format{name}); + } + return false; + } + + if(command == "start") { + if(shared.create(name, 4096)) { + print("[{0}] started\n", string_format{name}); + auto pid = fork(); + if(pid == 0) { + signal(SIGHUP, SIG_IGN); + signal(SIGPIPE, SIG_IGN); + _name = name; + return true; + } + shared.close(); + } else { + print("[{0}] start failed ({1})\n", string_format{name, strerror(errno)}); + } + return false; + } + + if(command == "status") { + print("[{0}] stopped\n", string_format{name}); + return false; + } + + return false; +} + +inline auto service::receive() -> string { + string command; + if(shared) { + if(auto data = shared.acquire()) { + if(*data) { + command.resize(4095); + memory::copy(command.get(), data, 4095); + memory::fill(data, 4096); + } + shared.release(); + if(command == "remove") { + _stop = true; + return ""; + } else if(command == "start") { + return ""; + } else if(command == "status") { + return ""; + } else if(command == "stop") { + _stop = true; + shared.remove(); + return ""; + } + } + } + return command; +} + +inline auto service::name() const -> string { + return _name; +} + +inline auto service::stop() const -> bool { + return _stop; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/posix/shared-memory.hpp b/roms/snes-test-roms/bass-untech/nall/posix/shared-memory.hpp new file mode 100644 index 00000000..5a4a375f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/posix/shared-memory.hpp @@ -0,0 +1,147 @@ +#pragma once + +#include +#include + +namespace nall { + +struct shared_memory { + shared_memory() = default; + shared_memory(const shared_memory&) = delete; + auto operator=(const shared_memory&) -> shared_memory& = delete; + + ~shared_memory() { + reset(); + } + + explicit operator bool() const { + return _mode != mode::inactive; + } + + auto size() const -> uint { + return _size; + } + + auto acquired() const -> bool { + return _acquired; + } + + auto acquire() -> uint8_t* { + if(!acquired()) { + sem_wait(_semaphore); + _acquired = true; + } + return _data; + } + + auto release() -> void { + if(acquired()) { + sem_post(_semaphore); + _acquired = false; + } + } + + auto reset() -> void { + release(); + if(_mode == mode::server) return remove(); + if(_mode == mode::client) return close(); + } + + auto create(const string& name, uint size) -> bool { + reset(); + + _name = {"/nall-", string{name}.transform("/:", "--")}; + _size = size; + + //O_CREAT | O_EXCL seems to throw ENOENT even when semaphore does not exist ... + _semaphore = sem_open(_name, O_CREAT, 0644, 1); + if(_semaphore == SEM_FAILED) return remove(), false; + + _descriptor = shm_open(_name, O_CREAT | O_TRUNC | O_RDWR, 0644); + if(_descriptor < 0) return remove(), false; + + if(ftruncate(_descriptor, _size) != 0) return remove(), false; + + _data = (uint8_t*)mmap(nullptr, _size, PROT_READ | PROT_WRITE, MAP_SHARED, _descriptor, 0); + if(_data == MAP_FAILED) return remove(), false; + + memory::fill(_data, _size); + + _mode = mode::server; + return true; + } + + auto remove() -> void { + if(_data) { + munmap(_data, _size); + _data = nullptr; + } + + if(_descriptor) { + ::close(_descriptor); + shm_unlink(_name); + _descriptor = -1; + } + + if(_semaphore) { + sem_close(_semaphore); + sem_unlink(_name); + _semaphore = nullptr; + } + + _mode = mode::inactive; + _name = ""; + _size = 0; + } + + auto open(const string& name, uint size) -> bool { + reset(); + + _name = {"/nall-", string{name}.transform("/:", "--")}; + _size = size; + + _semaphore = sem_open(_name, 0, 0644); + if(_semaphore == SEM_FAILED) return close(), false; + + _descriptor = shm_open(_name, O_RDWR, 0644); + if(_descriptor < 0) return close(), false; + + _data = (uint8_t*)mmap(nullptr, _size, PROT_READ | PROT_WRITE, MAP_SHARED, _descriptor, 0); + if(_data == MAP_FAILED) return close(), false; + + _mode = mode::client; + return true; + } + + auto close() -> void { + if(_data) { + munmap(_data, _size); + _data = nullptr; + } + + if(_descriptor) { + ::close(_descriptor); + _descriptor = -1; + } + + if(_semaphore) { + sem_close(_semaphore); + _semaphore = nullptr; + } + + _mode = mode::inactive; + _name = ""; + _size = 0; + } + +private: + enum class mode : uint { server, client, inactive } _mode = mode::inactive; + string _name; + sem_t* _semaphore = nullptr; + int _descriptor = -1; + uint8_t* _data = nullptr; + uint _size = 0; + bool _acquired = false; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives.hpp b/roms/snes-test-roms/bass-untech/nall/primitives.hpp new file mode 100644 index 00000000..fd81129e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives.hpp @@ -0,0 +1,26 @@ +#pragma once + +#include +#include +#include + +namespace nall { + struct Boolean; + template struct Natural; + template struct Integer; + template struct Real; +} + +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nall { + template auto Natural::integer() const -> Integer { return Integer(*this); } + template auto Integer::natural() const -> Natural { return Natural(*this); } +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/bit-field.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/bit-field.hpp new file mode 100644 index 00000000..624876c7 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/bit-field.hpp @@ -0,0 +1,122 @@ +#pragma once + +namespace nall { + +template struct BitField; + +/* static BitField */ + +template struct BitField { + static_assert(Precision >= 1 && Precision <= 64); + using type = + conditional_t>>>; + enum : uint { shift = Index < 0 ? Precision + Index : Index }; + enum : type { mask = 1ull << shift }; + + BitField(const BitField&) = delete; + + auto& operator=(const BitField& source) { + target = target & ~mask | (bool)source << shift; + return *this; + } + + template BitField(T* source) : target((type&)*source) { + static_assert(sizeof(T) == sizeof(type)); + } + + auto bit() const { + return shift; + } + + operator bool() const { + return target & mask; + } + + auto& operator=(bool source) { + target = target & ~mask | source << shift; + return *this; + } + + auto& operator&=(bool source) { + target = target & (~mask | source << shift); + return *this; + } + + auto& operator^=(bool source) { + target = target ^ source << shift; + return *this; + } + + auto& operator|=(bool source) { + target = target | source << shift; + return *this; + } + +private: + type& target; +}; + +/* dynamic BitField */ + +template struct BitField { + static_assert(Precision >= 1 && Precision <= 64); + using type = + conditional_t>>>; + + BitField(const BitField&) = delete; + + auto& operator=(const BitField& source) { + target = target & ~mask | (bool)source << shift; + return *this; + } + + template BitField(T* source, int index) : target((type&)*source) { + static_assert(sizeof(T) == sizeof(type)); + if(index < 0) index = Precision + index; + mask = 1ull << index; + shift = index; + } + + auto bit() const { + return shift; + } + + operator bool() const { + return target & mask; + } + + auto& operator=(bool source) { + target = target & ~mask | source << shift; + return *this; + } + + auto& operator&=(bool source) { + target = target & (~mask | source << shift); + return *this; + } + + auto& operator^=(bool source) { + target = target ^ source << shift; + return *this; + } + + auto& operator|=(bool source) { + target = target | source << shift; + return *this; + } + +private: + type& target; + type mask; + uint shift; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/bit-range.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/bit-range.hpp new file mode 100644 index 00000000..0c95becd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/bit-range.hpp @@ -0,0 +1,251 @@ +#pragma once + +namespace nall { + +/* static BitRange */ + +template struct BitRange { + static_assert(Precision >= 1 && Precision <= 64); + static_assert(Lo < Precision && Hi < Precision); + static_assert(Lo <= Hi); + using type = + conditional_t>>>; + enum : uint { lo = Lo < 0 ? Precision + Lo : Lo }; + enum : uint { hi = Hi < 0 ? Precision + Hi : Hi }; + enum : type { mask = ~0ull >> 64 - (hi - lo + 1) << lo }; + enum : uint { shift = lo }; + + BitRange(const BitRange& source) = delete; + + auto& operator=(const BitRange& source) { + target = target & ~mask | ((source.target & source.mask) >> source.shift) << shift & mask; + return *this; + } + + template BitRange(T* source) : target((type&)*source) { + static_assert(sizeof(T) == sizeof(type)); + } + + operator type() const { + return (target & mask) >> shift; + } + + auto operator++(int) { + auto value = (target & mask) >> shift; + target = target & ~mask | target + (1 << shift) & mask; + return value; + } + + auto operator--(int) { + auto value = (target & mask) >> shift; + target = target & ~mask | target - (1 << shift) & mask; + return value; + } + + auto& operator++() { + target = target & ~mask | target + (1 << shift) & mask; + return *this; + } + + auto& operator--() { + target = target & ~mask | target - (1 << shift) & mask; + return *this; + } + + template auto& operator=(const T& source) { + target = target & ~mask | source << shift & mask; + return *this; + } + + template auto& operator*=(const T& source) { + auto value = ((target & mask) >> shift) * source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator/=(const T& source) { + auto value = ((target & mask) >> shift) / source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator%=(const T& source) { + auto value = ((target & mask) >> shift) % source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator+=(const T& source) { + auto value = ((target & mask) >> shift) + source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator-=(const T& source) { + auto value = ((target & mask) >> shift) - source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator<<=(const T& source) { + auto value = ((target & mask) >> shift) << source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator>>=(const T& source) { + auto value = ((target & mask) >> shift) >> source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator&=(const T& source) { + target = target & (~mask | source << shift & mask); + return *this; + } + + template auto& operator^=(const T& source) { + target = target ^ source << shift & mask; + return *this; + } + + template auto& operator|=(const T& source) { + target = target | source << shift & mask; + return *this; + } + +private: + type& target; +}; + +/* dynamic BitRange */ + +template struct DynamicBitRange { + static_assert(Precision >= 1 && Precision <= 64); + using type = + conditional_t>>>; + + DynamicBitRange(const DynamicBitRange& source) = delete; + + auto& operator=(const DynamicBitRange& source) { + target = target & ~mask | ((source.target & source.mask) >> source.shift) << shift & mask; + return *this; + } + + DynamicBitRange(Type& source, int index) : target(source) { + if(index < 0) index = Precision + index; + mask = 1ull << index; + shift = index; + } + + DynamicBitRange(Type& source, int lo, int hi) : target(source) { + if(lo < 0) lo = Precision + lo; + if(hi < 0) hi = Precision + hi; + if(lo > hi) swap(lo, hi); + mask = ~0ull >> 64 - (hi - lo + 1) << lo; + shift = lo; + } + + operator type() const { + return (target & mask) >> shift; + } + + auto operator++(int) { + auto value = (target & mask) >> shift; + target = target & ~mask | target + (1 << shift) & mask; + return value; + } + + auto operator--(int) { + auto value = (target & mask) >> shift; + target = target & ~mask | target - (1 << shift) & mask; + return value; + } + + auto& operator++() { + target = target & ~mask | target + (1 << shift) & mask; + return *this; + } + + auto& operator--() { + target = target & ~mask | target - (1 << shift) & mask; + return *this; + } + + template auto& operator=(const T& source) { + target = target & ~mask | source << shift & mask; + return *this; + } + + template auto& operator*=(const T& source) { + auto value = ((target & mask) >> shift) * source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator/=(const T& source) { + auto value = ((target & mask) >> shift) / source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator%=(const T& source) { + auto value = ((target & mask) >> shift) % source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator+=(const T& source) { + auto value = ((target & mask) >> shift) + source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator-=(const T& source) { + auto value = ((target & mask) >> shift) - source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator<<=(const T& source) { + auto value = ((target & mask) >> shift) << source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator>>=(const T& source) { + auto value = ((target & mask) >> shift) >> source; + target = target & ~mask | value << shift & mask; + return *this; + } + + template auto& operator&=(const T& source) { + target = target & (~mask | source << shift & mask); + return *this; + } + + template auto& operator^=(const T& source) { + target = target ^ source << shift & mask; + return *this; + } + + template auto& operator|=(const T& source) { + target = target | source << shift & mask; + return *this; + } + +private: + Type& target; + type mask; + uint shift; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/boolean.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/boolean.hpp new file mode 100644 index 00000000..3d92e51a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/boolean.hpp @@ -0,0 +1,30 @@ +#pragma once + +namespace nall { + +struct Boolean { + static constexpr auto bits() -> uint { return 1; } + using btype = bool; + + Boolean() : data(false) {} + template Boolean(const T& value) : data(value) {} + explicit Boolean(const char* value) { data = !strcmp(value, "true"); } + + operator bool() const { return data; } + template auto& operator=(const T& value) { data = value; return *this; } + + auto flip() { return data ^= 1; } + auto raise() { return data == 0 ? data = 1, true : false; } + auto lower() { return data == 1 ? data = 0, true : false; } + + auto flip(bool value) { return data != value ? (data = value, true) : false; } + auto raise(bool value) { return !data && value ? (data = value, true) : (data = value, false); } + auto lower(bool value) { return data && !value ? (data = value, true) : (data = value, false); } + + auto serialize(serializer& s) { s(data); } + +private: + btype data; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/integer.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/integer.hpp new file mode 100644 index 00000000..dfc85803 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/integer.hpp @@ -0,0 +1,86 @@ +#pragma once + +namespace nall { + +template struct Integer { + static_assert(Precision >= 1 && Precision <= 64); + static constexpr auto bits() -> uint { return Precision; } + using stype = + conditional_t>>>; + using utype = typename Natural::utype; + static constexpr auto mask() -> utype { return ~0ull >> 64 - Precision; } + static constexpr auto sign() -> utype { return 1ull << Precision - 1; } + + Integer() : data(0) {} + template Integer(Integer value) { data = cast(value); } + template Integer(const T& value) { data = cast(value); } + explicit Integer(const char* value) { data = cast(toInteger(value)); } + + operator stype() const { return data; } + + auto operator++(int) { auto value = *this; data = cast(data + 1); return value; } + auto operator--(int) { auto value = *this; data = cast(data - 1); return value; } + + auto& operator++() { data = cast(data + 1); return *this; } + auto& operator--() { data = cast(data - 1); return *this; } + + template auto& operator =(const T& value) { data = cast( value); return *this; } + template auto& operator *=(const T& value) { data = cast(data * value); return *this; } + template auto& operator /=(const T& value) { data = cast(data / value); return *this; } + template auto& operator %=(const T& value) { data = cast(data % value); return *this; } + template auto& operator +=(const T& value) { data = cast(data + value); return *this; } + template auto& operator -=(const T& value) { data = cast(data - value); return *this; } + template auto& operator<<=(const T& value) { data = cast(data << value); return *this; } + template auto& operator>>=(const T& value) { data = cast(data >> value); return *this; } + template auto& operator &=(const T& value) { data = cast(data & value); return *this; } + template auto& operator ^=(const T& value) { data = cast(data ^ value); return *this; } + template auto& operator |=(const T& value) { data = cast(data | value); return *this; } + + auto bit(int index) -> DynamicBitRange { return {*this, index}; } + auto bit(int index) const -> const DynamicBitRange { return {(Integer&)*this, index}; } + + auto bit(int lo, int hi) -> DynamicBitRange { return {*this, lo, hi}; } + auto bit(int lo, int hi) const -> const DynamicBitRange { return {(Integer&)*this, lo, hi}; } + + auto byte(int index) -> DynamicBitRange { return {*this, index * 8 + 0, index * 8 + 7}; } + auto byte(int index) const -> const DynamicBitRange { return {(Integer&)*this, index * 8 + 0, index * 8 + 7}; } + + auto mask(int index) const -> utype { + return data & 1 << index; + } + + auto mask(int lo, int hi) const -> utype { + return data & (~0ull >> 64 - (hi - lo + 1) << lo); + } + + auto slice(int index) const { return Natural<>{bit(index)}; } + auto slice(int lo, int hi) const { return Natural<>{bit(lo, hi)}; } + + auto clamp(uint bits) -> stype { + const int64_t b = 1ull << bits - 1; + const int64_t m = b - 1; + return data > m ? m : data < -b ? -b : data; + } + + auto clip(uint bits) -> stype { + const uint64_t b = 1ull << bits - 1; + const uint64_t m = b * 2 - 1; + return (data & m ^ b) - b; + } + + auto serialize(serializer& s) { s(data); } + auto natural() const -> Natural; + +private: + auto cast(stype value) const -> stype { + return (value & mask() ^ sign()) - sign(); + } + + stype data; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/literals.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/literals.hpp new file mode 100644 index 00000000..0e852338 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/literals.hpp @@ -0,0 +1,143 @@ +#pragma once + +namespace nall { + +inline auto operator"" _b(unsigned long long value) { return boolean{value}; } +inline auto operator"" _n(unsigned long long value) { return natural{value}; } +inline auto operator"" _i(unsigned long long value) { return integer{value}; } +inline auto operator"" _r(long double value) { return real{value}; } + +inline auto operator"" _n1(unsigned long long value) { return natural1{value}; } +inline auto operator"" _n2(unsigned long long value) { return natural2{value}; } +inline auto operator"" _n3(unsigned long long value) { return natural3{value}; } +inline auto operator"" _n4(unsigned long long value) { return natural4{value}; } +inline auto operator"" _n5(unsigned long long value) { return natural5{value}; } +inline auto operator"" _n6(unsigned long long value) { return natural6{value}; } +inline auto operator"" _n7(unsigned long long value) { return natural7{value}; } +inline auto operator"" _n8(unsigned long long value) { return natural8{value}; } +inline auto operator"" _n9(unsigned long long value) { return natural9{value}; } +inline auto operator"" _n10(unsigned long long value) { return natural10{value}; } +inline auto operator"" _n11(unsigned long long value) { return natural11{value}; } +inline auto operator"" _n12(unsigned long long value) { return natural12{value}; } +inline auto operator"" _n13(unsigned long long value) { return natural13{value}; } +inline auto operator"" _n14(unsigned long long value) { return natural14{value}; } +inline auto operator"" _n15(unsigned long long value) { return natural15{value}; } +inline auto operator"" _n16(unsigned long long value) { return natural16{value}; } +inline auto operator"" _n17(unsigned long long value) { return natural17{value}; } +inline auto operator"" _n18(unsigned long long value) { return natural18{value}; } +inline auto operator"" _n19(unsigned long long value) { return natural19{value}; } +inline auto operator"" _n20(unsigned long long value) { return natural20{value}; } +inline auto operator"" _n21(unsigned long long value) { return natural21{value}; } +inline auto operator"" _n22(unsigned long long value) { return natural22{value}; } +inline auto operator"" _n23(unsigned long long value) { return natural23{value}; } +inline auto operator"" _n24(unsigned long long value) { return natural24{value}; } +inline auto operator"" _n25(unsigned long long value) { return natural25{value}; } +inline auto operator"" _n26(unsigned long long value) { return natural26{value}; } +inline auto operator"" _n27(unsigned long long value) { return natural27{value}; } +inline auto operator"" _n28(unsigned long long value) { return natural28{value}; } +inline auto operator"" _n29(unsigned long long value) { return natural29{value}; } +inline auto operator"" _n30(unsigned long long value) { return natural30{value}; } +inline auto operator"" _n31(unsigned long long value) { return natural31{value}; } +inline auto operator"" _n32(unsigned long long value) { return natural32{value}; } +inline auto operator"" _n33(unsigned long long value) { return natural33{value}; } +inline auto operator"" _n34(unsigned long long value) { return natural34{value}; } +inline auto operator"" _n35(unsigned long long value) { return natural35{value}; } +inline auto operator"" _n36(unsigned long long value) { return natural36{value}; } +inline auto operator"" _n37(unsigned long long value) { return natural37{value}; } +inline auto operator"" _n38(unsigned long long value) { return natural38{value}; } +inline auto operator"" _n39(unsigned long long value) { return natural39{value}; } +inline auto operator"" _n40(unsigned long long value) { return natural40{value}; } +inline auto operator"" _n41(unsigned long long value) { return natural41{value}; } +inline auto operator"" _n42(unsigned long long value) { return natural42{value}; } +inline auto operator"" _n43(unsigned long long value) { return natural43{value}; } +inline auto operator"" _n44(unsigned long long value) { return natural44{value}; } +inline auto operator"" _n45(unsigned long long value) { return natural45{value}; } +inline auto operator"" _n46(unsigned long long value) { return natural46{value}; } +inline auto operator"" _n47(unsigned long long value) { return natural47{value}; } +inline auto operator"" _n48(unsigned long long value) { return natural48{value}; } +inline auto operator"" _n49(unsigned long long value) { return natural49{value}; } +inline auto operator"" _n50(unsigned long long value) { return natural50{value}; } +inline auto operator"" _n51(unsigned long long value) { return natural51{value}; } +inline auto operator"" _n52(unsigned long long value) { return natural52{value}; } +inline auto operator"" _n53(unsigned long long value) { return natural53{value}; } +inline auto operator"" _n54(unsigned long long value) { return natural54{value}; } +inline auto operator"" _n55(unsigned long long value) { return natural55{value}; } +inline auto operator"" _n56(unsigned long long value) { return natural56{value}; } +inline auto operator"" _n57(unsigned long long value) { return natural57{value}; } +inline auto operator"" _n58(unsigned long long value) { return natural58{value}; } +inline auto operator"" _n59(unsigned long long value) { return natural59{value}; } +inline auto operator"" _n60(unsigned long long value) { return natural60{value}; } +inline auto operator"" _n61(unsigned long long value) { return natural61{value}; } +inline auto operator"" _n62(unsigned long long value) { return natural62{value}; } +inline auto operator"" _n63(unsigned long long value) { return natural63{value}; } +inline auto operator"" _n64(unsigned long long value) { return natural64{value}; } + +inline auto operator"" _i1(unsigned long long value) { return integer1{value}; } +inline auto operator"" _i2(unsigned long long value) { return integer2{value}; } +inline auto operator"" _i3(unsigned long long value) { return integer3{value}; } +inline auto operator"" _i4(unsigned long long value) { return integer4{value}; } +inline auto operator"" _i5(unsigned long long value) { return integer5{value}; } +inline auto operator"" _i6(unsigned long long value) { return integer6{value}; } +inline auto operator"" _i7(unsigned long long value) { return integer7{value}; } +inline auto operator"" _i8(unsigned long long value) { return integer8{value}; } +inline auto operator"" _i9(unsigned long long value) { return integer9{value}; } +inline auto operator"" _i10(unsigned long long value) { return integer10{value}; } +inline auto operator"" _i11(unsigned long long value) { return integer11{value}; } +inline auto operator"" _i12(unsigned long long value) { return integer12{value}; } +inline auto operator"" _i13(unsigned long long value) { return integer13{value}; } +inline auto operator"" _i14(unsigned long long value) { return integer14{value}; } +inline auto operator"" _i15(unsigned long long value) { return integer15{value}; } +inline auto operator"" _i16(unsigned long long value) { return integer16{value}; } +inline auto operator"" _i17(unsigned long long value) { return integer17{value}; } +inline auto operator"" _i18(unsigned long long value) { return integer18{value}; } +inline auto operator"" _i19(unsigned long long value) { return integer19{value}; } +inline auto operator"" _i20(unsigned long long value) { return integer20{value}; } +inline auto operator"" _i21(unsigned long long value) { return integer21{value}; } +inline auto operator"" _i22(unsigned long long value) { return integer22{value}; } +inline auto operator"" _i23(unsigned long long value) { return integer23{value}; } +inline auto operator"" _i24(unsigned long long value) { return integer24{value}; } +inline auto operator"" _i25(unsigned long long value) { return integer25{value}; } +inline auto operator"" _i26(unsigned long long value) { return integer26{value}; } +inline auto operator"" _i27(unsigned long long value) { return integer27{value}; } +inline auto operator"" _i28(unsigned long long value) { return integer28{value}; } +inline auto operator"" _i29(unsigned long long value) { return integer29{value}; } +inline auto operator"" _i30(unsigned long long value) { return integer30{value}; } +inline auto operator"" _i31(unsigned long long value) { return integer31{value}; } +inline auto operator"" _i32(unsigned long long value) { return integer32{value}; } +inline auto operator"" _i33(unsigned long long value) { return integer33{value}; } +inline auto operator"" _i34(unsigned long long value) { return integer34{value}; } +inline auto operator"" _i35(unsigned long long value) { return integer35{value}; } +inline auto operator"" _i36(unsigned long long value) { return integer36{value}; } +inline auto operator"" _i37(unsigned long long value) { return integer37{value}; } +inline auto operator"" _i38(unsigned long long value) { return integer38{value}; } +inline auto operator"" _i39(unsigned long long value) { return integer39{value}; } +inline auto operator"" _i40(unsigned long long value) { return integer40{value}; } +inline auto operator"" _i41(unsigned long long value) { return integer41{value}; } +inline auto operator"" _i42(unsigned long long value) { return integer42{value}; } +inline auto operator"" _i43(unsigned long long value) { return integer43{value}; } +inline auto operator"" _i44(unsigned long long value) { return integer44{value}; } +inline auto operator"" _i45(unsigned long long value) { return integer45{value}; } +inline auto operator"" _i46(unsigned long long value) { return integer46{value}; } +inline auto operator"" _i47(unsigned long long value) { return integer47{value}; } +inline auto operator"" _i48(unsigned long long value) { return integer48{value}; } +inline auto operator"" _i49(unsigned long long value) { return integer49{value}; } +inline auto operator"" _i50(unsigned long long value) { return integer50{value}; } +inline auto operator"" _i51(unsigned long long value) { return integer51{value}; } +inline auto operator"" _i52(unsigned long long value) { return integer52{value}; } +inline auto operator"" _i53(unsigned long long value) { return integer53{value}; } +inline auto operator"" _i54(unsigned long long value) { return integer54{value}; } +inline auto operator"" _i55(unsigned long long value) { return integer55{value}; } +inline auto operator"" _i56(unsigned long long value) { return integer56{value}; } +inline auto operator"" _i57(unsigned long long value) { return integer57{value}; } +inline auto operator"" _i58(unsigned long long value) { return integer58{value}; } +inline auto operator"" _i59(unsigned long long value) { return integer59{value}; } +inline auto operator"" _i60(unsigned long long value) { return integer60{value}; } +inline auto operator"" _i61(unsigned long long value) { return integer61{value}; } +inline auto operator"" _i62(unsigned long long value) { return integer62{value}; } +inline auto operator"" _i63(unsigned long long value) { return integer63{value}; } +inline auto operator"" _i64(unsigned long long value) { return integer64{value}; } + +inline auto operator"" _r32(long double value) { return real32{value}; } +inline auto operator"" _r64(long double value) { return real32{value}; } + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/natural.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/natural.hpp new file mode 100644 index 00000000..3af3f5aa --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/natural.hpp @@ -0,0 +1,84 @@ +#pragma once + +namespace nall { + +template struct Natural { + static_assert(Precision >= 1 && Precision <= 64); + static constexpr auto bits() -> uint { return Precision; } + using utype = + conditional_t>>>; + static constexpr auto mask() -> utype { return ~0ull >> 64 - Precision; } + + Natural() : data(0) {} + template Natural(Natural value) { data = cast(value); } + template Natural(const T& value) { data = cast(value); } + explicit Natural(const char* value) { data = cast(toNatural(value)); } + + operator utype() const { return data; } + + auto operator++(int) { auto value = *this; data = cast(data + 1); return value; } + auto operator--(int) { auto value = *this; data = cast(data - 1); return value; } + + auto& operator++() { data = cast(data + 1); return *this; } + auto& operator--() { data = cast(data - 1); return *this; } + + template auto& operator =(const T& value) { data = cast( value); return *this; } + template auto& operator *=(const T& value) { data = cast(data * value); return *this; } + template auto& operator /=(const T& value) { data = cast(data / value); return *this; } + template auto& operator %=(const T& value) { data = cast(data % value); return *this; } + template auto& operator +=(const T& value) { data = cast(data + value); return *this; } + template auto& operator -=(const T& value) { data = cast(data - value); return *this; } + template auto& operator<<=(const T& value) { data = cast(data << value); return *this; } + template auto& operator>>=(const T& value) { data = cast(data >> value); return *this; } + template auto& operator &=(const T& value) { data = cast(data & value); return *this; } + template auto& operator ^=(const T& value) { data = cast(data ^ value); return *this; } + template auto& operator |=(const T& value) { data = cast(data | value); return *this; } + + auto bit(int index) -> DynamicBitRange { return {*this, index}; } + auto bit(int index) const -> const DynamicBitRange { return {(Natural&)*this, index}; } + + auto bit(int lo, int hi) -> DynamicBitRange { return {*this, lo, hi}; } + auto bit(int lo, int hi) const -> const DynamicBitRange { return {(Natural&)*this, lo, hi}; } + + auto byte(int index) -> DynamicBitRange { return {*this, index * 8 + 0, index * 8 + 7}; } + auto byte(int index) const -> const DynamicBitRange { return {(Natural&)*this, index * 8 + 0, index * 8 + 7}; } + + auto mask(int index) const -> utype { + return data & 1 << index; + } + + auto mask(int lo, int hi) const -> utype { + return data & (~0ull >> 64 - (hi - lo + 1) << lo); + } + + auto slice(int index) const { return Natural<>{bit(index)}; } + auto slice(int lo, int hi) const { return Natural<>{bit(lo, hi)}; } + + auto clamp(uint bits) -> utype { + const uint64_t b = 1ull << bits - 1; + const uint64_t m = b * 2 - 1; + return data < m ? data : m; + } + + auto clip(uint bits) -> utype { + const uint64_t b = 1ull << bits - 1; + const uint64_t m = b * 2 - 1; + return data & m; + } + + auto serialize(serializer& s) { s(data); } + auto integer() const -> Integer; + +private: + auto cast(utype value) const -> utype { + return value & mask(); + } + + utype data; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/real.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/real.hpp new file mode 100644 index 00000000..d5058f1b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/real.hpp @@ -0,0 +1,39 @@ +#pragma once + +namespace nall { + +template struct Real { + static_assert(Precision == 32 || Precision == 64); + static constexpr auto bits() -> uint { return Precision; } + using ftype = + conditional_t>; + + Real() : data(0.0) {} + template Real(Real value) : data((ftype)value) {} + template Real(const T& value) : data((ftype)value) {} + explicit Real(const char* value) : data((ftype)toReal(value)) {} + + operator ftype() const { return data; } + + auto operator++(int) { auto value = *this; ++data; return value; } + auto operator--(int) { auto value = *this; --data; return value; } + + auto& operator++() { data++; return *this; } + auto& operator--() { data--; return *this; } + + template auto& operator =(const T& value) { data = value; return *this; } + template auto& operator*=(const T& value) { data = data * value; return *this; } + template auto& operator/=(const T& value) { data = data / value; return *this; } + template auto& operator%=(const T& value) { data = data % value; return *this; } + template auto& operator+=(const T& value) { data = data + value; return *this; } + template auto& operator-=(const T& value) { data = data - value; return *this; } + + auto serialize(serializer& s) { s(data); } + +private: + ftype data; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/primitives/types.hpp b/roms/snes-test-roms/bass-untech/nall/primitives/types.hpp new file mode 100644 index 00000000..74ca6a6a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/primitives/types.hpp @@ -0,0 +1,45 @@ +#pragma once + +namespace nall { + using boolean = Boolean; + using natural = Natural<>; + using integer = Integer<>; + using real = Real<>; + + using natural1 = Natural< 1>; using natural2 = Natural< 2>; using natural3 = Natural< 3>; using natural4 = Natural< 4>; + using natural5 = Natural< 5>; using natural6 = Natural< 6>; using natural7 = Natural< 7>; using natural8 = Natural< 8>; + using natural9 = Natural< 9>; using natural10 = Natural<10>; using natural11 = Natural<11>; using natural12 = Natural<12>; + using natural13 = Natural<13>; using natural14 = Natural<14>; using natural15 = Natural<15>; using natural16 = Natural<16>; + using natural17 = Natural<17>; using natural18 = Natural<18>; using natural19 = Natural<19>; using natural20 = Natural<20>; + using natural21 = Natural<21>; using natural22 = Natural<22>; using natural23 = Natural<23>; using natural24 = Natural<24>; + using natural25 = Natural<25>; using natural26 = Natural<26>; using natural27 = Natural<27>; using natural28 = Natural<28>; + using natural29 = Natural<29>; using natural30 = Natural<30>; using natural31 = Natural<31>; using natural32 = Natural<32>; + using natural33 = Natural<33>; using natural34 = Natural<34>; using natural35 = Natural<35>; using natural36 = Natural<36>; + using natural37 = Natural<37>; using natural38 = Natural<38>; using natural39 = Natural<39>; using natural40 = Natural<40>; + using natural41 = Natural<41>; using natural42 = Natural<42>; using natural43 = Natural<43>; using natural44 = Natural<44>; + using natural45 = Natural<45>; using natural46 = Natural<46>; using natural47 = Natural<47>; using natural48 = Natural<48>; + using natural49 = Natural<49>; using natural50 = Natural<50>; using natural51 = Natural<51>; using natural52 = Natural<52>; + using natural53 = Natural<53>; using natural54 = Natural<54>; using natural55 = Natural<55>; using natural56 = Natural<56>; + using natural57 = Natural<57>; using natural58 = Natural<58>; using natural59 = Natural<59>; using natural60 = Natural<60>; + using natural61 = Natural<61>; using natural62 = Natural<62>; using natural63 = Natural<63>; using natural64 = Natural<64>; + + using integer1 = Integer< 1>; using integer2 = Integer< 2>; using integer3 = Integer< 3>; using integer4 = Integer< 4>; + using integer5 = Integer< 5>; using integer6 = Integer< 6>; using integer7 = Integer< 7>; using integer8 = Integer< 8>; + using integer9 = Integer< 9>; using integer10 = Integer<10>; using integer11 = Integer<11>; using integer12 = Integer<12>; + using integer13 = Integer<13>; using integer14 = Integer<14>; using integer15 = Integer<15>; using integer16 = Integer<16>; + using integer17 = Integer<17>; using integer18 = Integer<18>; using integer19 = Integer<19>; using integer20 = Integer<20>; + using integer21 = Integer<21>; using integer22 = Integer<22>; using integer23 = Integer<23>; using integer24 = Integer<24>; + using integer25 = Integer<25>; using integer26 = Integer<26>; using integer27 = Integer<27>; using integer28 = Integer<28>; + using integer29 = Integer<29>; using integer30 = Integer<30>; using integer31 = Integer<31>; using integer32 = Integer<32>; + using integer33 = Integer<33>; using integer34 = Integer<34>; using integer35 = Integer<35>; using integer36 = Integer<36>; + using integer37 = Integer<37>; using integer38 = Integer<38>; using integer39 = Integer<39>; using integer40 = Integer<40>; + using integer41 = Integer<41>; using integer42 = Integer<42>; using integer43 = Integer<43>; using integer44 = Integer<44>; + using integer45 = Integer<45>; using integer46 = Integer<46>; using integer47 = Integer<47>; using integer48 = Integer<48>; + using integer49 = Integer<49>; using integer50 = Integer<50>; using integer51 = Integer<51>; using integer52 = Integer<52>; + using integer53 = Integer<53>; using integer54 = Integer<54>; using integer55 = Integer<55>; using integer56 = Integer<56>; + using integer57 = Integer<57>; using integer58 = Integer<58>; using integer59 = Integer<59>; using integer60 = Integer<60>; + using integer61 = Integer<61>; using integer62 = Integer<62>; using integer63 = Integer<63>; using integer64 = Integer<64>; + + using real32 = Real<32>; + using real64 = Real<64>; +} diff --git a/roms/snes-test-roms/bass-untech/nall/property.hpp b/roms/snes-test-roms/bass-untech/nall/property.hpp new file mode 100644 index 00000000..00dd7c7f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/property.hpp @@ -0,0 +1,13 @@ +#if !defined(property) + #define property1(declaration) public: declaration + #define property2(declaration, getter) public: __declspec(property(get=getter)) declaration; protected: declaration##_ + #define property3(declaration, getter, setter) public: __declspec(property(get=getter, put=setter)) declaration; protected: declaration##_ + #define property_(_1, _2, _3, name, ...) name + #define property(...) property_(__VA_ARGS__, property3, property2, property1)(__VA_ARGS__) +#else + #undef property1 + #undef property2 + #undef property3 + #undef property_ + #undef property +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/queue.hpp b/roms/snes-test-roms/bass-untech/nall/queue.hpp new file mode 100644 index 00000000..6b5e7744 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/queue.hpp @@ -0,0 +1,4 @@ +#include +#include +#include +#include diff --git a/roms/snes-test-roms/bass-untech/nall/queue/spsc.hpp b/roms/snes-test-roms/bass-untech/nall/queue/spsc.hpp new file mode 100644 index 00000000..6201729d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/queue/spsc.hpp @@ -0,0 +1,66 @@ +#pragma once + +//single-producer, single-consumer lockless queue +//includes await functions for spin-loops + +namespace nall { + +template struct queue_spsc; + +template +struct queue_spsc { + auto flush() -> void { + _read = 0; + _write = 2 * Size; + } + + auto size() const -> uint { + return (_write - _read) % (2 * Size); + } + + auto empty() const -> bool { + return size() == 0; + } + + auto full() const -> bool { + return size() == Size; + } + + auto read() -> maybe { + if(empty()) return nothing; + auto value = _data[_read % Size]; + _read = _read + 1 < 2 * Size ? _read + 1 : 0; + return value; + } + + auto write(const T& value) -> bool { + if(full()) return false; + _data[_write % Size] = value; + _write = _write + 1 < 4 * Size ? _write + 1 : 2 * Size; + return true; + } + + auto await_empty() -> void { + while(!empty()) spinloop(); + } + + auto await_read() -> T { + while(empty()) spinloop(); + auto value = _data[_read % Size]; + _read = _read + 1 < 2 * Size ? _read + 1 : 0; + return value; + } + + auto await_write(const T& value) -> void { + while(full()) spinloop(); + _data[_write % Size] = value; + _write = _write + 1 < 4 * Size ? _write + 1 : 2 * Size; + } + +private: + T _data[Size]; + std::atomic _read = 0; + std::atomic _write = 2 * Size; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/queue/st.hpp b/roms/snes-test-roms/bass-untech/nall/queue/st.hpp new file mode 100644 index 00000000..46f3ea7e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/queue/st.hpp @@ -0,0 +1,174 @@ +#pragma once + +//simple circular ring buffer + +namespace nall { + +template struct queue; + +template +struct queue { + auto flush() -> void { + _read = 0; + _write = 2 * Size; + } + + auto size() const -> uint { + return (_write - _read) % (2 * Size); + } + + auto capacity() const -> uint { + return Size; + } + + auto empty() const -> bool { + return size() == 0; + } + + auto full() const -> bool { + return size() == Size; + } + + auto peek(uint index) const -> T { + return _data[(_read + index) % Size]; + } + + auto read() -> maybe { + if(empty()) return nothing; + auto value = _data[_read % Size]; + _read = _read + 1 < 2 * Size ? _read + 1 : 0; + return value; + } + + auto read(const T& fallback) -> T { + if(empty()) return fallback; + auto value = _data[_read % Size]; + _read = _read + 1 < 2 * Size ? _read + 1 : 0; + return value; + } + + auto write(const T& value) -> bool { + if(full()) return false; + _data[_write % Size] = value; + _write = _write + 1 < 4 * Size ? _write + 1 : 2 * Size; + return true; + } + + auto serialize(serializer& s) -> void { + s(_data); + s(_read); + s(_write); + } + +private: + T _data[Size]; + uint _read = 0; + uint _write = 2 * Size; +}; + +template +struct queue { + queue() = default; + queue(const queue& source) { operator=(source); } + queue(queue&& source) { operator=(move(source)); } + ~queue() { reset(); } + + auto operator=(const queue& source) -> queue& { + if(this == &source) return *this; + delete[] _data; + _data = new T[source._capacity]; + _capacity = source._capacity; + _size = source._size; + _read = source._read; + _write = source._write; + for(uint n : range(_capacity)) _data[n] = source._data[n]; + return *this; + } + + auto operator=(queue&& source) -> queue& { + if(this == &source) return *this; + _data = source._data; + _capacity = source._capacity; + _size = source._size; + _read = source._read; + _write = source._write; + source._data = nullptr; + source.reset(); + return *this; + } + + template auto capacity() const -> uint { return _capacity * sizeof(T) / sizeof(U); } + template auto size() const -> uint { return _size * sizeof(T) / sizeof(U); } + auto empty() const -> bool { return _size == 0; } + auto pending() const -> bool { return _size > 0; } + auto full() const -> bool { return _size >= (int)_capacity; } + auto underflow() const -> bool { return _size < 0; } + auto overflow() const -> bool { return _size > (int)_capacity; } + + auto data() -> T* { return _data; } + auto data() const -> const T* { return _data; } + + auto reset() { + delete[] _data; + _data = nullptr; + _capacity = 0; + _size = 0; + _read = 0; + _write = 0; + } + + auto resize(uint capacity, const T& value = {}) -> void { + delete[] _data; + _data = new T[capacity]; + _capacity = capacity; + _size = 0; + _read = 0; + _write = 0; + for(uint n : range(_capacity)) _data[n] = value; + } + + auto flush() -> void { + _size = 0; + _read = 0; + _write = 0; + } + + auto fill(const T& value = {}) -> void { + _size = 0; + _read = 0; + _write = 0; + for(uint n : range(_capacity)) _data[n] = value; + } + + auto peek(uint index) const -> T { + return _data[(_read + index) % _capacity]; + } + + auto read() -> T { + T value = _data[_read++]; + if(_read >= _capacity) _read = 0; + _size--; + return value; + } + + auto write(const T& value) -> void { + _data[_write++] = value; + if(_write >= _capacity) _write = 0; + _size++; + } + + auto serialize(serializer& s) -> void { + s(array_span{_data, _capacity}); + s(_read); + s(_write); + } + +private: + T* _data = nullptr; + uint _capacity = 0; + int _size = 0; + uint _read = 0; + uint _write = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/random.hpp b/roms/snes-test-roms/bass-untech/nall/random.hpp new file mode 100644 index 00000000..53e1e015 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/random.hpp @@ -0,0 +1,168 @@ +#pragma once + +#include +#include +#include +#include +#include +#if !defined(PLATFORM_ANDROID) +#include +#endif + +#if defined(PLATFORM_LINUX) && __has_include() + #include +#elif defined(PLATFORM_ANDROID) && __has_include() + #include +#elif defined(PLATFORM_WINDOWS) && __has_include() + #include +#else + #include +#endif + +namespace nall { + +template struct RNG { + template auto random() -> T { + T value = 0; + for(uint n : range((sizeof(T) + 3) / 4)) { + value = value << 32 | (uint32_t)static_cast(this)->read(); + } + return value; + } + + template auto bound(T range) -> T { + T threshold = -range % range; + while(true) { + T value = random(); + if(value >= threshold) return value % range; + } + } + +protected: + auto randomSeed() -> uint256_t { + uint256_t seed = 0; + #if defined(PLATFORM_BSD) || defined(PLATFORM_MACOS) + for(uint n : range(8)) seed = seed << 32 | (uint32_t)arc4random(); + #elif defined(PLATFORM_LINUX) && __has_include() + getrandom(&seed, 32, GRND_NONBLOCK); + #elif defined(PLATFORM_ANDROID) && __has_include() + syscall(__NR_getrandom, &seed, 32, 0x0001); //GRND_NONBLOCK + #elif defined(PLATFORM_WINDOWS) && __has_include() + HCRYPTPROV provider; + if(CryptAcquireContext(&provider, nullptr, MS_STRONG_PROV, PROV_RSA_FULL, CRYPT_VERIFYCONTEXT)) { + CryptGenRandom(provider, 32, (BYTE*)&seed); + CryptReleaseContext(provider, 0); + } + #else + srand(time(nullptr)); + for(uint n : range(32)) seed = seed << 8 | (uint8_t)rand(); + if(auto fp = fopen("/dev/urandom", "rb")) { + fread(&seed, 32, 1, fp); + fclose(fp); + } + #endif + return seed; + } +}; + +namespace PRNG { + +//Galois linear feedback shift register using CRC64 polynomials +struct LFSR : RNG { + LFSR() { seed(); } + + auto seed(maybe seed = {}) -> void { + lfsr = seed ? seed() : (uint64_t)randomSeed(); + for(uint n : range(8)) read(); //hide the CRC64 polynomial from initial output + } + + auto serialize(serializer& s) -> void { + s(lfsr); + } + +private: + auto read() -> uint64_t { + return lfsr = (lfsr >> 1) ^ (-(lfsr & 1) & crc64); + } + + static const uint64_t crc64 = 0xc96c'5795'd787'0f42; + uint64_t lfsr = crc64; + + friend class RNG; +}; + +struct PCG : RNG { + PCG() { seed(); } + + auto seed(maybe seed = {}, maybe sequence = {}) -> void { + if(!seed) seed = (uint32_t)randomSeed(); + if(!sequence) sequence = 0; + + state = 0; + increment = sequence() << 1 | 1; + read(); + state += seed(); + read(); + } + + auto serialize(serializer& s) -> void { + s(state); + s(increment); + } + +private: + auto read() -> uint32_t { + uint64_t state = this->state; + this->state = state * 6'364'136'223'846'793'005ull + increment; + uint32_t xorshift = (state >> 18 ^ state) >> 27; + uint32_t rotate = state >> 59; + return xorshift >> rotate | xorshift << (-rotate & 31); + } + + uint64_t state = 0; + uint64_t increment = 0; + + friend class RNG; +}; + +} + +#if !defined(PLATFORM_ANDROID) +namespace CSPRNG { + +//XChaCha20 cryptographically secure pseudo-random number generator +struct XChaCha20 : RNG { + XChaCha20() { seed(); } + + auto seed(maybe key = {}, maybe nonce = {}) -> void { + //the randomness comes from the key; the nonce just adds a bit of added entropy + if(!key) key = randomSeed(); + if(!nonce) nonce = (uint192_t)clock() << 64 | chrono::nanosecond(); + context = {key(), nonce()}; + } + +private: + auto read() -> uint32_t { + if(!counter) { context.cipher(); context.increment(); } + uint32_t value = context.block[counter++]; + if(counter == 16) counter = 0; //64-bytes per block; 4 bytes per read + return value; + } + + Cipher::XChaCha20 context{0, 0}; + uint counter = 0; + + friend class RNG; +}; + +} +#endif + +// + +template inline auto random() -> T { + static PRNG::PCG pcg; //note: unseeded + return pcg.random(); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/range.hpp b/roms/snes-test-roms/bass-untech/nall/range.hpp new file mode 100644 index 00000000..891f5eca --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/range.hpp @@ -0,0 +1,51 @@ +#pragma once + +namespace nall { + +struct range_t { + struct iterator { + iterator(int64_t position, int64_t step = 0) : position(position), step(step) {} + auto operator*() const -> int64_t { return position; } + auto operator!=(const iterator& source) const -> bool { return step > 0 ? position < source.position : position > source.position; } + auto operator++() -> iterator& { position += step; return *this; } + + private: + int64_t position; + const int64_t step; + }; + + struct reverse_iterator { + reverse_iterator(int64_t position, int64_t step = 0) : position(position), step(step) {} + auto operator*() const -> int64_t { return position; } + auto operator!=(const reverse_iterator& source) const -> bool { return step > 0 ? position > source.position : position < source.position; } + auto operator++() -> reverse_iterator& { position -= step; return *this; } + + private: + int64_t position; + const int64_t step; + }; + + auto begin() const -> iterator { return {origin, stride}; } + auto end() const -> iterator { return {target}; } + + auto rbegin() const -> reverse_iterator { return {target - stride, stride}; } + auto rend() const -> reverse_iterator { return {origin - stride}; } + + int64_t origin; + int64_t target; + int64_t stride; +}; + +inline auto range(int64_t size) { + return range_t{0, size, 1}; +} + +inline auto range(int64_t offset, int64_t size) { + return range_t{offset, size, 1}; +} + +inline auto range(int64_t offset, int64_t size, int64_t step) { + return range_t{offset, size, step}; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/amd64.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/amd64.hpp new file mode 100644 index 00000000..2679599f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/amd64.hpp @@ -0,0 +1,14 @@ +#pragma once + +namespace nall::recompiler { + struct amd64 { + #include "emitter.hpp" + #include "constants.hpp" + #include "encoder-instructions.hpp" + #if defined(PLATFORM_WINDOWS) + #include "encoder-calls-windows.hpp" + #else + #include "encoder-calls-systemv.hpp" + #endif + }; +} diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/constants.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/constants.hpp new file mode 100644 index 00000000..0d1ff6d3 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/constants.hpp @@ -0,0 +1,137 @@ +#pragma once + +//{ + struct imm8 { + explicit imm8(u8 data) : data(data) {} + u8 data; + }; + + struct imm16 { + explicit imm16(u16 data) : data(data) {} + u16 data; + }; + + struct imm32 { + explicit imm32(u32 data) : data(data) {} + u32 data; + }; + + struct imm64 { + explicit imm64(u64 data) : data(data) {} + template explicit imm64(T* pointer) : data((u64)pointer) {} + template explicit imm64(auto (C::*function)(P...) -> R) { + union force_cast_ub { + auto (C::*function)(P...) -> R; + u64 pointer; + } cast{function}; + data = cast.pointer; + } + template explicit imm64(auto (C::*function)(P...) const -> R) { + union force_cast_ub { + auto (C::*function)(P...) const -> R; + u64 pointer; + } cast{function}; + data = cast.pointer; + } + u64 data; + }; + + struct mem64 { + explicit mem64(u64 data) : data(data) {} + template explicit mem64(T* pointer) : data((u64)pointer) {} + template explicit mem64(T C::*variable, C* object) { + union force_cast_ub { + T C::*variable; + u64 pointer; + } cast{variable}; + data = cast.pointer + u64(object); + } + u64 data; + }; + + enum class reg8 : uint { + al, cl, dl, bl, ah, ch, dh, bh, r8b, r9b, r10b, r11b, r12b, r13b, r14b, r15b, + }; + static constexpr reg8 al = reg8::al; + static constexpr reg8 cl = reg8::cl; + static constexpr reg8 dl = reg8::dl; + static constexpr reg8 bl = reg8::bl; + static constexpr reg8 ah = reg8::ah; + static constexpr reg8 ch = reg8::ch; + static constexpr reg8 dh = reg8::dh; + static constexpr reg8 bh = reg8::bh; + static constexpr reg8 r8b = reg8::r8b; + static constexpr reg8 r9b = reg8::r9b; + static constexpr reg8 r10b = reg8::r10b; + static constexpr reg8 r11b = reg8::r11b; + static constexpr reg8 r12b = reg8::r12b; + static constexpr reg8 r13b = reg8::r13b; + static constexpr reg8 r14b = reg8::r14b; + static constexpr reg8 r15b = reg8::r15b; + + enum class reg16 : uint { + ax, cx, dx, bx, sp, bp, si, di, r8w, r9w, r10w, r11w, r12w, r13w, r14w, r15w, + }; + static constexpr reg16 ax = reg16::ax; + static constexpr reg16 cx = reg16::cx; + static constexpr reg16 dx = reg16::dx; + static constexpr reg16 bx = reg16::bx; + static constexpr reg16 sp = reg16::sp; + static constexpr reg16 bp = reg16::bp; + static constexpr reg16 si = reg16::si; + static constexpr reg16 di = reg16::di; + static constexpr reg16 r8w = reg16::r8w; + static constexpr reg16 r9w = reg16::r9w; + static constexpr reg16 r10w = reg16::r10w; + static constexpr reg16 r11w = reg16::r11w; + static constexpr reg16 r12w = reg16::r12w; + static constexpr reg16 r13w = reg16::r13w; + static constexpr reg16 r14w = reg16::r14w; + static constexpr reg16 r15w = reg16::r15w; + + enum class reg32 : uint { + eax, ecx, edx, ebx, esp, ebp, esi, edi, r8d, r9d, r10d, r11d, r12d, r13d, r14d, r15d, + }; + static constexpr reg32 eax = reg32::eax; + static constexpr reg32 ecx = reg32::ecx; + static constexpr reg32 edx = reg32::edx; + static constexpr reg32 ebx = reg32::ebx; + static constexpr reg32 esp = reg32::esp; + static constexpr reg32 ebp = reg32::ebp; + static constexpr reg32 esi = reg32::esi; + static constexpr reg32 edi = reg32::edi; + static constexpr reg32 r8d = reg32::r8d; + static constexpr reg32 r9d = reg32::r9d; + static constexpr reg32 r10d = reg32::r10d; + static constexpr reg32 r11d = reg32::r11d; + static constexpr reg32 r12d = reg32::r12d; + static constexpr reg32 r13d = reg32::r13d; + static constexpr reg32 r14d = reg32::r14d; + static constexpr reg32 r15d = reg32::r15d; + + enum class reg64 : uint { + rax, rcx, rdx, rbx, rsp, rbp, rsi, rdi, r8, r9, r10, r11, r12, r13, r14, r15, + }; + static constexpr reg64 rax = reg64::rax; + static constexpr reg64 rcx = reg64::rcx; + static constexpr reg64 rdx = reg64::rdx; + static constexpr reg64 rbx = reg64::rbx; + static constexpr reg64 rsp = reg64::rsp; + static constexpr reg64 rbp = reg64::rbp; + static constexpr reg64 rsi = reg64::rsi; + static constexpr reg64 rdi = reg64::rdi; + static constexpr reg64 r8 = reg64::r8; + static constexpr reg64 r9 = reg64::r9; + static constexpr reg64 r10 = reg64::r10; + static constexpr reg64 r11 = reg64::r11; + static constexpr reg64 r12 = reg64::r12; + static constexpr reg64 r13 = reg64::r13; + static constexpr reg64 r14 = reg64::r14; + static constexpr reg64 r15 = reg64::r15; + + struct dis64 { + explicit dis64(reg64 base, s32 offset) : base(base), offset(offset) {} + reg64 base; + s32 offset; + }; +//}; diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/emitter.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/emitter.hpp new file mode 100644 index 00000000..82d4309a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/emitter.hpp @@ -0,0 +1,58 @@ +#pragma once + +struct emitter { + auto byte(u8 data) { + span.write(data); + } + + auto word(u16 data) { + span.write(data >> 0); + span.write(data >> 8); + } + + auto dword(u32 data) { + span.write(data >> 0); + span.write(data >> 8); + span.write(data >> 16); + span.write(data >> 24); + } + + auto qword(u64 data) { + span.write(data >> 0); + span.write(data >> 8); + span.write(data >> 16); + span.write(data >> 24); + span.write(data >> 32); + span.write(data >> 40); + span.write(data >> 48); + span.write(data >> 56); + } + + auto rex(bool w, bool r, bool x, bool b) { + u8 data = 0x40 | w << 3 | r << 2 | x << 1 | b << 0; + if(data == 0x40) return; //rex prefix not needed + byte(data); + } + + auto modrm(u8 mod, u8 reg, u8 rm) { + byte(mod << 6 | reg << 3 | rm << 0); + } + + //scale: {index*1, index*2, index*4, index*8} + //index: {eax, ecx, edx, ebx, invalid, ebp, esi, edi} + //base: {eax, ecx, edx, ebx, esp, displacement, esi, edi} + auto sib(u8 scale, u8 index, u8 base) { + byte(scale << 6 | index << 3 | base << 0); + } + + array_span span, origin; +} emit; + +auto bind(array_span span) { + emit.span = span; + emit.origin = span; +} + +auto size() const -> u32 { + return emit.span.data() - emit.origin.data(); +} diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-systemv.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-systemv.hpp new file mode 100644 index 00000000..db782d33 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-systemv.hpp @@ -0,0 +1,73 @@ +#pragma once + +//{ + //virtual instructions to call member functions + template + auto call(auto (C::*function)(P...) -> R, C* object) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + call(rax); + add(rsp, imm8{0x08}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + mov(rsi, imm64{p0}); + call(rax); + add(rsp, imm8{0x08}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + mov(rsi, imm64{p0}); + mov(rdx, imm64{p1}); + call(rax); + add(rsp, imm8{0x08}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + mov(rsi, imm64{p0}); + mov(rdx, imm64{p1}); + mov(rcx, imm64{p2}); + call(rax); + add(rsp, imm8{0x08}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2, P3 p3) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + mov(rsi, imm64{p0}); + mov(rdx, imm64{p1}); + mov(rcx, imm64{p2}); + mov(r8, imm64{p3}); + call(rax); + add(rsp, imm8{0x08}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2, P3 p3, P4 p4) { + sub(rsp, imm8{0x08}); + mov(rax, imm64{function}); + mov(rdi, imm64{object}); + mov(rsi, imm64{p0}); + mov(rdx, imm64{p1}); + mov(rcx, imm64{p2}); + mov(r8, imm64{p3}); + mov(r9, imm64{p4}); + call(rax); + add(rsp, imm8{0x08}); + } +//}; diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-windows.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-windows.hpp new file mode 100644 index 00000000..0ad24b31 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-calls-windows.hpp @@ -0,0 +1,76 @@ +#pragma once + +//{ + //virtual instructions to call member functions + template + auto call(auto (C::*function)(P...) -> R, C* object) { + sub(rsp, imm8{0x28}); + mov(rcx, imm64{object}); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x28}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0) { + sub(rsp, imm8{0x28}); + mov(rcx, imm64{object}); + mov(rdx, imm64{p0}); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x28}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1) { + sub(rsp, imm8{0x28}); + mov(rcx, imm64{object}); + mov(rdx, imm64{p0}); + mov(r8, imm64{p1}); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x28}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2) { + sub(rsp, imm8{0x28}); + mov(rcx, imm64{object}); + mov(rdx, imm64{p0}); + mov(r8, imm64{p1}); + mov(r9, imm64{p2}); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x28}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2, P3 p3) { + sub(rsp, imm8{0x38}); + mov(rcx, imm64{object}); + mov(rdx, imm64{p0}); + mov(r8, imm64{p1}); + mov(r9, imm64{p2}); + mov(rax, imm64{p3}); + mov(dis64{rsp, 0x20}, rax); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x38}); + } + + template + auto call(auto (C::*function)(P...) -> R, C* object, P0 p0, P1 p1, P2 p2, P3 p3, P4 p4) { + sub(rsp, imm8{0x38}); + mov(rcx, imm64{object}); + mov(rdx, imm64{p0}); + mov(r8, imm64{p1}); + mov(r9, imm64{p2}); + mov(rax, imm64{p3}); + mov(dis64{rsp, 0x20}, rax); + mov(rax, imm64{p4}); + mov(dis64{rsp, 0x28}, rax); + mov(rax, imm64{function}); + call(rax); + add(rsp, imm8{0x38}); + } +//}; diff --git a/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-instructions.hpp b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-instructions.hpp new file mode 100644 index 00000000..8cc0db7b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/recompiler/amd64/encoder-instructions.hpp @@ -0,0 +1,169 @@ +#pragma once + +//{ + //call reg + auto call(reg64 rt) { + auto _rt = (uint)rt; + emit.rex(0, 0, 0, _rt & 8); + emit.byte(0xff); + emit.modrm(3, 2, _rt & 7); + } + + //mov reg,imm + auto mov(reg64 rt, imm32 is) { + auto _rt = (uint)rt; + emit.rex(1, 0, 0, _rt & 8); + emit.byte(0xc7); + emit.modrm(3, 0, _rt & 7); + emit.dword(is.data); + } + + //mov reg,imm + auto mov(reg64 rt, imm64 is) { + auto _rt = (uint)rt; + emit.rex(1, 0, 0, _rt & 8); + emit.byte(0xb8 | _rt & 7); + emit.qword(is.data); + } + + //mov reg,[mem] + auto mov(reg64 rt, mem64 ps) { + if(unlikely(rt != rax)) throw; + emit.rex(1, 0, 0, 0); + emit.byte(0xa1); + emit.qword(ps.data); + } + + //mov [mem],reg + auto mov(mem64 pt, reg64 rs) { + if(unlikely(rs != rax)) throw; + emit.rex(1, 0, 0, 0); + emit.byte(0xa3); + emit.qword(pt.data); + } + + //mov [reg+mem],reg + //todo: add more valid register combinations + auto mov(dis64 dt, reg64 rs) { + if(unlikely(dt.base != rsp)) throw; + if(unlikely(rs != rax)) throw; + emit.rex(1, 0, 0, 0); + emit.byte(0x89); + emit.modrm(2, 0, 4); + emit.sib(0, 4, 4); + emit.dword(dt.offset); + } + + //ret + auto ret() { + emit.byte(0xc3); + } + + //inc reg + auto inc(reg64 rt) { + auto _rt = (uint)rt; + emit.rex(1, 0, 0, _rt & 8); + emit.byte(0xff); + emit.modrm(3, 0, _rt & 7); + } + + //dec reg + auto dec(reg64 rt) { + auto _rt = (uint)rt; + emit.rex(1, 0, 0, _rt & 8); + emit.byte(0xff); + emit.modrm(3, 1, _rt & 7); + } + + #define op(code) \ + auto _rt = (uint)rt, _rs = (uint)rs; \ + emit.rex(0, _rs & 8, 0, _rt & 8); \ + emit.byte(code); \ + emit.modrm(3, _rs & 7, _rt & 7); + auto adc (reg8 rt, reg8 rs) { op(0x10); } + auto add (reg8 rt, reg8 rs) { op(0x00); } + auto and (reg8 rt, reg8 rs) { op(0x20); } + auto cmp (reg8 rt, reg8 rs) { op(0x38); } + auto mov (reg8 rt, reg8 rs) { op(0x88); } + auto or (reg8 rt, reg8 rs) { op(0x08); } + auto sbb (reg8 rt, reg8 rs) { op(0x18); } + auto sub (reg8 rt, reg8 rs) { op(0x28); } + auto test(reg8 rt, reg8 rs) { op(0x84); } + auto xor (reg8 rt, reg8 rs) { op(0x30); } + #undef op + + #define op(code) \ + auto _rt = (uint)rt, _rs = (uint)rs; \ + emit.byte(0x66); \ + emit.rex(0, _rs & 8, 0, _rt & 8); \ + emit.byte(code); \ + emit.modrm(3, _rs & 7, _rt & 7); + auto adc (reg16 rt, reg16 rs) { op(0x11); } + auto add (reg16 rt, reg16 rs) { op(0x01); } + auto and (reg16 rt, reg16 rs) { op(0x21); } + auto cmp (reg16 rt, reg16 rs) { op(0x39); } + auto mov (reg16 rt, reg16 rs) { op(0x89); } + auto or (reg16 rt, reg16 rs) { op(0x09); } + auto sbb (reg16 rt, reg16 rs) { op(0x19); } + auto sub (reg16 rt, reg16 rs) { op(0x29); } + auto test(reg16 rt, reg16 rs) { op(0x85); } + auto xor (reg16 rt, reg16 rs) { op(0x31); } + #undef op + + #define op(code) \ + auto _rt = (uint)rt, _rs = (uint)rs; \ + emit.rex(0, _rs & 8, 0, _rt & 8); \ + emit.byte(code); \ + emit.modrm(3, _rs & 7, _rt & 7); + auto adc (reg32 rt, reg32 rs) { op(0x11); } + auto add (reg32 rt, reg32 rs) { op(0x01); } + auto and (reg32 rt, reg32 rs) { op(0x21); } + auto cmp (reg32 rt, reg32 rs) { op(0x39); } + auto mov (reg32 rt, reg32 rs) { op(0x89); } + auto or (reg32 rt, reg32 rs) { op(0x09); } + auto sbb (reg32 rt, reg32 rs) { op(0x19); } + auto sub (reg32 rt, reg32 rs) { op(0x29); } + auto test(reg32 rt, reg32 rs) { op(0x85); } + auto xor (reg32 rt, reg32 rs) { op(0x31); } + #undef op + + #define op(code) \ + auto _rt = (uint)rt, _rs = (uint)rs; \ + emit.rex(1, _rs & 8, 0, _rt & 8); \ + emit.byte(code); \ + emit.modrm(3, _rs & 7, _rt & 7); + auto adc (reg64 rt, reg64 rs) { op(0x11); } + auto add (reg64 rt, reg64 rs) { op(0x01); } + auto and (reg64 rt, reg64 rs) { op(0x21); } + auto cmp (reg64 rt, reg64 rs) { op(0x39); } + auto mov (reg64 rt, reg64 rs) { op(0x89); } + auto or (reg64 rt, reg64 rs) { op(0x09); } + auto sbb (reg64 rt, reg64 rs) { op(0x19); } + auto sub (reg64 rt, reg64 rs) { op(0x29); } + auto test(reg64 rt, reg64 rs) { op(0x85); } + auto xor (reg64 rt, reg64 rs) { op(0x31); } + #undef op + + #define op(code, reg) \ + auto _rt = (uint)rt; \ + emit.rex(1, 0, 0, _rt & 8); \ + emit.byte(code); \ + emit.modrm(3, reg, _rt & 7); \ + emit.byte(is.data); + auto adc(reg64 rt, imm8 is) { op(0x83, 2); } + auto add(reg64 rt, imm8 is) { op(0x83, 0); } + auto and(reg64 rt, imm8 is) { op(0x83, 4); } + auto cmp(reg64 rt, imm8 is) { op(0x83, 7); } + auto or (reg64 rt, imm8 is) { op(0x83, 1); } + auto sbb(reg64 rt, imm8 is) { op(0x83, 3); } + auto sub(reg64 rt, imm8 is) { op(0x83, 5); } + auto xor(reg64 rt, imm8 is) { op(0x83, 6); } + #undef op + + #define op(code) \ + emit.byte(code); \ + emit.byte(it.data); + auto jnz(imm8 it) { op(0x75); } + auto jz (imm8 it) { op(0x74); } + #undef op +//}; diff --git a/roms/snes-test-roms/bass-untech/nall/reed-solomon.hpp b/roms/snes-test-roms/bass-untech/nall/reed-solomon.hpp new file mode 100644 index 00000000..d04bb661 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/reed-solomon.hpp @@ -0,0 +1,218 @@ +#pragma once + +namespace nall { + +//RS(n,k) = ReedSolomon +template +struct ReedSolomon { + enum : uint { Parity = Length - Inputs }; + static_assert(Length <= 255 && Length > 0); + static_assert(Parity <= 32 && Parity > 0); + + using Field = GaloisField; + template using Polynomial = Matrix; + + template + static auto shift(Polynomial polynomial) -> Polynomial { + for(int n = Size - 1; n > 0; n--) polynomial[n] = polynomial[n - 1]; + polynomial[0] = 0; + return polynomial; + } + + template + static auto degree(const Polynomial& polynomial) -> uint { + for(int n = Size; n > 0; n--) { + if(polynomial[n - 1] != 0) return n - 1; + } + return 0; + } + + template + static auto evaluate(const Polynomial& polynomial, Field field) -> Field { + Field sum = 0; + for(uint n : range(Size)) sum += polynomial[n] * field.pow(n); + return sum; + } + + Polynomial message; + Polynomial syndromes; + Polynomial locators; + + ReedSolomon() = default; + ReedSolomon(const ReedSolomon&) = default; + + ReedSolomon(const initializer_list& source) { + uint index = 0; + for(auto& value : source) { + if(index >= Length) break; + message[index++] = value; + } + } + + auto operator[](uint index) -> Field& { return message[index]; } + auto operator[](uint index) const -> Field { return message[index]; } + + auto calculateSyndromes() -> void { + static const Polynomial bases = [] { + Polynomial bases; + for(uint n : range(Parity)) { + bases[n] = Field::exp(n); + } + return bases; + }(); + + syndromes = {}; + for(uint m : range(Length)) { + for(uint p : range(Parity)) { + syndromes[p] *= bases[p]; + syndromes[p] += message[m]; + } + } + } + + auto generateParity() -> void { + static const Polynomial matrix = [] { + Polynomial matrix{}; + for(uint row : range(Parity)) { + for(uint col : range(Parity)) { + matrix(row, col) = Field::exp(row * col); + } + } + if(auto result = matrix.invert()) return *result; + throw; //should never occur + }(); + + for(uint p : range(Parity)) message[Inputs + p] = 0; + calculateSyndromes(); + auto parity = matrix * syndromes; + for(uint p : range(Parity)) message[Inputs + p] = parity[Parity - (p + 1)]; + } + + auto syndromesAreZero() -> bool { + for(uint p : range(Parity)) { + if(syndromes[p]) return false; + } + return true; + } + + //algorithm: Berlekamp-Massey + auto calculateLocators() -> void { + Polynomial history{1}; + locators = history; + uint errors = 0; + + for(uint n : range(Parity)) { + Field discrepancy = 0; + for(uint l : range(errors + 1)) { + discrepancy += locators[l] * syndromes[n - l]; + } + + history = shift(history); + if(discrepancy) { + auto located = locators - history * discrepancy; + if(errors * 2 <= n) { + errors = (n + 1) - errors; + history = locators * discrepancy.inv(); + } + locators = located; + } + } + } + + //algorithm: brute force + //todo: implement Chien search here + auto calculateErrors() -> vector { + calculateSyndromes(); + if(syndromesAreZero()) return {}; //no errors detected + calculateLocators(); + vector errors; + for(uint n : range(Length)) { + if(evaluate(locators, Field{2}.pow(255 - n))) continue; + errors.append(Length - (n + 1)); + } + return errors; + } + + template + static auto calculateErasures(array_view errors) -> maybe> { + Polynomial matrix{}; + for(uint row : range(Size)) { + for(uint col : range(Size)) { + uint index = Length - (errors[col] + 1); + matrix(row, col) = Field::exp(row * index); + } + } + return matrix.invert(); + } + + template + auto correctErasures(array_view errors) -> int { + calculateSyndromes(); + if(syndromesAreZero()) return 0; //no errors detected + if(auto matrix = calculateErasures(errors)) { + Polynomial factors; + for(uint n : range(Size)) factors[n] = syndromes[n]; + auto errata = matrix() * factors; + for(uint m : range(Size)) { + message[errors[m]] += errata[m]; + } + calculateSyndromes(); + if(syndromesAreZero()) return Size; //corrected Size errors + return -Size; //failed to correct Size errors + } + return -Size; //should never occur, but might ... + } + + //note: the erasure matrix is generated as a Polynomial, where N is the number of errors to correct. + //because this is a template parameter, and the actual number of errors may very, this function is needed. + //the alternative would be to convert Matrix to a dynamically sized Matrix(Rows, Cols) type, + //but this would require heap memory allocations and would be a massive performance penalty. + auto correctErrata(array_view errors) -> int { + if(errors.size() >= Parity) return -errors.size(); //too many errors to be correctable + + switch(errors.size()) { + case 0: return 0; + case 1: return correctErasures< 1>(errors); + case 2: return correctErasures< 2>(errors); + case 3: return correctErasures< 3>(errors); + case 4: return correctErasures< 4>(errors); + case 5: return correctErasures< 5>(errors); + case 6: return correctErasures< 6>(errors); + case 7: return correctErasures< 7>(errors); + case 8: return correctErasures< 8>(errors); + case 9: return correctErasures< 9>(errors); + case 10: return correctErasures<10>(errors); + case 11: return correctErasures<11>(errors); + case 12: return correctErasures<12>(errors); + case 13: return correctErasures<13>(errors); + case 14: return correctErasures<14>(errors); + case 15: return correctErasures<15>(errors); + case 16: return correctErasures<16>(errors); + case 17: return correctErasures<17>(errors); + case 18: return correctErasures<18>(errors); + case 19: return correctErasures<19>(errors); + case 20: return correctErasures<20>(errors); + case 21: return correctErasures<21>(errors); + case 22: return correctErasures<22>(errors); + case 23: return correctErasures<23>(errors); + case 24: return correctErasures<24>(errors); + case 25: return correctErasures<25>(errors); + case 26: return correctErasures<26>(errors); + case 27: return correctErasures<27>(errors); + case 28: return correctErasures<28>(errors); + case 29: return correctErasures<29>(errors); + case 30: return correctErasures<30>(errors); + case 31: return correctErasures<31>(errors); + case 32: return correctErasures<32>(errors); + } + return -errors.size(); //it's possible to correct more errors if the above switch were extended ... + } + + //convenience function for when erasures aren't needed + auto correctErrors() -> int { + auto errors = calculateErrors(); + return correctErrata(errors); + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/run.hpp b/roms/snes-test-roms/bass-untech/nall/run.hpp new file mode 100644 index 00000000..14f92ec4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/run.hpp @@ -0,0 +1,214 @@ +#pragma once + +//auto execute(const string& name, const string& args...) -> string; +//[[synchronous]] +//executes program, waits for completion, and returns data written to stdout + +//auto invoke(const string& name, const string& args...) -> void; +//[[asynchronous]] +//if a program is specified, it is executed with the arguments provided +//if a file is specified, the file is opened using the program associated with said file type +//if a folder is specified, the folder is opened using the associated file explorer +//if a URL is specified, the default web browser is opened and pointed at the URL requested + +#include +#include + +namespace nall { + +struct execute_result_t { + explicit operator bool() const { return code == EXIT_SUCCESS; } + + int code = EXIT_FAILURE; + string output; + string error; +}; + +#if defined(PLATFORM_MACOS) || defined(PLATFORM_LINUX) || defined(PLATFORM_BSD) + +template inline auto execute(const string& name, P&&... p) -> execute_result_t { + int fdout[2]; + int fderr[2]; + if(pipe(fdout) == -1) return {}; + if(pipe(fderr) == -1) return {}; + + pid_t pid = fork(); + if(pid == 0) { + const char* argv[1 + sizeof...(p) + 1]; + const char** argp = argv; + vector argl(forward

(p)...); + *argp++ = (const char*)name; + for(auto& arg : argl) *argp++ = (const char*)arg; + *argp++ = nullptr; + + dup2(fdout[1], STDOUT_FILENO); + dup2(fderr[1], STDERR_FILENO); + close(fdout[0]); + close(fderr[0]); + close(fdout[1]); + close(fderr[1]); + execvp(name, (char* const*)argv); + //this is called only if execvp fails: + //use _exit instead of exit, to avoid destroying key shared file descriptors + _exit(EXIT_FAILURE); + } else { + close(fdout[1]); + close(fderr[1]); + + char buffer[256]; + execute_result_t result; + + while(true) { + auto size = read(fdout[0], buffer, sizeof(buffer)); + if(size <= 0) break; + + auto offset = result.output.size(); + result.output.resize(offset + size); + memory::copy(result.output.get() + offset, buffer, size); + } + + while(true) { + auto size = read(fderr[0], buffer, sizeof(buffer)); + if(size <= 0) break; + + auto offset = result.error.size(); + result.error.resize(offset + size); + memory::copy(result.error.get() + offset, buffer, size); + } + + close(fdout[0]); + close(fderr[0]); + + int status = 0; + waitpid(pid, &status, 0); + if(!WIFEXITED(status)) return {}; + result.code = WEXITSTATUS(status); + return result; + } +} + +template inline auto invoke(const string& name, P&&... p) -> void { + pid_t pid = fork(); + if(pid == 0) { + const char* argv[1 + sizeof...(p) + 1]; + const char** argp = argv; + vector argl(forward

(p)...); + *argp++ = (const char*)name; + for(auto& arg : argl) *argp++ = (const char*)arg; + *argp++ = nullptr; + + if(execvp(name, (char* const*)argv) < 0) { + #if defined(PLATFORM_MACOS) + execlp("open", "open", (const char*)name, nullptr); + #else + execlp("xdg-open", "xdg-open", (const char*)name, nullptr); + #endif + } + exit(0); + } +} + +#elif defined(PLATFORM_WINDOWS) + +template inline auto execute(const string& name, P&&... p) -> execute_result_t { + vector argl(name, forward

(p)...); + for(auto& arg : argl) if(arg.find(" ")) arg = {"\"", arg, "\""}; + string arguments = argl.merge(" "); + + SECURITY_ATTRIBUTES sa; + ZeroMemory(&sa, sizeof(SECURITY_ATTRIBUTES)); + sa.nLength = sizeof(SECURITY_ATTRIBUTES); + sa.bInheritHandle = true; + sa.lpSecurityDescriptor = nullptr; + + HANDLE stdoutRead; + HANDLE stdoutWrite; + if(!CreatePipe(&stdoutRead, &stdoutWrite, &sa, 0)) return {}; + if(!SetHandleInformation(stdoutRead, HANDLE_FLAG_INHERIT, 0)) return {}; + + HANDLE stderrRead; + HANDLE stderrWrite; + if(!CreatePipe(&stderrRead, &stderrWrite, &sa, 0)) return {}; + if(!SetHandleInformation(stderrRead, HANDLE_FLAG_INHERIT, 0)) return {}; + + HANDLE stdinRead; + HANDLE stdinWrite; + if(!CreatePipe(&stdinRead, &stdinWrite, &sa, 0)) return {}; + if(!SetHandleInformation(stdinWrite, HANDLE_FLAG_INHERIT, 0)) return {}; + + STARTUPINFO si; + ZeroMemory(&si, sizeof(STARTUPINFO)); + si.cb = sizeof(STARTUPINFO); + si.hStdOutput = stdoutWrite; + si.hStdError = stderrWrite; + si.hStdInput = stdinRead; + si.dwFlags = STARTF_USESTDHANDLES; + + PROCESS_INFORMATION pi; + ZeroMemory(&pi, sizeof(PROCESS_INFORMATION)); + + if(!CreateProcess( + nullptr, utf16_t(arguments), + nullptr, nullptr, true, CREATE_NO_WINDOW, + nullptr, nullptr, &si, &pi + )) return {}; + + DWORD exitCode = EXIT_FAILURE; + if(WaitForSingleObject(pi.hProcess, INFINITE)) return {}; + if(!GetExitCodeProcess(pi.hProcess, &exitCode)) return {}; + CloseHandle(pi.hThread); + CloseHandle(pi.hProcess); + + char buffer[256]; + execute_result_t result; + result.code = exitCode; + + while(true) { + DWORD read, available, remaining; + if(!PeekNamedPipe(stdoutRead, nullptr, sizeof(buffer), &read, &available, &remaining)) break; + if(read == 0) break; + + if(!ReadFile(stdoutRead, buffer, sizeof(buffer), &read, nullptr)) break; + if(read == 0) break; + + auto offset = result.output.size(); + result.output.resize(offset + read); + memory::copy(result.output.get() + offset, buffer, read); + } + + while(true) { + DWORD read, available, remaining; + if(!PeekNamedPipe(stderrRead, nullptr, sizeof(buffer), &read, &available, &remaining)) break; + if(read == 0) break; + + if(!ReadFile(stderrRead, buffer, sizeof(buffer), &read, nullptr)) break; + if(read == 0) break; + + auto offset = result.error.size(); + result.error.resize(offset + read); + memory::copy(result.error.get() + offset, buffer, read); + } + + return result; +} + +template inline auto invoke(const string& name, P&&... p) -> void { + vector argl(forward

(p)...); + for(auto& arg : argl) if(arg.find(" ")) arg = {"\"", arg, "\""}; + string arguments = argl.merge(" "); + string directory = Path::program().replace("/", "\\"); + ShellExecute(nullptr, nullptr, utf16_t(name), utf16_t(arguments), utf16_t(directory), SW_SHOWNORMAL); +} + +#else + +template inline auto execute(const string& name, P&&... p) -> string { + return ""; +} + +template inline auto invoke(const string& name, P&&... p) -> void { +} + +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/serial.hpp b/roms/snes-test-roms/bass-untech/nall/serial.hpp new file mode 100644 index 00000000..671e8ffe --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/serial.hpp @@ -0,0 +1,113 @@ +#pragma once + +#include +#include +#include + +#if !defined(API_POSIX) + #error "nall/serial: unsupported system" +#endif + +#include +#include +#include +#include + +namespace nall { + +struct serial { + ~serial() { + close(); + } + + auto readable() -> bool { + if(!opened) return false; + fd_set fdset; + FD_ZERO(&fdset); + FD_SET(port, &fdset); + timeval timeout; + timeout.tv_sec = 0; + timeout.tv_usec = 0; + int result = select(FD_SETSIZE, &fdset, nullptr, nullptr, &timeout); + if(result < 1) return false; + return FD_ISSET(port, &fdset); + } + + //-1 on error, otherwise return bytes read + auto read(uint8_t* data, uint length) -> int { + if(!opened) return -1; + return ::read(port, (void*)data, length); + } + + auto writable() -> bool { + if(!opened) return false; + fd_set fdset; + FD_ZERO(&fdset); + FD_SET(port, &fdset); + timeval timeout; + timeout.tv_sec = 0; + timeout.tv_usec = 0; + int result = select(FD_SETSIZE, nullptr, &fdset, nullptr, &timeout); + if(result < 1) return false; + return FD_ISSET(port, &fdset); + } + + //-1 on error, otherwise return bytes written + auto write(const uint8_t* data, uint length) -> int { + if(!opened) return -1; + return ::write(port, (void*)data, length); + } + + //rate==0: use flow control (synchronous mode) + //rate!=0: baud-rate (asynchronous mode) + auto open(string device, uint rate = 0) -> bool { + close(); + + if(!device) device = "/dev/ttyU0"; //note: default device name is for FreeBSD 10+ + port = ::open(device, O_RDWR | O_NOCTTY | O_NDELAY | O_NONBLOCK); + if(port == -1) return false; + + if(ioctl(port, TIOCEXCL) == -1) { close(); return false; } + if(fcntl(port, F_SETFL, 0) == -1) { close(); return false; } + if(tcgetattr(port, &original_attr) == -1) { close(); return false; } + + termios attr = original_attr; + cfmakeraw(&attr); + cfsetspeed(&attr, rate ? rate : 57600); //rate value has no effect in synchronous mode + + attr.c_lflag &=~ (ECHO | ECHONL | ISIG | ICANON | IEXTEN); + attr.c_iflag &=~ (BRKINT | PARMRK | INPCK | ISTRIP | INLCR | IGNCR | ICRNL | IXON | IXOFF | IXANY); + attr.c_iflag |= (IGNBRK | IGNPAR); + attr.c_oflag &=~ (OPOST); + attr.c_cflag &=~ (CSIZE | CSTOPB | PARENB | CLOCAL); + attr.c_cflag |= (CS8 | CREAD); + if(rate) { + attr.c_cflag &= ~CRTSCTS; + } else { + attr.c_cflag |= CRTSCTS; + } + attr.c_cc[VTIME] = attr.c_cc[VMIN] = 0; + + if(tcsetattr(port, TCSANOW, &attr) == -1) { close(); return false; } + return opened = true; + } + + auto close() -> void { + if(port != -1) { + tcdrain(port); + if(opened) { + tcsetattr(port, TCSANOW, &original_attr); + opened = false; + } + ::close(port); + port = -1; + } + } + +private: + int port = -1; + bool opened = false; + termios original_attr; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/serializer.hpp b/roms/snes-test-roms/bass-untech/nall/serializer.hpp new file mode 100644 index 00000000..0fda6e23 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/serializer.hpp @@ -0,0 +1,180 @@ +#pragma once + +//serializer: a class designed to save and restore the state of classes. +// +//benefits: +//- data() will be portable in size (it is not necessary to specify type sizes.) +//- data() will be portable in endianness (always stored internally as little-endian.) +//- one serialize function can both save and restore class states. +// +//caveats: +//- only plain-old-data can be stored. complex classes must provide serialize(serializer&); +//- floating-point usage is not portable across different implementations + +#include +#include +#include +#include +#include +#include + +namespace nall { + +struct serializer; + +template +struct has_serialize { + template static auto test(decltype(std::declval().serialize(std::declval()))*) -> char; + template static auto test(...) -> long; + static constexpr bool value = sizeof(test(0)) == sizeof(char); +}; +template constexpr bool has_serialize_v = has_serialize::value; + +struct serializer { + explicit operator bool() const { + return _size; + } + + auto reading() const -> bool { + return _mode == 0; + } + + auto writing() const -> bool { + return _mode == 1; + } + + auto setReading() -> void { + _mode = 0; + _size = 0; + } + + auto setWriting() -> void { + _mode = 1; + _size = 0; + } + + auto data() const -> const uint8_t* { + return _data; + } + + auto size() const -> uint { + return _size; + } + + auto capacity() const -> uint { + return _capacity; + } + + auto reserve(uint size) -> void { + if(size > _capacity) { + auto data = new uint8_t[bit::round(size)](); + memory::copy(data, _data, _capacity); + delete[] _data; + _data = data; + _capacity = bit::round(size); + } + } + + template auto operator()(T& value) -> serializer& { + static_assert(has_serialize_v || is_integral_v || is_floating_point_v); + if constexpr(has_serialize_v) { + value.serialize(*this); + } else if constexpr(is_integral_v) { + integer(value); + } else if constexpr(is_floating_point_v) { + real(value); + } + return *this; + } + + template auto operator()(T (&array)[N]) -> serializer& { + for(auto& value : array) operator()(value); + return *this; + } + + template auto operator()(array_span array) -> serializer& { + for(auto& value : array) operator()(value); + return *this; + } + + auto operator=(const serializer& s) -> serializer& { + if(_data) delete[] _data; + + _mode = s._mode; + _data = new uint8_t[s._capacity]; + _size = s._size; + _capacity = s._capacity; + + memory::copy(_data, s._data, s._capacity); + return *this; + } + + auto operator=(serializer&& s) -> serializer& { + if(_data) delete[] _data; + + _mode = s._mode; + _data = s._data; + _size = s._size; + _capacity = s._capacity; + + s._data = nullptr; + return *this; + } + + serializer(const serializer& s) { operator=(s); } + serializer(serializer&& s) { operator=(move(s)); } + + serializer() { + setWriting(); + _data = new uint8_t[1024 * 1024](); + _size = 0; + _capacity = 1024 * 1024; + } + + serializer(const uint8_t* data, uint capacity) { + setReading(); + _data = new uint8_t[capacity](); + _size = 0; + _capacity = capacity; + memory::copy(_data, data, capacity); + } + + ~serializer() { + if(_data) delete[] _data; + } + +private: + template auto integer(T& value) -> serializer& { + enum : uint { size = std::is_same::value ? 1 : sizeof(T) }; + reserve(_size + size); + if(writing()) { + T copy = value; + for(uint n : range(size)) _data[_size++] = copy, copy >>= 8; + } else if(reading()) { + value = 0; + for(uint n : range(size)) value |= (T)_data[_size++] << (n << 3); + } + return *this; + } + + template auto real(T& value) -> serializer& { + enum : uint { size = sizeof(T) }; + reserve(_size + size); + //this is rather dangerous, and not cross-platform safe; + //but there is no standardized way to export floating point values + auto p = (uint8_t*)&value; + if(writing()) { + for(uint n : range(size)) _data[_size++] = p[n]; + } else if(reading()) { + for(uint n : range(size)) p[n] = _data[_size++]; + } + return *this; + } + + bool _mode = 0; + uint8_t* _data = nullptr; + uint _size = 0; + uint _capacity = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/service.hpp b/roms/snes-test-roms/bass-untech/nall/service.hpp new file mode 100644 index 00000000..3d3c9024 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/service.hpp @@ -0,0 +1,13 @@ +#pragma once + +//service model template built on top of shared-memory + +#include + +#if defined(API_POSIX) + #include +#endif + +#if defined(API_WINDOWS) + #include +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/set.hpp b/roms/snes-test-roms/bass-untech/nall/set.hpp new file mode 100644 index 00000000..733bf843 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/set.hpp @@ -0,0 +1,266 @@ +#pragma once + +//set +//implementation: red-black tree +// +//search: O(log n) average; O(log n) worst +//insert: O(log n) average; O(log n) worst +//remove: O(log n) average; O(log n) worst +// +//requirements: +// bool T::operator==(const T&) const; +// bool T::operator< (const T&) const; + +#include +#include + +namespace nall { + +template struct set { + struct node_t { + T value; + bool red = 1; + node_t* link[2] = {nullptr, nullptr}; + node_t() = default; + node_t(const T& value) : value(value) {} + }; + + node_t* root = nullptr; + uint nodes = 0; + + set() = default; + set(const set& source) { operator=(source); } + set(set&& source) { operator=(move(source)); } + set(std::initializer_list list) { for(auto& value : list) insert(value); } + ~set() { reset(); } + + auto operator=(const set& source) -> set& { + if(this == &source) return *this; + reset(); + copy(root, source.root); + nodes = source.nodes; + return *this; + } + + auto operator=(set&& source) -> set& { + if(this == &source) return *this; + root = source.root; + nodes = source.nodes; + source.root = nullptr; + source.nodes = 0; + return *this; + } + + explicit operator bool() const { return nodes; } + auto size() const -> uint { return nodes; } + + auto reset() -> void { + reset(root); + nodes = 0; + } + + auto find(const T& value) -> maybe { + if(node_t* node = find(root, value)) return node->value; + return nothing; + } + + auto find(const T& value) const -> maybe { + if(node_t* node = find(root, value)) return node->value; + return nothing; + } + + auto insert(const T& value) -> maybe { + uint count = size(); + node_t* v = insert(root, value); + root->red = 0; + if(size() == count) return nothing; + return v->value; + } + + template auto insert(const T& value, P&&... p) -> bool { + bool result = insert(value); + insert(forward

(p)...) | result; + return result; + } + + auto remove(const T& value) -> bool { + uint count = size(); + bool done = 0; + remove(root, &value, done); + if(root) root->red = 0; + return size() < count; + } + + template auto remove(const T& value, P&&... p) -> bool { + bool result = remove(value); + return remove(forward

(p)...) | result; + } + + struct base_iterator { + auto operator!=(const base_iterator& source) const -> bool { return position != source.position; } + + auto operator++() -> base_iterator& { + if(++position >= source.size()) { position = source.size(); return *this; } + + if(stack.right()->link[1]) { + stack.append(stack.right()->link[1]); + while(stack.right()->link[0]) stack.append(stack.right()->link[0]); + } else { + node_t* child; + do child = stack.takeRight(); + while(child == stack.right()->link[1]); + } + + return *this; + } + + base_iterator(const set& source, uint position) : source(source), position(position) { + node_t* node = source.root; + while(node) { + stack.append(node); + node = node->link[0]; + } + } + + protected: + const set& source; + uint position; + vector stack; + }; + + struct iterator : base_iterator { + iterator(const set& source, uint position) : base_iterator(source, position) {} + auto operator*() const -> T& { return base_iterator::stack.right()->value; } + }; + + auto begin() -> iterator { return iterator(*this, 0); } + auto end() -> iterator { return iterator(*this, size()); } + + struct const_iterator : base_iterator { + const_iterator(const set& source, uint position) : base_iterator(source, position) {} + auto operator*() const -> const T& { return base_iterator::stack.right()->value; } + }; + + auto begin() const -> const const_iterator { return const_iterator(*this, 0); } + auto end() const -> const const_iterator { return const_iterator(*this, size()); } + +private: + auto reset(node_t*& node) -> void { + if(!node) return; + if(node->link[0]) reset(node->link[0]); + if(node->link[1]) reset(node->link[1]); + delete node; + node = nullptr; + } + + auto copy(node_t*& target, const node_t* source) -> void { + if(!source) return; + target = new node_t(source->value); + target->red = source->red; + copy(target->link[0], source->link[0]); + copy(target->link[1], source->link[1]); + } + + auto find(node_t* node, const T& value) const -> node_t* { + if(node == nullptr) return nullptr; + if(node->value == value) return node; + return find(node->link[node->value < value], value); + } + + auto red(node_t* node) const -> bool { return node && node->red; } + auto black(node_t* node) const -> bool { return !red(node); } + + auto rotate(node_t*& a, bool dir) -> void { + node_t*& b = a->link[!dir]; + node_t*& c = b->link[dir]; + a->red = 1, b->red = 0; + std::swap(a, b); + std::swap(b, c); + } + + auto rotateTwice(node_t*& node, bool dir) -> void { + rotate(node->link[!dir], !dir); + rotate(node, dir); + } + + auto insert(node_t*& node, const T& value) -> node_t* { + if(!node) { nodes++; node = new node_t(value); return node; } + if(node->value == value) { node->value = value; return node; } //prevent duplicate entries + + bool dir = node->value < value; + node_t* v = insert(node->link[dir], value); + if(black(node->link[dir])) return v; + + if(red(node->link[!dir])) { + node->red = 1; + node->link[0]->red = 0; + node->link[1]->red = 0; + } else if(red(node->link[dir]->link[dir])) { + rotate(node, !dir); + } else if(red(node->link[dir]->link[!dir])) { + rotateTwice(node, !dir); + } + + return v; + } + + auto balance(node_t*& node, bool dir, bool& done) -> void { + node_t* p = node; + node_t* s = node->link[!dir]; + if(!s) return; + + if(red(s)) { + rotate(node, dir); + s = p->link[!dir]; + } + + if(black(s->link[0]) && black(s->link[1])) { + if(red(p)) done = 1; + p->red = 0, s->red = 1; + } else { + bool save = p->red; + bool head = node == p; + + if(red(s->link[!dir])) rotate(p, dir); + else rotateTwice(p, dir); + + p->red = save; + p->link[0]->red = 0; + p->link[1]->red = 0; + + if(head) node = p; + else node->link[dir] = p; + + done = 1; + } + } + + auto remove(node_t*& node, const T* value, bool& done) -> void { + if(!node) { done = 1; return; } + + if(node->value == *value) { + if(!node->link[0] || !node->link[1]) { + node_t* save = node->link[!node->link[0]]; + + if(red(node)) done = 1; + else if(red(save)) save->red = 0, done = 1; + + nodes--; + delete node; + node = save; + return; + } else { + node_t* heir = node->link[0]; + while(heir->link[1]) heir = heir->link[1]; + node->value = heir->value; + value = &heir->value; + } + } + + bool dir = node->value < *value; + remove(node->link[dir], value, done); + if(!done) balance(node, dir, done); + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/shared-memory.hpp b/roms/snes-test-roms/bass-untech/nall/shared-memory.hpp new file mode 100644 index 00000000..9d40bca6 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/shared-memory.hpp @@ -0,0 +1,12 @@ +#pragma once + +#include +#include + +#if defined(API_POSIX) + #include +#endif + +#if defined(API_WINDOWS) + #include +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/shared-pointer.hpp b/roms/snes-test-roms/bass-untech/nall/shared-pointer.hpp new file mode 100644 index 00000000..e5755c13 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/shared-pointer.hpp @@ -0,0 +1,291 @@ +#pragma once + +#include +#include +#include +#include + +namespace nall { + +template struct shared_pointer; + +struct shared_pointer_manager { + void* pointer = nullptr; + function deleter; + uint strong = 0; + uint weak = 0; + + shared_pointer_manager(void* pointer) : pointer(pointer) { + } +}; + +template struct shared_pointer; +template struct shared_pointer_weak; +template struct shared_pointer_this; +struct shared_pointer_this_base{}; + +template +struct shared_pointer { + template static auto create(P&&... p) { + return shared_pointer{new T{forward

(p)...}}; + } + + using type = T; + shared_pointer_manager* manager = nullptr; + + template + struct is_compatible { + static constexpr bool value = is_base_of::value || is_base_of::value; + }; + + shared_pointer() { + } + + shared_pointer(T* source) { + operator=(source); + } + + shared_pointer(T* source, const function& deleter) { + operator=(source); + manager->deleter = function([=](void* p) { + deleter((T*)p); + }); + } + + shared_pointer(const shared_pointer& source) { + operator=(source); + } + + shared_pointer(shared_pointer&& source) { + operator=(move(source)); + } + + template::value>> + shared_pointer(const shared_pointer& source) { + operator=(source); + } + + template::value>> + shared_pointer(shared_pointer&& source) { + operator=(move(source)); + } + + template::value>> + shared_pointer(const shared_pointer_weak& source) { + operator=(source); + } + + template::value>> + shared_pointer(const shared_pointer& source, T* pointer) { + if((bool)source && (T*)source.manager->pointer == pointer) { + manager = source.manager; + manager->strong++; + } + } + + ~shared_pointer() { + reset(); + } + + auto operator=(T* source) -> shared_pointer& { + reset(); + if(source) { + manager = new shared_pointer_manager((void*)source); + manager->strong++; + if constexpr(is_base_of_v) { + source->weak = *this; + } + } + return *this; + } + + auto operator=(const shared_pointer& source) -> shared_pointer& { + if(this != &source) { + reset(); + if((bool)source) { + manager = source.manager; + manager->strong++; + } + } + return *this; + } + + auto operator=(shared_pointer&& source) -> shared_pointer& { + if(this != &source) { + reset(); + manager = source.manager; + source.manager = nullptr; + } + return *this; + } + + template::value>> + auto operator=(const shared_pointer& source) -> shared_pointer& { + if((uintptr)this != (uintptr)&source) { + reset(); + if((bool)source) { + manager = source.manager; + manager->strong++; + } + } + return *this; + } + + template::value>> + auto operator=(shared_pointer&& source) -> shared_pointer& { + if((uintptr)this != (uintptr)&source) { + reset(); + manager = source.manager; + source.manager = nullptr; + } + return *this; + } + + template::value>> + auto operator=(const shared_pointer_weak& source) -> shared_pointer& { + reset(); + if((bool)source) { + manager = source.manager; + manager->strong++; + } + return *this; + } + + auto data() -> T* { + if(manager) return (T*)manager->pointer; + return nullptr; + } + + auto data() const -> const T* { + if(manager) return (T*)manager->pointer; + return nullptr; + } + + auto operator->() -> T* { return data(); } + auto operator->() const -> const T* { return data(); } + + auto operator*() -> T& { return *data(); } + auto operator*() const -> const T& { return *data(); } + + auto operator()() -> T& { return *data(); } + auto operator()() const -> const T& { return *data(); } + + template + auto operator==(const shared_pointer& source) const -> bool { + return manager == source.manager; + } + + template + auto operator!=(const shared_pointer& source) const -> bool { + return manager != source.manager; + } + + explicit operator bool() const { + return manager && manager->strong; + } + + auto unique() const -> bool { + return manager && manager->strong == 1; + } + + auto references() const -> uint { + return manager ? manager->strong : 0; + } + + auto reset() -> void { + if(manager && manager->strong) { + //pointer may contain weak references; if strong==0 it may destroy manager + //as such, we must destroy strong before decrementing it to zero + if(manager->strong == 1) { + if(manager->deleter) { + manager->deleter(manager->pointer); + } else { + delete (T*)manager->pointer; + } + manager->pointer = nullptr; + } + if(--manager->strong == 0) { + if(manager->weak == 0) { + delete manager; + } + } + } + manager = nullptr; + } + + template + auto cast() -> shared_pointer { + if(auto pointer = dynamic_cast(data())) { + return {*this, pointer}; + } + return {}; + } +}; + +template +struct shared_pointer_weak { + using type = T; + shared_pointer_manager* manager = nullptr; + + shared_pointer_weak() { + } + + shared_pointer_weak(const shared_pointer& source) { + operator=(source); + } + + auto operator=(const shared_pointer& source) -> shared_pointer_weak& { + reset(); + if(manager = source.manager) manager->weak++; + return *this; + } + + ~shared_pointer_weak() { + reset(); + } + + auto operator==(const shared_pointer_weak& source) const -> bool { + return manager == source.manager; + } + + auto operator!=(const shared_pointer_weak& source) const -> bool { + return manager != source.manager; + } + + explicit operator bool() const { + return manager && manager->strong; + } + + auto acquire() const -> shared_pointer { + return shared_pointer(*this); + } + + auto reset() -> void { + if(manager && --manager->weak == 0) { + if(manager->strong == 0) { + delete manager; + } + } + manager = nullptr; + } +}; + +template +struct shared_pointer_this : shared_pointer_this_base { + shared_pointer_weak weak; + auto shared() -> shared_pointer { return weak; } + auto shared() const -> shared_pointer { return weak; } +}; + +template +auto shared_pointer_make(P&&... p) -> shared_pointer { + return shared_pointer{new T{forward

(p)...}}; +} + +template +struct shared_pointer_new : shared_pointer { + shared_pointer_new(const shared_pointer& source) : shared_pointer(source) {} + template shared_pointer_new(P&&... p) : shared_pointer(new T(forward

(p)...)) {} +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/smtp.hpp b/roms/snes-test-roms/bass-untech/nall/smtp.hpp new file mode 100644 index 00000000..d09823d1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/smtp.hpp @@ -0,0 +1,314 @@ +#pragma once + +#include +#include +#include + +#if !defined(PLATFORM_WINDOWS) + #include + #include + #include + #include +#else + #include + #include +#endif + +namespace nall { + +struct SMTP { + enum class Format : uint { Plain, HTML }; + + auto server(string server, uint16_t port = 25) -> void; + auto from(string mail, string name = "") -> void; + auto to(string mail, string name = "") -> void; + auto cc(string mail, string name = "") -> void; + auto bcc(string mail, string name = "") -> void; + auto attachment(const uint8_t* data, uint size, string name) -> void; + auto attachment(string filename, string name = "") -> bool; + auto subject(string subject) -> void; + auto body(string body, Format format = Format::Plain) -> void; + + auto send() -> bool; + auto message() -> string; + auto response() -> string; + + #if defined(API_WINDOWS) + auto close(int) -> int; + SMTP(); + #endif + +private: + struct Information { + string server; + uint16_t port; + struct Contact { + string mail; + string name; + }; + Contact from; + vector to; + vector cc; + vector bcc; + struct Attachment { + vector buffer; + string name; + }; + string subject; + string body; + Format format = Format::Plain; + vector attachments; + + string message; + string response; + } info; + + auto send(int sock, const string& text) -> bool; + auto recv(int sock) -> string; + auto boundary() -> string; + auto filename(const string& filename) -> string; + auto contact(const Information::Contact& contact) -> string; + auto contacts(const vector& contacts) -> string; + auto split(const string& text) -> string; +}; + +inline auto SMTP::server(string server, uint16_t port) -> void { + info.server = server; + info.port = port; +} + +inline auto SMTP::from(string mail, string name) -> void { + info.from = {mail, name}; +} + +inline auto SMTP::to(string mail, string name) -> void { + info.to.append({mail, name}); +} + +inline auto SMTP::cc(string mail, string name) -> void { + info.cc.append({mail, name}); +} + +inline auto SMTP::bcc(string mail, string name) -> void { + info.bcc.append({mail, name}); +} + +inline auto SMTP::attachment(const uint8_t* data, uint size, string name) -> void { + vector buffer; + buffer.resize(size); + memcpy(buffer.data(), data, size); + info.attachments.append({std::move(buffer), name}); +} + +inline auto SMTP::attachment(string filename, string name) -> bool { + if(!file::exists(filename)) return false; + if(name == "") name = notdir(filename); + auto buffer = file::read(filename); + info.attachments.append({std::move(buffer), name}); + return true; +} + +inline auto SMTP::subject(string subject) -> void { + info.subject = subject; +} + +inline auto SMTP::body(string body, Format format) -> void { + info.body = body; + info.format = format; +} + +inline auto SMTP::send() -> bool { + info.message.append("From: =?UTF-8?B?", Base64::encode(contact(info.from)), "?=\r\n"); + info.message.append("To: =?UTF-8?B?", Base64::encode(contacts(info.to)), "?=\r\n"); + info.message.append("Cc: =?UTF-8?B?", Base64::encode(contacts(info.cc)), "?=\r\n"); + info.message.append("Subject: =?UTF-8?B?", Base64::encode(info.subject), "?=\r\n"); + + string uniqueID = boundary(); + + info.message.append("MIME-Version: 1.0\r\n"); + info.message.append("Content-Type: multipart/mixed; boundary=", uniqueID, "\r\n"); + info.message.append("\r\n"); + + string format = (info.format == Format::Plain ? "text/plain" : "text/html"); + + info.message.append("--", uniqueID, "\r\n"); + info.message.append("Content-Type: ", format, "; charset=UTF-8\r\n"); + info.message.append("Content-Transfer-Encoding: base64\r\n"); + info.message.append("\r\n"); + info.message.append(split(Base64::encode(info.body)), "\r\n"); + info.message.append("\r\n"); + + for(auto& attachment : info.attachments) { + info.message.append("--", uniqueID, "\r\n"); + info.message.append("Content-Type: application/octet-stream\r\n"); + info.message.append("Content-Transfer-Encoding: base64\r\n"); + info.message.append("Content-Disposition: attachment; size=", attachment.buffer.size(), "; filename*=UTF-8''", filename(attachment.name), "\r\n"); + info.message.append("\r\n"); + info.message.append(split(Base64::encode(attachment.buffer)), "\r\n"); + info.message.append("\r\n"); + } + + info.message.append("--", uniqueID, "--\r\n"); + + addrinfo hints; + memset(&hints, 0, sizeof(addrinfo)); + hints.ai_family = AF_UNSPEC; + hints.ai_socktype = SOCK_STREAM; + hints.ai_flags = AI_PASSIVE; + + addrinfo* serverinfo; + int status = getaddrinfo(info.server, string(info.port), &hints, &serverinfo); + if(status != 0) return false; + + int sock = socket(serverinfo->ai_family, serverinfo->ai_socktype, serverinfo->ai_protocol); + if(sock == -1) return false; + + int result = connect(sock, serverinfo->ai_addr, serverinfo->ai_addrlen); + if(result == -1) return false; + + string response; + info.response.append(response = recv(sock)); + if(!response.beginswith("220 ")) { close(sock); return false; } + + send(sock, {"HELO ", info.server, "\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + + send(sock, {"MAIL FROM: <", info.from.mail, ">\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + + for(auto& contact : info.to) { + send(sock, {"RCPT TO: <", contact.mail, ">\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + } + + for(auto& contact : info.cc) { + send(sock, {"RCPT TO: <", contact.mail, ">\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + } + + for(auto& contact : info.bcc) { + send(sock, {"RCPT TO: <", contact.mail, ">\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + } + + send(sock, {"DATA\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("354 ")) { close(sock); return false; } + + send(sock, {info.message, "\r\n", ".\r\n"}); + info.response.append(response = recv(sock)); + if(!response.beginswith("250 ")) { close(sock); return false; } + + send(sock, {"QUIT\r\n"}); + info.response.append(response = recv(sock)); +//if(!response.beginswith("221 ")) { close(sock); return false; } + + close(sock); + return true; +} + +inline auto SMTP::message() -> string { + return info.message; +} + +inline auto SMTP::response() -> string { + return info.response; +} + +inline auto SMTP::send(int sock, const string& text) -> bool { + const char* data = text.data(); + uint size = text.size(); + while(size) { + int length = ::send(sock, (const char*)data, size, 0); + if(length == -1) return false; + data += length; + size -= length; + } + return true; +} + +inline auto SMTP::recv(int sock) -> string { + vector buffer; + while(true) { + char c; + if(::recv(sock, &c, sizeof(char), 0) < 1) break; + buffer.append(c); + if(c == '\n') break; + } + buffer.append(0); + return buffer; +} + +inline auto SMTP::boundary() -> string { + random_lfsr random; + random.seed(time(0)); + string boundary; + for(uint n = 0; n < 16; n++) boundary.append(hex<2>(random())); + return boundary; +} + +inline auto SMTP::filename(const string& filename) -> string { + string result; + for(auto& n : filename) { + if(n <= 32 || n >= 127) result.append("%", hex<2>(n)); + else result.append(n); + } + return result; +} + +inline auto SMTP::contact(const Information::Contact& contact) -> string { + if(!contact.name) return contact.mail; + return {"\"", contact.name, "\" <", contact.mail, ">"}; +} + +inline auto SMTP::contacts(const vector& contacts) -> string { + string result; + for(auto& contact : contacts) { + result.append(this->contact(contact), "; "); + } + result.trimRight("; ", 1L); + return result; +} + +inline auto SMTP::split(const string& text) -> string { + string result; + + uint offset = 0; + while(offset < text.size()) { + uint length = min(76, text.size() - offset); + if(length < 76) { + result.append(text.slice(offset)); + } else { + result.append(text.slice(offset, 76), "\r\n"); + } + offset += length; + } + + return result; +} + +#if defined(API_WINDOWS) +inline auto SMTP::close(int sock) -> int { + return closesocket(sock); +} + +inline SMTP::SMTP() { + int sock = socket(AF_INET, SOCK_STREAM, IPPROTO_TCP); + if(sock == INVALID_SOCKET && WSAGetLastError() == WSANOTINITIALISED) { + WSADATA wsaData; + if(WSAStartup(MAKEWORD(2, 2), &wsaData) != 0) { + WSACleanup(); + return; + } + } else { + close(sock); + } +} +#endif + +} diff --git a/roms/snes-test-roms/bass-untech/nall/stdint.hpp b/roms/snes-test-roms/bass-untech/nall/stdint.hpp new file mode 100644 index 00000000..dbd5fc83 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/stdint.hpp @@ -0,0 +1,87 @@ +#pragma once + +#if defined(_MSC_VER) + typedef signed char int8_t; + typedef signed short int16_t; + typedef signed int int32_t; + typedef signed long long int64_t; + typedef int64_t intmax_t; + #if defined(_WIN64) + typedef int64_t intptr_t; + #else + typedef int32_t intptr_t; + #endif + + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; + typedef unsigned int uint32_t; + typedef unsigned long long uint64_t; + typedef uint64_t uintmax_t; + #if defined(_WIN64) + typedef uint64_t uintptr_t; + #else + typedef uint32_t uintptr_t; + #endif +#else + #include +#endif + +//note: (u)intmax actually mean it: use as many bits as is possible +#if defined(__SIZEOF_INT128__) + using int128_t = signed __int128; + using uint128_t = unsigned __int128; + + #define INTMAX_BITS 128 + using intmax = int128_t; + using uintmax = uint128_t; +#else + #define INTMAX_BITS 64 + using intmax = intmax_t; + using uintmax = uintmax_t; +#endif + +using intptr = intptr_t; +using uintptr = uintptr_t; + +using float32_t = float; +using float64_t = double; +//note: long double size is not reliable across platforms +//using float80_t = long double; + +static_assert(sizeof( int8_t) == 1, "int8_t is not of the correct size" ); +static_assert(sizeof(int16_t) == 2, "int16_t is not of the correct size"); +static_assert(sizeof(int32_t) == 4, "int32_t is not of the correct size"); +static_assert(sizeof(int64_t) == 8, "int64_t is not of the correct size"); + +static_assert(sizeof( uint8_t) == 1, "int8_t is not of the correct size" ); +static_assert(sizeof(uint16_t) == 2, "int16_t is not of the correct size"); +static_assert(sizeof(uint32_t) == 4, "int32_t is not of the correct size"); +static_assert(sizeof(uint64_t) == 8, "int64_t is not of the correct size"); + +static_assert(sizeof(float) >= 4, "float32_t is not of the correct size"); +static_assert(sizeof(double) >= 8, "float64_t is not of the correct size"); +//static_assert(sizeof(long double) >= 10, "float80_t is not of the correct size"); + +using sint = signed int; +using uint = unsigned int; +using real32_t = float; +using real64_t = double; + +//shorthand +using s8 = int8_t; +using s16 = int16_t; +using s32 = int32_t; +using s64 = int64_t; + +using u8 = uint8_t; +using u16 = uint16_t; +using u32 = uint32_t; +using u64 = uint64_t; + +using f32 = float32_t; +using f64 = float64_t; + +#if defined(__SIZEOF_INT128__) + using s128 = int128_t; + using u128 = uint128_t; +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/string.hpp b/roms/snes-test-roms/bass-untech/nall/string.hpp new file mode 100644 index 00000000..9c27f5ce --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string.hpp @@ -0,0 +1,366 @@ +#pragma once + +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nall { + +struct string; +struct string_format; + +struct string_view { + using type = string_view; + + //view.hpp + string_view(); + string_view(const string_view& source); + string_view(string_view&& source); + string_view(const char* data); + string_view(const char* data, uint size); + string_view(const string& source); + template string_view(P&&... p); + ~string_view(); + + auto operator=(const string_view& source) -> type&; + auto operator=(string_view&& source) -> type&; + + explicit operator bool() const; + operator const char*() const; + auto data() const -> const char*; + auto size() const -> uint; + + auto begin() const { return &_data[0]; } + auto end() const { return &_data[size()]; } + +protected: + string* _string; + const char* _data; + mutable int _size; +}; + +//adaptive (SSO + COW) is by far the best choice, the others exist solely to: +//1) demonstrate the performance benefit of combining SSO + COW +//2) rule out allocator bugs by trying different allocators when needed +#define NALL_STRING_ALLOCATOR_ADAPTIVE +//#define NALL_STRING_ALLOCATOR_COPY_ON_WRITE +//#define NALL_STRING_ALLOCATOR_SMALL_STRING_OPTIMIZATION +//#define NALL_STRING_ALLOCATOR_VECTOR + +//cast.hpp +template struct stringify; + +//format.hpp +template auto print(P&&...) -> void; +template auto print(FILE*, P&&...) -> void; +template auto pad(const T& value, long precision = 0, char padchar = ' ') -> string; +auto hex(uintmax value, long precision = 0, char padchar = '0') -> string; +auto octal(uintmax value, long precision = 0, char padchar = '0') -> string; +auto binary(uintmax value, long precision = 0, char padchar = '0') -> string; + +//match.hpp +auto tokenize(const char* s, const char* p) -> bool; +auto tokenize(vector& list, const char* s, const char* p) -> bool; + +//utf8.hpp +auto characters(string_view self, int offset = 0, int length = -1) -> uint; + +//utility.hpp +auto slice(string_view self, int offset = 0, int length = -1) -> string; +template auto fromInteger(char* result, T value) -> char*; +template auto fromNatural(char* result, T value) -> char*; +template auto fromReal(char* str, T value) -> uint; + +struct string { + using type = string; + +protected: + #if defined(NALL_STRING_ALLOCATOR_ADAPTIVE) + enum : uint { SSO = 24 }; + union { + struct { //copy-on-write + char* _data; + uint* _refs; + }; + struct { //small-string-optimization + char _text[SSO]; + }; + }; + auto _allocate() -> void; + auto _copy() -> void; + auto _resize() -> void; + #endif + + #if defined(NALL_STRING_ALLOCATOR_COPY_ON_WRITE) + char* _data; + mutable uint* _refs; + auto _allocate() -> char*; + auto _copy() -> char*; + #endif + + #if defined(NALL_STRING_ALLOCATOR_SMALL_STRING_OPTIMIZATION) + enum : uint { SSO = 24 }; + union { + char* _data; + char _text[SSO]; + }; + #endif + + #if defined(NALL_STRING_ALLOCATOR_VECTOR) + char* _data; + #endif + + uint _capacity; + uint _size; + +public: + string(); + string(string& source) : string() { operator=(source); } + string(const string& source) : string() { operator=(source); } + string(string&& source) : string() { operator=(move(source)); } + template auto get() -> T*; + template auto data() const -> const T*; + template auto size() const -> uint { return _size / sizeof(T); } + template auto capacity() const -> uint { return _capacity / sizeof(T); } + auto reset() -> type&; + auto reserve(uint) -> type&; + auto resize(uint) -> type&; + auto operator=(const string&) -> type&; + auto operator=(string&&) -> type&; + + template string(T&& s, P&&... p) : string() { + append(forward(s), forward

(p)...); + } + ~string() { reset(); } + + explicit operator bool() const { return _size; } + operator const char*() const { return (const char*)data(); } + operator array_span() { return {(char*)get(), size()}; } + operator array_view() const { return {(const char*)data(), size()}; } + operator array_span() { return {(uint8_t*)get(), size()}; } + operator array_view() const { return {(const uint8_t*)data(), size()}; } + + auto operator==(const string& source) const -> bool { + return size() == source.size() && memory::compare(data(), source.data(), size()) == 0; + } + auto operator!=(const string& source) const -> bool { + return size() != source.size() || memory::compare(data(), source.data(), size()) != 0; + } + + auto operator==(const char* source) const -> bool { return strcmp(data(), source) == 0; } + auto operator!=(const char* source) const -> bool { return strcmp(data(), source) != 0; } + + auto operator==(string_view source) const -> bool { return compare(source) == 0; } + auto operator!=(string_view source) const -> bool { return compare(source) != 0; } + auto operator< (string_view source) const -> bool { return compare(source) < 0; } + auto operator<=(string_view source) const -> bool { return compare(source) <= 0; } + auto operator> (string_view source) const -> bool { return compare(source) > 0; } + auto operator>=(string_view source) const -> bool { return compare(source) >= 0; } + + auto begin() -> char* { return &get()[0]; } + auto end() -> char* { return &get()[size()]; } + auto begin() const -> const char* { return &data()[0]; } + auto end() const -> const char* { return &data()[size()]; } + + //atoi.hpp + auto boolean() const -> bool; + auto integer() const -> intmax; + auto natural() const -> uintmax; + auto hex() const -> uintmax; + auto real() const -> double; + + //core.hpp + auto operator[](uint) const -> const char&; + auto operator()(uint, char = 0) const -> char; + template auto assign(P&&...) -> type&; + template auto prepend(const T&, P&&...) -> type&; + template auto prepend(const nall::string_format&, P&&...) -> type&; + template auto _prepend(const stringify&) -> type&; + template auto append(const T&, P&&...) -> type&; + template auto append(const nall::string_format&, P&&...) -> type&; + template auto _append(const stringify&) -> type&; + auto length() const -> uint; + + //find.hpp + auto contains(string_view characters) const -> maybe; + + template auto _find(int, string_view) const -> maybe; + + auto find(string_view source) const -> maybe; + auto ifind(string_view source) const -> maybe; + auto qfind(string_view source) const -> maybe; + auto iqfind(string_view source) const -> maybe; + + auto findFrom(int offset, string_view source) const -> maybe; + auto ifindFrom(int offset, string_view source) const -> maybe; + + auto findNext(int offset, string_view source) const -> maybe; + auto ifindNext(int offset, string_view source) const -> maybe; + + auto findPrevious(int offset, string_view source) const -> maybe; + auto ifindPrevious(int offset, string_view source) const -> maybe; + + //format.hpp + auto format(const nall::string_format& params) -> type&; + + //compare.hpp + template static auto _compare(const char*, uint, const char*, uint) -> int; + + static auto compare(string_view, string_view) -> int; + static auto icompare(string_view, string_view) -> int; + + auto compare(string_view source) const -> int; + auto icompare(string_view source) const -> int; + + auto equals(string_view source) const -> bool; + auto iequals(string_view source) const -> bool; + + auto beginsWith(string_view source) const -> bool; + auto ibeginsWith(string_view source) const -> bool; + + auto endsWith(string_view source) const -> bool; + auto iendsWith(string_view source) const -> bool; + + //convert.hpp + auto downcase() -> type&; + auto upcase() -> type&; + + auto qdowncase() -> type&; + auto qupcase() -> type&; + + auto transform(string_view from, string_view to) -> type&; + + //match.hpp + auto match(string_view source) const -> bool; + auto imatch(string_view source) const -> bool; + + //replace.hpp + template auto _replace(string_view, string_view, long) -> type&; + auto replace(string_view from, string_view to, long limit = LONG_MAX) -> type&; + auto ireplace(string_view from, string_view to, long limit = LONG_MAX) -> type&; + auto qreplace(string_view from, string_view to, long limit = LONG_MAX) -> type&; + auto iqreplace(string_view from, string_view to, long limit = LONG_MAX) -> type&; + + //split.hpp + auto split(string_view key, long limit = LONG_MAX) const -> vector; + auto isplit(string_view key, long limit = LONG_MAX) const -> vector; + auto qsplit(string_view key, long limit = LONG_MAX) const -> vector; + auto iqsplit(string_view key, long limit = LONG_MAX) const -> vector; + + //trim.hpp + auto trim(string_view lhs, string_view rhs, long limit = LONG_MAX) -> type&; + auto trimLeft(string_view lhs, long limit = LONG_MAX) -> type&; + auto trimRight(string_view rhs, long limit = LONG_MAX) -> type&; + + auto itrim(string_view lhs, string_view rhs, long limit = LONG_MAX) -> type&; + auto itrimLeft(string_view lhs, long limit = LONG_MAX) -> type&; + auto itrimRight(string_view rhs, long limit = LONG_MAX) -> type&; + + auto strip() -> type&; + auto stripLeft() -> type&; + auto stripRight() -> type&; + + //utf8.hpp + auto characters(int offset = 0, int length = -1) const -> uint; + + //utility.hpp + static auto read(string_view filename) -> string; + static auto repeat(string_view pattern, uint times) -> string; + auto fill(char fill = ' ') -> type&; + auto hash() const -> uint; + auto remove(uint offset, uint length) -> type&; + auto reverse() -> type&; + auto size(int length, char fill = ' ') -> type&; + auto slice(int offset = 0, int length = -1) const -> string; +}; + +template<> struct vector : vector_base { + using type = vector; + using vector_base::vector_base; + + vector(const vector& source) { vector_base::operator=(source); } + vector(vector& source) { vector_base::operator=(source); } + vector(vector&& source) { vector_base::operator=(move(source)); } + template vector(P&&... p) { append(forward

(p)...); } + + auto operator=(const vector& source) -> type& { return vector_base::operator=(source), *this; } + auto operator=(vector& source) -> type& { return vector_base::operator=(source), *this; } + auto operator=(vector&& source) -> type& { return vector_base::operator=(move(source)), *this; } + + //vector.hpp + template auto append(const string&, P&&...) -> type&; + auto append() -> type&; + + auto isort() -> type&; + auto find(string_view source) const -> maybe; + auto ifind(string_view source) const -> maybe; + auto match(string_view pattern) const -> vector; + auto merge(string_view separator = "") const -> string; + auto strip() -> type&; + + //split.hpp + template auto _split(string_view, string_view, long) -> type&; +}; + +struct string_format : vector { + using type = string_format; + + template string_format(P&&... p) { reserve(sizeof...(p)); append(forward

(p)...); } + template auto append(const T&, P&&... p) -> type&; + auto append() -> type&; +}; + +inline auto operator"" _s(const char* value, std::size_t) -> string { return {value}; } + +} + +#include +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include diff --git a/roms/snes-test-roms/bass-untech/nall/string/allocator/adaptive.hpp b/roms/snes-test-roms/bass-untech/nall/string/allocator/adaptive.hpp new file mode 100644 index 00000000..57505d32 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/allocator/adaptive.hpp @@ -0,0 +1,123 @@ +#pragma once + +/***** + adaptive allocator + sizeof(string) == SSO + 8 + + aggressively tries to avoid heap allocations + small strings are stored on the stack + large strings are shared via copy-on-write + + SSO alone is very slow on large strings due to copying + SSO alone is very slightly faster than this allocator on small strings + + COW alone is very slow on small strings due to heap allocations + COW alone is very slightly faster than this allocator on large strings + + adaptive is thus very fast for all string sizes +*****/ + +namespace nall { + +inline string::string() : _data(nullptr), _capacity(SSO - 1), _size(0) { +} + +template +inline auto string::get() -> T* { + if(_capacity < SSO) return (T*)_text; + if(*_refs > 1) _copy(); + return (T*)_data; +} + +template +inline auto string::data() const -> const T* { + if(_capacity < SSO) return (const T*)_text; + return (const T*)_data; +} + +inline auto string::reset() -> type& { + if(_capacity >= SSO && !--*_refs) memory::free(_data); + _data = nullptr; + _capacity = SSO - 1; + _size = 0; + return *this; +} + +inline auto string::reserve(uint capacity) -> type& { + if(capacity <= _capacity) return *this; + capacity = bit::round(capacity + 1) - 1; + if(_capacity < SSO) { + _capacity = capacity; + _allocate(); + } else if(*_refs > 1) { + _capacity = capacity; + _copy(); + } else { + _capacity = capacity; + _resize(); + } + return *this; +} + +inline auto string::resize(uint size) -> type& { + reserve(size); + get()[_size = size] = 0; + return *this; +} + +inline auto string::operator=(const string& source) -> type& { + if(&source == this) return *this; + reset(); + if(source._capacity >= SSO) { + _data = source._data; + _refs = source._refs; + _capacity = source._capacity; + _size = source._size; + ++*_refs; + } else { + memory::copy(_text, source._text, SSO); + _capacity = source._capacity; + _size = source._size; + } + return *this; +} + +inline auto string::operator=(string&& source) -> type& { + if(&source == this) return *this; + reset(); + memory::copy(this, &source, sizeof(string)); + source._data = nullptr; + source._capacity = SSO - 1; + source._size = 0; + return *this; +} + +//SSO -> COW +inline auto string::_allocate() -> void { + char _temp[SSO]; + memory::copy(_temp, _text, SSO); + _data = memory::allocate(_capacity + 1 + sizeof(uint)); + memory::copy(_data, _temp, SSO); + _refs = (uint*)(_data + _capacity + 1); //always aligned by 32 via reserve() + *_refs = 1; +} + +//COW -> Unique +inline auto string::_copy() -> void { + auto _temp = memory::allocate(_capacity + 1 + sizeof(uint)); + memory::copy(_temp, _data, _size = min(_capacity, _size)); + _temp[_size] = 0; + --*_refs; + _data = _temp; + _refs = (uint*)(_data + _capacity + 1); + *_refs = 1; +} + +//COW -> Resize +inline auto string::_resize() -> void { + _data = memory::resize(_data, _capacity + 1 + sizeof(uint)); + _refs = (uint*)(_data + _capacity + 1); + *_refs = 1; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/allocator/copy-on-write.hpp b/roms/snes-test-roms/bass-untech/nall/string/allocator/copy-on-write.hpp new file mode 100644 index 00000000..9c0452ec --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/allocator/copy-on-write.hpp @@ -0,0 +1,92 @@ +#pragma once + +namespace nall { + +inline string::string() : _data(nullptr), _refs(nullptr), _capacity(0), _size(0) { +} + +template +inline auto string::get() -> T* { + static char _null[] = ""; + if(!_data) return (T*)_null; + if(*_refs > 1) _data = _copy(); //make unique for write operations + return (T*)_data; +} + +template +inline auto string::data() const -> const T* { + static const char _null[] = ""; + if(!_data) return (const T*)_null; + return (const T*)_data; +} + +inline auto string::reset() -> type& { + if(_data && !--*_refs) { + memory::free(_data); + _data = nullptr; //_refs = nullptr; is unnecessary + } + _capacity = 0; + _size = 0; + return *this; +} + +inline auto string::reserve(uint capacity) -> type& { + if(capacity > _capacity) { + _capacity = bit::round(max(31u, capacity) + 1) - 1; + _data = _data ? _copy() : _allocate(); + } + return *this; +} + +inline auto string::resize(uint size) -> type& { + reserve(size); + get()[_size = size] = 0; + return *this; +} + +inline auto string::operator=(const string& source) -> string& { + if(&source == this) return *this; + reset(); + if(source._data) { + _data = source._data; + _refs = source._refs; + _capacity = source._capacity; + _size = source._size; + ++*_refs; + } + return *this; +} + +inline auto string::operator=(string&& source) -> string& { + if(&source == this) return *this; + reset(); + _data = source._data; + _refs = source._refs; + _capacity = source._capacity; + _size = source._size; + source._data = nullptr; + source._refs = nullptr; + source._capacity = 0; + source._size = 0; + return *this; +} + +inline auto string::_allocate() -> char* { + auto _temp = memory::allocate(_capacity + 1 + sizeof(uint)); + *_temp = 0; + _refs = (uint*)(_temp + _capacity + 1); //this will always be aligned by 32 via reserve() + *_refs = 1; + return _temp; +} + +inline auto string::_copy() -> char* { + auto _temp = memory::allocate(_capacity + 1 + sizeof(uint)); + memory::copy(_temp, _data, _size = min(_capacity, _size)); + _temp[_size] = 0; + --*_refs; + _refs = (uint*)(_temp + _capacity + 1); + *_refs = 1; + return _temp; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/allocator/small-string-optimization.hpp b/roms/snes-test-roms/bass-untech/nall/string/allocator/small-string-optimization.hpp new file mode 100644 index 00000000..403981d5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/allocator/small-string-optimization.hpp @@ -0,0 +1,95 @@ +#pragma once + +/* +small string optimization (SSO) allocator +sizeof(string) == 8 + string::SSO + +utilizes a union to store small strings directly into text pointer +bypasses the need to allocate heap memory for small strings +requires extra computations, which can be slower for large strings + +pros: +* potential for in-place resize +* no heap allocation when (capacity < SSO) + +cons: +* added overhead to fetch data() +* pass-by-value requires heap allocation when (capacity >= SSO) + +*/ + +namespace nall { + +inline string::string() { + _data = nullptr; + _capacity = SSO - 1; + _size = 0; +} + +template +inline auto string::get() -> T* { + if(_capacity < SSO) return (T*)_text; + return (T*)_data; +} + +template +inline auto string::data() const -> const T* { + if(_capacity < SSO) return (const T*)_text; + return (const T*)_data; +} + +inline auto string::reset() -> type& { + if(_capacity >= SSO) memory::free(_data); + _data = nullptr; + _capacity = SSO - 1; + _size = 0; + return *this; +} + +inline auto string::reserve(uint capacity) -> type& { + if(capacity <= _capacity) return *this; + capacity = bit::round(capacity + 1) - 1; + if(_capacity < SSO) { + char _temp[SSO]; + memory::copy(_temp, _text, SSO); + _data = memory::allocate(_capacity = capacity + 1); + memory::copy(_data, _temp, SSO); + } else { + _data = memory::resize(_data, _capacity = capacity + 1); + } + return *this; +} + +inline auto string::resize(uint size) -> type& { + reserve(size); + get()[_size = size] = 0; + return *this; +} + +inline auto string::operator=(const string& source) -> type& { + if(&source == this) return *this; + reset(); + if(source._capacity >= SSO) { + _data = memory::allocate(source._capacity + 1); + _capacity = source._capacity; + _size = source._size; + memory::copy(_data, source._data, source._size + 1); + } else { + memory::copy(_text, source._text, SSO); + _capacity = SSO - 1; + _size = source._size; + } + return *this; +} + +inline auto string::operator=(string&& source) -> type& { + if(&source == this) return *this; + reset(); + memory::copy(this, &source, sizeof(string)); + source._data = nullptr; + source._capacity = SSO - 1; + source._size = 0; + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/allocator/vector.hpp b/roms/snes-test-roms/bass-untech/nall/string/allocator/vector.hpp new file mode 100644 index 00000000..15b5de26 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/allocator/vector.hpp @@ -0,0 +1,84 @@ +#pragma once + +/* +vector allocator +sizeof(string) == 16 (amd64) + +utilizes a raw string pointer +always allocates memory onto the heap when string is not empty + +pros: +* potential for in-place resize +* simplicity + +cons: +* always allocates heap memory on (capacity > 0) +* pass-by-value requires heap allocation + +*/ + +namespace nall { + +template +inline auto string::get() -> T* { + if(_capacity == 0) reserve(1); + return (T*)_data; +} + +template +inline auto string::data() const -> const T* { + if(_capacity == 0) return (const T*)""; + return (const T*)_data; +} + +inline auto string::reset() -> type& { + if(_data) { memory::free(_data); _data = nullptr; } + _capacity = 0; + _size = 0; + return *this; +} + +inline auto string::reserve(uint capacity) -> type& { + if(capacity > _capacity) { + _capacity = bit::round(capacity + 1) - 1; + _data = memory::resize(_data, _capacity + 1); + _data[_capacity] = 0; + } + return *this; +} + +inline auto string::resize(uint size) -> type& { + reserve(size); + get()[_size = size] = 0; + return *this; +} + +inline auto string::operator=(const string& source) -> type& { + if(&source == this) return *this; + reset(); + _data = memory::allocate(source._size + 1); + _capacity = source._size; + _size = source._size; + memory::copy(_data, source.data(), source.size() + 1); + return *this; +} + +inline auto string::operator=(string&& source) -> type& { + if(&source == this) return *this; + reset(); + _data = source._data; + _capacity = source._capacity; + _size = source._size; + source._data = nullptr; + source._capacity = 0; + source._size = 0; + return *this; +} + +inline string::string() { + _data = nullptr; + _capacity = 0; + _size = 0; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/atoi.hpp b/roms/snes-test-roms/bass-untech/nall/string/atoi.hpp new file mode 100644 index 00000000..54c93d42 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/atoi.hpp @@ -0,0 +1,25 @@ +#pragma once + +namespace nall { + +inline auto string::boolean() const -> bool { + return equals("true"); +} + +inline auto string::integer() const -> intmax { + return toInteger(data()); +} + +inline auto string::natural() const -> uintmax { + return toNatural(data()); +} + +inline auto string::hex() const -> uintmax { + return toHex(data()); +} + +inline auto string::real() const -> double { + return toReal(data()); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/cast.hpp b/roms/snes-test-roms/bass-untech/nall/string/cast.hpp new file mode 100644 index 00000000..f80754a5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/cast.hpp @@ -0,0 +1,288 @@ +#pragma once + +//convert any (supported) type to a const char* without constructing a new nall::string +//this is used inside string{...} to build nall::string values + +namespace nall { + +//booleans + +template<> struct stringify { + stringify(bool value) : _value(value) {} + auto data() const -> const char* { return _value ? "true" : "false"; } + auto size() const -> uint { return _value ? 4 : 5; } + bool _value; +}; + +template<> struct stringify { + stringify(bool value) : _value(value) {} + auto data() const -> const char* { return _value ? "true" : "false"; } + auto size() const -> uint { return _value ? 4 : 5; } + bool _value; +}; + +//characters + +template<> struct stringify { + stringify(char source) { _data[0] = source; _data[1] = 0; } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return 1; } + char _data[2]; +}; + +//signed integers + +template<> struct stringify { + stringify(signed char source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(signed char) * 3]; +}; + +template<> struct stringify { + stringify(signed short source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(signed short) * 3]; +}; + +template<> struct stringify { + stringify(signed int source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(signed int) * 3]; +}; + +template<> struct stringify { + stringify(signed long source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(signed long) * 3]; +}; + +template<> struct stringify { + stringify(signed long long source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(signed long long) * 3]; +}; + +#if defined(__SIZEOF_INT128__) +template<> struct stringify { + stringify(int128_t source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(int128_t) * 3]; +}; +#endif + +template struct stringify> { + stringify(Integer source) { fromInteger(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[2 + sizeof(int64_t) * 3]; +}; + +//unsigned integers + +template<> struct stringify { + stringify(unsigned char source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(unsigned char) * 3]; +}; + +template<> struct stringify { + stringify(unsigned short source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(unsigned short) * 3]; +}; + +template<> struct stringify { + stringify(unsigned int source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(unsigned int) * 3]; +}; + +template<> struct stringify { + stringify(unsigned long source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(unsigned long) * 3]; +}; + +template<> struct stringify { + stringify(unsigned long long source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(unsigned long long) * 3]; +}; + +#if defined(__SIZEOF_INT128__) +template<> struct stringify { + stringify(uint128_t source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(uint128_t) * 3]; +}; +#endif + +template struct stringify> { + stringify(Natural source) { fromNatural(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[1 + sizeof(uint64_t) * 3]; +}; + +//floating-point + +template<> struct stringify { + stringify(float source) { fromReal(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[256]; +}; + +template<> struct stringify { + stringify(double source) { fromReal(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[256]; +}; + +template<> struct stringify { + stringify(long double source) { fromReal(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[256]; +}; + +template struct stringify> { + stringify(Real source) { fromReal(_data, source); } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[256]; +}; + +//arrays + +template<> struct stringify> { + stringify(vector source) { + _text.resize(source.size()); + memory::copy(_text.data(), source.data(), source.size()); + } + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + vector _text; +}; + +template<> struct stringify&> { + stringify(const vector& source) { + _text.resize(source.size()); + memory::copy(_text.data(), source.data(), source.size()); + } + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + vector _text; +}; + +//char arrays + +template<> struct stringify { + stringify(char* source) : _data(source ? source : "") {} + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + const char* _data; +}; + +template<> struct stringify { + stringify(const char* source) : _data(source ? source : "") {} + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + const char* _data; +}; + +//strings + +template<> struct stringify { + stringify(const string& source) : _text(source) {} + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + const string& _text; +}; + +template<> struct stringify { + stringify(const string& source) : _text(source) {} + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + const string& _text; +}; + +template<> struct stringify { + stringify(const string_view& source) : _view(source) {} + auto data() const -> const char* { return _view.data(); } + auto size() const -> uint { return _view.size(); } + const string_view& _view; +}; + +template<> struct stringify { + stringify(const string_view& source) : _view(source) {} + auto data() const -> const char* { return _view.data(); } + auto size() const -> uint { return _view.size(); } + const string_view& _view; +}; + +template<> struct stringify> { + stringify(const array_view& source) : _view(source) {} + auto data() const -> const char* { return _view.data(); } + auto size() const -> uint { return _view.size(); } + const array_view& _view; +}; + +template<> struct stringify&> { + stringify(const array_view& source) : _view(source) {} + auto data() const -> const char* { return _view.data(); } + auto size() const -> uint { return _view.size(); } + const array_view& _view; +}; + +template<> struct stringify { + stringify(const string_pascal& source) : _text(source) {} + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + const string_pascal& _text; +}; + +template<> struct stringify { + stringify(const string_pascal& source) : _text(source) {} + auto data() const -> const char* { return _text.data(); } + auto size() const -> uint { return _text.size(); } + const string_pascal& _text; +}; + +//pointers + +//note: T = char* is matched by stringify +template struct stringify { + stringify(const T* source) { + if(!source) { + memory::copy(_data, "(nullptr)", 10); + } else { + memory::copy(_data, "0x", 2); + fromNatural(_data + 2, (uintptr)source); + } + } + auto data() const -> const char* { return _data; } + auto size() const -> uint { return strlen(_data); } + char _data[256]; +}; + +// + +template inline auto make_string(T value) -> stringify { + return stringify(forward(value)); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/compare.hpp b/roms/snes-test-roms/bass-untech/nall/string/compare.hpp new file mode 100644 index 00000000..6e9c2ccd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/compare.hpp @@ -0,0 +1,58 @@ +#pragma once + +namespace nall { + +template +inline auto string::_compare(const char* target, uint capacity, const char* source, uint size) -> int { + if(Insensitive) return memory::icompare(target, capacity, source, size); + return memory::compare(target, capacity, source, size); +} + +//size() + 1 includes null-terminator; required to properly compare strings of differing lengths +inline auto string::compare(string_view x, string_view y) -> int { + return memory::compare(x.data(), x.size() + 1, y.data(), y.size() + 1); +} + +inline auto string::icompare(string_view x, string_view y) -> int { + return memory::icompare(x.data(), x.size() + 1, y.data(), y.size() + 1); +} + +inline auto string::compare(string_view source) const -> int { + return memory::compare(data(), size() + 1, source.data(), source.size() + 1); +} + +inline auto string::icompare(string_view source) const -> int { + return memory::icompare(data(), size() + 1, source.data(), source.size() + 1); +} + +inline auto string::equals(string_view source) const -> bool { + if(size() != source.size()) return false; + return memory::compare(data(), source.data(), source.size()) == 0; +} + +inline auto string::iequals(string_view source) const -> bool { + if(size() != source.size()) return false; + return memory::icompare(data(), source.data(), source.size()) == 0; +} + +inline auto string::beginsWith(string_view source) const -> bool { + if(source.size() > size()) return false; + return memory::compare(data(), source.data(), source.size()) == 0; +} + +inline auto string::ibeginsWith(string_view source) const -> bool { + if(source.size() > size()) return false; + return memory::icompare(data(), source.data(), source.size()) == 0; +} + +inline auto string::endsWith(string_view source) const -> bool { + if(source.size() > size()) return false; + return memory::compare(data() + size() - source.size(), source.data(), source.size()) == 0; +} + +inline auto string::iendsWith(string_view source) const -> bool { + if(source.size() > size()) return false; + return memory::icompare(data() + size() - source.size(), source.data(), source.size()) == 0; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/convert.hpp b/roms/snes-test-roms/bass-untech/nall/string/convert.hpp new file mode 100644 index 00000000..82de77db --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/convert.hpp @@ -0,0 +1,53 @@ +#pragma once + +namespace nall { + +inline auto string::downcase() -> string& { + char* p = get(); + for(uint n = 0; n < size(); n++) { + if(p[n] >= 'A' && p[n] <= 'Z') p[n] += 0x20; + } + return *this; +} + +inline auto string::qdowncase() -> string& { + char* p = get(); + for(uint n = 0, quoted = 0; n < size(); n++) { + if(p[n] == '\"') quoted ^= 1; + if(!quoted && p[n] >= 'A' && p[n] <= 'Z') p[n] += 0x20; + } + return *this; +} + +inline auto string::upcase() -> string& { + char* p = get(); + for(uint n = 0; n < size(); n++) { + if(p[n] >= 'a' && p[n] <= 'z') p[n] -= 0x20; + } + return *this; +} + +inline auto string::qupcase() -> string& { + char* p = get(); + for(uint n = 0, quoted = 0; n < size(); n++) { + if(p[n] == '\"') quoted ^= 1; + if(!quoted && p[n] >= 'a' && p[n] <= 'z') p[n] -= 0x20; + } + return *this; +} + +inline auto string::transform(string_view from, string_view to) -> string& { + if(from.size() != to.size() || from.size() == 0) return *this; //patterns must be the same length + char* p = get(); + for(uint n = 0; n < size(); n++) { + for(uint s = 0; s < from.size(); s++) { + if(p[n] == from[s]) { + p[n] = to[s]; + break; + } + } + } + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/core.hpp b/roms/snes-test-roms/bass-untech/nall/string/core.hpp new file mode 100644 index 00000000..315b6001 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/core.hpp @@ -0,0 +1,75 @@ +#pragma once + +//only allocators may access _data or modify _size and _capacity +//all other functions must use data(), size(), capacity() + +#if defined(NALL_STRING_ALLOCATOR_ADAPTIVE) + #include +#elif defined(NALL_STRING_ALLOCATOR_COPY_ON_WRITE) + #include +#elif defined(NALL_STRING_ALLOCATOR_SMALL_STRING_OPTIMIZATION) + #include +#elif defined(NALL_STRING_ALLOCATOR_VECTOR) + #include +#endif + +namespace nall { + +inline auto string::operator[](uint position) const -> const char& { + #ifdef DEBUG + struct out_of_bounds {}; + if(position >= size() + 1) throw out_of_bounds{}; + #endif + return data()[position]; +} + +inline auto string::operator()(uint position, char fallback) const -> char { + if(position >= size() + 1) return fallback; + return data()[position]; +} + +template inline auto string::assign(P&&... p) -> string& { + resize(0); + return append(forward

(p)...); +} + +template inline auto string::prepend(const T& value, P&&... p) -> string& { + if constexpr(sizeof...(p)) prepend(forward

(p)...); + return _prepend(make_string(value)); +} + +template inline auto string::prepend(const nall::string_format& value, P&&... p) -> string& { + if constexpr(sizeof...(p)) prepend(forward

(p)...); + return format(value); +} + +template inline auto string::_prepend(const stringify& source) -> string& { + resize(source.size() + size()); + memory::move(get() + source.size(), get(), size() - source.size()); + memory::copy(get(), source.data(), source.size()); + return *this; +} + +template inline auto string::append(const T& value, P&&... p) -> string& { + _append(make_string(value)); + if constexpr(sizeof...(p) > 0) append(forward

(p)...); + return *this; +} + +template inline auto string::append(const nall::string_format& value, P&&... p) -> string& { + format(value); + if constexpr(sizeof...(p)) append(forward

(p)...); + return *this; +} + +template inline auto string::_append(const stringify& source) -> string& { + resize(size() + source.size()); + memory::copy(get() + size() - source.size(), source.data(), source.size()); + return *this; +} + +inline auto string::length() const -> uint { + return strlen(data()); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/eval/evaluator.hpp b/roms/snes-test-roms/bass-untech/nall/string/eval/evaluator.hpp new file mode 100644 index 00000000..cecffd40 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/eval/evaluator.hpp @@ -0,0 +1,146 @@ +#pragma once + +namespace nall::Eval { + +inline auto evaluateExpression(Node* node) -> string { + #define p(n) evaluateExpression(node->link[n]) + switch(node->type) { + case Node::Type::Null: return "Null"; + case Node::Type::Literal: return {"Literal:", node->literal}; + case Node::Type::Function: return {"Function(0:", p(0), ", 1:", p(1), ")"}; + case Node::Type::Subscript: return {"Subscript(0:", p(0), ", 1:", p(1), ")"}; + case Node::Type::Member: return {"Member(0:", p(0), ", 1:", p(1), ")"}; + case Node::Type::SuffixIncrement: return {"SuffixIncrement(0:", p(0), ")"}; + case Node::Type::SuffixDecrement: return {"SuffixDecrement(0:", p(0), ")"}; + case Node::Type::Reference: return {"Reference(0:", p(0), ")"}; + case Node::Type::Dereference: return {"Dereference(0:", p(0), ")"}; + case Node::Type::BitwiseNot: return {"Complement(0:", p(0), ")"}; + case Node::Type::PrefixIncrement: return {"PrefixIncrement(0:", p(0), ")"}; + case Node::Type::PrefixDecrement: return {"PrefixDecrement(0:", p(0), ")"}; + case Node::Type::Add: return {"Add(0:", p(0), ", 1:", p(1), ")"}; + case Node::Type::Multiply: return {"Multiply(0:", p(0), ", 1:", p(1), ")"}; + case Node::Type::Concatenate: return {"Concatenate(0:", p(0), ", ", p(1), ")"}; + case Node::Type::Coalesce: return {"Coalesce(0:", p(0), ", ", p(1), ")"}; + case Node::Type::Condition: return {"Condition(0:", p(0), ", ", p(1), ", ", p(2), ")"}; + case Node::Type::Assign: return {"Assign(0:", p(0), ", ", p(1), ")"}; + case Node::Type::Separator: { + string result = "Separator("; + for(auto& link : node->link) { + result.append(evaluateExpression(link), ", "); + } + return result.trimRight(", ", 1L).append(")"); + } + } + #undef p + + throw "invalid operator"; +} + +inline auto evaluateInteger(Node* node) -> int64_t { + if(node->type == Node::Type::Literal) return toInteger(node->literal); + + #define p(n) evaluateInteger(node->link[n]) + switch(node->type) { + case Node::Type::SuffixIncrement: return p(0); + case Node::Type::SuffixDecrement: return p(0); + case Node::Type::LogicalNot: return !p(0); + case Node::Type::BitwiseNot: return ~p(0); + case Node::Type::Positive: return +p(0); + case Node::Type::Negative: return -p(0); + case Node::Type::PrefixIncrement: return p(0) + 1; + case Node::Type::PrefixDecrement: return p(0) - 1; + case Node::Type::Multiply: return p(0) * p(1); + case Node::Type::Divide: return p(0) / p(1); + case Node::Type::Modulo: return p(0) % p(1); + case Node::Type::Add: return p(0) + p(1); + case Node::Type::Subtract: return p(0) - p(1); + case Node::Type::ShiftLeft: return p(0) << p(1); + case Node::Type::ShiftRight: return p(0) >> p(1); + case Node::Type::BitwiseAnd: return p(0) & p(1); + case Node::Type::BitwiseOr: return p(0) | p(1); + case Node::Type::BitwiseXor: return p(0) ^ p(1); + case Node::Type::Equal: return p(0) == p(1); + case Node::Type::NotEqual: return p(0) != p(1); + case Node::Type::LessThanEqual: return p(0) <= p(1); + case Node::Type::GreaterThanEqual: return p(0) >= p(1); + case Node::Type::LessThan: return p(0) < p(1); + case Node::Type::GreaterThan: return p(0) > p(1); + case Node::Type::LogicalAnd: return p(0) && p(1); + case Node::Type::LogicalOr: return p(0) || p(1); + case Node::Type::Condition: return p(0) ? p(1) : p(2); + case Node::Type::Assign: return p(1); + case Node::Type::AssignMultiply: return p(0) * p(1); + case Node::Type::AssignDivide: return p(0) / p(1); + case Node::Type::AssignModulo: return p(0) % p(1); + case Node::Type::AssignAdd: return p(0) + p(1); + case Node::Type::AssignSubtract: return p(0) - p(1); + case Node::Type::AssignShiftLeft: return p(0) << p(1); + case Node::Type::AssignShiftRight: return p(0) >> p(1); + case Node::Type::AssignBitwiseAnd: return p(0) & p(1); + case Node::Type::AssignBitwiseOr: return p(0) | p(1); + case Node::Type::AssignBitwiseXor: return p(0) ^ p(1); + } + #undef p + + throw "invalid operator"; +} + +inline auto integer(const string& expression) -> maybe { + try { + auto tree = new Node; + const char* p = expression; + parse(tree, p, 0); + auto result = evaluateInteger(tree); + delete tree; + return result; + } catch(const char*) { + return nothing; + } +} + +inline auto evaluateReal(Node* node) -> long double { + if(node->type == Node::Type::Literal) return toReal(node->literal); + + #define p(n) evaluateReal(node->link[n]) + switch(node->type) { + case Node::Type::LogicalNot: return !p(0); + case Node::Type::Positive: return +p(0); + case Node::Type::Negative: return -p(0); + case Node::Type::Multiply: return p(0) * p(1); + case Node::Type::Divide: return p(0) / p(1); + case Node::Type::Add: return p(0) + p(1); + case Node::Type::Subtract: return p(0) - p(1); + case Node::Type::Equal: return p(0) == p(1); + case Node::Type::NotEqual: return p(0) != p(1); + case Node::Type::LessThanEqual: return p(0) <= p(1); + case Node::Type::GreaterThanEqual: return p(0) >= p(1); + case Node::Type::LessThan: return p(0) < p(1); + case Node::Type::GreaterThan: return p(0) > p(1); + case Node::Type::LogicalAnd: return p(0) && p(1); + case Node::Type::LogicalOr: return p(0) || p(1); + case Node::Type::Condition: return p(0) ? p(1) : p(2); + case Node::Type::Assign: return p(1); + case Node::Type::AssignMultiply: return p(0) * p(1); + case Node::Type::AssignDivide: return p(0) / p(1); + case Node::Type::AssignAdd: return p(0) + p(1); + case Node::Type::AssignSubtract: return p(0) - p(1); + } + #undef p + + throw "invalid operator"; +} + +inline auto real(const string& expression) -> maybe { + try { + auto tree = new Node; + const char* p = expression; + parse(tree, p, 0); + auto result = evaluateReal(tree); + delete tree; + return result; + } catch(const char*) { + return nothing; + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/eval/literal.hpp b/roms/snes-test-roms/bass-untech/nall/string/eval/literal.hpp new file mode 100644 index 00000000..7c717704 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/eval/literal.hpp @@ -0,0 +1,102 @@ +#pragma once + +namespace nall::Eval { + +inline auto isLiteral(const char*& s) -> bool { + char n = s[0]; + return (n >= 'A' && n <= 'Z') + || (n >= 'a' && n <= 'z') + || (n >= '0' && n <= '9') + || (n == '%' || n == '$' || n == '_' || n == '.') + || (n == '\'' || n == '\"'); +} + +inline auto literalNumber(const char*& s) -> string { + const char* p = s; + + //binary + if(p[0] == '%' || (p[0] == '0' && p[1] == 'b')) { + uint prefix = 1 + (p[0] == '0'); + p += prefix; + while(p[0] == '\'' || p[0] == '0' || p[0] == '1') p++; + if(p - s <= prefix) throw "invalid binary literal"; + string result = slice(s, 0, p - s); + s = p; + return result; + } + + //octal + if(p[0] == '0' && p[1] == 'o') { + uint prefix = 1 + (p[0] == '0'); + p += prefix; + while(p[0] == '\'' || (p[0] >= '0' && p[0] <= '7')) p++; + if(p - s <= prefix) throw "invalid octal literal"; + string result = slice(s, 0, p - s); + s = p; + return result; + } + + //hex + if(p[0] == '$' || (p[0] == '0' && p[1] == 'x')) { + uint prefix = 1 + (p[0] == '0'); + p += prefix; + while(p[0] == '\'' || (p[0] >= '0' && p[0] <= '9') || (p[0] >= 'A' && p[0] <= 'F') || (p[0] >= 'a' && p[0] <= 'f')) p++; + if(p - s <= prefix) throw "invalid hex literal"; + string result = slice(s, 0, p - s); + s = p; + return result; + } + + //decimal + while(p[0] == '\'' || (p[0] >= '0' && p[0] <= '9')) p++; + if(p[0] != '.') { + string result = slice(s, 0, p - s); + s = p; + return result; + } + + //floating-point + p++; + while(p[0] == '\'' || (p[0] >= '0' && p[0] <= '9')) p++; + string result = slice(s, 0, p - s); + s = p; + return result; +} + +inline auto literalString(const char*& s) -> string { + const char* p = s; + char escape = *p++; + + while(p[0] && p[0] != escape) { + if(p[0] == '\\') p++; + p++; + } + if(*p++ != escape) throw "unclosed string literal"; + + string result = slice(s, 0, p - s); + s = p; + return result; +} + +inline auto literalVariable(const char*& s) -> string { + const char* p = s; + + while(p[0] == '_' || p[0] == '.' || (p[0] >= 'A' && p[0] <= 'Z') || (p[0] >= 'a' && p[0] <= 'z') || (p[0] >= '0' && p[0] <= '9')) p++; + + string result = slice(s, 0, p - s); + s = p; + return result; +} + +inline auto literal(const char*& s) -> string { + const char* p = s; + + if(p[0] >= '0' && p[0] <= '9') return literalNumber(s); + if(p[0] == '%' || p[0] == '$') return literalNumber(s); + if(p[0] == '\'' || p[0] == '\"') return literalString(s); + if(p[0] == '_' || p[0] == '.' || (p[0] >= 'A' && p[0] <= 'Z') || (p[0] >= 'a' && p[0] <= 'z')) return literalVariable(s); + + throw "invalid literal"; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/eval/node.hpp b/roms/snes-test-roms/bass-untech/nall/string/eval/node.hpp new file mode 100644 index 00000000..d02a928e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/eval/node.hpp @@ -0,0 +1,37 @@ +#pragma once + +namespace nall::Eval { + +struct Node { + enum class Type : uint { + Null, + Literal, + Function, Subscript, Member, SuffixIncrement, SuffixDecrement, + Reference, Dereference, LogicalNot, BitwiseNot, Positive, Negative, PrefixIncrement, PrefixDecrement, + Multiply, Divide, Modulo, + Add, Subtract, + RotateLeft, RotateRight, ShiftLeft, ShiftRight, + BitwiseAnd, BitwiseOr, BitwiseXor, + Concatenate, + Equal, NotEqual, LessThanEqual, GreaterThanEqual, LessThan, GreaterThan, + LogicalAnd, LogicalOr, + Coalesce, Condition, + Assign, Create, //all assignment operators have the same precedence + AssignMultiply, AssignDivide, AssignModulo, + AssignAdd, AssignSubtract, + AssignRotateLeft, AssignRotateRight, AssignShiftLeft, AssignShiftRight, + AssignBitwiseAnd, AssignBitwiseOr, AssignBitwiseXor, + AssignConcatenate, + Separator, + }; + + Type type; + string literal; + vector link; + + Node() : type(Type::Null) {} + Node(Type type) : type(type) {} + ~Node() { for(auto& node : link) delete node; } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/eval/parser.hpp b/roms/snes-test-roms/bass-untech/nall/string/eval/parser.hpp new file mode 100644 index 00000000..c01af0a5 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/eval/parser.hpp @@ -0,0 +1,195 @@ +#pragma once + +namespace nall::Eval { + +inline auto whitespace(char n) -> bool { + return n == ' ' || n == '\t' || n == '\r' || n == '\n'; +} + +//operator associativity and precedence: +// right: a[] a() a.b a++ a-- +// left: &a *a !a ~a +a -a ++a --a +// left: a*b a/b a%b +// left: a+b a-b +// left: a<<>>b a<>b +// left: a&b +// left: a^b +// left: a|b +// left: a~b +// left: a<=b a>=b ab +// left: a==b a!=b +// left: a&&b +// left: a||b +// right: a??b a?b:c +// right: a=b a:=b a*=b a/=b a%=b a+=b a-=b a<<<=b a>>>=b a<<=b a>>=b a&=b a^=b a|=b a~=b +// left: a,b +//differences from C++17: +// a&b, a^b, a|b precedence was elevated above comparison operators +// a?b:c precedence was elevated above assignment operators +// a<<>>b a<<<=b a>>>=b rotation operators were added +// a~b a~=b concatenation operators were added +// a??b coalesce operator was added +inline auto parse(Node*& node, const char*& s, uint depth) -> void { + auto unaryPrefix = [&](Node::Type type, uint seek, uint depth) { + auto parent = new Node(type); + parse(parent->link(0) = new Node, s += seek, depth); + node = parent; + }; + + auto unarySuffix = [&](Node::Type type, uint seek, uint depth) { + auto parent = new Node(type); + parent->link(0) = node; + parse(parent, s += seek, depth); + node = parent; + }; + + auto binary = [&](Node::Type type, uint seek, uint depth) { + auto parent = new Node(type); + parent->link(0) = node; + parse(parent->link(1) = new Node, s += seek, depth); + node = parent; + }; + + auto ternary = [&](Node::Type type, uint seek, uint depth) { + auto parent = new Node(type); + parent->link(0) = node; + parse(parent->link(1) = new Node, s += seek, depth); + if(s[0] != ':') throw "mismatched ternary"; + parse(parent->link(2) = new Node, s += seek, depth); + node = parent; + }; + + auto separator = [&](Node::Type type, uint seek, uint depth) { + if(node->type != Node::Type::Separator) return binary(type, seek, depth); + uint n = node->link.size(); + parse(node->link(n) = new Node, s += seek, depth); + }; + + while(whitespace(s[0])) s++; + if(!s[0]) return; + + if(s[0] == '(' && !node->link) { + parse(node, s += 1, 1); + if(*s++ != ')') throw "mismatched group"; + } + + if(isLiteral(s)) { + node->type = Node::Type::Literal; + node->literal = literal(s); + } + + #define p() (!node->literal && !node->link) + while(true) { + while(whitespace(s[0])) s++; + if(!s[0]) return; + + if(depth >= 17) break; //left associativity + if(s[0] == '(' && !p()) { + binary(Node::Type::Function, 1, 1); + if(*s++ != ')') throw "mismatched function"; + continue; + } + if(s[0] == '[') { + binary(Node::Type::Subscript, 1, 1); + if(*s++ != ']') throw "mismatched subscript"; + continue; + } + if(s[0] == '.') { binary(Node::Type::Member, 1, 17); continue; } + if(s[0] == '+' && s[1] == '+' && !p()) { unarySuffix(Node::Type::SuffixIncrement, 2, 17); continue; } + if(s[0] == '-' && s[1] == '-' && !p()) { unarySuffix(Node::Type::SuffixDecrement, 2, 17); continue; } + + if(s[0] == '&' && p()) { unaryPrefix(Node::Type::Reference, 1, 16); continue; } + if(s[0] == '*' && p()) { unaryPrefix(Node::Type::Dereference, 1, 16); continue; } + if(s[0] == '!' && p()) { unaryPrefix(Node::Type::LogicalNot, 1, 16); continue; } + if(s[0] == '~' && p()) { unaryPrefix(Node::Type::BitwiseNot, 1, 16); continue; } + if(s[0] == '+' && s[1] != '+' && p()) { unaryPrefix(Node::Type::Positive, 1, 16); continue; } + if(s[0] == '-' && s[1] != '-' && p()) { unaryPrefix(Node::Type::Negative, 1, 16); continue; } + if(s[0] == '+' && s[1] == '+' && p()) { unaryPrefix(Node::Type::PrefixIncrement, 2, 16); continue; } + if(s[0] == '-' && s[1] == '-' && p()) { unaryPrefix(Node::Type::PrefixDecrement, 2, 16); continue; } + if(depth >= 16) break; //right associativity + + if(depth >= 15) break; //left associativity + if(s[0] == '*' && s[1] != '=') { binary(Node::Type::Multiply, 1, 15); continue; } + if(s[0] == '/' && s[1] != '=') { binary(Node::Type::Divide, 1, 15); continue; } + if(s[0] == '%' && s[1] != '=') { binary(Node::Type::Modulo, 1, 15); continue; } + + if(depth >= 14) break; //left associativity + if(s[0] == '+' && s[1] != '=') { binary(Node::Type::Add, 1, 14); continue; } + if(s[0] == '-' && s[1] != '=') { binary(Node::Type::Subtract, 1, 14); continue; } + + if(depth >= 13) break; //left associativity + if(s[0] == '<' && s[1] == '<' && s[2] == '<' && s[3] != '=') { binary(Node::Type::RotateLeft, 3, 13); continue; } + if(s[0] == '>' && s[1] == '>' && s[2] == '>' && s[3] != '=') { binary(Node::Type::RotateRight, 3, 13); continue; } + if(s[0] == '<' && s[1] == '<' && s[2] != '=') { binary(Node::Type::ShiftLeft, 2, 13); continue; } + if(s[0] == '>' && s[1] == '>' && s[2] != '=') { binary(Node::Type::ShiftRight, 2, 13); continue; } + + if(depth >= 12) break; //left associativity + if(s[0] == '&' && s[1] != '&' && s[1] != '=') { binary(Node::Type::BitwiseAnd, 1, 12); continue; } + + if(depth >= 11) break; //left associativity + if(s[0] == '^' && s[1] != '^' && s[1] != '=') { binary(Node::Type::BitwiseXor, 1, 11); continue; } + + if(depth >= 10) break; //left associativity + if(s[0] == '|' && s[1] != '|' && s[1] != '=') { binary(Node::Type::BitwiseOr, 1, 10); continue; } + + if(depth >= 9) break; //left associativity + if(s[0] == '~' && s[1] != '=') { binary(Node::Type::Concatenate, 1, 9); continue; } + + if(depth >= 8) break; //left associativity + if(s[0] == '<' && s[1] == '=') { binary(Node::Type::LessThanEqual, 2, 8); continue; } + if(s[0] == '>' && s[1] == '=') { binary(Node::Type::GreaterThanEqual, 2, 8); continue; } + if(s[0] == '<') { binary(Node::Type::LessThan, 1, 8); continue; } + if(s[0] == '>') { binary(Node::Type::GreaterThan, 1, 8); continue; } + + if(depth >= 7) break; //left associativity + if(s[0] == '=' && s[1] == '=') { binary(Node::Type::Equal, 2, 7); continue; } + if(s[0] == '!' && s[1] == '=') { binary(Node::Type::NotEqual, 2, 7); continue; } + + if(depth >= 6) break; //left associativity + if(s[0] == '&' && s[1] == '&') { binary(Node::Type::LogicalAnd, 2, 6); continue; } + + if(depth >= 5) break; //left associativity + if(s[0] == '|' && s[1] == '|') { binary(Node::Type::LogicalOr, 2, 5); continue; } + + if(s[0] == '?' && s[1] == '?') { binary(Node::Type::Coalesce, 2, 4); continue; } + if(s[0] == '?' && s[1] != '?') { ternary(Node::Type::Condition, 1, 4); continue; } + if(depth >= 4) break; //right associativity + + if(s[0] == '=') { binary(Node::Type::Assign, 1, 3); continue; } + if(s[0] == ':' && s[1] == '=') { binary(Node::Type::Create, 2, 3); continue; } + if(s[0] == '*' && s[1] == '=') { binary(Node::Type::AssignMultiply, 2, 3); continue; } + if(s[0] == '/' && s[1] == '=') { binary(Node::Type::AssignDivide, 2, 3); continue; } + if(s[0] == '%' && s[1] == '=') { binary(Node::Type::AssignModulo, 2, 3); continue; } + if(s[0] == '+' && s[1] == '=') { binary(Node::Type::AssignAdd, 2, 3); continue; } + if(s[0] == '-' && s[1] == '=') { binary(Node::Type::AssignSubtract, 2, 3); continue; } + if(s[0] == '<' && s[1] == '<' && s[2] == '<' && s[3] == '=') { binary(Node::Type::AssignRotateLeft, 4, 3); continue; } + if(s[0] == '>' && s[1] == '>' && s[2] == '>' && s[3] == '=') { binary(Node::Type::AssignRotateRight, 4, 3); continue; } + if(s[0] == '<' && s[1] == '<' && s[2] == '=') { binary(Node::Type::AssignShiftLeft, 3, 3); continue; } + if(s[0] == '>' && s[1] == '>' && s[2] == '=') { binary(Node::Type::AssignShiftRight, 3, 3); continue; } + if(s[0] == '&' && s[1] == '=') { binary(Node::Type::AssignBitwiseAnd, 2, 3); continue; } + if(s[0] == '^' && s[1] == '=') { binary(Node::Type::AssignBitwiseXor, 2, 3); continue; } + if(s[0] == '|' && s[1] == '=') { binary(Node::Type::AssignBitwiseOr, 2, 3); continue; } + if(s[0] == '~' && s[1] == '=') { binary(Node::Type::AssignConcatenate, 2, 3); continue; } + if(depth >= 3) break; //right associativity + + if(depth >= 2) break; //left associativity + if(s[0] == ',') { separator(Node::Type::Separator, 1, 2); continue; } + + if(depth >= 1 && (s[0] == ')' || s[0] == ']')) break; + + while(whitespace(s[0])) s++; + if(!s[0]) break; + + throw "unrecognized terminal"; + } + #undef p +} + +inline auto parse(const string& expression) -> Node* { + auto result = new Node; + const char* p = expression; + parse(result, p, 0); + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/find.hpp b/roms/snes-test-roms/bass-untech/nall/string/find.hpp new file mode 100644 index 00000000..ee6dbb55 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/find.hpp @@ -0,0 +1,65 @@ +#pragma once + +namespace nall { + +inline auto string::contains(string_view characters) const -> maybe { + for(uint x : range(size())) { + for(char y : characters) { + if(operator[](x) == y) return x; + } + } + return nothing; +} + +template inline auto string::_find(int offset, string_view source) const -> maybe { + if(source.size() == 0) return nothing; + auto p = data(); + for(uint n = offset, quoted = 0; n < size();) { + if(Quoted) { if(p[n] == '\"') { quoted ^= 1; n++; continue; } if(quoted) { n++; continue; } } + if(_compare(p + n, size() - n, source.data(), source.size())) { n++; continue; } + return n - offset; + } + return nothing; +} + +inline auto string::find(string_view source) const -> maybe { return _find<0, 0>(0, source); } +inline auto string::ifind(string_view source) const -> maybe { return _find<1, 0>(0, source); } +inline auto string::qfind(string_view source) const -> maybe { return _find<0, 1>(0, source); } +inline auto string::iqfind(string_view source) const -> maybe { return _find<1, 1>(0, source); } + +inline auto string::findFrom(int offset, string_view source) const -> maybe { return _find<0, 0>(offset, source); } +inline auto string::ifindFrom(int offset, string_view source) const -> maybe { return _find<1, 0>(offset, source); } + +inline auto string::findNext(int offset, string_view source) const -> maybe { + if(source.size() == 0) return nothing; + for(int n = offset + 1; n < size(); n++) { + if(memory::compare(data() + n, size() - n, source.data(), source.size()) == 0) return n; + } + return nothing; +} + +inline auto string::ifindNext(int offset, string_view source) const -> maybe { + if(source.size() == 0) return nothing; + for(int n = offset + 1; n < size(); n++) { + if(memory::icompare(data() + n, size() - n, source.data(), source.size()) == 0) return n; + } + return nothing; +} + +inline auto string::findPrevious(int offset, string_view source) const -> maybe { + if(source.size() == 0) return nothing; + for(int n = offset - 1; n >= 0; n--) { + if(memory::compare(data() + n, size() - n, source.data(), source.size()) == 0) return n; + } + return nothing; +} + +inline auto string::ifindPrevious(int offset, string_view source) const -> maybe { + if(source.size() == 0) return nothing; + for(int n = offset - 1; n >= 0; n--) { + if(memory::icompare(data() + n, size() - n, source.data(), source.size()) == 0) return n; + } + return nothing; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/format.hpp b/roms/snes-test-roms/bass-untech/nall/string/format.hpp new file mode 100644 index 00000000..c5bbc561 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/format.hpp @@ -0,0 +1,138 @@ +#pragma once + +namespace nall { + +//nall::format is a vector of parameters that can be applied to a string +//each {#} token will be replaced with its appropriate format parameter + +inline auto string::format(const nall::string_format& params) -> type& { + auto size = (int)this->size(); + auto data = memory::allocate(size); + memory::copy(data, this->data(), size); + + int x = 0; + while(x < size - 2) { //2 = minimum tag length + if(data[x] != '{') { x++; continue; } + + int y = x + 1; + while(y < size - 1) { //-1 avoids going out of bounds on test after this loop + if(data[y] != '}') { y++; continue; } + break; + } + + if(data[y++] != '}') { x++; continue; } + + static auto isNumeric = [](char* s, char* e) -> bool { + if(s == e) return false; //ignore empty tags: {} + while(s < e) { + if(*s >= '0' && *s <= '9') { s++; continue; } + return false; + } + return true; + }; + if(!isNumeric(&data[x + 1], &data[y - 1])) { x++; continue; } + + uint index = toNatural(&data[x + 1]); + if(index >= params.size()) { x++; continue; } + + uint sourceSize = y - x; + uint targetSize = params[index].size(); + uint remaining = size - x; + + if(sourceSize > targetSize) { + uint difference = sourceSize - targetSize; + memory::move(&data[x], &data[x + difference], remaining - difference); + size -= difference; + } else if(targetSize > sourceSize) { + uint difference = targetSize - sourceSize; + data = (char*)realloc(data, size + difference); + size += difference; + memory::move(&data[x + difference], &data[x], remaining); + } + memory::copy(&data[x], params[index].data(), targetSize); + x += targetSize; + } + + resize(size); + memory::copy(get(), data, size); + memory::free(data); + return *this; +} + +template inline auto string_format::append(const T& value, P&&... p) -> string_format& { + vector::append(value); + return append(forward

(p)...); +} + +inline auto string_format::append() -> string_format& { + return *this; +} + +template inline auto print(P&&... p) -> void { + string s{forward

(p)...}; + fwrite(s.data(), 1, s.size(), stdout); + fflush(stdout); +} + +template inline auto print(FILE* fp, P&&... p) -> void { + string s{forward

(p)...}; + fwrite(s.data(), 1, s.size(), fp); + if(fp == stdout || fp == stderr) fflush(fp); +} + +template inline auto pad(const T& value, long precision, char padchar) -> string { + string buffer{value}; + if(precision) buffer.size(precision, padchar); + return buffer; +} + +inline auto hex(uintmax value, long precision, char padchar) -> string { + string buffer; + buffer.resize(sizeof(uintmax) * 2); + char* p = buffer.get(); + + uint size = 0; + do { + uint n = value & 15; + p[size++] = n < 10 ? '0' + n : 'a' + n - 10; + value >>= 4; + } while(value); + buffer.resize(size); + buffer.reverse(); + if(precision) buffer.size(precision, padchar); + return buffer; +} + +inline auto octal(uintmax value, long precision, char padchar) -> string { + string buffer; + buffer.resize(sizeof(uintmax) * 3); + char* p = buffer.get(); + + uint size = 0; + do { + p[size++] = '0' + (value & 7); + value >>= 3; + } while(value); + buffer.resize(size); + buffer.reverse(); + if(precision) buffer.size(precision, padchar); + return buffer; +} + +inline auto binary(uintmax value, long precision, char padchar) -> string { + string buffer; + buffer.resize(sizeof(uintmax) * 8); + char* p = buffer.get(); + + uint size = 0; + do { + p[size++] = '0' + (value & 1); + value >>= 1; + } while(value); + buffer.resize(size); + buffer.reverse(); + if(precision) buffer.size(precision, padchar); + return buffer; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/markup/bml.hpp b/roms/snes-test-roms/bass-untech/nall/string/markup/bml.hpp new file mode 100644 index 00000000..3bf05ddf --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/markup/bml.hpp @@ -0,0 +1,189 @@ +#pragma once + +//BML v1.0 parser +//revision 0.04 + +namespace nall::BML { + +//metadata is used to store nesting level + +struct ManagedNode; +using SharedNode = shared_pointer; + +struct ManagedNode : Markup::ManagedNode { +protected: + //test to verify if a valid character for a node name + auto valid(char p) const -> bool { //A-Z, a-z, 0-9, -. + return p - 'A' < 26u || p - 'a' < 26u || p - '0' < 10u || p - '-' < 2u; + } + + //determine indentation level, without incrementing pointer + auto readDepth(const char* p) -> uint { + uint depth = 0; + while(p[depth] == '\t' || p[depth] == ' ') depth++; + return depth; + } + + //determine indentation level + auto parseDepth(const char*& p) -> uint { + uint depth = readDepth(p); + p += depth; + return depth; + } + + //read name + auto parseName(const char*& p) -> void { + uint length = 0; + while(valid(p[length])) length++; + if(length == 0) throw "Invalid node name"; + _name = slice(p, 0, length); + p += length; + } + + auto parseData(const char*& p, string_view spacing) -> void { + if(*p == '=' && *(p + 1) == '\"') { + uint length = 2; + while(p[length] && p[length] != '\n' && p[length] != '\"') length++; + if(p[length] != '\"') throw "Unescaped value"; + _value = {slice(p, 2, length - 2), "\n"}; + p += length + 1; + } else if(*p == '=') { + uint length = 1; + while(p[length] && p[length] != '\n' && p[length] != '\"' && p[length] != ' ') length++; + if(p[length] == '\"') throw "Illegal character in value"; + _value = {slice(p, 1, length - 1), "\n"}; + p += length; + } else if(*p == ':') { + uint length = 1; + while(p[length] && p[length] != '\n') length++; + _value = {slice(p, 1, length - 1).trimLeft(spacing, 1L), "\n"}; + p += length; + } + } + + //read all attributes for a node + auto parseAttributes(const char*& p, string_view spacing) -> void { + while(*p && *p != '\n') { + if(*p != ' ') throw "Invalid node name"; + while(*p == ' ') p++; //skip excess spaces + if(*(p + 0) == '/' && *(p + 1) == '/') break; //skip comments + + SharedNode node(new ManagedNode); + uint length = 0; + while(valid(p[length])) length++; + if(length == 0) throw "Invalid attribute name"; + node->_name = slice(p, 0, length); + node->parseData(p += length, spacing); + node->_value.trimRight("\n", 1L); + _children.append(node); + } + } + + //read a node and all of its child nodes + auto parseNode(const vector& text, uint& y, string_view spacing) -> void { + const char* p = text[y++]; + _metadata = parseDepth(p); + parseName(p); + parseData(p, spacing); + parseAttributes(p, spacing); + + while(y < text.size()) { + uint depth = readDepth(text[y]); + if(depth <= _metadata) break; + + if(text[y][depth] == ':') { + _value.append(slice(text[y++], depth + 1).trimLeft(spacing, 1L), "\n"); + continue; + } + + SharedNode node(new ManagedNode); + node->parseNode(text, y, spacing); + _children.append(node); + } + + _value.trimRight("\n", 1L); + } + + //read top-level nodes + auto parse(string document, string_view spacing) -> void { + //in order to simplify the parsing logic; we do an initial pass to normalize the data + //the below code will turn '\r\n' into '\n'; skip empty lines; and skip comment lines + char* p = document.get(), *output = p; + while(*p) { + char* origin = p; + bool empty = true; + while(*p) { + //scan for first non-whitespace character. if it's a line feed or comment; skip the line + if(p[0] == ' ' || p[0] == '\t') { p++; continue; } + empty = p[0] == '\r' || p[0] == '\n' || (p[0] == '/' && p[1] == '/'); + break; + } + while(*p) { + if(p[0] == '\r') p[0] = '\n'; //turns '\r\n' into '\n\n' (second '\n' will be skipped) + if(*p++ == '\n') break; //include '\n' in the output to be copied + } + if(empty) continue; + + memory::move(output, origin, p - origin); + output += p - origin; + } + document.resize(document.size() - (p - output)).trimRight("\n"); + if(document.size() == 0) return; //empty document + + auto text = document.split("\n"); + uint y = 0; + while(y < text.size()) { + SharedNode node(new ManagedNode); + node->parseNode(text, y, spacing); + if(node->_metadata > 0) throw "Root nodes cannot be indented"; + _children.append(node); + } + } + + friend auto unserialize(const string&, string_view) -> Markup::Node; +}; + +inline auto unserialize(const string& markup, string_view spacing = {}) -> Markup::Node { + SharedNode node(new ManagedNode); + try { + node->parse(markup, spacing); + } catch(const char* error) { + node.reset(); + } + return (Markup::SharedNode&)node; +} + +inline auto serialize(const Markup::Node& node, string_view spacing = {}, uint depth = 0) -> string { + if(!node.name()) { + string result; + for(auto leaf : node) { + result.append(serialize(leaf, spacing, depth)); + } + return result; + } + + string padding; + padding.resize(depth * 2); + padding.fill(' '); + + vector lines; + if(auto value = node.value()) lines = value.split("\n"); + + string result; + result.append(padding); + result.append(node.name()); + if(lines.size() == 1) result.append(":", spacing, lines[0]); + result.append("\n"); + if(lines.size() > 1) { + padding.append(" "); + for(auto& line : lines) { + result.append(padding, ":", spacing, line, "\n"); + } + } + for(auto leaf : node) { + result.append(serialize(leaf, spacing, depth + 1)); + } + return result; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/markup/find.hpp b/roms/snes-test-roms/bass-untech/nall/string/markup/find.hpp new file mode 100644 index 00000000..5ba5dab1 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/markup/find.hpp @@ -0,0 +1,137 @@ +#pragma once + +namespace nall::Markup { + +inline auto ManagedNode::_evaluate(string query) const -> bool { + if(!query) return true; + + for(auto& rule : query.split(",")) { + enum class Comparator : uint { ID, EQ, NE, LT, LE, GT, GE }; + auto comparator = Comparator::ID; + if(rule.match("*!=*")) comparator = Comparator::NE; + else if(rule.match("*<=*")) comparator = Comparator::LE; + else if(rule.match("*>=*")) comparator = Comparator::GE; + else if(rule.match ("*=*")) comparator = Comparator::EQ; + else if(rule.match ("*<*")) comparator = Comparator::LT; + else if(rule.match ("*>*")) comparator = Comparator::GT; + + if(comparator == Comparator::ID) { + if(_find(rule).size()) continue; + return false; + } + + vector side; + switch(comparator) { + case Comparator::EQ: side = rule.split ("=", 1L); break; + case Comparator::NE: side = rule.split("!=", 1L); break; + case Comparator::LT: side = rule.split ("<", 1L); break; + case Comparator::LE: side = rule.split("<=", 1L); break; + case Comparator::GT: side = rule.split (">", 1L); break; + case Comparator::GE: side = rule.split(">=", 1L); break; + } + + string data = string{_value}.strip(); + if(side(0)) { + auto result = _find(side(0)); + if(result.size() == 0) return false; + data = result[0].text(); //strips whitespace so rules can match without requiring it + } + + switch(comparator) { + case Comparator::EQ: if(data.match(side(1)) == true) continue; break; + case Comparator::NE: if(data.match(side(1)) == false) continue; break; + case Comparator::LT: if(data.natural() < side(1).natural()) continue; break; + case Comparator::LE: if(data.natural() <= side(1).natural()) continue; break; + case Comparator::GT: if(data.natural() > side(1).natural()) continue; break; + case Comparator::GE: if(data.natural() >= side(1).natural()) continue; break; + } + + return false; + } + + return true; +} + +inline auto ManagedNode::_find(const string& query) const -> vector { + vector result; + + auto path = query.split("/"); + string name = path.take(0), rule; + uint lo = 0u, hi = ~0u; + + if(name.match("*[*]")) { + auto p = name.trimRight("]", 1L).split("[", 1L); + name = p(0); + if(p(1).find("-")) { + p = p(1).split("-", 1L); + lo = !p(0) ? 0u : p(0).natural(); + hi = !p(1) ? ~0u : p(1).natural(); + } else { + lo = hi = p(1).natural(); + } + } + + if(name.match("*(*)")) { + auto p = name.trimRight(")", 1L).split("(", 1L); + name = p(0); + rule = p(1); + } + + uint position = 0; + for(auto& node : _children) { + if(!node->_name.match(name)) continue; + if(!node->_evaluate(rule)) continue; + + bool inrange = position >= lo && position <= hi; + position++; + if(!inrange) continue; + + if(path.size() == 0) { + result.append(node); + } else for(auto& item : node->_find(path.merge("/"))) { + result.append(item); + } + } + + return result; +} + +//operator[](string) +inline auto ManagedNode::_lookup(const string& path) const -> Node { + auto result = _find(path); + return result ? result[0] : Node{}; + +/*//faster, but cannot search + if(auto position = path.find("/")) { + auto name = slice(path, 0, *position); + for(auto& node : _children) { + if(name == node->_name) { + return node->_lookup(slice(path, *position + 1)); + } + } + } else for(auto& node : _children) { + if(path == node->_name) return node; + } + return {}; +*/ +} + +inline auto ManagedNode::_create(const string& path) -> Node { + if(auto position = path.find("/")) { + auto name = slice(path, 0, *position); + for(auto& node : _children) { + if(name == node->_name) { + return node->_create(slice(path, *position + 1)); + } + } + _children.append(new ManagedNode(name)); + return _children.right()->_create(slice(path, *position + 1)); + } + for(auto& node : _children) { + if(path == node->_name) return node; + } + _children.append(new ManagedNode(path)); + return _children.right(); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/markup/node.hpp b/roms/snes-test-roms/bass-untech/nall/string/markup/node.hpp new file mode 100644 index 00000000..fb25d977 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/markup/node.hpp @@ -0,0 +1,147 @@ +#pragma once + +namespace nall::Markup { + +struct Node; +struct ManagedNode; +using SharedNode = shared_pointer; + +struct ManagedNode { + ManagedNode() = default; + ManagedNode(const string& name) : _name(name) {} + ManagedNode(const string& name, const string& value) : _name(name), _value(value) {} + + auto clone() const -> SharedNode { + SharedNode clone{new ManagedNode(_name, _value)}; + for(auto& child : _children) { + clone->_children.append(child->clone()); + } + return clone; + } + + auto copy(SharedNode source) -> void { + _name = source->_name; + _value = source->_value; + _metadata = source->_metadata; + _children.reset(); + for(auto child : source->_children) { + _children.append(child->clone()); + } + } + +protected: + string _name; + string _value; + uintptr _metadata = 0; + vector _children; + + auto _evaluate(string query) const -> bool; + auto _find(const string& query) const -> vector; + auto _lookup(const string& path) const -> Node; + auto _create(const string& path) -> Node; + + friend class Node; +}; + +struct Node { + Node() : shared(new ManagedNode) {} + Node(const SharedNode& source) : shared(source ? source : new ManagedNode) {} + Node(const nall::string& name) : shared(new ManagedNode(name)) {} + Node(const nall::string& name, const nall::string& value) : shared(new ManagedNode(name, value)) {} + + auto unique() const -> bool { return shared.unique(); } + auto clone() const -> Node { return shared->clone(); } + auto copy(Node source) -> void { return shared->copy(source.shared); } + + explicit operator bool() const { return shared->_name || shared->_children; } + auto name() const -> nall::string { return shared->_name; } + auto value() const -> nall::string { return shared->_value; } + + auto value(nall::string& target) const -> bool { if(shared) target = string(); return (bool)shared; } + auto value(bool& target) const -> bool { if(shared) target = boolean(); return (bool)shared; } + auto value(int& target) const -> bool { if(shared) target = integer(); return (bool)shared; } + auto value(uint& target) const -> bool { if(shared) target = natural(); return (bool)shared; } + auto value(double& target) const -> bool { if(shared) target = real(); return (bool)shared; } + + auto text() const -> nall::string { return value().strip(); } + auto string() const -> nall::string { return value().strip(); } + auto boolean() const -> bool { return text() == "true"; } + auto integer() const -> int64_t { return text().integer(); } + auto natural() const -> uint64_t { return text().natural(); } + auto real() const -> double { return text().real(); } + + auto text(const nall::string& fallback) const -> nall::string { return bool(*this) ? text() : fallback; } + auto string(const nall::string& fallback) const -> nall::string { return bool(*this) ? string() : fallback; } + auto boolean(bool fallback) const -> bool { return bool(*this) ? boolean() : fallback; } + auto integer(int64_t fallback) const -> int64_t { return bool(*this) ? integer() : fallback; } + auto natural(uint64_t fallback) const -> uint64_t { return bool(*this) ? natural() : fallback; } + auto real(double fallback) const -> double { return bool(*this) ? real() : fallback; } + + auto setName(const nall::string& name = "") -> Node& { shared->_name = name; return *this; } + auto setValue(const nall::string& value = "") -> Node& { shared->_value = value; return *this; } + + auto reset() -> void { shared->_children.reset(); } + auto size() const -> uint { return shared->_children.size(); } + + auto prepend(const Node& node) -> void { shared->_children.prepend(node.shared); } + auto append(const Node& node) -> void { shared->_children.append(node.shared); } + auto remove(const Node& node) -> bool { + for(auto n : range(size())) { + if(node.shared == shared->_children[n]) { + return shared->_children.remove(n), true; + } + } + return false; + } + + auto insert(uint position, const Node& node) -> bool { + if(position > size()) return false; //used > instead of >= to allow indexed-equivalent of append() + return shared->_children.insert(position, node.shared), true; + } + + auto remove(uint position) -> bool { + if(position >= size()) return false; + return shared->_children.remove(position), true; + } + + auto swap(uint x, uint y) -> bool { + if(x >= size() || y >= size()) return false; + return std::swap(shared->_children[x], shared->_children[y]), true; + } + + auto sort(function comparator = [](auto x, auto y) { + return nall::string::compare(x.shared->_name, y.shared->_name) < 0; + }) -> void { + nall::sort(shared->_children.data(), shared->_children.size(), [&](auto x, auto y) { + return comparator(x, y); //this call converts SharedNode objects to Node objects + }); + } + + auto operator[](int position) -> Node { + if(position >= size()) return {}; + return shared->_children[position]; + } + + auto operator[](const nall::string& path) const -> Node { return shared->_lookup(path); } + auto operator()(const nall::string& path) -> Node { return shared->_create(path); } + auto find(const nall::string& query) const -> vector { return shared->_find(query); } + + struct iterator { + auto operator*() -> Node { return {source.shared->_children[position]}; } + auto operator!=(const iterator& source) const -> bool { return position != source.position; } + auto operator++() -> iterator& { return position++, *this; } + iterator(const Node& source, uint position) : source(source), position(position) {} + + private: + const Node& source; + uint position; + }; + + auto begin() const -> iterator { return iterator(*this, 0); } + auto end() const -> iterator { return iterator(*this, size()); } + +protected: + SharedNode shared; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/markup/xml.hpp b/roms/snes-test-roms/bass-untech/nall/string/markup/xml.hpp new file mode 100644 index 00000000..b7557b52 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/markup/xml.hpp @@ -0,0 +1,217 @@ +#pragma once + +//XML v1.0 subset parser +//revision 0.04 + +namespace nall::XML { + +//metadata: +// 0 = element +// 1 = attribute + +struct ManagedNode; +using SharedNode = shared_pointer; + +struct ManagedNode : Markup::ManagedNode { +protected: + auto escape() const -> string { + string result = _value; + result.replace("&", "&"); + result.replace("<", "<"); + result.replace(">", ">"); + if(_metadata == 1) { + result.replace("\'", "'"); + result.replace("\"", """); + } + return result; + } + + auto isName(char c) const -> bool { + if(c >= 'A' && c <= 'Z') return true; + if(c >= 'a' && c <= 'z') return true; + if(c >= '0' && c <= '9') return true; + if(c == '.' || c == '_') return true; + if(c == '?') return true; + return false; + } + + auto isWhitespace(char c) const -> bool { + if(c == ' ' || c == '\t') return true; + if(c == '\r' || c == '\n') return true; + return false; + } + + //copy part of string from source document into target string; decode markup while copying + auto copy(string& target, const char* source, uint length) -> void { + target.reserve(length + 1); + + #if defined(NALL_XML_LITERAL) + memory::copy(target.pointer(), source, length); + target[length] = 0; + return; + #endif + + char* output = target.get(); + while(length) { + if(*source == '&') { + if(!memory::compare(source, "<", 4)) { *output++ = '<'; source += 4; length -= 4; continue; } + if(!memory::compare(source, ">", 4)) { *output++ = '>'; source += 4; length -= 4; continue; } + if(!memory::compare(source, "&", 5)) { *output++ = '&'; source += 5; length -= 5; continue; } + if(!memory::compare(source, "'", 6)) { *output++ = '\''; source += 6; length -= 6; continue; } + if(!memory::compare(source, """, 6)) { *output++ = '\"'; source += 6; length -= 6; continue; } + } + + if(_metadata == 0 && source[0] == '<' && source[1] == '!') { + //comment + if(!memory::compare(source, "", 3)) source++, length--; + source += 3, length -= 3; + continue; + } + + //CDATA + if(!memory::compare(source, "", 3)) *output++ = *source++, length--; + source += 3, length -= 3; + continue; + } + } + + *output++ = *source++, length--; + } + *output = 0; + } + + auto parseExpression(const char*& p) -> bool { + if(*(p + 1) != '!') return false; + + //comment + if(!memory::compare(p, "", 3)) p++; + if(!*p) throw "unclosed comment"; + p += 3; + return true; + } + + //CDATA + if(!memory::compare(p, "", 3)) p++; + if(!*p) throw "unclosed CDATA"; + p += 3; + return true; + } + + //DOCTYPE + if(!memory::compare(p, "') counter--; + } while(counter); + return true; + } + + return false; + } + + //returns true if tag closes itself (); false if not () + auto parseHead(const char*& p) -> bool { + //parse name + const char* nameStart = ++p; //skip '<' + while(isName(*p)) p++; + const char* nameEnd = p; + copy(_name, nameStart, nameEnd - nameStart); + if(!_name) throw "missing element name"; + + //parse attributes + while(*p) { + while(isWhitespace(*p)) p++; + if(!*p) throw "unclosed attribute"; + if(*p == '?' || *p == '/' || *p == '>') break; + + //parse attribute name + SharedNode attribute(new ManagedNode); + attribute->_metadata = 1; + + const char* nameStart = p; + while(isName(*p)) p++; + const char* nameEnd = p; + copy(attribute->_name, nameStart, nameEnd - nameStart); + if(!attribute->_name) throw "missing attribute name"; + + //parse attribute data + if(*p++ != '=') throw "missing attribute value"; + char terminal = *p++; + if(terminal != '\'' && terminal != '\"') throw "attribute value not quoted"; + const char* dataStart = p; + while(*p && *p != terminal) p++; + if(!*p) throw "missing attribute data terminal"; + const char* dataEnd = p++; //skip closing terminal + + copy(attribute->_value, dataStart, dataEnd - dataStart); + _children.append(attribute); + } + + //parse closure + if(*p == '?' && *(p + 1) == '>') { p += 2; return true; } + if(*p == '/' && *(p + 1) == '>') { p += 2; return true; } + if(*p == '>') { p += 1; return false; } + throw "invalid element tag"; + } + + //parse element and all of its child elements + auto parseElement(const char*& p) -> void { + SharedNode node(new ManagedNode); + if(node->parseHead(p) == false) node->parse(p); + _children.append(node); + } + + //return true if matches this node's name + auto parseClosureElement(const char*& p) -> bool { + if(p[0] != '<' || p[1] != '/') return false; + p += 2; + const char* nameStart = p; + while(*p && *p != '>') p++; + if(*p != '>') throw "unclosed closure element"; + const char* nameEnd = p++; + if(memory::compare(_name.data(), nameStart, nameEnd - nameStart)) throw "closure element name mismatch"; + return true; + } + + //parse contents of an element + auto parse(const char*& p) -> void { + const char* dataStart = p; + const char* dataEnd = p; + + while(*p) { + while(*p && *p != '<') p++; + if(!*p) break; + dataEnd = p; + if(parseClosureElement(p) == true) break; + if(parseExpression(p) == true) continue; + parseElement(p); + } + + copy(_value, dataStart, dataEnd - dataStart); + } + + friend auto unserialize(const string&) -> Markup::SharedNode; +}; + +inline auto unserialize(const string& markup) -> Markup::SharedNode { + auto node = new ManagedNode; + try { + const char* p = markup; + node->parse(p); + } catch(const char* error) { + delete node; + node = nullptr; + } + return node; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/match.hpp b/roms/snes-test-roms/bass-untech/nall/string/match.hpp new file mode 100644 index 00000000..48af8542 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/match.hpp @@ -0,0 +1,90 @@ +#pragma once + +namespace nall { + +//todo: these functions are not binary-safe + +inline auto string::match(string_view source) const -> bool { + const char* s = data(); + const char* p = source.data(); + + const char* cp = nullptr; + const char* mp = nullptr; + while(*s && *p != '*') { + if(*p != '?' && *s != *p) return false; + p++, s++; + } + while(*s) { + if(*p == '*') { + if(!*++p) return true; + mp = p, cp = s + 1; + } else if(*p == '?' || *p == *s) { + p++, s++; + } else { + p = mp, s = cp++; + } + } + while(*p == '*') p++; + return !*p; +} + +inline auto string::imatch(string_view source) const -> bool { + static auto chrlower = [](char c) -> char { + return (c >= 'A' && c <= 'Z') ? c + ('a' - 'A') : c; + }; + + const char* s = data(); + const char* p = source.data(); + + const char* cp = nullptr; + const char* mp = nullptr; + while(*s && *p != '*') { + if(*p != '?' && chrlower(*s) != chrlower(*p)) return false; + p++, s++; + } + while(*s) { + if(*p == '*') { + if(!*++p) return true; + mp = p, cp = s + 1; + } else if(*p == '?' || chrlower(*p) == chrlower(*s)) { + p++, s++; + } else { + p = mp, s = cp++; + } + } + while(*p == '*') p++; + return !*p; +} + +inline auto tokenize(const char* s, const char* p) -> bool { + while(*s) { + if(*p == '*') { + while(*s) if(tokenize(s++, p + 1)) return true; + return !*++p; + } + if(*s++ != *p++) return false; + } + while(*p == '*') p++; + return !*p; +} + +inline auto tokenize(vector& list, const char* s, const char* p) -> bool { + while(*s) { + if(*p == '*') { + const char* b = s; + while(*s) { + if(tokenize(list, s++, p + 1)) { + list.prepend(slice(b, 0, --s - b)); + return true; + } + } + list.prepend(b); + return !*++p; + } + if(*s++ != *p++) return false; + } + while(*p == '*') { list.prepend(s); p++; } + return !*p; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/pascal.hpp b/roms/snes-test-roms/bass-untech/nall/string/pascal.hpp new file mode 100644 index 00000000..cadfe767 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/pascal.hpp @@ -0,0 +1,79 @@ +#pragma once + +namespace nall { + +struct string_pascal { + using type = string_pascal; + + string_pascal(const char* text = nullptr) { + if(text && *text) { + uint size = strlen(text); + _data = memory::allocate(sizeof(uint) + size + 1); + ((uint*)_data)[0] = size; + memory::copy(_data + sizeof(uint), text, size); + _data[sizeof(uint) + size] = 0; + } + } + + string_pascal(const string& text) { + if(text.size()) { + _data = memory::allocate(sizeof(uint) + text.size() + 1); + ((uint*)_data)[0] = text.size(); + memory::copy(_data + sizeof(uint), text.data(), text.size()); + _data[sizeof(uint) + text.size()] = 0; + } + } + + string_pascal(const string_pascal& source) { operator=(source); } + string_pascal(string_pascal&& source) { operator=(move(source)); } + + ~string_pascal() { + if(_data) memory::free(_data); + } + + explicit operator bool() const { return _data; } + operator const char*() const { return _data ? _data + sizeof(uint) : nullptr; } + operator string() const { return _data ? string{_data + sizeof(uint)} : ""; } + + auto operator=(const string_pascal& source) -> type& { + if(this == &source) return *this; + if(_data) { memory::free(_data); _data = nullptr; } + if(source._data) { + uint size = source.size(); + _data = memory::allocate(sizeof(uint) + size); + memory::copy(_data, source._data, sizeof(uint) + size); + } + return *this; + } + + auto operator=(string_pascal&& source) -> type& { + if(this == &source) return *this; + if(_data) memory::free(_data); + _data = source._data; + source._data = nullptr; + return *this; + } + + auto operator==(string_view source) const -> bool { + return size() == source.size() && memory::compare(data(), source.data(), size()) == 0; + } + + auto operator!=(string_view source) const -> bool { + return size() != source.size() || memory::compare(data(), source.data(), size()) != 0; + } + + auto data() const -> char* { + if(!_data) return nullptr; + return _data + sizeof(uint); + } + + auto size() const -> uint { + if(!_data) return 0; + return ((uint*)_data)[0]; + } + +protected: + char* _data = nullptr; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/replace.hpp b/roms/snes-test-roms/bass-untech/nall/string/replace.hpp new file mode 100644 index 00000000..49b0073f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/replace.hpp @@ -0,0 +1,94 @@ +#pragma once + +namespace nall { + +template +inline auto string::_replace(string_view from, string_view to, long limit) -> string& { + if(limit <= 0 || from.size() == 0) return *this; + + int size = this->size(); + int matches = 0; + int quoted = 0; + + //count matches first, so that we only need to reallocate memory once + //(recording matches would also require memory allocation, so this is not done) + { const char* p = data(); + for(int n = 0; n <= size - (int)from.size();) { + if(Quoted) { if(p[n] == '\"') { quoted ^= 1; n++; continue; } if(quoted) { n++; continue; } } + if(_compare(p + n, size - n, from.data(), from.size())) { n++; continue; } + + if(++matches >= limit) break; + n += from.size(); + } + } + if(matches == 0) return *this; + + //in-place overwrite + if(to.size() == from.size()) { + char* p = get(); + + for(int n = 0, remaining = matches, quoted = 0; n <= size - (int)from.size();) { + if(Quoted) { if(p[n] == '\"') { quoted ^= 1; n++; continue; } if(quoted) { n++; continue; } } + if(_compare(p + n, size - n, from.data(), from.size())) { n++; continue; } + + memory::copy(p + n, to.data(), to.size()); + + if(!--remaining) break; + n += from.size(); + } + } + + //left-to-right shrink + else if(to.size() < from.size()) { + char* p = get(); + int offset = 0; + int base = 0; + + for(int n = 0, remaining = matches, quoted = 0; n <= size - (int)from.size();) { + if(Quoted) { if(p[n] == '\"') { quoted ^= 1; n++; continue; } if(quoted) { n++; continue; } } + if(_compare(p + n, size - n, from.data(), from.size())) { n++; continue; } + + if(base) memory::move(p + offset, p + base, n - base); + memory::copy(p + offset + (n - base), to.data(), to.size()); + offset += (n - base) + to.size(); + + n += from.size(); + base = n; + if(!--remaining) break; + } + + memory::move(p + offset, p + base, size - base); + resize(size - matches * (from.size() - to.size())); + } + + //right-to-left expand + else if(to.size() > from.size()) { + resize(size + matches * (to.size() - from.size())); + char* p = get(); + + int offset = this->size(); + int base = size; + + for(int n = size, remaining = matches; n >= (int)from.size();) { //quoted reused from parent scope since we are iterating backward + if(Quoted) { if(p[n] == '\"') { quoted ^= 1; n--; continue; } if(quoted) { n--; continue; } } + if(_compare(p + n - from.size(), size - n + from.size(), from.data(), from.size())) { n--; continue; } + + memory::move(p + offset - (base - n), p + base - (base - n), base - n); + memory::copy(p + offset - (base - n) - to.size(), to.data(), to.size()); + offset -= (base - n) + to.size(); + + if(!--remaining) break; + n -= from.size(); + base = n; + } + } + + return *this; +} + +inline auto string::replace(string_view from, string_view to, long limit) -> string& { return _replace<0, 0>(from, to, limit); } +inline auto string::ireplace(string_view from, string_view to, long limit) -> string& { return _replace<1, 0>(from, to, limit); } +inline auto string::qreplace(string_view from, string_view to, long limit) -> string& { return _replace<0, 1>(from, to, limit); } +inline auto string::iqreplace(string_view from, string_view to, long limit) -> string& { return _replace<1, 1>(from, to, limit); } + +}; diff --git a/roms/snes-test-roms/bass-untech/nall/string/split.hpp b/roms/snes-test-roms/bass-untech/nall/string/split.hpp new file mode 100644 index 00000000..8a127b90 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/split.hpp @@ -0,0 +1,46 @@ +#pragma once + +namespace nall { + +template +inline auto vector::_split(string_view source, string_view find, long limit) -> type& { + reset(); + if(limit <= 0 || find.size() == 0) return *this; + + const char* p = source.data(); + int size = source.size(); + int base = 0; + int matches = 0; + + for(int n = 0, quoted = 0; n <= size - (int)find.size();) { + if constexpr(Quoted) { + if(quoted && p[n] == '\\') { n += 2; continue; } + if(p[n] == '\'' && quoted != 2) { quoted ^= 1; n++; continue; } + if(p[n] == '\"' && quoted != 1) { quoted ^= 2; n++; continue; } + if(quoted) { n++; continue; } + } + if(string::_compare(p + n, size - n, find.data(), find.size())) { n++; continue; } + if(matches >= limit) break; + + string& s = operator()(matches); + s.resize(n - base); + memory::copy(s.get(), p + base, n - base); + + n += find.size(); + base = n; + matches++; + } + + string& s = operator()(matches); + s.resize(size - base); + memory::copy(s.get(), p + base, size - base); + + return *this; +} + +inline auto string::split(string_view on, long limit) const -> vector { return vector()._split<0, 0>(*this, on, limit); } +inline auto string::isplit(string_view on, long limit) const -> vector { return vector()._split<1, 0>(*this, on, limit); } +inline auto string::qsplit(string_view on, long limit) const -> vector { return vector()._split<0, 1>(*this, on, limit); } +inline auto string::iqsplit(string_view on, long limit) const -> vector { return vector()._split<1, 1>(*this, on, limit); } + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/transform/cml.hpp b/roms/snes-test-roms/bass-untech/nall/string/transform/cml.hpp new file mode 100644 index 00000000..1e3cf803 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/transform/cml.hpp @@ -0,0 +1,120 @@ +#pragma once + +/* CSS Markup Language (CML) v1.0 parser + * revision 0.02 + */ + +#include + +namespace nall { + +struct CML { + auto& setPath(const string& pathname) { settings.path = pathname; return *this; } + auto& setReader(const function& reader) { settings.reader = reader; return *this; } + + auto parse(const string& filename) -> string; + auto parse(const string& filedata, const string& pathname) -> string; + +private: + struct Settings { + string path; + function reader; + } settings; + + struct State { + string output; + } state; + + struct Variable { + string name; + string value; + }; + vector variables; + bool inMedia = false; + bool inMediaNode = false; + + auto parseDocument(const string& filedata, const string& pathname, uint depth) -> bool; +}; + +inline auto CML::parse(const string& filename) -> string { + if(!settings.path) settings.path = Location::path(filename); + string document = settings.reader ? settings.reader(filename) : string::read(filename); + parseDocument(document, settings.path, 0); + return state.output; +} + +inline auto CML::parse(const string& filedata, const string& pathname) -> string { + settings.path = pathname; + parseDocument(filedata, settings.path, 0); + return state.output; +} + +inline auto CML::parseDocument(const string& filedata, const string& pathname, uint depth) -> bool { + if(depth >= 100) return false; //prevent infinite recursion + + auto vendorAppend = [&](const string& name, const string& value) { + state.output.append(" -moz-", name, ": ", value, ";\n"); + state.output.append(" -webkit-", name, ": ", value, ";\n"); + }; + + for(auto& block : filedata.split("\n\n")) { + auto lines = block.stripRight().split("\n"); + auto name = lines.takeFirst(); + + if(name.beginsWith("include ")) { + name.trimLeft("include ", 1L); + string filename{pathname, name}; + string document = settings.reader ? settings.reader(filename) : string::read(filename); + parseDocument(document, Location::path(filename), depth + 1); + continue; + } + + if(name == "variables") { + for(auto& line : lines) { + auto data = line.split(":", 1L).strip(); + variables.append({data(0), data(1)}); + } + continue; + } + + state.output.append(name, " {\n"); + inMedia = name.beginsWith("@media"); + + for(auto& line : lines) { + if(inMedia && !line.find(": ")) { + if(inMediaNode) state.output.append(" }\n"); + state.output.append(line, " {\n"); + inMediaNode = true; + continue; + } + + auto data = line.split(":", 1L).strip(); + auto name = data(0), value = data(1); + while(auto offset = value.find("var(")) { + bool found = false; + if(auto length = value.findFrom(*offset, ")")) { + string name = slice(value, *offset + 4, *length - 4); + for(auto& variable : variables) { + if(variable.name == name) { + value = {slice(value, 0, *offset), variable.value, slice(value, *offset + *length + 1)}; + found = true; + break; + } + } + } + if(!found) break; + } + state.output.append(inMedia ? " " : " ", name, ": ", value, ";\n"); + if(name == "box-sizing") vendorAppend(name, value); + } + if(inMediaNode) { + state.output.append(" }\n"); + inMediaNode = false; + } + state.output.append("}\n\n"); + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/transform/dml.hpp b/roms/snes-test-roms/bass-untech/nall/string/transform/dml.hpp new file mode 100644 index 00000000..a1862194 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/transform/dml.hpp @@ -0,0 +1,357 @@ +#pragma once + +/* Document Markup Language (DML) v1.0 parser + * revision 0.06 + */ + +#include + +namespace nall { + +struct DML { + auto content() const -> string { return state.output; } + + auto& setAllowHTML(bool allowHTML) { settings.allowHTML = allowHTML; return *this; } + auto& setHost(const string& hostname) { settings.host = hostname; return *this; } + auto& setPath(const string& pathname) { settings.path = pathname; return *this; } + auto& setReader(const function& reader) { settings.reader = reader; return *this; } + + auto parse(const string& filedata, const string& pathname) -> string; + auto parse(const string& filename) -> string; + + auto attribute(const string& name) const -> string; + +private: + struct Settings { + bool allowHTML = true; + string host = "localhost"; + string path; + function reader; + } settings; + + struct State { + string output; + } state; + + struct Attribute { + string name; + string value; + }; + vector attributes; + + auto parseDocument(const string& filedata, const string& pathname, uint depth) -> bool; + auto parseBlock(string& block, const string& pathname, uint depth) -> bool; + auto count(const string& text, char value) -> uint; + + auto address(string text) -> string; + auto escape(const string& text) -> string; + auto anchor(const string& text) -> string; + auto markup(const string& text) -> string; +}; + +inline auto DML::attribute(const string& name) const -> string { + for(auto& attribute : attributes) { + if(attribute.name == name) return attribute.value; + } + return {}; +} + +inline auto DML::parse(const string& filedata, const string& pathname) -> string { + state = {}; + settings.path = pathname; + parseDocument(filedata, settings.path, 0); + return state.output; +} + +inline auto DML::parse(const string& filename) -> string { + state = {}; + if(!settings.path) settings.path = Location::path(filename); + string document = settings.reader ? settings.reader(filename) : string::read(filename); + parseDocument(document, settings.path, 0); + return state.output; +} + +inline auto DML::parseDocument(const string& filedata, const string& pathname, uint depth) -> bool { + if(depth >= 100) return false; //attempt to prevent infinite recursion with reasonable limit + + auto blocks = filedata.split("\n\n"); + for(auto& block : blocks) parseBlock(block, pathname, depth); + return true; +} + +inline auto DML::parseBlock(string& block, const string& pathname, uint depth) -> bool { + if(!block.stripRight()) return true; + auto lines = block.split("\n"); + + //include + if(block.beginsWith("")) { + string filename{pathname, block.trim("", 1L).strip()}; + string document = settings.reader ? settings.reader(filename) : string::read(filename); + parseDocument(document, Location::path(filename), depth + 1); + } + + //attribute + else if(block.beginsWith("? ")) { + for(auto n : range(lines.size())) { + if(!lines[n].beginsWith("? ")) continue; + auto part = lines[n].trimLeft("? ", 1L).split(":", 1L); + if(part.size() != 2) continue; + auto name = part[0].strip(); + auto value = part[1].strip(); + attributes.append({name, value}); + } + } + + //html + else if(block.beginsWith("\n") && settings.allowHTML) { + for(auto n : range(lines.size())) { + if(n == 0 || !lines[n].beginsWith(" ")) continue; + state.output.append(lines[n].trimLeft(" ", 1L), "\n"); + } + } + + //header + else if(auto depth = count(block, '#')) { + auto content = slice(lines.takeLeft(), depth + 1); + auto data = markup(content); + auto name = anchor(content); + if(depth <= 5) { + state.output.append("", data); + for(auto& line : lines) { + if(count(line, '#') != depth) continue; + state.output.append("", slice(line, depth + 1), ""); + } + state.output.append("\n"); + } + } + + //navigation + else if(count(block, '-')) { + state.output.append("

\n"); + } + + //list + else if(count(block, '*')) { + uint level = 0; + for(auto& line : lines) { + if(auto depth = count(line, '*')) { + while(level < depth) level++, state.output.append("
    \n"); + while(level > depth) level--, state.output.append("
\n"); + auto data = markup(slice(line, depth + 1)); + state.output.append("
  • ", data, "
  • \n"); + } + } + while(level--) state.output.append("\n"); + } + + //quote + else if(count(block, '>')) { + uint level = 0; + for(auto& line : lines) { + if(auto depth = count(line, '>')) { + while(level < depth) level++, state.output.append("
    \n"); + while(level > depth) level--, state.output.append("
    \n"); + auto data = markup(slice(line, depth + 1)); + state.output.append(data, "\n"); + } + } + while(level--) state.output.append("\n"); + } + + //code + else if(block.beginsWith(" ")) { + state.output.append("
    ");
    +    for(auto& line : lines) {
    +      if(!line.beginsWith("  ")) continue;
    +      state.output.append(escape(line.trimLeft("  ", 1L)), "\n");
    +    }
    +    state.output.trimRight("\n", 1L).append("
    \n"); + } + + //divider + else if(block.equals("---")) { + state.output.append("
    \n"); + } + + //paragraph + else { + auto content = markup(block); + if(content.beginsWith("")) { + state.output.append(content, "\n"); + } else { + state.output.append("

    ", content, "

    \n"); + } + } + + return true; +} + +inline auto DML::count(const string& text, char value) -> uint { + for(uint n = 0; n < text.size(); n++) { + if(text[n] != value) { + if(text[n] == ' ') return n; + break; + } + } + return 0; +} + +// . => domain +// ./* => domain/* +// ../subdomain => subdomain.domain +// ../subdomain/* => subdomain.domain/* +inline auto DML::address(string s) -> string { + if(s.beginsWith("../")) { + s.trimLeft("../", 1L); + if(auto p = s.find("/")) { + return {"//", s.slice(0, *p), ".", settings.host, s.slice(*p)}; + } else { + return {"//", s, ".", settings.host}; + } + } + if(s.beginsWith("./")) { + s.trimLeft(".", 1L); + return {"//", settings.host, s}; + } + if(s == ".") { + return {"//", settings.host}; + } + return s; +} + +inline auto DML::escape(const string& text) -> string { + string output; + for(auto c : text) { + if(c == '&') { output.append("&"); continue; } + if(c == '<') { output.append("<"); continue; } + if(c == '>') { output.append(">"); continue; } + if(c == '"') { output.append("""); continue; } + output.append(c); + } + return output; +} + +inline auto DML::anchor(const string& text) -> string { + string output; + for(char c : text) { + if(c >= 'a' && c <= 'z') { output.append(c); continue; } + if(c >= 'A' && c <= 'Z') { output.append(char(c + 0x20)); continue; } + if(!output.endsWith("-")) output.append('-'); + } + return output.trim("-", "-"); +} + +inline auto DML::markup(const string& s) -> string { + string t; + + boolean strong; + boolean emphasis; + boolean insertion; + boolean deletion; + boolean code; + + maybe link; + maybe image; + + for(uint n = 0; n < s.size();) { + char a = s[n]; + char b = s[n + 1]; + + if(!link && !image) { + if(a == '*' && b == '*') { t.append(strong.flip() ? "" : ""); n += 2; continue; } + if(a == '/' && b == '/') { t.append(emphasis.flip() ? "" : ""); n += 2; continue; } + if(a == '_' && b == '_') { t.append(insertion.flip() ? "" : ""); n += 2; continue; } + if(a == '~' && b == '~') { t.append(deletion.flip() ? "" : ""); n += 2; continue; } + if(a == '|' && b == '|') { t.append(code.flip() ? "" : ""); n += 2; continue; } + if(a =='\\' && b =='\\') { t.append("
    "); n += 2; continue; } + + if(a == '[' && b == '[') { n += 2; link = n; continue; } + if(a == '{' && b == '{') { n += 2; image = n; continue; } + } + + if(link && !image && a == ']' && b == ']') { + auto list = slice(s, link(), n - link()).split("::", 1L); + string uri = address(list.last()); + string name = list.size() == 2 ? list.first() : uri.split("//", 1L).last(); + + t.append("", escape(name), ""); + + n += 2; + link = nothing; + continue; + } + + if(image && !link && a == '}' && b == '}') { + auto side = slice(s, image(), n - image()).split("}{", 1L); + auto list = side(0).split("::", 1L); + string uri = address(list.last()); + string name = list.size() == 2 ? list.first() : uri.split("//", 1L).last(); + list = side(1).split("; "); + boolean link, title, caption; + string width, height; + for(auto p : list) { + if(p == "link") { link = true; continue; } + if(p == "title") { title = true; continue; } + if(p == "caption") { caption = true; continue; } + if(p.beginsWith("width:")) { p.trimLeft("width:", 1L); width = p.strip(); continue; } + if(p.beginsWith("height:")) { p.trimLeft("height:", 1L); height = p.strip(); continue; } + } + + if(caption) { + t.append("
    \n"); + if(link) t.append(""); + t.append("\"",\n"); + if(link) t.append("\n"); + t.append("
    ", escape(name), "
    \n"); + t.append("
    "); + } else { + if(link) t.append(""); + t.append("\"","); + if(link) t.append(""); + } + + n += 2; + image = nothing; + continue; + } + + if(link || image) { n++; continue; } + if(a =='\\') { t.append(b); n += 2; continue; } + if(a == '&') { t.append("&"); n++; continue; } + if(a == '<') { t.append("<"); n++; continue; } + if(a == '>') { t.append(">"); n++; continue; } + if(a == '"') { t.append("""); n++; continue; } + t.append(a); n++; continue; + } + + if(strong) t.append(""); + if(emphasis) t.append(""); + if(insertion) t.append(""); + if(deletion) t.append(""); + if(code) t.append(""); + + return t; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/trim.hpp b/roms/snes-test-roms/bass-untech/nall/string/trim.hpp new file mode 100644 index 00000000..e34d3d2d --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/trim.hpp @@ -0,0 +1,102 @@ +#pragma once + +namespace nall { + +inline auto string::trim(string_view lhs, string_view rhs, long limit) -> string& { + trimRight(rhs, limit); + trimLeft(lhs, limit); + return *this; +} + +inline auto string::trimLeft(string_view lhs, long limit) -> string& { + if(lhs.size() == 0) return *this; + long matches = 0; + while(matches < limit) { + int offset = lhs.size() * matches; + int length = (int)size() - offset; + if(length < (int)lhs.size()) break; + if(memory::compare(data() + offset, lhs.data(), lhs.size()) != 0) break; + matches++; + } + if(matches) remove(0, lhs.size() * matches); + return *this; +} + +inline auto string::trimRight(string_view rhs, long limit) -> string& { + if(rhs.size() == 0) return *this; + long matches = 0; + while(matches < limit) { + int offset = (int)size() - rhs.size() * (matches + 1); + int length = (int)size() - offset; + if(offset < 0 || length < (int)rhs.size()) break; + if(memory::compare(data() + offset, rhs.data(), rhs.size()) != 0) break; + matches++; + } + if(matches) resize(size() - rhs.size() * matches); + return *this; +} + +inline auto string::itrim(string_view lhs, string_view rhs, long limit) -> string& { + itrimRight(rhs, limit); + itrimLeft(lhs, limit); + return *this; +} + +inline auto string::itrimLeft(string_view lhs, long limit) -> string& { + if(lhs.size() == 0) return *this; + long matches = 0; + while(matches < limit) { + int offset = lhs.size() * matches; + int length = (int)size() - offset; + if(length < (int)lhs.size()) break; + if(memory::icompare(data() + offset, lhs.data(), lhs.size()) != 0) break; + matches++; + } + if(matches) remove(0, lhs.size() * matches); + return *this; +} + +inline auto string::itrimRight(string_view rhs, long limit) -> string& { + if(rhs.size() == 0) return *this; + long matches = 0; + while(matches < limit) { + int offset = (int)size() - rhs.size() * (matches + 1); + int length = (int)size() - offset; + if(offset < 0 || length < (int)rhs.size()) break; + if(memory::icompare(data() + offset, rhs.data(), rhs.size()) != 0) break; + matches++; + } + if(matches) resize(size() - rhs.size() * matches); + return *this; +} + +inline auto string::strip() -> string& { + stripRight(); + stripLeft(); + return *this; +} + +inline auto string::stripLeft() -> string& { + uint length = 0; + while(length < size()) { + char input = operator[](length); + if(input != ' ' && input != '\t' && input != '\r' && input != '\n') break; + length++; + } + if(length) remove(0, length); + return *this; +} + +inline auto string::stripRight() -> string& { + uint length = 0; + while(length < size()) { + bool matched = false; + char input = operator[](size() - length - 1); + if(input != ' ' && input != '\t' && input != '\r' && input != '\n') break; + length++; + } + if(length) resize(size() - length); + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/utf8.hpp b/roms/snes-test-roms/bass-untech/nall/string/utf8.hpp new file mode 100644 index 00000000..ff03cecb --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/utf8.hpp @@ -0,0 +1,32 @@ +#pragma once + +namespace nall { + +//note: this function assumes the string contains valid UTF-8 characters +//invalid characters will result in an incorrect result from this function +//invalid case 1: byte 1 == 0b'01xxxxxx +//invalid case 2: bytes 2-4 != 0b'10xxxxxx +//invalid case 3: end of string without bytes 2-4 present +inline auto characters(string_view self, int offset, int length) -> uint { + uint characters = 0; + if(offset < 0) offset = self.size() - abs(offset); + if(offset >= 0 && offset < self.size()) { + if(length < 0) length = self.size() - offset; + if(length >= 0) { + for(int index = offset; index < offset + length;) { + auto byte = self.data()[index++]; + if((byte & 0b111'00000) == 0b110'00000) index += 1; + if((byte & 0b1111'0000) == 0b1110'0000) index += 2; + if((byte & 0b11111'000) == 0b11110'000) index += 3; + characters++; + } + } + } + return characters; +} + +inline auto string::characters(int offset, int length) const -> uint { + return nall::characters(*this, offset, length); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/utility.hpp b/roms/snes-test-roms/bass-untech/nall/string/utility.hpp new file mode 100644 index 00000000..6f93e944 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/utility.hpp @@ -0,0 +1,165 @@ +#pragma once + +namespace nall { + +inline auto string::read(string_view filename) -> string { + #if !defined(_WIN32) + FILE* fp = fopen(filename, "rb"); + #else + FILE* fp = _wfopen(utf16_t(filename), L"rb"); + #endif + + string result; + if(!fp) return result; + + fseek(fp, 0, SEEK_END); + int filesize = ftell(fp); + if(filesize < 0) return fclose(fp), result; + + rewind(fp); + result.resize(filesize); + (void)fread(result.get(), 1, filesize, fp); + return fclose(fp), result; +} + +inline auto string::repeat(string_view pattern, uint times) -> string { + string result; + while(times--) result.append(pattern.data()); + return result; +} + +inline auto string::fill(char fill) -> string& { + memory::fill(get(), size(), fill); + return *this; +} + +inline auto string::hash() const -> uint { + const char* p = data(); + uint length = size(); + uint result = 5381; + while(length--) result = (result << 5) + result + *p++; + return result; +} + +inline auto string::remove(uint offset, uint length) -> string& { + char* p = get(); + length = min(length, size()); + memory::move(p + offset, p + offset + length, size() - length); + return resize(size() - length); +} + +inline auto string::reverse() -> string& { + char* p = get(); + uint length = size(); + uint pivot = length >> 1; + for(int x = 0, y = length - 1; x < pivot && y >= 0; x++, y--) std::swap(p[x], p[y]); + return *this; +} + +//+length => insert/delete from start (right justify) +//-length => insert/delete from end (left justify) +inline auto string::size(int length, char fill) -> string& { + uint size = this->size(); + if(size == length) return *this; + + bool right = length >= 0; + length = abs(length); + + if(size < length) { //expand + resize(length); + char* p = get(); + uint displacement = length - size; + if(right) memory::move(p + displacement, p, size); + else p += size; + while(displacement--) *p++ = fill; + } else { //shrink + char* p = get(); + uint displacement = size - length; + if(right) memory::move(p, p + displacement, length); + resize(length); + } + + return *this; +} + +inline auto slice(string_view self, int offset, int length) -> string { + string result; + if(offset < 0) offset = self.size() - abs(offset); + if(offset >= 0 && offset < self.size()) { + if(length < 0) length = self.size() - offset; + if(length >= 0) { + result.resize(length); + memory::copy(result.get(), self.data() + offset, length); + } + } + return result; +} + +inline auto string::slice(int offset, int length) const -> string { + return nall::slice(*this, offset, length); +} + +template inline auto fromInteger(char* result, T value) -> char* { + bool negative = value < 0; + if(!negative) value = -value; //negate positive integers to support eg INT_MIN + + char buffer[1 + sizeof(T) * 3]; + uint size = 0; + + do { + int n = value % 10; //-0 to -9 + buffer[size++] = '0' - n; //'0' to '9' + value /= 10; + } while(value); + if(negative) buffer[size++] = '-'; + + for(int x = size - 1, y = 0; x >= 0 && y < size; x--, y++) result[x] = buffer[y]; + result[size] = 0; + return result; +} + +template inline auto fromNatural(char* result, T value) -> char* { + char buffer[1 + sizeof(T) * 3]; + uint size = 0; + + do { + uint n = value % 10; + buffer[size++] = '0' + n; + value /= 10; + } while(value); + + for(int x = size - 1, y = 0; x >= 0 && y < size; x--, y++) result[x] = buffer[y]; + result[size] = 0; + return result; +} + +//using sprintf is certainly not the most ideal method to convert +//a double to a string ... but attempting to parse a double by +//hand, digit-by-digit, results in subtle rounding errors. +template inline auto fromReal(char* result, T value) -> uint { + char buffer[256]; + #ifdef _WIN32 + //Windows C-runtime does not support long double via sprintf() + sprintf(buffer, "%f", (double)value); + #else + sprintf(buffer, "%Lf", (long double)value); + #endif + + //remove excess 0's in fraction (2.500000 -> 2.5) + for(char* p = buffer; *p; p++) { + if(*p == '.') { + char* p = buffer + strlen(buffer) - 1; + while(*p == '0') { + if(*(p - 1) != '.') *p = 0; //... but not for eg 1.0 -> 1. + p--; + } + break; + } + } + + uint length = strlen(buffer); + if(result) strcpy(result, buffer); + return length + 1; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/vector.hpp b/roms/snes-test-roms/bass-untech/nall/string/vector.hpp new file mode 100644 index 00000000..642020f7 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/vector.hpp @@ -0,0 +1,60 @@ +#pragma once + +namespace nall { + +template inline auto vector::append(const string& data, P&&... p) -> type& { + vector_base::append(data); + append(forward

    (p)...); + return *this; +} + +inline auto vector::append() -> type& { + return *this; +} + +inline auto vector::isort() -> type& { + sort([](const string& x, const string& y) { + return memory::icompare(x.data(), x.size(), y.data(), y.size()) < 0; + }); + return *this; +} + +inline auto vector::find(string_view source) const -> maybe { + for(uint n = 0; n < size(); n++) { + if(operator[](n).equals(source)) return n; + } + return {}; +} + +inline auto vector::ifind(string_view source) const -> maybe { + for(uint n = 0; n < size(); n++) { + if(operator[](n).iequals(source)) return n; + } + return {}; +} + +inline auto vector::match(string_view pattern) const -> vector { + vector result; + for(uint n = 0; n < size(); n++) { + if(operator[](n).match(pattern)) result.append(operator[](n)); + } + return result; +} + +inline auto vector::merge(string_view separator) const -> string { + string output; + for(uint n = 0; n < size(); n++) { + output.append(operator[](n)); + if(n < size() - 1) output.append(separator.data()); + } + return output; +} + +inline auto vector::strip() -> type& { + for(uint n = 0; n < size(); n++) { + operator[](n).strip(); + } + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/string/view.hpp b/roms/snes-test-roms/bass-untech/nall/string/view.hpp new file mode 100644 index 00000000..c070d678 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/string/view.hpp @@ -0,0 +1,89 @@ +#pragma once + +namespace nall { + +inline string_view::string_view() { + _string = nullptr; + _data = ""; + _size = 0; +} + +inline string_view::string_view(const string_view& source) { + if(this == &source) return; + _string = nullptr; + _data = source._data; + _size = source._size; +} + +inline string_view::string_view(string_view&& source) { + if(this == &source) return; + _string = source._string; + _data = source._data; + _size = source._size; + source._string = nullptr; +} + +inline string_view::string_view(const char* data) { + _string = nullptr; + _data = data; + _size = -1; //defer length calculation, as it is often unnecessary +} + +inline string_view::string_view(const char* data, uint size) { + _string = nullptr; + _data = data; + _size = size; +} + +inline string_view::string_view(const string& source) { + _string = nullptr; + _data = source.data(); + _size = source.size(); +} + +template +inline string_view::string_view(P&&... p) { + _string = new string{forward

    (p)...}; + _data = _string->data(); + _size = _string->size(); +} + +inline string_view::~string_view() { + if(_string) delete _string; +} + +inline auto string_view::operator=(const string_view& source) -> type& { + if(this == &source) return *this; + _string = nullptr; + _data = source._data; + _size = source._size; + return *this; +} + +inline auto string_view::operator=(string_view&& source) -> type& { + if(this == &source) return *this; + _string = source._string; + _data = source._data; + _size = source._size; + source._string = nullptr; + return *this; +} + +inline string_view::operator bool() const { + return _size > 0; +} + +inline string_view::operator const char*() const { + return _data; +} + +inline auto string_view::data() const -> const char* { + return _data; +} + +inline auto string_view::size() const -> uint { + if(_size < 0) _size = strlen(_data); + return _size; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/suffix-array.hpp b/roms/snes-test-roms/bass-untech/nall/suffix-array.hpp new file mode 100644 index 00000000..3189cd75 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/suffix-array.hpp @@ -0,0 +1,386 @@ +#pragma once + +#include +#include +#include +#include +#include + +namespace nall { + +/* + +input: + data = "acaacatat" + 0 "acaacatat" + 1 "caacatat" + 2 "aacatat" + 3 "acatat" + 4 "catat" + 5 "atat" + 6 "tat" + 7 "at" + 8 "t" + 9 "" + +suffix_array: + suffixes = [9,2,0,3,7,5,1,4,8,6] => input + suffixes: + 9 "" + 2 "aacatat" + 0 "acaacatat" + 3 "acatat" + 7 "at" + 5 "atat" + 1 "caacatat" + 4 "catat" + 8 "t" + 6 "tat" + +[auxiliary data structures to represent information lost from suffix trees] + +suffix_array_invert: + inverted = [2,6,1,3,7,5,9,4,8,0] => input + suffixes[inverted]: + 2 "acaacatat" + 6 "caacatat" + 1 "aacatat" + 3 "acatat" + 7 "catat" + 5 "atat" + 9 "tat" + 4 "at" + 8 "t" + 0 "" + +suffix_array_phi: + phi = [2,5,9,0,1,7,8,3,4,0] + +suffix_array_lcp: + prefixes = [0,0,1,3,1,2,0,2,0,1] => lcp[n] == lcp(n, n-1) + "" 0 + "aacatat" 0 + "acaacatat" 1 "a" + "acatat" 3 "aca" + "at" 1 "a" + "atat" 2 "at" + "caacatat" 0 + "catat" 2 "ca" + "t" 0 + "tat" 1 "t" + +suffix_array_plcp: + plcp = [1,0,0,3,2,2,1,1,0,0] + +suffix_array_lrcp: + llcp = [0,0,0,3,0,2,0,2,0,0] => llcp[m] == lcp(l, m) + rlcp = [0,1,1,1,0,0,0,0,0,0] => rlcp[m] == lcp(m, r) + +suffix_array_lpf: + lengths = [0,0,1,3,2,1,0,2,1,0] + offsets = [0,0,0,0,1,3,4,5,6,2] + "acaacatat" (0,-) + "caacatat" (0,-) + "aacatat" (1,0) at 0, match "a" + "acatat" (3,0) at 0, match "aca" + "catat" (2,1) at 1, match "ca" + "atat" (1,3) at 3, match "a" + "tat" (0,-) + "at" (2,5) at 5, match "at" + "t" (1,6) at 6, match "t" + "" (0,-) + +*/ + +// suffix array via induced sorting +// O(n) +inline auto suffix_array(array_view input) -> vector { + return induced_sort(input); +} + +// inverse +// O(n) +inline auto suffix_array_invert(array_view sa) -> vector { + vector isa; + isa.reallocate(sa.size()); + for(int i : range(sa.size())) isa[sa[i]] = i; + return isa; +} + +// auxiliary data structure for plcp and lpf computation +// O(n) +inline auto suffix_array_phi(array_view sa) -> vector { + vector phi; + phi.reallocate(sa.size()); + phi[sa[0]] = 0; + for(int i : range(1, sa.size())) phi[sa[i]] = sa[i - 1]; + return phi; +} + +// longest common prefix: lcp(l, r) +// O(n) +inline auto suffix_array_lcp(int l, int r, array_view sa, array_view input) -> int { + int i = sa[l], j = sa[r], k = 0, size = input.size(); + while(i + k < size && j + k < size && input[i + k] == input[j + k]) k++; + return k; +} + +// longest common prefix: lcp(i, j, k) +// O(n) +inline auto suffix_array_lcp(int i, int j, int k, array_view input) -> int { + int size = input.size(); + while(i + k < size && j + k < size && input[i + k] == input[j + k]) k++; + return k; +} + +// longest common prefix: lcp[n] == lcp(n, n-1) +// O(n) +inline auto suffix_array_lcp(array_view sa, array_view isa, array_view input) -> vector { + int k = 0, size = input.size(); + vector lcp; + lcp.reallocate(size + 1); + for(int i : range(size)) { + if(isa[i] == size) { k = 0; continue; } //the next substring is empty; ignore it + int j = sa[isa[i] + 1]; + while(i + k < size && j + k < size && input[i + k] == input[j + k]) k++; + lcp[1 + isa[i]] = k; + if(k) k--; + } + lcp[0] = 0; + return lcp; +} + +// longest common prefix (from permuted longest common prefix) +// O(n) +inline auto suffix_array_lcp(array_view plcp, array_view sa) -> vector { + vector lcp; + lcp.reallocate(plcp.size()); + for(int i : range(plcp.size())) lcp[i] = plcp[sa[i]]; + return lcp; +} + +// permuted longest common prefix +// O(n) +inline auto suffix_array_plcp(array_view phi, array_view input) -> vector { + vector plcp; + plcp.reallocate(phi.size()); + int k = 0, size = input.size(); + for(int i : range(size)) { + int j = phi[i]; + while(i + k < size && j + k < size && input[i + k] == input[j + k]) k++; + plcp[i] = k; + if(k) k--; + } + return plcp; +} + +// permuted longest common prefix (from longest common prefix) +// O(n) +inline auto suffix_array_plcp(array_view lcp, array_view sa) -> vector { + vector plcp; + plcp.reallocate(lcp.size()); + for(int i : range(lcp.size())) plcp[sa[i]] = lcp[i]; + return plcp; +} + +// longest common prefixes - left + right +// llcp[m] == lcp(l, m) +// rlcp[m] == lcp(m, r) +// O(n) +// requires: lcp -or- plcp+sa +inline auto suffix_array_lrcp(vector& llcp, vector& rlcp, array_view lcp, array_view plcp, array_view sa, array_view input) -> void { + int size = input.size(); + llcp.reset(), llcp.reallocate(size + 1); + rlcp.reset(), rlcp.reallocate(size + 1); + + function recurse = [&](int l, int r) -> int { + if(l >= r - 1) { + if(l >= size) return 0; + if(lcp) return lcp[l]; + return plcp[sa[l]]; + } + int m = l + r >> 1; + llcp[m - 1] = recurse(l, m); + rlcp[m - 1] = recurse(m, r); + return min(llcp[m - 1], rlcp[m - 1]); + }; + recurse(1, size + 1); + + llcp[0] = 0; + rlcp[0] = 0; +} + +// longest previous factor +// O(n) +// optional: plcp +inline auto suffix_array_lpf(vector& lengths, vector& offsets, array_view phi, array_view plcp, array_view input) -> void { + int k = 0, size = input.size(); + lengths.reset(), lengths.resize(size + 1, -1); + offsets.reset(), offsets.resize(size + 1, -1); + + function recurse = [&](int i, int j, int k) -> void { + if(lengths[i] < 0) { + lengths[i] = k; + offsets[i] = j; + } else if(lengths[i] < k) { + if(offsets[i] > j) { + recurse(offsets[i], j, lengths[i]); + } else { + recurse(j, offsets[i], lengths[i]); + } + lengths[i] = k; + offsets[i] = j; + } else { + if(offsets[i] > j) { + recurse(offsets[i], j, k); + } else { + recurse(j, offsets[i], k); + } + } + }; + + for(int i : range(size)) { + int j = phi[i]; + if(plcp) k = plcp[i]; + else while(i + k < size && j + k < size && input[i + k] == input[j + k]) k++; + if(i > j) { + recurse(i, j, k); + } else { + recurse(j, i, k); + } + if(k) k--; + } + + lengths[0] = 0; + offsets[0] = 0; +} + +// O(n log m) +inline auto suffix_array_find(int& length, int& offset, array_view sa, array_view input, array_view match) -> bool { + length = 0, offset = 0; + int l = 0, r = input.size(); + + while(l < r - 1) { + int m = l + r >> 1; + int s = sa[m]; + + int k = 0; + while(k < match.size() && s + k < input.size()) { + if(match[k] != input[s + k]) break; + k++; + } + + if(k > length) { + length = k; + offset = s; + if(k == match.size()) return true; + } + + if(k == match.size() || s + k == input.size()) k--; + + if(match[k] < input[s + k]) { + r = m; + } else { + l = m; + } + } + + return false; +} + +// O(n + log m) +inline auto suffix_array_find(int& length, int& offset, array_view llcp, array_view rlcp, array_view sa, array_view input, array_view match) -> bool { + length = 0, offset = 0; + int l = 0, r = input.size(), k = 0; + + while(l < r - 1) { + int m = l + r >> 1; + int s = sa[m]; + + while(k < match.size() && s + k < input.size()) { + if(match[k] != input[s + k]) break; + k++; + } + + if(k > length) { + length = k; + offset = s; + if(k == match.size()) return true; + } + + if(k == match.size() || s + k == input.size()) k--; + + if(match[k] < input[s + k]) { + r = m; + k = min(k, llcp[m]); + } else { + l = m; + k = min(k, rlcp[m]); + } + } + + return false; +} + +// + +//there are multiple strategies for building the required auxiliary structures for suffix arrays + +struct SuffixArray { + using type = SuffixArray; + + //O(n) + SuffixArray(array_view input) : input(input) { + sa = suffix_array(input); + } + + //O(n) + auto lrcp() -> type& { + //if(!isa) isa = suffix_array_invert(sa); + //if(!lcp) lcp = suffix_array_lcp(sa, isa, input); + if(!phi) phi = suffix_array_phi(sa); + if(!plcp) plcp = suffix_array_plcp(phi, input); + //if(!lcp) lcp = suffix_array_lcp(plcp, sa); + if(!llcp || !rlcp) suffix_array_lrcp(llcp, rlcp, lcp, plcp, sa, input); + return *this; + } + + //O(n) + auto lpf() -> type& { + if(!phi) phi = suffix_array_phi(sa); + //if(!plcp) plcp = suffix_array_plcp(phi, input); + if(!lengths || !offsets) suffix_array_lpf(lengths, offsets, phi, plcp, input); + return *this; + } + + auto operator[](int offset) const -> int { + return sa[offset]; + } + + //O(n log m) + //O(n + log m) with lrcp() + auto find(int& length, int& offset, array_view match) -> bool { + if(!llcp || !rlcp) return suffix_array_find(length, offset, sa, input, match); //O(n log m) + return suffix_array_find(length, offset, llcp, rlcp, sa, input, match); //O(n + log m) + } + + //O(n) with lpf() + auto previous(int& length, int& offset, int address) -> void { + length = lengths[address]; + offset = offsets[address]; + } + + //non-owning reference: SuffixArray is invalidated if memory is freed + array_view input; + + //suffix array and auxiliary data structures + vector sa; //suffix array + vector isa; //inverted suffix array + vector phi; //phi + vector plcp; //permuted longest common prefixes + vector lcp; //longest common prefixes + vector llcp; //longest common prefixes - left + vector rlcp; //longest common prefixes - right + vector lengths; //longest previous factors + vector offsets; //longest previous factors +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/terminal.hpp b/roms/snes-test-roms/bass-untech/nall/terminal.hpp new file mode 100644 index 00000000..90041639 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/terminal.hpp @@ -0,0 +1,65 @@ +#pragma once + +#include + +namespace nall::terminal { + +inline auto escapable() -> bool { + #if defined(PLATFORM_WINDOWS) + //todo: colors are supported by Windows 10+ and with alternate terminals (eg msys) + //disabled for now for compatibility with Windows 7 and 8.1's cmd.exe + return false; + #endif + return true; +} + +namespace color { + +template inline auto black(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[30m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto blue(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[94m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto green(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[92m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto cyan(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[96m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto red(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[91m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto magenta(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[95m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto yellow(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[93m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto white(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[97m", string{forward

    (p)...}, "\e[0m"}; +} + +template inline auto gray(P&&... p) -> string { + if(!escapable()) return string{forward

    (p)...}; + return {"\e[37m", string{forward

    (p)...}, "\e[0m"}; +} + +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/thread.hpp b/roms/snes-test-roms/bass-untech/nall/thread.hpp new file mode 100644 index 00000000..c3675efd --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/thread.hpp @@ -0,0 +1,144 @@ +#pragma once + +//simple thread library +//primary rationale is that std::thread does not support custom stack sizes +//this is highly critical in certain applications such as threaded web servers +//an added bonus is that it avoids licensing issues on Windows +//win32-pthreads (needed for std::thread) is licensed under the GPL only + +#include +#include +#include + +namespace nall { + using mutex = std::mutex; + using recursive_mutex = std::recursive_mutex; + template using lock_guard = std::lock_guard; + template using atomic = std::atomic; +} + +#if defined(API_POSIX) + +#include + +namespace nall { + +struct thread { + auto join() -> void; + + static auto create(const function& callback, uintptr parameter = 0, uint stacksize = 0) -> thread; + static auto detach() -> void; + static auto exit() -> void; + + struct context { + function void> callback; + uintptr parameter = 0; + }; + +private: + pthread_t handle = (pthread_t)nullptr; +}; + +inline auto _threadCallback(void* parameter) -> void* { + auto context = (thread::context*)parameter; + context->callback(context->parameter); + delete context; + return nullptr; +} + +inline auto thread::join() -> void { + pthread_join(handle, nullptr); +} + +inline auto thread::create(const function& callback, uintptr parameter, uint stacksize) -> thread { + thread instance; + + auto context = new thread::context; + context->callback = callback; + context->parameter = parameter; + + pthread_attr_t attr; + pthread_attr_init(&attr); + if(stacksize) pthread_attr_setstacksize(&attr, max(PTHREAD_STACK_MIN, stacksize)); + + pthread_create(&instance.handle, &attr, _threadCallback, (void*)context); + return instance; +} + +inline auto thread::detach() -> void { + pthread_detach(pthread_self()); +} + +inline auto thread::exit() -> void { + pthread_exit(nullptr); +} + +} + +#elif defined(API_WINDOWS) + +namespace nall { + +struct thread { + ~thread(); + auto join() -> void; + + static auto create(const function& callback, uintptr parameter = 0, uint stacksize = 0) -> thread; + static auto detach() -> void; + static auto exit() -> void; + + struct context { + function void> callback; + uintptr parameter = 0; + }; + +private: + HANDLE handle = 0; +}; + +inline auto WINAPI _threadCallback(void* parameter) -> DWORD { + auto context = (thread::context*)parameter; + context->callback(context->parameter); + delete context; + return 0; +} + +inline thread::~thread() { + if(handle) { + CloseHandle(handle); + handle = 0; + } +} + +inline auto thread::join() -> void { + if(handle) { + WaitForSingleObject(handle, INFINITE); + CloseHandle(handle); + handle = 0; + } +} + +inline auto thread::create(const function& callback, uintptr parameter, uint stacksize) -> thread { + thread instance; + + auto context = new thread::context; + context->callback = callback; + context->parameter = parameter; + + instance.handle = CreateThread(nullptr, stacksize, _threadCallback, (void*)context, 0, nullptr); + return instance; +} + +inline auto thread::detach() -> void { + //Windows threads do not use this concept: + //~thread() frees resources via CloseHandle() + //thread continues to run even after handle is closed +} + +inline auto thread::exit() -> void { + ExitThread(0); +} + +} + +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/traits.hpp b/roms/snes-test-roms/bass-untech/nall/traits.hpp new file mode 100644 index 00000000..4c237fb8 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/traits.hpp @@ -0,0 +1,52 @@ +#pragma once + +#include +#include + +//pull all type traits used by nall from std namespace into nall namespace +//this removes the requirement to prefix type traits with std:: within nall + +namespace nall { + using std::add_const; + using std::conditional; + using std::conditional_t; + using std::decay; + using std::declval; + using std::enable_if; + using std::enable_if_t; + using std::false_type; + using std::is_floating_point; + using std::is_floating_point_v; + using std::forward; + using std::initializer_list; + using std::is_array; + using std::is_array_v; + using std::is_base_of; + using std::is_base_of_v; + using std::is_function; + using std::is_integral; + using std::is_integral_v; + using std::is_pointer; + using std::is_pointer_v; + using std::is_same; + using std::is_same_v; + using std::is_signed; + using std::is_signed_v; + using std::is_unsigned; + using std::is_unsigned_v; + using std::move; + using std::nullptr_t; + using std::remove_extent; + using std::remove_extent_t; + using std::remove_reference; + using std::remove_reference_t; + using std::swap; + using std::true_type; +} + +namespace std { + #if INTMAX_BITS >= 128 + template<> struct is_signed : true_type {}; + template<> struct is_unsigned : true_type {}; + #endif +} diff --git a/roms/snes-test-roms/bass-untech/nall/unique-pointer.hpp b/roms/snes-test-roms/bass-untech/nall/unique-pointer.hpp new file mode 100644 index 00000000..03399801 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/unique-pointer.hpp @@ -0,0 +1,116 @@ +#pragma once + +namespace nall { + +template +struct unique_pointer { + template static auto create(P&&... p) { + return unique_pointer{new T{forward

    (p)...}}; + } + + using type = T; + T* pointer = nullptr; + function deleter; + + unique_pointer(const unique_pointer&) = delete; + auto operator=(const unique_pointer&) -> unique_pointer& = delete; + + unique_pointer(T* pointer = nullptr, const function& deleter = {}) : pointer(pointer), deleter(deleter) {} + ~unique_pointer() { reset(); } + + auto operator=(T* source) -> unique_pointer& { + reset(); + pointer = source; + return *this; + } + + explicit operator bool() const { return pointer; } + + auto operator->() -> T* { return pointer; } + auto operator->() const -> const T* { return pointer; } + + auto operator*() -> T& { return *pointer; } + auto operator*() const -> const T& { return *pointer; } + + auto operator()() -> T& { return *pointer; } + auto operator()() const -> const T& { return *pointer; } + + auto data() -> T* { return pointer; } + auto data() const -> const T* { return pointer; } + + auto release() -> T* { + auto result = pointer; + pointer = nullptr; + return result; + } + + auto reset() -> void { + if(pointer) { + if(deleter) { + deleter(pointer); + } else { + delete pointer; + } + pointer = nullptr; + } + } + + auto swap(unique_pointer& target) -> void { + std::swap(pointer, target.pointer); + std::swap(deleter, target.deleter); + } +}; + +template +struct unique_pointer { + using type = T; + T* pointer = nullptr; + function deleter; + + unique_pointer(const unique_pointer&) = delete; + auto operator=(const unique_pointer&) -> unique_pointer& = delete; + + unique_pointer(T* pointer = nullptr, const function& deleter = {}) : pointer(pointer), deleter(deleter) {} + ~unique_pointer() { reset(); } + + auto operator=(T* source) -> unique_pointer& { + reset(); + pointer = source; + return *this; + } + + explicit operator bool() const { return pointer; } + + auto operator()() -> T* { return pointer; } + auto operator()() const -> T* { return pointer; } + + auto operator[](uint offset) -> T& { return pointer[offset]; } + auto operator[](uint offset) const -> const T& { return pointer[offset]; } + + auto data() -> T* { return pointer; } + auto data() const -> const T* { return pointer; } + + auto release() -> T* { + auto result = pointer; + pointer = nullptr; + return result; + } + + auto reset() -> void { + if(pointer) { + if(deleter) { + deleter(pointer); + } else { + delete[] pointer; + } + pointer = nullptr; + } + } + + auto swap(unique_pointer& target) -> void { + std::swap(pointer, target.pointer); + std::swap(deleter, target.deleter); + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/utility.hpp b/roms/snes-test-roms/bass-untech/nall/utility.hpp new file mode 100644 index 00000000..717da4e3 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/utility.hpp @@ -0,0 +1,29 @@ +#pragma once + +#include + +namespace nall { + +using std::tuple; + +template struct base_from_member { + base_from_member(T value) : value(value) {} + T value; +}; + +template struct castable { + operator To&() { return (To&)value; } + operator const To&() const { return (const To&)value; } + operator With&() { return value; } + operator const With&() const { return value; } + auto& operator=(const With& value) { return this->value = value; } + With value; +}; + +template inline auto allocate(uint size, const T& value) -> T* { + T* array = new T[size]; + for(uint i = 0; i < size; i++) array[i] = value; + return array; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/variant.hpp b/roms/snes-test-roms/bass-untech/nall/variant.hpp new file mode 100644 index 00000000..b08e3359 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/variant.hpp @@ -0,0 +1,148 @@ +#pragma once + +namespace nall { + +template struct variant_size { + static constexpr uint size = max(sizeof(T), variant_size::size); +}; + +template struct variant_size { + static constexpr uint size = sizeof(T); +}; + +template struct variant_index { + static constexpr uint index = is_same_v ? Index : variant_index::index; +}; + +template struct variant_index { + static constexpr uint index = is_same_v ? Index : 0; +}; + +template struct variant_copy { + constexpr variant_copy(uint index, uint assigned, void* target, void* source) { + if(index == assigned) new(target) T(*((T*)source)); + else variant_copy(index + 1, assigned, target, source); + } +}; + +template struct variant_copy { + constexpr variant_copy(uint index, uint assigned, void* target, void* source) { + if(index == assigned) new(target) T(*((T*)source)); + } +}; + +template struct variant_move { + constexpr variant_move(uint index, uint assigned, void* target, void* source) { + if(index == assigned) new(target) T(move(*((T*)source))); + else variant_move(index + 1, assigned, target, source); + } +}; + +template struct variant_move { + constexpr variant_move(uint index, uint assigned, void* target, void* source) { + if(index == assigned) new(target) T(move(*((T*)source))); + } +}; + +template struct variant_destruct { + constexpr variant_destruct(uint index, uint assigned, void* data) { + if(index == assigned) ((T*)data)->~T(); + else variant_destruct(index + 1, assigned, data); + } +}; + +template struct variant_destruct { + constexpr variant_destruct(uint index, uint assigned, void* data) { + if(index == assigned) ((T*)data)->~T(); + } +}; + +template struct variant_equals { + constexpr auto operator()(uint index, uint assigned) const -> bool { + if(index == assigned) return is_same_v; + return variant_equals()(index + 1, assigned); + } +}; + +template struct variant_equals { + constexpr auto operator()(uint index, uint assigned) const -> bool { + if(index == assigned) return is_same_v; + return false; + } +}; + +template struct variant final { //final as destructor is not virtual + variant() : assigned(0) {} + variant(const variant& source) { operator=(source); } + variant(variant&& source) { operator=(move(source)); } + template variant(const T& value) { operator=(value); } + template variant(T&& value) { operator=(move(value)); } + ~variant() { reset(); } + + explicit operator bool() const { return assigned; } + template explicit constexpr operator T&() { return get(); } + template explicit constexpr operator const T&() const { return get(); } + + template constexpr auto is() const -> bool { + return variant_equals()(1, assigned); + } + + template constexpr auto get() -> T& { + static_assert(variant_index<1, T, P...>::index, "type not in variant"); + struct variant_bad_cast{}; + if(!is()) throw variant_bad_cast{}; + return *((T*)data); + } + + template constexpr auto get() const -> const T& { + static_assert(variant_index<1, T, P...>::index, "type not in variant"); + struct variant_bad_cast{}; + if(!is()) throw variant_bad_cast{}; + return *((const T*)data); + } + + template constexpr auto get(const T& fallback) const -> const T& { + if(!is()) return fallback; + return *((const T*)data); + } + + auto reset() -> void { + if(assigned) variant_destruct(1, assigned, (void*)data); + assigned = 0; + } + + auto& operator=(const variant& source) { + reset(); + if(assigned = source.assigned) variant_copy(1, source.assigned, (void*)data, (void*)source.data); + return *this; + } + + auto& operator=(variant&& source) { + reset(); + if(assigned = source.assigned) variant_move(1, source.assigned, (void*)data, (void*)source.data); + source.assigned = 0; + return *this; + } + + template auto& operator=(const T& value) { + static_assert(variant_index<1, T, P...>::index, "type not in variant"); + reset(); + new((void*)&data) T(value); + assigned = variant_index<1, T, P...>::index; + return *this; + } + + template auto& operator=(T&& value) { + static_assert(variant_index<1, T, P...>::index, "type not in variant"); + reset(); + new((void*)&data) T(move(value)); + assigned = variant_index<1, T, P...>::index; + return *this; + } + +private: + alignas(P...) char data[variant_size::size]; + uint assigned; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/varint.hpp b/roms/snes-test-roms/bass-untech/nall/varint.hpp new file mode 100644 index 00000000..39785074 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/varint.hpp @@ -0,0 +1,122 @@ +#pragma once + +#include +#include +#include + +namespace nall { + +struct varint { + virtual auto read() -> uint8_t = 0; + virtual auto write(uint8_t) -> void = 0; + + auto readvu() -> uintmax { + uintmax data = 0, shift = 1; + while(true) { + uint8_t x = read(); + data += (x & 0x7f) * shift; + if(x & 0x80) break; + shift <<= 7; + data += shift; + } + return data; + } + + auto readvs() -> intmax { + uintmax data = readvu(); + bool negate = data & 1; + data >>= 1; + if(negate) data = ~data; + return data; + } + + auto writevu(uintmax data) -> void { + while(true) { + uint8_t x = data & 0x7f; + data >>= 7; + if(data == 0) return write(0x80 | x); + write(x); + data--; + } + } + + auto writevs(intmax data) -> void { + bool negate = data < 0; + if(negate) data = ~data; + data = (data << 1) | negate; + writevu(data); + } +}; + +struct VariadicNatural { + VariadicNatural() : mask(~0ull) { assign(0); } + template VariadicNatural(const T& value) : mask(~0ull) { assign(value); } + + operator uint64_t() const { return data; } + template auto& operator=(const T& value) { return assign(value); } + + auto operator++(int) { auto value = data; assign(data + 1); return value; } + auto operator--(int) { auto value = data; assign(data - 1); return value; } + + auto& operator++() { return assign(data + 1); } + auto& operator--() { return assign(data - 1); } + + auto& operator &=(const uint64_t value) { return assign(data & value); } + auto& operator |=(const uint64_t value) { return assign(data | value); } + auto& operator ^=(const uint64_t value) { return assign(data ^ value); } + auto& operator<<=(const uint64_t value) { return assign(data << value); } + auto& operator>>=(const uint64_t value) { return assign(data >> value); } + auto& operator +=(const uint64_t value) { return assign(data + value); } + auto& operator -=(const uint64_t value) { return assign(data - value); } + auto& operator *=(const uint64_t value) { return assign(data * value); } + auto& operator /=(const uint64_t value) { return assign(data / value); } + auto& operator %=(const uint64_t value) { return assign(data % value); } + + auto resize(uint bits) { + assert(bits <= 64); + mask = ~0ull >> (64 - bits); + data &= mask; + } + + auto serialize(serializer& s) { + s(data); + s(mask); + } + + struct Reference { + Reference(VariadicNatural& self, uint lo, uint hi) : self(self), Lo(lo), Hi(hi) {} + + operator uint64_t() const { + const uint64_t RangeBits = Hi - Lo + 1; + const uint64_t RangeMask = (((1ull << RangeBits) - 1) << Lo) & self.mask; + return (self & RangeMask) >> Lo; + } + + auto& operator=(const uint64_t value) { + const uint64_t RangeBits = Hi - Lo + 1; + const uint64_t RangeMask = (((1ull << RangeBits) - 1) << Lo) & self.mask; + self.data = (self.data & ~RangeMask) | ((value << Lo) & RangeMask); + return *this; + } + + private: + VariadicNatural& self; + const uint Lo; + const uint Hi; + }; + + auto bits(uint lo, uint hi) -> Reference { return {*this, lo < hi ? lo : hi, hi > lo ? hi : lo}; } + auto bit(uint index) -> Reference { return {*this, index, index}; } + auto byte(uint index) -> Reference { return {*this, index * 8 + 0, index * 8 + 7}; } + +private: + auto assign(uint64_t value) -> VariadicNatural& { + data = value & mask; + return *this; + } + + uint64_t data; + uint64_t mask; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector.hpp b/roms/snes-test-roms/bass-untech/nall/vector.hpp new file mode 100644 index 00000000..2f951355 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector.hpp @@ -0,0 +1,156 @@ +#pragma once + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +namespace nall { + +template +struct vector_base { + using type = vector_base; + + //core.hpp + vector_base() = default; + vector_base(const initializer_list& values); + vector_base(const type& source); + vector_base(type&& source); + ~vector_base(); + + explicit operator bool() const; + operator array_span(); + operator array_view() const; + template auto capacity() const -> uint64_t; + template auto size() const -> uint64_t; + template auto data() -> Cast*; + template auto data() const -> const Cast*; + + //assign.hpp + auto operator=(const type& source) -> type&; + auto operator=(type&& source) -> type&; + + //compare.hpp + auto operator==(const type& source) const -> bool; + auto operator!=(const type& source) const -> bool; + + //memory.hpp + auto reset() -> void; + auto acquire(const T* data, uint64_t size, uint64_t capacity = 0) -> void; + auto release() -> T*; + + auto reserveLeft(uint64_t capacity) -> bool; + auto reserveRight(uint64_t capacity) -> bool; + auto reserve(uint64_t capacity) -> bool { return reserveRight(capacity); } + + auto reallocateLeft(uint64_t size) -> bool; + auto reallocateRight(uint64_t size) -> bool; + auto reallocate(uint64_t size) -> bool { return reallocateRight(size); } + + auto resizeLeft(uint64_t size, const T& value = T()) -> bool; + auto resizeRight(uint64_t size, const T& value = T()) -> bool; + auto resize(uint64_t size, const T& value = T()) -> bool { return resizeRight(size, value); } + + //access.hpp + auto operator[](uint64_t offset) -> T&; + auto operator[](uint64_t offset) const -> const T&; + + auto operator()(uint64_t offset) -> T&; + auto operator()(uint64_t offset, const T& value) const -> const T&; + + auto left() -> T&; + auto first() -> T& { return left(); } + auto left() const -> const T&; + auto first() const -> const T& { return left(); } + + auto right() -> T&; + auto last() -> T& { return right(); } + auto right() const -> const T&; + auto last() const -> const T& { return right(); } + + //modify.hpp + auto prepend(const T& value) -> void; + auto prepend(T&& value) -> void; + auto prepend(const type& values) -> void; + auto prepend(type&& values) -> void; + + auto append(const T& value) -> void; + auto append(T&& value) -> void; + auto append(const type& values) -> void; + auto append(type&& values) -> void; + + auto insert(uint64_t offset, const T& value) -> void; + + auto removeLeft(uint64_t length = 1) -> void; + auto removeFirst(uint64_t length = 1) -> void { return removeLeft(length); } + auto removeRight(uint64_t length = 1) -> void; + auto removeLast(uint64_t length = 1) -> void { return removeRight(length); } + auto remove(uint64_t offset, uint64_t length = 1) -> void; + auto removeByIndex(uint64_t offset) -> bool; + auto removeByValue(const T& value) -> bool; + + auto takeLeft() -> T; + auto takeFirst() -> T { return move(takeLeft()); } + auto takeRight() -> T; + auto takeLast() -> T { return move(takeRight()); } + auto take(uint64_t offset) -> T; + + //iterator.hpp + auto begin() -> iterator { return {data(), 0}; } + auto end() -> iterator { return {data(), size()}; } + + auto begin() const -> iterator_const { return {data(), 0}; } + auto end() const -> iterator_const { return {data(), size()}; } + + auto rbegin() -> reverse_iterator { return {data(), size() - 1}; } + auto rend() -> reverse_iterator { return {data(), (uint64_t)-1}; } + + auto rbegin() const -> reverse_iterator_const { return {data(), size() - 1}; } + auto rend() const -> reverse_iterator_const { return {data(), (uint64_t)-1}; } + + //utility.hpp + auto fill(const T& value = {}) -> void; + auto sort(const function& comparator = [](auto& lhs, auto& rhs) { return lhs < rhs; }) -> void; + auto reverse() -> void; + auto find(const function& comparator) -> maybe; + auto find(const T& value) const -> maybe; + auto findSorted(const T& value) const -> maybe; + auto foreach(const function& callback) -> void; + auto foreach(const function& callback) -> void; + +protected: + T* _pool = nullptr; //pointer to first initialized element in pool + uint64_t _size = 0; //number of initialized elements in pool + uint64_t _left = 0; //number of allocated elements free on the left of pool + uint64_t _right = 0; //number of allocated elements free on the right of pool +}; + +} + +#define vector vector_base +#include +#include +#include +#include +#include +#include +#include +#include +#undef vector + +namespace nall { + template struct vector : vector_base { + using vector_base::vector_base; + }; +} + +#include diff --git a/roms/snes-test-roms/bass-untech/nall/vector/access.hpp b/roms/snes-test-roms/bass-untech/nall/vector/access.hpp new file mode 100644 index 00000000..62f44fb0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/access.hpp @@ -0,0 +1,47 @@ +#pragma once + +namespace nall { + +template auto vector::operator[](uint64_t offset) -> T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(offset >= size()) throw out_of_bounds{}; + #endif + return _pool[offset]; +} + +template auto vector::operator[](uint64_t offset) const -> const T& { + #ifdef DEBUG + struct out_of_bounds {}; + if(offset >= size()) throw out_of_bounds{}; + #endif + return _pool[offset]; +} + +template auto vector::operator()(uint64_t offset) -> T& { + while(offset >= size()) append(T()); + return _pool[offset]; +} + +template auto vector::operator()(uint64_t offset, const T& value) const -> const T& { + if(offset >= size()) return value; + return _pool[offset]; +} + +template auto vector::left() -> T& { + return _pool[0]; +} + +template auto vector::left() const -> const T& { + return _pool[0]; +} + +template auto vector::right() -> T& { + return _pool[_size - 1]; +} + +template auto vector::right() const -> const T& { + return _pool[_size - 1]; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/assign.hpp b/roms/snes-test-roms/bass-untech/nall/vector/assign.hpp new file mode 100644 index 00000000..2d66149c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/assign.hpp @@ -0,0 +1,28 @@ +#pragma once + +namespace nall { + +template auto vector::operator=(const vector& source) -> vector& { + if(this == &source) return *this; + _pool = memory::allocate(source._size); + _size = source._size; + _left = 0; + _right = 0; + for(uint64_t n : range(_size)) new(_pool + n) T(source._pool[n]); + return *this; +} + +template auto vector::operator=(vector&& source) -> vector& { + if(this == &source) return *this; + _pool = source._pool; + _size = source._size; + _left = source._left; + _right = source._right; + source._pool = nullptr; + source._size = 0; + source._left = 0; + source._right = 0; + return *this; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/compare.hpp b/roms/snes-test-roms/bass-untech/nall/vector/compare.hpp new file mode 100644 index 00000000..e2ef4b7b --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/compare.hpp @@ -0,0 +1,18 @@ +#pragma once + +namespace nall { + +template auto vector::operator==(const vector& source) const -> bool { + if(this == &source) return true; + if(size() != source.size()) return false; + for(uint64_t n = 0; n < size(); n++) { + if(operator[](n) != source[n]) return false; + } + return true; +} + +template auto vector::operator!=(const vector& source) const -> bool { + return !operator==(source); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/core.hpp b/roms/snes-test-roms/bass-untech/nall/vector/core.hpp new file mode 100644 index 00000000..a332928e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/core.hpp @@ -0,0 +1,50 @@ +#pragma once + +namespace nall { + +template vector::vector(const initializer_list& values) { + reserveRight(values.size()); + for(auto& value : values) append(value); +} + +template vector::vector(const vector& source) { + operator=(source); +} + +template vector::vector(vector&& source) { + operator=(move(source)); +} + +template vector::~vector() { + reset(); +} + +template vector::operator bool() const { + return _size; +} + +template vector::operator array_span() { + return {data(), size()}; +} + +template vector::operator array_view() const { + return {data(), size()}; +} + +template template auto vector::capacity() const -> uint64_t { + return (_left + _size + _right) * sizeof(T) / sizeof(Cast); +} + +template template auto vector::size() const -> uint64_t { + return _size * sizeof(T) / sizeof(Cast); +} + +template template auto vector::data() -> Cast* { + return (Cast*)_pool; +} + +template template auto vector::data() const -> const Cast* { + return (const Cast*)_pool; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/iterator.hpp b/roms/snes-test-roms/bass-untech/nall/vector/iterator.hpp new file mode 100644 index 00000000..67afb01a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/iterator.hpp @@ -0,0 +1,57 @@ +#pragma once + +namespace nall { + +template +struct vector_iterator { + vector_iterator(vector& self, uint64_t offset) : self(self), offset(offset) {} + auto operator*() -> T& { return self.operator[](offset); } + auto operator->() -> T* { return self.operator[](offset); } + auto operator!=(const vector_iterator& source) const -> bool { return offset != source.offset; } + auto operator++() -> vector_iterator& { return offset++, *this; } + +private: + vector& self; + uint64_t offset; +}; + +template +struct vector_iterator_const { + vector_iterator_const(const vector& self, uint64_t offset) : self(self), offset(offset) {} + auto operator*() -> const T& { return self.operator[](offset); } + auto operator->() -> T* { return self.operator[](offset); } + auto operator!=(const vector_iterator_const& source) const -> bool { return offset != source.offset; } + auto operator++() -> vector_iterator_const& { return offset++, *this; } + +private: + const vector& self; + uint64_t offset; +}; + +template +struct vector_reverse_iterator { + vector_reverse_iterator(vector& self, uint64_t offset) : self(self), offset(offset) {} + auto operator*() -> T& { return self.operator[](offset); } + auto operator->() -> T* { return self.operator[](offset); } + auto operator!=(const vector_reverse_iterator& source) const -> bool { return offset != source.offset; } + auto operator++() -> vector_reverse_iterator& { return offset--, *this; } + +private: + vector& self; + uint64_t offset; +}; + +template +struct vector_reverse_iterator_const { + vector_reverse_iterator_const(const vector& self, uint64_t offset) : self(self), offset(offset) {} + auto operator*() -> const T& { return self.operator[](offset); } + auto operator->() -> T* { return self.operator[](offset); } + auto operator!=(const vector_reverse_iterator_const& source) const -> bool { return offset != source.offset; } + auto operator++() -> vector_reverse_iterator_const& { return offset--, *this; } + +private: + const vector& self; + uint64_t offset; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/memory.hpp b/roms/snes-test-roms/bass-untech/nall/vector/memory.hpp new file mode 100644 index 00000000..15d7dd4f --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/memory.hpp @@ -0,0 +1,147 @@ +#pragma once + +namespace nall { + +//nall::vector acts internally as a deque (double-ended queue) +//it does this because it's essentially free to do so, only costing an extra integer in sizeof(vector) + +template auto vector::reset() -> void { + if(!_pool) return; + + for(uint64_t n : range(_size)) _pool[n].~T(); + memory::free(_pool - _left); + + _pool = nullptr; + _size = 0; + _left = 0; + _right = 0; +} + +//acquire ownership of allocated memory + +template auto vector::acquire(const T* data, uint64_t size, uint64_t capacity) -> void { + reset(); + _pool = data; + _size = size; + _left = 0; + _right = capacity ? capacity : size; +} + +//release ownership of allocated memory + +template auto vector::release() -> T* { + auto pool = _pool; + _pool = nullptr; + _size = 0; + _left = 0; + _right = 0; + return pool; +} + +//reserve allocates memory for objects, but does not initialize them +//when the vector desired size is known, this can be used to avoid growing the capacity dynamically +//reserve will not actually shrink the capacity, only expand it +//shrinking the capacity would destroy objects, and break amortized growth with reallocate and resize + +template auto vector::reserveLeft(uint64_t capacity) -> bool { + if(_size + _left >= capacity) return false; + + uint64_t left = bit::round(capacity); + auto pool = memory::allocate(left + _right) + (left - _size); + for(uint64_t n : range(_size)) new(pool + n) T(move(_pool[n])); + memory::free(_pool - _left); + + _pool = pool; + _left = left - _size; + + return true; +} + +template auto vector::reserveRight(uint64_t capacity) -> bool { + if(_size + _right >= capacity) return false; + + uint64_t right = bit::round(capacity); + auto pool = memory::allocate(_left + right) + _left; + for(uint64_t n : range(_size)) new(pool + n) T(move(_pool[n])); + memory::free(_pool - _left); + + _pool = pool; + _right = right - _size; + + return true; +} + +//reallocation is meant for POD types, to avoid the overhead of initialization +//do not use with non-POD types, or they will not be properly constructed or destructed + +template auto vector::reallocateLeft(uint64_t size) -> bool { + if(size < _size) { //shrink + _pool += _size - size; + _left += _size - size; + _size = size; + return true; + } + if(size > _size) { //grow + reserveLeft(size); + _pool -= size - _size; + _left -= size - _size; + _size = size; + return true; + } + return false; +} + +template auto vector::reallocateRight(uint64_t size) -> bool { + if(size < _size) { //shrink + _right += _size - size; + _size = size; + return true; + } + if(size > _size) { //grow + reserveRight(size); + _right -= size - _size; + _size = size; + return true; + } + return false; +} + +//resize is meant for non-POD types, and will properly construct objects + +template auto vector::resizeLeft(uint64_t size, const T& value) -> bool { + if(size < _size) { //shrink + for(uint64_t n : range(_size - size)) _pool[n].~T(); + _pool += _size - size; + _left += _size - size; + _size = size; + return true; + } + if(size > _size) { //grow + reserveLeft(size); + _pool -= size - _size; + for(uint64_t n : nall::reverse(range(size - _size))) new(_pool + n) T(value); + _left -= size - _size; + _size = size; + return true; + } + return false; +} + +template auto vector::resizeRight(uint64_t size, const T& value) -> bool { + if(size < _size) { //shrink + for(uint64_t n : range(size, _size)) _pool[n].~T(); + _right += _size - size; + _size = size; + return true; + } + if(size > _size) { //grow + reserveRight(size); + for(uint64_t n : range(_size, size)) new(_pool + n) T(value); + _right -= size - _size; + _size = size; + return true; + } + return false; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/modify.hpp b/roms/snes-test-roms/bass-untech/nall/vector/modify.hpp new file mode 100644 index 00000000..3386125e --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/modify.hpp @@ -0,0 +1,137 @@ +#pragma once + +namespace nall { + +template auto vector::prepend(const T& value) -> void { + reserveLeft(size() + 1); + new(--_pool) T(value); + _left--; + _size++; +} + +template auto vector::prepend(T&& value) -> void { + reserveLeft(size() + 1); + new(--_pool) T(move(value)); + _left--; + _size++; +} + +template auto vector::prepend(const vector& values) -> void { + reserveLeft(size() + values.size()); + _pool -= values.size(); + for(uint64_t n : range(values)) new(_pool + n) T(values[n]); + _left -= values.size(); + _size += values.size(); +} + +template auto vector::prepend(vector&& values) -> void { + reserveLeft(size() + values.size()); + _pool -= values.size(); + for(uint64_t n : range(values)) new(_pool + n) T(move(values[n])); + _left -= values.size(); + _size += values.size(); +} + +// + +template auto vector::append(const T& value) -> void { + reserveRight(size() + 1); + new(_pool + _size) T(value); + _right--; + _size++; +} + +template auto vector::append(T&& value) -> void { + reserveRight(size() + 1); + new(_pool + _size) T(move(value)); + _right--; + _size++; +} + +template auto vector::append(const vector& values) -> void { + reserveRight(size() + values.size()); + for(uint64_t n : range(values.size())) new(_pool + _size + n) T(values[n]); + _right -= values.size(); + _size += values.size(); +} + +template auto vector::append(vector&& values) -> void { + reserveRight(size() + values.size()); + for(uint64_t n : range(values.size())) new(_pool + _size + n) T(move(values[n])); + _right -= values.size(); + _size += values.size(); +} + +// + +template auto vector::insert(uint64_t offset, const T& value) -> void { + if(offset == 0) return prepend(value); + if(offset == size() - 1) return append(value); + reserveRight(size() + 1); + _size++; + for(int64_t n = size() - 1; n > offset; n--) { + _pool[n] = move(_pool[n - 1]); + } + new(_pool + offset) T(value); +} + +// + +template auto vector::removeLeft(uint64_t length) -> void { + if(length > size()) length = size(); + resizeLeft(size() - length); +} + +template auto vector::removeRight(uint64_t length) -> void { + if(length > size()) length = size(); + resizeRight(size() - length); +} + +template auto vector::remove(uint64_t offset, uint64_t length) -> void { + if(offset == 0) return removeLeft(length); + if(offset == size() - 1) return removeRight(length); + + for(uint64_t n = offset; n < size(); n++) { + if(n + length < size()) { + _pool[n] = move(_pool[n + length]); + } else { + _pool[n].~T(); + } + } + _size -= length; +} + +template auto vector::removeByIndex(uint64_t index) -> bool { + if(index < size()) return remove(index), true; + return false; +} + +template auto vector::removeByValue(const T& value) -> bool { + if(auto index = find(value)) return remove(*index), true; + return false; +} + +// + +template auto vector::takeLeft() -> T { + T value = move(_pool[0]); + removeLeft(); + return value; +} + +template auto vector::takeRight() -> T { + T value = move(_pool[size() - 1]); + removeRight(); + return value; +} + +template auto vector::take(uint64_t offset) -> T { + if(offset == 0) return takeLeft(); + if(offset == size() - 1) return takeRight(); + + T value = move(_pool[offset]); + remove(offset); + return value; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/specialization/uint8_t.hpp b/roms/snes-test-roms/bass-untech/nall/vector/specialization/uint8_t.hpp new file mode 100644 index 00000000..8ec5cadb --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/specialization/uint8_t.hpp @@ -0,0 +1,38 @@ +#pragma once + +namespace nall { + +template<> struct vector : vector_base { + using type = vector; + using vector_base::vector_base; + + template auto appendl(U value, uint size) -> void { + for(uint byte : range(size)) append(uint8_t(value >> byte * 8)); + } + + template auto appendm(U value, uint size) -> void { + for(uint byte : nall::reverse(range(size))) append(uint8_t(value >> byte * 8)); + } + + //note: string_view is not declared here yet ... + auto appends(array_view memory) -> void { + for(uint8_t byte : memory) append(byte); + } + + template auto readl(int offset, uint size) -> U { + if(offset < 0) offset = this->size() - abs(offset); + U value = 0; + for(uint byte : range(size)) value |= (U)operator[](offset + byte) << byte * 8; + return value; + } + + auto view(uint offset, uint length) -> array_view { + #ifdef DEBUG + struct out_of_bounds {}; + if(offset + length >= size()) throw out_of_bounds{}; + #endif + return {data() + offset, length}; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vector/utility.hpp b/roms/snes-test-roms/bass-untech/nall/vector/utility.hpp new file mode 100644 index 00000000..635f52ee --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vector/utility.hpp @@ -0,0 +1,47 @@ +#pragma once + +namespace nall { + +template auto vector::fill(const T& value) -> void { + for(uint64_t n : range(size())) _pool[n] = value; +} + +template auto vector::sort(const function& comparator) -> void { + nall::sort(_pool, _size, comparator); +} + +template auto vector::reverse() -> void { + vector reversed; + for(uint64_t n : range(size())) reversed.prepend(_pool[n]); + operator=(move(reversed)); +} + +template auto vector::find(const function& comparator) -> maybe { + for(uint64_t n : range(size())) if(comparator(_pool[n])) return n; + return nothing; +} + +template auto vector::find(const T& value) const -> maybe { + for(uint64_t n : range(size())) if(_pool[n] == value) return n; + return nothing; +} + +template auto vector::findSorted(const T& value) const -> maybe { + int64_t l = 0, r = size() - 1; + while(l <= r) { + int64_t m = l + (r - l >> 1); + if(value == _pool[m]) return m; + value < _pool[m] ? r = m - 1 : l = m + 1; + } + return nothing; +} + +template auto vector::foreach(const function& callback) -> void { + for(uint64_t n : range(size())) callback(_pool[n]); +} + +template auto vector::foreach(const function& callback) -> void { + for(uint64_t n : range(size())) callback(n, _pool[n]); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vfs.hpp b/roms/snes-test-roms/bass-untech/nall/vfs.hpp new file mode 100644 index 00000000..80396785 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vfs.hpp @@ -0,0 +1,3 @@ +#pragma once + +#include diff --git a/roms/snes-test-roms/bass-untech/nall/vfs/cdrom.hpp b/roms/snes-test-roms/bass-untech/nall/vfs/cdrom.hpp new file mode 100644 index 00000000..77ee126c --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vfs/cdrom.hpp @@ -0,0 +1,153 @@ +#pragma once + +#include +#include +#include +#include +#include +#include + +namespace nall::vfs { + +struct cdrom : file { + static auto open(const string& cueLocation) -> shared_pointer { + auto instance = shared_pointer{new cdrom}; + if(instance->load(cueLocation)) return instance; + return {}; + } + + auto size() const -> uintmax override { + return _image.size(); + } + + auto offset() const -> uintmax override { + return _offset; + } + + auto seek(intmax offset, index mode) -> void override { + if(mode == index::absolute) _offset = (uintmax)offset; + if(mode == index::relative) _offset += (intmax)offset; + } + + auto read() -> uint8_t override { + if(_offset >= _image.size()) return 0x00; + return _image[_offset++]; + } + + auto write(uint8_t data) -> void override { + //CD-ROMs are read-only; but allow writing anyway if needed, since the image is in memory + if(_offset >= _image.size()) return; + _image[_offset++] = data; + } + +private: + auto load(const string& cueLocation) -> bool { + Decode::CUE cuesheet; + if(!cuesheet.load(cueLocation)) return false; + + CD::Session session; + session.leadIn.lba = -LeadInSectors; + session.leadIn.end = -1; + int lbaDisc = Track1Pregap; + int endDisc = lbaDisc; + for(auto& file : cuesheet.files) { + for(auto& track : file.tracks) { + session.tracks[track.number].control = track.type == "audio" ? 0b0000 : 0b0100; + session.tracks[track.number].address = 0b0001; + for(auto& index : track.indices) { + session.tracks[track.number].indices[index.number].lba = lbaDisc + index.lba; + session.tracks[track.number].indices[index.number].end = lbaDisc + index.end; + } + } + lbaDisc += file.tracks.last().indices.last().end + 1; + endDisc = lbaDisc; + } + session.leadOut.lba = endDisc; + session.leadOut.end = endDisc + LeadOutSectors - 1; + + for(uint track : range(100)) { + if(!session.tracks[track]) continue; + session.firstTrack = track; + for(uint index : range(100)) { + if(!session.tracks[track].indices[index]) continue; + session.tracks[track].firstIndex = index; + break; + } + break; + } + + for(uint track : reverse(range(100))) { + if(!session.tracks[track]) continue; + session.lastTrack = track; + for(uint index : reverse(range(100))) { + if(!session.tracks[track].indices[index]) continue; + session.tracks[track].lastIndex = index; + break; + } + break; + } + + session.tracks[1].indices[0].lba = 0; //track 1, index 0 is not present in CUE files + session.tracks[1].indices[0].end = Track1Pregap - 1; + + _image.resize(2448 * (LeadInSectors + endDisc + LeadOutSectors)); + + lbaDisc = Track1Pregap; + for(auto& file : cuesheet.files) { + auto location = string{Location::path(cueLocation), file.name}; + auto filedata = nall::file::open(location, nall::file::mode::read); + if(file.type == "wave") filedata.seek(44); //skip RIFF header + uint64_t offset = 0; + for(auto& track : file.tracks) { + for(auto& index : track.indices) { + for(int sector : range(index.sectorCount())) { + auto target = _image.data() + 2448ull * (LeadInSectors + lbaDisc + index.lba + sector); + auto length = track.sectorSize(); + if(length == 2048) { + //ISO: generate header + parity data + memory::assign(target + 0, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff); //sync + memory::assign(target + 6, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00); //sync + auto [minute, second, frame] = CD::MSF(lbaDisc + index.lba + sector); + target[12] = CD::BCD::encode(minute); + target[13] = CD::BCD::encode(second); + target[14] = CD::BCD::encode(frame); + target[15] = 0x01; //mode + filedata.read({target + 16, length}); + CD::RSPC::encodeMode1({target, 2352}); + } + if(length == 2352) { + //BIN + WAV: direct copy + filedata.read({target, length}); + } + } + } + offset += track.sectorSize() * track.sectorCount(); + } + lbaDisc += file.tracks.last().indices.last().end + 1; + } + + auto subchannel = session.encode(LeadInSectors + session.leadOut.end + 1); + if(auto overlay = nall::file::read({Location::notsuffix(cueLocation), ".sub"})) { + auto target = subchannel.data() + 96 * (LeadInSectors + Track1Pregap); + auto length = (int64_t)subchannel.size() - 96 * (LeadInSectors + Track1Pregap); + memory::copy(target, length, overlay.data(), overlay.size()); + } + + for(uint64_t sector : range(size() / 2448)) { + auto source = subchannel.data() + sector * 96; + auto target = _image.data() + sector * 2448 + 2352; + memory::copy(target, source, 96); + } + + return true; + } + + vector _image; + uintmax _offset = 0; + + static constexpr int LeadInSectors = 7500; + static constexpr int Track1Pregap = 150; + static constexpr int LeadOutSectors = 6750; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vfs/disk.hpp b/roms/snes-test-roms/bass-untech/nall/vfs/disk.hpp new file mode 100644 index 00000000..a88bab90 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vfs/disk.hpp @@ -0,0 +1,51 @@ +#pragma once + +#include + +namespace nall::vfs { + +struct disk : file { + static auto open(string location_, mode mode_) -> shared_pointer { + auto instance = shared_pointer{new disk}; + if(!instance->_open(location_, mode_)) return {}; + return instance; + } + + auto size() const -> uintmax override { + return _fp.size(); + } + + auto offset() const -> uintmax override { + return _fp.offset(); + } + + auto seek(intmax offset_, index index_) -> void override { + _fp.seek(offset_, (uint)index_); + } + + auto read() -> uint8_t override { + return _fp.read(); + } + + auto write(uint8_t data_) -> void override { + _fp.write(data_); + } + + auto flush() -> void override { + _fp.flush(); + } + +private: + disk() = default; + disk(const disk&) = delete; + auto operator=(const disk&) -> disk& = delete; + + auto _open(string location_, mode mode_) -> bool { + if(!_fp.open(location_, (uint)mode_)) return false; + return true; + } + + file_buffer _fp; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vfs/memory.hpp b/roms/snes-test-roms/bass-untech/nall/vfs/memory.hpp new file mode 100644 index 00000000..2235fc45 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vfs/memory.hpp @@ -0,0 +1,67 @@ +#pragma once + +#include +#include + +namespace nall::vfs { + +struct memory : file { + ~memory() { delete[] _data; } + + static auto open(const void* data, uintmax size) -> shared_pointer { + auto instance = shared_pointer{new memory}; + instance->_open((const uint8_t*)data, size); + return instance; + } + + static auto open(string location, bool decompress = false) -> shared_pointer { + auto instance = shared_pointer{new memory}; + if(decompress && location.iendsWith(".zip")) { + Decode::ZIP archive; + if(archive.open(location) && archive.file.size() == 1) { + auto memory = archive.extract(archive.file.first()); + instance->_open(memory.data(), memory.size()); + return instance; + } + } + auto memory = nall::file::read(location); + instance->_open(memory.data(), memory.size()); + return instance; + } + + auto data() const -> const uint8_t* { return _data; } + auto size() const -> uintmax override { return _size; } + auto offset() const -> uintmax override { return _offset; } + + auto seek(intmax offset, index mode) -> void override { + if(mode == index::absolute) _offset = (uintmax)offset; + if(mode == index::relative) _offset += (intmax)offset; + } + + auto read() -> uint8_t override { + if(_offset >= _size) return 0x00; + return _data[_offset++]; + } + + auto write(uint8_t data) -> void override { + if(_offset >= _size) return; + _data[_offset++] = data; + } + +private: + memory() = default; + memory(const file&) = delete; + auto operator=(const memory&) -> memory& = delete; + + auto _open(const uint8_t* data, uintmax size) -> void { + _size = size; + _data = new uint8_t[size]; + nall::memory::copy(_data, data, size); + } + + uint8_t* _data = nullptr; + uintmax _size = 0; + uintmax _offset = 0; +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/vfs/vfs.hpp b/roms/snes-test-roms/bass-untech/nall/vfs/vfs.hpp new file mode 100644 index 00000000..9f02b0ae --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/vfs/vfs.hpp @@ -0,0 +1,72 @@ +#pragma once + +#include +#include + +namespace nall::vfs { + +struct file { + enum class mode : uint { read, write, modify, create }; + enum class index : uint { absolute, relative }; + + virtual ~file() = default; + + virtual auto size() const -> uintmax = 0; + virtual auto offset() const -> uintmax = 0; + + virtual auto seek(intmax offset, index = index::absolute) -> void = 0; + virtual auto read() -> uint8_t = 0; + virtual auto write(uint8_t data) -> void = 0; + virtual auto flush() -> void {} + + auto end() const -> bool { + return offset() >= size(); + } + + auto read(void* vdata, uintmax bytes) -> void { + auto data = (uint8_t*)vdata; + while(bytes--) *data++ = read(); + } + + auto readl(uint bytes) -> uintmax { + uintmax data = 0; + for(auto n : range(bytes)) data |= (uintmax)read() << n * 8; + return data; + } + + auto readm(uint bytes) -> uintmax { + uintmax data = 0; + for(auto n : range(bytes)) data = data << 8 | read(); + return data; + } + + auto reads() -> string { + string s; + s.resize(size()); + read(s.get(), s.size()); + return s; + } + + auto write(const void* vdata, uintmax bytes) -> void { + auto data = (const uint8_t*)vdata; + while(bytes--) write(*data++); + } + + auto writel(uintmax data, uint bytes) -> void { + for(auto n : range(bytes)) write(data), data >>= 8; + } + + auto writem(uintmax data, uint bytes) -> void { + for(auto n : reverse(range(bytes))) write(data >> n * 8); + } + + auto writes(const string& s) -> void { + write(s.data(), s.size()); + } +}; + +} + +#include +#include +#include diff --git a/roms/snes-test-roms/bass-untech/nall/view.hpp b/roms/snes-test-roms/bass-untech/nall/view.hpp new file mode 100644 index 00000000..ce874ce4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/view.hpp @@ -0,0 +1,7 @@ +#pragma once + +namespace nall { + +template struct view; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/detour.hpp b/roms/snes-test-roms/bass-untech/nall/windows/detour.hpp new file mode 100644 index 00000000..7bd05e96 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/detour.hpp @@ -0,0 +1,189 @@ +#pragma once + +#include +#include +#include +#include +#include + +namespace nall { + +#define Copy 0 +#define RelNear 1 + +struct detour { + static auto insert(const string& moduleName, const string& functionName, void*& source, void* target) -> bool; + static auto remove(const string& moduleName, const string& functionName, void*& source) -> bool; + +protected: + static auto length(const uint8* function) -> uint; + static auto mirror(uint8* target, const uint8* source) -> uint; + + struct opcode { + uint16 prefix; + uint length; + uint mode; + uint16 modify; + }; + static opcode opcodes[]; +}; + +//TODO: +//* fs:, gs: should force another opcode copy +//* conditional branches within +5-byte range should fail +detour::opcode detour::opcodes[] = { + {0x50, 1}, //push eax + {0x51, 1}, //push ecx + {0x52, 1}, //push edx + {0x53, 1}, //push ebx + {0x54, 1}, //push esp + {0x55, 1}, //push ebp + {0x56, 1}, //push esi + {0x57, 1}, //push edi + {0x58, 1}, //pop eax + {0x59, 1}, //pop ecx + {0x5a, 1}, //pop edx + {0x5b, 1}, //pop ebx + {0x5c, 1}, //pop esp + {0x5d, 1}, //pop ebp + {0x5e, 1}, //pop esi + {0x5f, 1}, //pop edi + {0x64, 1}, //fs: + {0x65, 1}, //gs: + {0x68, 5}, //push dword + {0x6a, 2}, //push byte + {0x74, 2, RelNear, 0x0f84}, //je near -> je far + {0x75, 2, RelNear, 0x0f85}, //jne near -> jne far + {0x89, 2}, //mov reg,reg + {0x8b, 2}, //mov reg,reg + {0x90, 1}, //nop + {0xa1, 5}, //mov eax,[dword] + {0xeb, 2, RelNear, 0xe9}, //jmp near -> jmp far +}; + +inline auto detour::insert(const string& moduleName, const string& functionName, void*& source, void* target) -> bool { + HMODULE module = GetModuleHandleW(utf16_t(moduleName)); + if(!module) return false; + + uint8* sourceData = (uint8_t*)GetProcAddress(module, functionName); + if(!sourceData) return false; + + uint sourceLength = detour::length(sourceData); + if(sourceLength < 5) { + //unable to clone enough bytes to insert hook + #if 1 + string output = {"detour::insert(", moduleName, "::", functionName, ") failed: "}; + for(uint n = 0; n < 16; n++) output.append(hex<2>(sourceData[n]), " "); + output.trimRight(" ", 1L); + MessageBoxA(0, output, "nall::detour", MB_OK); + #endif + return false; + } + + auto mirrorData = new uint8[512](); + detour::mirror(mirrorData, sourceData); + + DWORD privileges; + VirtualProtect((void*)mirrorData, 512, PAGE_EXECUTE_READWRITE, &privileges); + VirtualProtect((void*)sourceData, 256, PAGE_EXECUTE_READWRITE, &privileges); + uint64_t address = (uint64_t)target - ((uint64_t)sourceData + 5); + sourceData[0] = 0xe9; //jmp target + sourceData[1] = address >> 0; + sourceData[2] = address >> 8; + sourceData[3] = address >> 16; + sourceData[4] = address >> 24; + VirtualProtect((void*)sourceData, 256, privileges, &privileges); + + source = (void*)mirrorData; + return true; +} + +inline auto detour::remove(const string& moduleName, const string& functionName, void*& source) -> bool { + HMODULE module = GetModuleHandleW(utf16_t(moduleName)); + if(!module) return false; + + auto sourceData = (uint8*)GetProcAddress(module, functionName); + if(!sourceData) return false; + + auto mirrorData = (uint8*)source; + if(mirrorData == sourceData) return false; //hook was never installed + + uint length = detour::length(256 + mirrorData); + if(length < 5) return false; + + DWORD privileges; + VirtualProtect((void*)sourceData, 256, PAGE_EXECUTE_READWRITE, &privileges); + for(uint n = 0; n < length; n++) sourceData[n] = mirrorData[256 + n]; + VirtualProtect((void*)sourceData, 256, privileges, &privileges); + + source = (void*)sourceData; + delete[] mirrorData; + return true; +} + +inline auto detour::length(const uint8* function) -> uint { + uint length = 0; + while(length < 5) { + detour::opcode *opcode = 0; + foreach(op, detour::opcodes) { + if(function[length] == op.prefix) { + opcode = &op; + break; + } + } + if(opcode == 0) break; + length += opcode->length; + } + return length; +} + +inline auto detour::mirror(uint8* target, const uint8* source) -> uint { + const uint8* entryPoint = source; + for(uint n = 0; n < 256; n++) target[256 + n] = source[n]; + + uint size = detour::length(source); + while(size) { + detour::opcode* opcode = nullptr; + foreach(op, detour::opcodes) { + if(*source == op.prefix) { + opcode = &op; + break; + } + } + + switch(opcode->mode) { + case Copy: + for(uint n = 0; n < opcode->length; n++) *target++ = *source++; + break; + case RelNear: { + source++; + uint64_t sourceAddress = (uint64_t)source + 1 + (int8)*source; + *target++ = opcode->modify; + if(opcode->modify >> 8) *target++ = opcode->modify >> 8; + uint64_t targetAddress = (uint64_t)target + 4; + uint64_t address = sourceAddress - targetAddress; + *target++ = address >> 0; + *target++ = address >> 8; + *target++ = address >> 16; + *target++ = address >> 24; + source += 2; + } break; + } + + size -= opcode->length; + } + + uint64_t address = (entryPoint + detour::length(entryPoint)) - (target + 5); + *target++ = 0xe9; //jmp entryPoint + *target++ = address >> 0; + *target++ = address >> 8; + *target++ = address >> 16; + *target++ = address >> 24; + + return source - entryPoint; +} + +#undef Implied +#undef RelNear + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/guard.hpp b/roms/snes-test-roms/bass-untech/nall/windows/guard.hpp new file mode 100644 index 00000000..353874cb --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/guard.hpp @@ -0,0 +1,34 @@ +#ifndef NALL_WINDOWS_GUARD_HPP +#define NALL_WINDOWS_GUARD_HPP + +#define boolean WindowsBoolean +#define interface WindowsInterface + +#undef UNICODE +#undef WINVER +#undef WIN32_LEAN_AND_LEAN +#undef _WIN32_WINNT +#undef _WIN32_IE +#undef __MSVCRT_VERSION__ +#undef NOMINMAX +#undef PATH_MAX + +#define UNICODE +#define WINVER 0x0601 +#define WIN32_LEAN_AND_MEAN +#define _WIN32_WINNT WINVER +#define _WIN32_IE WINVER +#define __MSVCRT_VERSION__ WINVER +#define NOMINMAX +#define PATH_MAX 260 + +#else +#undef NALL_WINDOWS_GUARD_HPP + +#undef boolean +#undef interface + +#undef far +#undef near + +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/windows/guid.hpp b/roms/snes-test-roms/bass-untech/nall/windows/guid.hpp new file mode 100644 index 00000000..7c3ae2a4 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/guid.hpp @@ -0,0 +1,17 @@ +#pragma once + +#include + +namespace nall { + +inline auto guid() -> string { + GUID guidInstance; + CoCreateGuid(&guidInstance); + + wchar_t guidString[39]; + StringFromGUID2(guidInstance, guidString, 39); + + return (char*)utf8_t(guidString); +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/launcher.hpp b/roms/snes-test-roms/bass-untech/nall/windows/launcher.hpp new file mode 100644 index 00000000..e0d8b702 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/launcher.hpp @@ -0,0 +1,91 @@ +#pragma once + +namespace nall { + +//launch a new process and inject specified DLL into it + +inline auto launch(const char* applicationName, const char* libraryName, uint32 entryPoint) -> bool { + //if a launcher does not send at least one message, a wait cursor will appear + PostThreadMessage(GetCurrentThreadId(), WM_USER, 0, 0); + MSG msg; + GetMessage(&msg, 0, 0, 0); + + STARTUPINFOW si; + PROCESS_INFORMATION pi; + + memset(&si, 0, sizeof(STARTUPINFOW)); + BOOL result = CreateProcessW( + utf16_t(applicationName), GetCommandLineW(), NULL, NULL, TRUE, + DEBUG_PROCESS | DEBUG_ONLY_THIS_PROCESS, //do not break if application creates its own processes + NULL, NULL, &si, &pi + ); + if(result == false) return false; + + uint8 entryData[1024], entryHook[1024] = { + 0x68, 0x00, 0x00, 0x00, 0x00, //push libraryName + 0xb8, 0x00, 0x00, 0x00, 0x00, //mov eax,LoadLibraryW + 0xff, 0xd0, //call eax + 0xcd, 0x03, //int 3 + }; + + entryHook[1] = (uint8)((entryPoint + 14) >> 0); + entryHook[2] = (uint8)((entryPoint + 14) >> 8); + entryHook[3] = (uint8)((entryPoint + 14) >> 16); + entryHook[4] = (uint8)((entryPoint + 14) >> 24); + + auto pLoadLibraryW = (uint32)GetProcAddress(GetModuleHandleW(L"kernel32"), "LoadLibraryW"); + entryHook[6] = pLoadLibraryW >> 0; + entryHook[7] = pLoadLibraryW >> 8; + entryHook[8] = pLoadLibraryW >> 16; + entryHook[9] = pLoadLibraryW >> 24; + + utf16_t buffer = utf16_t(libraryName); + memcpy(entryHook + 14, buffer, 2 * wcslen(buffer) + 2); + + while(true) { + DEBUG_EVENT event; + WaitForDebugEvent(&event, INFINITE); + + if(event.dwDebugEventCode == EXIT_PROCESS_DEBUG_EVENT) break; + + if(event.dwDebugEventCode == EXCEPTION_DEBUG_EVENT) { + if(event.u.Exception.ExceptionRecord.ExceptionCode == EXCEPTION_BREAKPOINT) { + if(event.u.Exception.ExceptionRecord.ExceptionAddress == (void*)(entryPoint + 14 - 1)) { + HANDLE hProcess = OpenProcess(0, FALSE, event.dwProcessId); + HANDLE hThread = OpenThread(THREAD_ALL_ACCESS, FALSE, event.dwThreadId); + + CONTEXT context; + context.ContextFlags = CONTEXT_FULL; + GetThreadContext(hThread, &context); + + WriteProcessMemory(pi.hProcess, (void*)entryPoint, (void*)&entryData, sizeof entryData, NULL); + context.Eip = entryPoint; + SetThreadContext(hThread, &context); + + CloseHandle(hThread); + CloseHandle(hProcess); + } + + ContinueDebugEvent(event.dwProcessId, event.dwThreadId, DBG_CONTINUE); + continue; + } + + ContinueDebugEvent(event.dwProcessId, event.dwThreadId, DBG_EXCEPTION_NOT_HANDLED); + continue; + } + + if(event.dwDebugEventCode == CREATE_PROCESS_DEBUG_EVENT) { + ReadProcessMemory(pi.hProcess, (void*)entryPoint, (void*)&entryData, sizeof entryData, NULL); + WriteProcessMemory(pi.hProcess, (void*)entryPoint, (void*)&entryHook, sizeof entryHook, NULL); + + ContinueDebugEvent(event.dwProcessId, event.dwThreadId, DBG_CONTINUE); + continue; + } + + ContinueDebugEvent(event.dwProcessId, event.dwThreadId, DBG_CONTINUE); + } + + return true; +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/registry.hpp b/roms/snes-test-roms/bass-untech/nall/windows/registry.hpp new file mode 100644 index 00000000..96bbb328 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/registry.hpp @@ -0,0 +1,119 @@ +#pragma once + +#include +#include + +#include +#undef interface +#ifndef KEY_WOW64_64KEY + #define KEY_WOW64_64KEY 0x0100 +#endif +#ifndef KEY_WOW64_32KEY + #define KEY_WOW64_32KEY 0x0200 +#endif + +#ifndef NWR_FLAGS + #define NWR_FLAGS KEY_WOW64_64KEY +#endif + +#ifndef NWR_SIZE + #define NWR_SIZE 4096 +#endif + +namespace nall { + +struct registry { + static auto exists(const string& name) -> bool { + auto part = name.split("\\"); + HKEY handle, rootKey = root(part.takeLeft()); + string node = part.takeRight(); + string path = part.merge("\\"); + if(RegOpenKeyExW(rootKey, utf16_t(path), 0, NWR_FLAGS | KEY_READ, &handle) == ERROR_SUCCESS) { + wchar_t data[NWR_SIZE] = L""; + DWORD size = NWR_SIZE * sizeof(wchar_t); + LONG result = RegQueryValueExW(handle, utf16_t(node), nullptr, nullptr, (LPBYTE)&data, (LPDWORD)&size); + RegCloseKey(handle); + if(result == ERROR_SUCCESS) return true; + } + return false; + } + + static auto read(const string& name) -> string { + auto part = name.split("\\"); + HKEY handle, rootKey = root(part.takeLeft()); + string node = part.takeRight(); + string path = part.merge("\\"); + if(RegOpenKeyExW(rootKey, utf16_t(path), 0, NWR_FLAGS | KEY_READ, &handle) == ERROR_SUCCESS) { + wchar_t data[NWR_SIZE] = L""; + DWORD size = NWR_SIZE * sizeof(wchar_t); + LONG result = RegQueryValueExW(handle, utf16_t(node), nullptr, nullptr, (LPBYTE)&data, (LPDWORD)&size); + RegCloseKey(handle); + if(result == ERROR_SUCCESS) return (const char*)utf8_t(data); + } + return ""; + } + + static auto write(const string& name, const string& data = "") -> void { + auto part = name.split("\\"); + HKEY handle, rootKey = root(part.takeLeft()); + string node = part.takeRight(), path; + DWORD disposition; + for(uint n = 0; n < part.size(); n++) { + path.append(part[n]); + if(RegCreateKeyExW(rootKey, utf16_t(path), 0, nullptr, 0, NWR_FLAGS | KEY_ALL_ACCESS, nullptr, &handle, &disposition) == ERROR_SUCCESS) { + if(n == part.size() - 1) { + RegSetValueExW(handle, utf16_t(node), 0, REG_SZ, (BYTE*)(wchar_t*)utf16_t(data), (data.length() + 1) * sizeof(wchar_t)); + } + RegCloseKey(handle); + } + path.append("\\"); + } + } + + static auto remove(const string& name) -> bool { + auto part = name.split("\\"); + HKEY rootKey = root(part.takeLeft()); + string node = part.takeRight(); + string path = part.merge("\\"); + if(!node) return SHDeleteKeyW(rootKey, utf16_t(path)) == ERROR_SUCCESS; + return SHDeleteValueW(rootKey, utf16_t(path), utf16_t(node)) == ERROR_SUCCESS; + } + + static auto contents(const string& name) -> vector { + vector result; + auto part = name.split("\\"); + HKEY handle, rootKey = root(part.takeLeft()); + part.removeRight(); + string path = part.merge("\\"); + if(RegOpenKeyExW(rootKey, utf16_t(path), 0, NWR_FLAGS | KEY_READ, &handle) == ERROR_SUCCESS) { + DWORD folders, nodes; + RegQueryInfoKey(handle, nullptr, nullptr, nullptr, &folders, nullptr, nullptr, &nodes, nullptr, nullptr, nullptr, nullptr); + for(uint n = 0; n < folders; n++) { + wchar_t name[NWR_SIZE] = L""; + DWORD size = NWR_SIZE * sizeof(wchar_t); + RegEnumKeyEx(handle, n, (wchar_t*)&name, &size, nullptr, nullptr, nullptr, nullptr); + result.append(string{(const char*)utf8_t(name), "\\"}); + } + for(uint n = 0; n < nodes; n++) { + wchar_t name[NWR_SIZE] = L""; + DWORD size = NWR_SIZE * sizeof(wchar_t); + RegEnumValueW(handle, n, (wchar_t*)&name, &size, nullptr, nullptr, nullptr, nullptr); + result.append((const char*)utf8_t(name)); + } + RegCloseKey(handle); + } + return result; + } + +private: + static auto root(const string& name) -> HKEY { + if(name == "HKCR") return HKEY_CLASSES_ROOT; + if(name == "HKCC") return HKEY_CURRENT_CONFIG; + if(name == "HKCU") return HKEY_CURRENT_USER; + if(name == "HKLM") return HKEY_LOCAL_MACHINE; + if(name == "HKU" ) return HKEY_USERS; + return nullptr; + } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/service.hpp b/roms/snes-test-roms/bass-untech/nall/windows/service.hpp new file mode 100644 index 00000000..fa5d87f9 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/service.hpp @@ -0,0 +1,13 @@ +#pragma once + +namespace nall { + +struct service { + explicit operator bool() const { return false; } + auto command(const string& name, const string& command) -> bool { return false; } + auto receive() -> string { return ""; } + auto name() const -> string { return ""; } + auto stop() const -> bool { return false; } +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/shared-memory.hpp b/roms/snes-test-roms/bass-untech/nall/windows/shared-memory.hpp new file mode 100644 index 00000000..aa74a70a --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/shared-memory.hpp @@ -0,0 +1,27 @@ +#pragma once + +namespace nall { + +struct shared_memory { + shared_memory() = default; + shared_memory(const shared_memory&) = delete; + auto operator=(const shared_memory&) -> shared_memory& = delete; + + ~shared_memory() { + reset(); + } + + explicit operator bool() const { return false; } + auto empty() const -> bool { return true; } + auto size() const -> uint { return 0; } + auto acquired() const -> bool { return false; } + auto acquire() -> uint8_t* { return nullptr; } + auto release() -> void {} + auto reset() -> void {} + auto create(const string& name, uint size) -> bool { return false; } + auto remove() -> void {} + auto open(const string& name, uint size) -> bool { return false; } + auto close() -> void {} +}; + +} diff --git a/roms/snes-test-roms/bass-untech/nall/windows/utf8.hpp b/roms/snes-test-roms/bass-untech/nall/windows/utf8.hpp new file mode 100644 index 00000000..98d98fef --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/windows/utf8.hpp @@ -0,0 +1,86 @@ +#pragma once + +using uint = unsigned; + +namespace nall { + //UTF-8 to UTF-16 + struct utf16_t { + utf16_t(const char* s = "") { operator=(s); } + ~utf16_t() { reset(); } + + utf16_t(const utf16_t&) = delete; + auto operator=(const utf16_t&) -> utf16_t& = delete; + + auto operator=(const char* s) -> utf16_t& { + reset(); + if(!s) s = ""; + length = MultiByteToWideChar(CP_UTF8, 0, s, -1, nullptr, 0); + buffer = new wchar_t[length + 1]; + MultiByteToWideChar(CP_UTF8, 0, s, -1, buffer, length); + buffer[length] = 0; + return *this; + } + + operator wchar_t*() { return buffer; } + operator const wchar_t*() const { return buffer; } + + auto reset() -> void { + delete[] buffer; + length = 0; + } + + auto data() -> wchar_t* { return buffer; } + auto data() const -> const wchar_t* { return buffer; } + + auto size() const -> uint { return length; } + + private: + wchar_t* buffer = nullptr; + uint length = 0; + }; + + //UTF-16 to UTF-8 + struct utf8_t { + utf8_t(const wchar_t* s = L"") { operator=(s); } + ~utf8_t() { reset(); } + + utf8_t(const utf8_t&) = delete; + auto operator=(const utf8_t&) -> utf8_t& = delete; + + auto operator=(const wchar_t* s) -> utf8_t& { + reset(); + if(!s) s = L""; + length = WideCharToMultiByte(CP_UTF8, 0, s, -1, nullptr, 0, nullptr, nullptr); + buffer = new char[length + 1]; + WideCharToMultiByte(CP_UTF8, 0, s, -1, buffer, length, nullptr, nullptr); + buffer[length] = 0; + return *this; + } + + auto reset() -> void { + delete[] buffer; + length = 0; + } + + operator char*() { return buffer; } + operator const char*() const { return buffer; } + + auto data() -> char* { return buffer; } + auto data() const -> const char* { return buffer; } + + auto size() const -> uint { return length; } + + private: + char* buffer = nullptr; + uint length = 0; + }; + + inline auto utf8_arguments(int& argc, char**& argv) -> void { + wchar_t** wargv = CommandLineToArgvW(GetCommandLineW(), &argc); + argv = new char*[argc + 1](); + for(uint i = 0; i < argc; i++) { + argv[i] = new char[PATH_MAX]; + strcpy(argv[i], nall::utf8_t(wargv[i])); + } + } +} diff --git a/roms/snes-test-roms/bass-untech/nall/xorg/clipboard.hpp b/roms/snes-test-roms/bass-untech/nall/xorg/clipboard.hpp new file mode 100644 index 00000000..03dc5af0 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/xorg/clipboard.hpp @@ -0,0 +1,14 @@ +#pragma once + +#include + +namespace nall::Clipboard { + +inline auto clear() -> void { + XDisplay display; + if(auto atom = XInternAtom(display, "CLIPBOARD", XlibTrue)) { + XSetSelectionOwner(display, atom, XlibNone, XlibCurrentTime); + } +} + +} diff --git a/roms/snes-test-roms/bass-untech/nall/xorg/guard.hpp b/roms/snes-test-roms/bass-untech/nall/xorg/guard.hpp new file mode 100644 index 00000000..2ff49b75 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/xorg/guard.hpp @@ -0,0 +1,51 @@ +#ifndef NALL_XORG_GUARD_HPP +#define NALL_XORG_GUARD_HPP + +#define Atom XlibAtom +#define Display XlibDisplay +#define Font XlibFont +#define Screen XlibScreen +#define Window XlibWindow + +#else +#undef NALL_XORG_GUARD_HPP + +#undef Atom +#undef Display +#undef Font +#undef Screen +#undef Window + +#undef Above +#undef Below +#undef Bool + +#ifndef NALL_XORG_GUARD_CONSTANTS +#define NALL_XORG_GUARD_CONSTANTS +enum XlibConstants : int { + XlibButton1 = Button1, + XlibButton2 = Button2, + XlibButton3 = Button3, + XlibButton4 = Button4, + XlibButton5 = Button5, + XlibCurrentTime = CurrentTime, + XlibFalse = False, + XlibNone = None, + XlibTrue = True, +}; +#endif + +#undef Button1 +#undef Button2 +#undef Button3 +#undef Button4 +#undef Button5 +#undef CurrentTime +#undef False +#undef None +#undef True + +#undef MAX +#undef MIN + +#endif diff --git a/roms/snes-test-roms/bass-untech/nall/xorg/xorg.hpp b/roms/snes-test-roms/bass-untech/nall/xorg/xorg.hpp new file mode 100644 index 00000000..b93eef05 --- /dev/null +++ b/roms/snes-test-roms/bass-untech/nall/xorg/xorg.hpp @@ -0,0 +1,18 @@ +#pragma once + +#include +#include +#include +#include +#include +#include +#include + +struct XDisplay { + XDisplay() { _display = XOpenDisplay(nullptr); } + ~XDisplay() { XCloseDisplay(_display); } + operator XlibDisplay*() const { return _display; } + +private: + XlibDisplay* _display; +}; diff --git a/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sfc b/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sfc new file mode 100644 index 00000000..1241d2e4 Binary files /dev/null and b/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sfc differ diff --git a/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sym b/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sym new file mode 100644 index 00000000..17a2eecc --- /dev/null +++ b/roms/snes-test-roms/bin/65816-examples/arguments-after-jsr.sym @@ -0,0 +1,61 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +00828000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +00828300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a WaitFrame +00808512 WaitFrame.Loop +0080851a NmiHandler +0080851e NmiHandler.FastRomNmiHandler +00808565 NmiHandler.VBlank.TextBuffer.VBlank.SkipCharBuffer +00808594 NmiHandler.VBlank.TextBuffer.VBlank.SkipAttrBuffer +00808594 NmiHandler.EndVBlankRoutine +008085a4 Main +008085e5 Main.MainLoop +0080861c PrintString_Word_LongIndexed +00818000 PrintString_Word_AddrIndexed__far +00808632 PrintString_Long_StackIndirect +0081801c PrintString_Long_StackIndirect__far +00808650 PrintString_Long_DpIndirectLong +0081803d PrintString_Long_DpIndirectLong__far +0080866d _TB_PrintString__far +00828600 HelloWorld +0082860e Resources.Palette diff --git a/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sfc b/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sfc new file mode 100644 index 00000000..3a9d23c8 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sfc differ diff --git a/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sym b/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sym new file mode 100644 index 00000000..4b3b4a0d --- /dev/null +++ b/roms/snes-test-roms/bin/effects/hdma-textbox-wipe.sym @@ -0,0 +1,48 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +00808647 SetupHdma.Loop +0080866b WaitFrame +00808673 WaitFrame.Loop +0080867b NmiHandler +0080867f NmiHandler.FastRomNmiHandler +008086a4 NmiHandler.EndVBlankRoutine +008086b4 Process +008086c5 Process.ShowTextboxAnimation +008086db Process.TextboxOpenWait +008086e8 Process.HideTextboxAnimation +008086f8 Process.TextboxClosedWait +00808706 SetupPpu +008087d5 Main +008087f7 Main.MainLoop +00808800 HdmaTable +00808807 Resources.Bg_Palette +00808907 Resources.Bg1_Tiles +00808ce7 Resources.Bg1_Tilemap +008094e7 Resources.Bg2_Tiles +008096c7 Resources.Bg2_Tilemap +00809ec7 Resources.Bg3_Tiles +0080a077 Resources.Bg3_Tilemap +0080a877 Resources.Obj_Tiles +0080a937 Resources.Obj_Palette +0080a94d Resources.Obj_Oam diff --git a/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sfc b/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sfc new file mode 100644 index 00000000..303be031 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sfc differ diff --git a/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sym b/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sym new file mode 100644 index 00000000..392c1b1d --- /dev/null +++ b/roms/snes-test-roms/bin/effects/inidisp_extend_vblank.sym @@ -0,0 +1,56 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupAndEnableIrqHandler +0080866a IRQ_EnableDisplay +0080868d IRQ_EnableMainScreen +008086b6 IRQ_VBlank +00808704 IRQ_VBlank.NoOverrun +0080870b WaitFrame +00808710 WaitFrame.Loop +00808717 Init +00808747 SetupPpu +008087b6 Process +008087f2 Process.SkipChangeTiles +00808805 VerticalBlank +00808858 Main +00808871 Main.MainLoop +00818000 Resources.ObjTiles.Block_1 +00828000 Resources.ObjTiles.Block_2 +00838000 Resources.ObjTiles.Block_3 +00848000 Resources.ObjTiles.Block_4 +00858000 Resources.ObjTiles.Block_5 +00868000 Resources.ObjTiles.Block_6 +00878000 Resources.ObjTiles.Block_7 +00888000 Resources.ObjTiles.Block_8 +00898000 Resources.ObjTiles.Block_9 +008a8000 Resources.ObjTiles.Block_10 +008b8000 Resources.ObjTiles.Block_11 +008c8000 Resources.ObjTiles.Block_12 +008d8000 Resources.ObjTiles.Block_13 +008e8000 Resources.ObjTiles.Block_14 +008f8000 Resources.ObjTiles.Block_15 +00808879 Resources.Obj_Palette +00808899 Resources.InitialOamBuffer +00808989 Resources.Bg1_Palette +0080898d Resources.Bg1_Tiles +008089cd Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sfc b/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sfc new file mode 100644 index 00000000..ca03ca94 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sfc differ diff --git a/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sym b/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sym new file mode 100644 index 00000000..a267c9cf --- /dev/null +++ b/roms/snes-test-roms/bin/effects/inidisp_fadein_fadeout.sym @@ -0,0 +1,42 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 NmiHandler +00808648 NmiHandler.FastRomNmiHandler +00808670 NmiHandler.EndVBlankRoutine +00808680 WaitFrame +00808693 FadeInTransition +00808695 FadeInTransition.Loop +008086ad FadeToForceBlank +008086af FadeToForceBlank.Loop +008086cd WaitOneSecond +008086cf WaitOneSecond.Loop +008086d8 LoadImage_Map +00808709 LoadImage_Game +0080873a Main +0080875f Main.MainLoop +00808779 Resources.MapImage_Tiles +00808cf9 Resources.MapImage_Tilemap +008094f9 Resources.MapImage_Palette +00809519 Resources.GameImage_Tiles +00809ab9 Resources.GameImage_Tilemap +0080a2b9 Resources.GameImage_Palette diff --git a/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sfc b/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sfc new file mode 100644 index 00000000..5805232e Binary files /dev/null and b/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sfc differ diff --git a/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sym b/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sym new file mode 100644 index 00000000..01da5cfc --- /dev/null +++ b/roms/snes-test-roms/bin/effects/repeating_hdma_pattern.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 NmiHandler +00808645 WaitFrame +00808657 Main +0080866e Main.Loop +00808679 WaveyCloudEffect__Setup +008086d8 HOffset_Table +008086fd WaveyCloudEffect__Process +00808735 WaveyCloudEffect__Process.Loop +0080875d HdmaTable_Pattern_A +00808773 HdmaTable_Pattern_B +00808789 WaveyCloudEffect__VBlank +008087c2 Resources.Clouds_Tilemap +00808fc2 Resources.Clouds_Tiles +008097c2 Resources.Clouds_Palette diff --git a/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sfc b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sfc new file mode 100644 index 00000000..337c00b6 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sym b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sym new file mode 100644 index 00000000..05b99a07 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sym @@ -0,0 +1,30 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Transfer1bppTilesToVram_0 +0080868e Main +008086ef Main.MainLoop +008086f2 NmiHandler +008086f3 Resources.ZeroByte +008086f4 Resources.Palette +008086fc Resources.Tiles_1bpp +0080879c Resources.Map diff --git a/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sfc b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sfc new file mode 100644 index 00000000..1d3dd7ef Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sym b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sym new file mode 100644 index 00000000..1d890a02 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sym @@ -0,0 +1,30 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Transfer1bppTilesToVram_1 +0080868e Main +008086ef Main.MainLoop +008086f2 NmiHandler +008086f3 Resources.FixedByteFF +008086f4 Resources.Palette +008086fc Resources.Tiles_1bpp +008087ac Resources.Map diff --git a/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sfc b/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sfc new file mode 100644 index 00000000..56d9b6d5 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sym b/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sym new file mode 100644 index 00000000..46e0fba6 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-horizontal-scrolling.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 InitColumnBuffer +00808656 DrawNextColumn +00808685 DrawNextColumn.Loop +0080869f WaitFrame +008086a7 WaitFrame.Loop +008086af NmiHandler +008086b3 NmiHandler.FastRomNmiHandler +0080870c NmiHandler.EndVBlankRoutine +0080871c Main +00808779 Main.InitialDrawLoop +00808787 Main.MainLoop +008087a4 Resources.Tiles +008087c4 Resources.Palette +008087d4 Map.Data diff --git a/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sfc b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sfc new file mode 100644 index 00000000..00feb5e4 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sym b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sym new file mode 100644 index 00000000..1215f24e --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sym @@ -0,0 +1,32 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +008086a5 NmiHandler.VBlank.NoTransfer +008086a5 NmiHandler.EndVBlankRoutine +008086b5 Main +00808759 Main.MainLoop +00808793 Resources.Palette +0080879d Resources.Mode7Tiles diff --git a/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sfc b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sfc new file mode 100644 index 00000000..cc6b5bfe Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sym b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sym new file mode 100644 index 00000000..6d158362 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sym @@ -0,0 +1,32 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +008086a5 NmiHandler.VBlank.NoTransfer +008086a5 NmiHandler.EndVBlankRoutine +008086b5 Main +00808759 Main.MainLoop +0080879c Resources.Palette +008087a6 Resources.Mode7Tiles diff --git a/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sfc b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sfc new file mode 100644 index 00000000..5809f0cd Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sym b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sym new file mode 100644 index 00000000..4a0e1559 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 InitTilemapRowTransfers +0080865c DrawNextTwoRows +00808686 DrawNextTwoRows.Loop +008086a3 WaitFrame +008086ab WaitFrame.Loop +008086b3 NmiHandler +008086b7 NmiHandler.FastRomNmiHandler +00808748 NmiHandler.EndVBlankRoutine +00808758 Main +008087b9 Main.InitialDrawLoop +008087d0 Main.MainLoop +008087f5 Resources.Tiles +00808815 Resources.Palette +0080882d Map.Data diff --git a/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sfc b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sfc new file mode 100644 index 00000000..2d33ac85 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sfc differ diff --git a/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sym b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sym new file mode 100644 index 00000000..017c3cf9 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/vmain-vertical-scrolling.sym @@ -0,0 +1,35 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 InitTilemapRowTransfers +00808660 QueueRowTransfer +0080868c WaitFrame +00808694 WaitFrame.Loop +0080869c NmiHandler +008086a0 NmiHandler.FastRomNmiHandler +00808720 NmiHandler.EndVBlankRoutine +00808730 Main +00808791 Main.InitialDrawLoop +008087a5 Main.MainLoop +008087ca Resources.Tiles +008087ea Resources.Palette +00808802 Map.Data diff --git a/roms/snes-test-roms/bin/effects/window-mask-logic.sfc b/roms/snes-test-roms/bin/effects/window-mask-logic.sfc new file mode 100644 index 00000000..de4a9510 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/window-mask-logic.sfc differ diff --git a/roms/snes-test-roms/bin/effects/window-mask-logic.sym b/roms/snes-test-roms/bin/effects/window-mask-logic.sym new file mode 100644 index 00000000..2e71d018 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/window-mask-logic.sym @@ -0,0 +1,71 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupPpu +00808573 WaitFrame +0080857b WaitFrame.Loop +00808583 NmiHandler +00808587 NmiHandler.FastRomNmiHandler +008085dd NmiHandler.VBlank.TextBuffer.VBlank.SkipCharBuffer +0080860c NmiHandler.VBlank.TextBuffer.VBlank.SkipAttrBuffer +00808635 NmiHandler.EndVBlankRoutine +00808645 Init +0080864b Init.FallThrough +0080864b UpdateWindowLogicAndText +00808710 Process +00808741 Process.ToggleOptionFlag +00808748 Main +00808759 Main.MainLoop +00808761 HdmaTables.Window1 +00808783 HdmaTables.Window2 +0080c600 Resources.Palette +0080c604 Strings.Header +0080c616 Strings.LogicMaskStringTable +0080c61e Strings.Mask0 +0080c621 Strings.Mask1 +0080c625 Strings.Mask2 +0080c629 Strings.Mask3 +0080c62e Strings.Invert +0080c636 Strings.Window1 +0080c63c Strings.Window2 +0080c642 Strings.Instructions diff --git a/roms/snes-test-roms/bin/effects/window-precalculated-single.sfc b/roms/snes-test-roms/bin/effects/window-precalculated-single.sfc new file mode 100644 index 00000000..2033ab55 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/window-precalculated-single.sfc differ diff --git a/roms/snes-test-roms/bin/effects/window-precalculated-single.sym b/roms/snes-test-roms/bin/effects/window-precalculated-single.sym new file mode 100644 index 00000000..34381d4a --- /dev/null +++ b/roms/snes-test-roms/bin/effects/window-precalculated-single.sym @@ -0,0 +1,58 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 HdmaBuffer_NextBuffer +00808654 HdmaBuffer_NextBuffer.Else +00808657 HdmaBuffer_NextBuffer.EndIf +0080865b TranslateSingleWindow.__GetNextBufferAndProcessYOffset +0080868b TranslateSingleWindow.__GetNextBufferAndProcessYOffset.YOffsetPositive +008086bd TranslateSingleWindow.__GetNextBufferAndProcessYOffset.YOffsetZero +008086c3 TranslateSingleWindow.__GetNextBufferAndProcessYOffset.EndIf +008086d1 TranslateSingleWindow.__GetNextBufferAndProcessYOffset.ReturnFalse_A16 +008086d3 TranslateSingleWindow.__GetNextBufferAndProcessYOffset.ReturnFalse_A8 +008086d5 TranslateSingleWindow.DrawWindowLeftOffset +008086d8 TranslateSingleWindow.DrawWindowLeftOffset.InvertedA +008086e2 TranslateSingleWindow.DrawWindowLeftOffset.EntryLoop +008086e9 TranslateSingleWindow.DrawWindowLeftOffset.Loop +008086fb TranslateSingleWindow.DrawWindowLeftOffset.WindowOnscreen +0080870d TranslateSingleWindow.DrawWindowLeftOffset.EndIf +0080871b TranslateSingleWindow.DrawWindowLeftOffset.Fallthrough +0080871b TranslateSingleWindow.__EndHdmaTable +00808731 TranslateSingleWindow.DrawWindowRightOffset +0080873b TranslateSingleWindow.DrawWindowRightOffset.EntryLoop +00808742 TranslateSingleWindow.DrawWindowRightOffset.Loop +00808754 TranslateSingleWindow.DrawWindowRightOffset.WindowOnscreen +00808764 TranslateSingleWindow.DrawWindowRightOffset.EndIf +00808774 TranslateSingleWindow.DrawWindow +00808780 TranslateSingleWindow.DrawWindow.XOffsetNegative +00808789 TranslateSingleWindow.DrawWindow.WindowOffscreen +00808794 WaitFrame +0080879c WaitFrame.Loop +008087a4 NmiHandler +008087a8 NmiHandler.FastRomNmiHandler +008087e0 NmiHandler.VBlank.HdmaBuffer_VBlank.EndIf_227_ +008087e0 NmiHandler.EndVBlankRoutine +008087f0 Main +00808856 Main.SpinLoop +00808877 Main.InvertXVelocity +008088a0 Main.InvertYVelocity +008088bb ExclamationMark diff --git a/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sfc b/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sfc new file mode 100644 index 00000000..2c3dfe16 Binary files /dev/null and b/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sfc differ diff --git a/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sym b/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sym new file mode 100644 index 00000000..b5ae45b7 --- /dev/null +++ b/roms/snes-test-roms/bin/effects/window-precalculated-symmetrical.sym @@ -0,0 +1,51 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 HdmaBuffer_NextBuffer +00808654 HdmaBuffer_NextBuffer.Else +00808657 HdmaBuffer_NextBuffer.EndIf +0080865b DrawSymmetricalWindow +00808688 DrawSymmetricalWindow.JumpToEndHdmaTable +0080868d DrawSymmetricalWindow.TopYPositive +008086bd DrawSymmetricalWindow.DrawBuffer +008086c3 DrawSymmetricalWindow.DrawBuffer__A +008086d8 DrawSymmetricalWindow.EntryLoop +008086df DrawSymmetricalWindow.Loop +00808706 DrawSymmetricalWindow.EndLoop +00808706 DrawSymmetricalWindow.EndHdmaTable +0080871c DrawSymmetricalWindow.CentreXIsOffscreenLeft +00808721 DrawSymmetricalWindow.CentreXIsOffscreenLeft.EntryLoop +00808728 DrawSymmetricalWindow.CentreXIsOffscreenLeft.Loop +0080874d DrawSymmetricalWindow.CentreXIsOffscreenRight +00808752 DrawSymmetricalWindow.CentreXIsOffscreenRight.EntryLoop +00808759 DrawSymmetricalWindow.CentreXIsOffscreenRight.Loop +00808780 WaitFrame +00808788 WaitFrame.Loop +00808790 NmiHandler +00808794 NmiHandler.FastRomNmiHandler +008087cc NmiHandler.VBlank.HdmaBuffer_VBlank.EndIf_202_ +008087cc NmiHandler.EndVBlankRoutine +008087dc Main +00808842 Main.SpinLoop +00808863 Main.InvertXVelocity +0080888c Main.InvertYVelocity +008088a7 Pawn diff --git a/roms/snes-test-roms/bin/effects/window-shapes-single.sfc b/roms/snes-test-roms/bin/effects/window-shapes-single.sfc new file mode 100644 index 00000000..905f8d0b Binary files /dev/null and b/roms/snes-test-roms/bin/effects/window-shapes-single.sfc differ diff --git a/roms/snes-test-roms/bin/effects/window-shapes-single.sym b/roms/snes-test-roms/bin/effects/window-shapes-single.sym new file mode 100644 index 00000000..82f309fa --- /dev/null +++ b/roms/snes-test-roms/bin/effects/window-shapes-single.sym @@ -0,0 +1,47 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +008086af NmiHandler.EndVBlankRoutine +008086bf Main +00808714 Main.TimerLoop +00808738 Main.ButtonLoop +0080874c Main.SkipPrevious +00808763 Main.SkipNext +00808768 HdmaTablesTable +00808784 LeftGreaterThanRight +00808947 RectangularWindow +00808951 TallRectangularWindow +0080895e Trapezium_0 +00808ad7 Trapezium_1 +00808b9e Trapezium_2 +00808c46 TriangleR_0 +00808dbf TriangleR_1 +00808f61 TriangleR_2 +00809076 TriangleR_3 +008091e8 TriangleR_4 +00809359 Octagon +00809429 MultipleShapes +00809530 Circle diff --git a/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sfc b/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sfc new file mode 100644 index 00000000..bea5cfd5 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sym b/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sym new file mode 100644 index 00000000..101e1e4e --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sym @@ -0,0 +1,35 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +0080865a WaitFrame +00808662 WaitFrame.Loop +0080866a NmiHandler +0080866e NmiHandler.FastRomNmiHandler +0080868d NmiHandler.EndVBlankRoutine +0080869d SetupPpu +008086e2 Main +00808704 Main.MainLoop +0080870a HdmaTable +0080871d Resources.Bg1_Palette +0080875d Resources.Bg1_Tiles +0080877d Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sfc b/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sfc new file mode 100644 index 00000000..27d8f1f0 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sym b/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sym new file mode 100644 index 00000000..47f76bcd --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sym @@ -0,0 +1,40 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +00808659 WaitFrame +00808661 WaitFrame.Loop +00808669 NmiHandler +0080866d NmiHandler.FastRomNmiHandler +0080869c NmiHandler.EndVBlankRoutine +008086ac GetNextScanlineArray +008086c1 SetupShearAnimation +008086c9 ProcessShearAnimation +008086e3 ProcessShearAnimation.Loop +00808703 SetupPpu +00808748 Main +00808772 Main.MainLoop +00808786 HdmaTable_A +0080878d HdmaTable_B +00808794 Resources.Bg1_Palette +008087d4 Resources.Bg1_Tiles +008090a4 Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sfc b/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sfc new file mode 100644 index 00000000..9259ab28 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sym b/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sym new file mode 100644 index 00000000..a53a48b2 --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-double-buffered-parallax.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +00808654 WaitFrame +0080865c WaitFrame.Loop +00808664 NmiHandler +00808668 NmiHandler.FastRomNmiHandler +00808697 NmiHandler.EndVBlankRoutine +008086a7 GetNextHdmaBuffer +008086bc BuildHdmaTable +008086f5 SetupPpu +0080873a Main +00808764 Main.MainLoop +00808783 Resources.Bg1_Palette +008087c3 Resources.Bg1_Tiles +008087e3 Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sfc b/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sfc new file mode 100644 index 00000000..a941c06f Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sym b/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sym new file mode 100644 index 00000000..83e85a31 --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-indirect-mapping.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +0080865f WaitFrame +00808667 WaitFrame.Loop +0080866f NmiHandler +00808673 NmiHandler.FastRomNmiHandler +00808692 NmiHandler.EndVBlankRoutine +008086a2 SetupPpu +008086e7 Main +00808709 Main.MainLoop +0080870f ContiguousArray +008088cf IndirectHdmaTable +008088d6 Resources.Bg1_Palette +00808916 Resources.Bg1_Tiles +00808936 Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sfc b/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sfc new file mode 100644 index 00000000..5147f358 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sym b/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sym new file mode 100644 index 00000000..399fd60a --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sym @@ -0,0 +1,36 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +0080865f WaitFrame +00808667 WaitFrame.Loop +0080866f NmiHandler +00808673 NmiHandler.FastRomNmiHandler +00808692 NmiHandler.EndVBlankRoutine +008086a2 SetupPpu +008086e7 Main +00808709 Main.MainLoop +0080870f SineTable +0080876f IndirectHdmaTable +0080877f Resources.Bg1_Palette +008087bf Resources.Bg1_Tiles +008087df Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sfc b/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sfc new file mode 100644 index 00000000..9c59bdbf Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sfc differ diff --git a/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sym b/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sym new file mode 100644 index 00000000..1c80d9f2 --- /dev/null +++ b/roms/snes-test-roms/bin/examples/hdma-repeat-entry.sym @@ -0,0 +1,35 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 SetupHdma +0080865a WaitFrame +00808662 WaitFrame.Loop +0080866a NmiHandler +0080866e NmiHandler.FastRomNmiHandler +0080868d NmiHandler.EndVBlankRoutine +0080869d SetupPpu +008086e2 Main +00808704 Main.MainLoop +0080870a HdmaTable +008088cd Resources.Bg1_Palette +0080890d Resources.Bg1_Tiles +0080892d Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/examples/hdma-to-cgram.sfc b/roms/snes-test-roms/bin/examples/hdma-to-cgram.sfc new file mode 100644 index 00000000..4a13a4d0 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/hdma-to-cgram.sfc differ diff --git a/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sfc b/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sfc new file mode 100644 index 00000000..9b8b6dd0 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sfc differ diff --git a/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sym b/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sym new file mode 100644 index 00000000..3a9c8cbb --- /dev/null +++ b/roms/snes-test-roms/bin/examples/textbuffer-hello-world.sym @@ -0,0 +1,54 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +00818000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +00818300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a WaitFrame +00808512 WaitFrame.Loop +0080851a NmiHandler +0080851e NmiHandler.FastRomNmiHandler +00808565 NmiHandler.VBlank.TextBuffer.VBlank.SkipCharBuffer +00808594 NmiHandler.VBlank.TextBuffer.VBlank.SkipAttrBuffer +00808594 NmiHandler.EndVBlankRoutine +008085a4 Main +008085e5 Main.MainLoop +00818600 Main.String_314_ +00808602 Resources.Palette diff --git a/roms/snes-test-roms/bin/examples/vram-writes-without-dma.sfc b/roms/snes-test-roms/bin/examples/vram-writes-without-dma.sfc new file mode 100644 index 00000000..71109d85 Binary files /dev/null and b/roms/snes-test-roms/bin/examples/vram-writes-without-dma.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sfc new file mode 100644 index 00000000..d603342a Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sym new file mode 100644 index 00000000..70568a9a --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sym @@ -0,0 +1,59 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +0080c600 SetupTest.String_288_ +0080c611 SetupTest.String_301_ +0080c61f SetupTest.String_314_ +0080c625 SetupTest.String_327_ +0080857a DoTest +00808591 DoTest._autoJoyTest._Loop_autoJoyStart +008085a6 DoTest._autoJoyTest._Loop_autoJoyEnd +008085be ProcessState +008085e3 UpdateAndPrintState +00808610 Main +00808646 Main.MainLoop +00808676 Main.TextBuffer.VBlank.SkipCharBuffer +008086a5 Main.TextBuffer.VBlank.SkipAttrBuffer +0080c629 TitleAndVersionStr +0080c64f Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sfc new file mode 100644 index 00000000..eedc6449 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sym new file mode 100644 index 00000000..24fd4e04 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sym @@ -0,0 +1,59 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +00808524 Test +00808530 Test.LoopUntilAutojoy +00808537 Test.StartTest +00808541 Test.TestOver +0080854d Test.PrintResults +0080c600 Test.String_286_ +008085bd Test.TextBuffer.VBlank.SkipCharBuffer +008085ec Test.TextBuffer.VBlank.SkipAttrBuffer +008085f2 BitString_0 +008085f4 BitString_1 +008085f6 PrintBit +00808603 Main +00808639 Main.MainLoop +0080c603 TitleAndVersionStr +0080c65e Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sfc new file mode 100644 index 00000000..30a84258 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sym new file mode 100644 index 00000000..f5a1148f --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +0080c600 SetupTest.String_285_ +0080853a PrintResults +0080c614 PrintResults.String_300_ +0080c616 PrintResults.String_309_ +0080c618 PrintResults.String_318_ +0080c61a PrintResults.String_327_ +008085c6 PrintResults.TextBuffer.VBlank.SkipCharBuffer +008085f5 PrintResults.TextBuffer.VBlank.SkipAttrBuffer +008085fd DoTest +008089b6 Main +008089ec Main.MainLoop +0080c61c TitleAndVersionStr +0080c65d Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sfc new file mode 100644 index 00000000..7f955c3d Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sym new file mode 100644 index 00000000..61b5f655 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c648 SetupTest.String_287_ +0080c65a SetupTest.String_300_ +0080c66a SetupTest.String_313_ +0080c66e SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867e Main +008086b4 Main.MainLoop +0080c676 TitleAndVersionStr +0080c6d1 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sfc new file mode 100644 index 00000000..3f73f7d2 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sym new file mode 100644 index 00000000..cf191865 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sym @@ -0,0 +1,132 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +0080c600 SetupTest.String_285_ +0080c606 SetupTest.String_298_ +0080c608 SetupTest.String_311_ +0080c60b SetupTest.String_324_ +0080c60f SetupTest.String_337_ +0080c613 SetupTest.String_350_ +0080c617 SetupTest.String_363_ +0080c61b SetupTest.String_376_ +0080c61f SetupTest.String_389_ +0080c623 SetupTest.String_402_ +0080c627 SetupTest.String_415_ +0080c634 SetupTest.String_428_ +0080861b Test0 +0080862a Test0.LoopUntilAutojoy +0080862e Test0.ClearAutoJoyEnableFlag +00808630 Test0.ReenableAutoJoy +00808632 Test0.PollHvbjoyLoop +0080863b Test0.PrintResults +008086af Test0.TextBuffer.VBlank.SkipCharBuffer +008086de Test0.TextBuffer.VBlank.SkipAttrBuffer +008086e4 Test1 +008086f3 Test1.LoopUntilAutojoy +008086f7 Test1.ClearAutoJoyEnableFlag +00808705 Test1.ReenableAutoJoy +00808707 Test1.PollHvbjoyLoop +00808710 Test1.PrintResults +00808784 Test1.TextBuffer.VBlank.SkipCharBuffer +008087b3 Test1.TextBuffer.VBlank.SkipAttrBuffer +008087b9 Test2 +008087c8 Test2.LoopUntilAutojoy +008087cc Test2.ClearAutoJoyEnableFlag +008087de Test2.ReenableAutoJoy +008087e0 Test2.PollHvbjoyLoop +008087e9 Test2.PrintResults +0080885d Test2.TextBuffer.VBlank.SkipCharBuffer +0080888c Test2.TextBuffer.VBlank.SkipAttrBuffer +00808892 Test3 +008088a1 Test3.LoopUntilAutojoy +008088a5 Test3.ClearAutoJoyEnableFlag +008088bf Test3.ReenableAutoJoy +008088c1 Test3.PollHvbjoyLoop +008088ca Test3.PrintResults +0080893e Test3.TextBuffer.VBlank.SkipCharBuffer +0080896d Test3.TextBuffer.VBlank.SkipAttrBuffer +00808973 Test4 +00808982 Test4.LoopUntilAutojoy +00808986 Test4.ClearAutoJoyEnableFlag +0080899d Test4.ReenableAutoJoy +0080899f Test4.PollHvbjoyLoop +008089a8 Test4.PrintResults +00808a1c Test4.TextBuffer.VBlank.SkipCharBuffer +00808a4b Test4.TextBuffer.VBlank.SkipAttrBuffer +00808a51 Test5 +00808a60 Test5.LoopUntilAutojoy +00808a64 Test5.ClearAutoJoyEnableFlag +00808a7f Test5.ReenableAutoJoy +00808a81 Test5.PollHvbjoyLoop +00808a8a Test5.PrintResults +00808afe Test5.TextBuffer.VBlank.SkipCharBuffer +00808b2d Test5.TextBuffer.VBlank.SkipAttrBuffer +00808b33 Test6 +00808b42 Test6.LoopUntilAutojoy +00808b46 Test6.ClearAutoJoyEnableFlag +00808b5e Test6.ReenableAutoJoy +00808b60 Test6.PollHvbjoyLoop +00808b69 Test6.PrintResults +00808bdd Test6.TextBuffer.VBlank.SkipCharBuffer +00808c0c Test6.TextBuffer.VBlank.SkipAttrBuffer +00808c12 Test7 +00808c21 Test7.LoopUntilAutojoy +00808c25 Test7.ClearAutoJoyEnableFlag +00808c3e Test7.ReenableAutoJoy +00808c40 Test7.PollHvbjoyLoop +00808c49 Test7.PrintResults +00808cbd Test7.TextBuffer.VBlank.SkipCharBuffer +00808cec Test7.TextBuffer.VBlank.SkipAttrBuffer +00808cf2 Test8 +00808d01 Test8.LoopUntilAutojoy +00808d05 Test8.ClearAutoJoyEnableFlag +00808d1f Test8.ReenableAutoJoy +00808d21 Test8.PollHvbjoyLoop +00808d2a Test8.PrintResults +00808d9e Test8.TextBuffer.VBlank.SkipCharBuffer +00808dcd Test8.TextBuffer.VBlank.SkipAttrBuffer +00808dd3 Main +00808e09 Main.MainLoop +0080c640 TitleAndVersionStr +0080c697 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sfc new file mode 100644 index 00000000..b6fe6e71 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sym new file mode 100644 index 00000000..452a2765 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c65a SetupTest.String_287_ +0080c66c SetupTest.String_300_ +0080c67c SetupTest.String_313_ +0080c680 SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867c Main +008086b2 Main.MainLoop +0080c688 TitleAndVersionStr +0080c6de Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sfc new file mode 100644 index 00000000..d12c2964 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sym new file mode 100644 index 00000000..5d96bddb --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sym @@ -0,0 +1,53 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +0080c600 SetupTest.String_283_ +00808538 Test +0080856e Test.PrintResults +008085be Test.TextBuffer.VBlank.SkipCharBuffer +008085ed Test.TextBuffer.VBlank.SkipAttrBuffer +008085f3 Main +00808629 Main.MainLoop +0080c60d TitleAndVersionStr +0080c668 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sfc new file mode 100644 index 00000000..c8ebb45d Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sym new file mode 100644 index 00000000..001ee89c --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c636 SetupTest.String_287_ +0080c648 SetupTest.String_300_ +0080c658 SetupTest.String_313_ +0080c65c SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867c Main +008086b2 Main.MainLoop +0080c664 TitleAndVersionStr +0080c6b0 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sfc new file mode 100644 index 00000000..7aace593 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sym new file mode 100644 index 00000000..85abf690 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sym @@ -0,0 +1,317 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a SetupTest +0080c600 SetupTest.String_285_ +0080c606 SetupTest.String_298_ +0080c608 SetupTest.String_311_ +0080c60b SetupTest.String_324_ +0080c60f SetupTest.String_337_ +0080c613 SetupTest.String_350_ +0080c617 SetupTest.String_363_ +0080c61b SetupTest.String_376_ +0080c61f SetupTest.String_389_ +0080c62c SetupTest.String_402_ +008085f3 Test0 +008085fc Test0.LoopUntilAutojoy +00808600 Test0.ClearAutoJoyEnableFlag +00808682 Test0.InProgressFlagClear_1 +00808686 Test0.InProgressFlagClear_2 +0080868a Test0.InProgressFlagClear_3 +0080868e Test0.InProgressFlagClear_4 +00808692 Test0.InProgressFlagClear_5 +00808696 Test0.InProgressFlagClear_6 +0080869a Test0.InProgressFlagClear_7 +0080869e Test0.InProgressFlagClear_8 +008086a2 Test0.InProgressFlagClear_9 +008086a6 Test0.InProgressFlagClear_10 +008086aa Test0.InProgressFlagClear_11 +008086ae Test0.InProgressFlagClear_12 +008086b2 Test0.InProgressFlagClear_13 +008086b6 Test0.InProgressFlagClear_14 +008086ba Test0.InProgressFlagClear_15 +008086be Test0.InProgressFlagClear_16 +008086c2 Test0.InProgressFlagClear_17 +008086c6 Test0.InProgressFlagClear_18 +008086ca Test0.InProgressFlagClear_19 +008086ce Test0.InProgressFlagClear_20 +008086d2 Test0.InProgressFlagClear_21 +008086d6 Test0.InProgressFlagClear_22 +008086da Test0.InProgressFlagClear_23 +008086de Test0.InProgressFlagClear_24 +008086e2 Test0.InProgressFlagClear_25 +008086e6 Test0.InProgressFlagClear_26 +008086ea Test0.InProgressFlagClear_27 +008086ee Test0.InProgressFlagClear_28 +008086f2 Test0.InProgressFlagClear_29 +008086f6 Test0.InProgressFlagClear_30 +008086fa Test0.InProgressFlagClear_31 +008086fe Test0.PrintResults +00808772 Test0.TextBuffer.VBlank.SkipCharBuffer +008087a1 Test0.TextBuffer.VBlank.SkipAttrBuffer +008087a7 Test1 +008087b0 Test1.LoopUntilAutojoy +008087bc Test1.ClearAutoJoyEnableFlag +0080883e Test1.InProgressFlagClear_1 +00808842 Test1.InProgressFlagClear_2 +00808846 Test1.InProgressFlagClear_3 +0080884a Test1.InProgressFlagClear_4 +0080884e Test1.InProgressFlagClear_5 +00808852 Test1.InProgressFlagClear_6 +00808856 Test1.InProgressFlagClear_7 +0080885a Test1.InProgressFlagClear_8 +0080885e Test1.InProgressFlagClear_9 +00808862 Test1.InProgressFlagClear_10 +00808866 Test1.InProgressFlagClear_11 +0080886a Test1.InProgressFlagClear_12 +0080886e Test1.InProgressFlagClear_13 +00808872 Test1.InProgressFlagClear_14 +00808876 Test1.InProgressFlagClear_15 +0080887a Test1.InProgressFlagClear_16 +0080887e Test1.InProgressFlagClear_17 +00808882 Test1.InProgressFlagClear_18 +00808886 Test1.InProgressFlagClear_19 +0080888a Test1.InProgressFlagClear_20 +0080888e Test1.InProgressFlagClear_21 +00808892 Test1.InProgressFlagClear_22 +00808896 Test1.InProgressFlagClear_23 +0080889a Test1.InProgressFlagClear_24 +0080889e Test1.InProgressFlagClear_25 +008088a2 Test1.InProgressFlagClear_26 +008088a6 Test1.InProgressFlagClear_27 +008088aa Test1.InProgressFlagClear_28 +008088ae Test1.InProgressFlagClear_29 +008088b2 Test1.InProgressFlagClear_30 +008088b6 Test1.InProgressFlagClear_31 +008088ba Test1.PrintResults +0080892e Test1.TextBuffer.VBlank.SkipCharBuffer +0080895d Test1.TextBuffer.VBlank.SkipAttrBuffer +00808963 Test2 +0080896c Test2.LoopUntilAutojoy +00808980 Test2.ClearAutoJoyEnableFlag +00808a02 Test2.InProgressFlagClear_1 +00808a06 Test2.InProgressFlagClear_2 +00808a0a Test2.InProgressFlagClear_3 +00808a0e Test2.InProgressFlagClear_4 +00808a12 Test2.InProgressFlagClear_5 +00808a16 Test2.InProgressFlagClear_6 +00808a1a Test2.InProgressFlagClear_7 +00808a1e Test2.InProgressFlagClear_8 +00808a22 Test2.InProgressFlagClear_9 +00808a26 Test2.InProgressFlagClear_10 +00808a2a Test2.InProgressFlagClear_11 +00808a2e Test2.InProgressFlagClear_12 +00808a32 Test2.InProgressFlagClear_13 +00808a36 Test2.InProgressFlagClear_14 +00808a3a Test2.InProgressFlagClear_15 +00808a3e Test2.InProgressFlagClear_16 +00808a42 Test2.InProgressFlagClear_17 +00808a46 Test2.InProgressFlagClear_18 +00808a4a Test2.InProgressFlagClear_19 +00808a4e Test2.InProgressFlagClear_20 +00808a52 Test2.InProgressFlagClear_21 +00808a56 Test2.InProgressFlagClear_22 +00808a5a Test2.InProgressFlagClear_23 +00808a5e Test2.InProgressFlagClear_24 +00808a62 Test2.InProgressFlagClear_25 +00808a66 Test2.InProgressFlagClear_26 +00808a6a Test2.InProgressFlagClear_27 +00808a6e Test2.InProgressFlagClear_28 +00808a72 Test2.InProgressFlagClear_29 +00808a76 Test2.InProgressFlagClear_30 +00808a7a Test2.InProgressFlagClear_31 +00808a7e Test2.PrintResults +00808af2 Test2.TextBuffer.VBlank.SkipCharBuffer +00808b21 Test2.TextBuffer.VBlank.SkipAttrBuffer +00808b27 Test3 +00808b30 Test3.LoopUntilAutojoy +00808b4c Test3.ClearAutoJoyEnableFlag +00808bce Test3.InProgressFlagClear_1 +00808bd2 Test3.InProgressFlagClear_2 +00808bd6 Test3.InProgressFlagClear_3 +00808bda Test3.InProgressFlagClear_4 +00808bde Test3.InProgressFlagClear_5 +00808be2 Test3.InProgressFlagClear_6 +00808be6 Test3.InProgressFlagClear_7 +00808bea Test3.InProgressFlagClear_8 +00808bee Test3.InProgressFlagClear_9 +00808bf2 Test3.InProgressFlagClear_10 +00808bf6 Test3.InProgressFlagClear_11 +00808bfa Test3.InProgressFlagClear_12 +00808bfe Test3.InProgressFlagClear_13 +00808c02 Test3.InProgressFlagClear_14 +00808c06 Test3.InProgressFlagClear_15 +00808c0a Test3.InProgressFlagClear_16 +00808c0e Test3.InProgressFlagClear_17 +00808c12 Test3.InProgressFlagClear_18 +00808c16 Test3.InProgressFlagClear_19 +00808c1a Test3.InProgressFlagClear_20 +00808c1e Test3.InProgressFlagClear_21 +00808c22 Test3.InProgressFlagClear_22 +00808c26 Test3.InProgressFlagClear_23 +00808c2a Test3.InProgressFlagClear_24 +00808c2e Test3.InProgressFlagClear_25 +00808c32 Test3.InProgressFlagClear_26 +00808c36 Test3.InProgressFlagClear_27 +00808c3a Test3.InProgressFlagClear_28 +00808c3e Test3.InProgressFlagClear_29 +00808c42 Test3.InProgressFlagClear_30 +00808c46 Test3.InProgressFlagClear_31 +00808c4a Test3.PrintResults +00808cbe Test3.TextBuffer.VBlank.SkipCharBuffer +00808ced Test3.TextBuffer.VBlank.SkipAttrBuffer +00808cf3 Test4 +00808cfc Test4.LoopUntilAutojoy +00808d20 Test4.ClearAutoJoyEnableFlag +00808da2 Test4.InProgressFlagClear_1 +00808da6 Test4.InProgressFlagClear_2 +00808daa Test4.InProgressFlagClear_3 +00808dae Test4.InProgressFlagClear_4 +00808db2 Test4.InProgressFlagClear_5 +00808db6 Test4.InProgressFlagClear_6 +00808dba Test4.InProgressFlagClear_7 +00808dbe Test4.InProgressFlagClear_8 +00808dc2 Test4.InProgressFlagClear_9 +00808dc6 Test4.InProgressFlagClear_10 +00808dca Test4.InProgressFlagClear_11 +00808dce Test4.InProgressFlagClear_12 +00808dd2 Test4.InProgressFlagClear_13 +00808dd6 Test4.InProgressFlagClear_14 +00808dda Test4.InProgressFlagClear_15 +00808dde Test4.InProgressFlagClear_16 +00808de2 Test4.InProgressFlagClear_17 +00808de6 Test4.InProgressFlagClear_18 +00808dea Test4.InProgressFlagClear_19 +00808dee Test4.InProgressFlagClear_20 +00808df2 Test4.InProgressFlagClear_21 +00808df6 Test4.InProgressFlagClear_22 +00808dfa Test4.InProgressFlagClear_23 +00808dfe Test4.InProgressFlagClear_24 +00808e02 Test4.InProgressFlagClear_25 +00808e06 Test4.InProgressFlagClear_26 +00808e0a Test4.InProgressFlagClear_27 +00808e0e Test4.InProgressFlagClear_28 +00808e12 Test4.InProgressFlagClear_29 +00808e16 Test4.InProgressFlagClear_30 +00808e1a Test4.InProgressFlagClear_31 +00808e1e Test4.PrintResults +00808e92 Test4.TextBuffer.VBlank.SkipCharBuffer +00808ec1 Test4.TextBuffer.VBlank.SkipAttrBuffer +00808ec7 Test5 +00808ed0 Test5.LoopUntilAutojoy +00808f04 Test5.ClearAutoJoyEnableFlag +00808f86 Test5.InProgressFlagClear_1 +00808f8a Test5.InProgressFlagClear_2 +00808f8e Test5.InProgressFlagClear_3 +00808f92 Test5.InProgressFlagClear_4 +00808f96 Test5.InProgressFlagClear_5 +00808f9a Test5.InProgressFlagClear_6 +00808f9e Test5.InProgressFlagClear_7 +00808fa2 Test5.InProgressFlagClear_8 +00808fa6 Test5.InProgressFlagClear_9 +00808faa Test5.InProgressFlagClear_10 +00808fae Test5.InProgressFlagClear_11 +00808fb2 Test5.InProgressFlagClear_12 +00808fb6 Test5.InProgressFlagClear_13 +00808fba Test5.InProgressFlagClear_14 +00808fbe Test5.InProgressFlagClear_15 +00808fc2 Test5.InProgressFlagClear_16 +00808fc6 Test5.InProgressFlagClear_17 +00808fca Test5.InProgressFlagClear_18 +00808fce Test5.InProgressFlagClear_19 +00808fd2 Test5.InProgressFlagClear_20 +00808fd6 Test5.InProgressFlagClear_21 +00808fda Test5.InProgressFlagClear_22 +00808fde Test5.InProgressFlagClear_23 +00808fe2 Test5.InProgressFlagClear_24 +00808fe6 Test5.InProgressFlagClear_25 +00808fea Test5.InProgressFlagClear_26 +00808fee Test5.InProgressFlagClear_27 +00808ff2 Test5.InProgressFlagClear_28 +00808ff6 Test5.InProgressFlagClear_29 +00808ffa Test5.InProgressFlagClear_30 +00808ffe Test5.InProgressFlagClear_31 +00809002 Test5.PrintResults +00809076 Test5.TextBuffer.VBlank.SkipCharBuffer +008090a5 Test5.TextBuffer.VBlank.SkipAttrBuffer +008090ab Test6 +008090b4 Test6.LoopUntilAutojoy +008090f8 Test6.ClearAutoJoyEnableFlag +0080917a Test6.InProgressFlagClear_1 +0080917e Test6.InProgressFlagClear_2 +00809182 Test6.InProgressFlagClear_3 +00809186 Test6.InProgressFlagClear_4 +0080918a Test6.InProgressFlagClear_5 +0080918e Test6.InProgressFlagClear_6 +00809192 Test6.InProgressFlagClear_7 +00809196 Test6.InProgressFlagClear_8 +0080919a Test6.InProgressFlagClear_9 +0080919e Test6.InProgressFlagClear_10 +008091a2 Test6.InProgressFlagClear_11 +008091a6 Test6.InProgressFlagClear_12 +008091aa Test6.InProgressFlagClear_13 +008091ae Test6.InProgressFlagClear_14 +008091b2 Test6.InProgressFlagClear_15 +008091b6 Test6.InProgressFlagClear_16 +008091ba Test6.InProgressFlagClear_17 +008091be Test6.InProgressFlagClear_18 +008091c2 Test6.InProgressFlagClear_19 +008091c6 Test6.InProgressFlagClear_20 +008091ca Test6.InProgressFlagClear_21 +008091ce Test6.InProgressFlagClear_22 +008091d2 Test6.InProgressFlagClear_23 +008091d6 Test6.InProgressFlagClear_24 +008091da Test6.InProgressFlagClear_25 +008091de Test6.InProgressFlagClear_26 +008091e2 Test6.InProgressFlagClear_27 +008091e6 Test6.InProgressFlagClear_28 +008091ea Test6.InProgressFlagClear_29 +008091ee Test6.InProgressFlagClear_30 +008091f2 Test6.InProgressFlagClear_31 +008091f6 Test6.PrintResults +0080926a Test6.TextBuffer.VBlank.SkipCharBuffer +00809299 Test6.TextBuffer.VBlank.SkipAttrBuffer +0080929f Main +008092d5 Main.MainLoop +0080c638 TitleAndVersionStr +0080c66c Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sfc new file mode 100644 index 00000000..6bf2e753 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sym new file mode 100644 index 00000000..1a93f674 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c65a SetupTest.String_287_ +0080c66c SetupTest.String_300_ +0080c67c SetupTest.String_313_ +0080c680 SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867c Main +008086b2 Main.MainLoop +0080c688 TitleAndVersionStr +0080c6d2 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sfc new file mode 100644 index 00000000..ae3f626c Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sym new file mode 100644 index 00000000..1b6a4d45 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c63c SetupTest.String_300_ +0080c646 SetupTest.String_313_ +0080c652 SetupTest.String_326_ +0080c659 SetupTest.String_339_ +00808599 DoTest +0080860e DoTest.TextBuffer.VBlank.SkipCharBuffer +0080863d DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808643 IrqHandler +00808648 Main +0080867e Main.MainLoop +0080c664 TitleAndVersionStr +0080c6a3 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sfc new file mode 100644 index 00000000..4f542243 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sym new file mode 100644 index 00000000..425052fe --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c636 SetupTest.String_287_ +0080c648 SetupTest.String_300_ +0080c658 SetupTest.String_313_ +0080c65c SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867d Main +008086b3 Main.MainLoop +0080c664 TitleAndVersionStr +0080c6c3 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sfc new file mode 100644 index 00000000..a94c3b83 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sym new file mode 100644 index 00000000..6a9b85c6 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c636 SetupTest.String_287_ +0080c648 SetupTest.String_300_ +0080c658 SetupTest.String_313_ +0080c65c SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867d Main +008086b3 Main.MainLoop +0080c664 TitleAndVersionStr +0080c6c1 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sfc b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sfc new file mode 100644 index 00000000..58e138b5 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sym b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sym new file mode 100644 index 00000000..61b81cb8 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sym @@ -0,0 +1,57 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +0080c000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +0080c300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080c600 TestData +0080850a SetupTest +0080c648 SetupTest.String_287_ +0080c65a SetupTest.String_300_ +0080c66a SetupTest.String_313_ +0080c66e SetupTest.String_326_ +00808599 DoTest +00808642 DoTest.TextBuffer.VBlank.SkipCharBuffer +00808671 DoTest.TextBuffer.VBlank.SkipAttrBuffer +00808677 IrqHandler +0080867d Main +008086b3 Main.MainLoop +0080c676 TitleAndVersionStr +0080c6c6 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sfc b/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sfc new file mode 100644 index 00000000..2266ebc9 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sym b/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sym new file mode 100644 index 00000000..97767b62 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sym @@ -0,0 +1,26 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Main +00808682 Main.SpinLoop +0080a000 CgaddTable +0080a017 CgdataTable diff --git a/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sfc b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sfc new file mode 100644 index 00000000..7832094a Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sym b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sym new file mode 100644 index 00000000..291ea275 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sym @@ -0,0 +1,17 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 NmiHandler +00808004 NmiHandler.Nmi_Fast +00808014 BreakHandler +00808014 CopHandler +00808014 EmptyHandler +00808016 PartialHdmaTable +0080801b IrqHandler +0080801f ResetHandler +00808023 ResetHandler.Reset +00808060 Main +008080be Main.HdmaChannelLoop +008080c1 Main.HtimeLoop +008080db Main.WaitUntilHblank._Loop_58_ +008080e0 Main.WaitUntilHblankEnd._Loop_60_ +008080eb Main.WaitUntilHblank._Loop_62_ +008080fb Main.WaitUntilHblankEnd._Loop_64_ diff --git a/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sfc b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sfc new file mode 100644 index 00000000..f84b6eee Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sym b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sym new file mode 100644 index 00000000..c6671564 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sym @@ -0,0 +1,15 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 _wait_rom +00808000 WaitScanlines_A +00808007 WaitScanlines_A.Loop +0080801a NmiHandler +0080801a BreakHandler +0080801a CopHandler +0080801a EmptyHandler +0080802a PartialHdmaTable +0080802f IrqHandler +00808035 ResetHandler +00808039 ResetHandler.Reset +00808076 Main +008080e4 Main.HdmaChannelLoop +008081f0 Main._OddScanline diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sfc b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sfc new file mode 100644 index 00000000..9ffbfac3 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sym b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sym new file mode 100644 index 00000000..252cfaa1 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sym @@ -0,0 +1,27 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Main +00808694 Main.MainLoop +00808697 Resources.Palette +0080869f Resources.Bg1_Tiles +008086bf Resources.Bg1_Tilemap diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sfc b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sfc new file mode 100644 index 00000000..1203df91 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sym b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sym new file mode 100644 index 00000000..aae3b7cf --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sym @@ -0,0 +1,28 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b NmiHandler +0080854f NmiHandler.Nmi_Fast +0080855f Dma.ForceBlank.ClearVram +0080857f Dma.ForceBlank.ClearVramL +0080859f Dma.ForceBlank.ClearVramH +008085bf Dma.ForceBlank.ClearCgram +008085e2 Dma.ForceBlank.TransferToVram +008085fc Dma.ForceBlank.TransferToVramL +00808614 Dma.ForceBlank.TransferToVramH +0080862e Dma.ForceBlank.TransferToCgram +00808643 Dma.ForceBlank.TransferToOam +00808658 Main +00808680 Main.MainLoop +00808683 IrqHandler +008086ab IrqHandler.End diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sfc b/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sfc new file mode 100644 index 00000000..83ec1bcf Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sym b/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sym new file mode 100644 index 00000000..07bf7844 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sym @@ -0,0 +1,44 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b NmiHandler +0080854f NmiHandler.Nmi_Fast +0080855f Dma.ForceBlank.ClearVram +0080857f Dma.ForceBlank.ClearVramL +0080859f Dma.ForceBlank.ClearVramH +008085bf Dma.ForceBlank.ClearCgram +008085e2 Dma.ForceBlank.TransferToVram +008085fc Dma.ForceBlank.TransferToVramL +00808614 Dma.ForceBlank.TransferToVramH +0080862e Dma.ForceBlank.TransferToCgram +00808643 Dma.ForceBlank.TransferToOam +00808658 IrqHandler +00808667 WaitFrame +00808679 UpdateJoypad +00808679 UpdateJoypad.Loop +0080869f Main +008086b6 Main.Setup +008087e6 Main.MainLoop +00808811 Main.MoveUp +0080884c Main.GotoNextDisplayMode +0080885a DisplayModeSettings +008088ae Resources.Bg1_Tilemap +008090ae Resources.Tiles_8bpp +008098ae Resources.Palette_8bpp +008098b6 Resources.Tiles_4bpp +00809cb6 Resources.Palette_4bpp +00809cbe Resources.Tiles_2bpp +00809ebe Resources.Palette_2bpp +00809ec6 Resources.Obj_Tiles +0080aec6 Resources.Obj_Palette +0080aece Resources.Obj_Oam diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sfc b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sfc new file mode 100644 index 00000000..ca43f069 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sym b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sym new file mode 100644 index 00000000..e3328065 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sym @@ -0,0 +1,31 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 IrqHandler +0080864d Main +00808713 Main.Loop +00808717 Resources.Bg1_Tilemap +00808f17 Resources.Tiles_8bpp +00809717 Resources.Palette_8bpp +0080971f Resources.Obj_Tiles +0080a71f Resources.Obj_Palette +0080a727 Resources.Obj_Oam diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sfc b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sfc new file mode 100644 index 00000000..43c904d3 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sym b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sym new file mode 100644 index 00000000..b2a3fc67 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sym @@ -0,0 +1,32 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 IrqHandler +0080864d SetupPpu +008086dc Main +00808708 Main.Loop +0080870c Resources.Bg1_Tilemap +00808f0c Resources.Tiles_4bpp +0080930c Resources.Palette_4bpp +00809314 Resources.Obj_Tiles +0080a314 Resources.Obj_Palette +0080a31c Resources.Obj_Oam diff --git a/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sfc b/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sfc new file mode 100644 index 00000000..9f2ea7ad Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sym b/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sym new file mode 100644 index 00000000..7077a5a2 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/joypad_bounce_test.sym @@ -0,0 +1,45 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Main +0080871f Main.MainLoop +00808726 Main.WaitForKeyRelease +00808726 Main.WaitForHBlank.Loop_198_ +0080878b Main.WaitForKeyPressLoop +0080878b Main.WaitForHBlank.Loop_204_ +008087f2 Main.KeyPressLoop +008087f2 Main.WaitForHBlank.Loop_210_ +0080885a Main.KeyReleaseLoop +00808862 Main.WaitForHBlank.Loop_216_ +008088d7 BuildAndDisplayHdmaTables +00808a48 BuildAndDisplayHdmaTables.WaitForStartOfVBlank.InVBlankLoop_243_ +00808a4d BuildAndDisplayHdmaTables.WaitForStartOfVBlank.WaitForVBlankLoop_243_ +00808ae2 HdmaTable1_TableAddr +00808ae6 HdmaTable2_TableAddr +00808aea HdmaTable3_TableAddr +00808aee HdmaTable4_TableAddr +00808af2 Resources.Bg_Tiles +00808b72 Resources.Bg_Tilemap +00809372 Resources.Obj_Tiles +008094b2 Resources.Palette +00809532 Resources.ObjPalette +00809536 Resources.Oam diff --git a/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sfc b/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sfc new file mode 100644 index 00000000..cfeb974c Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sym b/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sym new file mode 100644 index 00000000..bf3602d5 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sym @@ -0,0 +1,28 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Main +008086ad Main.MainLoop +008086c0 Main.ScanlineLoop +00808735 Resources.Bg_Tiles +008087b5 Resources.Bg_Tilemap +00808fb5 Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sfc b/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sfc new file mode 100644 index 00000000..451ed9de Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sym b/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sym new file mode 100644 index 00000000..d42d4b03 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/object-dropout-test.sym @@ -0,0 +1,34 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 SetupPpu +008086cb Main +008086ea Main.MainLoop +008086f0 Resources.Obj_Tiles +0080a6f0 Resources.Obj_Palette +0080a7f0 Resources.Obj_Oam +0080a9f0 Resources.Obj_OamHiTable diff --git a/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sfc b/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sfc new file mode 100644 index 00000000..703e628a Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sym b/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sym new file mode 100644 index 00000000..50f58371 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/reset-position-test.sym @@ -0,0 +1,48 @@ +0000ffb6 SnesHeader.EmptyBytes +0080c000 BreakHandler.Font_1bpp +00808000 BreakHandler.CrashString +0080800b BreakHandler.BreakDataTable +00808045 BreakHandler.EmptyByte +00808046 BreakHandler.ISR +00808104 BreakHandler.ISR.PrintRegisterLoop +0080813f BreakHandler.ISR.SpinLoop +00808142 BreakHandler.PrintString +0080815a Dma.ForceBlank.ClearVram +0080817a Dma.ForceBlank.ClearVramL +0080819a Dma.ForceBlank.ClearVramH +008081ba Dma.ForceBlank.ClearCgram +008081dd Dma.ForceBlank.TransferToVram +008081f7 Dma.ForceBlank.TransferToVramL +0080820f Dma.ForceBlank.TransferToVramH +00808229 Dma.ForceBlank.TransferToCgram +0080823e Dma.ForceBlank.TransferToOam +00808253 ResetRegisters +0080c300 TextBuffer.Font_1bpp +008082ac TextBuffer.InitAndTransferToVram +008082b5 TextBuffer.ClearCharBufferAndResetCursor +008082c9 TextBuffer.ClearCharBufferAndResetCursor.Loop +008082d7 TextBuffer.ClearAttrBuffer +008082df TextBuffer.ClearAttrBuffer.Loop +008082ed TextBuffer.TransferFontAndBuffersToVram +00808332 TextBuffer.SetCursor +00808365 TextBuffer.NewLine +00808383 TextBuffer.NewLine.Loop +00808392 TextBuffer.PrintString +008083a0 TextBuffer.PrintString.Loop +008083b2 TextBuffer.PrintString.NewLineCharacter +008083c5 TextBuffer.PrintString.EmptyString +008083c6 TextBuffer.PrintOneHexDigitSpace_8A +008083da TextBuffer.PrintOneHexDigitSpace_8A.AfterX +008083fb TextBuffer.PrintHexSpace_8A +00808410 TextBuffer.PrintHexSpace_8A.AfterX +0080843e TextBuffer.PrintHexSpace_16Y +00808440 TextBuffer.PrintHexSpace_16Y.FallThrough +00808440 TextBuffer.PrintHexSpace_16_zpTmp0 +00808472 ResetHandler +008086bd ResetHandler.Loop +0080c600 ResetHandler.String_333_ +0080c61b ResetHandler.String_342_ +0080c625 ResetHandler.String_351_ +0080c630 ResetHandler.String_360_ +0080c64b ResetHandler.String_369_ +0080c664 Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sfc b/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sfc new file mode 100644 index 00000000..e85fd838 Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sym b/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sym new file mode 100644 index 00000000..c580e85e --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sym @@ -0,0 +1,27 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 Main +00808688 Main.MainLoop +0080869d Main.CorruptionLoop +008086ad Resources.Tiles_2bpp +008086bd Resources.Palette diff --git a/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sfc b/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sfc new file mode 100644 index 00000000..836f572f Binary files /dev/null and b/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sfc differ diff --git a/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sym b/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sym new file mode 100644 index 00000000..e0373395 --- /dev/null +++ b/roms/snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sym @@ -0,0 +1,67 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +00818000 BreakHandler.Font_1bpp +008080f1 BreakHandler.CrashString +008080fc BreakHandler.BreakDataTable +00808136 BreakHandler.EmptyByte +00808137 BreakHandler.ISR +008081f5 BreakHandler.ISR.PrintRegisterLoop +00808230 BreakHandler.ISR.SpinLoop +00808233 BreakHandler.PrintString +0080824b Dma.ForceBlank.ClearVram +0080826b Dma.ForceBlank.ClearVramL +0080828b Dma.ForceBlank.ClearVramH +008082ab Dma.ForceBlank.ClearCgram +008082ce Dma.ForceBlank.TransferToVram +008082e8 Dma.ForceBlank.TransferToVramL +00808300 Dma.ForceBlank.TransferToVramH +0080831a Dma.ForceBlank.TransferToCgram +0080832f Dma.ForceBlank.TransferToOam +00818300 TextBuffer.Font_1bpp +00808344 TextBuffer.InitAndTransferToVram +0080834d TextBuffer.ClearCharBufferAndResetCursor +00808361 TextBuffer.ClearCharBufferAndResetCursor.Loop +0080836f TextBuffer.ClearAttrBuffer +00808377 TextBuffer.ClearAttrBuffer.Loop +00808385 TextBuffer.TransferFontAndBuffersToVram +008083ca TextBuffer.SetCursor +008083fd TextBuffer.NewLine +0080841b TextBuffer.NewLine.Loop +0080842a TextBuffer.PrintString +00808438 TextBuffer.PrintString.Loop +0080844a TextBuffer.PrintString.NewLineCharacter +0080845d TextBuffer.PrintString.EmptyString +0080845e TextBuffer.PrintOneHexDigitSpace_8A +00808472 TextBuffer.PrintOneHexDigitSpace_8A.AfterX +00808493 TextBuffer.PrintHexSpace_8A +008084a8 TextBuffer.PrintHexSpace_8A.AfterX +008084d6 TextBuffer.PrintHexSpace_16Y +008084d8 TextBuffer.PrintHexSpace_16Y.FallThrough +008084d8 TextBuffer.PrintHexSpace_16_zpTmp0 +0080850a IrqHandler +00808513 WaitFrame +0080851b WaitFrame.Loop +00808523 NmiHandler +00808527 NmiHandler.FastRomNmiHandler +0080856e NmiHandler.VBlank.TextBuffer.VBlank.SkipCharBuffer +0080859d NmiHandler.VBlank.TextBuffer.VBlank.SkipAttrBuffer +008085c1 NmiHandler.EndVBlankRoutine +008085d1 RunOneTest +00808692 RunTests +00808731 PrintResults +0080874a PrintResults.CursorLoop +00818600 PrintResults.String_375_ +00818604 PrintResults.String_384_ +00818608 PrintResults.String_397_ +00818625 PrintResults.String_406_ +00808790 PrintResults.Loop +00818642 PrintResults.String_416_ +008087bf _PrintByte +008087c5 _PrintWord +008087d1 ProcessJoypad +00808824 Main +00808872 Main.MainLoop +00808881 Resources.Palette diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sfc new file mode 100644 index 00000000..8948bdc8 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sym new file mode 100644 index 00000000..bc28d1af --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sym @@ -0,0 +1,50 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808ca8 SetPixel.Zero +00808cb2 SetPixel.EndIf +00808cb3 ShiftTable +00808cbb InverseShiftTable +00808cc3 TransferTileBufferToVram +00808d1a Resources.ZeroByte diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sfc new file mode 100644 index 00000000..80149c2c Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sym new file mode 100644 index 00000000..2254bc88 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sym @@ -0,0 +1,50 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808c9d SetPixel.Zero +00808ca7 SetPixel.EndIf +00808ca8 ShiftTable +00808cb0 InverseShiftTable +00808cb8 TransferTileBufferToVram +00808d0f Resources.ZeroByte diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sfc new file mode 100644 index 00000000..18467e32 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sym new file mode 100644 index 00000000..33545693 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sym @@ -0,0 +1,51 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808cab SetPixel._DrawBit.Zero__392_ +00808cb5 SetPixel._DrawBit.EndIf__392_ +00808cc7 SetPixel._DrawBit.Zero__395_ +00808cd1 SetPixel._DrawBit.EndIf__395_ +00808cd2 ShiftTable +00808cda InverseShiftTable +00808ce2 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sfc new file mode 100644 index 00000000..0829706a Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sym new file mode 100644 index 00000000..9f296b68 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sym @@ -0,0 +1,51 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808c9f SetPixel._DrawBit.Zero__392_ +00808ca9 SetPixel._DrawBit.EndIf__392_ +00808cbb SetPixel._DrawBit.Zero__395_ +00808cc5 SetPixel._DrawBit.EndIf__395_ +00808cc6 ShiftTable +00808cce InverseShiftTable +00808cd6 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-with-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-with-remapping.sfc new file mode 100644 index 00000000..1a5962af Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-with-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sfc new file mode 100644 index 00000000..c6bec9e0 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sym new file mode 100644 index 00000000..ce6dce75 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sym @@ -0,0 +1,47 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808cd2 PlotTable +00808d12 MaskTable +00808d52 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sfc new file mode 100644 index 00000000..fc034930 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sym new file mode 100644 index 00000000..e432ee47 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sym @@ -0,0 +1,55 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808cab SetPixel._DrawBit.Zero__392_ +00808cb5 SetPixel._DrawBit.EndIf__392_ +00808cc7 SetPixel._DrawBit.Zero__395_ +00808cd1 SetPixel._DrawBit.EndIf__395_ +00808ce3 SetPixel._DrawBit.Zero__398_ +00808ced SetPixel._DrawBit.EndIf__398_ +00808cff SetPixel._DrawBit.Zero__401_ +00808d09 SetPixel._DrawBit.EndIf__401_ +00808d0a ShiftTable +00808d12 InverseShiftTable +00808d1a TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sfc new file mode 100644 index 00000000..6bd76cdc Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sym new file mode 100644 index 00000000..4e7edfe3 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sym @@ -0,0 +1,47 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808cc5 PlotTable +00808d05 MaskTable +00808d45 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sfc new file mode 100644 index 00000000..7ebd4b70 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sym new file mode 100644 index 00000000..4a7a5023 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sym @@ -0,0 +1,55 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808c9e SetPixel._DrawBit.Zero__392_ +00808ca8 SetPixel._DrawBit.EndIf__392_ +00808cba SetPixel._DrawBit.Zero__395_ +00808cc4 SetPixel._DrawBit.EndIf__395_ +00808cd6 SetPixel._DrawBit.Zero__398_ +00808ce0 SetPixel._DrawBit.EndIf__398_ +00808cf2 SetPixel._DrawBit.Zero__401_ +00808cfc SetPixel._DrawBit.EndIf__401_ +00808cfd ShiftTable +00808d05 InverseShiftTable +00808d0d TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sfc new file mode 100644 index 00000000..28d1e0d0 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sym new file mode 100644 index 00000000..f378e0f8 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sym @@ -0,0 +1,63 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808cab SetPixel._DrawBit.Zero__392_ +00808cb5 SetPixel._DrawBit.EndIf__392_ +00808cc7 SetPixel._DrawBit.Zero__395_ +00808cd1 SetPixel._DrawBit.EndIf__395_ +00808ce3 SetPixel._DrawBit.Zero__398_ +00808ced SetPixel._DrawBit.EndIf__398_ +00808cff SetPixel._DrawBit.Zero__401_ +00808d09 SetPixel._DrawBit.EndIf__401_ +00808d1b SetPixel._DrawBit.Zero__404_ +00808d25 SetPixel._DrawBit.EndIf__404_ +00808d37 SetPixel._DrawBit.Zero__407_ +00808d41 SetPixel._DrawBit.EndIf__407_ +00808d51 SetPixel._DrawBit.Zero__410_ +00808d5b SetPixel._DrawBit.EndIf__410_ +00808d6b SetPixel._DrawBit.Zero__413_ +00808d75 SetPixel._DrawBit.EndIf__413_ +00808d76 ShiftTable +00808d7e InverseShiftTable +00808d86 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sfc new file mode 100644 index 00000000..c286ce4c Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sym new file mode 100644 index 00000000..c438284e --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sym @@ -0,0 +1,63 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +008086d5 Main.MainLoop +008086d8 GenerateTilemap +008086fc ClearTileBuffer +00808701 ClearTileBuffer.Loop +0080870e DrawImage +00808711 DrawImage.Loop +00808725 SetPixelWithBoundsChecking +00808731 DrawLine.InvalidInput +00808732 DrawLine +008087a4 DrawLine.ShallowLoop +008087d9 DrawLine.SteepLine +008087ed DrawLine.SteepLoop +0080881b DrawLine.Return +0080881c Palette +00808a1c LineList +00808c74 SetPixel +00808c9c SetPixel._DrawBit.Zero__392_ +00808ca6 SetPixel._DrawBit.EndIf__392_ +00808cb8 SetPixel._DrawBit.Zero__395_ +00808cc2 SetPixel._DrawBit.EndIf__395_ +00808cd4 SetPixel._DrawBit.Zero__398_ +00808cde SetPixel._DrawBit.EndIf__398_ +00808cf0 SetPixel._DrawBit.Zero__401_ +00808cfa SetPixel._DrawBit.EndIf__401_ +00808d0c SetPixel._DrawBit.Zero__404_ +00808d16 SetPixel._DrawBit.EndIf__404_ +00808d28 SetPixel._DrawBit.Zero__407_ +00808d32 SetPixel._DrawBit.EndIf__407_ +00808d42 SetPixel._DrawBit.Zero__410_ +00808d4c SetPixel._DrawBit.EndIf__410_ +00808d5c SetPixel._DrawBit.Zero__413_ +00808d66 SetPixel._DrawBit.EndIf__413_ +00808d67 ShiftTable +00808d6f InverseShiftTable +00808d77 TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sfc new file mode 100644 index 00000000..5bcb07c4 Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sym new file mode 100644 index 00000000..479d2926 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sym @@ -0,0 +1,47 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +00808702 Main.MainLoop +00808705 ClearTileBuffer +0080870a ClearTileBuffer.Loop +00808717 DrawImage +0080871a DrawImage.Loop +0080872e SetPixelWithBoundsChecking +0080873a DrawLine.InvalidInput +0080873b DrawLine +008087ad DrawLine.ShallowLoop +008087e2 DrawLine.SteepLine +008087f6 DrawLine.SteepLoop +00808824 DrawLine.Return +00808825 Palette +00808a25 LineList +00808b51 SetPixel +00808b80 GenerateTilemap +00808b8b GenerateTilemap.YLoop +00808b9b GenerateTilemap.XLoop +00808baa TransferTileBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sfc new file mode 100644 index 00000000..859a277b Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sym new file mode 100644 index 00000000..97a5c1b1 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sym @@ -0,0 +1,46 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +00808702 Main.MainLoop +00808705 ClearTileBuffer +0080870a ClearTileBuffer.Loop +00808717 DrawImage +0080871a DrawImage.Loop +0080872e SetPixelWithBoundsChecking +0080873a DrawLine.InvalidInput +0080873b DrawLine +008087ad DrawLine.ShallowLoop +008087e2 DrawLine.SteepLine +008087f6 DrawLine.SteepLoop +00808824 DrawLine.Return +00808825 Palette +00808a25 LineList +00808b51 SetPixel +00808b6c GenerateTileData +00808b8e GenerateTileData.Loop +00808b9c TransferImageBufferToVram diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sfc new file mode 100644 index 00000000..db28ff9d Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sym new file mode 100644 index 00000000..2d28d33c --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sym @@ -0,0 +1,48 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +00808702 Main.MainLoop +00808705 ClearTileBuffer +0080870a ClearTileBuffer.Loop +00808717 DrawImage +0080871a DrawImage.Loop +0080872e SetPixelWithBoundsChecking +0080873a DrawLine.InvalidInput +0080873b DrawLine +008087ad DrawLine.ShallowLoop +008087e2 DrawLine.SteepLine +008087f6 DrawLine.SteepLoop +00808824 DrawLine.Return +00808825 Palette +00808a25 LineList +00808b51 SetPixel +00808b6c GenerateTilemap +00808b77 GenerateTilemap.YLoop +00808b85 GenerateTilemap.XLoop +00808b98 TransferTileBufferToVram +00808bba TransferTileBufferToVram.Loop diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sfc b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sfc new file mode 100644 index 00000000..b03eff6b Binary files /dev/null and b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sfc differ diff --git a/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sym b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sym new file mode 100644 index 00000000..9f959f13 --- /dev/null +++ b/roms/snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sym @@ -0,0 +1,47 @@ +0000ffb6 SnesHeader.EmptyBytes +00808000 ResetRegisters +00808059 ResetHandler +0080805d ResetHandler.reset +008080a2 ClearVramOamAndCgram +008080f1 BreakHandler.Font_1bpp +008083f1 BreakHandler.CrashString +008083fc BreakHandler.BreakDataTable +00808436 BreakHandler.EmptyByte +00808437 BreakHandler.ISR +008084f5 BreakHandler.ISR.PrintRegisterLoop +00808530 BreakHandler.ISR.SpinLoop +00808533 BreakHandler.PrintString +0080854b Dma.ForceBlank.ClearVram +0080856b Dma.ForceBlank.ClearVramL +0080858b Dma.ForceBlank.ClearVramH +008085ab Dma.ForceBlank.ClearCgram +008085ce Dma.ForceBlank.TransferToVram +008085e8 Dma.ForceBlank.TransferToVramL +00808600 Dma.ForceBlank.TransferToVramH +0080861a Dma.ForceBlank.TransferToCgram +0080862f Dma.ForceBlank.TransferToOam +00808644 WaitFrame +0080864c WaitFrame.Loop +00808654 NmiHandler +00808658 NmiHandler.FastRomNmiHandler +00808672 NmiHandler.EndVBlankRoutine +00808682 Main +00808702 Main.MainLoop +00808705 ClearTileBuffer +0080870a ClearTileBuffer.Loop +00808717 DrawImage +0080871a DrawImage.Loop +0080872e SetPixelWithBoundsChecking +0080873a DrawLine.InvalidInput +0080873b DrawLine +008087ad DrawLine.ShallowLoop +008087e2 DrawLine.SteepLine +008087f6 DrawLine.SteepLoop +00808824 DrawLine.Return +00808825 Palette +00808a25 LineList +00808b51 SetPixel +00808b6c GenerateTilemap +00808b77 GenerateTilemap.YLoop +00808b85 GenerateTilemap.XLoop +00808ba2 TransferTileBufferToVram diff --git a/roms/snes-test-roms/resources/example-backgrounds/bricks-2bpp-tiles.png b/roms/snes-test-roms/resources/example-backgrounds/bricks-2bpp-tiles.png new file mode 100644 index 00000000..a47862b0 Binary files /dev/null and b/roms/snes-test-roms/resources/example-backgrounds/bricks-2bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/example-backgrounds/bricks-4bpp-tiles.png b/roms/snes-test-roms/resources/example-backgrounds/bricks-4bpp-tiles.png new file mode 100644 index 00000000..244bdaf9 Binary files /dev/null and b/roms/snes-test-roms/resources/example-backgrounds/bricks-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/example-backgrounds/bricks-8bpp-tiles.png b/roms/snes-test-roms/resources/example-backgrounds/bricks-8bpp-tiles.png new file mode 100644 index 00000000..08b12cc9 Binary files /dev/null and b/roms/snes-test-roms/resources/example-backgrounds/bricks-8bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/example-backgrounds/bricks-tilemap.asm b/roms/snes-test-roms/resources/example-backgrounds/bricks-tilemap.asm new file mode 100644 index 00000000..3efe38f0 --- /dev/null +++ b/roms/snes-test-roms/resources/example-backgrounds/bricks-tilemap.asm @@ -0,0 +1,49 @@ +// A brick pattern tile map +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +// 32x32 tilemap +// 8x8 px tiles + +variable y = 0 +while y < 32 { + variable row = (y + 1) / 2 + variable rowOffset = (y + 1) % 2 + + variable startingTile = row * 4 + variable brickId = (row == 2 || row == 12) ? 0 : 1 + + // first row + variable x = 0 + while x < 32 { + dw ((startingTile + x) % 8) + brickId * 8 + rowOffset * 16 + x = x + 1 + } + + y = y + 1 +} + + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/resources/example-backgrounds/clouds-2bpp-tiles.png b/roms/snes-test-roms/resources/example-backgrounds/clouds-2bpp-tiles.png new file mode 100644 index 00000000..cade55c3 Binary files /dev/null and b/roms/snes-test-roms/resources/example-backgrounds/clouds-2bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/example-backgrounds/clouds-tilemap.asm b/roms/snes-test-roms/resources/example-backgrounds/clouds-tilemap.asm new file mode 100644 index 00000000..3a760819 --- /dev/null +++ b/roms/snes-test-roms/resources/example-backgrounds/clouds-tilemap.asm @@ -0,0 +1,48 @@ +// A clouds pattern tile map +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// 32x32 tilemap + + +constant PATTERN_WIDTH = 16 +constant PATTERN_HEIGHT = 8 + + +variable y = 0 +while y < 32 { + variable x = 0 + while x < 32 { + dw (x % PATTERN_WIDTH) + (y % PATTERN_HEIGHT) * PATTERN_WIDTH + + x = x + 1 + } + + y = y + 1 +} + + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/resources/example-backgrounds/obj-4bpp-tiles.png b/roms/snes-test-roms/resources/example-backgrounds/obj-4bpp-tiles.png new file mode 100644 index 00000000..f273a533 Binary files /dev/null and b/roms/snes-test-roms/resources/example-backgrounds/obj-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/example-backgrounds/obj-oam.asm b/roms/snes-test-roms/resources/example-backgrounds/obj-oam.asm new file mode 100644 index 00000000..d9145aff --- /dev/null +++ b/roms/snes-test-roms/resources/example-backgrounds/obj-oam.asm @@ -0,0 +1,59 @@ +// OAM for the `obj-4bpp-tiles.png` sprite image +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +constant tileSize = 32 + +constant width = 4 +constant height = 2 + +constant startX = (256 - (width * tileSize)) / 2 +constant startY = (224 - (height * tileSize)) / 2 + +variable tile = 0 +variable nextTileRow = 16 + +variable y = 0 +while y < height { + + variable x = 0 + while x < width { + db startX + x * tileSize + db startY + y * tileSize + dw tile | 0x3000 // highest priority + + tile = tile + tileSize / 8 + if tile >= nextTileRow { + nextTileRow = nextTileRow + (tileSize / 8) * 16 + tile = nextTileRow - 16 + } + + x = x + 1 + } + y = y + 1 +} + + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp-palette.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp-palette.png new file mode 100644 index 00000000..d8c716da Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp-palette.png differ diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.png new file mode 100644 index 00000000..7d3b4865 Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.png differ diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.txt b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.txt new file mode 100644 index 00000000..fc1d4b82 --- /dev/null +++ b/roms/snes-test-roms/resources/hdma-hoffset-examples/shear-titlescreen-2bpp.txt @@ -0,0 +1,4 @@ +Created with Aseprite + +Font is: NimbusRoman-Bold, size 50 + diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp-palette.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp-palette.png new file mode 100644 index 00000000..73c0862d Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp-palette.png differ diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp.png new file mode 100644 index 00000000..29cf41d0 Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/two-vertical-bars-2bpp.png differ diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp-palette.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp-palette.png new file mode 100644 index 00000000..73c0862d Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp-palette.png differ diff --git a/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp.png b/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp.png new file mode 100644 index 00000000..150edf7f Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-hoffset-examples/vertical-bar-2bpp.png differ diff --git a/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1-palette.png b/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1-palette.png new file mode 100644 index 00000000..656fb2c4 Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1-palette.png differ diff --git a/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1.png b/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1.png new file mode 100644 index 00000000..f1c32204 Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-textbox-wipe/bg1.png differ diff --git a/roms/snes-test-roms/resources/hdma-textbox-wipe/bg2-palette.png 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b/roms/snes-test-roms/resources/hdma-textbox-wipe/bg3.png differ diff --git a/roms/snes-test-roms/resources/hdma-textbox-wipe/oam.asm b/roms/snes-test-roms/resources/hdma-textbox-wipe/oam.asm new file mode 100644 index 00000000..cb0a98de --- /dev/null +++ b/roms/snes-test-roms/resources/hdma-textbox-wipe/oam.asm @@ -0,0 +1,59 @@ + + +macro soldierFacingRight(evaluate xPos, evaluate yPos) { + variable ty = 0 + while ty < 3 { + variable tx = 0 + while tx < 2 { + db {xPos} + tx * 8 + db {yPos} + ty * 8 + db tx + ty * 2 + db 0x20 + + tx = tx + 1 + } + ty = ty + 1 + } +} + + +macro soldierFacingLeft(evaluate xPos, evaluate yPos) { + variable ty = 0 + while ty < 3 { + variable tx = 0 + while tx < 2 { + db {xPos} + 8 - tx * 8 + db {yPos} + ty * 8 + db tx + ty * 2 + db 0x60 + + tx = tx + 1 + } + ty = ty + 1 + } +} + + +soldierFacingRight(84, 84) +soldierFacingRight(90, 64) +soldierFacingRight(96, 44) + +soldierFacingLeft(156, 84) +soldierFacingLeft(150, 64) +soldierFacingLeft(144, 44) + + + +constant TO_FILL = 512 - pc() +if TO_FILL <= 0 { + error "Too many sprites" +} + +// Move all unused sprites offscreen +fill 512 - pc(), 256-8 + + +// Hi table +fill 32, 0 + + diff --git a/roms/snes-test-roms/resources/hdma-textbox-wipe/obj-4bpp-tiles.png b/roms/snes-test-roms/resources/hdma-textbox-wipe/obj-4bpp-tiles.png new file mode 100644 index 00000000..e697255d Binary files /dev/null and b/roms/snes-test-roms/resources/hdma-textbox-wipe/obj-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game-palette.png b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game-palette.png new file mode 100644 index 00000000..33a15827 Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game-palette.png differ diff --git a/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game.png b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game.png new file mode 100644 index 00000000..e0633e47 Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/game.png differ diff --git a/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map-palette.png b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map-palette.png new file mode 100644 index 00000000..64752432 Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map-palette.png differ diff --git a/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map.png b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map.png new file mode 100644 index 00000000..053674ab Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp-fadein-fadeout/map.png differ diff --git a/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-2bpp-tiles.png b/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-2bpp-tiles.png new file mode 100644 index 00000000..0892219b Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-2bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-tilemap.asm b/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-tilemap.asm new file mode 100644 index 00000000..5baef5a4 --- /dev/null +++ b/roms/snes-test-roms/resources/inidisp_extend_vblank/bg1-tilemap.asm @@ -0,0 +1,38 @@ +// A simple 2x2 repeating tile pattern tilemap +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// 32x32 tilemap +// 8x8 px tiles + +variable i = 0 +while i < 1024 { + dw (i & 1) | ((i / 16) & 2) + + i = i + 1 +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-4bpp-tiles.png b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-4bpp-tiles.png new file mode 100644 index 00000000..9f9077df Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-oam.asm b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-oam.asm new file mode 100644 index 00000000..fe9d0bfd --- /dev/null +++ b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo-oam.asm @@ -0,0 +1,63 @@ +// OAM for the spinning logo. +// +// Assumes small sprites are 16x16 px. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +constant X_OFFSET = (256 - 192) / 2 +constant Y_OFFSET = (224 - 80) / 2 + +// Add a single sprite to Oam +macro sprite(evaluate x, evaluate y, evaluate tile) { + // 0x30 = highest priority + db X_OFFSET + {x}, Y_OFFSET + {y}, {tile}, 0x30 +} + +// Adds 4 sprites to the Oam +macro halfRow(x, y, tile) { + sprite({x} + 0, {y}, {tile} + 0) + sprite({x} + 16, {y}, {tile} + 2) + sprite({x} + 32, {y}, {tile} + 4) + sprite({x} + 48, {y}, {tile} + 6) +} + + +variable y = 0 +while y < 5 { + halfRow( 0, y * 16, y * 32) + halfRow(64, y * 16, y * 32 + 8) + + y = y + 1 +} +halfRow(128, 0, 0xa0) +halfRow(128, 16, 0xa8) +halfRow(128, 32, 0xc0) +halfRow(128, 48, 0xc8) +halfRow(128, 64, 0xe0) + + +// vim: ft=bass-65816 ts=4 sw=4 et: + + diff --git a/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo.aseprite b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo.aseprite new file mode 100644 index 00000000..319ef302 Binary files /dev/null and b/roms/snes-test-roms/resources/inidisp_extend_vblank/spinning-logo.aseprite differ diff --git a/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.aseprite b/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.aseprite new file mode 100644 index 00000000..ec2abb0a Binary files /dev/null and b/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.aseprite differ diff --git a/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.png b/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.png new file mode 100644 index 00000000..8a9494be Binary files /dev/null and b/roms/snes-test-roms/resources/obj-tests/hex8-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/test-patterns/obj-digits-4bpp-tiles.png b/roms/snes-test-roms/resources/test-patterns/obj-digits-4bpp-tiles.png new file mode 100644 index 00000000..c2590386 Binary files /dev/null and b/roms/snes-test-roms/resources/test-patterns/obj-digits-4bpp-tiles.png differ diff --git a/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern-palette.png b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern-palette.png new file mode 100644 index 00000000..99a0b037 Binary files /dev/null and b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern-palette.png differ diff --git a/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.png b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.png new file mode 100644 index 00000000..1c4deae9 Binary files /dev/null and b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.png differ diff --git a/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.txt b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.txt new file mode 100644 index 00000000..84e6abdf --- /dev/null +++ b/roms/snes-test-roms/resources/test-patterns/scanline-bit-pattern.txt @@ -0,0 +1,78 @@ +# +# Image created using python. +# +# This image is used to display a binary 8-bit value by writing `value - scanline -1` +# to BGxVOFS on every Horizontal-Blank. +# +# The image is designed to be used in Mode 0 so 2 layers can be combined to +# form a 16-bit output # with a unique on and off CGRAM index for all 16 bits. +# + +import argparse + +from PIL import Image +from PIL.ImageColor import getrgb + +BIT_SET_COLOR_NAMES = [ + "red", "lime", "yellow", "lightblue", "lightpink", "cyan", "violet", "white" +] + +BIT_SET_COLORS = [ getrgb(c) for c in BIT_SET_COLOR_NAMES ] + +BIT_CLEAR_COLORS = [ + (r // 2, g // 2, b // 2) for r, g, b in BIT_SET_COLORS +] + +BG_COLOR = getrgb("black") + +def build_image() -> Image: + START_X = 0 + X_SPACING = 12 + + im = Image.new('RGB', (256, 256), BG_COLOR) + + for scanline in range(256): + for line in range(8): + if scanline & (1 << (7 - line)): + c = BIT_SET_COLORS[line] + else: + c = BIT_CLEAR_COLORS[line] + x = START_X + line * X_SPACING + im.putpixel((x, scanline), c) + im.putpixel((x + 1, scanline), c) + + return im + + +def build_pal_image() -> Image: + im = Image.new('RGB', (16, 2), BG_COLOR) + + for bit in range(8): + y = (bit // 4) + x = (bit % 4) * 4 + + im.putpixel((x + 2, y), BIT_CLEAR_COLORS[bit]) + im.putpixel((x + 3, y), BIT_SET_COLORS[bit]) + + return im + + +def main() -> argparse.Namespace: + parser = argparse.ArgumentParser() + parser.add_argument("-o", "--output-img", required=True, help="output image PNG file") + parser.add_argument("-p", "--output-pal", required=True, help="output palette PNG file") + + args = parser.parse_args() + + im = build_image() + im_pal = build_pal_image() + + im.save(args.output_img, "PNG") + im_pal.save(args.output_pal, "PNG") + + return args + + +if __name__ == "__main__": + main() + diff --git a/roms/snes-test-roms/resources/textbuffer/font-1bpp-map.inc b/roms/snes-test-roms/resources/textbuffer/font-1bpp-map.inc new file mode 100644 index 00000000..da16cc0d --- /dev/null +++ b/roms/snes-test-roms/resources/textbuffer/font-1bpp-map.inc @@ -0,0 +1,21 @@ + +namespace Font { + constant ZERO = 0x01 + constant CAPITAL_A = 0x0b + constant SPACE = 0x5f + constant NEW_LINE = 0x60 + constant COLON = 0x4e + constant FIRST_INVALID_CHARACTER = 0x61 + + // String mapping + map '0', 0x01, 10 + map 'A', 0x0b, 26 + map 'a', 0x25, 26 + map '!', 0x3f, 15 + map ':', 0x4e, 7 + map '[', 0x55, 6 + map '{', 0x5b, 4 + map ' ', 0x5f + map '\n', 0x60 +} + diff --git a/roms/snes-test-roms/resources/textbuffer/font-1bpp-tiles.png b/roms/snes-test-roms/resources/textbuffer/font-1bpp-tiles.png new file mode 100644 index 00000000..8d961e6c Binary files /dev/null and b/roms/snes-test-roms/resources/textbuffer/font-1bpp-tiles.png differ diff --git a/roms/snes-test-roms/src/65816-examples/arguments-after-jsr.asm b/roms/snes-test-roms/src/65816-examples/arguments-after-jsr.asm new file mode 100644 index 00000000..da806f17 --- /dev/null +++ b/roms/snes-test-roms/src/65816-examples/arguments-after-jsr.asm @@ -0,0 +1,476 @@ +// Fixed subroutine arguments after the JSR/JSL instruction examples. +// +// These example subroutines read a 16 or 24 bit argument after the `JSR` or +// `JSL` instruction and then pass that value to the `TextBuffer.PrintString` +// subroutine. +// +// +// SPDX-FileCopyrightText: © 2026 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "ARGUMENTS AFTER JSR" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(code1, 0x818000, 0x81ffff) +createCodeBlock(rodata0, 0x828000, 0x82ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + TextBuffer.VBlank() +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + + MainLoop: + TextBuffer.SetCursor(0, 0) + + + jsr PrintString_Word_LongIndexed + dw HelloWorld + + jsl PrintString_Word_AddrIndexed__far + dw HelloWorld + + + jsr PrintString_Long_StackIndirect + dl HelloWorld + + jsl PrintString_Long_StackIndirect__far + dl HelloWorld + + + jsr PrintString_Long_DpIndirectLong + dl HelloWorld + + jsl PrintString_Long_DpIndirectLong__far + dl HelloWorld + + + jsr WaitFrame + + jmp MainLoop +} + + + +// Reads a 16 bit address argument after the `JSR` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the `Absolute Long Indexed, X` addressing to read the +// subroutine argument. +// +// INPUT: +// * dw 16-bit string address in STRING_BANK +// +// DB = low-RAM +a8() +i16() +code() +function PrintString_Word_LongIndexed { + rep #$31 +a16() + // Load and increment return address + lda 1,s + tax + // carry clear + adc.w #2 + sta 1,s + + // X = 1 byte before the arguments + + // Read arguments + lda.l (pc() & 0xff0000) + 1,x + tax + + sep #$20 +a8() + + lda.b #STRING_BANK + jmp TextBuffer.PrintString +} + + + +// Reads a 16 bit address argument after the `JSL` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the `Absolute Indexed, X` addressing to read the +// subroutine argument. +// +// INPUT: +// * dw 16-bit string address in STRING_BANK +// +// DB = low-RAM +a8() +i16() +code(code1) +function PrintString_Word_AddrIndexed__far { + // Confirm caller and callee banks are different + assert((pc() >> 16) & 0x3f != 0) + + phb + + // Set DB to return bank + lda 4,s + pha + plb +// DB = return bank + + rep #$31 +a16() + // Load and increment return address + lda 2,s + tax + // carry clear + adc.w #2 + sta 2,s + + // X = 1 byte before the arguments + + // Read argument + lda.w 1,x + tax + + sep #$20 +a8() + + plb +// DB restored + + lda.b #STRING_BANK + jml _TB_PrintString__far +} + + + +// Reads a 24 bit address argument after the `JSR` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the `SR Indirect Indexed, Y` addressing to read the +// subroutine argument. +// +// INPUT: +// * dl 24-bit string address +// +// +// DB = low-RAM +a8() +i16() +code() +function PrintString_Long_StackIndirect { + phb + + phk + plb +// DB = PK + + rep #$31 +a16() + // Read word address argument + ldy.w #1 + lda (2,s),y + iny + iny + + tax + + // Read bank argument + lda (2,s),y + tay + + // Increment return address + lda 2,s + // carry clear + adc.w #3 + sta 2,s + + sep #$20 +a8() + + plb +// DB restored + + tya + jmp TextBuffer.PrintString +} + + + +// Reads a 24 bit address argument after the `JSL` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the `SR Indirect Indexed, Y` addressing to read the +// subroutine argument. +// +// DB = low-RAM +a8() +i16() +code(code1) +function PrintString_Long_StackIndirect__far { + // Confirm caller and callee banks are different + assert((pc() >> 16) & 0x3f != 0) + + phb + + // Set DB to caller's program bank + lda 4,s + pha + plb + + rep #$31 +a16() + // Read bank argument + ldy.w #1 + lda (2,s),y + iny + iny + + tax + + // Read bank argument + lda (2,s),y + tay + + // Increment return address + lda 2,s + // carry clear + adc.w #3 + sta 2,s + + sep #$20 +a8() + + plb + + tya + jml _TB_PrintString__far +} + + + +// Reads a 24 bit address argument after the `JSR` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the DP Indirect Long addressing modes to read the +// subroutine argument. +// +// DP = 0 +// DB = low-RAM +a8() +i16() +code() +function PrintString_Long_DpIndirectLong { +constant _ptr = zpTmpPtr + + lda.b #pc() >> 16 + sta.b _ptr + 2 + + rep #$31 +a16() + // Get and increment return address + lda 1,s + inc + sta.b _ptr + // carry clear + adc.w #3 - 1 + sta 1,s + + // Read word address argument + lda [_ptr] + tax + + sep #$20 +a8() + + // Read bank argument + ldy.w #2 + lda [_ptr],y + + jmp TextBuffer.PrintString +} + + + +// Reads a 24 bit address argument after the `JSL` and passes it to +// `TextBuffer.PrintString`. +// +// This example uses the DP Indirect Long addressing modes to read the +// subroutine argument. +// +// DP = 0 +// DB = low-RAM +a8() +i16() +code(code1) +function PrintString_Long_DpIndirectLong__far { + // Confirm caller and callee banks are different + assert((pc() >> 16) & 0x3f != 0) + +constant _ptr = zpTmpPtr + + // Get return bank + lda 3,s + sta.b _ptr + 2 + + rep #$31 +a16() + // Get and increment return address + lda 1,s + inc + sta.b _ptr + // carry clear + adc.w #3 - 1 + sta 1,s + + + // Read subroutine argument + lda [_ptr] + tax + + sep #$20 +a8() + ldy.w #2 + lda [_ptr],y + + + jml _TB_PrintString__far +} + + +// Hack to call `TextBuffer.PrintString` from program bank 0x81 +// +// DB = low-RAM +a8() +i16() +code() +function _TB_PrintString__far { + jsr TextBuffer.PrintString + rtl +} + + +rodata(rodata0) + +constant STRING_BANK = pc() >> 16 + +HelloWorld: + db "Hello World!\n", 0 + + +namespace Resources { + +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/_common/assert.inc b/roms/snes-test-roms/src/_common/assert.inc new file mode 100644 index 00000000..d9f7a4d8 --- /dev/null +++ b/roms/snes-test-roms/src/_common/assert.inc @@ -0,0 +1,66 @@ +// common/assert.inc +// ================= +// +// Macros that break assembly if a test fails. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// Asserts than an expression is true +// Breaks assembly if expression if false +macro assert(test) { + if !({test}) { + error "{test}" + } +} + +// Asserts than an expression is a power of two +// Breaks assembly if expression if false +macro assertPowerOfTwo(evaluate test) { + if ({test} & ({test} - 1)) != 0 { + error "{test} is not a power of 2" + } +} + +// Asserts that a variable is inside zero page +// Breaks assembly if variable is not zero page +macro assertZeroPage(var) { + evaluate addr = {var} + if {addr} >= 0x100 && ({addr} < 0x7e0000 || {addr} >= 0x7e0100) { + error "{var} is not inside zero page" + } +} + +// Asserts that a variable is inside low-RAM +// Breaks assembly if variable is not in low-RAM +macro assertLowRam(var) { + evaluate addr = {var} + if {addr} >= 0x2000 && ({addr} < 0x7e0000 || {addr} >= 0x7e2000) { + error "{var} is not inside low-RAM" + } +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/cpu.inc b/roms/snes-test-roms/src/_common/cpu.inc new file mode 100644 index 00000000..fafe8832 --- /dev/null +++ b/roms/snes-test-roms/src/_common/cpu.inc @@ -0,0 +1,110 @@ +// common/cpu.inc +// ============== +// +// Provides a mechanism for managing the processor register sizes. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +variable __CPU__.aSize = 0 +variable __CPU__.iSize = 0 + +macro sep(evaluate v) { + if ({v} & 0x20) { + __CPU__.aSize = 8 + } + if ({v} & 0x10) { + __CPU__.iSize = 8 + } + + sep #{v} +} + +macro rep(evaluate v) { + if ({v} & 0x20) { + __CPU__.aSize = 16 + } + if ({v} & 0x10) { + __CPU__.iSize = 16 + } + + rep #{v} +} + +macro a8() { + __CPU__.aSize = 8 +} + +macro a16() { + __CPU__.aSize = 16 +} + +macro au() { + __CPU__.aSize = 0 +} + +macro i8() { + __CPU__.iSize = 8 +} + +macro i16() { + __CPU__.iSize = 16 +} + +macro iu() { + __CPU__.iSize = 0 +} + +macro punknown() { + __CPU__.aSize = 0 + __CPU__.iSize = 0 +} + +macro assert8a() { + if __CPU__.aSize != 8 { + error "require an 8 bit A" + } +} + +macro assert16a() { + if __CPU__.aSize != 16 { + error "require a 16 bit A" + } +} + +macro assert8i() { + if __CPU__.iSize != 8 { + error "require an 8 bit Index register" + } +} + +macro assert16i() { + if __CPU__.iSize != 16 { + error "require a 16 bit Index register" + } +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/enum.inc b/roms/snes-test-roms/src/_common/enum.inc new file mode 100644 index 00000000..ea10d7a7 --- /dev/null +++ b/roms/snes-test-roms/src/_common/enum.inc @@ -0,0 +1,96 @@ +// common/enum.inc +// =============== +// +// Turns the current scope into an enumeration. +// +// Enum constants are declared with the enum macro. +// +// NOTE: An enum cannot be nested in a scope +// +// usage: +// namespace functionTable { +// createEnum(0, 2) +// enum(initPtr) // 0 +// enum(deletePtr) // 2 +// enum(processPtr) // 4 +// endEnum() // (optional but highly recommended) +// } +// +// The `createEnum()`/`endEnum()` pair will create the following constants: +// +// * `__ENUM__.first`: the first value in the enum +// * `__ENUM__.last`: the last value in the enum +// * `__ENUM__.increment`: the difference between two successive enum values +// * `__ENUM__.count`: the number of items in the enum +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +inline createEnum(start, increment) { + if {increment} < 1 { + error "increment is invalid" + } + + constant __ENUM__.first = {start} + constant __ENUM__.increment = {increment} + evaluate __ENUM__.current = {start} +} +inline createEnum(start) { + createEnum({start}, 1) +} +inline createEnum() { + createEnum(0, 1) +} + +// NOTE: This tag is optional but highly recommended +inline endEnum() { + if !{defined __ENUM__.current} { + error "Current scope is not an enum" + } + if {defined __ENUM__.closed} { + error "Enum already closed" + } + if {__ENUM__.current} == __ENUM__.first { + error "Expected at least one enum()" + } + evaluate __ENUM__.closed = 1 + constant __ENUM__.last = {__ENUM__.current} - __ENUM__.increment + constant __ENUM__.count = ({__ENUM__.current} - __ENUM__.first) / __ENUM__.increment +} + +inline enum(id) { + if {defined __ENUM__.closed} { + error "Enum is closed, cannot add more values" + } + if !{defined __ENUM__.current} { + error "Current scope is not an enum" + } + + constant {id} = {__ENUM__.current} + evaluate __ENUM__.current = {__ENUM__.current} + __ENUM__.increment +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/functiontable.inc b/roms/snes-test-roms/src/_common/functiontable.inc new file mode 100644 index 00000000..dd0af0c3 --- /dev/null +++ b/roms/snes-test-roms/src/_common/functiontable.inc @@ -0,0 +1,61 @@ +// common/functiontable.inc +// ======================== +// +// Macros to build a function table from a given struct. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// Automatically builds the function table from a given struct +// +// NOTE: will change the current romblock to code. +// +// PARAM: struct - the struct that contains the function table +// PARAM: module - the struct that the table is called in (solves visibility problem) +// PARAM: tableName - the name of the function table (defualt FunctionTable) +inline buildFunctionTable(struct, module, tableName) { + code() + {tableName}: { + _buildFunctionTable_structs({struct}, {module}) + } +} +inline buildFunctionTable(struct, module) { + buildFunctionTable({struct}, {module}, FunctionTable) +} + +macro _buildFunctionTable_structs(struct, module) { + validateStructIsBase({struct}) + + evaluate n = 0 + while {n} < {{struct}.__STRUCT__.fields.size} { + assert({{struct}.__STRUCT__.fields.{n}.size} == 2) + dw {module}.{{struct}.__STRUCT__.fields.{n}.name} + + evaluate n = {n} + 1 + } +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/memory.inc b/roms/snes-test-roms/src/_common/memory.inc new file mode 100644 index 00000000..b307800f --- /dev/null +++ b/roms/snes-test-roms/src/_common/memory.inc @@ -0,0 +1,450 @@ +// common/memory.inc +// ================= +// +// Handles ROM and RAM mapping. +// +// The following need to be defined before including this file: +// +// * MEMORY_MAP - set to one of the values in the MEMORY_MAP scope +// * ROM_SIZE - the ROM size in Mbits +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +namespace MEMORY_MAP { + constant LOROM = 0x20 + constant HIROM = 0x21 +} + +if !{defined MEMORY_MAP} { + error "MEMORY_MAP is not defined" +} + +if !{defined ROM_SIZE} { + error "ROM_SIZE is not defined (value is in Mbits)" +} +if {ROM_SIZE} > 32 { + error "ROM_SIZE > 32 Mbits is not supported" +} else if {ROM_SIZE} < 1 { + error "ROM_SIZE is invalid" +} + +namespace private { + if MEMORY_MAP.{MEMORY_MAP} == MEMORY_MAP.LOROM { + macro seek(offset) { + origin (({offset} & 0x3f0000) >> 1) | ({offset} & 0x7fff) + base {offset} + } + + macro checkBlockIsValid(name, start, end) { + if (({end} & 0x3f0000) >> 1 | ({end} & 0x7fff)) > ({ROM_SIZE} * 0x20000) { + error "ROM block `{name}` is outside ROM_SIZE" + } + if ({start} & 0xFFFF) < 0x8000 { + error "ROM Block `{name}` is not in ROM area" + } + } + + } else if MEMORY_MAP.{MEMORY_MAP} == MEMORY_MAP.HIROM { + macro seek(offset) { + origin {offset} & 0x3fffff + base {offset} + } + + macro checkBlockIsValid(name, start, end) { + if ({end} & 0x3fffff) > ({ROM_SIZE} * 0x20000) { + error "ROM block `{name}` is outside ROM_SIZE" + } + if (({start} & 0x7fffff) < 0x3f0000) && (({start} & 0xFFFF) < 0x8000) { + error "ROM Block `{name}` is not in ROM area" + } + } + } else { + error "Unknown memory map `{MEMORY_MAP}`" + } + + macro checkBlockIsUnused(evaluate start, evaluate end) { + evaluate n = 0 + while {n} < {__MEMORY__.romBlockNames.count} { + define b = __MEMORY__.romBlocks.{__MEMORY__.romBlockNames.{n}} + + if ({start} & 0x3fffff) <= ({b}.end & 0x3fffff) && ({end} & 0x3fffff) >= ({b}.start & 0x3fffff) { + error "ROM Block `{name}` overlaps ROM block `{bn}`" + } + + evaluate n = {n} + 1 + } + } +} + + +// Pad output file to ROM_SIZE +origin {ROM_SIZE} * 1024 * 1024 / 8 - 1 +db 0 +origin 0 + + +// When set to non-zero then no more memory can be created or allocated. +variable __MEMORY__.finalized = 0 + +// Number of ROM Blocks defined in the `__MEMORY__.romBlockNames.` defines. +// +// It is a define because editing of romBlockNames is only done on the root scope. +evaluate __MEMORY__.romBlockNames.count = 0 + + +// Creates a new data block in a given ROM location. +// +// The data block is accessed with the `rodata` macro. +// +// This macro MUST BE called in the root scope. +// +// PARAMS: +// * id - the name of the block +// * start - the starting address of the block +// * end - the ending address of the block +inline createDataBlock(name, evaluate start, evaluate end) { + if __MEMORY__.finalized { + error "Memory module has been finalized, cannot create Data Block" + } + + if {defined __MEMORY__.romBlocks.{name}.start} { + error "ROM Block `{name}` already exists" + } + + private.checkBlockIsValid({name}, {start}, {end}) + + if {end} < {start} { + error "ROM Block `{name}` cannot have end before start" + } + if ({start} >> 16) != ({end} >> 16) { + error "ROM Block `{name}` can not cross data banks" + } + if ({start} & 0x3fffff) <= 0x00ffff && ({end} & 0x3fffff) >= 0x00ffb0 { + error "ROM Block `{name}` cannot touch the SNES Header" + } + + private.checkBlockIsUnused({start}, {end}) + + define __MEMORY__.romBlocks.{name} + variable __MEMORY__.romBlocks.{name}.pos = {start} + constant __MEMORY__.romBlocks.{name}.index = {__MEMORY__.romBlockNames.count} + constant __MEMORY__.romBlocks.{name}.start = {start} + constant __MEMORY__.romBlocks.{name}.end = {end} + + define __MEMORY__.romBlockNames.{__MEMORY__.romBlockNames.count} = {name} + evaluate __MEMORY__.romBlockNames.count = {__MEMORY__.romBlockNames.count} + 1 +} + + +// Index of the current ROM block. +variable __MEMORY__.currentRomBlockIndex = -1 + +// seeks to the next position in the selected block id +macro rodata(id) { + if __MEMORY__.finalized { + error "Memory module has been finalized, cannot seek to Data Block" + } + + if !{defined __MEMORY__.romBlocks.{id}} { + error "Rom block {id} does not exist" + } + + if __MEMORY__.currentRomBlockIndex >= 0 { + evaluate cbi = __MEMORY__.currentRomBlockIndex + define cb = {__MEMORY__.romBlockNames.{cbi}} + + if (pc() - 1) > __MEMORY__.romBlocks.{cb}.end { + error "Overflow in rom block {cb}" + } + __MEMORY__.romBlocks.{cb}.pos = pc() + } + + __MEMORY__.currentRomBlockIndex = __MEMORY__.romBlocks.{id}.index + private.seek(__MEMORY__.romBlocks.{id}.pos) + + if pc() >= __MEMORY__.romBlocks.{id}.end { + error "Overflow in rom block {id}" + } +} + +// duplicate of `createDataBlock`, written for clarity. +inline createCodeBlock(id, start, end) { + createDataBlock({id}, {start}, {end}) +} + +// duplicate of `rodata` written for clarity. +macro code(id) { + rodata({id}) +} + +macro code() { + code(code) +} + + +// Creates a constant containing the starting address of a block +inline storeBlockStart(name, blockId) { + constant {name} = __MEMORY__.romBlocks.{blockId}.start +} + +// Creates a constant containing the total number bytes used by a block. +// +// This value is NOT the current number of bytes used. Instead the +// constant will contain the total number of bytes used by the block +// when `finalizeMemory` is called. +inline storeBlockUsed(name, blockId) { + constant {name} = __MEMORY__.romBlocks.{blockId}.last - __MEMORY__.romBlocks.{blockId}.start +} + +// Creates a constant containing the final number of elements in a +// fixed-sized table block +// +// {name} will contain the value of ( / ) +// +// This value is NOT the current block count. Instead the constant will +// contain the total number of elements in the block when +// `finalizeMemory` is called. +// program. +inline storeBlockCount(name, blockId, evaluate elementSize) { + if {elementSize} <= 0 { + error "Invalid elementSize" + } + + constant {name} = (__MEMORY__.romBlocks.{blockId}.last - __MEMORY__.romBlocks.{blockId}.start) / {elementSize} +} + + +constant __MEMORY__.blockStack.max = 4 +variable __MEMORY__.blockStack.size = 0 +variable __MEMORY__.blockStack.0 = -1 +variable __MEMORY__.blockStack.1 = -1 +variable __MEMORY__.blockStack.2 = -1 +variable __MEMORY__.blockStack.3 = -1 + +// pushes the current code/data block onto the stack +macro pushBlock() { + evaluate stackIndex = __MEMORY__.blockStack.size + __MEMORY__.blockStack.{stackIndex} = __MEMORY__.currentRomBlockIndex + + __MEMORY__.blockStack.size = __MEMORY__.blockStack.size + 1 + + if __MEMORY__.blockStack.size >= __MEMORY__.blockStack.max { + error "block stack is too deep" + } +} + +// pulls the current code/data block from the stack +macro popBlock() { + if __MEMORY__.blockStack.size <= 0 { + error "No block stack" + } + + __MEMORY__.blockStack.size = __MEMORY__.blockStack.size - 1 + + evaluate stackIndex = __MEMORY__.blockStack.size + evaluate blockIndex = __MEMORY__.blockStack.{stackIndex} + rodata({__MEMORY__.romBlockNames.{blockIndex}}) +} + + + +// Number of ROM Blocks defined in the `__MEMORY__.ramBlockNames.` defines. +// +// It is a define because editing of ramBlockNames is only done on the root scope. +evaluate __MEMORY__.ramBlockNames.count = 0 + +// Create a new ram block with a given position and size. +// +// This macro MUST BE called in the root scope. +// +// RAM blocks can overlap. This is to reuse memory in different contexts. +// +// The RAM block is accessed with the `allocate` macro. +// +// Information about the block can be accessed by the following +// constants and variables: +// +// * `__MEMORY__.ramBlocks.{id}.pos` - the current position of the block +// * `__MEMORY__.ramBlocks.{id}.size` - the number of bytes assigned to the +// * `__MEMORY__.ramBlocks.{id}.remaining` - the number of bytes remaining in the block +// * `__MEMORY__.ramBlocks.{id}.start` - the starting address of the block +// * `__MEMORY__.ramBlocks.{id}.end` - the last address of the block +inline createRamBlock(id, evaluate start, evaluate end) { + if __MEMORY__.finalized { + error "Memory module has been finalized, cannot create RAM Block" + } + + if {defined __MEMORY__.ramBlocks.{id}} { + error "RAM Block `{id}` already exists" + } + if {end} < {start} { + error "RAM Block `{id}` cannot have end before start" + } + + define __MEMORY__.ramBlockNames.{__MEMORY__.ramBlockNames.count} = {id} + evaluate __MEMORY__.ramBlockNames.count = {__MEMORY__.ramBlockNames.count} + 1 + + define __MEMORY__.ramBlocks.{id} + constant __MEMORY__.ramBlocks.{id}.start = {start} + constant __MEMORY__.ramBlocks.{id}.end = {end} + + variable __MEMORY__.ramBlocks.{id}.pos = {start} + variable __MEMORY__.ramBlocks.{id}.remaining = {end} - {start} + 1 + variable __MEMORY__.ramBlocks.{id}.size = 0 +} + +// Allocate memory from the RAM block to a given constant name +inline allocate(name, blockId, evaluate size) { + if __MEMORY__.finalized { + error "Memory module has been finalized, cannot allocate memory" + } + + if !{defined __MEMORY__.ramBlocks.{blockId}} { + error "block {blockId} does not exist" + } + + if (__MEMORY__.ramBlocks.{blockId}.remaining < {size}) { + error "Cannot allocate {size} byte(s) from block {blockId}: Not enough space" + } + + constant {name} = __MEMORY__.ramBlocks.{blockId}.pos + + __MEMORY__.ramBlocks.{blockId}.pos = __MEMORY__.ramBlocks.{blockId}.pos + {size} + __MEMORY__.ramBlocks.{blockId}.size = __MEMORY__.ramBlocks.{blockId}.size + {size} + __MEMORY__.ramBlocks.{blockId}.remaining = __MEMORY__.ramBlocks.{blockId}.remaining - {size} +} + + +// Finalizes the memory module. +// +// Prints memory usage if `SHOW_MEMORY_USAGE` is defined. +// +// This macro MUST BE called ONCE at the end of the program. +inline finalizeMemory() { + // update position of current block + rodata(code) + + if __MEMORY__.finalized { + error "Memory module has already been finalized" + } + __MEMORY__.finalized = 1 + + if __MEMORY__.blockStack.size != 0 { + error "Block stack is not empty" + } + + _finalizeMemory_buildUseConstants(0) + + if {defined SHOW_MEMORY_USAGE} { + __printMemoryUsage() + } +} + +inline _finalizeMemory_buildUseConstants(evaluate n) { + // build used constants + if {n} < {__MEMORY__.romBlockNames.count} { + constant __MEMORY__.romBlocks.{__MEMORY__.romBlockNames.{n}}.last = __MEMORY__.romBlocks.{__MEMORY__.romBlockNames.{n}}.pos + _finalizeMemory_buildUseConstants({n} + 1) + } +} + + +macro __printMemoryUsage() { + print "\n" + print "DATA USAGE:\n" + print "\n" + print "Address | Size | Used | Free | Block Name\n" + print "--------+---------+---------+---------+--------------------------\n" + print " 00ff80 | 80 | 80 | 0 | SNES Header\n" + + evaluate totalSize = 80 + evaluate totalUsed = 80 + + evaluate n = 0 + while {n} < {__MEMORY__.romBlockNames.count} { + define blockName = {__MEMORY__.romBlockNames.{n}} + define block = __MEMORY__.romBlocks.{blockName} + + evaluate size = {block}.end - {block}.start + 1 + evaluate used = {block}.pos - {block}.start + + evaluate totalSize = {totalSize} + {size} + evaluate totalUsed = {totalUsed} + {used} + + print " " + print_hex(6, {block}.start) + print " | " + print_padded(7, {size}) + print " | " + print_padded(7, {used}) + print " | " + print_padded(7, {size} - {used}) + print " | {blockName}\n" + + evaluate n = {n} + 1 + } + + print "========+=========+=========+=========+==========================\n" + + print " TOTAL | " + print_padded(7, {totalSize}) + print " | " + print_padded(7, {totalUsed}) + print " | " + print_padded(7, {totalSize} - {totalUsed}) + print "\n" + + + print "\n" + print "\n" + print "RAM USAGE:\n" + print "\n" + print "Address | Size | Used | Free | Block Name\n" + print "--------+---------+---------+---------+--------------------------\n" + + // Don't print totals for RAM blocks as they may overlap + + evaluate n = 0 + while {n} < {__MEMORY__.ramBlockNames.count} { + define blockName = {__MEMORY__.ramBlockNames.{n}} + define block = __MEMORY__.ramBlocks.{blockName} + + print " " + print_hex(6, {block}.start) + print " | " + print_padded(7, {block}.end - {block}.start + 1) + print " | " + print_padded(7, {block}.size) + print " | " + print_padded(7, {block}.remaining) + print " | {blockName}\n" + + evaluate n = {n} + 1 + } +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/print.inc b/roms/snes-test-roms/src/_common/print.inc new file mode 100644 index 00000000..377db091 --- /dev/null +++ b/roms/snes-test-roms/src/_common/print.inc @@ -0,0 +1,91 @@ +// common/print.inc +// ================ +// +// Macros for extended printing to the screen. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// Prints a decimal integer number with padding +// +// PARAMS: +// * width - the printing width +// * value - the value to print +macro print_padded(evaluate width, evaluate value) { + variable w = {width} - 1 + variable v = {value} + + if v < 0 { + v = 0 - v + w = w - 1 + } + + while w > 0 { + if v < 10 { + print " " + } + w = w - 1 + v = v / 10 + } + + print {value} +} + +// Prints a hexadecimal number with padding +// +// NOTE: cannot print negative numbers +// +// PARAMS: +// * width - the printing width +// * value - the value to print +macro print_hex(evaluate width, evaluate value) { + if {width} > 0 || {value} > 0 { + print_hex({width} - 1, {value} / 16) + + evaluate d = {value} % 16 + if {d} < 10 { + print {d} + } else if {d} == 10 { + print "a" + } else if {d} == 11 { + print "b" + } else if {d} == 12 { + print "c" + } else if {d} == 13 { + print "d" + } else if {d} == 14 { + print "e" + } else if {d} == 15 { + print "f" + } + } +} + +macro print_hex(evaluate value) { + print_hex(1, {value}) +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/registers.inc b/roms/snes-test-roms/src/_common/registers.inc new file mode 100644 index 00000000..0fc8d86d --- /dev/null +++ b/roms/snes-test-roms/src/_common/registers.inc @@ -0,0 +1,1675 @@ +// common/registers.inc +// ==================== +// +// SNES Register Defines. +// +// Names and flags taken from Anomie's SNES Documents and nocash's +// fullsnes document. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// a Data Bank that can access the registers. +constant REGISTER_DB = 0x80 + + +// Tile Map Format +// +// cccccccc +// vhopppcc +// +// cccccccccc = character of tile +// ppp = palette +// o = order +// h = horizontal flip +// v = vertical flip +namespace Tilemap { + namespace char { + constant mask = %0000001111111111 + constant shift = 0 + } + namespace palette { + constant mask = %0001110000000000 + constant shift = 10 + } + + constant order = %0010000000000000 + constant hFlip = %0100000000000000 + constant vFlip = %1000000000000000 +} + +namespace TilemapH { + namespace char { + constant mask = %00000011 + constant shift = 0 + } + namespace palette { + constant mask = %00011100 + constant shift = 10 + } + + constant order = %00100000 + constant hFlip = %01000000 + constant vFlip = %10000000 +} + +// Palette format +// +// -bbbbbgggggrrrrr +// +// bbbbb = blue value +// ggggg = green value +// rrrrr = red value +namespace Palette { + namespace blue { + constant mask = %0111110000000000 + constant shift = 10 + } + namespace green { + constant mask = %0000001111100000 + constant shift = 5 + } + namespace red { + constant mask = %0000000000011111 + constant shift = 0 + } +} + +expression ToPalette(r, g, b) = ((b & 31) << 10) | ((g & 31) << 5) | (r & 31) + + +// OAM Table 0 Format +// +// xxxxxxxx +// yyyyyyyy +// cccccccc +// vhoopppN +// +// xxxxxxxx = lower 8 bits of x position of object +// yyyyyyyy = y position of object +// cccccccc = character of object +// N = Character Table to use(equivalent to 9th bit of c) +// ppp = palette +// oo = order +// h = horizontal flip +// v = vertical flip +namespace OamFormat { + constant xPos = 0 + constant yPos = 1 + constant char = 2 + constant attr = 3 + + constant size = 4 + + constant charAttr = 2 + + namespace attr { + namespace palette { + constant mask = %00001110 + constant shift = 1 + } + + namespace order { + constant mask = %00110000 + constant shift = 4 + } + + constant table = %00000001 + constant hFlip = %01000000 + constant vFlip = %10000000 + } + + namespace charAttr { + namespace char { + constant mask = %0000000111111111 + constant shift = 0 + } + namespace palette { + constant palette = %0000111000000000 + constant shift = 9 + } + namespace order { + constant order = %0011000000000000 + constant shift = 12 + } + constant table = %0000000100000000 + constant hflip = %0100000000000000 + constant vflip = %1000000000000000 + } +} + + + +// Screen Display +//(write, any) +// +// f---bbbb +// +// f = Force Blank +// bbbb = Screen Brightnes, 0 = Dull, 16 = max +constant INIDISP = 0x2100 + +namespace INIDISP { + constant force = %10000000 + + namespace brightness { + constant mask = %00001111 + constant shift = 0 + constant full = 15 + } +} + + + +// Object Size and Chr Address +//(write, v-blank) +// +// sssnnbbb +// +// sss = Object Size +// nn = Name Select +// bbb = Name Base Address(addr>>14) +constant OBSEL = 0x2101 + +namespace OBSEL { + namespace size { + constant mask = %11100000 + + constant s8_16 = %00000000 + constant s8_32 = %00100000 + constant s8_64 = %01000000 + constant s16_32 = %01100000 + constant s16_64 = %10000000 + constant s32_64 = %10100000 + constant s16x32_32x64 = %11000000 + constant s16x32_32x32 = %11100000 + } + + namespace name { + constant mask = %00011000 + constant shift = 3 + } + namespace base { + constant mask = %00000111 + constant shift = 0 + + /// Object Tile Address segments sizes. + /// The VRAM address used is 16384 * `bbb` + constant walign = 8192 + constant align = 16384 + } +} + + + +// OAM Address and Priority +//(write, v-blank) +// +// p------b aaaaaaaa +// +// p = Obj priority bit +// b = Table access(0 = Low Table, 1 = High Table) +// aaaaaaaa = Address +constant OAMADDL = 0x2102 +constant OAMADDH = 0x2103 + +namespace OAMADDH { + constant lowTable = %00000000 + constant hiTable = %00000001 + + /// Sprite Priority Select + /// When set, `OAMADDL` handles sprite priority. + constant priority = %10000000 +} + +// Word Access of OAMADDL/OAMADDH +//(write, word, v-blank) +constant OAMADD = 0x2102 + +namespace OAMADD { + namespace address { + constant mask = %0000000011111111 + constant shift = 0 + } + constant hiTable = %0000000100000000 + constant priority = %1000000000000000 +} + + + +// OAM Data Write +//(write, write twice, v-blank) +constant OAMDATA = 0x2104 + + + +// BG Mode and Character Size +//(write, h-blank, v-blank) +// +// DCBAemmm +// +// A/B/C/D = Character size for BG1 - BG4(1 = 16x16 tiles, 0 = 8x8 tiles) +// e = Mode 1 BG3 Priority +// mmm = BG Mode +constant BGMODE = 0x2105 + +namespace BGMODE { + namespace mode { + constant mask = %00000111 + } + constant mode0 = %00000000 + constant mode1 = %00000001 + constant mode1Bg3 = %00001001 + constant mode2 = %00000010 + constant mode3 = %00000011 + constant mode4 = %00000100 + constant mode5 = %00000101 + constant mode6 = %00000110 + constant mode7 = %00000111 + + namespace size { + constant mask = %11110000 + + constant bg1 = %00010000 + constant bg2 = %00100000 + constant bg3 = %01000000 + constant bg4 = %10000000 + } +} + + +// Screen Pixelation +//(write, h-blank, v-blank) +// +// xxxxDCBA +// +// A/B/C/D = Affect BG1 - BG4 +// xxxx = pixel size(0 to 16) +constant MOSAIC = 0x2106 + +namespace MOSAIC { + namespace affect { + constant mask = %00001111 + + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + } + + namespace size { + constant mask = %11110000 + constant shift = 4 + } +} + + + +// BG Tilemap Address and Size +//(write, v-blank) +// +// aaaaaass +// +// aaaaaa = Tilemap base address in VRAM(Addr>>10) +// ss = Tilemap size +constant BG1SC = 0x2107 +constant BG2SC = 0x2108 +constant BG3SC = 0x2109 +constant BG4SC = 0x210A + +namespace BGXSC { + namespace base { + constant mask = %11111100 + constant shift = 2 + + /// Address segments sizes. + /// The VRAM address used is 2048 * `aaaaaa` + constant walign = 1024 + constant align = 2048 + } + + namespace map { + constant mask = %00000011 + + constant s32x32 = %00000000 + constant s64x32 = %00000001 + constant s32x64 = %00000010 + constant s64x64 = %00000011 + } +} + + + +// BG1/2 Character Address +//(write, v-blank) +// +// bbbbaaaa +// +// aaaa - Base address for BG1(Addr>>13) +// bbbb - Base address for BG2(Addr>>13) +constant BG12NBA = 0x210B + +namespace BG12NBA { + namespace bg1 { + constant mask = %00001111 + constant shift = 0 + } + + namespace bg2 { + constant mask = %11110000 + constant shift = 4 + } + + /// Address segments sizes. + /// The VRAM address used is 8192 * `aaaa` + constant walign = 4096 + constant align = 8192 +} + + +// BG 3/4 Character Address +//(write, v-blank) +// +// bbbbaaaa +// +// aaaa - Base address for BG3(Addr>>13) +// bbbb - Base address for BG4(Addr>>13) +constant BG34NBA = 0x210C + +namespace BG34NBA { + namespace bg3 { + constant mask = %00001111 + constant shift = 0 + } + + namespace bg4 { + constant mask = %11110000 + constant shift = 4 + } + + /// Address segments sizes. + /// The VRAM address used is 8192 * `aaaa` + constant walign = 4096 + constant align = 8192 +} + + + +// BG Horizontal Scroll +//(write, write twice, h-blank, v-blank) +// +// ------xx xxxxxxxx +// +// x = BG Horizontal offset +constant BG1HOFS = 0x210D +constant BG2HOFS = 0x210F +constant BG3HOFS = 0x2111 +constant BG4HOFS = 0x2113 + +// Mode 7 BG Horizontal Scroll +//(write, write twice, h-blank, v-blank) +// +// ---mmmmm mmmmmmmm +// +// m = Mode 7 BG Offset(M7HOFS only) +constant M7HOFS = 0x210D + + + +// BG Vertical Scroll +//(write, write twice, h-blank, v-blank) +// +// ------yy yyyyyyyy +// +// y = BG Vertical offset +constant BG1VOFS = 0x210E +constant BG2VOFS = 0x2110 +constant BG3VOFS = 0x2112 +constant BG4VOFS = 0x2114 + +// Mode 7 BG Vertical Scroll +//(write, write twice, h-blank, v-blank) +// +// ---mmmmm mmmmmmmm +// +// m = Mode 7 BG1 Offset(M7VOFS only) +constant M7VOFS = 0x210E + + + +// Video Port Control +//(write, v-blank) +// +// i---mmii +// +// i = Address increment mode +// ii = Address increment amount +// mm = Address remapping +// +constant VMAIN = 0x2115 + +namespace VMAIN { + namespace increment { + constant mask = %00000011 + + constant by1 = %00000000 + constant by32 = %00000001 + constant by128 = %00000010 + } + + namespace remap { + constant mask = %00001100 + + constant _8bits = %00000100 + constant _9bits = %00001000 + constant _10bits = %00001100 + } + + namespace incrementMode { + constant mask = %10000000 + + constant low = %00000000 + constant high = %10000000 + } +} + + + +// VRAM Word Address +//(write, word, v-blank) +constant VMADD = 0x2116 +constant VMADDL = 0x2116 +constant VMADDH = 0x2117 + + + +// VRAM Data Write +//(write, word, v-blank) +constant VMDATA = 0x2118 +constant VMDATAL = 0x2118 +constant VMDATAH = 0x2119 + + + +// Mode 7 Select +//(write, v-blank) +// +// oo----vh +// +// oo = Out of screen area +// 00 - Screen Repeat +// 01 - Color 0 +// 10 - Tile 0 +// h = horizontal flip +// v = vertical flip +constant M7SEL = 0x211A + +namespace M7SEL { + namespace outOfScreen { + constant mask = %11000000 + + constant repeat = %00000000 + constant color0 = %10000000 + constant tile0 = %11000000 + } + + constant hFlip = %00000001 + constant vFlip = %00000010 +} + + + +// Mode 7 Matrix +//(write, write twice, 1:7:8 signed fixed point, h-blank, v-blank) +// +// The Matrix transformation is: +// [ X ] [ M7A M7B ] [ SX + M7HOFS - M7X ] [ M7X ] +// [ Y ] = [ M7C M7D ] * [ SY + M7VOFS - M7Y ] + [ M7Y ] +// +// Where SX and SY are screen coordinates +constant M7A = 0x211B +constant M7B = 0x211C +constant M7C = 0x211D +constant M7D = 0x211E + +// Mode 7 Center +//(write, write twice, 13 bit signed integer, h-blank, v-blank) +constant M7X = 0x211F +constant M7Y = 0x2120 + + + +// CGRAM Address +//(write, h-blank, v-blank) +constant CGADD = 0x2121 + +namespace CGADD { + /// Starting color of the OAM palette + constant objPalette = 128 +} + + + +// CGRAM Data Write +//(write, write twice, h-blank, v-blank) +// +// -bbbbbgg gggrrrrr +constant CGDATA = 0x2122 + + + +// Window Mask Settings +//(write, h-blank, v-blank) +// +// For each nibble: +// EIei +// +// e = Enable Window 1 +// i = Window 1 In/Out(1 = Inside, 0 = Outside) +// E = Enable Window 2 +// I = Window 2 In/Out(1 = Inside, 0 = Outside) +// +constant W12SEL = 0x2123 +constant W34SEL = 0x2124 +constant WOBJSEL = 0x2125 + +namespace WSEL { + namespace win1 { + constant enable = %0010 + constant inside = %0000 + constant outside = %0001 + } + + namespace win2 { + constant enable = %1000 + constant inside = %0000 + constant outside = %0100 + } +} + +namespace W12SEL { + namespace bg1 { + constant mask = %00001111 + constant shift = 0 + } + namespace bg2 { + constant mask = %11110000 + constant shift = 4 + } +} + +namespace W34SEL { + namespace bg3 { + constant mask = %00001111 + constant shift = 0 + } + namespace bg4 { + constant mask = %11110000 + constant shift = 4 + } +} + +namespace WOBJSEL { + namespace obj { + constant mask = %00001111 + constant shift = 0 + } + namespace color { + constant mask = %11110000 + constant shift = 4 + } +} + + + +// Window 1 Left Position +//(write, h-blank, v-blank) +constant WH0 = 0x2126 + +// Window 1 Right Position +//(write, h-blank, v-blank) +constant WH1 = 0x2127 + +// Window 2 Left Position +//(write, h-blank, v-blank) +constant WH2 = 0x2128 + +// Window 2 Right Position +//(write, h-blank, v-blank) +constant WH3 = 0x2129 + + + +// Window mask logic for Backgrounds +//(write, h-blank, v-blank) +// +// 44332211 +// +// For each bit pair: +// 00 = OR +// 01 = AND +// 10 = XOR +// 11 = XNOR +constant WBGLOG = 0x212A + +namespace WBGLOG { + namespace bg1 { + constant mask = %00000011 + constant shift = 0 + } + namespace bg2 { + constant mask = %00001100 + constant shift = 2 + } + namespace bg3 { + constant mask = %00110000 + constant shift = 4 + } + namespace bg4 { + constant mask = %11000000 + constant shift = 6 + } + + namespace logic { + constant or = %00 + constant and = %01 + constant xor = %10 + constant xnor = %11 + } +} + + +// Window mask logic for Objects and Color Window +//(write, h-blank, v-blank) +// +// ----ccoo +// +// For each bit pair: +// 00 = OR +// 01 = AND +// 10 = XOR +// 11 = XNOR +constant WOBJLOG = 0x212B + +namespace WOBJLOG { + namespace obj { + constant mask = %00000011 + constant shift = 0 + } + namespace color { + constant mask = %00001100 + constant shift = 2 + } + + namespace logic { + constant or = %00 + constant and = %01 + constant xor = %10 + constant xnor = %11 + } +} + + + +// Main Screen Designation +//(write, h-blank, v-blank) +// +// ----o4321 +// +// 1/2/3/4/o - enable BG1 - BG4 & Objects for the main screen +constant TM = 0x212C + +namespace TM { + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + constant obj = %00010000 +} + + + +// Sub Screen Designation +//(write, h-blank, v-blank) +// +// ----o4321 +// +// 1/2/3/4/o - enable BG1 - BG4 & Objects for the sub screen +constant TS = 0x212D + +namespace TS { + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + constant obj = %00010000 +} + + + +// Window Mask Designation for the Main Screen +//(write, h-blank, v-blank) +// +// ----o4321 +// +// 1/2/3/4/o - enable window masking for BG1-BG4 & Objects on the main screen +constant TMW = 0x212E + +namespace TMW { + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + constant obj = %00010000 +} + + + +// Window Mask Designation for the Sub Screen +//(write, h-blank, v-blank) +// +// ----o4321 +// +// 1/2/3/4/o - enable window masking for BG1 - BG4 & Objects for the sub screen +constant TSW = 0x212F + +namespace TSW { + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + constant obj = %00010000 +} + + + +// Color Addition Select +//(write, h-blank, v-blank) +// +// ccmm--sd +// +// cc = clip color +// 00 - Never +// 01 - Outside color window +// 10 - Inside color window +// 11 - always +// +// mm = prevent color math +// 00 - Never +// 01 - Outside color window +// 10 - Inside color window +// 11 - always +// +// s = Add subscreen enable +// d = Direct color mode for 256 color BG +constant CGWSEL = 0x2130 + +namespace CGWSEL { + namespace clip { + constant mask = %11000000 + + constant never = %00000000 + constant outside = %01000000 + constant inside = %10000000 + constant always = %11000000 + } + namespace prevent { + constant mask = %00110000 + + constant never = %00000000 + constant outside = %00010000 + constant inside = %00100000 + constant always = %00110000 + } + + constant addSubscreen = %00000010 + constant directColor = %00000001 +} + + + +// Color Math Designation +//(write, h-blank, v-blank) +// +// shbo4321 +// +// s = add/subtract colors(0 = add, 1 = subtract) +// h = Half color math +// 4/3/2/1/o/b = Enable color math for BG1 - BG4, Objects and Backdrop +constant CGADSUB = 0x2131 + +namespace CGADSUB { + namespace color { + constant add = %00000000 + constant subtract = %1000000 + } + constant halfColor = %01000000 + + namespace enable { + constant mask = %00111111 + + constant bg1 = %00000001 + constant bg2 = %00000010 + constant bg3 = %00000100 + constant bg4 = %00001000 + constant obj = %00010000 + constant backdrop = %00100000 + } +} + + + +// Fixed Color Data +//(write, h-blank, v-blank) +// +// bgrccccc +// +// b/g/r = color plane(s) +// ccccc = color intensity +constant COLDATA = 0x2132 + +namespace COLDATA { + namespace plane { + constant all = %11100000 + constant blue = %10000000 + constant green = %01000000 + constant red = %00100000 + } + namespace intensity { + constant mask = %00011111 + constant shift = 0 + } +} + + + +// Screen Mode/ Video Select +//(write, h-blank, v-blank) +// +// se--poIi +// +// s = External Sync +// e = Enable Mode 7 EXTBG +// p = Enable Psudeo-hires mode +// o = Enable overscan +// I = Oject Interlace +// i = Screen Interlace +constant SETINI = 0x2133 + +namespace SETINI { + constant extsync = %10000000 + constant extbg = %01000000 + constant psuedoHires = %00001000 + constant overscan = %00000100 + constant objInterlace = %00000010 + constant screenInterlace = %00000001 +} + + + +// Multiplication Result +//(read, long, h-blank, v-blank) +// +// Two's compliment product of 16 bit `M7A` and the +// most recent byte written to `M7B`. +// +// Should not be read during Mode 7 rendering. +constant MPY = 0x2134 +constant MPYL = 0x2134 +constant MPYM = 0x2135 +constant MPYH = 0x2136 + + + +// Software Latch for H/V Counter +//(read, any) +// +// See `OPHCT` and `OPVCT` +constant SLHV = 0x2137 + + + +// Data for OAM Read +//(read, read twice, h-blank, v-blank) +constant OAMDATAREAD = 0x2138 + + + +// VRAM Data Read +//(read, word, v-blank) +constant VMDATAREAD = 0x2139 +constant VMDATALREAD = 0x2139 +constant VMDATAHREAD = 0x213A + + + +// CGRAM Data Read +//(read, v-blank) +constant CGDATAREAD = 0x213B + + + +// Horizontal Scanline Location +//(read, read twice, any) +// +// --------x xxxxxxxx +// +// Notes: +// * Latched on `SLHV` read or Pin 6 of Port 2(bit 6 `WRIO`) falling trigger. +// * Range 0 to 339 +// * Visible range: 22 - 277 +// * Bits 1-7 of the high byte are open bus and should be masked +// * High/Low order reset on `STAT78` read. +constant OPHCT = 0x213C + constant OPHCT.mask = 0x1ff + constant OPHCT.max = 339 + + +// Vertical Scanline Location +//(read, read twice, any) +// +// --------y yyyyyyyy +// +// Notes: +// * Latched on `SLHV` read or Pin 6 of Port 2(bit 6 `WRIO`) falling trigger. +// * Range 0 to 261 NTSC (+1 when interlacing) +// * Range 0 to 311 PAL (+1 when interlacing) +// * Visible range 1 - 224, 1 - 239? on overscan. +// * Bits 1-7 of the high byte are open bus and should be masked +// * High/Low order reset on `STAT78` read. +constant OPVCT = 0x213D + constant OPVCT.mask = 0x1ff + constant OPVCT.max = 312 + + + +// PPU 5c77 Staus Flag and Version +//(read, any) +// +// trm-vvvv +// +// t = time over flag(more than 34 sprite tiles on a scanline) +// r = Range overflow(more than 32 sprites on a scanline) +// m = master/slave select. Unknown function +// vvvv = 5c77 chip number. +constant STAT77 = 0x213E + +namespace STAT77 { + namespace version { + constant mask = %00001111 + constant shift = 0 + } + + constant time = %10000000 + constant range = %01000000 +} + + + +// PPU 5c88 Staus Flag and Version +//(read, any) +// +// fl-pvvvv +// +// f = Interlace flag(toffled every v-blank) +// l = External Latch Flag(set when PPU counters latched) +// p = NTSC/PAL mode(1 = PAL, 0 = NTSC) +// vvvv = 5c78 chip number. +constant STAT78 = 0x213F + +namespace STAT78 { + namespace version { + constant mask = %00001111 + constant shift = 0 + } + + constant pal = %00010000 + constant interlace = %10000000 + constant extLatch = %01000000 +} + + + +// APU I/O Register +//(read/write, any) +constant APUIO0 = 0x2140 +constant APUIO1 = 0x2141 +constant APUIO2 = 0x2142 +constant APUIO3 = 0x2143 + + + +// WRAM Data Read/Write +//(read/write, any) +// +// Will not work with a DMA transfer from WRAM to WRAM. +constant WMDATA = 0x2180 + +// WRAM Address +//(write, long, any) +// +// -------x xxxxxxxx xxxxxxxx +constant WMADD = 0x2181 +constant WMADDL = 0x2181 +constant WMADDM = 0x2182 +constant WMADDH = 0x2183 + + + +// NES-style Joypad Access Port 1 +//(read/write, any) +// +// Read: ------ca +// Write: -------l +// +// l = latch line of both ports +// a = data 1 line +// b = data 2 Line +constant JOYSER0 = 0x4016 + +// write +namespace JOYSER0 { + constant latch = %00000001 +} +// read +namespace JOYSER0 { + constant data1 = %00000001 + constant data2 = %00000010 +} + + + +// NES-style Joypad Access Port 2 +//(read, any) +// +// ---111db +// +// b = data 1 line +// d = data 2 line +// 1 = Always set +constant JOYSER1 = 0x4017 + +namespace JOYSER1 { + constant data1 = %00000001 + constant data2 = %00000010 +} + + + +// Interrupt Enable Flags +//(write, any) +// +// n-vh---a +// +// n = Enable V-Blank(NMI) +// vh = Enable IRQ +// 00 - Disabled +// 01 - On H-Counter(`HTIME`) +// 10 - On V-Counter(`VTIME`) +// 11 - On V-Counter and H-Counter(`VTIME` and `HTIME`) +// a = Auto read joypad +constant NMITIMEN = 0x4200 + +namespace NMITIMEN { + constant vBlank = %10000000 + constant vCounter = %00100000 + constant hCounter = %00010000 + constant autoJoy = %00000001 +} + + + +// Programmable I/O Port +//(write, any) +// +// ab------ +// +// a = Pin 6 of Port 1 +// b = Pin 6 of Port 2 +// +// H/V Counters(`OPHCT` and `OPVCT` ) will be latched on lowering +// trigger of Port 2(Transition from 1 to 0). +constant WRIO = 0x4201 + +namespace WRIO { + constant port1 = %10000000 + constant port2 = %01000000 +} + + + +// Multiplicand A +//(write, any) +constant WRMPYA = 0x4202 + +// Multiplicand B +//(write, any) +// +// After 8 CPU cycles `RDMPY` will contain the unsigned product of `WRMPYA` and `WRMPYB`. +constant WRMPYB = 0x4203 + + + +// Dividend C +//(write, word, any) +constant WRDIV = 0x4204 +constant WRDIVL = 0x4204 +constant WRDIVH = 0x4205 + +// Divisor B +//(write, any) +// +// After 16 CPU cycles `RDDIV` will contain the unsigned quotient of `WRDIV` and `WRDIVB`. +// The remainder of the divison is stored in `RDMPY`. +constant WRDIVB = 0x4206 + + + +// H Timer +//(write, word, any) +// +// ------h hhhhhhhh +// +// hhhhhhhhh = horizontal counter target(Range 0 - 339) +// +// See `MNITIMEN` for details. +constant HTIME = 0x4207 +constant HTIMEL = 0x4207 +constant HTIMEH = 0x4208 + +// V Timer +//(write, word, any) +// +// ------v vvvvvvvv +// +// vvvvvvvvvv = vertical counter target(Range 0 - 261 NTSC and 0 - 311 PAL) +// +// See `MNITIMEN` for details. +constant VTIME = 0x4209 +constant VTIMEL = 0x4209 +constant VTIMEH = 0x420A + + + +// DMA Enable +//(write, any) +// +// 76543210 +// +// 7/6/5/4/3/2/1 = Enable DMA channel. +// +// When a DMA is activated the CPU will be paused until all DMAs are completed. +constant MDMAEN = 0x420B + +namespace MDMAEN { + constant dma0 = %00000001 + constant dma1 = %00000010 + constant dma2 = %00000100 + constant dma3 = %00001000 + constant dma4 = %00010000 + constant dma5 = %00100000 + constant dma6 = %01000000 + constant dma7 = %10000000 +} + +// HDMA Enable +//(write, any) +// +// 76543210 +// +// 7/6/5/4/3/2/1 = Enable HDMA channel. +constant HDMAEN = 0x420C + +namespace HDMAEN { + constant dma0 = %00000001 + constant dma1 = %00000010 + constant dma2 = %00000100 + constant dma3 = %00001000 + constant dma4 = %00010000 + constant dma5 = %00100000 + constant dma6 = %01000000 + constant dma7 = %10000000 +} + + + +// ROM Access Speed +//(write, any) +// +// -------r +// +// r = FastROM select(1 = FastROM, 0 = SlowROM) +constant MEMSEL = 0x420D + +namespace MEMSEL { + constant fastrom = %00000001 + constant slowrom = %00000000 +} + + + +// NMI Flag and 5A22 Version +//(read, any) +// +// n---vvvv +// +// n = MNI Flag. Set on start of V-Blank, cleaered on read +// or at end of V-Blank. +// vvvv = 5A22 Chip version number +// +// This register should be read during the MNI Handler. +constant RDNMI = 0x4210 + +namespace RDNMI { + constant nmi = %10000000 + + namespace verison { + constant mask = %00001111 + constant shift = 0 + } +} + + + +// IRQ Flag +//(read, any) +// +// i------- +// +// i = IRQ Flag. Set just after IRQ fires, cleared on read. +// +// This register should be read during the IRQ Handler. +constant TIMEUP = 0x4211 + + + +// PPU Status +//(read, any) +// +// vh-----a +// +// v = V-Blank Flag. Set during V-Blank +// h = H-Blank Flag. Set during H-Blank +// a = Auto Joypad read status. Set while reading, cleared when completed. +constant HVBJOY = 0x4212 + +namespace HVBJOY { + constant vBlank = %10000000 + constant hBlank = %01000000 + constant autoJoy = %00000001 +} + + + +// Programmable I/O Port(in-port) +// +// ab------ +// +// a = Pin 6 of Port 1 +// b = Pin 6 of Port 2 +constant RDIO = 0x4213 + +namespace RDIO { + constant port1 = %10000000 + constant port2 = %01000000 +} + + + +// Quotient of Divide Result +//(read, word, any) +// +// Set 16 CPU cycles after `WRDIVB` write +constant RDDIV = 0x4214 +constant RDDIVL = 0x4214 +constant RDDIVH = 0x4215 + + + +// Multiplication Product of Divide Remainder +//(read, word, any) +// +// Set 16 CPU cycles after `WRDIVB` write or 8 CPU cycles after `WRMPYB` write. +constant RDMPY = 0x4216 +constant RDMPYL = 0x4216 +constant RDMPYH = 0x4217 + + + +// Autojoy Controller Ports +//(read, word, any) +// +// Should not be read when bit 0 of `HVBJOY` set. +constant JOY1 = 0x4218 +constant JOY2 = 0x421A +constant JOY3 = 0x421C +constant JOY4 = 0x421E + +constant JOY1L = 0x4218 +constant JOY1H = 0x4219 +constant JOY2L = 0x421A +constant JOY2H = 0x421B +constant JOY3L = 0x421C +constant JOY3H = 0x421D +constant JOY4L = 0x421E +constant JOY4H = 0x421F + +namespace JOY { + constant b = %1000000000000000 + constant y = %0100000000000000 + constant select = %0010000000000000 + constant start = %0001000000000000 + constant up = %0000100000000000 + constant down = %0000010000000000 + constant left = %0000001000000000 + constant right = %0000000100000000 + constant a = %0000000010000000 + constant x = %0000000001000000 + constant l = %0000000000100000 + constant r = %0000000000010000 + + constant buttons = %1100000011000000 + constant dpad = %0000111100000000 + constant shoulder = %0000000000110000 + + namespace type { + constant mask = %0000000000001111 + + constant controller = %0000 + constant mouse = %0001 + constant konamiJustifer = %1110 + } +} + +namespace JOYH { + constant b = %10000000 + constant y = %01000000 + constant select = %00100000 + constant start = %00010000 + constant up = %00001000 + constant down = %00000100 + constant left = %00000010 + constant right = %00000001 + + constant dpad = %00001111 +} +namespace JOYL { + constant a = %10000000 + constant x = %01000000 + constant l = %00100000 + constant r = %00010000 + + namespace type { + constant mask = %00001111 + + constant controller = %0000 + constant mouse = %0001 + constant konamiJustifer = %1110 + } +} + + + +// DMA Control +//(read, write, any) +// +// da-ifttt +// +// d = Transfer direction(0 = CPU -> PPU, 1 = PPU -> CPU) +// a = HDMA Addressing Mode(0 = absolute, 1 = indirect). HDMA Only +// i = DMA Address Increment(0 = Increment, 1 = Decrement). DMA Only +// f = DMA Fixed Transfer(1 = Address will not change). DMA Only. +// ttt = Transfer Mode +// 000 - 1 register, write once( r ) +// 001 - 2 registers, write once( r, r+1 ) +// 010 - 1 register, write twice( r, r ) +// 011 - 2 registers, write twice each( r, r, r+1, r+1 ) +// 100 - 4 registers, write once( r, r+1, r+2, r+3 ) +// 101 - 2 register, write twice alt - undocumented +// 110 - 1 register, write twice - undocumented +// 111 - 2 registers, write twice each - undocumented +// +constant DMAP0 = 0x4300 +constant DMAP1 = 0x4310 +constant DMAP2 = 0x4320 +constant DMAP3 = 0x4330 +constant DMAP4 = 0x4340 +constant DMAP5 = 0x4350 +constant DMAP6 = 0x4360 +constant DMAP7 = 0x4370 + +namespace DMAP { + namespace transfer { + constant mask = %00000111 + + constant one = %000 + constant two = %001 + constant writeTwice = %010 + constant readTwice = %010 + constant twoWriteTwice = %011 + constant four = %100 + } + namespace direction { + constant increment = %00000000 + constant decrement = %00010000 + } + namespace addressing { + constant absolute = %00000000 + constant indirect = %01000000 + } + namespace direction { + constant toPpu = %00000000 + constant toCpu = %10000000 + } + + constant fixed = %00001000 +} + + + +// DMA Destination Register +//(read, write, any) +// +// Bus B Address(PPU Memmory Address, maps to $00:21xx) +constant BBAD0 = 0x4301 +constant BBAD1 = 0x4311 +constant BBAD2 = 0x4321 +constant BBAD3 = 0x4331 +constant BBAD4 = 0x4341 +constant BBAD5 = 0x4351 +constant BBAD6 = 0x4361 +constant BBAD7 = 0x4371 + + + +// DMA Source Address +//(read, write, long, any) +// +// Bus A Address(CPU Memory Address) +// +// DMA: +// * Starting address for DMA Transfer. +// * Address will be incremented/decremented +// * Bank will not change during DMA Transfer. +// +// HDMA: +// * Table address for HDMA Transfer. +constant A1T0 = 0x4302 +constant A1T1 = 0x4312 +constant A1T2 = 0x4322 +constant A1T3 = 0x4332 +constant A1T4 = 0x4342 +constant A1T5 = 0x4352 +constant A1T6 = 0x4362 +constant A1T7 = 0x4372 + +constant A1T0L = 0x4302 +constant A1T0H = 0x4303 +constant A1B0 = 0x4304 +constant A1T1L = 0x4312 +constant A1T1H = 0x4313 +constant A1B1 = 0x4314 +constant A1T2L = 0x4322 +constant A1T2H = 0x4323 +constant A1B2 = 0x4324 +constant A1T3L = 0x4332 +constant A1T3H = 0x4333 +constant A1B3 = 0x4334 +constant A1T4L = 0x4342 +constant A1T4H = 0x4343 +constant A1B4 = 0x4344 +constant A1T5L = 0x4352 +constant A1T5H = 0x4353 +constant A1B5 = 0x4354 +constant A1T6L = 0x4362 +constant A1T6H = 0x4363 +constant A1B6 = 0x4364 +constant A1T7L = 0x4372 +constant A1T7H = 0x4373 +constant A1B7 = 0x4374 + + + +// DMA Size / HDMA Indirect Address +//(read, write, word, any) +// +// DMA: +// * 16 Bits +// * Number of bytes to transfer +// * Decremented during DMA. +// * If 0 then 0x10000 bytes will be transfered. +// +// HDMA: +// * Holding space for indirect addressing mode +// * These registers should not be set by the CPU +constant DAS0 = 0x4305 +constant DAS1 = 0x4315 +constant DAS2 = 0x4325 +constant DAS3 = 0x4335 +constant DAS4 = 0x4345 +constant DAS5 = 0x4355 +constant DAS6 = 0x4365 +constant DAS7 = 0x4375 + + +constant DAS0L = 0x4305 +constant DAS0H = 0x4306 +constant DAS1L = 0x4315 +constant DAS1H = 0x4316 +constant DAS2L = 0x4325 +constant DAS2H = 0x4326 +constant DAS3L = 0x4335 +constant DAS3H = 0x4336 +constant DAS4L = 0x4345 +constant DAS4H = 0x4346 +constant DAS5L = 0x4355 +constant DAS5H = 0x4356 +constant DAS6L = 0x4365 +constant DAS6H = 0x4366 +constant DAS7L = 0x4375 +constant DAS7H = 0x4376 + + + +// HDMA Indirect Address Bank +//(read, write, any) +// +// Used with HDMA only, combined with `DAS0` to form the effective address. +constant DASB0 = 0x4307 +constant DASB1 = 0x4317 +constant DASB2 = 0x4327 +constant DASB3 = 0x4337 +constant DASB4 = 0x4347 +constant DASB5 = 0x4357 +constant DASB6 = 0x4367 +constant DASB7 = 0x4377 + + + +// HDMA Table Address +//(read, write, word, any) +// +// Used with HDMA only. +// +// Only modify this register if starting HDMA mid frame. +constant A2A0 = 0x4308 +constant A2A1 = 0x4318 +constant A2A2 = 0x4328 +constant A2A3 = 0x4338 +constant A2A4 = 0x4348 +constant A2A5 = 0x4358 +constant A2A6 = 0x4368 +constant A2A7 = 0x4378 + +constant A2A0L = 0x4308 +constant A2A0H = 0x4309 +constant A2A1L = 0x4318 +constant A2A1H = 0x4319 +constant A2A2L = 0x4328 +constant A2A2H = 0x4329 +constant A2A3L = 0x4338 +constant A2A3H = 0x4339 +constant A2A4L = 0x4348 +constant A2A4H = 0x4349 +constant A2A5L = 0x4358 +constant A2A5H = 0x4359 +constant A2A6L = 0x4368 +constant A2A6H = 0x4369 +constant A2A7L = 0x4378 +constant A2A7H = 0x4379 + + + +// HDMA Line Counter +//(read, write, any) +// +// rccccccc +// +// r = Repeat Select(1 = HDMA every line, 0 +// ccccccc = Line Count +// +// Used with HDMA only. +// +// Only modify this register if starting HDMA mid frame. +constant NLTR0 = 0x430A +constant NLTR1 = 0x431A +constant NLTR2 = 0x432A +constant NLTR3 = 0x433A +constant NLTR4 = 0x434A +constant NLTR5 = 0x435A +constant NLTR6 = 0x436A +constant NLTR7 = 0x437A + +namespace NLTR { + constant repeat = %10000000 + + namespace count { + constant mask = %01111111 + constant shift = 0 + } +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/snes_header.inc b/roms/snes-test-roms/src/_common/snes_header.inc new file mode 100644 index 00000000..1ef514bc --- /dev/null +++ b/roms/snes-test-roms/src/_common/snes_header.inc @@ -0,0 +1,151 @@ +// common/snes_header.inc +// ====================== +// +// Builds the SNES ROM header. +// +// The following need to be defined before including this file: +// +// * MEMORY_MAP - set to one of the values in the MEMORY_MAP scope +// * ROM_SIZE - the ROM size in Mbits +// * REGION - the region of the ROM (must match the REGION scope) +// +// The following defines are optional, but must be defined before +// including this file. +// +// * CART_TYPE - the type of cart (see CART_TYPE scope, defaults to romOnly) +// * ROM_SPEED - the speed of the ROM (slow (default), fast) +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// ::TODO Handle SRAM:: + +namespace REGION { + constant Japan = 0x00 + constant US = 0x01 + constant Europe = 0x02 + constant Scandinavia = 0x03 + constant Europe_french = 0x06 + constant Dutch = 0x07 + constant Spanish = 0x08 + constant German = 0x09 + constant Italian = 0x0a + constant Chinese = 0x0b + constant Korean = 0x0d + constant Common = 0x0e + constant Canada = 0x0f + constant Brazil = 0x10 + constant Australia = 0x11 + constant otherX = 0x12 + constant otherY = 0x13 + constant otherZ = 0x14 +} + +namespace CART_TYPE { + constant romOnly = 0 + constant romRam = 1 + constant romSram = 2 +} +if !{defined CART_TYPE} { + define CART_TYPE = romOnly +} + +namespace ROM_SPEED { + constant fast = 0x10 + constant slow = 0x00 +} +if !{defined ROM_SPEED} { + define ROM_SPEED = slow +} + + +namespace SnesHeader { + +if {ROM_SIZE} <= 1 { + constant _HEADER_ROM_SIZE = 0x7 +} else if {ROM_SIZE} <= 2 { + constant _HEADER_ROM_SIZE = 0x8 +} else if {ROM_SIZE} <= 4 { + constant _HEADER_ROM_SIZE = 0x9 +} else if {ROM_SIZE} <= 8 { + constant _HEADER_ROM_SIZE = 0xA +} else if {ROM_SIZE} <= 16 { + constant _HEADER_ROM_SIZE = 0xB +} else if {ROM_SIZE} <= 32 { + constant _HEADER_ROM_SIZE = 0xC +} else if {ROM_SIZE} <= 64 { + constant _HEADER_ROM_SIZE = 0xD +} +constant _HEADER_MAP_MODE = MEMORY_MAP.{MEMORY_MAP}|ROM_SPEED.{ROM_SPEED} + +private.seek(0x00ffb0) + db " " // $ffbo - 2 Digit marker code (blank - unlicensed) + db " " // $ffb2 - 4 Character game code (blank - unlicensed) +EmptyBytes: + db 0, 0, 0, 0, 0, 0, 0 // $ffb6 - fixed value (7 bytes) + + db 0 // $ffbd - expansion RAM size + db 0 // $ffbe - special version + db 0 // $ffbf - cartridge type sub-number + + fill 21, ' ' +private.seek(0x00ffc0) + db {ROM_NAME} // $ffc0 - ROM name (21 characters) +private.seek(0x00ffd5) + db _HEADER_MAP_MODE // $ffd5 - map mode + db CART_TYPE.{CART_TYPE} // $ffd6 - cartridge type + db _HEADER_ROM_SIZE // $ffd7 - ROM size + db 0 // $ffd8 - RAM size + db REGION.{REGION} // $ffd9 - Destination code + db 0x33 // $ffda - fixed value + db {VERSION} // $ffdb - ROM version + dw 0xaaaa // $ffdc - checksum compliment + dw 0x5555 // $ffde - checksum + +// Native Interrupt Vectors + dw 0 // $ffe0 + dw 0 // $ffe2 + dw CopHandler // $ffe4 - native cop + dw BreakHandler // $ffe6 - native brk + dw EmptyHandler // $ffe8 - native abort + dw NmiHandler // $ffea - native nmi + dw 0 // $ffec + dw IrqHandler // $ffee - native irq + +// Emulated Interrupt Vectors + dw 0 // $fff0 + dw 0 // $fff2 + dw EmptyHandler // $fff4 - emu cop + dw 0 // $fff6 + dw EmptyHandler // $fff8 - emu abort + dw EmptyHandler // $fffa - emu nmi + dw ResetHandler // $fffc - emu reset + dw BreakHandler // $fffe - emu brk/irq +} + +private.seek(0) + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/struct.inc b/roms/snes-test-roms/src/_common/struct.inc new file mode 100644 index 00000000..afbcef03 --- /dev/null +++ b/roms/snes-test-roms/src/_common/struct.inc @@ -0,0 +1,188 @@ +// common/struct.inc +// ================= +// +// Turns the current scope into a struct. +// +// usage: +// namespace point { +// struct() +// struct_maxsize(4) // optional +// +// field(xPos, 2) +// field(yPos, 2) +// +// endstruct() +// } +// +// +// Basic struct inheritance can be achieved with the `basestruct` and +// `childstruct` macros. +// +// NOTE: Inner scopes will not work with struct inheritance. +// +// usage: +// namespace super { +// basestruct() +// struct_maxsize(16) // optional +// field(a, 2) +// endstruct() +// } +// namespace child { +// childstruct(super) +// field(b, 2) +// endstruct() +// } +// +// Child scope will contain `a` and `b` fields. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +inline struct(evaluate start) { + if {defined __STRUCT__} { + error "scope is already a struct" + } + + define __STRUCT__ + + constant __STRUCT__.start = {start} + variable __STRUCT__.inStruct = 0x1337 + variable __STRUCT__.isBaseStruct = 0 + variable __STRUCT__.pos = {start} + variable __STRUCT__.size = 0 + variable __STRUCT__.maxSize = 0 +} +inline struct() { + struct(0) +} + +inline basestruct_offset(evaluate start) { + struct({start}) + + __STRUCT__.isBaseStruct = 1 + define __STRUCT__.fields.size = 0 +} +inline basestruct() { + basestruct_offset(0) +} + +// raises an error is the struct is no a basestruct +macro validateStructIsBase(struct) { + if !{defined {struct}.__STRUCT__} { + error "struct `{struct}` does not exist" + } + if {struct}.__STRUCT__.isBaseStruct == 0 { + error "struct `{struct}` is not a basestruct" + } + if {struct}.__STRUCT__.inStruct { + error "basestruct `{struct}` is not closed" + } +} + +inline basestruct(parent) { + validateStructIsBase({parent}) + + basestruct_offset({parent}.__STRUCT__.start) + _childstruct_fields({parent}) +} + +inline childstruct(parent) { + validateStructIsBase({parent}) + + struct({parent}.__STRUCT__.start) + _childstruct_fields({parent}) +} + +inline _childstruct_fields(parent) { + __STRUCT__.maxSize = {parent}.__STRUCT__.maxSize + + evaluate n = 0 + while {n} < {{parent}.__STRUCT__.fields.size} { + field({{parent}.__STRUCT__.fields.{n}.name}, {{parent}.__STRUCT__.fields.{n}.size}) + + evaluate n = {n} + 1 + } + + assert(__STRUCT__.pos == {parent}.__STRUCT__.pos) +} + +// Creates a field in a struct of a given size. +inline field(name, evaluate size) { + if __STRUCT__.inStruct != 0x1337 { + error "Not in a struct" + } + if __STRUCT__.isBaseStruct { + define __STRUCT__.fields.{__STRUCT__.fields.size}.name = {name} + evaluate __STRUCT__.fields.{__STRUCT__.fields.size}.size = {size} + evaluate __STRUCT__.fields.size = {__STRUCT__.fields.size} + 1 + } + + assert({size} > 0) + + constant {name} = __STRUCT__.pos + __STRUCT__.pos = __STRUCT__.pos + {size} + __STRUCT__.size = __STRUCT__.size + {size} + + if __STRUCT__.maxSize > 0 && __STRUCT__.size > __STRUCT__.maxSize { + evaluate size = __STRUCT__.size + evaluate maxSize = __STRUCT__.maxSize + error "struct is too large, (size {size}, max {maxSize})" + } +} + +// Limits the size of the current struct to `maxSize` bytes +inline struct_maxsize(evaluate maxSize) { + assert({maxSize} > 0) + + if __STRUCT__.inStruct != 0x1337 { + error "Not in a struct" + } + if __STRUCT__.maxSize > 0 { + error "struct is already size limited" + } + __STRUCT__.maxSize = {maxSize} +} + +// Ends the struct, will create the `size` field. +// Also errors out if the struct is too large +inline endstruct() { + if __STRUCT__.inStruct != 0x1337 { + error "Not in a struct" + } + + if __STRUCT__.maxSize > 0 && __STRUCT__.size > __STRUCT__.maxSize { + evaluate size = __STRUCT__.size + evaluate maxSize = __STRUCT__.maxSize + error "struct is too large, (size {size}, max {maxSize})" + } + + __STRUCT__.inStruct = 0 + define __STRUCT__ = 1 + + constant size = __STRUCT__.size +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/_common/tmp_words.inc b/roms/snes-test-roms/src/_common/tmp_words.inc new file mode 100644 index 00000000..78542078 --- /dev/null +++ b/roms/snes-test-roms/src/_common/tmp_words.inc @@ -0,0 +1,65 @@ +// common/tmp_words.inc +// ==================== +// +// Marks unused words as a temporary variable to be accessed later. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +variable __TMP_WORDS__.nMarks = 0 +variable __TMP_WORDS__.nAllocations = 0 + +// Mark an unused word as a temporary variable that can be accessed +// later. +// +// This macro MUST BE called in the root scope. +// +// var must be in DB 0x7e +inline markTmpWord(evaluate var) { + assert(({var} >> 16) == 0x7e) + + evaluate __TMP_WORDS__.n = __TMP_WORDS__.nMarks + constant __TMP_WORDS__.{__TMP_WORDS__.n} = {var} + + __TMP_WORDS__.nMarks = __TMP_WORDS__.nMarks + 1 +} + +// Allocates a tmp Word to a given variable name. +// +// The variable will be located somewhere in DB 0x7e +// +// If you get a "unrecognized variable: __TMP_WORDS__.*" error +// then either: +// * a `markTmpWord` macro was not called in the root scope, or +// * you have run out of tmp words. +inline allocateTmpWord(name) { + evaluate __TMP_WORDS__.n = __TMP_WORDS__.nAllocations + constant {name} = __TMP_WORDS__.{__TMP_WORDS__.n} + + __TMP_WORDS__.nAllocations = __TMP_WORDS__.nAllocations + 1 +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/break_handler.inc b/roms/snes-test-roms/src/break_handler.inc new file mode 100644 index 00000000..a8680706 --- /dev/null +++ b/roms/snes-test-roms/src/break_handler.inc @@ -0,0 +1,374 @@ +// break_handler.inc +// ================= +// +// A Break Interrupt handler that prints the CPU registers on screen. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// This file might be included in tests that do not use `_common/memory.inc` +if {defined __MEMORY__.romBlocks.code} { + code() +} +namespace BreakHandler { + assert((pc() >> 16) | 0x80 == 0x80) + + constant VRAM_BG1_MAP_WADDR = 0x0000 + constant VRAM_BG1_TILES_WADDR = 0x1000 + + // Temporary variable used to calculate the address of registers in the stack + constant zpStack = 00 + + + if {defined __MEMORY__.romBlocks.rodata0} { + rodata(rodata0) + insert Font_1bpp, "../gen/textbuffer/font-1bpp-tiles.tiles" + code() + } else { + // no rodata0 bank + // Store the font in bank 0 + insert Font_1bpp, "../gen/textbuffer/font-1bpp-tiles.tiles" + } + include "../resources/textbuffer/font-1bpp-map.inc" + + + inline _string(evaluate x, evaluate y, string) { + assert({x} != 0) + + dw BreakHandler.VRAM_BG1_MAP_WADDR + {x} + 32 * {y} + db {string}, 0 + } + CrashString: + _string(6, 4, "CRASHED!") + + inline _line(evaluate x, evaluate y, string, evaluate stack_offset, evaluate size) { + _string({x}, {y}, {string}) + db {stack_offset}, {size} + } + BreakDataTable: + _line(6, 7, "PC", 16, 3) + _line(7, 9, "P", 13, 1) + _line(7, 11, "e", 3, 1) + _line(6, 13, "DB", 6, 1) + _line(6, 15, "SP", 2, 2) + _line(6, 17, "DP", 5, 2) + _line(7, 19, "A", 12, 2) + _line(7, 21, "X", 10, 2) + _line(7, 23, "Y", 8, 2) + EmptyByte: + db 0 + + + // Break Interrupt Service Routine + // + // This interrupt is also used for any unused interrupts. + // + // All registers unknown + // emulation bit unknown + function ISR { + // This ISR may be invoked in emulation mode, switch to native mode + clc + xce + + // MUST NOT MODIFY CARRY + + rep #%11111010 + // All flags except carry and interrupt-disable clear + // a16 + // i16 + pha + + // Disable interrupts (make sure an NMI interrupt will not interfere with this break handler) + // Also sets WRIO pins high (required for SLHV latching) + // saves two cycles compared to using an 8 bit Accumulator) + assert(NMITIMEN + 1 == WRIO) + lda.w #00 | ((WRIO.port1 | WRIO.port2)) << 8 + sta.l NMITIMEN + + phx + phy + + phb + phd + + sep #$24 + // a8 + // irq interrupts disable + + tsx + + // Save emulation flag to the stack + // carry = old emulation flag + lda.b #0 + rol + pha + + // CAN NOW MODIFY CARRY + + // invert emulation flag + eor.b #1 + lsr + // carry set if in native mode + + // Write original stack pointer to the stack + // (so it can be read by PrintRegisterLoop) + rep #$30 + // a16 + // carry set if in native mode + tsc + adc.w #13 + pha + + lda.w #0 + tcd + // DP = 0 + + // Decrement PC in stack to match the PC of the break instruction + // (This is safe, this BreakHandler never returns) + tsx + dec.b 14,x + dec.b 14,x + + + sep #$20 + // a8 + assert(pc() >> 16 == 0 || pc() >> 16 == 0x80) + phk + plb + // DB = 0 + + + // Setup PPU + jsr ResetRegisters + + stz.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + assert(VRAM_BG1_MAP_WADDR == 0) + stz.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + // Set the backdrop color to dark red + stz.w CGADD + + lda.b #8 + sta.w CGDATA + stz.w CGDATA + + // Set text color to white + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Clear tilemap + + ldx.w #EmptyByte + stx.w A1T0 + stz.w A1B0 + + ldx.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.two | (VMDATA << 8) + stx.w DMAP0 // also sets BBAD0 + + ldx.w #32 * 32 * 2 + stx.w DAS0 + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Clear high byte of tile data + + ldx.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (VMDATAH << 8) + stx.w DMAP0 // also sets BBAD0 + + ldy.w #Font_1bpp.size + sty.w DAS0 + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Copy font to VRAM + + // Y = Font_1bpp.size + sty.w DAS0 + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + stx.w DMAP0 // also sets BBAD0 + + ldx.w #Font_1bpp + lda.b #Font_1bpp >> 16 + stx.w A1T0 + sta.w A1B0 + + assert(VMAIN.incrementMode.low | VMAIN.increment.by1 == 0) + stz.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Print the strings + tsx + stx.b zpStack + + ldx.w #CrashString + jsr PrintString + + ldx.w #BreakDataTable + + PrintRegisterLoop: + jsr PrintString + + // Print colon, space + lda.b #Font.COLON + sta.w VMDATAL + stz.w VMDATAL + + phx + + tdc + // Ah = 0 + lda.b 1,x // size (byte) + tay + + lda.b 0,x // stack offset (byte) + rep #$31 + // a16 + // carry clear + adc.b zpStack + tax + + + // X = register address + // Y = register size + + sep #$20 + // a8 + + - + lda.b 0,x + lsr + lsr + lsr + lsr + assert(Font.ZERO == 1) + inc + sta.w VMDATAL + + lda.b 0,x + and.b #0xf + assert(Font.ZERO == 1) + inc + sta.w VMDATAL + + dex + + dey + bne - + + plx + inx + inx + + lda.b 0,x + bne PrintRegisterLoop + + + lda.b #0xf + sta.w INIDISP + + // Interrupts are disabled. + // This spinloop will loop forever and do absolutely nothing until the console has been reset. + SpinLoop: + wai + bra SpinLoop + } + + + // IN: X = string addr + // OUT: X = addr at end of string + // + // a8 + // i16 + // DB = 0 + function PrintString { + lda.b 0,x + inx + sta.w VMADDL + + lda.b 0,x + inx + sta.w VMADDH + + lda.b 0,x + - + sta.w VMDATAL + + inx + lda.b 0,x + bne - + inx + + rts + } +} + +constant BreakHandler = BreakHandler.ISR + + +// Use `BreakHandler` for all unused interrupts + +// (Used by emulation mode interrupts) +constant EmptyHandler = BreakHandler + + +if !{defined USES_IRQ_INTERRUPTS} { + constant IrqHandler = BreakHandler +} + +if !{defined USES_COP_INTERRUPTS} { + constant CopHandler = BreakHandler +} + + diff --git a/roms/snes-test-roms/src/common.inc b/roms/snes-test-roms/src/common.inc new file mode 100644 index 00000000..ffec73d8 --- /dev/null +++ b/roms/snes-test-roms/src/common.inc @@ -0,0 +1,36 @@ +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +include "_common/assert.inc" +include "_common/cpu.inc" +include "_common/enum.inc" +include "_common/memory.inc" +include "_common/print.inc" +include "_common/registers.inc" +include "_common/snes_header.inc" +include "_common/struct.inc" +include "_common/functiontable.inc" +include "_common/tmp_words.inc" + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/dma_forceblank.inc b/roms/snes-test-roms/src/dma_forceblank.inc new file mode 100644 index 00000000..aaba4adf --- /dev/null +++ b/roms/snes-test-roms/src/dma_forceblank.inc @@ -0,0 +1,405 @@ +// dma_forceblank.inc +// ================== +// +// Force Blank DMA Transfers. +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +namespace Dma { +namespace ForceBlank { + + +// Transfers a block of memory to VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +macro ToVram(addr, size) { + assert8a() + assert16i() + + ldx.w #{addr} + lda.b #({addr}) >> 16 + ldy.w #{size} + jsr Dma.ForceBlank.TransferToVram +} +macro ToVram(addr) { + Dma.ForceBlank.ToVram({addr}, {addr}.size) +} + + +// Transfers a block of memory to the low byte of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +macro ToVramL(addr, size) { + assert8a() + assert16i() + + ldx.w #{addr} + lda.b #({addr}) >> 16 + ldy.w #{size} + jsr Dma.ForceBlank.TransferToVramL +} +macro ToVramL(addr) { + Dma.ForceBlank.ToVramL({addr}, {addr}.size) +} + + +// Transfers a block of memory to the high byte of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +macro ToVramH(addr, size) { + assert8a() + assert16i() + + ldx.w #{addr} + lda.b #({addr}) >> 16 + ldy.w #{size} + jsr Dma.ForceBlank.TransferToVramH +} +macro ToVramH(addr) { + Dma.ForceBlank.ToVramH({addr}, {addr}.size) +} + + +// Transfers a block of memory to CGRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +macro ToCgram(addr, size) { + assert8a() + assert16i() + + ldx.w #{addr} + lda.b #({addr}) >> 16 + ldy.w #{size} + jsr Dma.ForceBlank.TransferToCgram +} +macro ToCgram(addr) { + Dma.ForceBlank.ToCgram({addr}, {addr}.size) +} + + +// Transfers a block of memory to OAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +macro ToOam(addr, size) { + assert8a() + assert16i() + + ldx.w #{addr} + lda.b #({addr}) >> 16 + ldy.w #{size} + jsr Dma.ForceBlank.TransferToOam +} +macro ToOam(addr) { + Dma.ForceBlank.ToOam({addr}, {addr}.size) +} + + +// Clears a block of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: X - vram address +// INPUT: Y - size (in bytes) +a8() +i16() +code() +function ClearVram { + stx.w VMADD + sty.w DAS0 + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldy.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.two | (VMDATA << 8) + sty.w DMAP0 // also sets BBAD0 + + ldx.w #SnesHeader.EmptyBytes + stx.w A1T0 + stz.w A1B0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +// Clear the low byte of a block of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: X - vram address +// INPUT: Y - size (in bytes to clear) +a8() +i16() +code() +function ClearVramL { + stx.w VMADD + sty.w DAS0 + + lda.b #VMAIN.incrementMode.low | VMAIN.increment.by1 + sta.w VMAIN + + ldy.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (VMDATAL << 8) + sty.w DMAP0 // also sets BBAD0 + + ldx.w #SnesHeader.EmptyBytes + stx.w A1T0 + stz.w A1B0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +// Clear the high byte of a block of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: X - vram address +// INPUT: Y - size (in bytes to clear) +a8() +i16() +code() +function ClearVramH { + stx.w VMADD + sty.w DAS0 + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldy.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (VMDATAH << 8) + sty.w DMAP0 // also sets BBAD0 + + ldx.w #SnesHeader.EmptyBytes + stx.w A1T0 + stz.w A1B0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + +// Clears a block of CGRAM +// DMA: Uses DMA channel 0 +// REQUIRES: DB access registers +// REQUIRES: screen blank +// +// INPUT: X - starting color +// INPUT: Y - nColors +a8() +i16() +code() +function ClearCgram { + php + + rep #$30 + sep #$10 +a16() +i8() + + stx.w CGADD + + tya + asl + sta.w DAS0 + + lda.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (CGDATA << 8) + sta.w DMAP0 // also sets BBAD0 + + stz.w A1B0 - 1 + lda.w #SnesHeader.EmptyBytes + sta.w A1T0 + + + ldx.b #MDMAEN.dma0 + stx.w MDMAEN + + plp + rts +} + + +// Transfers a block of memory to VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: A:X address +// INPUT: Y size (in bytes) +a8() +i16() +code() +function TransferToVram { + stx.w A1T0 + sta.w A1B0 + sty.w DAS0 + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.two | (VMDATA << 8) + stx.w DMAP0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + +// Transfers a block of memory to the low byte of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: A:X address +// INPUT: Y size (in bytes) +a8() +i16() +code() +function TransferToVramL { + stx.w A1T0 + sta.w A1B0 + sty.w DAS0 + + assert(VMAIN.incrementMode.low | VMAIN.increment.by1 == 0) + stz.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + stx.w DMAP0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + +// Transfers a block of memory to the high byte of VRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: A:X address +// INPUT: Y size (in bytes) +a8() +i16() +code() +function TransferToVramH { + stx.w A1T0 + sta.w A1B0 + sty.w DAS0 + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAH << 8) + stx.w DMAP0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + +// Transfers a block of memory to CGRAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: A:X address +// INPUT: Y size (in bytes) +a8() +i16() +code() +function TransferToCgram { + stx.w A1T0 + sta.w A1B0 + sty.w DAS0 + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (CGDATA << 8) + stx.w DMAP0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + +// Transfers a block of memory to OAM +// DMA: Uses DMA channel 0 +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: screen blank +// +// INPUT: A:X address +// INPUT: Y size (in bytes) +a8() +i16() +code() +function TransferToOam { + stx.w A1T0 + sta.w A1B0 + sty.w DAS0 + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (OAMDATA << 8) + stx.w DMAP0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + +} +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/effects/hdma-textbox-wipe.asm b/roms/snes-test-roms/src/effects/hdma-textbox-wipe.asm new file mode 100644 index 00000000..e10a1f44 --- /dev/null +++ b/roms/snes-test-roms/src/effects/hdma-textbox-wipe.asm @@ -0,0 +1,433 @@ +// HDMA textbox wipe animation. +// +// This animation is preformed by modifying a HDMA buffer in the VBlank routine +// (as opposed to a double-buffered HDMA effect). +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA TEXTBOX WIPE" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG2_MAP_WADDR = 0x0400 +constant VRAM_BG3_MAP_WADDR = 0x0800 + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG2_TILES_WADDR = 0x3000 +constant VRAM_BG3_TILES_WADDR = 0x5000 + +constant VRAM_OBJ_TILES_WADDR = 0x6000 + + +namespace AnimationState { + createEnum() + enum(SHOW_TEXTBOX_ANIMATION) + enum(TEXTBOX_OPEN_WAIT) + enum(HIDE_TEXTBOX_ANIMATION) + enum(TEXTBOX_CLOSED_WAIT) + endEnum() +} + +// Number of frames to wait between animations +constant ANIMATION_WAIT_FRAMES = 60 + +// Height of the textbox before switching to `TEXTBOX_OPEN_WAIT` state. +constant MAX_TEXTBOX_HEIGHT = 64 + + + +constant HDMA_BUFFER_SIZE = 32 + +// HDMA buffer (in RAM) +// (in low-RAM) +allocate(hdmaBuffer, lowram, HDMA_BUFFER_SIZE) + + +// Animation state variable +// +// (`AnimationState` enum, low-RAM) +allocate(animationState, lowram, 1) + + +// Animation timer, used by the TEXTBOX_OPEN and TEXTBOX_CLOSED states. +// +// (uint8, lowRAM) +allocate(animationTimer, lowram, 1) + + + +// Visible textbox height, in scanlines. +// +// Used by the VBlank routine to preform the textbox wipe animation. +// +// This value MUST BE < 128. +// +// If this value is 0, there will be no textbox on screen. +// +// (uint8, low-RAM) +allocate(textboxHeight, lowram, 1) + + + +// Setup the textbox wipe animation HDMA effect. +// +// Uses DMA channel 7. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank, HDMA disabled +a8() +i16() +code() +function SetupHdma { + + // Copy `HdmaTable` (in ROM) to `hdmaBuffer` (in low-RAM) + ldx.w #HdmaTable.size - 1 + Loop: + lda.l HdmaTable,x + sta.w hdmaBuffer,x + dex + bpl Loop + + + // Reset `textboxHeight` and `animationState` + stz.w textboxHeight + + assert(AnimationState.SHOW_TEXTBOX_ANIMATION == 0) + stz.w animationState + + + // HDMA to `TM` + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP7 + + lda.b #TM + sta.w BBAD7 + + // HDMA table address + assertLowRam(hdmaBuffer) + ldx.w #hdmaBuffer + stx.w A1T7 + stz.w A1B7 + + rts +} + + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + assertLowRam(hdmaBuffer) + assertLowRam(textboxHeight) + + // Update the height of the textbox in the hdmaBuffer's HDMA-Table + // + // This is safe as HDMA is not active during VBlank. + + lda.w textboxHeight + sta.w hdmaBuffer + TEXTBOX_HEIGHT_OFFSET + + + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Process one frame of the textbox-wipe animation. +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access low-RAM +a8() +i16() +code() +function Process { + lda.w animationState + + cmp.b #AnimationState.SHOW_TEXTBOX_ANIMATION + beq ShowTextboxAnimation + + cmp.b #AnimationState.TEXTBOX_OPEN_WAIT + beq TextboxOpenWait + + cmp.b #AnimationState.HIDE_TEXTBOX_ANIMATION + beq HideTextboxAnimation + + assert(AnimationState.__ENUM__.count == 4) + bra TextboxClosedWait + + + +ShowTextboxAnimation: + lda.w textboxHeight + inc + sta.w textboxHeight + cmp.b #MAX_TEXTBOX_HEIGHT + bcc + + // textbox is completely visible, change animation state + lda.b #AnimationState.TEXTBOX_OPEN_WAIT + sta.w animationState + + lda.b #ANIMATION_WAIT_FRAMES + sta.w animationTimer + + + rts + + +TextboxOpenWait: + dec.w animationTimer + bne + + wdm #1 + + // Timer has ended, change animation state + lda.b #AnimationState.HIDE_TEXTBOX_ANIMATION + sta.w animationState + + + rts + + +HideTextboxAnimation: + dec.w textboxHeight + bne + + // textboxHeight == 0, change animation state + + lda.b #AnimationState.TEXTBOX_CLOSED_WAIT + sta.w animationState + + lda.b #ANIMATION_WAIT_FRAMES + sta.w animationTimer + + + rts + + +TextboxClosedWait: + dec.w animationTimer + bne + + // Timer has ended, change animation state + stz.w textboxHeight + + lda.b #AnimationState.SHOW_TEXTBOX_ANIMATION + sta.w animationState + + + rts +} + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode1 + sta.w BGMODE + + lda.b #OBSEL.size.s8_16 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG2_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG2SC + + lda.b #(VRAM_BG3_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG3SC + + lda.b #((VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift) | ((VRAM_BG2_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg2.shift) + sta.w BG12NBA + + lda.b #(VRAM_BG3_TILES_WADDR / BG34NBA.walign) << BG34NBA.bg3.shift + sta.w BG34NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg_Palette) + + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG2_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2_Tiles) + + ldx.w #VRAM_BG3_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg3_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + ldx.w #VRAM_BG2_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2_Tilemap) + + ldx.w #VRAM_BG3_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg3_Tilemap) + + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + + + lda.b #TM.bg1 | TM.bg2 | TM.bg3 | TM.obj + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr Process + + jsr WaitFrame + + jmp MainLoop +} + + + + +// The byte offset, within HdmaTable, for the height of the textbox. +constant TEXTBOX_HEIGHT_OFFSET = 2 + + +// HDMA Table for the `TM` register (one register transfer pattern). +HdmaTable: + db 32 // 32 scanlines, non-repeat entry + db 0x13 // TM = BG1, BG2, OBJ + + db 64 // 64 scanlines, non-repeat entry + db 0x04 // TM = BG3 + + db 1 // 1 scanline + db 0x13 // TM = BG1, BG2, OBJ + + db 0 // End HDMA table + +constant HdmaTable.size = pc() - HdmaTable + +assert(HDMA_BUFFER_SIZE > HdmaTable.size) + + + + +// Resources +// ========= + +namespace Resources { + insert Bg_Palette, "../../gen/hdma-textbox-wipe/bg1.palette" + + insert Bg1_Tiles, "../../gen/hdma-textbox-wipe/bg1.4bpp" + insert Bg1_Tilemap, "../../gen/hdma-textbox-wipe/bg1.tilemap" + + insert Bg2_Tiles, "../../gen/hdma-textbox-wipe/bg2.4bpp" + insert Bg2_Tilemap, "../../gen/hdma-textbox-wipe/bg2.tilemap" + + insert Bg3_Tiles, "../../gen/hdma-textbox-wipe/bg3.2bpp" + insert Bg3_Tilemap, "../../gen/hdma-textbox-wipe/bg3.tilemap" + + insert Obj_Tiles, "../../gen/hdma-textbox-wipe/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../gen/hdma-textbox-wipe/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../gen/hdma-textbox-wipe/oam.bin" + + assert(Obj_Oam.size == 544) +} + + diff --git a/roms/snes-test-roms/src/effects/inidisp_extend_vblank.asm b/roms/snes-test-roms/src/effects/inidisp_extend_vblank.asm new file mode 100644 index 00000000..e2102b79 --- /dev/null +++ b/roms/snes-test-roms/src/effects/inidisp_extend_vblank.asm @@ -0,0 +1,828 @@ +// Extend VBlank demo +// +// This demo uses extended-VBlank to transfer 8736 bytes of data to the PPU +// on every display frame. +// +// IRQ interrupts and the INIDISP register are used to decrease the number +// of visible scanlines, moving them into the VBlank routine and increasing +// the amount of data that can be transferred during the VBlank routine. +// +// The mid-screen activation OBJ glitch is hidden by disabling backgrounds +// and sprites for the first visible scanline. This technique works best +// if the background colour is black. +// +// The IRQ interrupts have been carefully timed to ensure critical register +// writes occur within Horizontal-Blank. +// +// This demo does not use HDMA. Combining HDMA with extended VBlank +// requires careful consideration and is beyond the scope of this demo. +// +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 4 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "INIDISP EXTEND VBLANK" +define VERSION = 1 + +define USES_IRQ_INTERRUPTS + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rom1, 0x818000, 0x81ffff) +createCodeBlock(rom2, 0x828000, 0x82ffff) +createCodeBlock(rom3, 0x838000, 0x83ffff) +createCodeBlock(rom4, 0x848000, 0x84ffff) +createCodeBlock(rom5, 0x858000, 0x85ffff) +createCodeBlock(rom6, 0x868000, 0x86ffff) +createCodeBlock(rom7, 0x878000, 0x87ffff) +createCodeBlock(rom8, 0x888000, 0x88ffff) +createCodeBlock(rom9, 0x898000, 0x89ffff) +createCodeBlock(rom10, 0x8a8000, 0x8affff) +createCodeBlock(rom11, 0x8b8000, 0x8bffff) +createCodeBlock(rom12, 0x8c8000, 0x8cffff) +createCodeBlock(rom13, 0x8d8000, 0x8dffff) +createCodeBlock(rom14, 0x8e8000, 0x8effff) +createCodeBlock(rom15, 0x8f8000, 0x8fffff) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// +// ============================================================================ +// + + +// Number of scanlines to remove from the top and bottom. +// +// There will be `224 - 2 * N_SCANLINES_TO_REMOVE` visible scanlines. +// +// VBlank will be extended by `2 * N_SCANLINES_TO_REMOVE - 1` scanlines. +// +constant N_SCANLINES_TO_REMOVE = 10; + + +// The scanline to trigger the `IRQ_EnableDisplay` IRQ ISR. +constant ENABLE_DISPLAY_SCANLINE = N_SCANLINES_TO_REMOVE - 1 + +// The scanline to trigger the `IRQ_VBlank` IRQ ISR. +constant VBLANK_SCANLINE = 224 - N_SCANLINES_TO_REMOVE + + +// H-Counter position of the IRQ interrupts. +// +// Mesen-SX's Event Viewer was used to confirm the IRQ ISR's critical +// writes occurred within Horizontal-Blank. +// +// NOTE: This value MUST be re-calibrated whenever `IRQ_EnableDisplay`, +// `IRQ_EnableMainScreen`, or the `INIDISP` write within `IRQ_VBlank` +// is changed. +// +constant IRQ_X_POS = 240 + + + +// IRQ ISR +// +// Located in RAM so the address of the interrupt handler can be changed. +// +// Will contain `jml 0x80????`, where `????` is the address of the next IRQ +// handler to execute. +allocate(IrqHandler, lowram, 4) + + +// Address of the next IRQ ISR. +// (long addr) +constant irqHandlerAddr = IrqHandler + 1 + + +// Update VBlank flag. +// +// Set by `WaitFrame`, cleared by `IRQ_VBlank`. +// +// (byte flag) +allocate(vBlankFlag, lowram, 1) + + +// The brightness of the display for the current frame. +// +// (uint8 INIDISP shadow variable) +allocate(brightness, lowram, 1) + + +// Shadow variable of the TM register. +// +// (uint8 TM shadow variable) +allocate(tmShadow, lowram, 1) + + + +// This demo does not use NMI Interrupts. +constant NmiHandler = BreakHandler + + + +// Initialize and enable the extend VBlank IRQs. +// +// Assumes `brightness` and `tmShadow` are already set. +// +// Assumes IRQ and NMI interrupts are disabled. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: Force-Blank +// +a8() +i16() +code() +function SetupAndEnableIrqHandler { + // Write `jml IRQ_VBlank` to IrqHandler + lda.b #0x5c + sta.w IrqHandler + + ldx.w #IRQ_VBlank + stx.w IrqHandler + 1 + + lda.b #IRQ_VBlank >> 16 + sta.w IrqHandler + 3 + + + // Setup IRQ time + ldx.w #IRQ_X_POS + stx.w HTIME + + ldx.w #VBLANK_SCANLINE + stx.w VTIME + + + // Enable IRQ Interrupts + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter | NMITIMEN.autoJoy + sta.w NMITIMEN + + // Enable IRQ interrupts + cli + + // Clear IRQ flag + lda.w TIMEUP + + rts +} + + + +// First IRQ ISR of the display frame. +// +// Triggered on X=`IRQ_X_POS`, Y=`ENABLE_DISPLAY_SCANLINE`. +// +// Turns off Force-Blank and ends the extended VBlank. +// +au() +iu() +// DB unknown +code() +function IRQ_EnableDisplay { + + // No need to set/clear x or decimal flags. They are not used by this ISR. + sep #$20 +a8() + pha + + // Data Bank and Direct Page registers are unknown. + // Use long addressing on all data writes. + + + // Enable display. + // + // A bank-byte of `0x0f` is used to pre-load the data-bus with bit-7 + // clear (and full brightness) before the INIDISP write to mitigate the + // INIDISP open-bus early read glitch (corrupt sprite tiles). + // + // This mitigation is not required as the OBJ tiles on the next + // scanline are already glitched (as the screen is enabled mid-frame). + // + // Long addressing is required as the Data Bank is unknown. + lda.l brightness + sta.l 0x0f0000 | INIDISP + + + // Schedule the next IRQ on the next scanline + + lda.b #IRQ_EnableMainScreen + sta.l irqHandlerAddr + lda.b #IRQ_EnableMainScreen >> 8 + sta.l irqHandlerAddr + 1 + + lda.b #NMITIMEN.hCounter | NMITIMEN.autoJoy + sta.l NMITIMEN + + + // Clear IRQ flag + lda.l TIMEUP + + + pla + rti +} + + + +// Second IRQ ISR of the display frame. +// +// Triggered on X=`IRQ_X_POS`, Y=`ENABLE_DISPLAY_SCANLINE + 1`. +// +// Turns on background layers and sprites. +// +au() +iu() +// DB unknown +code() +function IRQ_EnableMainScreen { + + // No need to set/clear x or decimal flags. They are not used by this ISR. + sep #$20 +a8() + pha + + // Data Bank and Direct Page registers are unknown. + // Use long addressing on all reads and writes. + + // Enable Backgrounds and sprites + lda.l tmShadow + sta.l TM + + + // Schedule next IRQ + // (8 bit write to VTIME is safe, VTIMEH is always 0) + + lda.b #IRQ_VBlank + sta.l irqHandlerAddr + lda.b #IRQ_VBlank >> 8 + sta.l irqHandlerAddr + 1 + + lda.b #VBLANK_SCANLINE + sta.l VTIMEL + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter | NMITIMEN.autoJoy + sta.l NMITIMEN + + + // Clear IRQ flag + lda.l TIMEUP + + + pla + rti +} + + + +// Third IRQ ISR of the display frame. +// +// Triggered on X=`IRQ_X_POS`, Y=`VBLANK_SCANLINE`. +// +// * Turns on Force-Blank, disabling the screen, starting the extended VBlank. +// * Turns off background layers and sprites. +// * Executes the `VBlank` routine if `vBlankFlag` is set. +// +// This routine MUST COMPLETE before the EnableDisplay IRQ is scheduled to start. +// Failure to do so can cause blank lines and/or fullscreen flashing (major +// photosensitivity issue). +// +au() +iu() +// DB unknown +code() +function IRQ_VBlank { + + // Clear m, x, decimal flags + rep #$38 +a16() +i16() + pha + + sep #$20 +a8() + // Disable display. + // + // INIDISP is written as early as possible to ensure write is preformed + // within H-Blank. + // + // A bank-byte of `0x80` is used to pre-load the data-bus with bit-7 set + // before the INIDISP write to mitigate the INIDISP open-bus early read + // glitch. + // + // Long addressing is required as the Data Bank is unknown. + lda.l brightness + ora.b #INIDISP.force + sta.l 0x800000 | INIDISP + + + phx + phy + phb + + assert(pc() >> 16 == 0x80) + phk + plb +// DB = 0x80 + + + // Schedule next IRQ Handler + // (8 bit write to VTIME is safe, VTIMEH is always 0) + // + // Scheduled early to ensure the next IRQ is triggered on time. + + lda.b #IRQ_EnableDisplay + sta.w irqHandlerAddr + lda.b #IRQ_EnableDisplay >> 8 + sta.w irqHandlerAddr + 1 + + lda.b #ENABLE_DISPLAY_SCANLINE + sta.w VTIMEL + + // Clear IRQ flag + lda.w TIMEUP + + + // Disable all backgrounds and sprites + stz.w TM + + + // Execute Vertical Blank routine (if vBlankFlag is set) + lda.w vBlankFlag + beq + + jsr VerticalBlank + + stz.w vBlankFlag + + + + + // Confirm VBlank did not overrun. + // Break if VBlank overran. + sep #$30 +i8() + // Read vertical scanline location + lda.w SLHV + ldx.w OPVCT + lda.w OPVCT + // X = OPVCT low byte + // A = OPVCT high byte + + and.b #1 + bne NoOverrun + cpx.b #ENABLE_DISPLAY_SCANLINE + bcc NoOverrun + + cpx.b #VBLANK_SCANLINE + bcs NoOverrun + + // VBlank overran + jmp BreakHandler +NoOverrun: + + + // Restore registers from stack + rep #$30 +a16() +i16() + plb + ply + plx + pla + + rti +} + + + +// Wait until the end of `IRQ_VBlank`. +// +// REQUIRES: 8 bit A, DB access low-RAM +a8() +iu() +code() +function WaitFrame { + + // Execute `VBlank` routine on the next `IRQ_VBlank` interrupt + lda.b #1 + sta.w vBlankFlag + + + // Loop until the vBlankFlag clear + Loop: + wai + lda.w vBlankFlag + bne Loop + + rts +} + + + +// +// ============================================================================ +// + + +// Demo Variables +// -------------- + + +// VRAM Table +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_OBJ_TILES_WADDR = 0x6000 + + +// The address of the OBJ tiles to load during VBlank +// (long addr) +allocate(objTilesAddr, lowram, 3) + + +// Frame counter. Incremented once per frame. +// (uint8) +allocate(frameCounter, lowram, 1) + + +// OAM Buffer +// (two tables: 512 byte low table and 32 byte high table) +allocate(oamBuffer, lowram, 544) +constant oamBuffer.size = 544 + +constant hiOamBuffer = oamBuffer + 512 + + + +// Initialize the demo's variables +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function Init { + + // Initialize oamBuffer + + // Copy InitialOamBuffer to oamBuffer + ldx.w #0 + - + lda.l Resources.InitialOamBuffer,x + sta.w oamBuffer,x + + inx + cpx.w #Resources.InitialOamBuffer.size + bcc - + + // Move all unused sprites off-screen + lda.b #256 - 16 + - + sta.w oamBuffer,x + inx + cpx.w #128 * 4 + bcc - + + // Clear oamBuffer high table + - + stz.w oamBuffer,x + inx + cpx.w #oamBuffer.size + bcc - + + + // Initialize `objTilesAddr` + ldx.w #Resources.ObjTiles.Block_1 + stx.w objTilesAddr + lda.b #Resources.ObjTiles.Block_1 >> 16 + sta.w objTilesAddr + 2 + + + rts +} + + + +// Setup the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: Force-Blank +a8() +i16() +code() +function SetupPpu { + + // Disable HDMA + stz.b HDMAEN + + + // Setup PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #OBSEL.size.s16_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #TM.bg1 | TM.obj + sta.w tmShadow + + + // Move BG1 so it appears centered + lda.b #8 + sta.w BG1HOFS + stz.w BG1HOFS + + lda.b #7 + sta.w BG1VOFS + stz.w BG1VOFS + + + // Transfer Palettes to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + + // Transfer BG1 data to VRAM + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + + // Start demo at 1 brightness + lda.b #1 + sta.w brightness + + + rts +} + + + +// Process the demo. +// +// Called once per frame. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function Process { + inc.w frameCounter + + + // Move all the sprites up one pixel + ldx.w #0 + - + dec.w oamBuffer + 1,x + inx + inx + inx + inx + cpx.w #Resources.InitialOamBuffer.size + bcc - + + + // Change sprite tiles every second frame + lda.w frameCounter + and.b #1 + bne SkipChangeTiles + // Increment `objTilesAddr` (with wrapping) + rep #$30 + a16() + lda.w objTilesAddr + clc + adc.w #Resources.ObjTiles.FRAME_SIZE + sta.w objTilesAddr + + sep #$20 + a8() + bcc ++ + // 16 bit address overflowed, reset address + ldx.w #Resources.ObjTiles.FirstAddr + stx.w objTilesAddr + + // Increment `objTilesAddr` bank (with wrapping) + lda.w objTilesAddr + 2 + inc + cmp.b #Resources.ObjTiles.LastBank + bcc + + lda.b #Resources.ObjTiles.FirstBank + + + sta.w objTilesAddr + 2 + + +SkipChangeTiles: + + + // On every 16th frame: Increment brightness (if not at full brightness) + lda.w frameCounter + and.b #15 + bne + + lda.w brightness + cmp.b #INIDISP.brightness.mask + beq + + inc + sta.w brightness + + + + rts +} + + + +// VBlank routine. +// +// Called once per frame by `IRQ_VBlank`. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// REQUIRES: Force-Blank +a8() +i16() +code() +function VerticalBlank { + + // Transfer oamBuffer to OAM using DMA channel 0 + stz.w OAMADDL + stz.w OAMADDH + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #OAMDATA + sta.w BBAD0 + + ldx.w #oamBuffer + stx.w A1T0 + lda.b #oamBuffer >> 16 + sta.w A1B0 + + ldx.w #oamBuffer.size + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Transfer tiles at address `objTilesAddr` to VRAM using DMA channel 0 + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w objTilesAddr + stx.w A1T0 + lda.w objTilesAddr + 2 + sta.w A1B0 + + ldx.w #Resources.ObjTiles.FRAME_SIZE + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + rts +} + + + +au() +iu() +code() +function Main { + sep #$20 + rep #$10 +a8() +i16() + + phk + plb +// DB = 0x80 + + + // Force-Blank + lda.b #INIDISP.force + sta.l 0x800000 | INIDISP + + jsr Init + jsr SetupPpu + + jsr SetupAndEnableIrqHandler + + + // Setting DB to `0x7e` to demonstrate why the IRQ handlers must either + // change the DB register or use long-addressing on every read/write. + lda.b #0x7e + pha + plb +// DB = 0x7e + + MainLoop: + jsr WaitFrame + + jsr Process + + bra MainLoop +} + + + +namespace Resources { + + // Object Tiles are too large to fit inside a single bank. + namespace ObjTiles { + // The comment at the top of this file MUST BE updated if `FRAME_SIZE` changes. + constant FRAME_SIZE = 128 * 128 / 2 + + constant N_FRAMES = 60 + + constant FRAMES_PER_BANK = 32 * 1024 / FRAME_SIZE + constant N_BANKS = (N_FRAMES + (FRAMES_PER_BANK - 1)) / FRAMES_PER_BANK + constant BYTES_PER_BANK = FRAME_SIZE * FRAMES_PER_BANK + + variable i = 0 + while i < N_BANKS { + evaluate _bank = i + 1 + rodata(rom{_bank}) + assert(pc() & 0xffff == 0x8000) + + insert Block_{_bank}, "../../gen/inidisp_extend_vblank/spinning-logo-4bpp-tiles.tiles", i * BYTES_PER_BANK, BYTES_PER_BANK + + i = i + 1 + } + + constant FirstAddr = Block_1 & 0xffff + + constant FirstBank = Block_1 >> 16 + constant LastBank = pc() >> 16 + } + + rodata(code) + insert Obj_Palette, "../../gen/inidisp_extend_vblank/spinning-logo-4bpp-tiles.pal" + + insert InitialOamBuffer, "../../gen/inidisp_extend_vblank/spinning-logo-oam.bin" + assert(Resources.InitialOamBuffer.size < 544) + + + rodata(code) + insert Bg1_Palette, "../../gen/inidisp_extend_vblank/bg1-2bpp-tiles.pal" + insert Bg1_Tiles, "../../gen/inidisp_extend_vblank/bg1-2bpp-tiles.tiles" + insert Bg1_Tilemap, "../../gen/inidisp_extend_vblank/bg1-tilemap.bin" +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/inidisp_fadein_fadeout.asm b/roms/snes-test-roms/src/effects/inidisp_fadein_fadeout.asm new file mode 100644 index 00000000..acbfd68f --- /dev/null +++ b/roms/snes-test-roms/src/effects/inidisp_fadein_fadeout.asm @@ -0,0 +1,403 @@ +// An INIDISP fade-in, fade-to-force-blank screen transition demo. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "FADEIN FADEOUT DEMO" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Frame counter. Incremented every NMI interrupt +// (uint32) +allocate(frameCounter, lowram, 4) + + +// INIDISP shadow variable +allocate(inidisp_shadow, lowram, 1) + + +// Execute V-Blank Routine flag +// +// The VBlank routine will be executed if this value is non-zero. +// +// (byte flag) +allocate(vBlankFlag, lowram, 1) + + + +// NMI ISR +au() +iu() +code() +function NmiHandler { + // Jump to FastROM bank + jml FastRomNmiHandler +FastRomNmiHandler: + + // Save CPU state + rep #$30 +a16() +i16() + pha + phx + phy + phd + phb + + + phk + plb +// DB = 0x80 + + lda.w #0 + tcd +// DP = 0 + + + sep #$20 +a8() + + // Only execute the VBlank routine if `vBlankFlag` is non-zero. + // (prevents corruption during force-blank setup or a lag frame) + lda.w vBlankFlag + bne + + jmp EndVBlankRoutine + + + + // Enable force-blank (and set brightness bits) + lda.w inidisp_shadow + ora.b #INIDISP.force + sta.w INIDISP + + + // VBlank routine goes here + + + // Only write to `INIDISP` when `vBlankFlag` is set. + // + // We do not want to accidentally enable/disable the screen (or change the brightness) + // in the middle of a setup routine or a lag-frame. + assert8a() + lda.w inidisp_shadow + sta.w INIDISP + + + stz.w vBlankFlag + + +EndVBlankRoutine: + + + rep #$30 +a16() +i16() + + // Increment 32 bit frameCounter + inc.w frameCounter + bne + + inc.w frameCounter + 2 + + + + + // Restore CPU state + assert16a() + assert16i() + plb + pld + ply + plx + pla + + rti +} + + + +// Wait until the start of a new display frame +// (or the end of the VBlank routine (NmiHandler)). +// +// REQUIRES: NMI enabled, DB access low-RAM +au() +iu() +code() +function WaitFrame { + php + sep #$20 +a8() + + lda.b #1 + sta.w vBlankFlag + + + // Loop until frameCounter has changed + lda.w frameCounter + - + wai + + cmp.w frameCounter + beq - + + plp + + rts +} + + + +// Fade-in screen transition. +// +// ASSUMES: In force-blank or screen brightness is 0. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function FadeInTransition { + + lda.b #0 + + Loop: + sta.w inidisp_shadow + + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + + lda.w inidisp_shadow + inc + cmp.b #INIDISP.brightness.mask + 1 + bne Loop + + rts +} + + + +// Fade-to-black screen transition. +// +// Returns with force-blank enabled. +// +// ASSUMES: Screen active and at full brightness +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function FadeToForceBlank { + + lda.b #INIDISP.brightness.mask + + Loop: + sta.w inidisp_shadow + + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + + lda.w inidisp_shadow + dec + bpl Loop + + + lda.b #INIDISP.force + sta.w inidisp_shadow + + // Must wait until the end of the VBlank routine before Force-Blank is enabled + jsr WaitFrame + + rts +} + + + +// Pause execution for 60 frames. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function WaitOneSecond { + + lda.b #60 + + Loop: + pha + + jsr WaitFrame + + pla + dec + bne Loop + + rts +} + + + +// Transfer MapImage to VRAM and CGRAM +// +// REQUIRES: Force-Blank +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function LoadImage_Map { + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.MapImage_Tiles) + + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.MapImage_Tilemap) + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.MapImage_Palette) + + rts +} + + + +// Transfer GameImage to VRAM and CGRAM +// +// REQUIRES: Force-Blank +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function LoadImage_Game { + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.GameImage_Tiles) + + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.GameImage_Tilemap) + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.GameImage_Palette) + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + // Enable NMI interrupt + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + + // Setup PPU registers + lda.b #INIDISP.force | 0xf + sta.w inidisp_shadow + sta.w INIDISP + + lda.b #1 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + MainLoop: + jsr LoadImage_Map + + jsr FadeInTransition + jsr WaitOneSecond + jsr FadeToForceBlank + + jsr LoadImage_Game + + jsr FadeInTransition + jsr WaitOneSecond + jsr FadeToForceBlank + + bra MainLoop +} + + + +namespace Resources { + insert MapImage_Tiles, "../../gen/inidisp-fadein-fadeout/map.4bpp" + insert MapImage_Tilemap, "../../gen/inidisp-fadein-fadeout/map.tilemap" + insert MapImage_Palette, "../../gen/inidisp-fadein-fadeout/map.palette" + + insert GameImage_Tiles, "../../gen/inidisp-fadein-fadeout/game.4bpp" + insert GameImage_Tilemap, "../../gen/inidisp-fadein-fadeout/game.tilemap" + insert GameImage_Palette, "../../gen/inidisp-fadein-fadeout/game.palette" +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/repeating_hdma_pattern.asm b/roms/snes-test-roms/src/effects/repeating_hdma_pattern.asm new file mode 100644 index 00000000..b9fba0c4 --- /dev/null +++ b/roms/snes-test-roms/src/effects/repeating_hdma_pattern.asm @@ -0,0 +1,501 @@ +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// This example uses HDMA indirect mode to repeat a 37 scanline HDMA +// effect across the entire display. +// +// HDMA indirect addressing mode allows me to write a HDMA table that +// contains multiple pointers to the same data. This allows me to +// repeat a dynamic HDMA pattern multiple times while only calculating +// the HDMA data values once per frame. +// +// This example also employs double buffering of the HDMA pattern data +// to prevent screen tearing and/or glitches. + + + +define ROM_NAME = "REPEATING HDMA PATTERN" +define VERSION = 0 + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 + +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../common.inc" + + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// VRAM Map +constant VRAM_BG3_MAP_WADDR = 0x0000 +constant VRAM_BG3_TILES_WADDR = 0x1000 + + +constant DISPLAY_HEIGHT = 224 + + +// Using a prime number to demonstrate the code works for any size pattern +constant HDMA_PATTERN_LINES = 37 + + +// Velocity of the cloud background +// (2x 16:16 unsigned fractional integer) +constant CLOUDS_X_VELOCITY = -0x018000; +constant CLOUDS_Y_VELOCITY = 0x00cccc; + + + +// BG3 horizontal and vertical offset shadows (with storage for fractional-subpixels) +// (2x 16:16 unsigned fractional integer) +allocate(bg3_hofs_sx, lowram, 2) +allocate(bg3_hofs, lowram, 2) +allocate(bg3_vofs_sx, lowram, 2) +allocate(bg3_vofs, lowram, 2) + + +// A double-buffer to store the HDMA pattern to. +// +// The `activeHdmaPatternBuffer` flag is used to determine which buffer +// to write to. +// +// (2x uint16[HDMA_PATTERN_LINES] ) +allocate(hdmaPatternBuffer_A, lowram, 2 * HDMA_PATTERN_LINES) +allocate(hdmaPatternBuffer_B, lowram, 2 * HDMA_PATTERN_LINES) + + +// Flag to determine which of the two HDMA Pattern buffers is active. +// +// Zero = hdmaPatternBuffer_A +// Non-Zero = hdmaPatternBuffer_B +// +// (byte flag) +allocate(activeHdmaPatternBuffer, lowram, 1) + + + +// NMI Handler - does nothing +au() +iu() +code() +function NmiHandler { + rti +} + + + +// Waits until the start of VBlank +// REQUIRES: NMI enabled +// REQUIRES: DB access registers +au() +iu() +code() +function WaitFrame { + php + sep #$20 +a8() + + // Wait until end of vBlank (if in vBlank) + assert(HVBJOY.vBlank == 0x80) + - + lda.l HVBJOY + bmi - + + + // Wait until start of the next vBlank + - + wai + assert(HVBJOY.vBlank == 0x80) + lda.l HVBJOY + bpl - + + plp + + rts +} + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + jsr WaveyCloudEffect__Setup + + + // Enable NMI interrupts + // (required by WaitFrame) + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + + // Wait until VBlank before enabling the screen + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + + Loop: + jsr WaveyCloudEffect__Process + + jsr WaitFrame + // In VBlank + jsr WaveyCloudEffect__VBlank + + bra Loop +} + + + +// Effect setup routine. +// +// Reset effect variables, initialize the PPU and upload data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// MODIFIES: enables force-blank +a8() +i16() +code() +function WaveyCloudEffect__Setup { + stz.w NMITIMEN + + + // Force blank + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + + // Reset variables + + // reset 16 bit variables + ldx.w #0 + stx.w bg3_hofs_sx + stx.w bg3_hofs + stx.w bg3_vofs_sx + stx.w bg3_vofs + + // reset 8 bit variables + stz.w activeHdmaPatternBuffer + + + + // Set PPU registers + + lda.b #1 + sta.w BGMODE + + lda.b #(VRAM_BG3_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG3SC + + lda.b #(VRAM_BG3_TILES_WADDR / BG34NBA.walign) << BG34NBA.bg3.shift + sta.w BG34NBA + + lda.b #TM.bg3 + sta.w TM + + + + // Transfer tiles and map to VRAM + + ldx.w #VRAM_BG3_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Clouds_Tilemap) + + + ldx.w #VRAM_BG3_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Clouds_Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Clouds_Palette) + + + rts +} + + + +// Horizontal offset offsets for the HDMA effect +// +// Each byte contains the value to shift the BG3HOFS register by. +// +// +// Calculated using python: +// +// >>> [ int((math.sin(i / 37 * math.tau) + 1) * 5.5) for i in range(37) ] +// +// +// (const uint8 array) +HOffset_Table: + db 5, 6, 7, 8, 8, 9, 10, 10, 10, 10, 10, 10, 10, 9, 9, 8, 7, 6, 5, 5, 4, 3, 2, 1, 1, 0, 0, 0, 0, 0, 0, 0, 1, 2, 2, 3, 4 +constant HOffset_Table.size = pc() - HOffset_Table + +assert(HOffset_Table.size == HDMA_PATTERN_LINES) + + + +// Effect process routine. +// +// This routine is to be called once per frame. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function WaveyCloudEffect__Process { + + + // Get address of the next pattern buffer + // (ie, get the non-active buffer) + lda.w activeHdmaPatternBuffer + bne + + // A == 0 + ldy.w #hdmaPatternBuffer_B + bra ++ + + + // A != 0 + ldy.w #hdmaPatternBuffer_A + + + // Y = pattern Buffer Address + + + rep #$20 +a16() + + + // Update BG scroll offset + + // MUST NOT MODIFY Y + + // 32 bit addition + // bg3_hofs += CLOUDS_X_VELOCITY + clc + lda.w bg3_hofs_sx + adc.w #CLOUDS_X_VELOCITY + sta.w bg3_hofs_sx + + lda.w bg3_hofs + adc.w #CLOUDS_X_VELOCITY >> 16 + sta.w bg3_hofs + + + // 32 bit addition + // bg3_vofs += CLOUDS_Y_VELOCITY + clc + lda.w bg3_vofs_sx + adc.w #CLOUDS_Y_VELOCITY + sta.w bg3_vofs_sx + + lda.w bg3_vofs + adc.w #CLOUDS_Y_VELOCITY >> 16 + sta.w bg3_vofs + + + + // Populate HDMA pattern buffer + // + // Y = pattern Buffer Address + + // for x in 0 to HOffset_Table.size: + // *bufferPtr++ = HOffset_Table[x] + bg3_hofs + // + + ldx.w #0 + + Loop: + // Y = pattern Buffer Address + + lda.l HOffset_Table,x + and.w #0xff + clc + adc.w bg3_hofs + + sta.w 0,y + iny + iny + + inx + cpx.w #HOffset_Table.size + bcc Loop + + + + sep #$20 +a8() + + + // Swap active pattern buffer + lda.w activeHdmaPatternBuffer + bne + + // activeHdmaPatternBuffer == 0 + lda.b #0xff + sta.w activeHdmaPatternBuffer + bra ++ + + + // activeHdmaPatternBuffer != 0 + stz.w activeHdmaPatternBuffer + + + + rts +} + + + +// Create a repeating HDMA indirect table for the given `patternBuffer`. +macro buildHdmaTable(patternBuffer) { + assert(HDMA_PATTERN_LINES < 127) + + evaluate n = (DISPLAY_HEIGHT + HDMA_PATTERN_LINES - 1) / HDMA_PATTERN_LINES + + while {n} > 0 { + // HDMA_PATTERN_LINES scanlines in repeat mode + db 0x80 | HDMA_PATTERN_LINES + // pointer to pattern data + dw {patternBuffer} + + evaluate n = {n} - 1 + } + + // end of HDMA table + db 0 +} + +HdmaTable_Pattern_A: + buildHdmaTable(hdmaPatternBuffer_A) + +HdmaTable_Pattern_B: + buildHdmaTable(hdmaPatternBuffer_B) + + + +// Effect VBlank routine. +// +// +// NOTE: Uses DMA Channel 7 for HDMA +// +// REQUIRES: In VBlank +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function WaveyCloudEffect__VBlank { + + // Disable HDMA + stz.w HDMAEN + + + + // Update BG3VOFS + lda.w bg3_vofs + sta.w BG3VOFS + lda.w bg3_vofs + 1 + sta.w BG3VOFS + + + + // Setup HDMA + + // Get HDMA Table address + lda.w activeHdmaPatternBuffer + bne + + // A == 0 + ldx.w #HdmaTable_Pattern_A + bra ++ + + + // A != 0 + ldx.w #HdmaTable_Pattern_B + + + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.indirect | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG3HOFS + sta.w BBAD7 + + // X = HDMA Table address + stx.w A1T7 + + lda.b #HdmaTable_Pattern_A >> 16 + sta.w A1B7 + + + // Indirect address bank (Pattern data in Work-RAM) + lda.b #0x7e + sta.w DASB7 + + + // Enable HDMA + lda.b #HDMAEN.dma7 + sta.w HDMAEN + + + rts +} + + + +namespace Resources { + insert Clouds_Tilemap, "../../gen/example-backgrounds/clouds-tilemap.bin" + + insert Clouds_Tiles, "../../gen/example-backgrounds/clouds-2bpp-tiles.tiles" + insert Clouds_Palette, "../../gen/example-backgrounds/clouds-2bpp-tiles.pal" +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-0.asm b/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-0.asm new file mode 100644 index 00000000..c33ddac0 --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-0.asm @@ -0,0 +1,498 @@ +// A simple demo that uses VMAIN to quickly convert 1bpp tiles to 2bpp tiles +// and transfer them into vram. +// +// This demo will set the high bits to 0, effectively creating tiles +// that use 2bpp palette colours 0 (transparent) & 1. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VMAIN 1BPP TILES 0" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 // 32x32 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + +// The size of a single tilemap +constant TILEMAP_WIDTH = 32 +constant TILEMAP_HEIGHT = 32 + + + +// Temporary zero-page word variable +// (word) +allocate(zpTmp0, zeropage, 2) + + + + +// Transfer 1bpp tiles to VRAM, converting the 1bpp tiles to 2bpp tiles +// with a high bit of 0. +// +// The tiles will have transparent pixels and will use 2bpp palette colours 0 & 1. +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +// REQUIRES: Force Blank enabled +// +// Uses DMA channel 0 +// +// INPUT: zpTmp0 = VRAM word address to store the tile data +// A:X = address of 1bpp tile data +// Y = size of 1bpp tile data +a8() +i16() +code() +function Transfer1bppTilesToVram_0 { + + // First DMA transfer. + // + // Transfer the tiles data to the VRAM low bytes (VMADDL). + + // MUST NOT modify Y + + // A:X = 1bpp tile address + stx.w A1T0 + sta.w A1B0 + + // Y = size + sty.w DAS0 + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + + lda.b #VMAIN.incrementMode.low | VMAIN.increment.by1 + sta.w VMAIN + + ldx.b zpTmp0 + stx.w VMADD + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + + // Second DMA transfer. + // + // Fill the high bits with zeros + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldx.b zpTmp0 + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one | DMAP.fixed + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #Resources.ZeroByte + stx.w A1T0 + lda.b #Resources.ZeroByte >> 16 + sta.w A1B0 + + // Y = size + sty.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Set PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + // Transfer tilemap to VRAM + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Map) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + // Clear the first tile in BG1 + ldx.w #VRAM_BG1_TILES_WADDR + ldy.w #16 + jsr Dma.ForceBlank.ClearVram + + + // Transfer 1bpp tiles to VRAM + + // Start transfer from tile 1, tile 0 will be fully transparent. + ldx.w #VRAM_BG1_TILES_WADDR + 8 + stx.b zpTmp0 + + ldx.w #Resources.Tiles_1bpp + lda.b #Resources.Tiles_1bpp >> 16 + ldy.w #Resources.Tiles_1bpp.size + + jsr Transfer1bppTilesToVram_0 + + + + // Wait until VBlank + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + wai + + // Enable screen, full brightness + lda.b #15 + sta.w INIDISP + + + MainLoop: + wai + bra MainLoop +} + + + + +// Interrupts +// ========== + + +// NMI ISR +// +// Does nothing +au() +iu() +code() +function NmiHandler { + rti +} + + + +// Resources +// ========= + +namespace Resources { + + +ZeroByte: + db 0 + + +Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 31, 31) + dw ToPalette(31, 0, 0) + dw ToPalette(31, 0, 0) + +constant Palette.size = pc() - Palette + + + +Tiles_1bpp: + db %01000010 + db %01000010 + db %01000010 + db %01111110 + db %01000010 + db %01000010 + db %01000010 + db %00000000 + + db %01111110 + db %01000000 + db %01000000 + db %01111000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %00111100 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %00111100 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %01000010 + db %01000010 + db %01011010 + db %01011010 + db %01100110 + db %01100110 + db %01000010 + db %00000000 + + db %00111100 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %00111100 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01001000 + db %01000100 + db %01000010 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01111000 + db %01000100 + db %01000010 + db %01000010 + db %01000010 + db %01000100 + db %01111000 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %00111110 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00111110 + db %00000000 + + db %01100010 + db %01100010 + db %01010010 + db %01010010 + db %01001010 + db %01001010 + db %01000110 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %00011000 + db %00101000 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00111110 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000000 + db %01000000 + db %01000000 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000000 + db %01000000 + db %01000000 + db %00000000 + + db %00011000 + db %00011000 + db %00011000 + db %00011000 + db %00000000 + db %00000000 + db %00011000 + db %00000000 + + +constant Tiles_1bpp.size = pc() - Tiles_1bpp + +assert(Tiles_1bpp.size % 8 == 0) +constant N_TILES = Tiles_1bpp.size / 8 + + + +assert(N_TILES < TILEMAP_WIDTH) + +constant MARGIN_TOP = 6 +constant MARGIN_LEFT = (TILEMAP_WIDTH - N_TILES) / 2 + + +Map: + fill MARGIN_TOP * TILEMAP_WIDTH * 2, 0 + + fill MARGIN_LEFT * 2, 0 + + variable _i = 0 + while _i < N_TILES { + dw _i + 1 + _i = _i + 1 + } + fill (TILEMAP_WIDTH - MARGIN_LEFT - N_TILES) * 2, 0 + + fill (TILEMAP_HEIGHT - MARGIN_TOP - 1) * TILEMAP_WIDTH * 2, 0 + +constant Map.size = pc() - Map + +assert(Map.size == TILEMAP_WIDTH * TILEMAP_HEIGHT * 2) + + +} + + diff --git a/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-1.asm b/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-1.asm new file mode 100644 index 00000000..f15a5665 --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-1bpp-tiles-1.asm @@ -0,0 +1,517 @@ +// A simple demo that uses VMAIN to quickly convert 1bpp tiles to 2bpp tiles +// and transfer them into vram. +// +// This demo will set the high bits to 1, effectively creating fully opaque +// tiles that use 2bpp palette colours 2 & 3. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VMAIN 1BPP TILES 1" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 // 32x32 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + +// The size of a single tilemap +constant TILEMAP_WIDTH = 32 +constant TILEMAP_HEIGHT = 32 + + + +// Temporary zero-page word variable +// (word) +allocate(zpTmp0, zeropage, 2) + + + + +// Transfer 1bpp tiles to VRAM, converting the 1bpp tiles to 2bpp tiles +// with a high bit of 1. +// +// The tiles will be fully opaque and will use 2bpp palette colours 2 & 3. +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +// REQUIRES: Force Blank enabled +// +// Uses DMA channel 0 +// +// INPUT: zpTmp0 = VRAM word address to store the tile data +// A:X = address of 1bpp tile data +// Y = size of 1bpp tile data +a8() +i16() +code() +function Transfer1bppTilesToVram_1 { + + // First DMA transfer. + // + // Transfer the tiles data to the VRAM low bytes (VMADDL). + + // MUST NOT modify Y + + // A:X = 1bpp tile address + stx.w A1T0 + sta.w A1B0 + + // Y = size + sty.w DAS0 + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + + lda.b #VMAIN.incrementMode.low | VMAIN.increment.by1 + sta.w VMAIN + + ldx.b zpTmp0 + stx.w VMADD + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + + // Second DMA transfer. + // + // Fill the high bits with ones (0xff) + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldx.b zpTmp0 + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one | DMAP.fixed + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #Resources.FixedByteFF + stx.w A1T0 + lda.b #Resources.FixedByteFF >> 16 + sta.w A1B0 + + // Y = size + sty.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Set PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + // Transfer tilemap to VRAM + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Map) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + + // Clear the first tile in BG1 + ldx.w #VRAM_BG1_TILES_WADDR + ldy.w #16 + jsr Dma.ForceBlank.ClearVram + + + // Transfer 1bpp tiles to VRAM + + // Start transfer from tile 1, tile 0 will be fully transparent. + ldx.w #VRAM_BG1_TILES_WADDR + 8 + stx.b zpTmp0 + + ldx.w #Resources.Tiles_1bpp + lda.b #Resources.Tiles_1bpp >> 16 + ldy.w #Resources.Tiles_1bpp.size + + jsr Transfer1bppTilesToVram_1 + + + + // Wait until VBlank + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + wai + + // Enable screen, full brightness + lda.b #15 + sta.w INIDISP + + + MainLoop: + wai + bra MainLoop +} + + + + +// Interrupts +// ========== + + +// NMI ISR +// +// Does nothing +au() +iu() +code() +function NmiHandler { + rti +} + + + +// Resources +// ========= + +namespace Resources { + + +FixedByteFF: + db 0xff + + +Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 0, 0) + dw ToPalette( 0, 6, 12) + dw ToPalette(31, 31, 31) + +constant Palette.size = pc() - Palette + + + +Tiles_1bpp: + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %01000010 + db %01000010 + db %01000010 + db %01111110 + db %01000010 + db %01000010 + db %01000010 + db %00000000 + + db %01111110 + db %01000000 + db %01000000 + db %01111000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %00111100 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %00111100 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %01000010 + db %01000010 + db %01011010 + db %01011010 + db %01100110 + db %01100110 + db %01000010 + db %00000000 + + db %00111100 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %01000010 + db %00111100 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01001000 + db %01000100 + db %01000010 + db %00000000 + + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01000000 + db %01111110 + db %00000000 + + db %01111000 + db %01000100 + db %01000010 + db %01000010 + db %01000010 + db %01000100 + db %01111000 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %00111110 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00111110 + db %00000000 + + db %01100010 + db %01100010 + db %01010010 + db %01010010 + db %01001010 + db %01001010 + db %01000110 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + db %00011000 + db %00101000 + db %00001000 + db %00001000 + db %00001000 + db %00001000 + db %00111110 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000000 + db %01000000 + db %01000000 + db %00000000 + + db %01111100 + db %01000010 + db %01000010 + db %01111100 + db %01000000 + db %01000000 + db %01000000 + db %00000000 + + db %00011000 + db %00011000 + db %00011000 + db %00011000 + db %00000000 + db %00000000 + db %00011000 + db %00000000 + + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + +constant Tiles_1bpp.size = pc() - Tiles_1bpp + +assert(Tiles_1bpp.size % 8 == 0) +constant N_TILES = Tiles_1bpp.size / 8 + + + +assert(N_TILES < TILEMAP_WIDTH) + +constant MARGIN_TOP = 6 +constant MARGIN_LEFT = (TILEMAP_WIDTH - N_TILES) / 2 + + +Map: + fill MARGIN_TOP * TILEMAP_WIDTH * 2, 0 + + fill MARGIN_LEFT * 2, 0 + + variable _i = 0 + while _i < N_TILES { + dw _i + 1 + _i = _i + 1 + } + fill (TILEMAP_WIDTH - MARGIN_LEFT - N_TILES) * 2, 0 + + fill (TILEMAP_HEIGHT - MARGIN_TOP - 1) * TILEMAP_WIDTH * 2, 0 + +constant Map.size = pc() - Map + +assert(Map.size == TILEMAP_WIDTH * TILEMAP_HEIGHT * 2) + + +} + + diff --git a/roms/snes-test-roms/src/effects/vmain-horizontal-scrolling.asm b/roms/snes-test-roms/src/effects/vmain-horizontal-scrolling.asm new file mode 100644 index 00000000..90f2c13e --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-horizontal-scrolling.asm @@ -0,0 +1,456 @@ +// A horizontally scrolling demo that displays a map that is more than 64 tiles long. +// +// This demo uses the VMAIN register (in "increment by 32" mode) to transfer an +// entire column of tilemap cells to VRAM in a single DMA transfer. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VMAIN HORIZONTAL SCROLLING" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 // 64x32 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// The size of a single tilemap (BG1 is 2 tilemaps wide) +constant TILEMAP_WIDTH = 32 +constant TILEMAP_HEIGHT = 32 +constant TILEMAP_WORD_SIZE = TILEMAP_WIDTH * TILEMAP_HEIGHT + + + +// A buffer holding a column of tilemap cells. +// +// (32x tilemap word entries) +allocate(columnBuffer, lowram, TILEMAP_HEIGHT * 2) +constant columnBuffer.size = TILEMAP_HEIGHT * 2 + + +// If this value is zero, the `columnBuffer` will be transferred to VRAM on the next VBlank. +// (byte flag) +allocate(transferColumnBufferOnZero, lowram, 1) + + +// The VRAM word address to transfer the `columnBuffer` to. +// +// (VRAM word address) +allocate(columnBufferVramWaddr, lowram, 2) + + +// The index within the map data for the last transferred column. +// +// NOTE: This index is incremented before the Map Data is read as +// to keep it in sync with `columnBufferVramWaddr`. +// +// (Word Index into `Map`) +allocate(columnBufferMapPos, lowram, 2) + + + +// Shadow variable of the BG1 Horizontal Offset register +// (uint16) +allocate(bg1_hofs, lowram, 2) + + +// Used to determine if the next column is to be uploaded to VRAM +// (byte) +allocate(maskedHofsPreviousColumnDraw, lowram, 1) + + + +// Initialise the column buffer +// +// REQUIRES: 8 bit A, 16 bit Index, DB = REGISTER, DP = 0 +a8() +i16() +code() +function InitColumnBuffer { + lda.b #1 + sta.w transferColumnBufferOnZero + + // Set `vramWaddr` to the last column in the second tilemap. + // On the next call to `DrawNextColumn`, `vramWaddr` will be incremented to the first column of the first tilemap. + ldx.w #VRAM_BG1_MAP_WADDR + TILEMAP_WORD_SIZE + (TILEMAP_WIDTH - 1) + stx.w columnBufferVramWaddr + + // Also set `columnBufferMapPos` to the end of the map + // (keeping it in sync with `columnBufferVramWaddr`) + ldx.w #(Map.MAP_WIDTH - 1) * 2 + stx.w columnBufferMapPos + + + rts +} + + + +// Populate the `columnBuffer` with the next map column +// and schedule a DMA transfer for the next VBlank. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access low-RAM, DP = 0 +a8() +i16() +code() +function DrawNextColumn { + rep #$30 +a16() + + // Increment `columnBufferVramWaddr`, advancing to the next tilemap as required + lda.w columnBufferVramWaddr + inc + cmp.w #VRAM_BG1_MAP_WADDR + TILEMAP_WORD_SIZE + TILEMAP_WIDTH + bcc + + // Past the end of the second tilemap, go back to the start of the first tilemap + lda.w #VRAM_BG1_MAP_WADDR + bra ++ + + + cmp.w #VRAM_BG1_MAP_WADDR + TILEMAP_WIDTH + bne + + // Past the end of the first tilemap, go to the second tilemap + lda.w #VRAM_BG1_MAP_WADDR + TILEMAP_WORD_SIZE + + + sta.w columnBufferVramWaddr + + + // Increment `columnBufferMapPos` with wrapping + lda.w columnBufferMapPos + inc + inc + cmp.w #Map.MAP_WIDTH * 2 + bcc + + lda.w #0 + + + sta.w columnBufferMapPos + + tax + + + // Populate the `columnBuffer` with a column of Map cells + // + // X = index into Map + // Y = index into columnBuffer + ldy.w #0 + Loop: + lda.l Map.Data,x + sta.w columnBuffer,y + + txa + clc + adc.w #Map.MAP_WIDTH * 2 + tax + + iny + iny + cpy.w #columnBuffer.size + bcc Loop + + + sep #$20 +a8() + + // Transfer the `columnBuffer` to VRAM on the next VBlank + stz.w transferColumnBufferOnZero + + rts +} + + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = registers, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Transfer `columnBuffer` to VRAM if `transferColumnBufferOnZero` is zero. + lda.w transferColumnBufferOnZero + bne + + // Transfer one tilemap column to VRAM + lda.b #VMAIN.increment.by32 | VMAIN.incrementMode.high + sta.w VMAIN + + + ldx.w columnBufferVramWaddr + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #columnBuffer + stx.w A1T0 + lda.b #columnBuffer >> 16 + sta.w A1B0 + + ldx.w #columnBuffer.size + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // A is non-zero + sta.w transferColumnBufferOnZero + + + + + lda.w bg1_hofs + sta.w BG1HOFS + lda.w bg1_hofs + 1 + sta.w BG1HOFS +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Initialise column buffer + jsr InitColumnBuffer + + + // Set PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s64x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + // Set BG1 Vertical Offset to -1. + lda.b #0xff + sta.w BG1VOFS + sta.w BG1VOFS + + + // Transfer tiles and palette to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + EnableVblankInterrupts() + + + + jsr WaitFrame + + // Enable screen, full brightness (still in VBlank) + lda.b #15 + sta.w INIDISP + + + + // Slowly draw the first 32 columns + lda.b #TILEMAP_WIDTH + 2 + InitialDrawLoop: + pha + jsr DrawNextColumn + + jsr WaitFrame + jsr WaitFrame + pla + dec + bne InitialDrawLoop + + + + // Scroll BG1 horizontally, drawing new columns when needed. + MainLoop: + ldx.w bg1_hofs + inx + inx + inx + stx.w bg1_hofs + + txa + and.b #~7 + cmp.w maskedHofsPreviousColumnDraw + beq + + sta.w maskedHofsPreviousColumnDraw + + jsr DrawNextColumn + + + + jsr WaitFrame + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { +Tiles: +// Blank tile + fill 16, 0 + +// Tilled tile + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + +constant Tiles.size = pc() - Tiles + + +Palette: + dw ToPalette( 0, 0 , 0) + dw ToPalette(22, 6, 6) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + + dw ToPalette( 0, 0 , 0) + dw ToPalette(11, 13, 28) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + +constant Palette.size = pc() - Palette +} + + + +// The map to display +// +// (Grid of TileMap words) +namespace Map { + +constant MAP_WIDTH = 164 +constant MAP_HEIGHT = 32 + + +constant _ = 0 +constant H = 1 | (0 << Tilemap.palette.shift) +constant W = 1 | (1 << Tilemap.palette.shift) + + +Data: + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,W,W,W,W,_,_,_,_,_,W,W,W,W,W,W,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,W,W,W,W,_,_,_,_,W,W,W,W,W,W,W,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,H,_,_,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,W,_,_,W,W,W,_,_,_,W,W,_,_,_,W,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,W,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,W,W,W,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,W,W,W,W,W,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,W,W,W,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,W,W,W,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,W,W,W,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,W,W,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,W,W,W,W,W,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,W,W,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,W,W,W,W,W,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,W,W,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,_,W,W,W,W,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,_,W,W,W,W,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,H,H,H,_,_,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,W,W,W,_,_,W,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,_,_,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,_,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,W,W,W,W,W,W,_,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,W,W,W,W,W,W,W,_,_,_,W,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,H,H,_,_,_,_,H,H,_,_,_,H,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,_,_,_,_,_,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,_,_,_,_,W,W,W,W,_,_,_,_,_,W,W,_,_,_,_,_,W,W,_,_,_,W,W,W,W,W,W,W,_,_,_,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, +constant Data.size = pc() - Data + +assert(Data.size == MAP_WIDTH * MAP_HEIGHT * 2) + +} + diff --git a/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-columns.asm b/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-columns.asm new file mode 100644 index 00000000..c2505320 --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-columns.asm @@ -0,0 +1,315 @@ +// A simple demo that uses VMAIN to draw an entire Mode 7 tilemap column +// in a single DMA transfer. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "MODE7 TILEMAP COLUMNS" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +constant MODE7_TILEMAP_WIDTH = 128 +constant MODE7_TILEMAP_HEIGHT = 128 + + +constant COLUMNS_TO_TRANSFER = 32 + +assert(COLUMNS_TO_TRANSFER < MODE7_TILEMAP_WIDTH) + + +constant MODE7_MATRIX_A = 0x0100 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0100 + + + +// If this variable is zero, draw the next column on the next VBlank +// +// (byte flag) +allocate(transferColumnOnZero, lowram, 1) + + +// VRAM word address of the next mode-7 column to transfer. +// +// This variable MUST contain a value < `MODE7_TILEMAP_WIDTH`. +// +// (VRAM word address) +allocate(columnVramWaddr, lowram, 2) + + +// The tileId of the column to draw. +// +// (byte) +allocate(columnTile, lowram, 1) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = registers, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + + lda.w transferColumnOnZero + bne NoTransfer + + // Transfer one MODE7 tilemap column to VRAM + lda.b #VMAIN.incrementMode.low | VMAIN.increment.by128 + sta.w VMAIN + + + ldx.w columnVramWaddr + stx.w VMADD + + + // Transfer `MODE7_TILEMAP_HEIGHT` copies of the `columnTile` byte to the mode 7 tilemap + lda.b #DMAP.direction.toPpu | DMAP.transfer.one | DMAP.fixed + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #columnTile + stx.w A1T0 + lda.b #columnTile >> 16 + sta.w A1B0 + + ldx.w #MODE7_TILEMAP_HEIGHT + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // A is non-zero + sta.w transferColumnOnZero + + NoTransfer: +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + + // Setup variables + ldx.w #0 + stx.w columnVramWaddr + + lda.b #1 + sta.w columnTile + + stz.w transferColumnOnZero + + + + // Setup PPU registers + + // Mode 7 + lda.b #BGMODE.mode7 + sta.w BGMODE + + stz.w M7SEL + + + // Initialize Mode 7 matrix + lda.b #MODE7_MATRIX_A + sta.w M7A + lda.b #MODE7_MATRIX_A >> 8 + sta.w M7A + lda.b #MODE7_MATRIX_B + sta.w M7B + lda.b #MODE7_MATRIX_B >> 8 + sta.w M7B + lda.b #MODE7_MATRIX_C + sta.w M7C + lda.b #MODE7_MATRIX_C >> 8 + sta.w M7C + lda.b #MODE7_MATRIX_D + sta.w M7D + lda.b #MODE7_MATRIX_D >> 8 + sta.w M7D + + stz.w M7X + stz.w M7X + stz.w M7Y + stz.w M7Y + + + stz.w BG1HOFS + stz.w BG1HOFS + + lda.b #-1 + sta.w BG1VOFS + sta.w BG1VOFS + + + // Enable BG1 + lda.b #TM.bg1 + sta.w TM + + + // Clear Mode 7 Tilemap + ldx.w #0 + ldy.w #MODE7_TILEMAP_WIDTH * MODE7_TILEMAP_WIDTH + jsr Dma.ForceBlank.ClearVramL + + + // Transfer tiles and palette to VRAM + ldx.w #0 + stx.w VMADD + Dma.ForceBlank.ToVramH(Resources.Mode7Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + EnableVblankInterrupts(); + + jsr WaitFrame + + // Enable screen, full brightness (still in VBlank) + lda.b #15 + sta.w INIDISP + + + + MainLoop: + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + + + // Advance to the next column + ldx.w columnVramWaddr + inx + cpx.w #COLUMNS_TO_TRANSFER + bcc ++ + // Reached the end of the screen, start again with a different tile + lda.w columnTile + inc + cmp.b #Resources.N_TILES + bcc + + lda.b #0 + + + sta.w columnTile + + ldx.w #0 + + + stx.w columnVramWaddr + + stz.w transferColumnOnZero + + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { + + +Palette: + dw ToPalette( 0, 0 , 0) + dw ToPalette(31, 31, 31) + dw ToPalette(31, 0 , 0) + dw ToPalette( 0, 31 , 0) + dw ToPalette( 0, 0 , 31) + +constant Palette.size = pc() - Palette + + +constant N_TILES = Palette.size / 2 + + + +Mode7Tiles: + variable _i = 0 + while _i < N_TILES { + fill 64, _i + + _i = _i + 1 + } +constant Mode7Tiles.size = pc() - Mode7Tiles + +assert(Mode7Tiles.size == 8 * 8 * N_TILES) + +} + + diff --git a/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-rows.asm b/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-rows.asm new file mode 100644 index 00000000..f12e3d9e --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-mode7-tilemap-rows.asm @@ -0,0 +1,321 @@ +// A simple demo that uses VMAIN to draw an entire Mode 7 tilemap row +// in a single DMA transfer. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "MODE7 TILEMAP ROWS" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +constant MODE7_TILEMAP_WIDTH = 128 +constant MODE7_TILEMAP_HEIGHT = 128 + + +constant ROWS_TO_TRANSFER = 28 + +assert(ROWS_TO_TRANSFER < MODE7_TILEMAP_WIDTH) + + +constant MODE7_MATRIX_A = 0x0100 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0100 + + + +// If this variable is zero, draw the next row on the next VBlank +// +// (byte flag) +allocate(transferRowOnZero, lowram, 1) + + +// VRAM word address of the next mode-7 row to transfer. +// +// (VRAM word address) +allocate(rowVramWaddr, lowram, 2) + + +// The tileId of the row to draw. +// +// (byte) +allocate(rowTile, lowram, 1) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = registers, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + + lda.w transferRowOnZero + bne NoTransfer + + // Transfer one MODE7 tilemap row to VRAM + lda.b #VMAIN.incrementMode.low | VMAIN.increment.by1 + sta.w VMAIN + + + ldx.w rowVramWaddr + stx.w VMADD + + + // Transfer `MODE7_TILEMAP_HEIGHT` copies of the `rowTile` byte to the mode 7 tilemap + lda.b #DMAP.direction.toPpu | DMAP.transfer.one | DMAP.fixed + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #rowTile + stx.w A1T0 + lda.b #rowTile >> 16 + sta.w A1B0 + + ldx.w #MODE7_TILEMAP_WIDTH + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // A is non-zero + sta.w transferRowOnZero + + NoTransfer: +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + + // Setup variables + ldx.w #0 + stx.w rowVramWaddr + + lda.b #1 + sta.w rowTile + + stz.w transferRowOnZero + + + + // Setup PPU registers + + // Mode 7 + lda.b #BGMODE.mode7 + sta.w BGMODE + + stz.w M7SEL + + + // Initialize Mode 7 matrix + lda.b #MODE7_MATRIX_A + sta.w M7A + lda.b #MODE7_MATRIX_A >> 8 + sta.w M7A + lda.b #MODE7_MATRIX_B + sta.w M7B + lda.b #MODE7_MATRIX_B >> 8 + sta.w M7B + lda.b #MODE7_MATRIX_C + sta.w M7C + lda.b #MODE7_MATRIX_C >> 8 + sta.w M7C + lda.b #MODE7_MATRIX_D + sta.w M7D + lda.b #MODE7_MATRIX_D >> 8 + sta.w M7D + + stz.w M7X + stz.w M7X + stz.w M7Y + stz.w M7Y + + + stz.w BG1HOFS + stz.w BG1HOFS + + lda.b #-1 + sta.w BG1VOFS + sta.w BG1VOFS + + + // Enable BG1 + lda.b #TM.bg1 + sta.w TM + + + // Clear Mode 7 Tilemap + ldx.w #0 + ldy.w #MODE7_TILEMAP_WIDTH * MODE7_TILEMAP_WIDTH + jsr Dma.ForceBlank.ClearVramL + + + // Transfer tiles and palette to VRAM + ldx.w #0 + stx.w VMADD + Dma.ForceBlank.ToVramH(Resources.Mode7Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + EnableVblankInterrupts() + + jsr WaitFrame + + // Enable screen, full brightness (still in VBlank) + lda.b #15 + sta.w INIDISP + + + + MainLoop: + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + + + // Advance to the next row + rep #$30 + a16() + lda.w rowVramWaddr + clc + adc.w #MODE7_TILEMAP_WIDTH + cmp.w #MODE7_TILEMAP_WIDTH * ROWS_TO_TRANSFER + bcc + + lda.w #0 + + + sta.w rowVramWaddr + + sep #$20 + a8() + // carry set if `rowVramWaddr` has been reset + bcc ++ + // `rowVramWaddr` has been reset, draw a different tile + lda.w rowTile + inc + cmp.b #Resources.N_TILES + bcc + + lda.b #0 + + + sta.w rowTile + + + + stz.w transferRowOnZero + + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { + + +Palette: + dw ToPalette( 0, 0 , 0) + dw ToPalette(31, 31, 31) + dw ToPalette(31, 0 , 0) + dw ToPalette( 0, 31 , 0) + dw ToPalette( 0, 0 , 31) + +constant Palette.size = pc() - Palette + + +constant N_TILES = Palette.size / 2 + + + +Mode7Tiles: + variable _i = 0 + while _i < N_TILES { + fill 64, _i + + _i = _i + 1 + } +constant Mode7Tiles.size = pc() - Mode7Tiles + +assert(Mode7Tiles.size == 8 * 8 * N_TILES) + +} + + diff --git a/roms/snes-test-roms/src/effects/vmain-vertical-scrolling-2-rows.asm b/roms/snes-test-roms/src/effects/vmain-vertical-scrolling-2-rows.asm new file mode 100644 index 00000000..12d25174 --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-vertical-scrolling-2-rows.asm @@ -0,0 +1,647 @@ +// A vertically scrolling demo that displays a map that is more than 64 tiles tall, +// updating two tilemap rows at a time. +// +// This demo is preformed on a background that is two tilemaps wide and one tilemap +// tall (64x32 tiles). +// +// Due to the non-contiguous nature of a 64 tile wide tilemap, the transfer to VRAM +// requires 4 DMA transfers. This demo uses two DMA channels to transfer the +// buffer in two `MDMAEN` writes. See the `VBlank()` macro for more details. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VMAIN VERTICAL SCROLLING 2R" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 // 64x32 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// The size of a single tilemap (BG1 is 2 tilemaps wide) +constant TILEMAP_WIDTH = 32 +constant TILEMAP_HEIGHT = 32 +constant TILEMAP_WORD_SIZE = TILEMAP_WIDTH * TILEMAP_HEIGHT + + + +// If this value is zero, the `tilemapRowBuffer` will be transferred to VRAM on the next VBlank interrupt. +// (byte flag) +allocate(transferTilemapRowBufferOnZero, lowram, 1) + + +constant N_ROWS_TO_TRANSFER = 2 +constant ROW_BUFFER_WIDTH = 64 + +// A buffer holding two rows of tilemap cells. +// +// (64x2 grid of tilemap words) +allocate(tilemapRowBuffer, lowram, N_ROWS_TO_TRANSFER * ROW_BUFFER_WIDTH * 2) +constant tilemapRowBuffer.size = N_ROWS_TO_TRANSFER * ROW_BUFFER_WIDTH * 2 + + +// The VRAM word address to transfer `tilemapRowBuffer` to. +// +// (VRAM word address) +allocate(tilemapRowVramWaddr, lowram, 2) + + +// The index within the map data for the last transferred row. +// +// NOTE: This index is incremented before the Map Data is read as +// to keep it in sync with `tilemapRowVramWaddr`. +// +// (word index into `Map.Data`) +allocate(tilemapRowMapPos, lowram, 2) + + + +// Shadow variable of the BG1 Horizontal Offset register +// (uint16) +allocate(bg1_hofs, lowram, 2) + +// Shadow variable of the BG1 Vertical Offset register +// (uint16) +allocate(bg1_vofs, lowram, 2) + + + +// Camera Y position. +// +// (uint16) +allocate(cameraYpos, lowram, 2) + +// Used to determine if the next row is to be uploaded to VRAM +// (byte) +allocate(maskedCameraYpos, lowram, 1) + + + +// Initialize the tilemap row transfer subsystem. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = REGISTER, DP = 0 +a8() +i16() +code() +function InitTilemapRowTransfers { + lda.b #1 + sta.w transferTilemapRowBufferOnZero + + + // Set `tilemapRowVramWaddr` to the last row in the tilemap. + // On the next call to `QueueRowTransfer`, `tilemapRowVramWaddr`will be incremented to the first row of the tilemap. + ldx.w #VRAM_BG1_MAP_WADDR + TILEMAP_WORD_SIZE * 2 + stx.w tilemapRowVramWaddr + + + // Also set `tilemapRowMapPos` to the end of the map + // (keep it in sync with `tilemapRowVramWaddr`) + ldx.w #Map.Data.size + stx.w tilemapRowMapPos + + + ldx.w #0 + stx.w cameraYpos + + rts +} + + + +// Populate the `tilemapRowBuffer` with the next two map rows +// and schedule a DMA transfer for the next VBlank. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access low-RAM, DP = 0 +a8() +i16() +code() +function DrawNextTwoRows { + rep #$30 +a16() + + // Increment `tilemapRowVramWaddr`, wrapping as required + assert(TILEMAP_HEIGHT % N_ROWS_TO_TRANSFER == 0) + + lda.w tilemapRowVramWaddr + clc + adc.w #TILEMAP_WIDTH * N_ROWS_TO_TRANSFER + cmp.w #VRAM_BG1_MAP_WADDR + TILEMAP_WIDTH * TILEMAP_HEIGHT + bcc + + lda.w #VRAM_BG1_MAP_WADDR + + + sta.w tilemapRowVramWaddr + + + // Advance index to the next row, wrapping as necessary + lda.w tilemapRowMapPos + clc + adc.w #Map.MAP_WIDTH * N_ROWS_TO_TRANSFER * 2 + cmp.w #Map.Data.size + bcc + + lda.w #0 + + + sta.w tilemapRowMapPos + tax + + + + // Populate `tilemapRowBuffer` with 2 tilemap rows + // + // X = index into Map + // Y = index into one row of `tilemapRowBuffer` + ldy.w #0 + Loop: + assert(N_ROWS_TO_TRANSFER == 2) + lda.l Map.Data + 0 * Map.MAP_WIDTH * 2,x + sta.w tilemapRowBuffer + 0 * ROW_BUFFER_WIDTH * 2,y + + lda.l Map.Data + 1 * Map.MAP_WIDTH * 2,x + sta.w tilemapRowBuffer + 1 * ROW_BUFFER_WIDTH * 2,y + + inx + inx + + iny + iny + cpy.w #ROW_BUFFER_WIDTH * 2 + bcc Loop + + + sep #$20 +a8() + + // Transfer `tilemapRowBuffer` to VRAM on the next VBlank + stz.w transferTilemapRowBufferOnZero + + rts +} + + + + +// VBlank routine +// +// Uses DMA channels 0 & 1 +// +// REQUIRES: 8 bit A, 16 bit Index, DB = registers, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + + // Transfer tilemapRowBuffer to VRAM if `transferTilemapRowBufferOnZero` is zero + lda.w transferTilemapRowBufferOnZero + bne + + // Due to the discontiguous nature of a 64 tile wide tilemap the transfer of + // `tilemapRowBuffer` (a 64x2 word grid) to VRAM requires 4 DMA transfers. + // + // * tilemapRowBuffer[ 0 - 63] to VRAM word address `tilemapRowVramWaddr` + // * tilemapRowBuffer[128 - 191] to VRAM word address `tilemapRowVramWaddr + 32` + // * tilemapRowBuffer[ 64 - 127] to VRAM word address `tilemapRowVramWaddr + 0x400` + // * tilemapRowBuffer[192 - 255] to VRAM word address `tilemapRowVramWaddr + 0x400 + 32` + // + // + // By using two DMA channels, one for the top row and a second for the bottom row, + // we can transfer the left and right quarters of the buffer to VRAM in a single + // `MDMAEN` write. After the transfer, the final two quarters will be transferred. + // + // * tilemapRowBuffer[ 0 - 63] and tilemapRowBuffer[128 - 191] to VRAM word address `tilemapRowVramWaddr` + // * tilemapRowBuffer[ 64 - 127] and tilemapRowBuffer[192 - 255] to VRAM word address `tilemapRowVramWaddr + 0x400` + + assert(tilemapRowBuffer.size == 2 * 64 * 2) + + // Set VMAIN to normal word access + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w tilemapRowVramWaddr + stx.w VMADD + + + // Setup Two DMA channels, transfer from `tilemapRowBuffer` and `tilemapRowBuffer + 128` to VRAM + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + sta.w DMAP1 + + lda.b #VMDATA + sta.w BBAD0 + sta.w BBAD1 + + ldx.w #tilemapRowBuffer + stx.w A1T0 + ldx.w #tilemapRowBuffer + 128 + stx.w A1T1 + + lda.b #tilemapRowBuffer >> 16 + sta.w A1B0 + sta.w A1B1 + + + // Transfer the first half of both rows to the first tilemap + // (located at VRAM Word address `tilemapRowVramWaddr`) + ldx.w #TILEMAP_WIDTH * 2 + stx.w DAS0 + stx.w DAS1 + + // Transfer two DMA channels at once + lda.b #MDMAEN.dma1 | MDMAEN.dma0 + sta.w MDMAEN + + + // Transfer the second half of both row to the second tilemap + // (located at VRAM Word address `tilemapRowVramWaddr + TILEMAP_WORD_SIZE`) + // + // No need to set the DMA control, destination or address registers. They are already contain the correct values. + // + // After the first transfer, the source address on DMA channel 0 is `tilemapRowBuffer + 64` and + // the source address on channel 1 is `tilemapRowBuffer + 128 + 64`. + + // X contains `TILEMAP_WIDTH * 2` + stx.w DAS0 + stx.w DAS1 + + + // Set VRAM word Address to `tilemapRowVramWaddr + TILEMAP_WORD_SIZE` + assert(TILEMAP_WORD_SIZE & 0xff == 0) + lda.w tilemapRowVramWaddr + sta.w VMADDL + + lda.w tilemapRowVramWaddr + 1 + clc + adc.b #TILEMAP_WORD_SIZE >> 8 + sta.w VMADDH + + + // Transfer two DMA channels at once + lda.b #MDMAEN.dma1 | MDMAEN.dma0 + sta.w MDMAEN + + + // A is non-zero + sta.w transferTilemapRowBufferOnZero + + + + + // Transfer bg1 offset shadow variables to PPU + lda.w bg1_hofs + sta.w BG1HOFS + lda.w bg1_hofs + 1 + sta.w BG1HOFS + + lda.w bg1_vofs + sta.w BG1VOFS + lda.w bg1_vofs + 1 + sta.w BG1VOFS +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Initialise the tilemap row transfers + jsr InitTilemapRowTransfers + + + // Offset BG1 so both the left and right tilemaps are onscreen + ldx.w #128 + stx.w bg1_hofs + + ldx.w #0 + stx.w cameraYpos + + + // Set PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s64x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + // Transfer tiles and palette to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + EnableVblankInterrupts() + + + jsr WaitFrame + + // Enable screen, full brightness (still in VBlank) + lda.b #15 + sta.w INIDISP + + + + // Slowly draw the first 15 pairs of rows + lda.b #15 + InitialDrawLoop: + pha + jsr DrawNextTwoRows + + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + pla + dec + bne InitialDrawLoop + + + + // Scroll BG1 vertically, drawing new rows as required + MainLoop: + rep #$30 + a16() + lda.w cameraYpos + clc + adc.w #1 + sta.w cameraYpos + + // Must adjust the vertical offset by -1 to align the Background and Object layers. + dec + sta.w bg1_vofs + + sep #$20 + a8() + + assertPowerOfTwo(N_ROWS_TO_TRANSFER) + and.b #~((N_ROWS_TO_TRANSFER * 8) - 1) + cmp.w maskedCameraYpos + beq + + sta.w maskedCameraYpos + + jsr DrawNextTwoRows + + + + jsr WaitFrame + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { +Tiles: +// Blank tile + fill 16, 0 + +// Tilled tile + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + +constant Tiles.size = pc() - Tiles + + +Palette: + dw ToPalette( 0, 0 , 0) + dw ToPalette(22, 6, 6) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + + dw ToPalette( 0, 0 , 0) + dw ToPalette(11, 13, 28) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + + dw ToPalette( 0, 0 , 0) + dw ToPalette(27, 21, 12) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + +constant Palette.size = pc() - Palette +} + + + +// The map to display +// +// (Grid of TileMap words) +namespace Map { + +constant MAP_WIDTH = 70 +constant MAP_HEIGHT = 112 + + +assert(MAP_WIDTH > TILEMAP_WIDTH * 2) +assert(MAP_HEIGHT > TILEMAP_HEIGHT * 2) + + +constant _ = 0 +constant H = 1 | (0 << Tilemap.palette.shift) +constant W = 1 | (1 << Tilemap.palette.shift) +constant T = 1 | (2 << Tilemap.palette.shift) + +Data: + + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw 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_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw 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_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,W,_,_,_,W,W,W,_,_,_,_,_,_,_,_,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,_,_,_,_,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,W,W,W,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,_,_,_,_,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,_,_,_,_,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,W,W,W,W,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,W,_,_,_,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,W,W,W,W,W,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,T,T,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,T,T,T,T,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,W,W,W,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + +constant Data.size = pc() - Data + +assert(Data.size == MAP_WIDTH * MAP_HEIGHT * 2) +assert(Data.size % (MAP_HEIGHT * N_ROWS_TO_TRANSFER) == 0) + +} + diff --git a/roms/snes-test-roms/src/effects/vmain-vertical-scrolling.asm b/roms/snes-test-roms/src/effects/vmain-vertical-scrolling.asm new file mode 100644 index 00000000..435cfa5c --- /dev/null +++ b/roms/snes-test-roms/src/effects/vmain-vertical-scrolling.asm @@ -0,0 +1,574 @@ +// A vertically scrolling demo that displays a map that is more than 64 tiles tall. +// +// This demo is preformed on a background that is two tilemaps wide and one tilemap +// tall (64x32 tiles). +// +// Transferring a 64 tile tilemap row to a 64x32 or 64x64 tilemap in VRAM requires +// two separate DMA transfers since tilemap columns 31 and 32 are non-contiguous. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VMAIN VERTICAL SCROLLING" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// VRAM Map +constant VRAM_BG1_MAP_WADDR = 0x0000 // 64x32 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// The size of a single tilemap (BG1 is 2 tilemaps wide) +constant TILEMAP_WIDTH = 32 +constant TILEMAP_HEIGHT = 32 +constant TILEMAP_WORD_SIZE = TILEMAP_WIDTH * TILEMAP_HEIGHT + + + + +// If this value is zero, the next row will be transferred to VRAM on the next VBlank interrupt. +// (byte flag) +allocate(transferTilemapRowOnZero, lowram, 1) + +// The VRAM word address to transfer the map data. +// +// (VRAM word address) +allocate(tilemapRowVramWaddr, lowram, 2) + +// Long address of the tilemap row to transfer to VRAM. +// +// (long address into `Map.Data`) +allocate(tilemapRowFarAddr, lowram, 3) + + + +// Shadow variable of the BG1 Horizontal Offset register +// (uint16) +allocate(bg1_hofs, lowram, 2) + +// Shadow variable of the BG1 Vertical Offset register +// (uint16) +allocate(bg1_vofs, lowram, 2) + + + +// Camera Y position. +// +// (uint16) +allocate(cameraYpos, lowram, 2) + +// Used to determine if the next row is to be uploaded to VRAM +// (byte) +allocate(maskedCameraYpos, lowram, 1) + + + +// Initialize the tilemap row transfer subsystem. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = REGISTER, DP = 0 +a8() +i16() +code() +function InitTilemapRowTransfers { + lda.b #1 + sta.w transferTilemapRowOnZero + + + // Set `tilemapRowVramWaddr` to the last row in the tilemap. + // On the next call to `QueueRowTransfer`, `tilemapRowVramWaddr`will be incremented to the first row of the tilemap. + ldx.w #VRAM_BG1_MAP_WADDR + TILEMAP_WORD_SIZE * 2 + stx.w tilemapRowVramWaddr + + + // Also set `tilemapRowVramWaddr` to the end of the map + // (keep it in sync with `tilemapRowVramWaddr`) + ldx.w #Map.Data + Map.Data.size + stx.w tilemapRowFarAddr + + lda.b #Map.Data >> 16 + sta.b tilemapRowFarAddr + 2 + + + ldx.w #0 + stx.w cameraYpos + + rts +} + + + +// Queue a transfer of the next tilemap row to VRAM on the next VBlank. +// +// REQUIRES: 8 bit A, 16 bit Index, DB access low-RAM, DP = 0 +a8() +i16() +code() +function QueueRowTransfer { + rep #$30 +a16() + + // Increment `tilemapRowVramWaddr`, wrapping as required + lda.w tilemapRowVramWaddr + clc + adc.w #TILEMAP_WIDTH + cmp.w #VRAM_BG1_MAP_WADDR + TILEMAP_WIDTH * TILEMAP_HEIGHT + bcc + + lda.w #VRAM_BG1_MAP_WADDR + + + sta.w tilemapRowVramWaddr + + + // Advance pointer to the next row, wrapping as necessary + // (leave bank unchanged) + lda.w tilemapRowFarAddr + clc + adc.w #Map.MAP_WIDTH * 2 + cmp.w #Map.Data + Map.Data.size + bcc + + lda.w #Map.Data + + + sta.w tilemapRowFarAddr + + + sep #$20 +a8() + + // Transfer the tilemap row to VRAM on the next VBlank + stz.w transferTilemapRowOnZero + + rts +} + + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = registers, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + + // Transfer tilemap row to VRAM if `transferTilemapRowOnZero` is + // zero + lda.w transferTilemapRowOnZero + bne + + // As BG1 is two tilemaps (64 tiles) wide, the row must be split in two + // and uploaded to VRAM using two DMA transfers. + // + // The first will transfer 32 tilemap cells to `tilemapRowFarAddr` + // The second will transfer 32 tilemap cells to `tilemapRowFarAddr + TILEMAP_WORD_SIZE` + + // Set VMAIN to normal word access + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + + // Setup DMA, transfer from `tilemapRowVramWaddr` to VRAM + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w tilemapRowFarAddr + stx.w A1T0 + lda.w tilemapRowFarAddr + 2 + sta.w A1B0 + + + // Transfer the first half of the row to the first tilemap + // (located at VRAM Word address `tilemapRowVramWaddr`) + ldx.w #TILEMAP_WIDTH * 2 + stx.w DAS0 + + ldx.w tilemapRowVramWaddr + stx.w VMADD + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Transfer the second half of the row to the second tilemap + // (located at VRAM Word address `tilemapRowVramWaddr + TILEMAP_WORD_SIZE`) + // + // No need to set the DMA control, destination or address registers. They are already contain the correct values. + ldx.w #TILEMAP_WIDTH * 2 + stx.w DAS0 + + assert(TILEMAP_WORD_SIZE & 0xff == 0) + lda.w tilemapRowVramWaddr + sta.w VMADDL + + lda.w tilemapRowVramWaddr + 1 + clc + adc.b #TILEMAP_WORD_SIZE >> 8 + sta.w VMADDH + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // A is non-zero + sta.w transferTilemapRowOnZero + + + + + // Transfer bg1 offset shadow variables to PPU + lda.w bg1_hofs + sta.w BG1HOFS + lda.w bg1_hofs + 1 + sta.w BG1HOFS + + lda.w bg1_vofs + sta.w BG1VOFS + lda.w bg1_vofs + 1 + sta.w BG1VOFS +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Initialise the tilemap row transfers + jsr InitTilemapRowTransfers + + + // Offset BG1 so both the left and right tilemaps are onscreen + ldx.w #128 + stx.w bg1_hofs + + ldx.w #0 + stx.w cameraYpos + + + // Set PPU registers + + // Mode 0 + stz.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s64x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + + + // Transfer tiles and palette to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + EnableVblankInterrupts() + + jsr WaitFrame + + // Enable screen, full brightness (still in VBlank) + lda.b #15 + sta.w INIDISP + + + + // Slowly draw the first 29 rows + lda.b #29 + InitialDrawLoop: + pha + jsr QueueRowTransfer + + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + jsr WaitFrame + pla + dec + bne InitialDrawLoop + + + + // Scroll BG1 vertically, drawing new columns when needed. + MainLoop: + rep #$30 + a16() + lda.w cameraYpos + clc + adc.w #1 + sta.w cameraYpos + + // Must adjust the vertical offset by -1 to align the Background and Object layers. + dec + sta.w bg1_vofs + + sep #$20 + a8() + + and.b #~7 + cmp.w maskedCameraYpos + beq + + sta.w maskedCameraYpos + + jsr QueueRowTransfer + + + + jsr WaitFrame + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { +Tiles: +// Blank tile + fill 16, 0 + +// Tilled tile + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + +constant Tiles.size = pc() - Tiles + + +Palette: + dw ToPalette( 0, 0 , 0) + dw ToPalette(22, 6, 6) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + + dw ToPalette( 0, 0 , 0) + dw ToPalette(11, 13, 28) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + + dw ToPalette( 0, 0 , 0) + dw ToPalette(27, 21, 12) + dw ToPalette( 0, 0 , 0) + dw ToPalette( 0, 0 , 0) + +constant Palette.size = pc() - Palette +} + + + +// The map to display +// +// (Grid of TileMap words) +namespace Map { + +constant MAP_WIDTH = 70 +constant MAP_HEIGHT = 112 + + +assert(MAP_WIDTH > TILEMAP_WIDTH * 2) +assert(MAP_HEIGHT > TILEMAP_HEIGHT * 2) + + +constant _ = 0 +constant H = 1 | (0 << Tilemap.palette.shift) +constant W = 1 | (1 << Tilemap.palette.shift) +constant T = 1 | (2 << Tilemap.palette.shift) + +Data: + + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw 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_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,W,W,_,_,_,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,T,T,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,T,T,T,T,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,W,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,W,W,_,_,_,_,_,W,W,W,W,W,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,H,H,_,_,_,H,H,_,_,W,W,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + dw _,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,H,H,H,H,H,H,_,_,_,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,H,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_,_, + +constant Data.size = pc() - Data + +assert(Data.size == MAP_WIDTH * MAP_HEIGHT * 2) + +} + diff --git a/roms/snes-test-roms/src/effects/window-mask-logic.asm b/roms/snes-test-roms/src/effects/window-mask-logic.asm new file mode 100644 index 00000000..dcdf4b36 --- /dev/null +++ b/roms/snes-test-roms/src/effects/window-mask-logic.asm @@ -0,0 +1,524 @@ +// An interactive test rom to demonstrate all of the window mask logic settings. +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "WINDOW MASK LOGIC" +define VERSION = 0 + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 + +define ROM_SPEED = fast +define REGION = Japan + + +define VBLANK_READS_JOYPAD + + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80bfff) +createCodeBlock(rodata0, 0x80c000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + +// The selected logic and invert settings for the backdrop layer +// +// ----21ll +// 1 = invert window 1 +// 2 = invert window 2 +// ll = window mask logic +allocate(selectedMaskLogic, zeropage, 1) + constant selectedMaskLogic.LOGIC_MASK = 0b0011 + constant selectedMaskLogic.INVERT_WIN_1 = 0b0100 + constant selectedMaskLogic.INVERT_WIN_2 = 0b1000 + + +// Options +allocate(options, zeropage, 1) + constant options.SHOW_WIN1 = WSEL.win1.enable << WOBJSEL.color.shift + constant options.SHOW_WIN2 = WSEL.win2.enable << WOBJSEL.color.shift + constant options.SHOW_INSTRUCTIONS = 1 + + +// Register shadow variable for the WOBJSEL register +allocate(wobjselShadow, zeropage, 1) + +// Register shadow variable for the WOBJLOG register +allocate(wobjlogShadow, zeropage, 1) + + + +// Setup PPU +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers, DP = 0 +a8() +i16() +code() +function SetupPpu { + jsr ResetRegisters + + // Window settings + + // Disable windows for backgrounds and objects + stz.w TMW + stz.w TSW + + // Color math settings + + // Clip colors to black inside the color window + // Disable color math outside the color window + // Use fixed color for color math + lda.b #CGWSEL.clip.inside | CGWSEL.prevent.outside + sta.w CGWSEL + + // Color math addition + // Enable color math on backdrop + lda.b #CGADSUB.color.add | CGADSUB.enable.backdrop + sta.w CGADSUB + + // Set fixed color to violet + lda.b #COLDATA.plane.blue | 31 + sta.w COLDATA + lda.b #COLDATA.plane.green | 0 + sta.w COLDATA + lda.b #COLDATA.plane.red | 15 + sta.w COLDATA + + + // Setup and HDMA channels 6 & 7 to the 2 windows + + // HDMA channel 6 to WH0 & WH1 + ldx.w #DMAP.direction.toPpu | DMAP.transfer.two | (WH0 << 8) + stx.w DMAP6 // also sets BBAD6 + + ldx.w #HdmaTables.Window1 + lda.b #HdmaTables.Window1 >> 16 + stx.w A1T6 + sta.w A1B6 + + // HDMA channel 7 to WH2 & WH3 + ldx.w #DMAP.direction.toPpu | DMAP.transfer.two | (WH2 << 8) + stx.w DMAP7 // also sets BBAD7 + + ldx.w #HdmaTables.Window2 + lda.b #HdmaTables.Window2 >> 16 + stx.w A1T7 + sta.w A1B7 + + + // Setup text buffer + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jmp TextBuffer.InitAndTransferToVram +} + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Enable HDMA 6 & 7 + // (Must occur in VBlank to prevent glitches) + lda.b #HDMAEN.dma7 | HDMAEN.dma6 + sta.w HDMAEN + + + // Update window mask logic + lda.b wobjselShadow + sta.w WOBJSEL + + lda.b wobjlogShadow + sta.w WOBJLOG + + + TextBuffer.VBlank() + + + // Enable display, full brightness + lda.b #0x0f + sta.w INIDISP +} + +include "../vblank_interrupts.inc" + + + +a8() +i16() +code() +function Init { + stz.b selectedMaskLogic + + lda.b #0xff + sta.b options + +FallThrough: +} + + + +a8() +i16() +code() +function UpdateWindowLogicAndText { + assert(Init.FallThrough == pc()) + + lda.b options + and.b #(WSEL.win1.enable | WSEL.win2.enable) << WOBJSEL.color.shift + sta.b wobjselShadow + + lda.b selectedMaskLogic + bit.b #selectedMaskLogic.INVERT_WIN_1 + beq + + lda.b #WSEL.win1.outside << WOBJSEL.color.shift + tsb.b wobjselShadow + + + + lda.b selectedMaskLogic + bit.b #selectedMaskLogic.INVERT_WIN_2 + beq + + lda.b #WSEL.win2.outside << WOBJSEL.color.shift + tsb.b wobjselShadow + + + + lda.b selectedMaskLogic + and.b #selectedMaskLogic.LOGIC_MASK + assert(WOBJLOG.color.shift == 2) + asl + asl + sta.b wobjlogShadow + + + // Update text + + jsr TextBuffer.ClearCharBufferAndResetCursor + + TextBuffer.SetCursor(0, 1) + TextBuffer.PrintString(Strings.Header) + + + TextBuffer.SetCursor(0, 5) + + rep #$30 +a16() + lda.b selectedMaskLogic + and.w #selectedMaskLogic.LOGIC_MASK + asl + tax + lda.l Strings.LogicMaskStringTable,x + tax + + sep #$20 +a8() + lda.b #Strings.LogicMaskStringTable << 16 + jsr TextBuffer.PrintString + + + lda.b options + bit.b #options.SHOW_WIN1 + beq ++ + TextBuffer.SetCursor(0, 7) + lda.b selectedMaskLogic + bit.b #selectedMaskLogic.INVERT_WIN_1 + beq + + TextBuffer.PrintString(Strings.Invert) + + + TextBuffer.PrintString(Strings.Window1) + + + + + lda.b options + bit.b #options.SHOW_WIN2 + beq ++ + TextBuffer.SetCursor(0, 8) + lda.b selectedMaskLogic + bit.b #selectedMaskLogic.INVERT_WIN_2 + beq + + TextBuffer.PrintString(Strings.Invert) + + + TextBuffer.PrintString(Strings.Window2) + + + + lda.b options + bit.b #options.SHOW_INSTRUCTIONS + beq + + TextBuffer.SetCursor(0, 18) + TextBuffer.PrintString(Strings.Instructions) + + + + rts +} + + +a8() +i16() +code() +function Process { + lda.w joypadPressed + 1 + + bit.b #JOYH.right + beq + + inc.b selectedMaskLogic + jmp UpdateWindowLogicAndText + + + + bit.b #JOYH.left + beq + + dec.b selectedMaskLogic + jmp UpdateWindowLogicAndText + + + + bit.b #JOYH.select + beq + + lda.b #options.SHOW_INSTRUCTIONS + bra ToggleOptionFlag + + + + + lda.w joypadPressed + + bit.b #JOYL.l + beq + + lda.b #options.SHOW_WIN1 + bra ToggleOptionFlag + + + + bit.b #JOYL.r + beq + + lda.b #options.SHOW_WIN2 + bra ToggleOptionFlag + + + + rts + + +ToggleOptionFlag: + // A = option flag to flip + eor.b options + sta.b options + jmp UpdateWindowLogicAndText +} + + + + +a8() +i16() +code() +function Main { + jsr SetupPpu + + jsr Init + + EnableVblankInterrupts() + + + MainLoop: + jsr WaitFrame + jsr Process + bra MainLoop +} + + + +namespace HdmaTables { + +constant N_SEGMENTS = 5 +constant W1_HEIGHT = 35 +constant W1_PADDING = (224 - W1_HEIGHT * N_SEGMENTS) / (N_SEGMENTS + 1) + +constant W1_LEFT = 160 +constant W1_RIGHT = 210 +constant W2_WIDTH = W1_RIGHT - W1_LEFT + 1 + +constant W2_MARGIN = 5 +constant W2_HEIGHT = W1_HEIGHT - W2_MARGIN * 2 +constant W2_PADDING = W1_PADDING + W2_MARGIN * 2 + +constant W2_X_START = W1_LEFT - W2_HEIGHT / 2 - 4 +constant W2_X_END = W1_RIGHT + W2_HEIGHT / 2 + 4 + +Window1: + assert(W1_PADDING < 0x80) + assert(W1_HEIGHT < 0x80) + + variable _segment = 0 + while _segment < N_SEGMENTS { + db W1_PADDING, 0xff, 0 // disable window + db W1_HEIGHT, W1_LEFT, W1_RIGHT // rectangle window + + _segment = _segment + 1 + } + db 1, 0xff, 0 // disable window + db 0 // end HDMA table + + +// Window 2 - diamonds +// (Chose diamonds over circles as diamonds have a sharper intersection then circles) +Window2: + assert(W2_PADDING < 0x80) + assert(W2_HEIGHT < 0x80) + + db W2_PADDING - W2_MARGIN, 0xff, 0 // disable window + + variable _segment = 0 + while _segment < N_SEGMENTS { + variable _left = W2_X_START + (W2_X_END - W2_X_START) * _segment / (N_SEGMENTS - 1) + variable _right = _left + variable _j = 0 + // Diamond + db 0x80 | W2_HEIGHT // HDMA repeat mode + while _j < W2_HEIGHT { + db _left, _right // left/right window values + + if _j < W2_HEIGHT / 2 { + _left = _left - 1 + _right = _right + 1 + } else { + _left = _left + 1 + _right = _right - 1 + } + _j = _j + 1 + } + + db W2_PADDING, 0xff, 0 // disable window + + _segment = _segment + 1 + } + db 0 // end HDMA table + +} + + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(31, 31, 31) + dw ToPalette(0, 0, 0) +constant Palette.size = pc() - Palette +} + + +rodata(rodata0) +namespace Strings { + Header: + db "WINDOW MASK\nLOGIC", 0 + + + LogicMaskStringTable: + dw Mask0 + dw Mask1 + dw Mask2 + dw Mask3 + + Mask0: + assert(WOBJLOG.logic.or == 0) + db "OR", 0 + + Mask1: + assert(WOBJLOG.logic.and == 1) + db "AND", 0 + + Mask2: + assert(WOBJLOG.logic.xor == 2) + db "XOR", 0 + + Mask3: + assert(WOBJLOG.logic.xnor == 3) + db "XNOR", 0 + + + Invert: + db "INVERT ", 0 + + Window1: + db "WIN 1", 0 + + Window2: + db "WIN 2", 0 + + + Instructions: + db "RIGHT: Next" + db "\n", "LEFT: Previous" + db "\n", + db "\n", "Toggle:" + db "\n", " L: WIN 1" + db "\n", " R: WIN 2" + db "\n", "SEL: Instructions" + db 0 +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/window-precalculated-single.asm b/roms/snes-test-roms/src/effects/window-precalculated-single.asm new file mode 100644 index 00000000..72a8a154 --- /dev/null +++ b/roms/snes-test-roms/src/effects/window-precalculated-single.asm @@ -0,0 +1,902 @@ +// A precalculated non-symmetrical single-window HDMA demo. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "PRECALCULATED WINDOW" +define VERSION = 0 + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 + +define ROM_SPEED = fast +define REGION = Japan + + + +architecture wdc65816-strict + +include "../common.inc" + + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +constant DISPLAY_WIDTH = 256 +constant DISPLAY_HEIGHT = 224 + + +constant HDMA_ENTRY_MAX_SCANLINES = 127 + + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + + + + +// HDMA Double Buffering +// ===================== + +constant HDMA_BUFFER_SIZE = 2048 + +constant HDMA_CHANNEL = 7 + + +// Notifies the `HdmaBuffer_VBlank` macro that a new HDMA buffer is available. +// +// If non-zero, a HDMA from `currentHdmaBuffer` to `hdmaBufferTarget` will be activated +// on the next VBlank. +// +// (byte flag) +allocate(hdmaBufferVBlankFlag, lowram, 1) + + +// Address of current HDMA buffer. +// MUST point to `hdmaBuffer0` or `hdmaBuffer1` +// MUST only be modified by `HdmaBuffer_NextBuffer` +// (word address) +allocate(currentHdmaBuffer, lowram, 2) + + +// Shadow of `DMAP` and `BBAD` HDMA registers for the HDMA buffer +// (word) +allocate(hdmaBufferTarget, lowram, 2) + + +// HDMA double buffers +// (2x HDMA_BUFFER_SIZE byte array) +allocate(hdmaBuffer0, wram7e, HDMA_BUFFER_SIZE) +allocate(hdmaBuffer1, wram7e, HDMA_BUFFER_SIZE) + + + +// Initialize the HDMA double buffer to a given PPU register. +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0 +// DB access registers +macro HdmaBuffer_Init(evaluate dmap, evaluate bbad) { + assert8a() + assert16i() + + ldx.w #({dmap} & 0xff) | ({bbad} << 8) + stx.w hdmaBufferTarget + + ldx.w #hdmaBuffer0 + stx.w currentHdmaBuffer + + stz.w hdmaBufferVBlankFlag +} + + + +// Retrieve the next HDMA buffer. +// +// NOTE: This buffer MUST BE committed and the VBlank routine MUST be processed before the next +// `HdmaBuffer_NextBuffer` call. +// +// RETURN: x = currentHdmaBuffer = the new HDMA buffer +// +// DB access Low-RAM +au() +i16() +code() +function HdmaBuffer_NextBuffer { + // Do not transfer the new buffer until it has been committed + stz.w hdmaBufferVBlankFlag + + + ldx.w currentHdmaBuffer + cpx.w #hdmaBuffer0 + bne Else + ldx.w #hdmaBuffer1 + bra EndIf +Else: + ldx.w #hdmaBuffer0 +EndIf: + stx.w currentHdmaBuffer + + rts +} + + + +// Commit the current HDMA buffer. +// The HDMA registers will be updated on the next VBlank. +// +// REQUIRES: 8 bit A, 16 bit Index +// DB access Low-RAM +macro HdmaBuffer_Commmit() { + assert8a() + + lda.b #1 + sta.w hdmaBufferVBlankFlag +} + + + +// HDMA double buffer VBlank routine. +// Updates HDMA registers if `hdmaBufferVBlankFlag` is non-zero. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: in VBlank +// +// DB access registers +macro HdmaBuffer_VBlank() { + lda.w hdmaBufferVBlankFlag + beq EndIf{#} + ldx.w hdmaBufferTarget + stx.w DMAP0 + (HDMA_CHANNEL * 0x10) // Also sets BBAD + + ldx.w currentHdmaBuffer + stx.w A1T0 + (HDMA_CHANNEL * 0x10) + + lda.b #hdmaBuffer0 >> 16 + sta.w A1B7 + + lda.b #1 << HDMA_CHANNEL + sta.w HDMAEN + + stz.w hdmaBufferVBlankFlag +EndIf{#}: +} + + + +// TranslateSingleWindow +// ===================== + + +namespace TranslateSingleWindow { + + +// WINDOW TABLE DATA FORMAT: +// count u8 Number of scanlines +// (must not be 0) +// (must be <= 2 * HDMA_ENTRY_MAX_SCANLINES) +// (should be <= DISPLAY_HEIGHT) +// +// repeated `count` times: +// left u8 window left position +// right u8 window right position + +// Window Table data. +// Accessed with `long,x` addressing mode +constant _TableOffset = WINDOW_TABLE_DATA_BANK << 16 +constant _Table__count = _TableOffset +constant _Table__data = _TableOffset + 1 + + +constant MAX_HORIZONTAL_TRANSLATION = 0xff + + + +// Temporary word variables +constant _yOffset = zpTmp0 +constant _xOffset = zpTmp1 +constant _secondHdmaEntryScanlines = zpTmp2 +constant _remainingScanlines = zpTmp3 + + + +// Confirm these functions will not overflow the HDMA buffer +// (+8 for `YOffsetPositive`) +// (`1 + 2 * HDMA_ENTRY_MAX_SCANLINES` for a single HDMA repeat-mode entry) +// (+4 for `__EndHdmaTable`) +// (+16 to be extra safe) +assert(8 + 2 * (1 + 2 * HDMA_ENTRY_MAX_SCANLINES) + 4 + 16 < HDMA_BUFFER_SIZE) + + + + +// Retrieve the next HDMA buffer and process the Y-Axis offset. +// +// INPUT: X = ROM Table word address +// INPUT: _yOffset = Y offset (sint16) +// +// RETURN: Carry: set if window is vertically onscreen +// +// RETURN: WMADD = HDMA buffer position +// RETURN: X = table address after the above-screen offscreen scanlines (if any) +// RETURN: A = number of scanlines in the first HDMA entry +// RETURN: _secondHdmaEntryScanlines = number of scanlines in the second HDMA entry (if any) +// +// The caller MUST branch to `__EndHdmaTable` if this function returns false. +// +// NOTE: Uses `WMDATA` +// +// DP = 0 +// DB access registers +a8() +i16() +code() +function __GetNextBufferAndProcessYOffset { + + phx + + // Set `WMDATA` address to the next HDMA buffer + jsr HdmaBuffer_NextBuffer + assert(hdmaBuffer0 >> 16 == 0x7e) + stx.w WMADD + stz.w VMADD + 2 + + plx + + ldy.b _yOffset + beq YOffsetZero + bpl YOffsetPositive + // _yOffset is negative + + rep #$31 + a16() + // Decrement number of scanlines to draw. + // + // _remainingScanlines = (u8)Table_count + (s16)_yOffset + // (yOffset is negative, equivalent to `A = Table_count - abs(_yOffset)`) + lda.l _Table__count,x + and.w #0xff + // carry clear + adc.b _yOffset + sta.b _remainingScanlines + + // Test if the window is vertically offscreen + bmi ReturnFalse_A16 + beq ReturnFalse_A16 + + + // Increment table position. + // + // X = _tableAddr - 2 * _yOffset + txa + sec + sbc.b _yOffset + sec + sbc.b _yOffset + tax + + + sep #$20 + a8() + lda.b _remainingScanlines + bra EndIf + + + YOffsetPositive: + // yOffset is > 0 + + // Test if the window is vertically offscreen + cpy.w #DISPLAY_HEIGHT + bcs ReturnFalse_A8 + + // Disable the window for `Y` scanlines using one or two HDMA non-repeat-mode entries. + + assert(DISPLAY_HEIGHT < 2 * HDMA_ENTRY_MAX_SCANLINES) + assert(2 * HDMA_ENTRY_MAX_SCANLINES < 0xff) + tya + cmp.b #HDMA_ENTRY_MAX_SCANLINES + 1 + bcc + + // Y > HDMA_ENTRY_MAX_SCANLINES + + // write `Y - HDMA_ENTRY_MAX_SCANLINES` to buffer (number of scanlines, non-repeat mode) + // write `0xff` to buffer (left window position) + // write `0` to buffer (right window position) + sec + sbc.b #HDMA_ENTRY_MAX_SCANLINES + + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + lda.b #HDMA_ENTRY_MAX_SCANLINES + + + + // write `A` to buffer (number of scanlines, non-repeat mode) + // write `0xff` to buffer (left window position) + // write `0` to buffer (right window position) + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + + // Calculate the number of scanlines to draw + // + // A = DISPLAY_HEIGHT - Y + lda.b #DISPLAY_HEIGHT + sec + sbc.b _yOffset + + // Branch if all scanlines are on vertically screen + cmp.l _Table__count,x + bcs YOffsetZero + bra EndIf + + + YOffsetZero: + // _yOffset is zero or all scanlines are vertically onscreen + lda.l _Table__count,x + beq ReturnFalse_A8 + + EndIf: + + + + // A = number of scanlines to draw + // + // Calculate return A and _secondHdmaEntryScanlines values + + stz.b _secondHdmaEntryScanlines + + cmp.b #HDMA_ENTRY_MAX_SCANLINES + bcc + + // carry set + sbc.b #HDMA_ENTRY_MAX_SCANLINES + sta.b _secondHdmaEntryScanlines + + lda.b #HDMA_ENTRY_MAX_SCANLINES + + + + // return true + sec + rts + + + +au() +ReturnFalse_A16: + sep #$20 +a8() +ReturnFalse_A8: + clc + rts +} + + + +// Draw a precalculated HDMA window with a left x-offset. +// +// INPUT: X - address of window table data (in WINDOW_TABLE_DATA_BANK) +// INPUT: A - x-axis left offset (u8) +// INPUT: yOffset - y-axis offset (s16, zeropage temporary) +// +// NOTE: Uses `WMDATA` +// +// DP = 0 +// DB access registers +a8() +i16() +code() +function DrawWindowLeftOffset { +constant yOffset = _yOffset + + // Negate A. + // + // Using a negative A allows me to store `_xOffset` in the `Y` register. + // Only the lobyte of -A is required. The code below assumes hibyte is always 0xff. + eor.b #0xff + inc +InvertedA: + sta.b _xOffset + + jsr __GetNextBufferAndProcessYOffset + bcc __EndHdmaTable + + ldy.w _xOffset + + EntryLoop: + // A = number of scanlines in the HDMA entry + // X = pre-calculated HDMA table address + // Y = _xOffset (only the lobyte is used, hibyte is unknown) + + sta.b _remainingScanlines + + // repeat mode, `A` scanlines + ora.b #0x80 + sta.w WMDATA + + Loop: + // right = _xOffset + _Table__data[x+1] + // if right < 0: + // write 0xff to buffer + // write 0 to buffer + // else: + // left = _xOffset + _Table__data[x] + // if left < 0: + // left = 0 + // write `left` to buffer + // write `right` to buffer + tya + clc + adc.l _Table__data + 1,x // right + bcs WindowOnscreen + // Window is offscreen. + // Disable HDMA window (left = 0xff, right = 0) + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + bra EndIf + + + WindowOnscreen: + xba // store right position in the high byte of A + // slightly faster than using a zero-page variable + tya + clc + adc.l _Table__data + 0,x // left + bcs + + lda.b #0 + + + + sta.w WMDATA + xba + sta.w WMDATA + EndIf: + + inx + inx + + dec.b _remainingScanlines + bne Loop + + + // Check if a second HDMA entry is required + lda.b _secondHdmaEntryScanlines + beq __EndHdmaTable + + stz.b _secondHdmaEntryScanlines + bra EntryLoop + +Fallthrough: +} + + + +// Finish the HDMA window table and commit the HDMA buffer. +// +// INPUT: WMADD = HDMA buffer position +// +// NOTE: Uses `WMDATA` +// +// DB access registers +a8() +i16() +code() +function __EndHdmaTable { + assert(pc() == DrawWindowLeftOffset.Fallthrough) + + // Disable HDMA window for 1 scanline (left = 0xff, right = 0) + lda.b #1 + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + // End HDMA table byte + stz.w WMDATA + + HdmaBuffer_Commmit() + + rts +} + + + +// Draw a precalculated HDMA window with a right x-offset. +// +// INPUT: X - address of window table data (in WINDOW_TABLE_DATA_BANK) +// INPUT: A - x-axis left offset (u8) +// INPUT: yOffset - y-axis offset (s16, zeropage temporary) +// +// NOTE: Uses `WMDATA` +// +// DP = 0 +// DB access registers +a8() +i16() +code() +function DrawWindowRightOffset { +constant yOffset = _yOffset + + + sta.b _xOffset + + jsr __GetNextBufferAndProcessYOffset + bcc __EndHdmaTable + + ldy.w _xOffset + + EntryLoop: + // A = number of scanlines in the HDMA entry + // X = pre-calculated HDMA table address + // Y = _xOffset (only the lobyte is used, hibyte is unknown) + + sta.b _remainingScanlines + + // repeat mode, `A` scanlines + ora.b #0x80 + sta.w WMDATA + + Loop: + // left = _xOffset + _Table__data[x] + // if left > 255: + // write 0xff to buffer + // write 0 to buffer + // else: + // write `left` to buffer + // + // right = _xOffset + _Table__data[x+1] + // if right > 255: + // right = 255 + // write `right` to buffer + tya + clc + adc.l _Table__data + 0,x // left + bcc WindowOnscreen + // Window is offscreen. + // Disable HDMA window (left = 0xff, right = 0) + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + bra EndIf + + + WindowOnscreen: + sta.w WMDATA + + tya + clc + adc.l _Table__data + 1,x // right + bcc + + lda.b #0xff + + + sta.w WMDATA + EndIf: + + inx + inx + + dec.b _remainingScanlines + bne Loop + + + // Check if a second HDMA entry is required + lda.b _secondHdmaEntryScanlines + beq __EndHdmaTable + + stz.b _secondHdmaEntryScanlines + bra EntryLoop + + bra __EndHdmaTable +} + + + +// Draw a precalculated HDMA window at a given offset. +// +// The window will not be drawn is `xOffset < -MAX_HORIZONTAL_TRANSLATION` +// or `xOffset > MAX_HORIZONTAL_TRANSLATION`. +// +// INPUT: X - address of window table data (in WINDOW_TABLE_DATA_BANK) +// INPUT: xOffset - x-axis offset (s16, zeropage temporary) +// INPUT: yOffset - y-axis offset (s16, zeropage temporary) +// +// NOTE: Uses `WMDATA` +// +// DB access registers +a8() +i16() +code() +function DrawWindow { +constant xOffset = _xOffset +constant yOffset = _yOffset + + ldy.b _xOffset + bmi XOffsetNegative + // Y (_xOffset) is positive + cpy.w #MAX_HORIZONTAL_TRANSLATION + 1 + bcs WindowOffscreen + tya + bra DrawWindowRightOffset + + + XOffsetNegative: + // Y (_xOffset) is negative + cpy.w #-MAX_HORIZONTAL_TRANSLATION + bcc WindowOffscreen + tya + jmp DrawWindowLeftOffset.InvertedA + + +WindowOffscreen: + // Set `WMDATA` address to the next HDMA buffer + jsr HdmaBuffer_NextBuffer + assert(hdmaBuffer0 >> 16 == 0x7e) + stx.w WMADD + stz.w VMADD + 2 + + bra __EndHdmaTable +} + + +} + + + + +// Main +// ==== + +// Window position +// (2x sint16) +allocate(xPos, lowram, 2) +allocate(yPos, lowram, 2) + +// Window velocity +// (2x sint16) +allocate(xVelocity, lowram, 2) +allocate(yVelocity, lowram, 2) + + +constant _SHAPE_WIDTH = 49 +constant _SHAPE_HEIGHT = 140 +constant _PADDING = 2 + + +constant MIN_X_POS = -128 - _SHAPE_WIDTH +constant MAX_X_POS = +128 + _SHAPE_WIDTH +constant MIN_Y_POS = -_SHAPE_HEIGHT - _PADDING +constant MAX_Y_POS = DISPLAY_HEIGHT + _PADDING + +constant START_X_POS = 0 +constant START_Y_POS = 0 + +constant START_X_VELOCITY = 1 +constant START_Y_VELOCITY = 1 + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + HdmaBuffer_VBlank() +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sep #$20 + rep #$10 +a8() +i16() + + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + + // Set Backdrop colour to white + stz.w CGADD + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Window settings + + // Disable windows for backgrounds and objects + stz.w TMW + stz.w TSW + + // Enable window 1 for color math + lda.b #(WSEL.win1.enable) << WOBJSEL.color.shift + sta.w WOBJSEL + + // Set window mask logic for color math + lda.b #WOBJLOG.logic.or << WOBJLOG.color.shift + sta.w WOBJLOG + + // Clip colors to black outside the color window + // Disable color math everywhere + lda.b #CGWSEL.clip.outside | CGWSEL.prevent.always + sta.w CGWSEL + + // No color math + stz.w CGADSUB + + + // Setup HDMA double buffering (HDMA to WH0 & WH1) + HdmaBuffer_Init(DMAP.direction.toPpu | DMAP.transfer.two, WH0) + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + // Reset variables + ldx.w #START_X_POS + stx.w xPos + + ldy.w #START_Y_POS + sty.w yPos + + ldx.w #START_X_VELOCITY + stx.w xVelocity + + ldy.w #START_Y_VELOCITY + sty.w yVelocity + + + SpinLoop: + jsr WaitFrame + + + rep #$30 + a16() + + lda.w xPos + clc + adc.w xVelocity + tax + + bpl + + cpx.w #MIN_X_POS + 1 + bcs ++ + ldx.w #MIN_X_POS + bra InvertXVelocity + + + cpx.w #MAX_X_POS + bcc + + ldx.w #MAX_X_POS + InvertXVelocity: + lda.w #0 + sec + sbc.w xVelocity + sta.w xVelocity + + + stx.w xPos + + + lda.w yPos + clc + adc.w yVelocity + tay + + bpl + + cpy.w #MIN_Y_POS + 1 + bcs ++ + ldy.w #MIN_Y_POS + bra InvertYVelocity + + + cpy.w #MAX_Y_POS + bcc + + ldy.w #MAX_Y_POS + InvertYVelocity: + lda.w #0 + sec + sbc.w yVelocity + sta.w yVelocity + + + sty.w yPos + + sep #$20 + a8() + + + stx.b TranslateSingleWindow.DrawWindow.xOffset + sty.b TranslateSingleWindow.DrawWindow.yOffset + ldx.w #ExclamationMark + jsr TranslateSingleWindow.DrawWindow + + + bra SpinLoop +} + + + + +// Rom Data +// ======== + +constant WINDOW_TABLE_DATA_BANK = pc() >> 16 + + +ExclamationMark: + // first byte: number of scanlines + db 140 + + // remaining bytes: left and right value + db 0x85, 0x8c, 0x83, 0x8e, 0x81, 0x90, 0x80, 0x92, 0x7f, 0x93, 0x7e, 0x94, 0x7d, 0x94, 0x7c, 0x95 + db 0x7c, 0x95, 0x7b, 0x96, 0x7b, 0x96, 0x7b, 0x97, 0x7a, 0x97, 0x7a, 0x97, 0x7a, 0x97, 0x7a, 0x97 + db 0x7a, 0x97, 0x7a, 0x97, 0x7a, 0x97, 0x7a, 0x96, 0x7a, 0x96, 0x7a, 0x96, 0x7a, 0x95, 0x7a, 0x95 + db 0x7a, 0x95, 0x7a, 0x94, 0x7a, 0x94, 0x7a, 0x94, 0x7a, 0x93, 0x7a, 0x93, 0x7a, 0x93, 0x7a, 0x92 + db 0x7a, 0x92, 0x7a, 0x92, 0x7a, 0x91, 0x7a, 0x91, 0x7a, 0x91, 0x7a, 0x90, 0x7a, 0x90, 0x79, 0x90 + db 0x79, 0x8f, 0x79, 0x8f, 0x79, 0x8f, 0x79, 0x8e, 0x79, 0x8e, 0x79, 0x8e, 0x79, 0x8d, 0x79, 0x8d + db 0x79, 0x8d, 0x79, 0x8c, 0x79, 0x8c, 0x79, 0x8c, 0x79, 0x8b, 0x79, 0x8b, 0x79, 0x8b, 0x79, 0x8b + db 0x79, 0x8a, 0x79, 0x8a, 0x79, 0x8a, 0x79, 0x89, 0x79, 0x89, 0x79, 0x89, 0x79, 0x88, 0x79, 0x88 + db 0x79, 0x88, 0x79, 0x87, 0x79, 0x87, 0x79, 0x87, 0x79, 0x86, 0x79, 0x86, 0x79, 0x86, 0x79, 0x85 + db 0x79, 0x85, 0x78, 0x85, 0x78, 0x84, 0x78, 0x84, 0x78, 0x84, 0x78, 0x83, 0x78, 0x83, 0x78, 0x83 + db 0x78, 0x82, 0x78, 0x82, 0x78, 0x82, 0x78, 0x81, 0x78, 0x81, 0x78, 0x81, 0x78, 0x80, 0x78, 0x80 + db 0x78, 0x80, 0x78, 0x7f, 0x78, 0x7f, 0x78, 0x7f, 0x78, 0x7e, 0x79, 0x7e, 0xff, 0x00, 0xff, 0x00 + db 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00 + db 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0xff, 0x00, 0x72, 0x79, 0x6f, 0x7b + db 0x6e, 0x7d, 0x6c, 0x7e, 0x6b, 0x7f, 0x6a, 0x80, 0x6a, 0x81, 0x69, 0x82, 0x69, 0x82, 0x68, 0x83 + db 0x68, 0x83, 0x67, 0x83, 0x67, 0x83, 0x67, 0x84, 0x67, 0x84, 0x67, 0x84, 0x67, 0x84, 0x67, 0x84 + db 0x67, 0x83, 0x68, 0x83, 0x68, 0x83, 0x69, 0x82, 0x69, 0x82, 0x6a, 0x81, 0x6a, 0x80, 0x6b, 0x7f + db 0x6c, 0x7e, 0x6e, 0x7d, 0x70, 0x7b, 0x72, 0x79 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/window-precalculated-symmetrical.asm b/roms/snes-test-roms/src/effects/window-precalculated-symmetrical.asm new file mode 100644 index 00000000..e67ab174 --- /dev/null +++ b/roms/snes-test-roms/src/effects/window-precalculated-symmetrical.asm @@ -0,0 +1,806 @@ +// A precalculated horizontally-symmetrical single-window HDMA demo. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "SYMMETRICAL WINDOW" +define VERSION = 0 + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 + +define ROM_SPEED = fast +define REGION = Japan + + + +architecture wdc65816-strict + +include "../common.inc" + + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +constant DISPLAY_WIDTH = 256 +constant DISPLAY_HEIGHT = 224 + + +constant HDMA_ENTRY_MAX_SCANLINES = 127 + + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + + + + +// HDMA Double Buffering +// ===================== + +constant HDMA_BUFFER_SIZE = 2048 + +constant HDMA_CHANNEL = 7 + + +// Notifies the `HdmaBuffer_VBlank` macro that a new HDMA buffer is available. +// +// If non-zero, a HDMA from `currentHdmaBuffer` to `hdmaBufferTarget` will be activated +// on the next VBlank. +// +// (byte flag) +allocate(hdmaBufferVBlankFlag, lowram, 1) + + +// Address of current HDMA buffer. +// MUST point to `hdmaBuffer0` or `hdmaBuffer1` +// MUST only be modified by `HdmaBuffer_NextBuffer` +// (word address) +allocate(currentHdmaBuffer, lowram, 2) + + +// Shadow of `DMAP` and `BBAD` HDMA registers for the HDMA buffer +// (word) +allocate(hdmaBufferTarget, lowram, 2) + + +// HDMA double buffers +// (2x HDMA_BUFFER_SIZE byte array) +allocate(hdmaBuffer0, wram7e, HDMA_BUFFER_SIZE) +allocate(hdmaBuffer1, wram7e, HDMA_BUFFER_SIZE) + + + +// Initialize the HDMA double buffer to a given PPU register. +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0 +// DB access registers +macro HdmaBuffer_Init(evaluate dmap, evaluate bbad) { + assert8a() + assert16i() + + ldx.w #({dmap} & 0xff) | ({bbad} << 8) + stx.w hdmaBufferTarget + + ldx.w #hdmaBuffer0 + stx.w currentHdmaBuffer + + stz.w hdmaBufferVBlankFlag +} + + + +// Retrieve the next HDMA buffer. +// +// NOTE: This buffer MUST BE committed and the VBlank routine MUST be processed before the next +// `HdmaBuffer_NextBuffer` call. +// +// RETURN: x = currentHdmaBuffer = the new HDMA buffer +// +// DB access low-RAM +au() +i16() +code() +function HdmaBuffer_NextBuffer { + // Do not transfer the new buffer until it has been committed + stz.w hdmaBufferVBlankFlag + + + ldx.w currentHdmaBuffer + cpx.w #hdmaBuffer0 + bne Else + ldx.w #hdmaBuffer1 + bra EndIf +Else: + ldx.w #hdmaBuffer0 +EndIf: + stx.w currentHdmaBuffer + + rts +} + + + +// Commit the current HDMA buffer. +// The HDMA registers will be updated on the next VBlank. +// +// REQUIRES: 8 bit A, 16 bit Index +// DB access low-RAM +macro HdmaBuffer_Commmit() { + assert8a() + + lda.b #1 + sta.w hdmaBufferVBlankFlag +} + + + +// HDMA double buffer VBlank routine. +// Updates HDMA registers if `hdmaBufferVBlankFlag` is non-zero. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: in VBlank +// +// DB access registers +macro HdmaBuffer_VBlank() { + lda.w hdmaBufferVBlankFlag + beq EndIf{#} + ldx.w hdmaBufferTarget + stx.w DMAP0 + (HDMA_CHANNEL * 0x10) // Also sets BBAD + + ldx.w currentHdmaBuffer + stx.w A1T0 + (HDMA_CHANNEL * 0x10) + + lda.b #hdmaBuffer0 >> 16 + sta.w A1B7 + + lda.b #1 << HDMA_CHANNEL + sta.w HDMAEN + + stz.w hdmaBufferVBlankFlag +EndIf{#}: +} + + + +// DrawSymmetricalWindow +// ===================== + + +// Draw a horizontally symmetrical window to the HDMA buffer +// +// NOTE: This function does not support windowless scanlines inside the window table data. +// +// NOTE: Uses `WMDATA` +// +// INPUT: centreX - centre X position (s16, zeropage temporary) +// INPUT: topY - top Y position (s16, zeropage temporary) +// INPUT: X - address of window table data (in WINDOW_TABLE_DATA_BANK) +// +// +// WINDOW TABLE DATA FORMAT: +// count u8 Number of scanlines +// (must not be 0) +// (should be <= DISPLAY_HEIGHT) +// +// data u8[count] Window half-width for each scanline +// (window window is `2 * half_width + 1`) +// +// DP = 0 +// DB access registers +a8() +i16() +function DrawSymmetricalWindow { +constant centreX = zpTmp0 +constant topY = zpTmp1 + +// Number of scanlines to draw +// (u16, accessed with both 8 and 16 bit A) +constant _remainingScanlines = zpTmp2 // must be u16 + +// Number of scanlines in the second HDMA repeat-mode entry (if any) +// (u8) +constant _secondHdmaEntryScanlines = zpTmp3 + + +// Window Table data. +// Accessed with `long,x` addressing mode +constant _TableOffset = WINDOW_TABLE_DATA_BANK << 16 +constant _Table__count = _TableOffset +constant _Table__data = _TableOffset + 1 + + + // Confirm this function will not overflow the HDMA buffer + // (+8 for `TopYPositive`) + // (`1 + 2 * HDMA_ENTRY_MAX_SCANLINES` for a single HDMA repeat-mode entry) + // (+4 for `EndHdmaTable`) + // (+16 to be extra safe) + assert(8 + 2 * (1 + 2 * HDMA_ENTRY_MAX_SCANLINES) + 4 + 16 < HDMA_BUFFER_SIZE) + + + phx + + // Set `WMDATA` address to the next HDMA buffer + jsr HdmaBuffer_NextBuffer + assert(hdmaBuffer0 >> 16 == 0x7e) + stx.w WMADD + stz.w VMADD + 2 + + plx + + + ldy.b topY + beq DrawBuffer + bpl TopYPositive + // topY is negative + + rep #$31 + a16() + + // Decrement number of scanlines to draw. + // + // _remainingScanlines = (u8)Table_count + (s16)topY + // (topY is negative, equivalent to `A = Table_count - abs(topY)`) + lda.l _Table__count,x + and.w #0xff + // carry clear + adc.b topY + sta.b _remainingScanlines + + // Branch if the window is vertically offscreen + bmi JumpToEndHdmaTable + beq JumpToEndHdmaTable + + + // Increment table position. + // + // X = X - topY + // (topY is negative, equivalent to `X = X + abs(topY)`) + txa + sec + sbc.b topY + tax + + sep #$20 + a8() + lda.b _remainingScanlines + bra DrawBuffer__A + + + au() + JumpToEndHdmaTable: + sep #$20 + a8() + jmp EndHdmaTable + + + TopYPositive: + // topY is > 0 + + // Test if the window is vertically offscreen + cpy.w #DISPLAY_HEIGHT + bcs EndHdmaTable + + // Disable the window for `Y` scanlines using one or two HDMA non-repeat-mode entries. + + assert(DISPLAY_HEIGHT < 2 * HDMA_ENTRY_MAX_SCANLINES) + assert(2 * HDMA_ENTRY_MAX_SCANLINES < 0xff) + tya + cmp.b #HDMA_ENTRY_MAX_SCANLINES + 1 + bcc + + // Y > HDMA_ENTRY_MAX_SCANLINES + + // write `Y - HDMA_ENTRY_MAX_SCANLINES` to buffer (number of scanlines, non-repeat mode) + // write `0xff` to buffer (left window position) + // write `0` to buffer (right window position) + sec + sbc.b #HDMA_ENTRY_MAX_SCANLINES + + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + lda.b #HDMA_ENTRY_MAX_SCANLINES + + + + // write `A` to buffer (number of scanlines, non-repeat mode) + // write `0xff` to buffer (left window position) + // write `0` to buffer (right window position) + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + + // Calculate the number of scanlines to draw + + // A = DISPLAY_HEIGHT - Y + // + lda.b #DISPLAY_HEIGHT + sec + sbc.b topY + + cmp.l _Table__count,x + bcc DrawBuffer__A + + + +DrawBuffer: + lda.l _Table__count,x + beq EndHdmaTable + +DrawBuffer__A: + // X = table address + // A = number of scanlines to draw + stz.b _secondHdmaEntryScanlines + + cmp.b #HDMA_ENTRY_MAX_SCANLINES + bcc + + // carry set + sbc.b #HDMA_ENTRY_MAX_SCANLINES + sta.b _secondHdmaEntryScanlines + + lda.b #HDMA_ENTRY_MAX_SCANLINES + + + + ldy.b centreX + bmi CentreXIsOffscreenLeft + cpy.w #DISPLAY_WIDTH + bcs CentreXIsOffscreenRight + + + EntryLoop: + // A = number of scanlines in the HDMA entry + sta.b _remainingScanlines + + // repeat mode, `A` scanlines + ora.b #0x80 + sta.w WMDATA + + + // Y = centreX + // X = pre-calculated HDMA table address + Loop: + // left = centreX - _Table__data[x] + // if left < 0: + // left = 0 + // write `left` to buffer + tya + sec + sbc.l _Table__data,x + bcs + + lda.b #0 + + + sta.w WMDATA + + // right = centreX + _Table__data[x] + // if right > 255: + // right = 255 + // write `right` to buffer + tya + clc + adc.l _Table__data,x + bcc + + lda.b #0xff + + + sta.w WMDATA + + inx + + dec.b _remainingScanlines + bne Loop + + + // Check if a second HDMA entry is required + lda.b _secondHdmaEntryScanlines + beq EndLoop + + stz.b _secondHdmaEntryScanlines + bra EntryLoop + EndLoop: + + +a8() +EndHdmaTable: + // Disable HDMA window for 1 scanline (left = 0xff, right = 0) + lda.b #1 + sta.w WMDATA + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + // End HDMA table byte + stz.w WMDATA + + + HdmaBuffer_Commmit() + + + rts + + + +a8() +i16() +CentreXIsOffscreenLeft: +namespace CentreXIsOffscreenLeft { + // Y = centreX + // Y (centreX) is negative + // A = number of scanlines to draw in the first HDMA entry + // _secondHdmaEntryScanlines is set + + + // Test if the window will never be horizontally onscreen. + // If there is no early-exit, all the math can be calculated with an 8 bit Accumulator. + assert(DISPLAY_WIDTH <= 0x100) + cpy.w #-DISPLAY_WIDTH + bcc EndHdmaTable + + + EntryLoop: + // A = number of scanlines in the HDMA entry + sta.b _remainingScanlines + + // repeat mode, `A` scanlines + ora.b #0x80 + sta.w WMDATA + + + // Y = centreX + // X = pre-calculated HDMA table address + Loop: + // right = centreX + _Table__data[x] + // if right > 0: + // write `0` to buffer + // write `right` to buffer + // else: + // write `0xff` to buffer + // write `0` to buffer + + // Assumes high byte of Y is always 0xff + tya + clc + adc.l _Table__data,x + bcc + + stz.w WMDATA + sta.w WMDATA + bra ++ + + + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + + + inx + + dec.b _remainingScanlines + bne Loop + + + // Check if a second HDMA entry is required + lda.b _secondHdmaEntryScanlines + beq EndHdmaTable + + stz.b _secondHdmaEntryScanlines + bra EntryLoop +} + + + +CentreXIsOffscreenRight: +namespace CentreXIsOffscreenRight { + // Y = centreX + // Y (centreX) is positive and >= DISPLAY_WIDTH + // A = number of scanlines to draw in the first HDMA entry + // _secondHdmaEntryScanlines is set + + + // Test if the window will never be horizontally onscreen. + // If there is no early-exit, all the math can be calculated with an 8 bit Accumulator. + assert(DISPLAY_WIDTH == 0x100) + cpy.w #0x1ff + bcs EndHdmaTable + + + EntryLoop: + // A = number of scanlines in the HDMA entry + sta.b _remainingScanlines + + // repeat mode, `A` scanlines + ora.b #0x80 + sta.w WMDATA + + + // Y = centreX + // X = pre-calculated HDMA table address + Loop: + // left = centreX - _Table__data[x] + // if left < 0x100: + // write `left` to buffer + // write `255` to buffer + // else: + // write `255` to buffer + // write `0` to buffer + + // Assumes high byte of centreX is always 0x01 + tya + sec + sbc.l _Table__data,x + bcs + + sta.w WMDATA + + lda.b #0xff + sta.w WMDATA + bra ++ + + + lda.b #0xff + sta.w WMDATA + stz.w WMDATA + + + + inx + + dec.b _remainingScanlines + bne Loop + + + // Check if a second HDMA entry is required + lda.b _secondHdmaEntryScanlines + beq EndHdmaTable + + stz.b _secondHdmaEntryScanlines + bra EntryLoop +} + +} + + + + +// Main +// ==== + +// Window position +// (2x sint16) +allocate(xPos, lowram, 2) +allocate(yPos, lowram, 2) + +// Window velocity +// (2x sint16) +allocate(xVelocity, lowram, 2) +allocate(yVelocity, lowram, 2) + + +constant _SHAPE_HALF_WIDTH = 55 +constant _SHAPE_HEIGHT = 140 +constant _PADDING = 2 + + +constant MIN_X_POS = -_SHAPE_HALF_WIDTH - _PADDING +constant MAX_X_POS = DISPLAY_WIDTH + _SHAPE_HALF_WIDTH + _PADDING +constant MIN_Y_POS = -_SHAPE_HEIGHT - _PADDING +constant MAX_Y_POS = DISPLAY_HEIGHT + _PADDING + +constant START_X_POS = 0 +constant START_Y_POS = -_SHAPE_HEIGHT / 2 + +constant START_X_VELOCITY = 1 +constant START_Y_VELOCITY = 1 + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + HdmaBuffer_VBlank() +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sep #$20 + rep #$10 +a8() +i16() + + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + + // Set Backdrop colour to white + stz.w CGADD + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Window settings + + // Disable windows for backgrounds and objects + stz.w TMW + stz.w TSW + + // Enable window 1 for color math + lda.b #(WSEL.win1.enable) << WOBJSEL.color.shift + sta.w WOBJSEL + + // Set window mask logic for color math + lda.b #WOBJLOG.logic.or << WOBJLOG.color.shift + sta.w WOBJLOG + + // Clip colors to black outside the color window + // Disable color math everywhere + lda.b #CGWSEL.clip.outside | CGWSEL.prevent.always + sta.w CGWSEL + + // No color math + stz.w CGADSUB + + + // Setup HDMA double buffering (HDMA to WH0 & WH1) + HdmaBuffer_Init(DMAP.direction.toPpu | DMAP.transfer.two, WH0) + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + + // Reset variables + ldx.w #START_X_POS + stx.w xPos + + ldy.w #START_Y_POS + sty.w yPos + + ldx.w #START_X_VELOCITY + stx.w xVelocity + + ldy.w #START_Y_VELOCITY + sty.w yVelocity + + + SpinLoop: + jsr WaitFrame + + + rep #$30 + a16() + + lda.w xPos + clc + adc.w xVelocity + tax + + bpl + + cpx.w #MIN_X_POS + 1 + bcs ++ + ldx.w #MIN_X_POS + bra InvertXVelocity + + + cpx.w #MAX_X_POS + bcc + + ldx.w #MAX_X_POS + InvertXVelocity: + lda.w #0 + sec + sbc.w xVelocity + sta.w xVelocity + + + stx.w xPos + + + lda.w yPos + clc + adc.w yVelocity + tay + + bpl + + cpy.w #MIN_Y_POS + 1 + bcs ++ + ldy.w #MIN_Y_POS + bra InvertYVelocity + + + cpy.w #MAX_Y_POS + bcc + + ldy.w #MAX_Y_POS + InvertYVelocity: + lda.w #0 + sec + sbc.w yVelocity + sta.w yVelocity + + + sty.w yPos + + sep #$20 + a8() + + + stx.b DrawSymmetricalWindow.centreX + sty.b DrawSymmetricalWindow.topY + ldx.w #Pawn + jsr DrawSymmetricalWindow + + + bra SpinLoop +} + + + + +// Rom Data +// ======== + +constant WINDOW_TABLE_DATA_BANK = pc() >> 16 + + +Pawn: + // first byte: number of scanlines + db 140 + + // remaining bytes: scanline half-width + db 5, 8, 10, 11, 13, 14, 15, 16, 16, 17, 18, 18, 19, 19, 19, 20 + db 20, 20, 20, 20, 20, 20, 20, 19, 19, 19, 18, 18, 17, 16, 16, 15 + db 14, 13, 11, 10, 9, 9, 21, 25, 27, 28, 28, 27, 25, 21, 14, 14 + db 14, 14, 14, 14, 13, 13, 13, 13, 13, 13, 13, 12, 12, 12, 12, 12 + db 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 12, 13, 13, 13, 13, 13 + db 13, 13, 13, 14, 14, 14, 14, 14, 15, 15, 15, 15, 16, 16, 16, 16 + db 17, 17, 18, 18, 18, 19, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24 + db 25, 26, 27, 29, 31, 34, 37, 40, 43, 45, 47, 49, 50, 51, 52, 53 + db 53, 54, 54, 55, 55, 55, 55, 55, 55, 55, 55, 54 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/effects/window-shapes-single.asm b/roms/snes-test-roms/src/effects/window-shapes-single.asm new file mode 100644 index 00000000..dfb4315e --- /dev/null +++ b/roms/snes-test-roms/src/effects/window-shapes-single.asm @@ -0,0 +1,858 @@ +// A small sample of shapes that can be created from a single window, built +// using hard-coded HDMA tables. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define ROM_NAME = "SINGLE WINDOW SHAPES" +define VERSION = 0 + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 + +define ROM_SPEED = fast +define REGION = Japan + + +define VBLANK_READS_JOYPAD + + +architecture wdc65816-strict + +include "../common.inc" + + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant DISPLAY_WIDTH = 256 +constant DISPLAY_HEIGHT = 224 + + +// Number of display frames between HDMA tables +constant CHANGE_HDMA_TABLE_INTERVAL = 2 * 60 + + +// Frame countdown timer until the next HDMA table is displayed +// (uint16) +allocate(countdownToNextHdmaTable, lowram, 2) + + +// The HDMA table to display. +// (word index into `HdmaTablesTable`) +allocate(hdmaTableIndex, lowram, 2) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Setup and enable HDMA channel 7 + + // HDMA to WH0 & WH1 + ldx.w #DMAP.direction.toPpu | DMAP.transfer.two | (WH0 << 8) + stx.w DMAP7 // also sets BBAD7 + + ldx.w hdmaTableIndex + + ldy.w HdmaTablesTable,x + sty.w A1T7 + lda.b #HdmaTablesTable >> 16 + sta.w A1B7 + + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + + // Reset variables + ldx.w #0 + stx.w hdmaTableIndex + + ldx.w #CHANGE_HDMA_TABLE_INTERVAL - 1 + stx.w countdownToNextHdmaTable + + + // Set Backdrop colour to white + stz.w CGADD + lda.b #0xFF + sta.w CGDATA + sta.w CGDATA + + + // Window settings + + // Disable windows for backgrounds and objects + stz.w TMW + stz.w TSW + + // Enable window 1 for color math + lda.b #(WSEL.win1.enable) << WOBJSEL.color.shift + sta.w WOBJSEL + + // Set window mask logic for color math + lda.b #WOBJLOG.logic.or << WOBJLOG.color.shift + sta.w WOBJLOG + + + // Color math settings + + // Clip colors to black inside the color window + // Disable color math outside the color window + // Use fixed color for color math + lda.b #CGWSEL.clip.inside | CGWSEL.prevent.outside + sta.w CGWSEL + + // Color math addition + // Enable color math on backdrop + lda.b #CGADSUB.color.add | CGADSUB.enable.backdrop + sta.w CGADSUB + + // Set fixed color to violet + lda.b #COLDATA.plane.blue | 31 + sta.w COLDATA + lda.b #COLDATA.plane.green | 0 + sta.w COLDATA + lda.b #COLDATA.plane.red | 15 + sta.w COLDATA + + + EnableVblankInterrupts() + + lda.b #0x0f + sta.w INIDISP + + + TimerLoop: + ldy.w countdownToNextHdmaTable + dey + bpl ++ + // countdown timer is 0, display the next HDMA Table + ldx.w hdmaTableIndex + inx + inx + cpx.w #HdmaTablesTable.size + bcc + + ldx.w #0 + + + stx.w hdmaTableIndex + + ldy.w #CHANGE_HDMA_TABLE_INTERVAL - 1 + + + sty.w countdownToNextHdmaTable + + jsr WaitFrame + + ldx.w joypadPressed + beq TimerLoop + + + // A button has been pressed, switch to joypad controls + ButtonLoop: + lda.w joypadPressed + 1 + and.b #JOYH.left | JOYH.y + beq SkipPrevious + // Display the previous HDMA table + ldx.w hdmaTableIndex + dex + dex + bpl + + ldx.w #HdmaTablesTable.size - 2 + + + stx.w hdmaTableIndex + SkipPrevious: + + + lda.w joypadPressed + 1 + and.b #JOYH.right | JOYH.b + beq SkipNext + // Display the next HDMA table + ldx.w hdmaTableIndex + inx + inx + cpx.w #HdmaTablesTable.size + bcc + + ldx.w #0 + + + stx.w hdmaTableIndex + SkipNext: + + jsr WaitFrame + + bra ButtonLoop + +} + + + +// List of HDMA tables to registers WH0 and WH1 +HdmaTablesTable: + dw LeftGreaterThanRight + dw RectangularWindow + dw TallRectangularWindow + dw Trapezium_0 + dw Trapezium_1 + dw Trapezium_2 + dw TriangleR_0 + dw TriangleR_1 + dw TriangleR_2 + dw TriangleR_3 + dw TriangleR_4 + dw Octagon + dw MultipleShapes + dw Circle +constant HdmaTablesTable.size = pc() - HdmaTablesTable + + +// Assert `HdmaTablesTable` can be accessed with DB = PB (in VBlank macro) +assert(HdmaTablesTable >> 16 == pc() >> 16) + + + + +// Demonstrates that there is no window if `left > right`. +LeftGreaterThanRight: +namespace LeftGreaterThanRight { + variable scanline = 0 + + // repeat mode, 127 scanlines + db 0x80 | 127 + while scanline < 127 { + // Subtracting 254 so there is a scanline where WH0 == WH1 + db scanline, 254 - scanline + scanline = scanline + 1 + } + + // repeat mode, 97 scanlines + db 0x80 | (DISPLAY_HEIGHT - 127) + while scanline < DISPLAY_HEIGHT { + db scanline, 254 - scanline + scanline = scanline + 1 + } + + // End of HDMA table + db 0 +} + + + + +// Rectangular window +RectangularWindow: +namespace RectangularWindow { + constant HEIGHT = 100 + constant WIDTH = 100 + constant X = (DISPLAY_WIDTH - WIDTH) / 2 + constant Y = (DISPLAY_HEIGHT - HEIGHT) / 2 + + assert(X + WIDTH <= 0xff) + + // Disable window for the first `Y` scanlines + // (if Y >= 0x80, two HDMA entries are required) + assert(Y < 0x80) + db Y + // Disable window (WH0 > WH1) + db 0xff, 0 + + // Enable window for `HEIGHT` scanlines + // (if HEIGHT >= 0x80, two HDMA entries are required) + assert(HEIGHT < 0x80) + db HEIGHT + db X, X + WIDTH + + // Disable window for 1 scanline + db 1 + // Disable window (WH0 > WH1) + db 0xff, 0 + + // End HDMA Table + db 0 +} + + + + +// Tall Rectangular window (> 127 scanlines tall) +TallRectangularWindow: +namespace TallRectangularWindow { + constant HEIGHT = 200 + constant WIDTH = 80 + constant X = (DISPLAY_WIDTH - WIDTH) / 2 + constant Y = (DISPLAY_HEIGHT - HEIGHT) / 2 + + assert(X + WIDTH <= 0xff) + + // Disable window for the first `Y` scanlines + // (if Y >= 0x80, two HDMA entries are required) + assert(Y < 0x80) + db Y + // Disable window (WH0 > WH1) + db 0xff, 0 + + + // Enable window for `HEIGHT` scanlines + // + // Since `HEIGHT > 0x7f`, two HDMA entries are required. + assert(HEIGHT > 0x7f) + assert(HEIGHT < 0x7f * 2) + + // 127 scanlines + db 0x7f + // Enable window (X to `X + WIDTH`) + db X, X + WIDTH + + // `HEIGHT - 127` scanlines + db HEIGHT - 127 + // Enable window (X to `X + WIDTH`) + db X, X + WIDTH + + + // Disable window for 1 scanline + db 1 + // Disable window (WH0 > WH1) + db 0xff, 0 + + // End HDMA Table + db 0 +} + + + + +// Used for converting 8.8 fixed point to integers (and vice versa) +constant FIXED_POINT_SCALE = 0x100 + + +// A macro to generate a HDMA table for an acute triangle with an axis-aligned base. +// +// There are many different ways of drawing a triangle, this macro uses a fixed-point delta to +// calculate the left and right position for each scanline. +// +// ASSUMES: top_x/top_y are inside the screen +// +// PARAM: left: the starting left window position (integer) +// PARAM: right: the starting right window position (integer) +// PARAM: top_y: the Y-position of the top of the triangle (integer) +// PARAM: height: the height of the triangle (integer) +// PARAM: dx_left: the delta-X of left side of the triangle (8.8 fixed point integer) +// PARAM: dx_right: the delta-X of the right side of the triangle (8.8 fixed point integer) +macro Trapezium_HdmaTable(variable left, variable right, evaluate top_y, evaluate height, evaluate dx_left, evaluate dx_right) { + assert(left <= right) + assert({height} > 0) + assert({top_y} + {height} <= DISPLAY_HEIGHT) + + // Disable window for the first `top_y` scanlines + if {top_y} > 127 { + // HDMA entry must be split in two if `top_y` > 127 + db 127 + db 0xff, 0 + db {top_y} - 127 + db 0xff, 0 + } else if {top_y} > 0 { + db {top_y} + db 0xff, 0 + } + + left = left * FIXED_POINT_SCALE + FIXED_POINT_SCALE / 2 + right = right * FIXED_POINT_SCALE + FIXED_POINT_SCALE / 2 + + // Start a HDMA entry in repeat mode + if {height} > 127 { + db 0x80 | 127 + } else { + db 0x80 | {height} + } + + variable i = 0 + while i < {height} { + if i == 127 { + // After 127 scanlines the first HDMA table is completed. + // Start a new HDMA entry for the remaining scanlines. + db 0x80 | ({height} - 127) + } + + db left / FIXED_POINT_SCALE, right / FIXED_POINT_SCALE + + left = left - {dx_left} + if left < 0 { + left = 0 + } + + right = right + {dx_right} + if right >= DISPLAY_WIDTH * FIXED_POINT_SCALE { + right = (DISPLAY_WIDTH * FIXED_POINT_SCALE) - 1 + } + + i = i + 1 + } + + // Disable window for 1 scanline + db 1 + db 0xff, 0 + + // End HDMA table + db 0 +} + + +// A Trapezium can be used to draw an acute triangle with an horizontal base +Trapezium_0: + Trapezium_HdmaTable(127, 128, 20, 184, 0x005c, 0x005c) + + +Trapezium_1: + Trapezium_HdmaTable(54, 64, 130, 94, 0x00d8, 0x0070) + +Trapezium_2: + Trapezium_HdmaTable(100, 200, 20, 80, 0x00e0, 0x00e0) + + + + +// Generate a HDMA repeat mode block for two angled window positions. +// +// NOTE: This inline macro will only create a single HDMA table entry. +// Height MUST be <= 127. +// +// NOTE: This inline macro will modify the `left` and `right` variables. +// +// PARAM: height: The number of scanlines to draw (integer <= 127) +// PARAM: dx_left/dx_right: The delta-x for each scanline (.8 signed fixed point) +inline __DrawAngledLines(evaluate height, evaluate dx_left, evaluate dx_right) { + if {height} > 0 { + // Start a HDMA entry in repeat mode + assert({height} <= 127) + db 0x80 | {height} + + variable i = 0 + while i < {height} { + left = left + {dx_left} + right = right + {dx_right} + + if right < 0 || left >= DISPLAY_WIDTH * FIXED_POINT_SCALE { + // Window is off-screen + db 255, 0 + } else { + // Window is on-screen, clamp window positions to an 8 bit value + variable l = left / FIXED_POINT_SCALE + if l < 0 { + l = 0 + } + + variable r = right / FIXED_POINT_SCALE + if r >= 255 { + r = 255 + } + + db l, r + } + + i = i + 1 + } + } +} + + +// A macro to generate a HDMA table for a triangle pointing to the right. +// +// There are many different ways of drawing a triangle, this macro uses a fixed-point delta to +// calculate the left and right position for each scanline. +// +// ASSUMES: y-positions are inside the screen +// +macro TrianglePointingRight_HdmaTable(evaluate top_x, evaluate top_y, evaluate center_x, evaluate center_y, evaluate bottom_x, evaluate bottom_y) { + evaluate h1 = {center_y} - {top_y} + evaluate h2 = {bottom_y} - {center_y} + + assert({top_y} >= 0 && {top_y} <= 127 * 2) + assert({h1} >= 0 && {h1} <= 127 * 2) + assert({h2} >= 0 && {h2} <= 127 * 2) + assert({bottom_y} < DISPLAY_HEIGHT) + assert({center_x} >= {top_x}) + assert({center_x} >= {bottom_x}) + + evaluate dx_left = (({bottom_x} - {top_x}) * FIXED_POINT_SCALE) / ({h1} + {h2}) + evaluate dx_right1 = (({center_x} - {top_x}) * FIXED_POINT_SCALE) / {h1} + evaluate dx_right2 = (({bottom_x} - {center_x}) * FIXED_POINT_SCALE) / {h2} + + + // Disable window for the first `top_y` scanlines + if {top_y} > 127 { + // HDMA entry must be split in two if `top_y` > 127 + db 127 + db 0xff, 0 + db {top_y} - 127 + db 0xff, 0 + } else if {top_y} > 0 { + db {top_y} + db 0xff, 0 + } + + + variable left = {top_x} * FIXED_POINT_SCALE + variable right = left + + if {h1} > 127 { + __DrawAngledLines(127, {dx_left}, {dx_right1}) + __DrawAngledLines({h1} - 127, {dx_left}, {dx_right1}) + } else { + __DrawAngledLines({h1}, {dx_left}, {dx_right1}) + } + + if {h2} > 127 { + __DrawAngledLines(127, {dx_left}, {dx_right2}) + __DrawAngledLines({h2} - 127, {dx_left}, {dx_right2}) + } else { + __DrawAngledLines({h2}, {dx_left}, {dx_right2}) + } + + + // Disable window for 1 scanline + db 1 + db 0xff, 0 + + // End HDMA table + db 0 +} + +TriangleR_0: + TrianglePointingRight_HdmaTable(20, 20, 236, 112, 20, 204) + +TriangleR_1: + assert(200 - 10 > 0x80) + TrianglePointingRight_HdmaTable(10, 10, 246, 200, 128, 214) + + +// Aspect corrected equilateral triangle +TriangleR_2: + TrianglePointingRight_HdmaTable(79, 55, 197, 92, 110, 189) + + +// Triangle with the top horizontally off-screen +TriangleR_3: + TrianglePointingRight_HdmaTable(-80, 20, 150, 150, 80, 200) + + +// Triangle with the top horizontally off-screen +TriangleR_4: + TrianglePointingRight_HdmaTable(120, 20, 320, 100, 300, 200) + + + + +Octagon: +namespace Octagon { + constant SIDE_LENTH = 70 + constant DIAGONAL_AXIS = 49 // sqrt(70**2 / 2) + constant Y_OFFSET = (DISPLAY_HEIGHT - DIAGONAL_AXIS * 2 - SIDE_LENTH) / 2 + + constant TOP_LEFT = (DISPLAY_WIDTH - SIDE_LENTH) / 2 + constant TOP_RIGHT = TOP_LEFT + SIDE_LENTH - 1 + + constant MIDDLE_LEFT = TOP_LEFT - DIAGONAL_AXIS + constant MIDDLE_RIGHT = MIDDLE_LEFT + DIAGONAL_AXIS * 2 + SIDE_LENTH - 1 + + + // Disable window for `Y_OFFSET` scanlines + assert(Y_OFFSET < 0x80) + db Y_OFFSET + // Disable window (WH0 > WH1) + db 0xff, 0 + + + // Draw angled lines. + // + // Repeat mode, `DIAGONAL_AXIS` scanlines + assert(DIAGONAL_AXIS < 0x80) + db 0x80 | DIAGONAL_AXIS + variable i = 0 + while i < DIAGONAL_AXIS { + db TOP_LEFT - i, TOP_RIGHT + i + i = i + 1 + } + + + // Fixed window for `SIDE_LENTH` scanlines + assert(SIDE_LENTH < 0x80) + db SIDE_LENTH + db MIDDLE_LEFT, MIDDLE_RIGHT + + + // Draw angled lines. + // + // Repeat mode, `DIAGONAL_AXIS` scanlines + assert(DIAGONAL_AXIS < 0x80) + db 0x80 | DIAGONAL_AXIS + variable i = 0 + while i < DIAGONAL_AXIS { + db MIDDLE_LEFT + i + 1, MIDDLE_RIGHT - i - 1 + i = i + 1 + } + + + // Disable window for 1 scanline + db 1 + // Disable window (WH0 > WH1) + db 0xff, 0 + + // End HDMA Table + db 0 +} + + + + +// A single window can display multiple shapes, so long as they do not overlap +MultipleShapes: +namespace MultipleShapes { + // Shape 1 - rectangle + db 22 + db 100, 156 + + // 10 scanlines with no window + db 10 + db 0xff, 0 + + // Shape 2 - diamond + // (HDMA repeat mode) + db 0x80 | (30 * 2 - 1) + variable i = 0 + while i < 30 { + db 60 - i, 60 + i + i = i + 1 + } + i = i - 1 + while i > 0 { + i = i - 1 + db 60 - i, 60 + i + } + + + // 10 scanlines with no window + db 10 + db 0xff, 0 + + + // Shape 3 - another rectangle + db 22 + db 100, 156 + + + // 10 scanlines with no window + db 10 + db 0xff, 0 + + + // Shape 4 - diamond + // (HDMA repeat mode) + db 0x80 | (30 * 2 - 1) + variable i = 0 + while i < 30 { + db 196 - i, 196 + i + i = i + 1 + } + i = i - 1 + while i > 0 { + i = i - 1 + db 196 - i, 196 + i + } + + + // 10 scanlines with no window + db 10 + db 0xff, 0 + + + // Shape 4 - one final rectangle + db 22 + db 100, 156 + + + // Disable window for 1 scanline + db 1 + db 0xff, 0 + + // End HDMA table + db 0 +} + + + + +// A HDMA circular window +Circle: + // Disable window for 62 scanlines + db 62 + db 0xff, 0 + + // repeat mode, 50 scanlines + db 0x80 | 50 + // Calculated using python + // + // y = r - i - 1 + // offset = math.sqrt(r ** 2 - y ** 2) * x_scale + // left = round(cx - offset) + // right = round(cx + offset) + + db 119, 137 + db 116, 140 + db 113, 143 + db 111, 145 + db 109, 147 + db 107, 149 + db 106, 150 + db 104, 152 + db 103, 153 + db 102, 154 + db 101, 155 + db 100, 156 + db 99, 157 + db 98, 158 + db 97, 159 + db 96, 160 + db 95, 161 + db 94, 162 + db 94, 162 + db 93, 163 + db 92, 164 + db 92, 164 + db 91, 165 + db 91, 165 + db 90, 166 + db 90, 166 + db 89, 167 + db 89, 167 + db 88, 168 + db 88, 168 + db 88, 168 + db 87, 169 + db 87, 169 + db 87, 169 + db 86, 170 + db 86, 170 + db 86, 170 + db 86, 170 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + + // repeat mode, 50 scanlines + db 0x80 | 50 + // The following is the reverse of the previous block + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + db 84, 172 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 85, 171 + db 86, 170 + db 86, 170 + db 86, 170 + db 86, 170 + db 87, 169 + db 87, 169 + db 87, 169 + db 88, 168 + db 88, 168 + db 88, 168 + db 89, 167 + db 89, 167 + db 90, 166 + db 90, 166 + db 91, 165 + db 91, 165 + db 92, 164 + db 92, 164 + db 93, 163 + db 94, 162 + db 94, 162 + db 95, 161 + db 96, 160 + db 97, 159 + db 98, 158 + db 99, 157 + db 100, 156 + db 101, 155 + db 102, 154 + db 103, 153 + db 104, 152 + db 106, 150 + db 107, 149 + db 109, 147 + db 111, 145 + db 113, 143 + db 116, 140 + db 119, 137 + + // Disable window for 1 scanline + db 1 + db 0xff, 0 + + // End HDMA table + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/examples/hdma-160scanline-hdma-entry.asm b/roms/snes-test-roms/src/examples/hdma-160scanline-hdma-entry.asm new file mode 100644 index 00000000..9a27f4f6 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-160scanline-hdma-entry.asm @@ -0,0 +1,210 @@ +// Test ROM showing how to implement a non-repeat HDMA entry that is 160 scanlines tall. +// +// This test ROM was used to generate a screenshot for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "160SL HDMA ENTRY" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Setup the HDMA registers. +// +// Uses DMA channel 7. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // HDMA table address + ldx.w #HdmaTable + stx.w A1T7 + lda.b #HdmaTable >> 16 + sta.w A1B7 + + rts +} + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +// HDMA Table for the `BG1HOFS` register (one register, write twice transfer pattern). +HdmaTable: + // 160 scanlines with BG1HOFS = 0 + // Too many scanlines to fit in a single HDMA entry. + db 127 // 127 scanlines, non-repeat entry + dw 0 + + db 33 // 33 scanlines, non-repeat entry (+127 = 160 scanlines total) + dw 0 // Same data value as the previous entry + + + // Change BG1HOFS every 16 scanlines + db 16 // 16 scanlines, non-repeat entry + dw -2 + + db 16 // 16 scanlines, non-repeat entry + dw -4 + + db 16 // 16 scanlines, non-repeat entry + dw -6 + + db 16 // 16 scanlines + dw -8 + + db 0 // End HDMA table + + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.tilemap" +} + diff --git a/roms/snes-test-roms/src/examples/hdma-double-buffered-indirect-shear.asm b/roms/snes-test-roms/src/examples/hdma-double-buffered-indirect-shear.asm new file mode 100644 index 00000000..2bcbd5c5 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-double-buffered-indirect-shear.asm @@ -0,0 +1,421 @@ +// Test ROM showing how to implement a indirect double buffered HDMA effect. +// +// This test ROM was used to generate an animated image for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA SHEAR ANIMATION" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) + + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Number of frames to execute before resetting the demo +// (time in frames) +constant RESET_DELAY = 60 * 8 + + + +constant HDMA_BYTES_PER_TRANSFER = 2 +constant N_HDMA_SCANLINES = 224 + + +// Flag to determine which of the two scanline arrays is used by the MainLoop. +// +// (byte flag) +allocate(activeScanlineArray, lowram, 1) + + +// A contiguous array of word values for each scanline. +// +// These variables can be used for any 2 byte HDMA transfer pattern. +// +// (2x u16[H_HDMA_SCANLINES] buffers) +allocate(scanlineArray_A, wram7e, HDMA_BYTES_PER_TRANSFER * N_HDMA_SCANLINES) +allocate(scanlineArray_B, wram7e, HDMA_BYTES_PER_TRANSFER * N_HDMA_SCANLINES) + + +// (uint16) +allocate(animationTimer, wram7e, 2) + + + +// Setup the HDMA registers. +// +// Uses HDMA channel 7. +// +// NOTE: `ProcessShearAnimation` MUST be called before the next `WaitFrame` call. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +// DB = REGISTERS +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.addressing.indirect | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // Set HDMA table bank + // (assumes HdmaTable_A and HdmaTable_B are in the same bank) + lda.b #HdmaTable_A >> 16 + sta.w A1B7 + + // HDMA indirect bank + assert(scanlineArray_A >> 16 == scanlineArray_B >> 16) + lda.b #scanlineArray_A >> 16 + sta.w DASB7 + + rts +} + + + +// VBlank routine. +// +// Uses HDMA channel 7. +// +// MUST NOT be executed in a lag-frame +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Set HDMA table address (depending on which scanline-array was last used by the MainLoop) + lda.w activeScanlineArray + beq + + ldx.w #HdmaTable_A + bra ++ + + + ldx.w #HdmaTable_B + + + stx.w A1T7 + + + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Retrieve the next scanline array. +// +// MUST ONLY be called 0 or 1 times between `WaitFrame` calls. +// +// RETURN: X = Scanline Array address +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x7e, DP = 0 +a8() +i16() +code() +// DB = 0x7e +function GetNextScanlineArray { + lda.w activeScanlineArray + beq + + ldx.w #scanlineArray_B + lda.b #0 + bra ++ + + + ldx.w #scanlineArray_A + lda.b #1 + + + sta.w activeScanlineArray + + rts +} + + + +// Setup the shear animation. +// +// NOTE: This function does setup the PPU or HDMA. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x7e, DP = 0 +a8() +i16() +code() +// DB = 0x7e +function SetupShearAnimation { + ldx.w #0 + stx.w animationTimer + + bra ProcessShearAnimation +} + + + +// Process a single frame of the shear animation +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x7e, DP = 0 +a8() +i16() +code() +// DB = 0x7e +function ProcessShearAnimation { +// sint16 +constant _tmp = zpTmp0 + + // NOTE: tmp is signed + + // scanlineArray = GetNextScanlineArray() + // + // animationTimer = animationTimer + 2 + // if animationTimer > 512 + N_HDMA_SCANLINES: + // animationTimer = 512 + N_HDMA_SCANLINES + // + // tmp = animationTimer + // + // for i = 0 to N_HDMA_SCANLINES-1: + // tmp = tmp - 2 + // scanlineArray[i] = clamp(tmp, 0, 256) + // + + + jsr GetNextScanlineArray + // X = address of scanline array + + rep #$30 +a16() +i16() + + lda.w animationTimer + inc + inc + cmp.w #512 + N_HDMA_SCANLINES + bcc + + lda.w #512 + N_HDMA_SCANLINES + + + sta.w animationTimer + + sta.b _tmp + + + ldy.w #N_HDMA_SCANLINES + Loop: + // X = scanline array pointer + // Y = number of scanlines left + + lda.b _tmp + dec + dec + sta.b _tmp + + bpl + + lda.w #0 + bra ++ + + + cmp.w #256 + bcc + + lda.w #256 + + + + sta.w 0,x + inx + inx + + dey + bne Loop + + + sep #$20 +a8() + rts +} + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s64x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + + lda.b #0x7e + pha + plb +// DB = 0x7e + + + jsr SetupShearAnimation + + + // Enable screen (on the next VBlank) + // Long addressing is required, DB cannot access INIDISP register + jsr WaitFrame + lda.b #0x0f + sta.l INIDISP + + + MainLoop: + jsr WaitFrame + + // Reset the demo after RESET_DELAY frames + // Must be done immediately after WaitFrame to prevent screen tearing. + ldx.w frameCounter + cpx.w #RESET_DELAY + bcc + + jmp ResetHandler + + + + jsr ProcessShearAnimation + + jmp MainLoop +} + + + +// Indirect HDMA table to the data in `scanlineArray_A` +// NOTE: This table can only be used on 2-byte HDMA transfer patterns +HdmaTable_A: + db 0x80 | 112 // 112 scanlines, repeat entry + // Word address pointing to the first half of `scanlineArray_A` + dw scanlineArray_A + + db 0x80 | 112 // 112 scanlines, repeat entry + // Word address pointing to the second half of `scanlineArray_A` + dw scanlineArray_A + 112 * 2 + + db 0 // End HDMA table + + + +// Indirect HDMA table to the data in `scanlineArray_B` +// NOTE: This table can only be used on 2-byte HDMA transfer patterns +HdmaTable_B: + db 0x80 | 112 // 112 scanlines, repeat entry + // Word address pointing to the first half of `scanlineArray_B` + dw scanlineArray_B + + db 0x80 | 112 // 112 scanlines, repeat entry + // Word address pointing to the second half of `scanlineArray_B` + dw scanlineArray_B + 112 * 2 + + db 0 // End HDMA table + + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/shear-titlescreen-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/shear-titlescreen-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/shear-titlescreen-2bpp.tilemap" +} + + diff --git a/roms/snes-test-roms/src/examples/hdma-double-buffered-parallax.asm b/roms/snes-test-roms/src/examples/hdma-double-buffered-parallax.asm new file mode 100644 index 00000000..9424fdd0 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-double-buffered-parallax.asm @@ -0,0 +1,372 @@ +// Test ROM showing how to implement a double buffered parallax HDMA effect. +// +// This test ROM was used to generate a GIF for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA PARALLAX EXAMPLE" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +constant HDMA_BUFFER_SIZE = 512 + +// Flag to determine which of the two HDMA buffers is active. +// +// Used by MainLoop Used by the HDMA controller +// Zero = hdmaBuffer_A hdmaBuffer_B +// Non-Zero = hdmaBuffer_B hdmaBuffer_A +// +// (byte flag) +allocate(activeHdmaBuffer, lowram, 1) + +// 2 HDMA buffers +// (2x u8[HDMA_BUFFER_SIZE] buffers) +allocate(hdmaBuffer_A, wram7e, HDMA_BUFFER_SIZE) +allocate(hdmaBuffer_B, wram7e, HDMA_BUFFER_SIZE) + + +// Camera x position +// (16.16 fixed point) +allocate(camera_xpos, wram7e, 4) + +// Camera subpixel x position +constant camera_xpos.sx = camera_xpos + +// Camera pixel x position +constant camera_xpos.px = camera_xpos + 2 + + +// Camera's x-axis speed (in subpixels/frame). +// +// This specific speed was chosen so the effect repeats every 10 seconds. +// +// (16.16 fixed point) +constant CAMERA_XPOS_SPEED = 0x000369d0 + + + +// Setup the HDMA registers. +// +// Uses HDMA channel 7. +// +// NOTE: `BuildHdmaTable` MUST be called before the next `WaitFrame` call. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +// DB = REGISTERS +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // Set HDMA table bank + assert(hdmaBuffer_A >> 16 == hdmaBuffer_B >> 16) + lda.b #hdmaBuffer_A >> 16 + sta.w A1B7 + + rts +} + + + +// VBlank routine. +// +// Uses HDMA channel 7. +// +// MUST NOT be executed in a lag-frame +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Set HDMA table address (depending on which buffer was last used by the MainLoop) + lda.w activeHdmaBuffer + beq + + ldx.w #hdmaBuffer_A + bra ++ + + + ldx.w #hdmaBuffer_B + + + stx.w A1T7 + + + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Retrieve the next HDMA buffer. +// +// MUST ONLY be called 0 or 1 times between `WaitFrame` calls. +// +// RETURN: X = HDMA buffer address +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x7e, DP = 0 +a8() +i16() +code() +// DB = 0x7e +function GetNextHdmaBuffer { + lda.w activeHdmaBuffer + beq + + ldx.w #hdmaBuffer_B + lda.b #0 + bra ++ + + + ldx.w #hdmaBuffer_A + lda.b #1 + + + sta.w activeHdmaBuffer + + rts +} + + + +// Build the HDMA table +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x7e, DP = 0 +a8() +i16() +code() +// DB = 0x7e +function BuildHdmaTable { + + // Confirm the HDMA table can fit inside a HDMA buffer + assert(HDMA_BUFFER_SIZE >= 12 + 1) + + + // hdmaTable = GetNextHdmaBuffer() + // hdmaTable[ 0] as u8 = 45 + // hdmaTable[ 1] as u16 = camera_xpos_px >> 3 + // hdmaTable[ 3] as u8 = 22 + // hdmaTable[ 4] as u16 = camera_xpos_px >> 2 + // hdmaTable[ 6] as u8 = 128 + // hdmaTable[ 7] as u16 = camera_xpos_px + // hdmaTable[ 9] as u8 = 128 + // hdmaTable[10] as u16 = int(camera_xpos << 1) + // hdmaTable[12] as u8 = 0 + + + jsr GetNextHdmaBuffer + // X = address of HDMA buffer + + + // Set line counters + // NOTE: All values MUST BE <= 128 + lda.b #45 + sta.w 0,x + + lda.b #22 + sta.w 3,x + + lda.b #128 + sta.w 6,x + + lda.b #1 + sta.w 9,x + + stz.w 12,x + + + // Calculate BG1HOFS values + rep #$30 +a16() + lda.w camera_xpos.px + sta.w 7,x + lsr + lsr + sta.w 4,x + lsr + sta.w 1,x + + + // Read the MSB of camera subpixel word + lda.w camera_xpos.sx + asl + lda.w camera_xpos.px + rol + sta.w 10,x + + + sep #$20 +a8() + rts +} + + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + + lda.b #0x7e + pha + plb +// DB = 0x7e + + + // Build the HDMA table before the first VBlank call + jsr BuildHdmaTable + + + // Enable screen (on the next VBlank) + // Long addressing is required, DB cannot access INIDISP register + jsr WaitFrame + lda.b #0x0f + sta.l INIDISP + + + MainLoop: + jsr WaitFrame + + // Increment the camera's x position + rep #$31 + a16() + // carry clear + lda.w camera_xpos + adc.w #CAMERA_XPOS_SPEED + sta.w camera_xpos + + lda.w camera_xpos + 2 + adc.w #CAMERA_XPOS_SPEED >> 16 + sta.w camera_xpos + 2 + + sep #$20 + a8() + + jsr BuildHdmaTable + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/two-vertical-bars-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/two-vertical-bars-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/two-vertical-bars-2bpp.tilemap" +} + + diff --git a/roms/snes-test-roms/src/examples/hdma-indirect-mapping.asm b/roms/snes-test-roms/src/examples/hdma-indirect-mapping.asm new file mode 100644 index 00000000..fe7ca202 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-indirect-mapping.asm @@ -0,0 +1,214 @@ +// Test ROM showing how to use HDMA indirect mode to map a contiguous array to a HDMA table. +// +// This test ROM was used to generate a screenshot for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA INDIRECT MAPPING" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Setup the HDMA registers. +// +// Uses DMA channel 7. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.addressing.indirect | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // HDMA table address + ldx.w #IndirectHdmaTable + stx.w A1T7 + lda.b #IndirectHdmaTable >> 16 + sta.w A1B7 + + // HDMA indirect bank + lda.b #ContiguousArray >> 16 + sta.w DASB7 + + rts +} + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +// Contiguous array of `BG1HOFS` values for all 244 scanlines +ContiguousArray: + dw 367, 366, 365, 364, 363, 362, 361, 360, 359, 358, 357, 356, 355, 354, 353, 352, 351, 350, 349, 348, 347, 346, 345, 344, 343, 342, 341, 340, 339, 338, 337, 336, 335, 334, 333, 332, 331, 330, 329, 328, 327, 326, 325, 324, 323, 322, 321, 320, 319, 318, 317, 316, 315, 314, 313, 312, 311, 310, 309, 308, 307, 306, 305, 304, 303, 302, 301, 300, 299, 298, 297, 296, 295, 294, 293, 292, 291, 290, 289, 288, 287, 286, 285, 284, 283, 282, 281, 280, 279, 278, 277, 276, 275, 274, 273, 272, 271, 270, 269, 268, 267, 266, 265, 264, 263, 262, 261, 260, 259, 258, 257, 256, 255, 254, 253, 252, 251, 250, 249, 248, 247, 246, 245, 244, 243, 242, 241, 240, 239, 238, 237, 236, 235, 234, 233, 232, 231, 230, 229, 228, 227, 226, 225, 224, 223, 222, 221, 220, 219, 218, 217, 216, 215, 214, 213, 212, 211, 210, 209, 208, 207, 206, 205, 204, 203, 202, 201, 200, 199, 198, 197, 196, 195, 194, 193, 192, 191, 190, 189, 188, 187, 186, 185, 184, 183, 182, 181, 180, 179, 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, 168, 167, 166, 165, 164, 163, 162, 161, 160, 159, 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, 148, 147, 146, 145, 144 + +constant ContiguousArray.size = pc() - ContiguousArray + +assert(ContiguousArray.size == 224 * 2) + + + +// Indirect HDMA Table for the `BG1HOFS` register (one register, write twice transfer pattern). +IndirectHdmaTable: + // Cannot fit all 224 scanlines in a single HDMA entry. + // Splitting the table into two equally sized entries. + db 0x80 | 112 // 112 scanlines, repeat entry + // Word address pointing to the first half of ContiguousArray + dw ContiguousArray + + db 0x80 | 112 // 112 scanlines, repeat entry (+112 = 224 scanlines total) + // Word address pointing to the second half of ContiguousArray + dw ContiguousArray + 112 * 2 + + db 0 // End HDMA table + + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.tilemap" +} + + + + diff --git a/roms/snes-test-roms/src/examples/hdma-indirect-repeating-pattern.asm b/roms/snes-test-roms/src/examples/hdma-indirect-repeating-pattern.asm new file mode 100644 index 00000000..cb1c10f0 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-indirect-repeating-pattern.asm @@ -0,0 +1,223 @@ +// Test ROM showing how to use HDMA indirect mode to repeat a scanline pattern multiple times. +// +// This test ROM was used to generate a screenshot for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA REPEATING DATA" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Setup the HDMA registers. +// +// Uses DMA channel 7. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.addressing.indirect | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // HDMA table address + ldx.w #IndirectHdmaTable + stx.w A1T7 + lda.b #IndirectHdmaTable >> 16 + sta.w A1B7 + + // HDMA indirect bank + lda.b #SineTable >> 16 + sta.w DASB7 + + rts +} + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +// Array of `BG1HOFS` values for every scanline +SineTable: + // Sine wave, calculated using python: + // >>> import math + // >>> [ round(16.5 * math.sin(math.radians(i * 360 / 48))) for i in range(48) ] + dw 0, 2, 4, 6, 8, 10, 12, 13, 14, 15, 16, 16, 16, 16, 16, 15, 14, 13, 12, 10, 8, 6, 4, 2, 0, -2, -4, -6, -8, -10, -12, -13, -14, -15, -16, -16, -16, -16, -16, -15, -14, -13, -12, -10, -8, -6, -4, -2 + +constant SineTable.size = pc() - SineTable + +assert(SineTable.size == 48 * 2) + + + +// Indirect HDMA Table for the `BG1HOFS` register (one register, write twice transfer pattern). +IndirectHdmaTable: + db 0x80 | 48 // 48 scanlines, repeat + // Word address to BG1HOFS data + dw SineTable + + db 0x80 | 48 // 48 scanlines, repeat + dw SineTable + + db 0x80 | 48 // 48 scanlines, repeat + dw SineTable + + db 0x80 | 48 // 48 scanlines, repeat + dw SineTable + + db 0x80 | 48 // 48 scanlines, repeat + dw SineTable + + db 0 // End HDMA table + // Not required. HDMA ends at the Vertical Blanking Period. + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.tilemap" +} + + + + diff --git a/roms/snes-test-roms/src/examples/hdma-repeat-entry.asm b/roms/snes-test-roms/src/examples/hdma-repeat-entry.asm new file mode 100644 index 00000000..7a8ae0d5 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-repeat-entry.asm @@ -0,0 +1,203 @@ +// Test ROM showing how to implement a repeat HDMA entry. +// +// This test ROM was used to generate a screenshot for the SNESdev wiki. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA REPEAT ENTRY" +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// Setup the HDMA registers. +// +// Uses DMA channel 7. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: HDMA disabled +a8() +i16() +code() +function SetupHdma { + // HDMA to `BG1HOFS` + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP7 + + lda.b #BG1HOFS + sta.w BBAD7 + + // HDMA table address + ldx.w #HdmaTable + stx.w A1T7 + lda.b #HdmaTable >> 16 + sta.w A1B7 + + rts +} + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + // Enable HDMA. + // HDMA should be enabled during VBlank. + // There is no need to write to `HDMAEN` on every VBlank, it can be written to on a single VBlank. + lda.b #HDMAEN.dma7 + sta.w HDMAEN +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg1_Palette) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + lda.b #TM.bg1 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + jsr SetupHdma + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +// HDMA Table for the `BG1HOFS` register (one register, write twice transfer pattern). +HdmaTable: + db 0x80 | 127 // 127 scanlines, repeat entry (maximum number of repeat scanlines per entry) + // 127 words (254 bytes) of BG1HOFS data for the next 127 scanlines + dw 144, 145, 146, 147, 148, 149, 150, 151, 152, 153, 154, 155, 156, 157, 158, 159, 160, 161, 162, 163, 164, 165, 166, 167, 168, 169, 170, 171, 172, 173, 174, 175, 176, 177, 178, 179, 180, 181, 182, 183, 184, 185, 186, 187, 188, 189, 190, 191, 192, 193, 194, 195, 196, 197, 198, 199, 200, 201, 202, 203, 204, 205, 206, 207, 208, 209, 210, 211, 212, 213, 214, 215, 216, 217, 218, 219, 220, 221, 222, 223, 224, 225, 226, 227, 228, 229, 230, 231, 232, 233, 234, 235, 236, 237, 238, 239, 240, 241, 242, 243, 244, 245, 246, 247, 248, 249, 250, 251, 252, 253, 254, 255, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270 + + db 0x80 | 97 // 97 scanlines, repeat entry (+127 = 224 scanlines total) + // 97 words (194 bytes) of BG1HOFS data for the next 97 scanlines + dw 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, 295, 296, 297, 298, 299, 300, 301, 302, 303, 304, 305, 306, 307, 308, 309, 310, 311, 312, 313, 314, 315, 316, 317, 318, 319, 320, 321, 322, 323, 324, 325, 326, 327, 328, 329, 330, 331, 332, 333, 334, 335, 336, 337, 338, 339, 340, 341, 342, 343, 344, 345, 346, 347, 348, 349, 350, 351, 352, 353, 354, 355, 356, 357, 358, 359, 360, 361, 362, 363, 364, 365, 366, 367 + + db 0 // End HDMA table + +constant HdmaTable.size = pc() - HdmaTable + +assert(HdmaTable.size == 224 * 2 + 3) + + + +// Resources +// ========= + +namespace Resources { + insert Bg1_Palette, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.palette" + insert Bg1_Tiles, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.2bpp" + insert Bg1_Tilemap, "../../gen/hdma-hoffset-examples/vertical-bar-2bpp.tilemap" +} + + + + diff --git a/roms/snes-test-roms/src/examples/hdma-to-cgram.asm b/roms/snes-test-roms/src/examples/hdma-to-cgram.asm new file mode 100644 index 00000000..22fb9449 --- /dev/null +++ b/roms/snes-test-roms/src/examples/hdma-to-cgram.asm @@ -0,0 +1,310 @@ +// HDMA to CGRAM example. +// +// This example shows two different techniques for creating a single colour gradient using HDMA. +// +// This example will alternate between the two HDMA techniques to prove they both output the exact +// same gradient. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA TO CGRAM" +define VERSION = 0 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG3_MAP_WADDR = 0x0000 +constant VRAM_BG3_TILES_WADDR = 0x1000 + + +rodata(code) + + +// A HDMA gradient for a single colour that uses two HDMA channels. +// +// The first HDMA channel will set the CGADD colour index. +// The second HDMA channel will write the CGDATA colour data. +// +// Both HDMA tables MUST have the same line-count bytes for all HDMA entries. +// +// (See `VBlank.TwoHdmaChannels` for HDMA register settings) +namespace Gradient_TwoHdmaChannels { + constant COLOR_TO_CHANGE = 1 + + + // HDMA Table to CGDATA (byte register pattern) + CGADD_HdmaTable: + db 32 // 32 scanlines, non-repeat entry + db COLOR_TO_CHANGE + + variable i = 0 + while i < 28 { + db 2 // 6 scanlines, non-repeat entry + db COLOR_TO_CHANGE + i = i + 1 + } + + db 0 // end of HDMA table + + + // HDMA Table to CGDATA (write twice pattern) + // + // This HDMA table MUST be processed after `CGADD_HdmaTable`. + // + // The HDMA entries MUST have the same line-count as `CGADD_HdmaTable`. + // + CGDATA_HdmaTable: + db 32 // 32 scanlines, non-repeat entry + dw 0 + + variable i = 0 + while i < 28 { + db 2 // 2 scanlines, non-repeat entry + dw (28 - i) << 10 + i = i + 1 + } + + db 0 // end of HDMA table +} + + + +// A HDMA gradient using a single HDMA channel to CGADD & CGDATA using a two-registers write-twice HDMA pattern. +// +// This HDMA will write to CGADD twice. +// The CGADD first write is ignored and the second CGADD write contains the colour index to change. +// +// (See `VBlank.OneHdmaChannel` for HDMA register settings) +namespace Gradient_OneHdmaChannel { + constant COLOR_TO_CHANGE = 1 + + + // HDMA Table to CGADD & CGDATA (two registers, write twice pattern) + HdmaTable: + db 32 // 32 scanlines, non-repeat entry + db 0, COLOR_TO_CHANGE // two writes to CGADD + dw 0 // CGDATA data (color value) + + variable i = 0 + while i < 28 { + db 2 // 2 scanlines, non-repeat entry + db 0, COLOR_TO_CHANGE // two writes to CGADD + dw (28 - i) << 10 // CGDATA data (color value) + i = i + 1 + } + + db 0 // end of HDMA table +} + + + +// VBlank routine. +// +// DMA: Uses HDMA channels 6 & 7 +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + // Alternate between `Gradient_TwoHdmaChannels` and `Gradient_OneHdmaChannel` every frame. + lda.w frameCounter + and.b #1 + beq OneHdmaChannel + + TwoHdmaChannels: + // Setup HDMA for Gradient_TwoHdmaChannels + + // Setup HDMA Channel 6 + // HDMA to `CGADD` (byte register pattern) + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP6 + + // HDMA target + lda.b #CGADD + sta.w BBAD6 + + // HDMA table address + ldx.w #Gradient_TwoHdmaChannels.CGADD_HdmaTable + lda.b #Gradient_TwoHdmaChannels.CGADD_HdmaTable >> 16 + stx.w A1T6 + sta.w A1B6 + + + // Setup HDMA Channel 7 + // HDMA to `CGDATA` (write twice pattern) + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP7 + + // HDMA target + lda.b #CGDATA + sta.w BBAD7 + + // HDMA table address + ldx.w #Gradient_TwoHdmaChannels.CGDATA_HdmaTable + lda.b #Gradient_TwoHdmaChannels.CGDATA_HdmaTable >> 16 + stx.w A1T7 + sta.w A1B7 + + // Enable HDMA + lda.b #HDMAEN.dma6 | HDMAEN.dma7 + sta.w HDMAEN + + bra EndIf + + + OneHdmaChannel: + // Setup HDMA for Gradient_OneHdmaChannel + + // HDMA to `CGADD` & `CGDATA` (two registers, write twice pattern) + lda.b #DMAP.direction.toPpu | DMAP.transfer.twoWriteTwice + sta.w DMAP7 + + // HDMA target + lda.b #CGADD + sta.w BBAD7 + + // HDMA table address + ldx.w #Gradient_OneHdmaChannel.HdmaTable + lda.b #Gradient_OneHdmaChannel.HdmaTable >> 16 + stx.w A1T7 + sta.w A1B7 + + // Enable HDMA + lda.b #HDMAEN.dma7 + sta.w HDMAEN + + EndIf: +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +// REQUIRES: In force-blank +a8() +i16() +code() +function SetupPpu { + lda.b #BGMODE.mode1 + sta.w BGMODE + + lda.b #(VRAM_BG3_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG3SC + + lda.b #(VRAM_BG3_TILES_WADDR / BG34NBA.walign) << BG34NBA.bg3.shift + sta.w BG34NBA + + + ldx.w #VRAM_BG3_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg3_Tiles) + + ldx.w #VRAM_BG3_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg3_Tilemap) + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Bg3_Palette) + + + + lda.b #TM.bg3 + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + + jmp MainLoop +} + + + +// Resources +// ========= + +namespace Resources { + insert Bg3_Tiles, "../../gen/hdma-textbox-wipe/bg3.2bpp" + insert Bg3_Tilemap, "../../gen/hdma-textbox-wipe/bg3.tilemap" + + // Only write 3 colours to the ROM + // The 4th colour is red and is used for invalid tiles that + // would be hidden in the textbox-wipe-animation demo. + insert Bg3_Palette, "../../gen/hdma-textbox-wipe/bg3.palette", 0, 6 +} + + diff --git a/roms/snes-test-roms/src/examples/textbuffer-hello-world.asm b/roms/snes-test-roms/src/examples/textbuffer-hello-world.asm new file mode 100644 index 00000000..eddd26ec --- /dev/null +++ b/roms/snes-test-roms/src/examples/textbuffer-hello-world.asm @@ -0,0 +1,152 @@ +// TextBuffer Hello World example +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HELLO WORLD" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rodata0, 0x818000, 0x81ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + TextBuffer.VBlank() +} + +include "../vblank_interrupts.inc" + + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + + MainLoop: + ldx.w #(TextBuffer.N_TEXT_COLUMNS - 5 - 12) / 2 + ldy.w #TextBuffer.N_TEXT_ROWS / 4 + jsr TextBuffer.SetCursor + + ldy.w frameCounter + jsr TextBuffer.PrintHexSpace_16Y + TextBuffer.PrintStringLiteral("Hello World!") + + jsr WaitFrame + + jmp MainLoop +} + + +namespace Resources { + +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + + + diff --git a/roms/snes-test-roms/src/examples/vram-writes-without-dma.asm b/roms/snes-test-roms/src/examples/vram-writes-without-dma.asm new file mode 100644 index 00000000..2c5b0b79 --- /dev/null +++ b/roms/snes-test-roms/src/examples/vram-writes-without-dma.asm @@ -0,0 +1,378 @@ +// A simple write data to VRAM without using DMA example. +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VRAM WRITES NO DMA" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rodata0, 0x818000, 0x81ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() +} + +include "../vblank_interrupts.inc" + + +// Write a block of colors to CGRAM. +// +// REQUIRES: Vertical-Blank or Force-Blank. +// (There is not enough Horizontal-Blank time to run this code) +a8() +i16() +// DB access registers +function WriteCgramData { + + // Reset CGRAM word address (color index) + stz.w CGADD + + ldx.w #0 + Loop: + // Write low byte + lda.l PaletteData,x + sta.w CGDATA + inx + + // Write high byte + lda.l PaletteData,x + sta.w CGDATA + inx + + cpx.w #PaletteData.size + bne Loop + rts +} + + + +// Writes the word data at `TileData` to VRAM word address `VRAM_BG1_TILES_WADDR`. +// +// REQUIRES: Force-Blank +// (There might not be enough Vertical-Blank time if `TileData` is too large) +a8() +i16() +// DB access registers +function WriteVramTileData { + // Set VMAIN to word access + lda.b #0x80 + sta.w VMAIN + + // Set VRAM word address + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + // Use a 16 bit accumulator + rep #$30 +a16() + + ldx.w #0 + Loop: + // Read one word of TileData and write it to VRAM + lda.l TileData,x + sta.w VMDATA + + inx + inx + cpx.w #TileData.size + bcc Loop + + sep #$20 +a8() + + rts +} + + + +// Build a BG1 tilemap and write it to VRAM +// +// REQUIRES: Force-Blank +// (There is not be enough Vertical-Blank time to run this code) +a8() +i16() +// DB access registers +function BuildTilemap { + +constant N_TILES = TileData.size / 16 + + // VRAM word access + lda.b #0x80 + sta.w VMAIN + + // Set VRAM word address + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + + // Use a 16 bit accumulator and 8 bit Index + rep #$20 + sep #$10 +a16() +i8() + + ldy.b #0 + OuterLoop: + ldx.b #0 + + InnerLoop: + // if y == 5 && x >= 5 && x < 5 + N_TILES: + // a = x - 5 + // else: + // a = 0 + // + cpy.b #5 + bne + + // 16 bits transferred, high byte of A is always 0 + txa + sec + sbc.w #5 + cmp.w #N_TILES + bcc ++ + + + lda.w #0 + + + + // Write 16-bit A to VRAM + sta.w VMDATA + + inx + cpx.b #32 + bcc InnerLoop + iny + cpy.b #32 + bcc OuterLoop + + + // Restore 8 bit A, 16 bit Index + rep #$10 + sep #$20 +a8() +i16() + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + jsr WriteCgramData + + jsr WriteVramTileData + + jsr BuildTilemap + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +PaletteData: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant PaletteData.size = pc() - PaletteData + + +// 2bpp tile data +TileData: + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01111110, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01111110, %00000000 + db %01000000, %00000000 + db %01111000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01111110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01111110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01111110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %00111100, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %10000010, %00000000 + db %10010010, %00000000 + db %10010010, %00000000 + db %10010010, %00000000 + db %01101100, %00000000 + db %01000100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %00111100, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01111100, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01111100, %00000000 + db %01000100, %00000000 + db %01000010, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01000000, %00000000 + db %01111110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000 + db %01111000, %00000000 + db %01000100, %00000000 + db %01000010, %00000000 + db %01000010, %00000000 + db %01000100, %00000000 + db %01111000, %00000000 + db %00000000, %00000000 + +constant TileData.size = pc() - TileData + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/dma-ends-hdma-start-1-ch.asm b/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/dma-ends-hdma-start-1-ch.asm new file mode 100644 index 00000000..533a9449 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/dma-ends-hdma-start-1-ch.asm @@ -0,0 +1,701 @@ +// DMA Ends at HDMA start test +// 1 HDMA channel with a DMA channel reading a constant (0) `MPYL` value to a fixed A-Bus address. +// +// +// The SNES Development Discord was discussing Ramsis's DMA<>HDMA crash test[1] and noticed the +// test displays a flicking HDMA gradient on S-CPU-A (CPU version 2) console. Investigating the +// test revealed the flicking gradient occurs when the DMA finishes at around the same time HDMA +// is initialized (shortly after the start of scanline 0). +// +// [1]: Test ROM that lets you trigger the infamous DMA<>HDMA clash by Ramsis +// https://forums.nesdev.org/viewtopic.php?p=155872#p155872 +// +// +// This test is designed to confirm or deny a HDMA can be interrupted by a DMA if the DMA finishes +// when HDMA starts. +// +// On every VBlank this test will: +// * Read the value of the HDMA state registers and stores them in Work-RAM. +// +// * Reset the `A2An` and `NLTRn` HDMA state registers. +// +// * Set the `BG2HOFS` register to a value that is not used by the HDMA. +// +// * Preform 2 DMA transfers on every Vertical Blank interrupt. +// The first DMA transfers a text buffer to VRAM, while the second DMA will repeatedly read the +// `MPYL` register `dmaDelay` times. +// +// After VBlank: +// * Test the copy of a `A2An` HDMA state variable matched the expected value. +// If the value was incorrect, a HDMA failure occurred. +// +// * If no error has been detected, increase the `dmaDelay` value every `DMA_DELAY_REPEAT` frames +// (so the end of the second DMA will slowly approach and then pass the HDMA start time). +// +// +// Please wait until the tests prints a success (HDMA OK) or failure (HDMA FAILURE DETECTED) message +// before publishing results. +// +// +// Test Results: +// * Straight vertical green line on the left: no HDMA +// * Wavy green line on the right: HDMA completed successfully +// * Green line on the right: HDMA was interrupted +// * Red screen: Break interrupt (crash) +// +// +// My Observations (on version 1 of this test): +// * Model-1 1/1/1 Super Famicom: No crash. HDMA Failure detected. +// * S-CPU-A Super Famicom: HDMA Failure detected. +// * 1-CHIP Super Famicom: HDMA Failure detected. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "DMA ENDS AT HDMA START" +define VERSION = 2 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant MIN_DMA_DELAY = 0x1310 +constant MAX_DMA_DELAY = 0x1350 + + +// The HDMA failure does not occur on every frame (most likely caused by NMI interrupt jitter). +// +// Repeat each `dmaDelay` test `DMA_DELAY_REPEAT` times to ensure the HDMA failure is detected quickly. +constant DMA_DELAY_REPEAT = 4 + + +constant DMA_CHANNEL = 0 +constant DMA_DELAY_CHANNEL = 1 +constant HDMA_CHANNEL = 2 + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +// If non-zero a HDMA failure was detected +allocate(hdmaFailureDetected, lowram, 1) + +// The number of bytes to read +allocate(dmaDelay, lowram, 2) + +allocate(dmaDelayCountdown, lowram, 1) + + +// The value of the HDMA A2AN register for the HDMA channel at the start of VBlank. +allocate(hdmaA2an, lowram, 2) +allocate(hdmaA2anOnFailure, lowram, 2) + +// The value of the HDMA NLTR register for the HDMA channel at the start of VBlank. +allocate(hdmaNltr, lowram, 1) +allocate(hdmaNltrOnFailure, lowram, 1) + + +// The PPU time at the end of the NMI routine, just after the DMA_DELAY DMA. +allocate(dmaEndTime_opvct, lowram, 2) +allocate(dmaEndTime_ophct, lowram, 2) + + +// The memory location to write the DMA writes to +allocate(dmaDelay_target, lowram, 1) + + +constant DISPLAY_HEIGHT = 224 + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG2_TILES_WADDR = 0x2000 + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG2_MAP_WADDR = 0x0400 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + + + +rodata(rodata0) +namespace Text { + constant TEST_VERSION = 2 + evaluate TEST_VERSION = TEST_VERSION + + evaluate dma_channel = DMA_CHANNEL + evaluate dma_delay_channel = DMA_DELAY_CHANNEL + evaluate hdma_channel = HDMA_CHANNEL + +TEST_STRING: + db "\n", "DMA ends at HDMA start test" + db "\n", "one HDMA channel version {TEST_VERSION}" + db "\n" + db "\n" + db "\n" + db "\n" + db "\n" + db "\n", " DMA {dma_delay_channel} (MPYL read)" + db "\n", " bytes read: $" + db "\n" + db "\n", " OPVCT: $" + db "\n" + db "\n", " OPHCT: ~$" + db "\n" + db "\n" + db "\n", " HDMA Table Address: $" + db "\n" + db "\n", " HDMA {hdma_channel} A2A{hdma_channel}: $" + db "\n", + db "\n", " HDMA {hdma_channel} NLTR{hdma_channel}: $" + db 0 + + constant VALUE_X = 22 + + constant TEST_RESULT_Y = 5 + constant TEST_RESULT_X = 3 + + constant DMA_DELAY_Y = 9 + constant DMA_END_OPVCT_Y = 11 + constant DMA_END_OPHCT_Y = 13 + + constant HDMA_TABLE_ADDR_Y = 16 + constant HDMA_A2AN_Y = 18 + constant HDMA_NLTR_Y = 20 + + constant HDMA_A2AN_ON_FAILURE_Y = 23 + constant HDMA_NLTR_ON_FAILURE_Y = 25 + +HDMA_OK: + db "HDMA OK", 0 + +HDMA_FAILURE_DETECTED: + // Must be larger then HDMA_OK_STR + db "HDMA FAILURE DETECTED", 0 + +A2AN_ON_FAILURE: + db " A2A{hdma_channel} on failure: $", 0 + +NLTR_ON_FAILURE: + db " NLTR{hdma_channel} on failure: $", 0 +} + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + // This value must be incremented whenever `SetupTest` is changed + constant TEST_VERSION = 2 + + evaluate hdma_channel = HDMA_CHANNEL + + + // Setup HDMA channels + + // BG2 HOFS HDMA + ldx.w #DMAP.direction.toPpu | DMAP.transfer.writeTwice | (BG2HOFS << 8) + stx.w DMAP{hdma_channel} // also sets BBAD{hdma_channel} + + ldx.w #HdmaTable_BG2HOFS + stx.w A1T{hdma_channel} + lda.b #HdmaTable_BG2HOFS >> 16 + sta.w A1B{hdma_channel} + + + TextBuffer.PrintString(Text.TEST_STRING) + + TextBuffer.SetCursor(Text.VALUE_X, Text.HDMA_TABLE_ADDR_Y) + ldy.w #HdmaTable_BG2HOFS + jsr TextBuffer.PrintHexSpace_16Y + + // Reset state + + stz.w hdmaFailureDetected + + ldx.w #MIN_DMA_DELAY + stx.w dmaDelay + + lda.b #DMA_DELAY_REPEAT + sta.w dmaDelayCountdown + + ldx.w #0xffff + stx.w hdmaA2an + stx.w hdmaA2anOnFailure + + lda.b #0xff + sta.w hdmaNltr + sta.w hdmaNltr + + + // Set value by read the DMA Delay to 0 + stz.w M7A + stz.w M7A + stz.w M7B + stz.w M7B + + + // Clear NMI flag + lda.w RDNMI + + // Enable VBlank interrupts + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + rts +} + + + +// DB = 0x80 +macro VBlank() { + // This macro MUST NOT use any branch or index-addressing instructions. + // + // This ensures the only variables in execution time are: + // * When the NMI interrupt starts (unavoidable) + // * When DMA starts (unavoidable) + // * `dmaDelay` (the variable I am testing) + + + // This value must be incremented whenever the VBlank macro is changed + constant TEST_VERSION = 2 + + evaluate dma_channel = DMA_CHANNEL + evaluate dma_delay_channel = DMA_DELAY_CHANNEL + evaluate hdma_channel = HDMA_CHANNEL + + assert8a() + assert16i() + + // Read HDMA state registers + ldx.w A2A{hdma_channel} + stx.w hdmaA2an + + lda.w NLTR{hdma_channel} + sta.w hdmaNltr + + + // Reset HDMA state registers + ldx.w #0 + stx.w A2A{hdma_channel} + + lda.b #0 + sta.w NLTR{hdma_channel} + + + + // Enable display, full brightness + lda.b #0xf + sta.w INIDISP + + + // Setup BG2 H-scroll to the left side of the screen. + // + // HDNA will override this value if HDMA is active. + lda.b #256 - 10 + sta.w BG2HOFS + stz.w BG2HOFS + + // Enable HDMA channels + lda.b #HDMAEN.dma{hdma_channel} + sta.w HDMAEN + + + // Transfer `charBuffer` to the low-bytes of VRAM at word-address `VRAM_TEXTBUFFER_MAP_WADDR`. + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + + assert(VMAIN.incrementMode.low | VMAIN.increment.by1 == 0) + stz.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + stx.w DMAP{dma_channel} // also sets BBAD{dma_channel} + + ldx.w #TextBuffer.charBuffer + stx.w A1T{dma_channel} + lda.b #TextBuffer.charBuffer >> 16 + sta.w A1B{dma_channel} + + ldx.w #TextBuffer.charBuffer.size + stx.w DAS{dma_channel} + + lda.b #MDMAEN.dma{dma_channel} + sta.w MDMAEN + + + // Do a DMA read of MPYL for `dmaDelay` bytes so the DMA could end as HDMA starts. + ldx.w #DMAP.direction.toCpu | DMAP.fixed | DMAP.transfer.one | (MPYL << 8) + stx.w DMAP{dma_delay_channel} // also sets BBAD{dma_delay_channel} + + ldx.w #dmaDelay_target + stx.w A1T{dma_delay_channel} + lda.b #dmaDelay_target >> 16 + sta.w A1B{dma_delay_channel} + + ldx.w dmaDelay + stx.w DAS{dma_delay_channel} + + lda.b #MDMAEN.dma{dma_delay_channel} + sta.w MDMAEN + + + // Read DMA end time from PPU + lda.w SLHV + + lda.w OPVCT + sta.w dmaEndTime_opvct + lda.w OPVCT + and.b #OPVCT.mask >> 8 + sta.w dmaEndTime_opvct + 1 + + lda.w OPHCT + sta.w dmaEndTime_ophct + lda.w OPHCT + and.b #OPHCT.mask >> 8 + sta.w dmaEndTime_ophct + 1 +} + + + +// DB = 0x80 +au() +i16() +code() +function ProcessTestResults { + // This value must be incremented whenever this subroutine is changed + constant TEST_VERSION = 2 + + // Use `A2An` to detect if HDMA was processed in the previous frame. + ldx.w hdmaA2an + cpx.w #HdmaTable_BG2HOFS.EXPECTED_A2An + beq + + lda.b #1 + sta.w hdmaFailureDetected + + stx.w hdmaA2anOnFailure + + lda.b hdmaNltr + sta.w hdmaNltrOnFailure + + + + lda.w hdmaFailureDetected + bne Return + dec.w dmaDelayCountdown + bne ++ + ldx.w dmaDelay + inx + cpx.w #MAX_DMA_DELAY + 1 + bcc + + ldx.w #MIN_DMA_DELAY + + + stx.w dmaDelay + + lda.b #DMA_DELAY_REPEAT + sta.w dmaDelayCountdown + + +Return: + rts +} + + + +// DB = 0x80 +a8() +i16() +code() +function PrintTestResults { + + inline print_u8(yPosConst, var) { + TextBuffer.SetCursor(Text.VALUE_X + 2, Text.{yPosConst}) + lda.w {var} + jsr TextBuffer.PrintHexSpace_8A + } + + inline print_u16(yPosConst, var) { + TextBuffer.SetCursor(Text.VALUE_X, Text.{yPosConst}) + ldy.w {var} + jsr TextBuffer.PrintHexSpace_16Y + } + + print_u16(DMA_DELAY_Y, dmaDelay) + print_u16(DMA_END_OPVCT_Y, dmaEndTime_opvct) + print_u16(DMA_END_OPHCT_Y, dmaEndTime_ophct) + print_u16(HDMA_A2AN_Y, hdmaA2an) + print_u8(HDMA_NLTR_Y, hdmaNltr) + + + TextBuffer.SetCursor(Text.TEST_RESULT_X, Text.TEST_RESULT_Y) + + lda.w hdmaFailureDetected + beq + + TextBuffer.PrintString(Text.HDMA_FAILURE_DETECTED) + + TextBuffer.SetCursor(0, Text.HDMA_A2AN_ON_FAILURE_Y) + TextBuffer.PrintString(Text.A2AN_ON_FAILURE) + + TextBuffer.SetCursor(0, Text.HDMA_NLTR_ON_FAILURE_Y) + TextBuffer.PrintString(Text.NLTR_ON_FAILURE) + + print_u8(HDMA_NLTR_ON_FAILURE_Y, hdmaNltrOnFailure) + print_u16(HDMA_A2AN_ON_FAILURE_Y, hdmaA2anOnFailure) + + bra EndIf + + + ldx.w dmaDelay + cpx.w #MAX_DMA_DELAY + bne EndIf + // String must be smaller then failure detected string + TextBuffer.PrintString(Text.HDMA_OK) + EndIf: + + rts +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 | TM.bg2 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG2_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG2SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift | (VRAM_BG2_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg2.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + ldx.w #VRAM_BG2_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2Tiles) + + ldx.w #VRAM_BG2_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2Map) + + + jsr SetupTest + + // Must wait 1 frame before processing results to avoid a false positive + wai + + MainLoop: + wai + + jsr ProcessTestResults + jsr PrintTestResults + + bra MainLoop +} + + +// DB unknown +au() +iu() +code() +function NmiHandler { + constant TEST_VERSION = 2 + + // This ISR must not use any branch or index-addressing instructions. + + // Save CPU state + rep #$30 +a16() +i16() + pha + phx + phy + phd + phb + + + phk + plb +// DB = 0x00 or 0x80 + + lda.w #0 + tcd +// DP = 0 + + sep #$20 +a8() + + // No lag frame detection + // The VBlank routine must execute each frame in a consistent manner. + VBlank() + + rep #$30 +a16() +i16() + + // Restore CPU state + assert16a() + assert16i() + plb + pld + ply + plx + pla + + rti +} + + + +namespace Resources { + +rodata(rodata0) +Palette: + // BG1 palette + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) + fill 60, 0 + + // BG2 palette + dw ToPalette(0, 0, 0) + dw ToPalette(0, 31, 0) + +constant Palette.size = pc() - Palette + + +Bg2Tiles: + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 +constant Bg2Tiles.size = pc() - Bg2Tiles + + +Bg2Map: + variable _i = 0 + while _i < 32 { + dw 1 + fill 31*2, 0 + + _i = _i + 1 + } + +constant Bg2Map.size = pc() - Bg2Tiles +} + + +// Write twice HDMA table to BG2 HOFS +HdmaTable_BG2HOFS: +namespace HdmaTable_BG2HOFS { + macro hofs_24() { + // Calculated using python + // >>> import math + // >>> [ round(20 + 4 * math.sin(i / 24 * math.tau)) for i in range(24) ] + dw 20, 21, 22, 23, 23, 24, 24, 24, 23, 23, 22, 21, 20, 19, 18, 17, 17, 16, 16, 16, 17, 17, 18, 19 + } + + db 0x80 | 120 // HDMA repeat mode, 120 scanlines + hofs_24() + hofs_24() + hofs_24() + hofs_24() + hofs_24() + + db 0x80 | 120 // HDMA repeat mode, 120 scanlines + hofs_24() + hofs_24() + hofs_24() + hofs_24() + hofs_24() + + db 0 // End HDMA table + + + // The expected A2An value at VBlank if the HDMA table is active + constant EXPECTED_A2An = HdmaTable_BG2HOFS + 2 + (DISPLAY_HEIGHT + 1) * 2 +} + + +finalizeMemory() + + +assert(SetupTest.TEST_VERSION == Text.TEST_VERSION) +assert(NmiHandler.TEST_VERSION == Text.TEST_VERSION) +assert(NmiHandler.VBlank.TEST_VERSION == Text.TEST_VERSION) +assert(ProcessTestResults.TEST_VERSION == Text.TEST_VERSION) + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/hdma-failure-last-dma-value-test.asm b/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/hdma-failure-last-dma-value-test.asm new file mode 100644 index 00000000..3fd43cac --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/dma-ends-at-hdma-start/hdma-failure-last-dma-value-test.asm @@ -0,0 +1,689 @@ +// DMA Ends at HDMA start test +// Testing the previous value read by the DMA controller. +// +// While working on the `dma-ends-hdma-start-1-ch.asm` test, I wondered if the previous value read +// by the DMA controller contributed to the HDMA failure. +// +// This test will setup a DMA from Work-RAM to the PPU that is designed to end when HDMA starts. +// The last value read by the DMA controller is slowly incremented from 0x00 to 0xff. The HDMA state +// registers are checked during VBlank to detect any HDMA failures and the results for each test +// value are displayed on screen. +// +// To eliminate NMI jitter and other timing issues, each test value is repeated multiple times with +// multiple DMA lengths to ensure at least one DMA transfer ends at the target time. +// +// If no HDMA failures are detected when the last DMA value is 0 (a known failure value), the test +// will display an error message. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA FAILURE TEST" +define VERSION = 2 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +// MAX_DMA_DELAY selected based off the `dma-ends-at-hdma-start-1-ch` test. +// MIN_DMA_DELAY selected to ensure the DMA_DELAY ends before scanline 0 starts (and confirmed with Mesen's Event Viewer). +constant MIN_DMA_DELAY = 0x1330 +constant MAX_DMA_DELAY = 0x133A + + +// The HDMA failure does not occur on every frame (most likely caused by NMI interrupt jitter). +// +// Repeat each `dmaDelay` test `DMA_DELAY_REPEAT` times to ensure the HDMA failure is detected quickly. +constant DMA_DELAY_REPEAT = 4 + + +// Using a different channel order then the `dma-ends-at-hdma-start-1-ch` test. +constant DMA_CHANNEL = 7 +constant DMA_DELAY_CHANNEL = 6 +constant HDMA_CHANNEL = 0 + + +// $2104 (OAMDATA) is chosen because there are no Objects on screen and it is visible in the Mesen Event Viewer. +constant DMA_DELAY_TARGET = 0x2104 + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +// The value to test (last byte read by the DMA controller before HDMA starts) +// (this value will cycle through 0x00-0xff throughout the test) +allocate(valueToTest, lowram, 1) + +// The number of bytes to read +allocate(dmaDelay, lowram, 2) + +allocate(dmaDelayCountdown, lowram, 1) + + +// The value of the HDMA A2AN register for the HDMA channel at the start of VBlank. +allocate(hdmaA2an, lowram, 2) + +// The value of the HDMA NLTR register for the HDMA channel at the start of VBlank. +// (unused) +allocate(hdmaNltr, lowram, 1) + + +allocate(testResults, lowram, 256) + + +// The buffer read by the DMA_DELAY_CHANNEL DMA. +// (Populated by `PopulateDmaBuffer`) +constant dmaBuffer.size = MAX_DMA_DELAY + 16 +allocate(dmaBuffer, wram7e, dmaBuffer.size) + + +constant DISPLAY_HEIGHT = 224 + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG2_TILES_WADDR = 0x2000 + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG2_MAP_WADDR = 0x0400 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + + + +rodata(rodata0) +namespace Text { + constant TEST_VERSION = 2 + evaluate TEST_VERSION = TEST_VERSION + + evaluate dma_channel = DMA_CHANNEL + evaluate dma_delay_channel = DMA_DELAY_CHANNEL + evaluate hdma_channel = HDMA_CHANNEL + +TEST_STRING: + db "\n", "DMA ends at HDMA start test" + db "\n", "previous DMA value test, v{TEST_VERSION}" + db "\n", + db "\n", + db "\n", + db "\n", " 0123456789abcdef" + db "\n", " 0" + db "\n", " 1" + db "\n", " 2" + db "\n", " 3" + db "\n", " 4" + db "\n", " 5" + db "\n", " 6" + db "\n", " 7" + db "\n", " 8" + db "\n", " 9" + db "\n", " a" + db "\n", " b" + db "\n", " c" + db "\n", " d" + db "\n", " e" + db "\n", " f" + db "\n", + db "\n", " X = Failure . = HDMA OK" + db "\n", + db 0 + + + constant RESULTS_X = 6 + constant RESULTS_Y = 7 + + constant NO_FAILURE_DETECTED_X = 1 + constant NO_FAILURE_DETECTED_Y = 4 +} + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + // This value must be incremented whenever `SetupTest` is changed + constant TEST_VERSION = 2 + + evaluate hdma_channel = HDMA_CHANNEL + + + // Setup HDMA channels + + // BG2 HOFS HDMA + ldx.w #DMAP.direction.toPpu | DMAP.transfer.writeTwice | (BG2HOFS << 8) + stx.w DMAP{hdma_channel} // also sets BBAD{hdma_channel} + + ldx.w #HdmaTable_BG2HOFS + stx.w A1T{hdma_channel} + lda.b #HdmaTable_BG2HOFS >> 16 + sta.w A1B{hdma_channel} + + + TextBuffer.PrintString(Text.TEST_STRING) + + + // Reset state + + stz.w valueToTest + + ldx.w #MIN_DMA_DELAY + stx.w dmaDelay + + lda.b #DMA_DELAY_REPEAT + sta.w dmaDelayCountdown + + ldx.w #0xffff + stx.w hdmaA2an + + lda.b #0xff + sta.w hdmaNltr + + jsr PopulateDmaBuffer + + + // Clear test results + ldx.w #0xff + - + stz.w testResults,x + dex + bpl - + + + // Clear NMI flag + lda.w RDNMI + + // Enable VBlank interrupts + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + rts +} + + + +// DB = 0x80 +macro VBlank() { + // This macro MUST NOT use any branch or index-addressing instructions. + // + // This ensures the only variables in execution time are: + // * When the NMI interrupt starts (unavoidable) + // * When DMA starts (unavoidable) + // * `dmaDelay` (the variable I am testing) + + + // This value must be incremented whenever the VBlank macro is changed + constant TEST_VERSION = 2 + + evaluate dma_channel = DMA_CHANNEL + evaluate dma_delay_channel = DMA_DELAY_CHANNEL + evaluate hdma_channel = HDMA_CHANNEL + + assert8a() + assert16i() + + // Read HDMA state registers + ldx.w A2A{hdma_channel} + stx.w hdmaA2an + + lda.w NLTR{hdma_channel} + sta.w hdmaNltr + + + // Reset HDMA state registers + ldx.w #0 + stx.w A2A{hdma_channel} + + lda.b #0 + sta.w NLTR{hdma_channel} + + + + // Enable display, full brightness + lda.b #0xf + sta.w INIDISP + + + // Setup BG2 H-scroll to the left side of the screen. + // + // HDNA will override this value if HDMA is active. + lda.b #256 - 10 + sta.w BG2HOFS + stz.w BG2HOFS + + // Enable HDMA channels + lda.b #HDMAEN.dma{hdma_channel} + sta.w HDMAEN + + + // Transfer `charBuffer` to the low-bytes of VRAM at word-address `VRAM_TEXTBUFFER_MAP_WADDR`. + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + + assert(VMAIN.incrementMode.low | VMAIN.increment.by1 == 0) + stz.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + stx.w DMAP{dma_channel} // also sets BBAD{dma_channel} + + ldx.w #TextBuffer.charBuffer + stx.w A1T{dma_channel} + lda.b #TextBuffer.charBuffer >> 16 + sta.w A1B{dma_channel} + + ldx.w #TextBuffer.charBuffer.size + stx.w DAS{dma_channel} + + lda.b #MDMAEN.dma{dma_channel} + sta.w MDMAEN + + + // Do a DMA write from `valueToTest` to the B-Bus `dmaDelay` bytes so the DMA could end as HDMA starts. + assert(DMA_DELAY_TARGET & ~0xff == 0x2100) + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (DMA_DELAY_TARGET << 8) + stx.w DMAP{dma_delay_channel} // also sets BBAD{dma_delay_channel} + + ldx.w #dmaBuffer + stx.w A1T{dma_delay_channel} + lda.b #dmaBuffer >> 16 + sta.w A1B{dma_delay_channel} + + ldx.w dmaDelay + stx.w DAS{dma_delay_channel} + + lda.b #MDMAEN.dma{dma_delay_channel} + sta.w MDMAEN +} + + +a8() +i16() +code() +function PopulateDmaBuffer { + lda.w valueToTest + + ldx.w #MIN_DMA_DELAY - 8 + - + sta.l dmaBuffer,x + inx + cpx.w #dmaBuffer.size + bcc - + + rts +} + + + +// DB = 0x80 +a8() +i16() +code() +function ProcessTestResults { + // This value must be incremented whenever this subroutine is changed + constant TEST_VERSION = 2 + + // Use `A2An` to detect if HDMA was processed in the previous frame. + ldx.w hdmaA2an + cpx.w #HdmaTable_BG2HOFS.EXPECTED_A2An + beq NoFailureDetected + sep #$30 + i8() + ldx.w valueToTest + + lda.b #1 + sta.w testResults,x + + rep #$10 + i16() +NoFailureDetected: + + dec.w dmaDelayCountdown + bne Return + ldx.w dmaDelay + inx + cpx.w #MAX_DMA_DELAY + 1 + bcc + + lda.w valueToTest + jsr PrintTestResult + + // Test the next value + inc.w valueToTest + + jsr PopulateDmaBuffer + + lda.w valueToTest + jsr SetCurosrPosAndGetResults + TextBuffer.PrintStringLiteral("?") + + jsr ConfirmHdmaFailureDetected + + ldx.w #MIN_DMA_DELAY + + + stx.w dmaDelay + + lda.b #DMA_DELAY_REPEAT + sta.w dmaDelayCountdown + +Return: + rts +} + + +a8() +i16() +code() +function ConfirmHdmaFailureDetected { + lda.w valueToTest + beq Return + + lda.w testResults + 0 + bne Return + + TextBuffer.SetCursor(Text.NO_FAILURE_DETECTED_X, Text.NO_FAILURE_DETECTED_Y) + TextBuffer.PrintStringLiteral("ERROR: No HDMA failure!!!") + +Return: + rts +} + + +// INPUT: A - test index +a8() +i16() +code() +function PrintTestResult { + jsr SetCurosrPosAndGetResults + beq + + TextBuffer.PrintStringLiteral("X") + bra ++ + + + TextBuffer.PrintStringLiteral(".") + + + + rts +} + + + +// INPUT: A - test index +// OUTPUT: A - test results +// OUTPUT: z - set if no results +a8() +i16() +code() +function SetCurosrPosAndGetResults { + sep #$30 +i8() + pha + + and.b #0x0f + clc + adc.b #Text.RESULTS_X + tax + + lda 1,s + lsr + lsr + lsr + lsr + clc + adc.b #Text.RESULTS_Y + tay + + jsr TextBuffer.SetCursor + + + plx + lda.w testResults,x + + rep #$10 +i16() + + rts +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 | TM.bg2 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG2_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG2SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift | (VRAM_BG2_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg2.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + ldx.w #VRAM_BG2_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2Tiles) + + ldx.w #VRAM_BG2_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg2Map) + + + jsr SetupTest + + // Must wait 1 frame before processing results to avoid a false positive + wai + + MainLoop: + wai + jsr ProcessTestResults + + bra MainLoop +} + + +// DB unknown +au() +iu() +code() +function NmiHandler { + constant TEST_VERSION = 2 + + // This ISR must not use any branch or index-addressing instructions. + + // Save CPU state + rep #$30 +a16() +i16() + pha + phx + phy + phd + phb + + + phk + plb +// DB = 0x00 or 0x80 + + lda.w #0 + tcd +// DP = 0 + + sep #$20 +a8() + + // No lag frame detection + // The VBlank routine must execute each frame in a consistent manner. + VBlank() + + rep #$30 +a16() +i16() + + // Restore CPU state + assert16a() + assert16i() + plb + pld + ply + plx + pla + + rti +} + + + +namespace Resources { + +rodata(rodata0) +Palette: + // BG1 palette + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) + fill 60, 0 + + // BG2 palette + dw ToPalette(0, 0, 0) + dw ToPalette(0, 31, 0) + +constant Palette.size = pc() - Palette + + +Bg2Tiles: + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + db %00000000, 0 + + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 + db %11000000, 0 +constant Bg2Tiles.size = pc() - Bg2Tiles + + +Bg2Map: + variable _i = 0 + while _i < 32 { + dw 1 + fill 31*2, 0 + + _i = _i + 1 + } + +constant Bg2Map.size = pc() - Bg2Tiles +} + + +// Write twice HDMA table to BG2 HOFS +HdmaTable_BG2HOFS: +namespace HdmaTable_BG2HOFS { + macro hofs_24() { + // Calculated using python + // >>> import math + // >>> [ round(20 + 4 * math.sin(i / 24 * math.tau)) for i in range(24) ] + dw 20, 21, 22, 23, 23, 24, 24, 24, 23, 23, 22, 21, 20, 19, 18, 17, 17, 16, 16, 16, 17, 17, 18, 19 + } + + db 0x80 | 120 // HDMA repeat mode, 120 scanlines + hofs_24() + hofs_24() + hofs_24() + hofs_24() + hofs_24() + + db 0x80 | 120 // HDMA repeat mode, 120 scanlines + hofs_24() + hofs_24() + hofs_24() + hofs_24() + hofs_24() + + db 0 // End HDMA table + + + // The expected A2An value at VBlank if the HDMA table is active + constant EXPECTED_A2An = HdmaTable_BG2HOFS + 2 + (DISPLAY_HEIGHT + 1) * 2 +} + + +finalizeMemory() + + +assert(SetupTest.TEST_VERSION == Text.TEST_VERSION) +assert(NmiHandler.TEST_VERSION == Text.TEST_VERSION) +assert(NmiHandler.VBlank.TEST_VERSION == Text.TEST_VERSION) +assert(ProcessTestResults.TEST_VERSION == Text.TEST_VERSION) + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/glitch-test.inc b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/glitch-test.inc new file mode 100644 index 00000000..0b069c60 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/glitch-test.inc @@ -0,0 +1,273 @@ +// Tests if writing to $2100 using HDMA can glitch sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" + + +// BG2-4 uses WADDR 0 +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + + +// NMI handler - does nothing +au() +iu() +code() +function NmiHandler { + rti +} + + + +// Waits until the start of VBlank +// REQUIRES: NMI enabled +au() +iu() +code() +function WaitFrame { + php + sep #$20 +a8() + // Wait until end of vBlank (if in vBlank) + - + lda.l HVBJOY + bmi - + + // Wait until start of next vBlank + - + wai + assert(HVBJOY.vBlank == 0x80) + lda.l HVBJOY + bpl - + + plp + + rts +} + + + +// Setup and initialize the PPU +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// MODIFIES: enables force-blank +macro SetupPpu() { + assert8a() + assert16i() + + // Enable NMI and autoJoy (just in case) + lda.b #NMITIMEN.vBlank | NMITIMEN.autoJoy + sta.w NMITIMEN + + jsr WaitFrame + + + // Set PPU registers + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #1 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + // BG2-BG4 have a TILE & MAP WADDR of 0 (as set by ResetRegisters) + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #TM.bg1 | TM.obj + sta.w TM + + + // Fill bottom half of CGRAM with a red pattern. + // 16 colour gradient of mid-red to bright-red, repeated 8 times + stz.w CGADD + + ldx.w #128 + - + txa + dec + eor.b #0xff + and.b #0x0f + ora.b #0x10 + sta.w CGDATA + stz.w CGDATA + + dex + bne - + + + // Fill top half of CGRAM with a bright green pattern. + // 16 colour gradient of mid-green to bright-green, repeated 8 times + sep #$30 + rep #$20 +a16() +i8() + ldx.b #128 + - + txa + dec + eor.w #0xffff + and.w #0x000f + ora.w #0x0010 + asl + asl + asl + asl + asl + + tay + sty.w CGDATA + xba + tay + sty.w CGDATA + + dex + bne - + + rep #$30 + sep #$20 +a8() +i16() + + + // Load obj palette + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Set size of sprites used in Obj_Oam to large (32x32) + lda.b #1 + stz.w OAMADDL + sta.w OAMADDH + + ldx.w #Resources.Obj_Oam.size / 4 / 4 + lda.b #%10101010 + - + sta.w OAMDATA + dex + bne - + + + // Transfer tiles and map to VRAM + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_4bpp) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette_4bpp) + + + // Enable VBlank (required for WaitFrame) + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + + SetupPpu() + + jsr WaitFrame + + SetupHdma() + + lda.b #0x0f + sta.w INIDISP + + + // Glitch is more likely to appear if I spinloop + SpinLoop: + bra SpinLoop +} + + + +namespace Resources { + insert Bg1_Tilemap, "../../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_4bpp, "../../../gen/example-backgrounds/bricks-4bpp-tiles.tiles" + insert Palette_4bpp, "../../../gen/example-backgrounds/bricks-4bpp-tiles.pal" + + insert Obj_Tiles, "../../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../../gen/example-backgrounds/obj-oam.bin" +} + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-0a.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-0a.asm new file mode 100644 index 00000000..9b8cf144 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-0a.asm @@ -0,0 +1,111 @@ +// Tests if writing to $2100 using HDMA after a previous HDMA channel has +// written data would glitch sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// This test does not glitch on my console. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 2100 2CH 0A TEST" +define VERSION = 1 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP6 + + lda.b #BGMODE + sta.w BBAD6 + + ldx.w #HdmaTable_bgmode + stx.w A1T6 + + lda.b #HdmaTable_bgmode >> 16 + sta.w A1B6 + + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP7 + + lda.b #0x00 + sta.w BBAD7 + + ldx.w #HdmaTable_inidisp + stx.w A1T7 + + lda.b #HdmaTable_inidisp >> 16 + sta.w A1B7 + + + lda.b #HDMAEN.dma6 | HDMAEN.dma7 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable_bgmode: + variable n = 0 + while n < 256 { + db 1 + // Bahamut Lagoon uses HDMA to write 0x0a to BGMODE ($2105) then 0x0f to INIDISP ($2100). + // This does not glitch on my system. + db 0x0a + + n = n + 1 + } + + db 0 + + +code() +HdmaTable_inidisp: + variable n = 0 + while n < 256 { + db 1 + db 0x0f + + db 1 + db 0x0d + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-81.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-81.asm new file mode 100644 index 00000000..babedac2 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch-2ch-81.asm @@ -0,0 +1,110 @@ +// Tests if writing to $2100 using HDMA after a previous HDMA channel has +// written data would glitch sprites. +// +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 2100 2CH 81 TEST" +define VERSION = 1 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP6 + + lda.b #BGMODE + sta.w BBAD6 + + ldx.w #HdmaTable_bgmode + stx.w A1T6 + + lda.b #HdmaTable_bgmode >> 16 + sta.w A1B6 + + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP7 + + lda.b #0x00 + sta.w BBAD7 + + ldx.w #HdmaTable_inidisp + stx.w A1T7 + + lda.b #HdmaTable_inidisp >> 16 + sta.w A1B7 + + + lda.b #HDMAEN.dma6 | HDMAEN.dma7 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable_bgmode: + variable n = 0 + while n < 256 { + db 1 + // If bit 7 is set then this table causes a glitch. + // It doesn't matter what the value or target register is, if bit 7 is set, it can glitch. + db 0x81 + + n = n + 1 + } + + db 0 + + +code() +HdmaTable_inidisp: + variable n = 0 + while n < 256 { + db 1 + db 0x0f + + db 1 + db 0x08 + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch.asm new file mode 100644 index 00000000..c90afcb5 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-2100-glitch.asm @@ -0,0 +1,77 @@ +// Tests if writing to $2100 using HDMA glitches sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 2100 GLITCH TEST" +define VERSION = 2 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP0 + + lda.b #0x00 + sta.w BBAD0 + + ldx.w #HdmaTable + stx.w A1T0 + + lda.b #HdmaTable >> 16 + sta.w A1B0 + + + lda.b #HDMAEN.dma0 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + // 2100 + db 0x0f + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-0f-glitch.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-0f-glitch.asm new file mode 100644 index 00000000..0b909693 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-0f-glitch.asm @@ -0,0 +1,77 @@ +// Tests if writing to $21ff and $2100 using the same HDMA channel glitches sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 21ff 2100 0F GLITCH" +define VERSION = 2 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.two + sta.w DMAP0 + + lda.b #0xff + sta.w BBAD0 + + ldx.w #HdmaTable + stx.w A1T0 + + lda.b #HdmaTable >> 16 + sta.w A1B0 + + + lda.b #HDMAEN.dma0 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + // 21ff 2100 + db 0x0f, 0x0f + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-glitch.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-glitch.asm new file mode 100644 index 00000000..9ed1a814 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-2100-glitch.asm @@ -0,0 +1,81 @@ +// Tests if writing to $21ff and $2100 using the same HDMA channel glitches sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 21ff 2100 GLITCH" +define VERSION = 2 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.two + sta.w DMAP0 + + lda.b #0xff + sta.w BBAD0 + + ldx.w #HdmaTable + stx.w A1T0 + + lda.b #HdmaTable >> 16 + sta.w A1B0 + + + lda.b #HDMAEN.dma0 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + // 21ff 2100 + db 0xff, 0x0f + + db 1 + // 21ff 2100 + db 0xff, 0x0a + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-glitch.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-glitch.asm new file mode 100644 index 00000000..ce5d895d --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch-hdma/hdma-21ff-glitch.asm @@ -0,0 +1,77 @@ +// Tests if writing to $21ff using HDMA glitches sprites. +// +// You may need to reset your console a few times for the glitch to appear. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "HDMA 21ff GLITCH TEST" +define VERSION = 2 + + +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + sta.w DMAP0 + + lda.b #0xff + sta.w BBAD0 + + ldx.w #HdmaTable + stx.w A1T0 + + lda.b #HdmaTable >> 16 + sta.w A1B0 + + + lda.b #HDMAEN.dma0 + sta.w HDMAEN +} + + +include "glitch-test.inc" + + +code() +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + // 21ff + db 0xff + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/_inidisp-hammer-common.inc b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/_inidisp-hammer-common.inc new file mode 100644 index 00000000..17d2d2f8 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/_inidisp-hammer-common.inc @@ -0,0 +1,197 @@ +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" + + + +// BG2-4 uses WADDR 0 +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + + +// This test does not use NMI Interrupts. +constant NmiHandler = BreakHandler + + + +// Setup and initialize the PPU +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// MODIFIES: enables force-blank +macro SetupPpu() { + assert8a() + assert16i() + + stz.w NMITIMEN + + + // Set PPU registers + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #1 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + // BG2-BG4 have a TILE & MAP WADDR of 0 (as set by ResetRegisters) + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #TM.bg1 | TM.obj + sta.w TM + + + // Fill bottom half of CGRAM with a red pattern. + // 16 colour gradient of mid-red to bright-red, repeated 8 times + stz.w CGADD + + ldx.w #128 + - + txa + dec + eor.b #0xff + and.b #0x0f + ora.b #0x10 + sta.w CGDATA + stz.w CGDATA + + dex + bne - + + + // Fill top half of CGRAM with a bright green pattern. + // 16 colour gradient of mid-green to bright-green, repeated 8 times + sep #$30 + rep #$20 +a16() +i8() + ldx.b #128 + - + txa + dec + eor.w #0xffff + and.w #0x000f + ora.w #0x0010 + asl + asl + asl + asl + asl + + tay + sty.w CGDATA + xba + tay + sty.w CGDATA + + dex + bne - + + rep #$30 + sep #$20 +a8() +i16() + + + // Load obj palette + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Set size of sprites used in Obj_Oam to large (32x32) + lda.b #1 + stz.w OAMADDL + sta.w OAMADDH + + ldx.w #Resources.Obj_Oam.size / 4 / 4 + lda.b #%10101010 + - + sta.w OAMDATA + dex + bne - + + + // Transfer tiles and map to VRAM + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_4bpp) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette_4bpp) +} + + +namespace Resources { + insert Bg1_Tilemap, "../../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_4bpp, "../../../gen/example-backgrounds/bricks-4bpp-tiles.tiles" + insert Palette_4bpp, "../../../gen/example-backgrounds/bricks-4bpp-tiles.pal" + + insert Obj_Tiles, "../../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../../gen/example-backgrounds/obj-oam.bin" +} + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-d7-glitch-test.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-d7-glitch-test.asm new file mode 100644 index 00000000..5400314f --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-d7-glitch-test.asm @@ -0,0 +1,101 @@ +// Tests if writing to INIDISP when the previous value on the data bus +// has bit 7 set would cause a sprite glitch. +// +// This is an interactive test: +// * if A/B/X/Y button is not pressed then the test will write +// 0x80 to $20ff and `0x0f` to INIDISP. +// +// * if A/B/X/Y button is pressed then the test will write +// 0x00 to $20ff and `0x0f` to INIDISP. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP D7 GLITCH TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + lda.b #0x0f + sta.w INIDISP + + lda.b #NMITIMEN.autoJoy + sta.w NMITIMEN + + + MainLoop: + // Check if a button is pressed + // There is not need to check `HVBJOY`, bad `JOY1` reads affect non-visible scanlines. + lda.b #JOYH.b | JOYH.y + bit.w JOY1H + bne ButtonPressed + + lda.b #JOYL.a | JOYL.x + bit.w JOY1L + bne ButtonPressed + // No button pressed, write to 2100 with data bus b7 set + ldx.w #0x0f80 + + bra EndIf + + ButtonPressed: + // No button pressed, write to 2100 with data bus b7 clear + ldx.w #0x0f00 + + EndIf: + + + // Wait until hBlank + - + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvc - + + + stx.w INIDISP - 1 + + + // Wait until the end of hBlank + - + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvs - + + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f-long.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f-long.asm new file mode 100644 index 00000000..7b166e3d --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f-long.asm @@ -0,0 +1,53 @@ +// Constantly writes 0x0f to address $802100 +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + lda.b #0x0f + + MainLoop: + sta.l 0x802100 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f.asm new file mode 100644 index 00000000..a28c4cbb --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f.asm @@ -0,0 +1,53 @@ +// Constantly writes 0x0f to INIDISP +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + lda.b #0x0f + + MainLoop: + sta.w INIDISP + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f00.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f00.asm new file mode 100644 index 00000000..02dc47eb --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f00.asm @@ -0,0 +1,54 @@ +// Constantly writes 0x0f00 to $20ff (0x00 to $20ff, 0x0f to $2100) +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + // ::TODO remove BG/OAM and replace with a white screen:: + + ldx.w #0x0f00 + MainLoop: + stx.w INIDISP - 1 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f0f.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f0f.asm new file mode 100644 index 00000000..2837751c --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f0f.asm @@ -0,0 +1,54 @@ +// Constantly writes 0x0f0f to $20ff (0x0f to $20ff, 0x0f to $2100) +// +// This test does not show any glitches +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + ldx.w #0x0f0f + MainLoop: + stx.w INIDISP - 1 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f-fast.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f-fast.asm new file mode 100644 index 00000000..25baec61 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f-fast.asm @@ -0,0 +1,53 @@ +// Constantly writes 0x0f8f to $20ff (0x8f to $20ff, 0x0f to $2100) +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + ldx.w #0x0f8f + + MainLoop: + stx.w INIDISP - 1 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f.asm new file mode 100644 index 00000000..ef1dd73f --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-0f8f.asm @@ -0,0 +1,53 @@ +// Constantly writes 0x0f8f to $20ff (0x8f to $20ff, 0x0f to $2100) +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + MainLoop: + // Adding a delay here the sprite glitch more interesting + ldx.w #0x0f8f + stx.w INIDISP - 1 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-8f0f.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-8f0f.asm new file mode 100644 index 00000000..a8aae278 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-8f0f.asm @@ -0,0 +1,53 @@ +// Constantly writes 0x8f0f to $20ff (0x0f to $20ff, 0x8f to $2100) +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + MainLoop: + // Adding a delay here makes the pattern easier to see on my display + ldx.w #0x8f0f + stx.w INIDISP - 1 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-long-0f2100.asm b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-long-0f2100.asm new file mode 100644 index 00000000..0a1b9888 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/inidisp-early-read-glitch/inidisp-hammer-long-0f2100.asm @@ -0,0 +1,56 @@ +// Constantly writes 0x0f to address $0f2100 +// +// This test confirms there are no corrupted tiles when using the +// `sta $0f2100` mitigation to the INIDISP open bus glitch. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "INIDISP HAMMER TEST" +define VERSION = 1 + +include "_inidisp-hammer-common.inc" + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + lda.b #0x0f + + MainLoop: + sta.l $0f2100 + + bra MainLoop +} + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_quick-model-1-dma-crash-test.inc b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_quick-model-1-dma-crash-test.inc new file mode 100644 index 00000000..77f80468 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_quick-model-1-dma-crash-test.inc @@ -0,0 +1,289 @@ +// A Model-1 HDMA/DMA crash test ROM +// +// This test is designed to recreate the conditions of the model 1/1/1 DMA/HDMA crash as quickly as +// possible (frame 0, scanline 1 or 0). +// +// Test output: +// * Red screen: A break interrupt occurred (crash). +// * White screen: HDMA was not active on scanline 0. +// * Green HDMA gradient: No crashes detected and no HDMA errors. +// The S-CPU may have done something unexpected, but it did not execute a `brk` or `cop` instructions. +// +// +// It has been discovered that a sd2snes has a different reset position to a normal cartridge. +// To make matters worse, there is a 10 dot jitter in the reset position. To minimize the +// reset-jitter half of the tests (`_test-no-irq-delay.inc`) use an IRQ interrupt to delay the test +// by a single scanline to minimize the test-start jitter to 3 dots. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +architecture wdc65816 + +include "../../_common/registers.inc" + + +// Memory location to store the `OPHCT` value read by the test. +// Used to verify the IRQ delay works correctly. +constant ophctValue = 0 + + +constant DISPLAY_HEIGHT = 224 + +constant FAILURE_COLOR = %00000'00000'01000 + + +// Lorom seek macro +macro seek(evaluate addr) { + origin (({addr} & 0x3f0000) >> 1) | ({addr} & 0x7fff) + base {addr} +} + + +seek(0xA000) +include "../../break_handler.inc" + + + +// This macro must be invoked at the start of an IRQ or Reset ISR. +// +// DB = 0 +// SP unknown +// e unknown +// d = 0 +// a8 +// i unknown +macro QuickDmaTest(evaluate DMA_TRANSFER_SIZE) { + // Latch PPU counters as early as possible + lda.w SLHV + + // Not setting Stack Pointer (not enough CPU time). + // The high byte of SP is 0x01 on reset and this test only uses a single variable at 0x00 + + clc + xce + + rep #$38 + sep #$24 +// d flag clear +// i flag set +// i16 +// a8 + + // Save OPHCT counter to be read by usb2snes to verify the horizontal-position is correct + lda.w OPHCT + sta.b ophctValue + + + // Set backdrop color to white + stz.w CGADD + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Setup mid-frame HDMA + ldx.w #DMAP.direction.toPpu | DMAP.transfer.twoWriteTwice | (CGADD << 8) + stx.w DMAP7 // Also sets BBAD7 + + ldx.w #HdmaTable + stx.w A1T7 + stz.w A1B7 + + // Set HDMA state registers for a repeat mode HDMA entry + inx + stx.w A2A7 // current HDMA table address + lda.b #0xff + sta.w NLTR7 // line counter + + lda.b #HDMAEN.dma7 + sta.w HDMAEN + + + // DMA transfer + // Transferring to OAMDATA so this transfer is visible on Mesen's Trace Viewer + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (OAMDATA << 8) + stx.w DMAP0 // also sets BBAD0 + + ldx.w #DmaBlock + stx.w A1T0 + stz.w A1B0 + + ldx.w #{DMA_TRANSFER_SIZE} + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + // Disable HDMA if there was no HDMA write at the end of scanline 0 + + // Wait a bit before testing the line counter + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + lda.w NLTR7 + cmp.b #0xff - 1 + beq + + stz.w HDMAEN + + + + jsr ResetRegistersExceptHdma + + + lda.b #0xf + sta.w INIDISP + + - + wai + bra - +} + + + +// NOTE: Does not reset HDMA +// +// a8 +// DB access registers +seek(0xB000) +function ResetRegisters { + stz.w HDMAEN + +// Fallthrough +} + + +function ResetRegistersExceptHdma { + stz.w NMITIMEN + + lda.b #INIDISP.force + sta.w INIDISP + + stz.w BGMODE + + stz.w MOSAIC + + lda.b #0xff + sta.w BG1VOFS + sta.w BG1VOFS + + stz.w BG1HOFS + stz.w BG1HOFS + + stz.w TM + stz.w TS + stz.w TMW + stz.w TSW + + stz.w CGWSEL + stz.w CGADSUB + + stz.w WOBJSEL + stz.w SETINI + + rts +} + + + +// The block of data to transfer on using DMA +// (using 0xff to make it easy to see on an oscilloscope) +DmaBlock: + fill 0x1000, 0xff + + + +// SNES Header +seek(0xffb0) +SnesHeader: + // Reset map + map 0, 0, 256 + + db " " // $ffbo - 2 Digit marker code (blank - unlicensed) + db " " // $ffb2 - 4 Character game code (blank - unlicensed) + db 0, 0, 0, 0, 0, 0, 0 // $ffb6 - fixed value (7 bytes) + + db 0 // $ffbd - expansion RAM size + db 0 // $ffbe - special version + db 0 // $ffbf - cartridge type sub-number + + fill 21, ' ' +seek(0xffc0) + db {ROM_NAME} // $ffc0 - ROM name (21 characters) +seek(0xffd5) + db 0x20 // $ffd5 - map mode + db 0 // $ffd6 - cartridge type (0 = ROM only) + db 7 // $ffd7 - ROM size (7 = 1Mbit) + db 0 // $ffd8 - RAM size + db 0 // $ffd9 - Destination code (0 = Japan, tested on a Super Famicom console) + db 0x33 // $ffda - fixed value + db VERSION // $ffdb - ROM version + dw 0xaaaa // $ffdc - checksum compliment + dw 0x5555 // $ffde - checksum + +// Native Interrupt Vectors + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw IrqHandler + +// Emulated Interrupt Vectors + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw BreakHandler + dw ResetHandler // $fffc - emu reset + dw BreakHandler + + + +// Padding +seek(0x03ffff) + db 0 + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-no-irq-delay.inc b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-no-irq-delay.inc new file mode 100644 index 00000000..e557badc --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-no-irq-delay.inc @@ -0,0 +1,78 @@ +// This test runs the quick-model-1-dma-crash without an IRQ delay. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +evaluate _dtl = DMA_TRANSFER_LENGTH + +define ROM_NAME = "QUICK DMA CRASH {_dtl}" +constant VERSION = 3 + +include "_quick-model-1-dma-crash-test.inc" + + +// DB = 0 +// SP = 0x01?? +// d = 0 +// i = 1 +// e = 1 +// a8 +// i8 +seek(0x8000) +function ResetHandler { + QuickDmaTest(DMA_TRANSFER_LENGTH) +} + + + +seek(0xE000) +HdmaTable: +namespace HdmaTable { + // HDMA table to CGRAM (2 registers write twice) + + variable _sl = 0 + + while _sl < DISPLAY_HEIGHT { + db 0x80 | 0x7f // HDMA repeat mode + + variable _i = 0 + while _i < 0x7f { + evaluate c = (_sl + 8) % 64 + if {c} > 31 { + evaluate c = 63 - {c} + } + _sl = _sl + 1 + + dw 0 // CGADD + dw {c} << 5 // CGDATA + + _i = _i + 1 + } + } + + db 0 +} + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-with-irq-delay.inc b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-with-irq-delay.inc new file mode 100644 index 00000000..0ca84ea5 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/_test-with-irq-delay.inc @@ -0,0 +1,116 @@ +// This test uses an IRQ interrupt to delay the start of the DMA crash test by one scanline in an +// attempt to get an sd2snes and a Quickdev16 RAM cart to start the test at the same horizontal +// position. +// +// I was not able to eliminate the test-start jitter, it has been reduced from 10 dots to 3 dots. +// +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +evaluate _dtl = DMA_TRANSFER_LENGTH + +define ROM_NAME = "QUICK DMA CRASH IRQ {_dtl}" +constant VERSION = 3 + +define USES_IRQ_INTERRUPTS + + +include "_quick-model-1-dma-crash-test.inc" + + +// DB = 0 +// SP = 0x01?? +// d = 0 +// i = 1 +// e = 1 +// a8 +// i8 +seek(0x8000) +function ResetHandler { + clc + xce + + rep #$10 +// i16 + + ldx.w #1 + stx.w VTIME + + ldx.w #23 + stx.w HTIME + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter + sta.w NMITIMEN + + // required nop + nop + + cli + + wai +} + + + +// DP = 0 +// DB = 0 +// d = 0 +seek(0x9000) +function IrqHandler { + QuickDmaTest(DMA_TRANSFER_LENGTH) +} + + + +seek(0xE000) +HdmaTable: +namespace HdmaTable { + // HDMA table to CGRAM (2 registers write twice) + // (use a different HDMA gradient then the `_test-no-irq-delay.inc` tests) + + variable _sl = 0 + + while _sl < DISPLAY_HEIGHT { + db 0x80 | 0x7f // HDMA repeat mode + + variable _i = 0 + while _i < 0x7f { + evaluate c = (_sl / 2 + 32 + 4) % 64 + if {c} > 31 { + evaluate c = 63 - {c} + } + _sl = _sl + 1 + + dw 0 // CGADD + dw {c} << 5 // CGDATA + + _i = _i + 1 + } + } + + db 0 +} + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-4.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-4.asm new file mode 100644 index 00000000..acf4b06f --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-4.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 4 + +include "_test-no-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-5.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-5.asm new file mode 100644 index 00000000..959b37ce --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-5.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 5 + +include "_test-no-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-6.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-6.asm new file mode 100644 index 00000000..35958297 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-6.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 6 + +include "_test-no-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-7.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-7.asm new file mode 100644 index 00000000..8eebfd9d --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-7.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 7 + +include "_test-no-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-4.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-4.asm new file mode 100644 index 00000000..ae1617df --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-4.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 4 + +include "_test-with-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-5.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-5.asm new file mode 100644 index 00000000..6c064b6f --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-5.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 5 + +include "_test-with-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-6.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-6.asm new file mode 100644 index 00000000..9f7c7e10 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-6.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 6 + +include "_test-with-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-7.asm b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-7.asm new file mode 100644 index 00000000..706725bf --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/quick-model-1-dma-crash/quick-model1-dma-crash-irq-7.asm @@ -0,0 +1,5 @@ + +constant DMA_TRANSFER_LENGTH = 7 + +include "_test-with-irq-delay.inc" + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/dma-test.inc b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/dma-test.inc new file mode 100644 index 00000000..2315e4ea --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/dma-test.inc @@ -0,0 +1,591 @@ +// S-CPU-A hardware DMA bug tests +// ============================== +// +// Near has reported that a DMA transfer can fail if a HDMA transfer +// with a B-Bus address of $2100 occurs on the previous scanline. +// +// +// This test will: +// * Create a HDMA transfer to INIDISP ($2100). +// +// * Preform a DMA transfer to Work-RAM on every visible scanline. +// The transfer will consist of a single byte of fixed data. +// If the DMA transfer fails, a different value will be written to Work-RAM instead. +// +// * At the end of the test, the Work-RAM data is transferred to Video-RAM. +// +// +// Output of these tests: +// +// * Green squares with a "scanline" effect - No DMA issues detected. +// The test will continue to test for a DMA bug until one occurs. +// +// * Red squares with no "scanline" effect - At least one DMA failure occurred. +// Each red square represents a single DMA failure, and green squares represent a +// successful DMA transfer. +// The test will stop execution and no-longer test for DMA failures. +// +// * No scanline effect and the display is at half-brightness - The break handler was executed. +// +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "SCPU-A DMA BUG TEST" +define VERSION = 0 + + +architecture wdc65816-strict + + +include "../../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(dp, 0x7e0000, 0x7e00ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7f, 0x7f0000, 0x7fffff) + + +// V-Counter value for the HTIME IRQ interrupt. +// +// The bug also happens in h-blank (irqXpos = 205) +define irqXpos = 20 + + +if !{defined hdma_dmap} { + evaluate hdma_dmap = DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.one + evaluate hdma_bbad = 0x00 +} + + + +// ::TODO a basic reset file that doesn't use DMA routines :: +include "../../reset_handler.inc" +include "../../dma_forceblank.inc" + + + +// VRAM MAP +// (test only uses BG1) +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + + +// Variables +constant testStatus.size = 28 * 32 +allocate(testStatus, wram7f, testStatus.size) + +allocate(byteAfterTestStatus, wram7f, 2) + +allocate(errorCount, dp, 2) + + + + +// Break ISR +// Disable HDMA, interrupts, set display to half brightness and stop execution. +code() +CopHandler: +EmptyHandler: +function BreakHandler { + // This ISR may be invoked in emulation mode, switch to native mode + sei + clc + xce + + sep #$30 +a8() +i8() + phk + plb + + stz.w NMITIMEN + stz.w HDMAEN + + lda.b #8 + sta.w INIDISP + +- + bra - +} + + + +// NMI ISR +// Does not do anything +code() +function NmiHandler { + rti +} + + + +// IRQ ISR +// +// Does not do anything +code() +function IrqHandler { + sep #$20 +a8() + pha + + lda.l TIMEUP + + pla + rti +} + + + +macro incrementErrorCount() { + assert8a() + + inc.b errorCount + bne Skip{#} + inc.b errorCount + 1 + Skip{#}: +} + + + +a8() +i16() +code() +function SetupPpu { + lda.b #INIDISP.force + sta.w INIDISP + + stz.w HDMAEN + + jsr WaitUntilVBlank + + + // Setup PPU registers + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #TM.bg1 + sta.w TM + stz.w TS + + + // Set BG1 scroll + stz.w BG1HOFS + stz.w BG1HOFS + + lda.b #0xff + sta.w BG1VOFS + sta.w BG1VOFS + + + + // Setup CGRAM colors + stz.w CGADD + + ldx.w #0 + - + lda.l PaletteData,x + sta.w CGDATA + + inx + cpx.w #PaletteData.size + bcc - + + + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + rep #$30 +a16() + + // Copy Tile Data + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + ldx.w #0 + - + lda.l TileData,x + sta.w VMDATA + + inx + inx + cpx.w #TileData.size + bcc - + + + // Clear tilemap + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + + ldx.w #32 * 32 + - + stz.w VMDATA + dex + dex + bne - + + + sep #$20 +a8() + + rts +} + + + +a8() +i16() +code() +function SetupHdma { + stz.w HDMAEN + + + lda.b #{hdma_dmap} + sta.w DMAP{hChannel} + + lda.b #{hdma_bbad} + sta.w BBAD{hChannel} + + + ldx.w #HdmaTable + stx.w A1T{hChannel} + + lda.b #HdmaTable >> 16 + sta.w A1B{hChannel} + + + // Enable HDMA + lda.b #HDMAEN.dma{hChannel} + sta.w HDMAEN + + rts +} + + + +a8() +i16() +code() +function DoTest { +constant WRITE_TEST_VALUE = 0x42 + + + // Setup WMDATA address + ldx.w #testStatus + stx.w WMADDL + + lda.b #testStatus >> 16 + sta.w WMADDH + + + // Reset the write test bytes + // (used to assert `WMDATA` writes exactly `testStatus.size` bytes to `testStatus`) + assert(byteAfterTestStatus == testStatus + testStatus.size) + lda.b #WRITE_TEST_VALUE + sta.l testStatus + testStatus.size - 1 + sta.l byteAfterTestStatus + + + // Setup MDMA + // Copy 1 byte to Work RAM + + ldy.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (WMDATA << 8) + sty.w DMAP{mChannel} // also sets BBAD + + ldx.w #SuccessByte + stx.w A1T{mChannel} + stz.w A1B{mChannel} + + ldy.w #1 + sty.w DAS{mChannel} + + + jsr WaitUntilVBlank + + jsr SetupHdma + + + // Setup IRQ + stz.w NMITIMEN + cli + + ldy.w #{irqXpos} + sty.w HTIME + + lda.b #NMITIMEN.hCounter + sta.w NMITIMEN + + + ldy.w #testStatus.size - 1 + + Loop: + // Y = number of tests to process + + wai + + // Do not do the test if we are in VBlank + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bmi Loop + + + // Disable HDMA + // (Confirm the bug still happens if HDMA is disabled) + stz.w HDMAEN + + + lda.b #1 + sta.w DAS{mChannel}L + + lda.b #MDMAEN.dma{mChannel} + sta.w MDMAEN + + + // Check if the MDMAEN failed + ldx.w DAS{mChannel}L + beq + + if {defined try_mdma_again} { + // Do a second attempt at a MDMA transfer + sta.w MDMAEN + + // Check if the second MDMA failed + ldx.w DAS{mChannel}L + beq + + } + + lda.b #FAILURE_TILE_ID + sta.w WMDATA + + incrementErrorCount() + + + + + // Reenable HDMA + lda.b #HDMAEN.dma{hChannel} + sta.w HDMAEN + + + dey + bpl Loop + + + // Diable IRQ + stz.w NMITIMEN + sei + + + // Confirm the last byte in `testStatus` was written to + lda.l testStatus + testStatus.size - 1 + cmp.b #WRITE_TEST_VALUE + beq Fail + + // Confirm `WMDATA` did not write to the byte after `testStatus` + lda.l byteAfterTestStatus + cmp.b #WRITE_TEST_VALUE + bne Fail + + + rts + + +Fail: + brk #0 +} + + + +a8() +i16() +code() +function ShowTestResults { + + jsr WaitUntilVBlank + + stz.w HDMAEN + + lda.b #INIDISP.force | 15 + sta.w INIDISP + + + // Copy testStatus data to BG1 MAP + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + + + ldy.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + sty.w DMAP0 // also sets BBAD0 + + ldx.w #testStatus + stx.w A1T0 + lda.b #testStatus >> 16 + sta.w A1B0 + + ldy.w #testStatus.size + sty.w DAS0 + +- + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // Retry DMA if it failed + ldy.w DAS0 + bne - + + + jsr SetupHdma + + + lda.b #15 + sta.w INIDISP + + rts +} + + + +au() +iu() +code() +function WaitUntilVBlank { + php + sep #$30 +a8() +i8() + + // Wait until VBlank + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + Loop: + wai + + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bpl Loop + + stz.w NMITIMEN + + plp + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + jsr SetupPpu + + + ldx.w #0 + stx.b errorCount + + + TestLoop: + jsr DoTest + + jsr ShowTestResults + + ldx.b errorCount + beq TestLoop + + + // We encountered a bad DMA transfer + // Disable HDMA and stop testing. + stz.w HDMAEN +- + bra - +} + + + +PaletteData: + dw ToPalette(24, 24, 15) + dw ToPalette( 0, 15, 0) + dw ToPalette(31, 0, 0) + dw ToPalette( 8, 8, 8) + +constant PaletteData.size = pc() - PaletteData + + +TileData: +// Blank tile + fill 16, 0 + +// Success tile + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %00000001 + db %11111111, %11111111 + +// Failure tile + db %00000000, %11111111 + db %01000010, %11111111 + db %00100100, %11111111 + db %00011000, %11111111 + db %00011000, %11111111 + db %00100100, %11111111 + db %01000010, %11111111 + db %00000000, %11111111 + +constant TileData.size = pc() - TileData +assert(TileData.size == 16 * 3) + +constant SUCCESS_TILE_ID = 1 +constant FAILURE_TILE_ID = 2 + + +SuccessByte: + db SUCCESS_TILE_ID + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-1.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-1.asm new file mode 100644 index 00000000..13df7e46 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-1.asm @@ -0,0 +1,58 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table occasionally triggers the bug +// (between 1 to 3 DMA failures per 896 tests) +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-2.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-2.asm new file mode 100644 index 00000000..11bb9c3f --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-2.asm @@ -0,0 +1,57 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table triggers the bug the most often (every 4th scanline) +HdmaTable: + variable n = 0 + while n < 128 { + db 2 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-3.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-3.asm new file mode 100644 index 00000000..16583cda --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-3.asm @@ -0,0 +1,57 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table triggers the bug every 3rd, 6th or 9th scanline +HdmaTable: + variable n = 0 + while n < 128 { + db 3 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-5.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-5.asm new file mode 100644 index 00000000..58cbb7b3 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-5.asm @@ -0,0 +1,57 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table triggers the bug every 5th or 10th scanline +HdmaTable: + variable n = 0 + while n < 128 { + db 5 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-ch0.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-ch0.asm new file mode 100644 index 00000000..ff41b905 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-ch0.asm @@ -0,0 +1,58 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +// I can also trigger this bug with MDMA ch 5, HDMA ch 0 +define mChannel = 5 +define hChannel = 0 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table triggers the bug the most often (every 4th scanline) +HdmaTable: + variable n = 0 + while n < 128 { + db 2 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix.asm new file mode 100644 index 00000000..ac20e7cd --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix.asm @@ -0,0 +1,61 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + +// Using HDMA to transfer two bytes to 0x21ff & 0x2100 +// (BBAD is not 0x00 and the bug is no-longer triggered) +evaluate hdma_dmap = 0x01 // DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.two +evaluate hdma_bbad = 0xff + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +HdmaTable: + variable n = 0 + while n < 128 { + db 2 + db 0 ; sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix2.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix2.asm new file mode 100644 index 00000000..b40b1abc --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-fix2.asm @@ -0,0 +1,59 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + +// If a DMA transfer fails, retry it once before marking it red. +define try_mdma_again = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +HdmaTable: + variable n = 0 + while n < 128 { + db 2 + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-r2.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-r2.asm new file mode 100644 index 00000000..67a20f94 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-r2.asm @@ -0,0 +1,60 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table occasionally triggers the bug +// (between 1 to 3 DMA failures per 896 tests) +HdmaTable: + variable n = 0 + while n < 128 { + // repeat mode, 2 lines + db $80 | 2 + sv() + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-strange.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-strange.asm new file mode 100644 index 00000000..0a9f00a9 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-strange.asm @@ -0,0 +1,69 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// For some strange reason this HDMA table does not appear trigger the bug +// on my 2/1/3 3-Chip Super Famicom console. +// +// This table did not trigger on my console after running this test for +// over 3 hours. +// +// Limited testing has shown that I am unable to trigger the bug in HDMA +// repeat mode with a line count >= 3. +// +// I have no idea if this behaviour is specific to my console or not. +HdmaTable: + variable n = 0 + while n < 256 { + // repeat mode, 3 lines + db $80 | 3 + sv() + sv() + sv() + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-two-regs.asm b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-two-regs.asm new file mode 100644 index 00000000..303be98b --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/scpu-a-dma-bug/scpu-a-dma-bug-two-regs.asm @@ -0,0 +1,61 @@ +// S-CPU-A hardware DMA bug test +// ============================= +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define mChannel = 0 +define hChannel = 1 + +// Use HDMA to transfer two bytes to 0x2100 & 0x2101 +evaluate hdma_dmap = 0x01 // DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.two +evaluate hdma_bbad = 0x00 + + +include "dma-test.inc" + + +variable sv_counter = 0 +macro sv() { + db sv_counter ? 15 : 8 + + sv_counter = !sv_counter +} + + +// This HDMA table triggers the bug the most often (every 4th scanline) +HdmaTable: + variable n = 0 + while n < 128 { + db 2 + sv() ; db 1 + + n = n + 1 + } + + db 0 + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-mode7ex.asm b/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-mode7ex.asm new file mode 100644 index 00000000..1469b663 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-mode7ex.asm @@ -0,0 +1,197 @@ +// Tests if the `SETINI` (`$2133`) register reads the data-bus too early. +// +// This tests constantly writes the value `0x40` to `SETINI` (enable Mode 7 +// EXTBG) while the previous value on the data-bus is `0x00`. +// +// Mode 7 EXTBG only uses 7 bits for the tile colour data. This means a mode 7 +// tile with a data value of `0x81` will use colour 1 in EXTBG mode or colour +// 129 in non-EXTBG mode. Secondly, Mode 7 EXTBG is only available on Mode 7 +// BG2 which is disabled if bit 6 of `SETINI` is clear. +// +// +// TEST OUTPUT: +// * If the PPU reads the register at the correct time then the console will +// only output a light green background. +// +// * If the PPU reads the register early then the console will output a light +// green background with either red or blue dots. +// * a red dot means BG2 is disabled. +// * a blue dot mean BG2 is enabled and the PPU is erroneously rendering an +// 8 bit mode 7 tile. +// +// You may need to reset your console a dozen times for the glitch to appear. +// +// The glitch appears ~20% of the time on both my 3-Chip 2/1/3 SFC console and +// my 1-Chip SFC console. +// +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "SETINI EARLY RD M7EX" +define VERSION = 1 +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +// Setup and initialize the PPU +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupPpu() { + assert8a() + assert16i() + + stz.w HDMAEN + stz.w NMITIMEN + + + // Set PPU registers + + // Disable the display + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + // Mode 7 + lda.b #7 + sta.w BGMODE + + // Mode 7 EXTBG mode uses BG 2 + lda.b #TM.bg2 + sta.w TM + + + // Reset Mode 7 Matrix + lda.b #1 + // M7A = 1 + stz.w M7A + sta.w M7A + // M7B = 0 + stz.w M7B + stz.w M7B + // M7C = 0 + stz.w M7C + stz.w M7C + // M7D = 1 + stz.w M7D + sta.w M7D + + // M7X = 0 + stz.w M7X + stz.w M7X + + // M7Y = 0 + stz.w M7Y + stz.w M7Y + + + + // Load palette + stz.w CGADD + Dma.ForceBlank.ToCgram(Palette) + + + // Load tile data to VRAM + ldx.w #0 + stx.w VMADD + Dma.ForceBlank.ToVramH(Mode7Tile) + + + // Enable display + lda.b #0x0f + sta.w INIDISP +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + + // Hammer the SETINI register, enabling Mode7 EXTBG while the previous value on the data bus is 0 + + // Check if it is safe to write to the register before SETINI + assert(SETINI - 1 == COLDATA) + + ldx.w #(SETINI.extbg) << 8 | (0x00) + + MainLoop: + stx.w SETINI - 1 + + bra MainLoop +} + + + +Mode7Tile: + fill 8*8, 0x81 +constant Mode7Tile.size = pc() - Mode7Tile + + +Palette: + variable n = 0 + while n < 256 { + if n == 0 { + // Invalid - red + dw ToPalette(31, 0, 0) + } else if n == 1 { + // Valid - light green + dw ToPalette(15, 31, 15) + } else { + // Invalid - blue + dw ToPalette(0, 0, 31) + } + + n = n + 1 + } +constant Palette.size = pc() - Palette + + diff --git a/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-obj.asm b/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-obj.asm new file mode 100644 index 00000000..90bccd3a --- /dev/null +++ b/roms/snes-test-roms/src/hardware-glitch-tests/setini-early-read-obj.asm @@ -0,0 +1,232 @@ +// Tests if the `SETINI` (`$2133`) register reads the data bus too early. +// +// This test uses HDMA to write `0x02` to COLDATA ($2132) immediately followed +// by a write of `0x00` to `SETINI` ($2133). If the SETINI register reads the +// data bus too early then the previous value on the data-bus (`0x02`) will +// briefly activate the "OBJ Interlace" flag and the PPU will output glitched +// sprite tiles. +// +// You may need to reset your console a few times for the glitch to appear. +// +// The sprite glitch appears ~60% of the time on my 3-chip 2/1/3 SFC console and +// ~30% of the time on my 1-chip SFC console. +// +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "SETINI EARLY RD OBJI" +define VERSION = 1 +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// BG2-4 uses WADDR 0 +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +// Setup and initialize the PPU +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// MODIFIES: enables force-blank +macro SetupPpu() { + assert8a() + assert16i() + + stz.w NMITIMEN + + + // Set PPU registers + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #1 + sta.w BGMODE + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + // BG2-BG4 have a TILE & MAP WADDR of 0 (as set by ResetRegisters) + + lda.b #OBSEL.size.s32_64 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #TM.bg1 | TM.obj + sta.w TM + + + // Load OBJ palette + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Reset OAM hi table + ldx.w #0x0100 + stx.w OAMADD + + lda.b #0 + sta.w OAMDATA + sta.w OAMDATA + + + + // Transfer tiles and map to VRAM + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_4bpp) + + + // Transfer palette to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette_4bpp) +} + + + +// Setup HDMA transfer +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +macro SetupHdma() { + assert8a() + assert16i() + + + stz.w HDMAEN + + + lda.b #DMAP.direction.toPpu | DMAP.addressing.absolute | DMAP.transfer.two + sta.w DMAP0 + + assert(COLDATA + 1 == SETINI) + lda.b #COLDATA + sta.w BBAD0 + + ldx.w #HdmaTable + stx.w A1T0 + + lda.b #HdmaTable >> 16 + sta.w A1B0 + + + lda.b #HDMAEN.dma0 + sta.w HDMAEN +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + sei + + SetupPpu() + + SetupHdma() + + + lda.b #0xf + sta.w INIDISP + + + MainLoop: + bra MainLoop +} + + + +namespace Resources { + insert Bg1_Tilemap, "../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.tiles" + insert Palette_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.pal" + + insert Obj_Tiles, "../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../gen/example-backgrounds/obj-oam.bin" +} + + + +HdmaTable: + variable n = 0 + while n < 256 { + db 1 + // COLDATA + // (corrupts sprite tiles if data-bus is read early) + db SETINI.objInterlace + + // SETINI + db 0 + + n = n + 1 + } + db 0 + + diff --git a/roms/snes-test-roms/src/hardware-tests/audio/ipl-speed-test.asm b/roms/snes-test-roms/src/hardware-tests/audio/ipl-speed-test.asm new file mode 100644 index 00000000..8e09c693 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/audio/ipl-speed-test.asm @@ -0,0 +1,365 @@ +// IPL speed test +// +// Test ROM that transfers 32678 bytes of data to Audio-RAM using the S-SMP IPL +// and prints the number of frames it took to make the transfer. +// +// SPDX-FileCopyrightText: © 2025 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2025 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "IPL SPEED TEST" +define VERSION = 1 +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createDataBlock(rodata0, 0x818000, 0x81ffff) +createDataBlock(rodata1, 0x828000, 0x82ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(stack, 0x7e0100, 0x7e01ff) +createRamBlock(lowram, 0x7e0200, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant TRANSFER_SIZE = 32 * 1024 + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + + +// zero-page temporary variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) +allocate(zpTmpPtr, zeropage, 3) + + +// Incremented every VBlank +allocate(frameCounter, zeropage, 1) + + +allocate(testCounter, zeropage, 1) + +allocate(test_startFrameCounter, zeropage, 1) +allocate(test_nVBlanks, zeropage, 1) + +allocate(data_farAddr, zeropage, 3) +allocate(data_remainingBytes, zeropage, 2) + + +// Minimal NMI ISR that also increments a frame counter +au() +iu() +// DB = 0x80 +function NmiHandler { + sep #$20 +a8() + inc.w frameCounter + + rti +} + + +// Initialise the IPL +a8() +i16() +// DB = 0x80 +function TestSetup { + // Clear start command port (just in case APUIO0 has $cc in it) + // SOURCE: `blarggapu.s` from lorom-template, originally written by blargg (Shay Green) + stz.w APUIO0 + + // Wait for ready signal + ldx.w #0xbbaa + - + cpx.w APUIO0 + bne - + + rts +} + + + +// OUT: test_nVBlanks = number of VBlanks during the transfer +a8() +i16() +// DB = 0x80 +function MeasureIpl { + rep #$30 + sep #$20 +a8() +i16() + + lda.b frameCounter + sta.b test_startFrameCounter + + + ldx.w #DataToTransfer + lda.b #DataToTransfer >> 16 + stx.b data_farAddr + sta.b data_farAddr + 2 + + ldx.w #DataToTransfer.size + stx.b data_remainingBytes + + + // Set destination ARAM address ($0200) + stz.w APUIO2 + lda.b #0x02 + sta.w APUIO3 + + // Send a new data command + // + // The first data command must use 0xcc. + // The rest of the data commands MUST be non-zero and be at least 2 larger than APUIO0. + // + // From the snesdev wiki + // https://snes.nesdev.org/wiki/Booting_the_SPC700#Writing_to_a_different_address + lda.w APUIO0 + clc + adc.b #$22 + bne + + inc + + + sta.w APUIO1 + sta.w APUIO0 + + // Wait for a response from the IPL + - + cmp.w APUIO0 + bne - + + sep #$30 +a8() +i8() + jsr _IplWriteLoop + + + rep #$30 + sep #$20 +a8() +i16() + + lda.b frameCounter + sec + sbc.b test_startFrameCounter + sta.b test_nVBlanks + + rts +} + + +// Optimised IPL writing loop +// +// This function uses DP indirect-long addressing to read the data to match what a game might do. +// +// Moved to a separate function so it can be profiled with Mesen +a8() +i8() +function _IplWriteLoop { + ldx.b #0 + + lda [data_farAddr] + + Loop: + // Send the next byte to the IPL + sta.w APUIO1 + + // Tell the IPL the next byte is ready + stx.w APUIO0 + + rep #$20 + a16() + inc.b data_farAddr + dec.b data_remainingBytes + beq Break + + sep #$20 + a8() + // Read next byte + lda [data_farAddr] + + txy + + inx + + // Wait for a response form the IPL + - + cpy.w APUIO0 + bne - + + bra Loop + +Break: + + sep #$20 +a8() + + // Wait for a response form the IPL + - + cpx.w APUIO0 + bne - + + rts +} + + + +// REQUIRED: Force-Blank +a8() +i16() +// DB = 0x80 +function SetupPpu_ForceBlank { + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Palette) + + jsr TextBuffer.InitAndTransferToVram + + rts +} + + +a8() +i16() +// DB = 0x80 +function Main { + jsr SetupPpu_ForceBlank + + evaluate TS = TRANSFER_SIZE + TextBuffer.PrintStringLiteral("Transferring {TS} bytes\nusing the IPL\n\n") + + TextBuffer.PrintStringLiteral(" # VBlanks Spinloop count") + + lda.b #15 + sta.w INIDISP + + + // Clear NMI flag + lda.w RDNMI + // Enable NMI + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + + + jsr TestSetup + + MainLoop: + wai + TextBuffer.VBlank() + + // Wait until start of VBlank + // to make the test output consistent + wai + + jsr MeasureIpl + + // Spinloop to the next VBlank + ldx.w #0 + lda.b frameCounter + - + inx + cmp.b frameCounter + beq - + phx + + // Output test results + + TextBuffer.PrintStringLiteral("\n ") + + inc.b testCounter + + lda.b testCounter + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.PrintStringLiteral(" 0x") + + lda.b test_nVBlanks + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.PrintStringLiteral(" 0x") + + ply + jsr TextBuffer.PrintHexSpace_16Y + + + ldx.w TextBuffer.cursorIndex + cpx.w #25 * 32 + bcc + + TextBuffer.SetCursor(0, 3) + + + + jmp MainLoop +} + + +rodata(rodata0) +Palette: + // BG1 palette + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) + +constant Palette.size = pc() - Palette + + +rodata(rodata1) +DataToTransfer: + variable _i = 0 + while _i < 256 { + fill 128, _i + _i = _i + 1 + } +constant DataToTransfer.size = pc() - DataToTransfer + +assert(DataToTransfer.size == TRANSFER_SIZE) + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/_modify-autojoy-during-autojoy.inc b/roms/snes-test-roms/src/hardware-tests/auto-joypad/_modify-autojoy-during-autojoy.inc new file mode 100644 index 00000000..6be5883c --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/_modify-autojoy-during-autojoy.inc @@ -0,0 +1,418 @@ +// Modify auto joypad enable flag during auto-joypad read tests. +// +// These tests uses IRQ to modify auto-joypad read (NMITIMEN.bit0) or joypad-latch (write +// JOYSER0.bit0) while automatic joypad read is normally active at various H/V positions and prints: +// * How many times the auto-joy flag is 1 +// * The output of the JOY1 register after auto-joypad read +// * The output of manually reading the JOYSER0 joypad register 16 times +// +// Be aware, the VTIME/HTIME is the time of the IRQ interrupt, it is not the position of the +// NMITIMEN/JOYSER0 write. +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define TEST_INSTRUCTIONS = "Press and hold a\nJoypad 1 button" + +define USES_IRQ_INTERRUPTS + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + + +constant TB_TEST_Y = 11 + +constant TB_TEST_X_TIME = 1 +constant TB_TEST_X_DATA = 12 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +allocate(testIndex, zeropage, 2) + +allocate(tmpCounter, zeropage, 2) + +allocate(manualRead, zeropage, 2) + + +rodata(rodata0) +TestData: +namespace TestData { + constant VTime = TestData; + constant HTime = TestData + 2; + constant YPos = TestData + 4; + + constant BYTES_PER_ROW = 6 + constant END_INDEX = N_TESTS * BYTES_PER_ROW + + variable _i = 0 + while _i < N_TESTS { + dw vtime[_i], htime[_i], TB_TEST_Y + _i + + _i = _i + 1 + } + + assert(pc() == TestData + END_INDEX) +} + + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + TextBuffer.SetCursor(TB_TEST_X_DATA - 1, TB_TEST_Y - 3) + TextBuffer.PrintStringLiteral("HVBJOY MANUAL") + + TextBuffer.SetCursor(TB_TEST_X_DATA - 1, TB_TEST_Y - 2) + TextBuffer.PrintStringLiteral("COUNT JOY1 READ") + + TextBuffer.SetCursor(TB_TEST_X_TIME + 3, TB_TEST_Y - 3) + TextBuffer.PrintStringLiteral("IRQ") + TextBuffer.SetCursor(TB_TEST_X_TIME + 1, TB_TEST_Y - 2) + TextBuffer.PrintStringLiteral("VT HT") + + ldx.w #0 + - + stx.b testIndex + + lda.w TestData.YPos,x + tay + ldx.w #TB_TEST_X_TIME + jsr TextBuffer.SetCursor + + ldx.b testIndex + ldy.w TestData.VTime,x + jsr TextBuffer.PrintHexSpace_16Y + + ldx.b testIndex + ldy.w TestData.HTime,x + jsr TextBuffer.PrintHexSpace_16Y + + assert(TestData.END_INDEX < 0xff) + tdc + lda.b testIndex + clc + adc.b #TestData.BYTES_PER_ROW + tax + cmp.b #TestData.END_INDEX + bne - + + rts +} + + + +// IN: X = testIndex +// DB = 0x80 +// D = 0 +a8() +i16() +code() +function DoTest { + // MUST Update this constant if the test changes + constant TEST_VERSION = 3 + + phd + pea $4200 + pld +// D = $4200 + + + // Use IRQ to wait until a fixed frame position + // TO ensure the HVBJOY loop starts at a consistent-ish frame time. + + stz.b NMITIMEN + + sei + + assert(pc() >> 16 == TestData >> 16) + ldy.w #0 + sty.b HTIME + + ldy.w #210 + sty.b VTIME + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter + bit.b TIMEUP // clear IRQ flag + sta.b NMITIMEN + + // Enable The first IRQ interrupt + lda.b #0 + cli + wai + + + // Disable IRQ interrupts + sei + stz.b NMITIMEN + + + + // Initialise joypad latch + assert(JOYSER_LATCH_START_VALUE & 1 == JOYSER_LATCH_START_VALUE) + lda.b #JOYSER_LATCH_START_VALUE + sta.w JOYSER0 + + + // Setup autojoy enable flag and enable interrupts + ldx.w testIndex + + assert(pc() >> 16 == TestData >> 16) + ldy.w TestData.HTime,x + sty.b HTIME + + ldy.w TestData.VTime,x + sty.b VTIME + + assert(AUTO_JOY_ENABLED_BEFORE_IRQ & 1 == AUTO_JOY_ENABLED_BEFORE_IRQ) + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter | (AUTO_JOY_ENABLED_BEFORE_IRQ & 1) + bit.b TIMEUP // clear IRQ flag + sta.b NMITIMEN + + + // While the IRQ is pending, read the auto-joy status flag a few hundred times + // to see if auto-joy is active. + // + // The IRQ will clear the NMITIMEN in the middle of this loop + + // Count number of times S-CPU reports autoJoy active + // + // X = loop decrementing counter + // Y = HVBJOY.autoJoy counter + // A = NMITIMEN.autoJoy + ldx.w #600 + ldy.w #0 + lda.b #HVBJOY.autoJoy + + // Enable The second IRQ interrupt + cli + + - + bit.b HVBJOY + beq + + iny + + + dex + bne - + + + pld +// D = 0 + + sty.b tmpCounter + + + // Read 16 bits from JOYSER0 + // Manual reading code from the SNESDEV wiki + // https://snes.nesdev.org/wiki/Controller_reading#Manual_controller_reading + lda.b #1 + sta.b manualRead + stz.b manualRead + 1 + - + lda.w JOYSER0 + lsr + rol.b manualRead + rol.b manualRead + 1 + bcc - + + + // Update text buffer + ldx.w testIndex + ldy.w TestData.YPos,x + ldx.w #TB_TEST_X_DATA + jsr TextBuffer.SetCursor + + ldy.b tmpCounter + jsr TextBuffer.PrintHexSpace_16Y + + ldy.w JOY1 + jsr TextBuffer.PrintHexSpace_16Y + + ldy.b manualRead + jsr TextBuffer.PrintHexSpace_16Y + + + // Transfer text buffer to VRAM + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + + rts +} + + +// IRQ ISR. +// +// Invoked twice per test: +// * on the first IRQ of the test: A = 0 +// * on the second IRQ of the test: A = NMITIMEN.autoJoy +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +a8() +iu() +code() +function IrqHandler { + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + assert(NMITIMEN.autoJoy == JOYSER0.latch) + + IrqCode() + + // Clear IRQ flag + bit.b TIMEUP + + rti +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + a16() + i16() + lda.b testIndex + clc + adc.w #TestData.BYTES_PER_ROW + cmp.w #TestData.END_INDEX + bcc + + lda.w #0 + + + sta.b testIndex + tax + + sep #$20 + a8() + jsr DoTest + + bra MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = DoTest.TEST_VERSION +evaluate DATA_VERSION = TestData.DATA_VERSION + db "\n", {TEST_NAME}, "\nversion {TEST_VERSION}-{DATA_VERSION}", "\n\n", {TEST_INSTRUCTIONS}, 0 + +assert({VERSION} == {TEST_VERSION} + {DATA_VERSION} + IrqHandler.IRQ_VERSION - 2) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/auto-joy-timing-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/auto-joy-timing-test.asm new file mode 100644 index 00000000..ff47938a --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/auto-joy-timing-test.asm @@ -0,0 +1,328 @@ +// Auto joypad read timing test +// +// This test is used to help determine the H-Time that the +// HVBJOY auto-joy read flag is set and cleared. +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "AUTOJOY TIMING TEST" +define VERSION = 0 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +constant TB_STATE_WIDTH = 3 * 5 - 1 +constant TB_LABEL_WIDTH = 8 + +constant TB_LABEL_X = (TextBuffer.N_TEXT_COLUMNS - TB_STATE_WIDTH - TB_LABEL_WIDTH)/2 +constant TB_STATE_X = TB_LABEL_X + TB_LABEL_WIDTH +constant TB_START_STATE_Y = 12 +constant TB_END_STATE_Y = TB_START_STATE_Y + 2 + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +namespace state { + struct() + field(current, 2) + field(min, 2) + field(max, 2) + endstruct() +} + +// State values for the auto-read start test and the auto-read end test. +// +// NOTE: These values are the OPHCT values after the test has completed. +// +// Not storing these in zeropage as I use a non-zero DP in `DoTest`. +allocate(autoJoyStart, lowram, state.size) +allocate(autoJoyEnd, lowram, state.size) + + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.PrintString(TitleAndVersionStr) + + TextBuffer.SetCursor(TB_STATE_X, TB_START_STATE_Y - 4) + TextBuffer.PrintStringLiteral("OPHCT after test") + + TextBuffer.SetCursor(TB_STATE_X, TB_START_STATE_Y - 2) + TextBuffer.PrintStringLiteral("cur min max") + + TextBuffer.SetCursor(TB_LABEL_X, TB_START_STATE_Y) + TextBuffer.PrintStringLiteral("start") + + TextBuffer.SetCursor(TB_LABEL_X, TB_END_STATE_Y) + TextBuffer.PrintStringLiteral("end") + + lda.b #NMITIMEN.autoJoy + sta.w NMITIMEN + + + // Reset state + ldx.w #0xffff + stx.w autoJoyStart + state.min + stx.w autoJoyEnd + state.min + + ldx.w #0 + stx.w autoJoyStart + state.max + stx.w autoJoyEnd + state.max + + rts +} + + + +// DB = 0x80 +a8() +i16() +code() +function DoTest { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + sep #$30 +a8() +i8() + // Wait until we are at scanline 200 (well before autojoy starts) + - + assert8i() + ldx.w SLHV + + ldx.w OPVCT + ldy.w OPVCT + + assert(OPVCT.max & 0xff < 200) + cpx.b #200 + bne - + + rep #$10 +i16() + + // Set DP to to save a cycle reading HVBJOY registers + assert(HVBJOY & 0xff00 == 0x4200) + pea 0x4200 + pld +// DP = 0x4200 + + // Using a macro to ensure the set and clear tests are the same + macro _autoJoyTest(branch, stateVar) { + // Loop until autojoy starts + lda.b #HVBJOY.autoJoy + _Loop_{stateVar}: + bit.b HVBJOY + {branch} _Loop_{stateVar} + + // Read h-time from PPU + lda.w SLHV + + lda.w OPHCT + sta.w {stateVar} + state.current + + lda.w OPHCT + sta.w {stateVar} + state.current + 1 + } + + _autoJoyTest(beq, autoJoyStart) + _autoJoyTest(bne, autoJoyEnd) + + // Restore DP + pea 0 + pld +// DP = 0 + + rts +} + + + +// DB = 0x80 +au() +i16() +code() +function ProcessState { + // Update the test buffer + TextBuffer.SetCursor(TB_STATE_X, TB_START_STATE_Y) + ldx.w #autoJoyStart + jsr UpdateAndPrintState + + TextBuffer.SetCursor(TB_STATE_X, TB_END_STATE_Y) + ldx.w #autoJoyEnd + jsr UpdateAndPrintState + + rts +} + + + +// DB = 0x80 +a8() +i16() +code() +// INPUT: X = state struct address +function UpdateAndPrintState { + allocate(currentStateIndex, zeropage, 2) + + stx.b currentStateIndex + + rep #$30 +a16() + // Update state + lda.b state.current,x + and.w #OPHCT.mask + sta.b state.current,x + + cmp.b state.min,x + bcs + + sta.b state.min,x + + + + cmp.b state.max,x + bcc + + sta.b state.max,x + + + + sep #$20 +a8() + + ldy.b state.current,x + jsr TextBuffer.PrintHexSpace_16Y + + ldx.b currentStateIndex + ldy.b state.min,x + jsr TextBuffer.PrintHexSpace_16Y + + ldx.b currentStateIndex + ldy.b state.max,x + jsr TextBuffer.PrintHexSpace_16Y + + rts +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + MainLoop: + jsr DoTest + + // The PPU is still VBlank, update the text buffer + TextBuffer.VBlank() + + jsr ProcessState + + bra MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = DoTest.TEST_VERSION + db "\n", "HVBJOY autojoy timing test", "\n", "version {TEST_VERSION}", 0 + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.asm new file mode 100644 index 00000000..d455a85a --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.asm @@ -0,0 +1,342 @@ +// Blipping autojoy enable latches joypad twice test. +// +// This test is used to determine if blipping (0 -> 1 -> 0) the NMITIMEN auto-joypad enable flag +// during the first auto-joypad clock will: +// * Clear the joypad latch pin when NMITIMEN auto-joypad is disabled. +// * Latch the joypad a second time when NMITIMEN auto-joypad is re-enabled. +// +// This is done by: +// * Waiting until HVBJOY reports auto-joypad is active. +// * Clear the NMITIMEN auto-joypad flag. +// * Manually read the controller twice using JOYSER0. +// * Enable the NMITIMEN auto-joypad flag before the end first auto-joy clock +// (128 master-cycles after the HVBJOY auto-joypad active flag set). +// +// Two manual JOYSER0 reads are required to prove the joypad latch pin is cleared when NMITIMEN +// auto-joypad is disabled. +// +// Test results: +// * The first two bits are the manual read +// * The final 16 bits are the automatic-joypad read +// +// If automatic joypad read latches (strobes) the joypad a second time, the two manual reads +// should match the two most-significant bits of the auto-joy read and the auto-joy read should be +// uncorrupted. +// +// CAUTION: +// This test is unable to meet the timing window required for the test on every test iteration. +// +// I'm theorizing the joypad is not latched a second time if the `NMITIMEN = 1` write is too late. +// +// +// +// SPDX-FileCopyrightText: © 2025 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2025 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "BLIP AJ LATCHES JP" +define TEST_NAME = "Blipping AUTOJOY enable\nlatches joypad twice test" +define TEST_INSTRUCTIONS = "Hold B, then Y, then SELECT" +define VERSION = 1 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +constant TB_RESULTS_XPOS = 4 + +constant TB_RESULTS_YPOS = 9 +constant TB_RESULTS_MAX_YPOS = TB_RESULTS_YPOS + 15 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +// Used to print JOY1 bits +allocate(tmpWord, zeropage, 2) +allocate(tmpCounter, zeropage, 1) + + +// Test variables +allocate(testRow, zeropage, 2) + +allocate(firstRead, zeropage, 1) +allocate(secondRead, zeropage, 1) + + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + ldy.w #0xffff + sty.b testRow + + rts +} + + +function Test { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + phd + pea $4200 + pld +// D = $4200 + + sep #$30 +a8() +i8() + + stz.w JOYSER0 + + lda.b #NMITIMEN.autoJoy + +LoopUntilAutojoy: + // Enable autojoy + sta.w NMITIMEN + + // Wait until start of auto-joy + - + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq - + + + // TIMING: + // This test should complete 128 master-cycles after HVBJOY auto-joy active flag is set. + // There is not enough CPU time to meet this deadline on every test iteration. + // I'm guessing half of the test iterations meet the deadline. + +StartTest: // 12-m-cycles for `beq -` above not taken + // Disable auto-joy + stz.b NMITIMEN // 18 m-cycles + + // Manually read the joypad twice + ldx.w JOYSER0 // 30 m-cycles + ldy.w JOYSER0 // 30 m-cycles + + // Enable auto-joy + sta.b NMITIMEN // 18 m-cycles +TestOver: + + // Save results + stx.w firstRead + sty.w secondRead + + + // Wait until autojoy has finished + lda.b #HVBJOY.autoJoy + - + bit.b HVBJOY + bne - + + +PrintResults: + rep #$10 +i16() + pld +// D = 0 + + ldy.b testRow + cpy.w #TB_RESULTS_MAX_YPOS + bcc + + ldy.w #TB_RESULTS_YPOS - 1 + + + iny + sty.b testRow + + ldx.w #TB_RESULTS_XPOS + jsr TextBuffer.SetCursor + + + lda.b firstRead + lsr + jsr PrintBit + + lda.b secondRead + lsr + jsr PrintBit + + + TextBuffer.PrintStringLiteral(" ") + + ldx.w JOY1 + stx.b tmpWord + + lda.b #16 + sta.b tmpCounter + + - + asl.b tmpWord + rol.b tmpWord + 1 + jsr PrintBit + dec.b tmpCounter + bne - + + + // Transfer text buffer to VRAM + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + rts +} + + +BitString_0: + db "0", 0 + +BitString_1: + db "1", 0 + + +// IN: carry = bit +// +// DB = 0x80 +a8() +i16() +code() +function PrintBit { + assert(BitString_0 >> 16 == BitString_1 >> 16) + + lda.b #BitString_0 >> 16 + ldx.w #BitString_0 + bcc + + ldx.w #BitString_1 + + + jmp TextBuffer.PrintString +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + sep #$20 + a8() + i16() + + jsr Test + + jmp MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = Test.TEST_VERSION + db "\n", {TEST_NAME}, "\n\nversion {TEST_VERSION}\n\n", {TEST_INSTRUCTIONS}, 0 + +assert({VERSION} == {TEST_VERSION}) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test-automatic.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test-automatic.asm new file mode 100644 index 00000000..d6608287 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test-automatic.asm @@ -0,0 +1,378 @@ +// Automatic blip auto joypad enable flag test. +// +// This test ROM is designed to see what happens if auto-joypad is disabled, then +// quickly re-enabled shortly after auto-joypad read stats. +// +// For 19 different wait values this test: +// * Waits until auto-joypad active flag is set +// * Waits X fastROM cycles +// * Disables auto-joypad enable (NMITIMEN = 0) +// * Enables auto-joypad (NMITIMEN = 1) 18 or 58 m-cycles later +// * Reads HVBJOY.bit0 in a loop to see if the auto-joypad enable flag is set +// * Prints the results +// +// Test Results: +// * Min HVBJOY.0 counter: +// The minimum number of times HVBJOY.bit0 was read in the loop when HVBJOY.bit0 was 1 at least one. +// +// * Row 1: At least 1 read occurred in the column +// * Row 2: At least 1 no-read occurred in the column +// * Rows 3+: Raw Read/No-read data +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "AUTOJOY BLIP TEST A" +define TEST_NAME = "Automatic AUTOJOY blip test\n(1-0-1 to AUTOJOY enable)" +define VERSION = 1 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +constant TB_MIN_READ_COUNTER_XPOS = 22 +constant TB_MIN_READ_COUNTER_YPOS = 5 + +constant TB_TEST_START_X = 4 + +constant TB_ANY_READ_YPOS = 7 +constant TB_ANY_NO_READ_YPOS = 8 + +constant TB_RAW_DATA_YPOS = 10 +constant TB_RAW_DATA_LAST_YPOS = 25 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + +// minimum non-zero HVBJOY.0 loop counter +allocate(minNonZeroCounter, zeropage, 2) + + +// Current cursor position +allocate(cursorXPos, zeropage, 2) +allocate(cursorYPos, zeropage, 2) + + +allocate(tmpCounter, zeropage, 2) + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + TextBuffer.SetCursor(TB_MIN_READ_COUNTER_XPOS - 20, TB_MIN_READ_COUNTER_YPOS) + TextBuffer.PrintStringLiteral("Min HVBJOY.0 count:") + + ldx.w #0xffff + stx.b cursorYPos + + stx.b minNonZeroCounter + + + rts +} + + +// TIMING: VBlank +// IN: Y = HVBJOY count +// DB = 0x80 +// D unknown +a8() +i16() +code() +function PrintResults { + sty.b tmpCounter + + ldx.b cursorXPos + ldy.b cursorYPos + jsr TextBuffer.SetCursor + + ldy.b tmpCounter + beq + + TextBuffer.PrintStringLiteral("R") + + // Updated the any read line + ldx.b cursorXPos + ldy.w #TB_ANY_READ_YPOS + jsr TextBuffer.SetCursor + TextBuffer.PrintStringLiteral("R") + + bra ++ + + + TextBuffer.PrintStringLiteral("-") + + // Updated the any no read line + ldx.b cursorXPos + ldy.w #TB_ANY_NO_READ_YPOS + jsr TextBuffer.SetCursor + TextBuffer.PrintStringLiteral("-") + + + + ldy.b tmpCounter + beq + + cpy.b minNonZeroCounter + bcs + + sty.b minNonZeroCounter + + TextBuffer.SetCursor(TB_MIN_READ_COUNTER_XPOS, TB_MIN_READ_COUNTER_YPOS) + + ldy.b tmpCounter + jsr TextBuffer.PrintHexSpace_16Y + + + + + // Transfer text buffer to VRAM + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + inc.b cursorXPos + + rts +} + + +// DB = $80 +// D = 0 +macro Test(evaluate numberOfFastRomCycles) { + assert8a() + assert16i() + + // MUST Update this constant if the test changes + assert(TEST_VERSION == 1) + + phd + pea $4200 + pld +// D = $4200 + + // Enable autojoy + lda.b #NMITIMEN.autoJoy + sta.b NMITIMEN + + + // Setup read-loop registers + ldx.w #200 + ldy.w #0 + + + // Wait for the start of autojoy + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + - + bit.b HVBJOY + beq - + + + // Add fastROM cycles between autojoy-flag set and autojoy enable blip + variable _c = {numberOfFastRomCycles} + while _c > 0 { + if _c == 3 { + rep #0 + _c = _c - 3 + } else if _c >= 2 { + nop + _c = _c - 2 + } else { + error "invalid numberOfFastRomCycles: {numberOfFastRomCycles}" + _c = 0 + } + } + + // Disable then quickly enable auto-joy + stz.b NMITIMEN + sta.b NMITIMEN + + // Count number of times S-CPU reports autoJoy active + - + // X = loop decrementing counter + // Y = HVBJOY.autoJoy counter + // A = NMITIMEN.autoJoy + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq + + iny + + + dex + bne - + + pld +// D = $4200 + + jsr PrintResults +} + + +// IN: X = testIndex +// DB = 0x80 +// D = 0 +a8() +i16() +code() +function DoTest { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + ldy.w #TB_TEST_START_X + sty.w cursorXPos + + + // Update cursor position + ldy.w cursorYPos + cpy.w #TB_RAW_DATA_LAST_YPOS + bcc + + ldy.w #TB_RAW_DATA_YPOS - 1 + + + iny + sty.b cursorYPos + + + // Selected 19 tests per line as it is a prime number + Test(0) + + inc.b cursorXPos + + evaluate i = 20 + while {i} < 37 { + Test({i}) + evaluate i = {i} + 1 + } + + inc.b cursorXPos + + Test(42) + + + rts +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + sep #$20 + a8() + i16() + jsr DoTest + + bra MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = DoTest.TEST_VERSION + db "\n", {TEST_NAME}, "\nversion {TEST_VERSION}", 0 + +assert({VERSION} == {TEST_VERSION}) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test.asm new file mode 100644 index 00000000..43703783 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-test.asm @@ -0,0 +1,71 @@ +// Blip auto joypad enable shortly after autojoy starts +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "BLIP AUTOJOY TEST" + +define TEST_NAME = "AUTOJOY blip test\n(1-0-1 to AUTOJOY enable)" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 12 + + array[N_TESTS] vtime = 224, 225, 225, 225, 226, 226, 226, 226, 226, 226, 227, 228 + array[N_TESTS] htime = 200, 70, 80, 90, 0, 64, 128, 192, 256, 320, 20, 20 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode disables auto-joypad. +// * on the second IRQ of the test: A is set and IrqCode clears and then quickly sets the auto-joypad enable flag. +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + stz.b NMITIMEN + // A = NMITIMEN.autoJoy OR 0 + sta.b NMITIMEN +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-timing-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-timing-test.asm new file mode 100644 index 00000000..0400ccdb --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/blip-autojoy-timing-test.asm @@ -0,0 +1,353 @@ +// Test ROM that determines how long the NMITIMEN auto-joy enable could be +// cleared in the first auto-joy cycle. +// +// This test will: +// 1. Wait until HVBJOY reports automatic joypad read active +// 2. Disable auto-joy (NMITIMEN = 0) +// 2. Delay for N master cycles +// 3. Enable auto-joy (NMITIMEN = 1) +// 3. Repeatedly poll HVBJOY joypad read active flag +// 4. Print the number of times HVBJOY reported auto-joy active. +// A value of 0xff is invalid. +// +// +// SPDX-FileCopyrightText: © 2025 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2025 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "BLIP AUTOJOY TIMING" +define TEST_NAME = "Blip AUTOJOY enable flag\ntiming test" +define TEST_INSTRUCTIONS = "Let this run for a minute\nor three" +define VERSION = 1 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +constant TB_DELAY_XPOS = 4 +constant TB_RAW_XPOS = 14 +constant TB_MIN_XPOS = TB_RAW_XPOS + 4 +constant TB_MAX_XPOS = TB_MIN_XPOS + 4 + +constant TB_LABEL_YPOS = 11 +constant TB_DATA_YPOS = TB_LABEL_YPOS + 2 + + +constant TEST_DATA_VERSION = 1 +constant N_TESTS = 9 +array[N_TESTS] TestDelays = 0, 96, 128, 200, 202, 204, 206, 208, 210 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +allocate(dummyStore, zeropage, 2) + +allocate(tmpCounter, zeropage, 1) + +allocate(minCounters, zeropage, N_TESTS) +allocate(maxCounters, zeropage, N_TESTS) + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + + TextBuffer.SetCursor(TB_DELAY_XPOS, TB_LABEL_YPOS) + TextBuffer.PrintStringLiteral("Delay") + + evaluate _i = 0 + while {_i} < N_TESTS { + evaluate _delay = TestDelays[{_i}] + + TextBuffer.SetCursor(TB_DELAY_XPOS, TB_DATA_YPOS + {_i}) + TextBuffer.PrintStringLiteral("{_delay}") + + evaluate _i = {_i} + 1 + } + + + TextBuffer.SetCursor(TB_RAW_XPOS - 1, TB_LABEL_YPOS - 1) + TextBuffer.PrintStringLiteral("HVBJOY COUNT") + + TextBuffer.SetCursor(TB_RAW_XPOS - 1, TB_LABEL_YPOS) + TextBuffer.PrintStringLiteral("RAW MIN MAX") + + ldx.w #N_TESTS - 1 + - + lda.b #0xff + sta.b minCounters,x + stz.b maxCounters,x + dex + bpl - + + rts +} + + +// DB = $80 +// D = 0 +inline _GenerateTest(evaluate TestNumber, evaluate DelayUntilClear, evaluate TbYpos) { + function Test{TestNumber} { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + constant N_HVBJOY_TESTS = 31 + + assert({TestNumber} < N_TESTS) + constant _minCounter = minCounters + {TestNumber} + constant _maxCounter = maxCounters + {TestNumber} + + + phd + pea $4200 + pld + // D = $4200 + + // X = loop decrementing counter + // Y = HVBJOY.autoJoy counter + // A = NMITIMEN.autoJoy + ldx.w #600 + ldy.w #0 + lda.b #NMITIMEN.autoJoy + + + // Enable autojoy + sta.b NMITIMEN + + // Wait until start of auto-joy + LoopUntilAutojoy: + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq LoopUntilAutojoy + + ClearAutoJoyEnableFlag: + stz.b NMITIMEN + + + // Delay for `DelayUntilClear` between the `stz` and `sta` NMITIMEN + constant N_DELAY_LOOPS = {DelayUntilClear} / 32 + variable _i = {DelayUntilClear} + while _i != 0 { + assert(_i >= 0) + if _i % 32 == 0 { + sta.l dummyStore + _i = _i - 32 + } else if _i % 12 == 0 { + nop + _i = _i - 12 + } else if _i % 34 == 0 { + sty.w dummyStore + _i = _i - 34 + } else if _i >= 26 { + bit.w $0000 + _i = _i - 26 + } else if _i >= 18 { + bit.b RDMPYL + _i = _i - 18 + } else { + print _i, "\n" + error "Cannot add delay {DelayUntilClear}" + _i = 0 + } + } + + ReenableAutoJoy: + // A = NMITIMEN.autoJoy + sta.b NMITIMEN + + + PollHvbjoyLoop: + bit.b HVBJOY + beq + + iny + + + dex + bne PollHvbjoyLoop + + tya + + PrintResults: + pld + // D = 0 + + // A = number of times HVBJOY was read + sta.b tmpCounter + + cmp.b _minCounter + bcs + + sta.b _minCounter + + + + cmp.b _maxCounter + bcc + + sta.b _maxCounter + + + + TextBuffer.SetCursor(TB_RAW_XPOS, {TbYpos}) + lda.b tmpCounter + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.SetCursor(TB_MIN_XPOS, {TbYpos}) + lda.b _minCounter + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.SetCursor(TB_MAX_XPOS, {TbYpos}) + lda.b _maxCounter + jsr TextBuffer.PrintHexSpace_8A + + + // Transfer text buffer to VRAM + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + rts + } +} + + +variable _i = 0 +while _i < N_TESTS { + _GenerateTest(_i, TestDelays[_i], TB_DATA_YPOS + _i) + + _i = _i + 1 +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + sep #$20 + a8() + i16() + + evaluate _i = 0 + while {_i} < N_TESTS { + jsr Test{_i} + evaluate _i = {_i} + 1 + } + + jmp MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = Test1.TEST_VERSION +evaluate TEST_DATA_VERSION = TEST_DATA_VERSION + db "\n", {TEST_NAME}, "\n\nversion {TEST_VERSION}-{TEST_DATA_VERSION}\n\n", {TEST_INSTRUCTIONS}, 0 + +assert({VERSION} == {TEST_VERSION} + TEST_DATA_VERSION - 1) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.asm new file mode 100644 index 00000000..73b2b4fa --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.asm @@ -0,0 +1,70 @@ +// Clear auto joypad flag during the first VBlank scanline test +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "CLEAR AUTOJOY VB SL" + +define TEST_NAME = "Clear AUTOJOY on\nfirst VBlank scanline" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 15 + + array[N_TESTS] vtime = 0, 224, 224, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225 + array[N_TESTS] htime = 0, 308, 324, 0, 16, 32, 48, 64, 80, 96, 112, 144, 160, 176, 192 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables IRQ Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode disables auto-joypad. +// * on the second IRQ of the test: A is set and IrqCode disables auto-joypad. +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // Disable IRQ interrupts and auto-joypad reading + stz.b NMITIMEN +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.asm new file mode 100644 index 00000000..6330017e --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.asm @@ -0,0 +1,282 @@ +// This test tests what happens when the NMITIMEN autojoy enable flag +// is cleared shortly after HVBJOY reports autojoy active. +// +// After the autojoy-enable-flag is cleared, this test will manually +// read the joypad using JOYSER0 (without latching) and print the +// JOY1 register and JOYSER0 manual read. +// +// +// SPDX-FileCopyrightText: © 2025 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2025 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "CLR AUTOJOY AFTER AJ" +define TEST_NAME = "Clear autojoy after HVBJOY\nreports autojoy active test" +define TEST_INSTRUCTIONS = "Hold B on controller 1" +define VERSION = 1 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +constant TB_RESULTS_XPOS = 9 + +constant TB_RESULTS_YPOS = 10 +constant TB_RESULTS_MAX_YPOS = TB_RESULTS_YPOS + 14 + +constant TB_HEADING_YPOS = TB_RESULTS_YPOS - 2 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No VBlank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +// Test variables +allocate(testRow, zeropage, 2) +allocate(manualRead, zeropage, 2) + + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + TextBuffer.SetCursor(TB_RESULTS_XPOS, TB_HEADING_YPOS) + TextBuffer.PrintStringLiteral("JOY1 JOYSER0") + + ldy.w #0xffff + sty.b testRow + + rts +} + + +function Test { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + phd + pea $4200 + pld +// D = $4200 + + sep #$20 +a8() + + lda.b #NMITIMEN.autoJoy + + // Enable autojoy + sta.b NMITIMEN + + // Wait until start of auto-joy + - + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq - + + // Delay determined experimentally. + // + // On my 1-CHIP SFC: + // * 156 m-cycles = No `0008 1000` + // * 158 m-cycles = Occasionally outputs `0008 1000`, sometimes `0001 0001` + // * 160 m-cycles = Occasionally outputs `0008 1000`, lots of `0001 0001` + // * 162 m-cycles = Lots of `0001 0001`, I did not see any `0008 1000` + + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop + nop // 12 m-cycles + bit.w manualRead // 26 m-cycles + + + // Disable auto-joy + stz.b NMITIMEN + + + // Wait until autojoy normally ends + ldx.w #600 + - + dex + bne - + + pld +// D = 0 + + // Read 16 bits from JOYSER0 + // Manual reading code from the SNESDEV wiki + // https://snes.nesdev.org/wiki/Controller_reading#Manual_controller_reading + lda.b #1 + sta.b manualRead + stz.b manualRead + 1 + - + lda.w JOYSER0 + lsr + rol.b manualRead + rol.b manualRead + 1 + bcc - + + +PrintResults: + ldy.b testRow + cpy.w #TB_RESULTS_MAX_YPOS + bcc + + ldy.w #TB_RESULTS_YPOS - 1 + + + iny + sty.b testRow + + ldx.w #TB_RESULTS_XPOS + jsr TextBuffer.SetCursor + + ldy.w JOY1 + jsr TextBuffer.PrintHexSpace_16Y + + ldy.b manualRead + jsr TextBuffer.PrintHexSpace_16Y + + + // Transfer text buffer to VRAM + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + rts +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + sep #$20 + a8() + i16() + + jsr Test + + jmp MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = Test.TEST_VERSION + db "\n", {TEST_NAME}, "\n\nversion {TEST_VERSION}\n\n", {TEST_INSTRUCTIONS}, 0 + +assert({VERSION} == {TEST_VERSION}) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.asm new file mode 100644 index 00000000..2079427a --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.asm @@ -0,0 +1,70 @@ +// Clear auto joypad flag during auto-joypad read test (multiple scanlines) +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "CLEAR AUTOJOY TEST" + +define TEST_NAME = "Clear AUTOJOY during AUTOJOY" +define VERSION = 4 + +namespace TestData { + constant DATA_VERSION = 2 + + constant N_TESTS = 9 + + array[N_TESTS] vtime = 224, 225, 225, 226, 226, 227, 227, 228, 228 + array[N_TESTS] htime = 200, 20, 200, 20, 200, 20, 200, 20, 200 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables IRQ Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode disables auto-joypad. +// * on the second IRQ of the test: A is set and IrqCode disables auto-joypad. +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // Disable IRQ interrupts and auto-joypad reading + stz.b NMITIMEN +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-timing-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-timing-test.asm new file mode 100644 index 00000000..17c5bfbe --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/clear-autojoy-timing-test.asm @@ -0,0 +1,334 @@ +// Test ROM that determines when the HVBJOY auto-joy active flag is cleared +// when auto-joy is disabled in the middle of auto-joy. +// +// This test will: +// 1. Wait until HVBJOY reports automatic joypad read active +// 2. Delay for N master cycles using `sta long` instructions +// 3. Repeatedly poll HVBJOY until it reports auto-joy not active +// 4. Print the number of times HVBJOY reported auto-joy active. +// A value of 0xff is invalid. +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "CLR AUTOJOY TIMING" +define TEST_NAME = "Clear AUTOJOY enable flag\ntiming test" +define VERSION = 1 + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +constant TB_DELAY_XPOS = 4 +constant TB_RAW_XPOS = 14 +constant TB_MIN_XPOS = TB_RAW_XPOS + 4 +constant TB_MAX_XPOS = TB_MIN_XPOS + 4 + +constant TB_LABEL_YPOS = 8 +constant TB_DATA_YPOS = TB_LABEL_YPOS + 2 + + +constant TEST_DATA_VERSION = 1 +constant N_TESTS = 7 +array[N_TESTS] TestDelays = 0, 64, 128, 192, 256, 384, 512 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +allocate(dummyStore, zeropage, 1) + +allocate(tmpCounter, zeropage, 1) + +allocate(minCounters, zeropage, N_TESTS) +allocate(maxCounters, zeropage, N_TESTS) + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + + TextBuffer.SetCursor(TB_DELAY_XPOS, TB_LABEL_YPOS) + TextBuffer.PrintStringLiteral("Delay") + + evaluate _i = 0 + while {_i} < N_TESTS { + evaluate _delay = TestDelays[{_i}] + + TextBuffer.SetCursor(TB_DELAY_XPOS, TB_DATA_YPOS + {_i} * 2) + TextBuffer.PrintStringLiteral("{_delay}") + + evaluate _i = {_i} + 1 + } + + + TextBuffer.SetCursor(TB_RAW_XPOS - 1, TB_LABEL_YPOS - 1) + TextBuffer.PrintStringLiteral("HVBJOY polls") + + TextBuffer.SetCursor(TB_RAW_XPOS - 1, TB_LABEL_YPOS) + TextBuffer.PrintStringLiteral("RAW MIN MAX") + + ldx.w #N_TESTS - 1 + - + lda.b #0xff + sta.b minCounters,x + stz.b maxCounters,x + dex + bpl - + + rts +} + + +// DB = $80 +// D = 0 +inline _GenerateTest(evaluate TestNumber, evaluate DelayUntilClear, evaluate TbYpos) { + function Test{TestNumber} { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + constant N_HVBJOY_TESTS = 31 + + assert({TestNumber} < N_TESTS) + constant _minCounter = minCounters + {TestNumber} + constant _maxCounter = maxCounters + {TestNumber} + + + phd + pea $4200 + pld + // D = $4200 + + // Enable autojoy + lda.b #NMITIMEN.autoJoy + sta.b NMITIMEN + + // Wait until autojoy is active + LoopUntilAutojoy: + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq LoopUntilAutojoy + + + // Delay for `DelayUntilClear` master cycles + assert({DelayUntilClear} % 32 == 0) + constant N_DELAY_LOOPS = {DelayUntilClear} / 32 + evaluate _i = 0 + while {_i} < N_DELAY_LOOPS { + // 4 FastROM, 1 SlowROM cycle = 32 master cycles + sta.l dummyStore + evaluate _i = {_i} + 1 + } + + ClearAutoJoyEnableFlag: + stz.b NMITIMEN + + // 30 master cycles between HVBJOY polls (18 for `bit.b fast`, 12 for `beq` not taken) + // 70 master cycles if there is also a Work-RAM refresh + // -12 master cycles for `beq` of the last poll + // +12 master cycles for `beq LoopUntilAutojoy` branch above not taken + // +18 master cycles for `stz.b NMITIMEN` + evaluate _i = 1 + while {_i} <= N_HVBJOY_TESTS { + bit.b HVBJOY + beq InProgressFlagClear_{_i} + evaluate _i = {_i} + 1 + } + + lda.b #0xff + bra PrintResults + + evaluate _i = 1 + while {_i} <= N_HVBJOY_TESTS { + InProgressFlagClear_{_i}: + lda.b #{_i} + bra PrintResults + evaluate _i = {_i} + 1 + } + + PrintResults: + pld + // D = 0 + + // A = number of times HVBJOY was read + sta.b tmpCounter + + cmp.b _minCounter + bcs + + sta.b _minCounter + + + + cmp.b _maxCounter + bcc + + sta.b _maxCounter + + + + TextBuffer.SetCursor(TB_RAW_XPOS, {TbYpos}) + lda.b tmpCounter + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.SetCursor(TB_MIN_XPOS, {TbYpos}) + lda.b _minCounter + jsr TextBuffer.PrintHexSpace_8A + + TextBuffer.SetCursor(TB_MAX_XPOS, {TbYpos}) + lda.b _maxCounter + jsr TextBuffer.PrintHexSpace_8A + + + // Transfer text buffer to VRAM + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + rts + } +} + + +variable _i = 0 +while _i < N_TESTS { + _GenerateTest(_i, TestDelays[_i], TB_DATA_YPOS + _i * 2) + + _i = _i + 1 +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + sep #$20 + a8() + i16() + + evaluate _i = 0 + while {_i} < N_TESTS { + jsr Test{_i} + evaluate _i = {_i} + 1 + } + + jmp MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = Test1.TEST_VERSION +evaluate TEST_DATA_VERSION = TEST_DATA_VERSION + db "\n", {TEST_NAME}, "\n\nversion {TEST_VERSION}-{TEST_DATA_VERSION}", 0 + +assert({VERSION} == {TEST_VERSION} + TEST_DATA_VERSION - 1) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test-2.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test-2.asm new file mode 100644 index 00000000..36d71643 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test-2.asm @@ -0,0 +1,69 @@ +// Enable auto joypad late using IRQ test +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +define ROM_NAME = "EN AUTOJOY LATE 2" + +define TEST_NAME = "Enable AUTOJOY late test 2" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 15 + + array[N_TESTS] vtime = 0, 224, 224, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225, 225 + array[N_TESTS] htime = 0, 308, 324, 0, 16, 32, 48, 64, 80, 96, 112, 144, 160, 176, 192 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 0 + + +// Disables Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode disables auto-joypad. +// * on the second IRQ of the test: A is set and IrqCode enables auto-joypad. +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // A = NMITIMEN.autoJoy OR 0 + sta.b NMITIMEN +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test.asm new file mode 100644 index 00000000..4df5d604 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/enable-autojoy-late-test.asm @@ -0,0 +1,367 @@ +// Enable auto joypad read late test. +// +// This test uses IRQ to enable auto-joypad read (0 to 1 transition for NMITIMEN.bit0) +// at various H/V positions and prints: +// * How many times the auto-joy flag is 1 +// * The output of the JOY1 register. +// +// Be aware, the VTIME/HTIME is the time of the IRQ interrupt, it is not the position of the +// NMITIMEN write. +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "EN AUTOJOY LATE TEST" + +define TEST_NAME = "Enable AUTOJOY late test" +define TEST_INSTRUCTIONS = "Press and hold Joypad 1" +define VERSION = 1 + +define USES_IRQ_INTERRUPTS + +architecture wdc65816-strict + +include "../../common.inc" + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + + +constant TB_TEST_Y = 10 + +constant TB_TEST_X_TIME = 1 +constant TB_TEST_X_DATA = 16 + + +include "../../reset_handler.inc" +include "../../break_handler.inc" +include "../../dma_forceblank.inc" +include "../../textbuffer.inc" + +// No Vblank interrupts +constant NmiHandler = BreakHandler + + +// zero-page temporary word variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) + +// zero-page temporary far pointer (used by TextBuffer) +allocate(zpTmpPtr, zeropage, 3) + + +allocate(testIndex, zeropage, 2) + +allocate(tmpCounter, zeropage, 2) + + +rodata(rodata0) +TestData: +namespace TestData { + constant VTime = TestData; + constant HTime = TestData + 2; + constant YPos = TestData + 4; + + constant BYTES_PER_ROW = 6 + + + variable _n_rows = 0 + macro _TestRow(vtime, htime) { + dw {vtime}, {htime}, TB_TEST_Y + _n_rows + _n_rows = _n_rows + 1 + } + macro _Scanlines(vtime) { + // Manually tweaked to be somewhere in the middle of the auto-joypad-clock + // (tested on my 2/1/3 SFC console, not the Mesen event viewer) + _TestRow({vtime}, 20) + _TestRow({vtime}, 200) + } + + constant DATA_VERSION = 1 + + _Scanlines(224) + _Scanlines(225) + _Scanlines(226) + _Scanlines(227) + _Scanlines(228) + + constant N_TESTS = _n_rows + constant END_INDEX = N_TESTS * BYTES_PER_ROW +} + + + +// DB = 0x80 +a8() +i16() +code() +function SetupTest { + TextBuffer.SetCursor(0, 0) + TextBuffer.PrintString(TitleAndVersionStr) + + TextBuffer.SetCursor(TB_TEST_X_TIME - 1, TB_TEST_Y - 3) + TextBuffer.PrintStringLiteral(" IRQ IRQ") + TextBuffer.SetCursor(TB_TEST_X_TIME - 1, TB_TEST_Y - 2) + TextBuffer.PrintStringLiteral("VTIME HTIME") + + TextBuffer.SetCursor(TB_TEST_X_DATA - 2, TB_TEST_Y - 3) + TextBuffer.PrintStringLiteral("HVBJOY") + + TextBuffer.SetCursor(TB_TEST_X_DATA - 1, TB_TEST_Y - 2) + TextBuffer.PrintStringLiteral("COUNT JOY1") + + ldx.w #0 + - + stx.b testIndex + + lda.w TestData.YPos,x + tay + ldx.w #TB_TEST_X_TIME + jsr TextBuffer.SetCursor + + ldx.b testIndex + ldy.w TestData.VTime,x + jsr TextBuffer.PrintHexSpace_16Y + + ldx.b testIndex + ldy.w TestData.HTime,x + jsr TextBuffer.PrintHexSpace_16Y + + assert(TestData.END_INDEX < 0xff) + tdc + lda.b testIndex + clc + adc.b #TestData.BYTES_PER_ROW + tax + cmp.b #TestData.END_INDEX + bne - + + rts +} + + + +// IN: X = testIndex +// DB = 0x80 +// D = 0 +a8() +i16() +code() +function DoTest { + // MUST Update this constant if the test changes + constant TEST_VERSION = 1 + + phd + pea $4200 + pld +// D = $4200 + + + // Enable IRQ, Disable autojoy + stz.b NMITIMEN + + assert(pc() >> 16 == TestData >> 16) + ldy.w TestData.HTime,x + sty.b HTIME + + ldy.w TestData.VTime,x + sty.b VTIME + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter + bit.b TIMEUP // clear IRQ flag + sta.b NMITIMEN + + // Enable IRQ interrupts + cli + + + // Setup read-loop registers + ldx.w #500 + ldy.w #0 + + // Enable autojoy in the IRQ interrupt + lda.b #NMITIMEN.autoJoy + wai + + // Count number of times S-CPU reports autoJoy active + - + // X = loop decrementing counter + // Y = HVBJOY.autoJoy counter + // A = NMITIMEN.autoJoy + assert(NMITIMEN.autoJoy == HVBJOY.autoJoy) + bit.b HVBJOY + beq + + iny + + + dex + bne - + + + pld +// D = $4200 + + sty.b tmpCounter + + + // Update text buffer + ldx.w testIndex + ldy.w TestData.YPos,x + ldx.w #TB_TEST_X_DATA + jsr TextBuffer.SetCursor + + ldy.b tmpCounter + jsr TextBuffer.PrintHexSpace_16Y + + ldy.w JOY1 + jsr TextBuffer.PrintHexSpace_16Y + + + // Transfer text buffer to VRAM + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + TextBuffer.VBlank() + + lda.b #0x0f + sta.w INIDISP + + + rts +} + + +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy +// DB = 80 +// D = $4200 +a8() +iu() +code() +function IrqHandler { + sta.b NMITIMEN + + // Clear IRQ flag + bit.b TIMEUP + + rti +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + lda.b #0xf + sta.w INIDISP + + + jsr SetupTest + + + MainLoop: + rep #$30 + a16() + i16() + lda.b testIndex + clc + adc.w #TestData.BYTES_PER_ROW + cmp.w #TestData.END_INDEX + bcc + + lda.w #0 + + + sta.b testIndex + tax + + sep #$20 + a8() + jsr DoTest + + bra MainLoop +} + + +rodata(rodata0) +TitleAndVersionStr: +evaluate TEST_VERSION = DoTest.TEST_VERSION +evaluate DATA_VERSION = TestData.DATA_VERSION + db "\n", {TEST_NAME}, "\nversion {TEST_VERSION}-{DATA_VERSION}", "\n\n", {TEST_INSTRUCTIONS}, 0 + +assert({VERSION} == {TEST_VERSION} + {DATA_VERSION} - 1) + +namespace Resources { + +rodata(rodata0) +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.asm new file mode 100644 index 00000000..00995b8c --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.asm @@ -0,0 +1,69 @@ +// Clear joypad latch during auto-joypad read test +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +define ROM_NAME = "JOYSER0 WR AUTOJOY 0" + +define TEST_NAME = "Clear joypad latch (1 -> 0)\nduring AUTOJOY test" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 9 + + array[N_TESTS] vtime = 224, 225, 225, 226, 226, 227, 227, 228, 228 + array[N_TESTS] htime = 200, 20, 200, 20, 200, 20, 200, 20, 200 +} + + +constant JOYSER_LATCH_START_VALUE = 1 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables IRQ Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode clears joypad latch +// * on the second IRQ of the test: A is set and IrqCode clears joypad latch +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // Clear joypad latch + stz.w JOYSER0 +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.asm new file mode 100644 index 00000000..df40dcea --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.asm @@ -0,0 +1,70 @@ +// Set joypad latch during auto-joypad read test +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +define ROM_NAME = "JOYSER0 WR AUTOJOY 1" + +define TEST_NAME = "Set joypad latch (0 -> 1)\nduring AUTOJOY test" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 9 + + array[N_TESTS] vtime = 229, 224, 225, 225, 226, 226, 227, 227, 228 + array[N_TESTS] htime = 0, 200, 20, 200, 20, 200, 20, 200, 20 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables IRQ Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode clears joypad latch +// * on the second IRQ of the test: A is set and IrqCode writes 1 to joypad latch +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // A = NMITIMEN.autoJoy or 0 + assert(NMITIMEN.autoJoy == JOYSER0.latch) + sta.w JOYSER0 +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/auto-joypad/joyser0-read-during-autojoy.asm b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joyser0-read-during-autojoy.asm new file mode 100644 index 00000000..6ad52fc6 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/auto-joypad/joyser0-read-during-autojoy.asm @@ -0,0 +1,69 @@ +// Manually read JOYSER0 during auto-joypad read test +// +// See _modify-autojoy-during-autojoy.inc for test details +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + +define ROM_NAME = "JOYSER0 RD AUTOJOY" + +define TEST_NAME = "JOYSER0 read\nduring AUTOJOY test" +define VERSION = 3 + +namespace TestData { + constant DATA_VERSION = 1 + + constant N_TESTS = 12 + + array[N_TESTS] vtime = 224, 225, 225, 225, 226, 226, 226, 226, 226, 226, 227, 228 + array[N_TESTS] htime = 200, 70, 80, 90, 0, 64, 128, 192, 256, 320, 20, 20 +} + + +constant JOYSER_LATCH_START_VALUE = 0 +constant AUTO_JOY_ENABLED_BEFORE_IRQ = 1 + + +// Disables IRQ Interrupts and +// * on the first IRQ of the test: A = 0 and IrqCode clears joypad latch +// * on the second IRQ of the test: A is set and IrqCode clears joypad latch +// +// ::HACK CPU registers are setup before IRQ fires:: +// Assumes IRQ interrupt set in DoTest +// +// A = NMITIMEN.autoJoy OR 0 +// DB = 80 +// D = $4200 +inline IrqCode() { + constant IRQ_VERSION = 1 + + assert8a() + + // Clear joypad latch + bit.w JOYSER0 +} + + +include "_modify-autojoy-during-autojoy.inc" + diff --git a/roms/snes-test-roms/src/hardware-tests/hdma-timing-demonstration.asm b/roms/snes-test-roms/src/hardware-tests/hdma-timing-demonstration.asm new file mode 100644 index 00000000..a9a733c5 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/hdma-timing-demonstration.asm @@ -0,0 +1,145 @@ +// A test used to create a HDMA timing diagram for the SNESdev wiki. +// +// To recreate the diagram you will need to run the test in Mesen, then: +// * Open the Event Viewer. +// * Open the Debugger. +// * Create a read breakpoint for $80A000 to $80A0FF +// * Enable "Mark on Event Viewer" on the breakpoint. +// * Unpause emulation. +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMA TIMING" +define VERSION = 1 + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x808fff) + +createDataBlock(tableBank, 0x80a000, 0x80afff) + +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + +a8() +i16() +// DB = 0x80 +// DP = 0 +code() +function Main { + lda.b #INIDISP.force | 0 + sta.w INIDISP + + + // Setup HDMA registers + // + // Using 2 HDMA channels to show that the line-counter is decremented/read after + // the HDMA transfers are completed. + + // Setup an HDMA to CGADD + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #CGADD + sta.w BBAD0 + + ldx.w #CgaddTable + lda.b #CgaddTable >> 16 + stx.w A1T0 + sta.w A1B0 + + // Setup an HDMA to CGDATA + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP1 + + lda.b #CGDATA + sta.w BBAD1 + + ldx.w #CgdataTable + lda.b #CgdataTable >> 16 + stx.w A1T1 + sta.w A1B1 + + + // Wait until VBlank starts + assert(HVBJOY.vBlank == 0x80) + - + lda.w HVBJOY + bmi - + + // Enable HDMA + lda.b #HDMAEN.dma0 | HDMAEN.dma1 + sta.w HDMAEN + + + lda.b #15 + sta.w INIDISP + + + SpinLoop: + wai + bra SpinLoop +} + + + +rodata(tableBank) + +// HDMA Table to CGADD (one register HDMA pattern) +CgaddTable: + variable _i = 0 + while _i < 11 { + db 16 + db 0 + _i = _i + 1 + } + db 0 + + +// HDMA Table to CGDATA (one register HDMA pattern) +CgdataTable: + variable _i = 0 + while _i < 11 { + variable c = 31 - (_i * 3) + db 16 + dw ToPalette(c, c, c) + _i = _i + 1 + } + + diff --git a/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test.asm b/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test.asm new file mode 100644 index 00000000..d733c2ff --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test.asm @@ -0,0 +1,323 @@ +// A simple HDMAEN latch test +// +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMAEN LATCH TEST" +define VERSION = 2 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../nmi_handler.inc" + + +constant VERTICAL_OFFSET = 6 +constant FIRST_HTIME = 220 +constant LAST_HTIME = FIRST_HTIME + 12 + + +// Pauses execution until the start of HBlank +// REQUIRES: 8 bit A, DB access registers +// KEEP: all +macro WaitUntilHblank() { + _Loop{#}: + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvc _Loop{#} +} + +// Pauses execution until the end of HBlank +// REQUIRES: 8 bit A, DB access registers +// KEEP: all +macro WaitUntilHblankEnd() { + _Loop{#}: + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvs _Loop{#} +} + + + +au() +iu() +code() +BreakHandler: +CopHandler: +EmptyHandler: + // Don't use STP, it can cause some versions snes9x to freeze + bra EmptyHandler + + + +code() +PartialHdmaTable: + // CGADD, CGDATA + dw 0, 31 << Palette.red.shift + db 0 + + +// IRQ ISR +// REQUIRES: DB access registers +a8() +iu() +code() +IrqHandler: + bit.w TIMEUP // Required to escape IrqHandler + rti + + +au() +iu() +code() +function ResetHandler { +constant STACK_BOTTOM = __MEMORY__.ramBlocks.stack.end +assert((STACK_BOTTOM & 0xffff) < 0x2000) +assert((STACK_BOTTOM >> 16) == 0 || (STACK_BOTTOM >> 16) == 0x7e) + + jml Reset +Reset: + + sei + clc + xce // Switch to native mode + + rep #$38 // 16 bit A, 16 bit Index, Decimal mode off +a16() +i16() + ldx.w #STACK_BOTTOM + txs // Setup stack + + lda.w #$0000 + tcd // Reset Direct Page + + // Set Data Bank + pea (REGISTER_DB << 8) | $30 + plp + plb +a8() +i8() + + stz.w NMITIMEN + stz.w HDMAEN + + // ROM access time + assert(ROM_SPEED.{ROM_SPEED} == ROM_SPEED.fast) + lda.b #MEMSEL.fastrom + sta.w MEMSEL + + lda.b #INIDISP.force + sta.b INIDISP + + + // Registers $2105 - $210c + // BG settings and VRAM base addresses + ldx.b #$210c - $2105 +- + stz.w $2105,x + dex + bpl - + + // Registers $2123 - $2133 + // Window Settings, BG/OBJ designation, Color Math, Screen Mode + // All disabled + ldx.b #0x2133 - 0x2123 +- + stz.w 0x2123,x + dex + bpl - + + // reset all of the DMA registers + // Registers $4300 - $437f + + ldx.b #0x7f +- + stz.w 0x4300,x + dex + bpl - + + + jml Main +} + + +a8() +i8() +code() +function Main { +allocate(_hdmaen, lowram, 1) + + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN + stz.w HDMAEN + + // Wait until VBlank + - + wai + assert(HVBJOY.vBlank == 0x80) + lda.w HVBJOY + bpl - + + + // Set BG to white + stz.w CGADD + + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Enable display - full brightness + lda.b #15 + sta.w INIDISP + + + // Setup HDMA registers + ldx.b #0x70 + - + lda.b #DMAP.direction.toPpu | DMAP.transfer.twoWriteTwice + sta.w DMAP0,x + + lda.b #CGADD & 0xff + sta.w BBAD0,x + + lda.b #PartialHdmaTable + sta.w A1T0L,x + sta.w A2A0L,x + + lda.b #PartialHdmaTable >> 8 + sta.w A1T0H,x + sta.w A2A0H,x + + lda.b #PartialHdmaTable >> 16 + sta.w A1B0,x + + txa + sec + sbc.b #0x10 + tax + bpl - + + + // Wait until scanline 8 + lda.b #VERTICAL_OFFSET + sta.w VTIMEL + stz.w VTIMEH + + lda.b #NMITIMEN.vCounter + sta.w NMITIMEN + + cli + wai + + + lda.b #1 + sta.w _hdmaen + + lda.b #0 + + // Signal start of test + wdm #0 + + HdmaChannelLoop: + // A = Dma index + tax + + ldy.b #FIRST_HTIME + + HtimeLoop: + // X = DMA index + // Y = HTIMEL to test + + // Reset HDMA registers + stz.w NLTR0,x + + lda.b #PartialHdmaTable + sta.w A2A0L,x + + // No need to set A2A0H + assert((PartialHdmaTable & 0xff) + 6 < 256) + + + // Y = htime to test + sty.w HTIMEL + stz.w HTIMEH + + lda.b #NMITIMEN.hCounter + sta.w NMITIMEN + + lda.w _hdmaen + wai + sta.w HDMAEN + + WaitUntilHblank() + WaitUntilHblankEnd() + + stz.w NMITIMEN + stz.w HDMAEN + + + // Set color 0 to white on next HBlank + + WaitUntilHblank() + + stz.w CGADD + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + WaitUntilHblankEnd() + + iny + cpy.b #LAST_HTIME + 1 + bcc HtimeLoop + + + asl.w _hdmaen + + txa + clc + adc.b #16 + cmp.b #0x80 + bcc HdmaChannelLoop + + assert((LAST_HTIME - FIRST_HTIME + 1) * 2 * 8 + VERTICAL_OFFSET < 224) + + jmp Main +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test_2.asm b/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test_2.asm new file mode 100644 index 00000000..d5726675 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/hdmaen_latch_test_2.asm @@ -0,0 +1,344 @@ +// A simple HDMAEN latch test +// +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "HDMAEN LATCH TEST 2" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x7e0000, 0x7e00ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../wait.inc" + + +constant VERTICAL_OFFSET = 6 +constant HTIME_TO_TEST = 206 +constant TESTS_PER_CHANNEL = 13 + + +au() +iu() +code() +NmiHandler: +BreakHandler: +CopHandler: +EmptyHandler: + sep #$20 +a8() + + lda.b #0 + sta.l NMITIMEN + + lda.b #8 + sta.l INIDISP + + // Don't use STP, it can cause some versions snes9x to freeze + bra EmptyHandler + + + +code() +PartialHdmaTable: + // CGADD, CGDATA + dw 0, 31 << Palette.red.shift + db 0 + + +// IRQ ISR +// REQUIRES: DB access registers +au() +iu() +code() +IrqHandler: + sep #$20 +a8() + bit.w TIMEUP // Required to escape IrqHandler + rti + + +au() +iu() +code() +function ResetHandler { +constant STACK_BOTTOM = __MEMORY__.ramBlocks.stack.end +assert((STACK_BOTTOM & 0xffff) < 0x2000) +assert((STACK_BOTTOM >> 16) == 0 || (STACK_BOTTOM >> 16) == 0x7e) + + jml Reset +Reset: + + sei + clc + xce // Switch to native mode + + rep #$38 // 16 bit A, 16 bit Index, Decimal mode off +a16() +i16() + ldx.w #STACK_BOTTOM + txs // Setup stack + + lda.w #$0000 + tcd // Reset Direct Page + + // Set Data Bank + pea (REGISTER_DB << 8) | $30 + plp + plb +a8() +i8() + + stz.w NMITIMEN + stz.w HDMAEN + + // ROM access time + assert(ROM_SPEED.{ROM_SPEED} == ROM_SPEED.fast) + lda.b #MEMSEL.fastrom + sta.w MEMSEL + + lda.b #INIDISP.force + sta.b INIDISP + + + // Registers $2105 - $210c + // BG settings and VRAM base addresses + ldx.b #$210c - $2105 +- + stz.w $2105,x + dex + bpl - + + // Registers $2123 - $2133 + // Window Settings, BG/OBJ designation, Color Math, Screen Mode + // All disabled + ldx.b #0x2133 - 0x2123 +- + stz.w 0x2123,x + dex + bpl - + + // reset all of the DMA registers + // Registers $4300 - $437f + + ldx.b #0x7f +- + stz.w 0x4300,x + dex + bpl - + + + jml Main +} + + +au() +iu() +code() +function Main { +allocate(_channelIndex, lowram, 2) +allocate(_hdmaen, lowram, 1) + + sep #$30 +a8() +i8() + + stz.w NMITIMEN + stz.w HDMAEN + + // Wait until VBlank + - + assert(HVBJOY.vBlank == 0x80) + lda.w HVBJOY + bpl - + + + // Set BG to white + stz.w CGADD + + lda.b #0xff + sta.w CGDATA + sta.w CGDATA + + + // Enable display - full brightness + lda.b #15 + sta.w INIDISP + + + // Setup HDMA registers + ldx.b #0x70 + - + lda.b #DMAP.direction.toPpu | DMAP.transfer.twoWriteTwice + sta.w DMAP0,x + + lda.b #CGADD & 0xff + sta.w BBAD0,x + + lda.b #PartialHdmaTable + sta.w A1T0L,x + sta.w A2A0L,x + + lda.b #PartialHdmaTable >> 8 + sta.w A1T0H,x + sta.w A2A0H,x + + lda.b #PartialHdmaTable >> 16 + sta.w A1B0,x + + txa + sec + sbc.b #0x10 + tax + bpl - + + + // Wait until scanline 8 + lda.b #VERTICAL_OFFSET + sta.w VTIMEL + stz.w VTIMEH + + lda.b #NMITIMEN.vCounter + sta.w NMITIMEN + + cli + wai + + + lda.b #HTIME_TO_TEST + sta.w HTIMEL + stz.w HTIMEH + + lda.b #NMITIMEN.hCounter + sta.w NMITIMEN + + + rep #$10 +a8() +i16() + ldx.w #0 + stx.w _channelIndex + + lda.b #1 + sta.w _hdmaen + + + HdmaChannelLoop: + evaluate t = 0 + while {t} < TESTS_PER_CHANNEL { + evaluate delay = 24 + {t} * 2 + evaluate after_delay = 48 - {t} * 2 + + wdm #{t} + + wai + w{delay}() + + lda.w _hdmaen + sta.w HDMAEN + + w{after_delay}() + + jsr _OddScanline + + evaluate t = {t} + 1 + } + + + lda.w _channelIndex + clc + adc.b #16 + sta.w _channelIndex + + + asl.w _hdmaen + beq + + jmp HdmaChannelLoop + + + + assert(TESTS_PER_CHANNEL * 2 * 8 + VERTICAL_OFFSET < 220) + + jmp Main + + +a8() +i16() +function _OddScanline { + wai + stz.w HDMAEN + + + // Reset HDMA registers + ldx.w _channelIndex + + stz.w NLTR0,x + + lda.b #PartialHdmaTable + sta.w A2A0L,x + + // No need to set A2A0H + assert((PartialHdmaTable & 0xff) + 6 < 256) + + // Set color 0 to white on next HBlank + + - + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvc - + + lda.b #0xff + stz.w CGADD + sta.w CGDATA + sta.w CGDATA + + // Required to get the H-Counter IRQ to fire at a consistent time + // (on bsnes-plus at least) + lda.b #11 + - + dec + bne - + + w32() + w18() + + rts +} + +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_0.asm b/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_0.asm new file mode 100644 index 00000000..52b30512 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_0.asm @@ -0,0 +1,159 @@ +// A simple test to demonstrate brightness 0 is not black on a SNES console. +// +// SPDX-FileCopyrightText: © 2021 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2021 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "INIDISP BRIGHTNESS 0" +define VERSION = 1 + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// Mode 0 +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU registers + + // Enable Force-Blank + lda.b #INIDISP.force | 0 + sta.w INIDISP + + + // Mode 0 + stz.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tiles) + + + + // Enable display, 0 brightness + lda.b #0 + sta.w INIDISP + + + + MainLoop: + wai + bra MainLoop +} + + + +namespace Resources { + + +// Palette +// Colour 0: white +// Colours 1-3: black +Palette: + dw 0xffff, 0x0000, 0x0000, 0x0000 +constant Palette.size = pc() - Palette + + +// BG 1 tiles +// 2bpp +// Tile 0: all pixels colour 0 +// Tile 1: all pixels colour 1 +Bg1_Tiles: + fill 16, 0x00 + fill 16, 0xff +constant Bg1_Tiles.size = pc() - Bg1_Tiles + + +// BG 1 tilemap +// Checkerboard pattern +Bg1_Tilemap: + variable x = 0 + variable y = 0 + + while y < 32 { + x = 0; + while x < 32 { + dw (y ^ x) & 1 + + x = x + 1 + } + + y = y + 1 + } +constant Bg1_Tilemap.size = pc() - Bg1_Tilemap + +assert(Bg1_Tilemap.size == 2048) + +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_delay.asm b/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_delay.asm new file mode 100644 index 00000000..c58cf107 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/inidisp_brightness_delay.asm @@ -0,0 +1,172 @@ +// A simple test to demonstrate the brightness delay on a RGB modded 1-chip console. +// +// NOTE: You must disable the *1CHIP transient fixes* and *Brightness limit* +// settings if you are running this test on an sd2snes. +// +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "BRIGHTNESS DELAY TEST" +define VERSION = 3 + +define USES_IRQ_INTERRUPTS + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../nmi_handler.inc" +include "../dma_forceblank.inc" + + +// The number of scanlines between each brightness test +constant BRIGHTNESS_TEST_HEIGHT = 32 + + +// The horizontal dot position to trigger IRQ +// +// This value is chosen to ensure that: +// 1) The SLHV latch is triggered after h-blank +// 2) The INIDISP store occurs before Work RAM refresh +constant IRQ_X_POS = 339 - 30 + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU registers + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Fill CGRAM with white + stz.w CGADD + + ldx.w #512 + lda.b #0xff + - + sta.w CGDATA + dex + bne - + + lda.b #0 + sta.w TM + + + + // Enable Horizontal IRQ + ldx.w #IRQ_X_POS + stx.w HTIME + + lda.b #NMITIMEN.hCounter | NMITIMEN.vBlank + sta.w NMITIMEN + + cli + + + MainLoop: + wai + bra MainLoop +} + + +// IRQ ISR +// +// Enable display (at full brightness) +function IrqHandler { + rep #$30 +a16() +i16() + phb + pha + phx + phy + + phk + plb + + sep #$30 +a8() +i8() + // Latch V Counter + lda.w SLHV + + // Read vertical scanline location + lda.w OPVCT + ldx.w OPVCT + // A = OPVCT low byte + + // Change brightness when we are on an appropriate scanline + assertPowerOfTwo(BRIGHTNESS_TEST_HEIGHT) + sec + sbc.b #8 + and.b #BRIGHTNESS_TEST_HEIGHT - 1 + bne + + // Full brightness + ldx.b #0xf + stx.w INIDISP + bra End + + + cmp.b #BRIGHTNESS_TEST_HEIGHT / 2 + bne + + // 0 brightness + stz.w INIDISP + + + +End: + lda.w TIMEUP // Required to escape IrqHandler + + rep #$30 +a16() +i16() + ply + plx + pla + plb + + rti +} + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/inidisp_enable_display_mid_frame.asm b/roms/snes-test-roms/src/hardware-tests/inidisp_enable_display_mid_frame.asm new file mode 100644 index 00000000..01fa2dd5 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/inidisp_enable_display_mid_frame.asm @@ -0,0 +1,550 @@ +// A simple test to show what happens when you enable the display mid frame +// +// Controls: +// D-pad: move enable display time +// Select: Move enable display to H-Blank +// A: Change background/tile modes +// +// +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "ENABLE DISPLAY MID FRAME" +define VERSION = 2 + +define USES_IRQ_INTERRUPTS + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../nmi_handler.inc" +include "../dma_forceblank.inc" + +// BG2-4 uses WADDR 0 +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + +// Temporary variables +allocate(_tmp, lowram, 2) + +// The current DisplayModeSettings entry to load +// (word index) +allocate(displayModeIndex, lowram, 2) + +// The current joypad state +// Call `UpdateJoypad` to update this variable +// (uint16, JOY state) +allocate(joypad, lowram, 2) + + +// The current X/Y position to fire IRQ interrupt at +// (2x uint16) +allocate(irq_x, lowram, 2) +allocate(irq_y, lowram, 2) + +constant IRQ_X_MAX = 339 +constant IRQ_Y_MAX = 261 + +constant IRQ_X_START = 15 +constant IRQ_Y_START = 89 + + + +// IRQ ISR +// +// Enable display (at full brightness) +IrqHandler: + sep #$20 +a8() + pha + // This ISR uses long addressing (faster than `phk : plb`) + + // Enable display - full brightness + lda.b #0x0f + sta.l INIDISP + + lda.l TIMEUP // Required to escape IrqHandler + + pla + rti + + + +// Waits until the start of VBlank +// REQUIRES: NMI enabled +au() +iu() +code() +function WaitFrame { + php + sep #$20 +a8() + // Wait until end of vBlank (if in vBlank) + - + lda.l HVBJOY + bmi - + + // Wait until start of next vBlank + - + wai + assert(HVBJOY.vBlank == 0x80) + lda.l HVBJOY + bpl - + + plp + + rts +} + + +// Reads the state of the joypad 1, saving it in the `joypad` variable +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function UpdateJoypad { + + Loop: + // Wait until autoJoy bit is cleared + lda.b #HVBJOY.autoJoy + + - + bit.w HVBJOY + bne - + + ldx.w JOY1 + + // Confirm we have not entered autoJoy when readying JOY1 + // We need to do this as this program does very little during vBlank + bit.w HVBJOY + bne Loop + + // Confirm this is a stable read + cpx.w JOY1 + bne Loop + + rep #$30 +a16() + txa + bit.w #JOY.type.mask + beq + + lda.w #0 + + + tax + sta.w joypad + + sep #$20 +a8() + + rts +} + + +// Setup and initialize the PPU +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +// MODIFIES: enables force-blank +macro SetupPpu() { + assert8a() + assert16i() + + // Enable NMI and autoJoy (just in case) + lda.b #NMITIMEN.vBlank | NMITIMEN.autoJoy + sta.w NMITIMEN + + jsr WaitFrame + + + // Set PPU registers + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + // BG2-BG4 have a TILE & MAP WADDR of 0 (as set by ResetRegisters) + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + + // Fill bottom half of CGRAM with a red pattern. + // 16 colour gradient of mid-red to bright-red, repeated 8 times + stz.w CGADD + + ldx.w #128 + - + txa + dec + eor.b #0xff + and.b #0x0f + ora.b #0x10 + sta.w CGDATA + stz.w CGDATA + + dex + bne - + + + // Fill top half of CGRAM with a bright green pattern. + // 16 colour gradient of mid-green to bright-green, repeated 8 times + sep #$30 + rep #$20 +a16() +i8() + ldx.b #128 + - + txa + dec + eor.w #0xffff + and.w #0x000f + ora.w #0x0010 + asl + asl + asl + asl + asl + + tay + sty.w CGDATA + xba + tay + sty.w CGDATA + + dex + bne - + + rep #$30 + sep #$20 +a8() +i16() + + + // Load obj palette + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Set size of sprites used in Obj_Oam to large (32x32) + lda.b #1 + stz.w OAMADDL + sta.w OAMADDH + + ldx.w #Resources.Obj_Oam.size / 4 / 4 + lda.b #%10101010 + - + sta.w OAMDATA + dex + bne - + + + // Load Tiles + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + // Load DisplayMode tiles/Settings + // ------------------------------- + + // Verify displayModeIndex in bounds + ldx.w displayModeIndex + cpx.w #DisplayModeSettings.TableSize + bcc + + ldx.w #0 + + + stx.w displayModeIndex + + lda.w DisplayModeSettings.BgMode,x + sta.w BGMODE + + lda.w DisplayModeSettings.Tm,x + sta.w TM + + + // Transfer tiles to VRAM + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + rep #$30 +a16() + + ldx.w displayModeIndex + lda.l DisplayModeSettings.Tiles,x + sta.w _tmp + lda.l DisplayModeSettings.Tiles.size,x + tay + + sep #$20 +a8() + lda.l DisplayModeSettings.Tiles + 2,x + ldx.w _tmp + + jsr Dma.ForceBlank.TransferToVram + + + // Transfer palette to CGRAM + + rep #$30 +a16() + + ldx.w displayModeIndex + lda.l DisplayModeSettings.Palette,x + sta.w _tmp + lda.l DisplayModeSettings.Palette.size,x + tay + + sep #$20 +a8() + lda.l DisplayModeSettings.Palette + 2,x + ldx.w _tmp + + stz.w CGADD + jsr Dma.ForceBlank.TransferToCgram + + + // Enable NMI and autoJoy + lda.b #NMITIMEN.vBlank | NMITIMEN.autoJoy + sta.w NMITIMEN + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP +} + + + +au() +iu() +code() +function Main { + rep #$30 +a16() +i16() + + stz.w displayModeIndex + + // Initialize IRQ position + ldx.w #IRQ_X_START + stx.w irq_x + stx.w HTIME + + ldy.w #IRQ_Y_START + sty.w irq_y + sty.w VTIME + +Setup: + rep #$30 + sep #$20 +a8() +i16() + cli // Enable IRQ interrupts + + SetupPpu() + + // Enable NMI, IRQ and autoJoy + lda.b #NMITIMEN.vBlank | NMITIMEN.vCounter | NMITIMEN.hCounter | NMITIMEN.autoJoy + sta.w NMITIMEN + + // Wait until user lets go of A + - + jsr WaitFrame + jsr UpdateJoypad + + lda.w joypad + and.b #JOYL.a + bne - + + a8() + i16() + MainLoop: + jsr WaitFrame + + // Force-blank, full brightness + // (IRQ will enable screen mid frame) + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr UpdateJoypad + + lda.w joypad + bit.b #JOYL.a + bne GotoNextDisplayMode + + + // Update IRQ x/y position + ldx.w irq_x + ldy.w irq_y + + lda.w joypad + 1 + + bit.b #JOYH.select + beq + + // select pressed + + // Mesen-S event viewer shows 24 dots between IRQ triggering and the store to INIDISP. + // -16 dots for tile buffer pre-load. + // -8 dots produces the most interesting glitches on my SFC. + + cpx.w #256 + ldx.w #IRQ_X_MAX - 24 - 16 - 8 + + // Go to the previous scanline if not in VBlank + bcc MoveUp + + + bit.b #JOYH.up + beq + + MoveUp: + // up pressed + dey + bpl + + ldy.w #IRQ_Y_MAX + + + bit.b #JOYH.down + beq + + // down pressed + iny + cpy.w #IRQ_Y_MAX + 1 + bcc + + ldy.w #0 + + + bit.b #JOYH.left + beq + + // left pressed + dex + bpl + + ldx.w #IRQ_X_MAX + dey + + + bit.b #JOYH.right + beq + + // right pressed + inx + cpx.w #IRQ_X_MAX + 1 + bcc + + ldx.w #0 + iny + + + + stx.w irq_x + stx.w HTIME + + sty.w irq_y + sty.w VTIME + + jmp MainLoop + + +GotoNextDisplayMode: + rep #$31 +a16() +i16() + lda.w displayModeIndex + // carry clear + adc.w #DisplayModeSettings.size + sta.w displayModeIndex + + jmp Setup +} + + + + +DisplayModeSettings: +namespace DisplayModeSettings { + struct(pc()) + field(BgMode, 1) + field(Tm, 1) + field(Tiles, 3) + field(Tiles.size, 2) + field(Palette, 3) + field(Palette.size, 2) + endstruct() + + macro _entry(tiles, palette, bgMode, evaluate tm) { + db {bgMode} + db {tm} + dl Resources.{tiles} + dw Resources.{tiles}.size + dl Resources.{palette} + dw Resources.{palette}.size + } + + _entry(Tiles_4bpp, Palette_4bpp, 1, TM.bg1 | TM.obj) + _entry(Tiles_4bpp, Palette_4bpp, 1, TM.bg1) + _entry(Tiles_2bpp, Palette_2bpp, 0, TM.bg1 | TM.obj) + _entry(Tiles_2bpp, Palette_2bpp, 0, TM.bg1) + _entry(Tiles_8bpp, Palette_8bpp, 3, TM.bg1 | TM.obj) + _entry(Tiles_8bpp, Palette_8bpp, 3, TM.bg1) + _entry(Tiles_8bpp, Palette_8bpp, 3, TM.obj) + + constant TableSize = pc() - DisplayModeSettings.BgMode + assert(TableSize % size == 0) +} + +namespace Resources { + insert Bg1_Tilemap, "../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_8bpp, "../../gen/example-backgrounds/bricks-8bpp-tiles.tiles" + insert Palette_8bpp, "../../gen/example-backgrounds/bricks-8bpp-tiles.pal" + insert Tiles_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.tiles" + insert Palette_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.pal" + insert Tiles_2bpp, "../../gen/example-backgrounds/bricks-2bpp-tiles.tiles" + insert Palette_2bpp, "../../gen/example-backgrounds/bricks-2bpp-tiles.pal" + + insert Obj_Tiles, "../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../gen/example-backgrounds/obj-oam.bin" +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank.asm b/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank.asm new file mode 100644 index 00000000..fb92e1ff --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank.asm @@ -0,0 +1,214 @@ +// A simple test to show what happens when you forget to force-blank +// before uploading data to the PPU. +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "FORGOT TO FORCE BLANK" +define VERSION = 0 + +define USES_IRQ_INTERRUPTS + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + +// BG2-4 uses WADDR 0 +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + +allocate(loopCounter, lowram, 2) + + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +// IRQ ISR +// +// Don't do anything, just return +function IrqHandler { + sep #$20 +a8() + pha + + lda.l TIMEUP + + pla + rti +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + // Fill the VRAM with data + // (If the VRAM is empty then the there is little to no corruption) + lda.b #INIDISP.force + sta.w INIDISP + + lda.b #64 * 1024 / Resources.Bg1_Tilemap + sta.w loopCounter + - + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + dec.w loopCounter + bne - + + + + // Enable display, full brightness. + // Forget to force blank + lda.b #0x0f + sta.w INIDISP + + + // Wait until it is line 40 (so we are not in VBlank) + ldy.w #40 + sty.w VTIME + + lda.b #NMITIMEN.vCounter + sta.w NMITIMEN + + wai + + + wdm #1 + + + // Setuo PPU registers + + lda.b #BGMODE.mode3 + sta.w BGMODE + + lda.b #TM.bg1 | TM.obj + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Set size of sprites used in Obj_Oam to large (32x32) + lda.b #1 + stz.w OAMADDL + sta.w OAMADDH + + ldx.w #Resources.Obj_Oam.size / 4 / 4 + lda.b #%10101010 + - + sta.w OAMDATA + dex + bne - + + + // Transfer tilemap to VRAM + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + // Transfer tiles to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_8bpp) + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + + // Transfer palettes to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette_8bpp) + + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + + // Enable display fill brightness + lda.b #0x0f + sta.w INIDISP + + + wdm #2 + + + // Loop forever + Loop: + wai + jmp Loop +} + + +namespace Resources { + insert Bg1_Tilemap, "../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_8bpp, "../../gen/example-backgrounds/bricks-8bpp-tiles.tiles" + insert Palette_8bpp, "../../gen/example-backgrounds/bricks-8bpp-tiles.pal" + + insert Obj_Tiles, "../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../gen/example-backgrounds/obj-oam.bin" +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank_2.asm b/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank_2.asm new file mode 100644 index 00000000..209bfd07 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/inidisp_forgot_to_force_blank_2.asm @@ -0,0 +1,215 @@ +// A simple test to show what happens when you forget to force-blank +// before uploading data to the PPU. +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "FORGOT FORCE BLANK 2" +define VERSION = 0 + +define USES_IRQ_INTERRUPTS + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_OBJ_TILES_WADDR = 0x6000 +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x1400 + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +// IRQ ISR +// +// Does not do anything. +function IrqHandler { + sep #$20 +a8() + pha + + lda.l TIMEUP + + pla + rti +} + + + +// Sets PPU registers and load data into VRAM/CGRAM/OAM +// +// REQUIRES: 8 bit A, 16 bit Index, DB access registers +a8() +i16() +code() +function SetupPpu { + + lda.b #BGMODE.mode1 + sta.w BGMODE + + lda.b #TM.bg1 | TM.obj + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + + // Load OAM + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + // Set size of sprites used in Obj_Oam to large (32x32) + lda.b #1 + stz.w OAMADDL + sta.w OAMADDH + + ldx.w #Resources.Obj_Oam.size / 4 / 4 + lda.b #%10101010 + - + sta.w OAMDATA + dex + bne - + + + // Transfer tilemap to VRAM + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg1_Tilemap) + + + // Transfer tiles to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_4bpp) + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + + // Transfer palettes to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette_4bpp) + + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + // Fill the VRAM with data + // (If the VRAM is empty then the there is little to no corruption) + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr Dma.ForceBlank.ClearVram + jsr Dma.ForceBlank.ClearCgram + + jsr SetupPpu + + + // Enable display, full brightness. + // Forget to force blank + lda.b #0x0f + sta.w INIDISP + + + // Wait until the screen is active + // (This position produces a nice looking glitch) + ldy.w #103 + sty.w VTIME + + ldy.w #137 + sty.w HTIME + + lda.b #NMITIMEN.vCounter | NMITIMEN.hCounter + sta.w NMITIMEN + + wai + + + // Transfer data to PPU during active display period + jsr SetupPpu + + + // Loop forever + Loop: + wai + jmp Loop +} + + +namespace Resources { + insert Bg1_Tilemap, "../../gen/example-backgrounds/bricks-tilemap.bin" + + insert Tiles_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.tiles" + insert Palette_4bpp, "../../gen/example-backgrounds/bricks-4bpp-tiles.pal" + + insert Obj_Tiles, "../../gen/example-backgrounds/obj-4bpp-tiles.tiles" + insert Obj_Palette, "../../gen/example-backgrounds/obj-4bpp-tiles.pal" + insert Obj_Oam, "../../gen/example-backgrounds/obj-oam.bin" +} + +finalizeMemory() + + diff --git a/roms/snes-test-roms/src/hardware-tests/joypad_bounce_test.asm b/roms/snes-test-roms/src/hardware-tests/joypad_bounce_test.asm new file mode 100644 index 00000000..57b90bd5 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/joypad_bounce_test.asm @@ -0,0 +1,643 @@ +// A test ROM design to display the contact bound on key-press and key-release. +// +// It reads 12 bits of controller port 1 every scanline, writes the data to a buffer and waits for +// no button presses for 262 scanlines (1 frame). Then it builds four HDMA tables to display ~200 +// scanlines after button-press and ~200 scanlines before button-release. +// +// For each pair of vertical lines represents one button. +// The left line is scanlines after button press and the right line is scanlines before release. +// +// CAUTION: This test is designed for one button at a time. +// CAUTION: This test cannot read controller data and build the HDMA tables at the same time. +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "JOYPAD BOUNCE TEST" +define VERSION = 1 + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1eff) +createRamBlock(stack, 0x7e1f00, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + +// This test does not use interrupts +constant NmiHandler = BreakHandler.ISR + + +// All four backgrounds use the same tilemap and tiles +constant VRAM_BG_TILES_WADDR = 0x1000 +constant VRAM_BG_MAP_WADDR = 0x0000 +constant VRAM_OBJ_TILES_WADDR = 0x6000 + + +constant N_BITS = 12; +constant SPACING_BETWEEN_BITS = 12 +constant SPACING_BETWEEN_LINES = 4 +constant TOTAL_WIDTH = (N_BITS - 1) * SPACING_BETWEEN_BITS + SPACING_BETWEEN_LINES + 2 + +constant BG1_X_OFFSET = -(256 - TOTAL_WIDTH) / 2 +constant BG2_X_OFFSET = BG1_X_OFFSET - 4 * SPACING_BETWEEN_BITS +constant BG3_X_OFFSET = BG1_X_OFFSET - SPACING_BETWEEN_LINES +constant BG4_X_OFFSET = BG2_X_OFFSET - SPACING_BETWEEN_LINES + +constant DISPLAY_HEIGHT = 224 +constant Y_OFFSET = 10 +constant N_SCANLINES_TO_DISPLAY = DISPLAY_HEIGHT - Y_OFFSET + + +// Number of scanlines of no-button presses to wait if the MainLoop starts with a button pressed +constant WAIT_FOR_RELEASE_THREASHOLD = 262 + +// Number of scanlines with 0 depressed buttons before displaying data. +constant RELEASE_THREASHOLD = 262 // 1 frame + +constant PRESS_BUFFER_SIZE = N_SCANLINES_TO_DISPLAY +constant RELEASE_BUFFER_SIZE = 0x600 + +assert(RELEASE_BUFFER_SIZE > DISPLAY_HEIGHT + RELEASE_THREASHOLD + 32) + + +allocate(zpTmpByte, zeropage, 1) + +// Used to determine if the release buffer is empty + +// HDMA double buffer control variable +// (word index into `HdmaTable*_TableAddr`) +allocate(currentHdmaTable, zeropage, 2) + + +// Determines if the `buttonReleaseBuffer` is full or not. +// (byte flag) +allocate(releaseBufferNotFull, zeropage, 1) + +// Index of the first line to of the release buffer to draw. +// (word index into `buttonReleaseBuffer_*`). +allocate(releaseBufferIndex, zeropage, 2) + + +// Button press buffer +allocate(buttonPressBuffer_l, lowram, PRESS_BUFFER_SIZE) +allocate(buttonPressBuffer_h, lowram, PRESS_BUFFER_SIZE) + +// Button release circular buffer +allocate(buttonReleaseBuffer_l, lowram, RELEASE_BUFFER_SIZE) +allocate(buttonReleaseBuffer_h, lowram, RELEASE_BUFFER_SIZE) + + + +assert(DISPLAY_HEIGHT * 2 + 32 < 0x200) +allocate(hdmaTable1_a, lowram, 0x200) +allocate(hdmaTable1_b, lowram, 0x200) +allocate(hdmaTable2_a, lowram, 0x200) +allocate(hdmaTable2_b, lowram, 0x200) +allocate(hdmaTable3_a, lowram, 0x200) +allocate(hdmaTable3_b, lowram, 0x200) +allocate(hdmaTable4_a, lowram, 0x200) +allocate(hdmaTable4_b, lowram, 0x200) + + +// The number of times the HDMA tables have been displayed +// (4x 0-9 digits) +allocate(readCounterDigits, lowram, 4) +constant readCounterDigits_size = 4 + + +// DB = 0x80 +macro WaitForStartOfVBlank() { + assert8a() + + InVBlankLoop{#}: + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bmi InVBlankLoop{#} + + WaitForVBlankLoop{#}: + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bpl WaitForVBlankLoop{#} +} + + +// DB = 0x80 +macro WaitForHBlank() { + assert8a() + + // Wait for H-Blank + Loop{#}: + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvc Loop{#} +} + + +// OUT: A = joypad low byte +// KEEP: X, Y +// DB = 0x80 +macro ReadJoypadBits_l() { + assert8a() + + // Latch the joypad + lda.b #JOYSER0.latch + sta.w JOYSER0 + stz.w JOYSER0 + + + variable _i = 0 + while _i < 7 { + lda.w JOYSER0 + lsr + rol.b zpTmpByte + _i = _i + 1 + } + lda.w JOYSER0 + lsr + lda.b zpTmpByte + rol +} + + + +// OUT: A = joypad hight byte (CAUTION: not rotated) +// KEEP: X, Y +// DB = 0x80 +macro ReadJoypadBits_h() { + variable _i = 0 + while _i < 3 { + lda.w JOYSER0 + lsr + rol.b zpTmpByte + _i = _i + 1 + } + + lda.w JOYSER0 + lsr + lda.b zpTmpByte + and.b #0b111 + rol +} + + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + stz.w NMITIMEN + + + // Set PPU registers + + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #(VRAM_BG_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + sta.w BG2SC + sta.w BG3SC + sta.w BG4SC + + lda.b #((VRAM_BG_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift) | ((VRAM_BG_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg2.shift) + sta.w BG12NBA + sta.w BG34NBA + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + lda.b #TM.bg1 | TM.bg2 | TM.bg3 | TM.bg4 | TM.obj + sta.w TM + + + lda.b #BG1_X_OFFSET + sta.w BG1HOFS + lda.b #BG1_X_OFFSET >> 16 + sta.w BG1HOFS + + lda.b #BG2_X_OFFSET + sta.w BG2HOFS + lda.b #BG2_X_OFFSET >> 16 + sta.w BG2HOFS + + lda.b #BG3_X_OFFSET + sta.w BG3HOFS + lda.b #BG3_X_OFFSET >> 16 + sta.w BG3HOFS + + lda.b #BG4_X_OFFSET + sta.w BG4HOFS + lda.b #BG4_X_OFFSET >> 16 + sta.w BG4HOFS + + + + ldx.w #VRAM_BG_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg_Tilemap) + + ldx.w #VRAM_BG_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg_Tiles) + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + Dma.ForceBlank.ToCgram(Resources.Palette) + Dma.ForceBlank.ToCgram(Resources.ObjPalette) + + stz.w OAMADDL + stz.w OAMADDL + Dma.ForceBlank.ToOam(Resources.Oam) + + // Clear Hi table + ldx.w #128 * 2 + stx.w OAMADD + stz.w OAMDATA + + + // Reset readCounterDigits + ldx.w #readCounterDigits_size - 1 + lda.b #9 + - + sta.w readCounterDigits,x + dex + bpl - + + + ldx.w #0 + jsr BuildAndDisplayHdmaTables + + lda.b #15 + sta.w INIDISP + + + MainLoop: + lda.b #1 + sta.b releaseBufferNotFull + + // If a button has been pressed, Wait for WAIT_FOR_RELEASE_THREASHOLD scanlines of no button presses. + // (To ensure buttonPressBuffer contains the initial key-press and contact bounce data) + ldx.w #1 + WaitForKeyRelease: + WaitForHBlank() + + ReadJoypadBits_l() + sta.b zpTmpByte + + ReadJoypadBits_h() + ora.b zpTmpByte + beq + + ldx.w #WAIT_FOR_RELEASE_THREASHOLD + + + dex + bne WaitForKeyRelease + + + // Wait until a button has been pressed + WaitForKeyPressLoop: + WaitForHBlank() + + ReadJoypadBits_l() + sta.w buttonPressBuffer_l + PRESS_BUFFER_SIZE - 1 + + ReadJoypadBits_h() + sta.w buttonPressBuffer_h + PRESS_BUFFER_SIZE - 1 + ora.w buttonPressBuffer_l + PRESS_BUFFER_SIZE - 1 + beq WaitForKeyPressLoop + + + // Read `N_KEYDOWN_SCANLINES` + ldx.w #PRESS_BUFFER_SIZE - 2 + KeyPressLoop: + WaitForHBlank() + + ReadJoypadBits_l() + sta.w buttonPressBuffer_l,x + + ReadJoypadBits_h() + sta.w buttonPressBuffer_h,x + + dex + bpl KeyPressLoop + + + ldy.w #RELEASE_THREASHOLD + ldx.w #RELEASE_BUFFER_SIZE + KeyReleaseLoop: + dex + bpl + + ldx.w #RELEASE_BUFFER_SIZE - 1 + + stz.b releaseBufferNotFull + + + + WaitForHBlank() + + ReadJoypadBits_l() + sta.w buttonReleaseBuffer_l,x + + ReadJoypadBits_h() + sta.w buttonReleaseBuffer_h,x + + ora.w buttonReleaseBuffer_l,x + beq + + ldy.w #RELEASE_THREASHOLD + + jmp KeyReleaseLoop + + + dey + bne KeyReleaseLoop + + rep #$10 + i16() + jsr BuildAndDisplayHdmaTables + + jmp MainLoop +} + + + +// IN: X = buttonReleaseBuffer index +// DB = 0x7e +a8() +i16() +function BuildAndDisplayHdmaTables { + lda.b releaseBufferNotFull + + rep #$30 +a16() + + beq + + cpx.w #RELEASE_BUFFER_SIZE - RELEASE_THREASHOLD - N_SCANLINES_TO_DISPLAY + bcc + + lda.w #RELEASE_BUFFER_SIZE - 1 + bra ++ + + + // The release buffer is full or contains enough data to display + txa + clc + adc.w #RELEASE_THREASHOLD + N_SCANLINES_TO_DISPLAY - 1 + cmp.w #RELEASE_BUFFER_SIZE + bcc + + // carry set + sbc.w #RELEASE_BUFFER_SIZE + + + sta.b releaseBufferIndex + + sep #$20 +a8() + + + ldy.b currentHdmaTable + beq + + ldy.w #0 + bra ++ + + + ldy.w #2 + + + sty.w currentHdmaTable + + + // IN: X = table offset + macro _BuildTable(evaluate table, evaluate data, evaluate bufferSize, evaluate yOffset) { + assert8a() + assert16i() + + ldy.b currentHdmaTable + lda.w HdmaTable{table}_TableAddr,y + sta.w WMADDL + lda.w HdmaTable{table}_TableAddr + 1,y + sta.w WMADDM + stz.w WMADDH + + + ldy.w #-1 + + if {yOffset} > 0 { + // HDMA table entry - repeat mode, yOffset lines + lda.b #0x80 | {yOffset} + sta.w WMDATA + + - + tya + sta.w WMDATA + stz.w WMDATA + dey + cpy.w #-1 - {yOffset} + bne - + } + + // Use a different `nScanlines1` value for each table to stagger HDMA entries + // and the reduce maximum HDMA time in H-Blank. + evaluate nScanlines1 = 127 - {table} + evaluate nScanlines2 = DISPLAY_HEIGHT - {nScanlines1} - {yOffset} + assert({nScanlines2} < 127) + + // HDMA table entry - repeat mode, nScanlines1 lines + lda.b #0x80 | {nScanlines1} + sta.w WMDATA + + - + tya + clc + adc.w {data},x + sta.w WMDATA + stz.w WMDATA + + dex + bpl + + ldx.w #{bufferSize} - 1 + + + + dey + cpy.w #-1 - {yOffset} - {nScanlines1} + bne + + // HDMA table entry - repeat mode, nScanlines2 lines + lda.b #0x80 | {nScanlines2} + sta.w WMDATA + + + cpy.w #-1 - DISPLAY_HEIGHT + bne - + + // HDMA end + stz.w WMDATA + } + ldx.w #PRESS_BUFFER_SIZE - 1 + _BuildTable(1, buttonPressBuffer_l, PRESS_BUFFER_SIZE, Y_OFFSET) + ldx.w #PRESS_BUFFER_SIZE - 1 + _BuildTable(2, buttonPressBuffer_h, PRESS_BUFFER_SIZE, Y_OFFSET) + ldx.b releaseBufferIndex + _BuildTable(3, buttonReleaseBuffer_l, RELEASE_BUFFER_SIZE, 0) + ldx.b releaseBufferIndex + _BuildTable(4, buttonReleaseBuffer_h, RELEASE_BUFFER_SIZE, 0) + + + // Clear release buffer + ldx.w #RELEASE_BUFFER_SIZE - 1 + - + stz.w buttonReleaseBuffer_l,x + stz.w buttonReleaseBuffer_h,x + dex + bpl - + + + // Increment read counter digits + ldx.w #readCounterDigits_size - 1 + - + inc.w readCounterDigits,x + lda.w readCounterDigits,x + cmp.b #10 + bcc + + stz.w readCounterDigits,x + dex + bpl - + + + + + WaitForStartOfVBlank() + + ldy.b currentHdmaTable + + macro _SetupHdmaChannel(evaluate c, evaluate bBusAddr, addrTable) { + assert8a() + assert16i() + + lda.b #DMAP.direction.toPpu | DMAP.transfer.writeTwice + sta.w DMAP{c} + + lda.b #{bBusAddr} + sta.w BBAD{c} + + ldx.w {addrTable},y + stx.w A1T{c} + stz.w A1B{c} + } + _SetupHdmaChannel(7, BG1VOFS, HdmaTable1_TableAddr) + _SetupHdmaChannel(6, BG2VOFS, HdmaTable2_TableAddr) + _SetupHdmaChannel(5, BG3VOFS, HdmaTable3_TableAddr) + _SetupHdmaChannel(4, BG4VOFS, HdmaTable4_TableAddr) + + lda.b #HDMAEN.dma7 | HDMAEN.dma6 | HDMAEN.dma5 | HDMAEN.dma4 + sta.w HDMAEN + + + // Transfer readCounterDigits to OAM + variable _i = 0 + while _i < readCounterDigits_size { + ldx.w #_i * 2 + 1 + stx.w OAMADD + + lda.w readCounterDigits + _i + sta.w OAMDATA + stz.w OAMDATA // OAMDATA is a write-twice register when writing to the low-table + + _i = _i + 1 + } + + rts +} + + +HdmaTable1_TableAddr: + dw hdmaTable1_a, hdmaTable1_b + +HdmaTable2_TableAddr: + dw hdmaTable2_a, hdmaTable2_b + +HdmaTable3_TableAddr: + dw hdmaTable3_a, hdmaTable3_b + +HdmaTable4_TableAddr: + dw hdmaTable4_a, hdmaTable4_b + + +namespace Resources { + insert Bg_Tiles, "../../gen/test-patterns/scanline-bit-pattern.2bpp" + insert Bg_Tilemap, "../../gen/test-patterns/scanline-bit-pattern.tilemap" + insert Obj_Tiles, "../../gen/test-patterns/obj-digits-4bpp-tiles.tiles" + + Palette: + dw 0, 0, ToPalette( 6, 6, 0), ToPalette(31, 31, 0) // B (yellow) + dw 0, 0, ToPalette( 0, 8, 0), ToPalette( 0, 24, 0) // Y (green) + dw 0, 0, ToPalette( 6, 0, 6), ToPalette(31, 0, 31) // select + dw 0, 0, ToPalette( 6, 0, 6), ToPalette(31, 0, 31) // start + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // up + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // down + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // left + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // right + + // Shifting BG2 4 lines saves me 4 rol instructions + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + + dw 0, 0, ToPalette( 8, 0, 0), ToPalette(31, 0, 0) // A (red) + dw 0, 0, ToPalette( 0, 0, 8), ToPalette( 6, 6, 31) // X (blue) + dw 0, 0, ToPalette( 6, 4, 6), ToPalette(25, 20, 25) // L + dw 0, 0, ToPalette( 6, 4, 6), ToPalette(25, 20, 25) // R + + constant Palette.size = pc() - Palette + assert(Palette.size == 16 * 4 * 2) + + + insert ObjPalette, "../../gen/test-patterns/obj-digits-4bpp-tiles.pal" + + + Oam: + variable _i = 0 + while _i < readCounterDigits_size { + db 218 + _i * 6, 16, 0, 0 + + _i = _i + 1 + } + constant Oam.size = pc() - Oam +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/joypad_rapid_read_test.asm b/roms/snes-test-roms/src/hardware-tests/joypad_rapid_read_test.asm new file mode 100644 index 00000000..9ba157c1 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/joypad_rapid_read_test.asm @@ -0,0 +1,247 @@ +// A test that reads and displays 12 bits from controller port 1 every visible scanline. +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "JOYPAD RAPID READ" +define VERSION = 0 + + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(stack, 0x7e1f00, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + +// This test does not use interrupts +constant NmiHandler = BreakHandler.ISR + + +// BG1 & BG2 use the same tilemap and tiles +constant VRAM_BG12_TILES_WADDR = 0x1000 +constant VRAM_BG12_MAP_WADDR = 0x0000 + + +constant N_BITS = 12; +constant SPACING_BETWEEN_BITS = 12 +constant TOTAL_WIDTH = (N_BITS - 1) * SPACING_BETWEEN_BITS + 2 + +constant BG1_X_OFFSET = -(256 - TOTAL_WIDTH) / 2 +constant BG2_X_OFFSET = BG1_X_OFFSET - 4 * SPACING_BETWEEN_BITS + + +allocate(zpTmpByte, zeropage, 1) + +// Offset between the BGxVOFS register and the data I want to display on the scanline. +allocate(vofsOffset, zeropage, 1) + + +// DB = 0x80 +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + stz.w NMITIMEN + + + // Set PPU registers + + + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + lda.b #(VRAM_BG12_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + sta.w BG2SC + + lda.b #((VRAM_BG12_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift) | ((VRAM_BG12_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg2.shift) + sta.w BG12NBA + + lda.b #SETINI.overscan + sta.w SETINI + + lda.b #TM.bg1 | TM.bg2 + sta.w TM + + + lda.b #BG1_X_OFFSET + sta.w BG1HOFS + lda.b #BG1_X_OFFSET >> 16 + sta.w BG1HOFS + + lda.b #BG2_X_OFFSET + sta.w BG2HOFS + lda.b #BG2_X_OFFSET >> 16 + sta.w BG2HOFS + + + + ldx.w #VRAM_BG12_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg_Tilemap) + + + ldx.w #VRAM_BG12_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Bg_Tiles) + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + sep #$30 +a8() +i8() + + MainLoop: + // Wait until VBlank + - + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bpl - + + // Enable the display + lda.b #0x0f + sta.w INIDISP + + lda.b #-1 + sta.b vofsOffset + + // Wait until the start of scanline 0 + - + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bmi - + + + ScanlineLoop: + // Latch the joypad + lda.b #JOYSER0.latch + sta.w JOYSER0 + stz.w JOYSER0 + + + variable _i = 0 + while _i < 7 { + lda.w JOYSER0 + lsr + rol.b zpTmpByte + _i = _i + 1 + } + lda.w JOYSER0 + lsr + lda.b zpTmpByte + rol + clc + adc.b vofsOffset + tay + + + variable _i = 0 + while _i < 3 { + lda.w JOYSER0 + lsr + rol.b zpTmpByte + _i = _i + 1 + } + + lda.w JOYSER0 + lsr + lda.b zpTmpByte + and.b #0b111 + rol + // carry clear + adc.b vofsOffset + + // Wait for H-Blank + - + assert(HVBJOY.hBlank == 0x40) + bit.w HVBJOY + bvc - + + sta.w BG2VOFS + stz.w BG2VOFS + + sty.w BG1VOFS + stz.w BG1VOFS + + dec.b vofsOffset + + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bpl ScanlineLoop + + jmp MainLoop +} + + + +namespace Resources { + insert Bg_Tiles, "../../gen/test-patterns/scanline-bit-pattern.2bpp" + insert Bg_Tilemap, "../../gen/test-patterns/scanline-bit-pattern.tilemap" + + Palette: + dw 0, 0, ToPalette( 6, 6, 0), ToPalette(31, 31, 0) // B (yellow) + dw 0, 0, ToPalette( 0, 8, 0), ToPalette( 0, 24, 0) // Y (green) + dw 0, 0, ToPalette( 6, 0, 6), ToPalette(31, 0, 31) // select + dw 0, 0, ToPalette( 6, 0, 6), ToPalette(31, 0, 31) // start + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // up + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // down + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // left + dw 0, 0, ToPalette( 6, 6, 6), ToPalette(31, 31, 31) // right + + // Shifting BG2 4 lines saves me 4 rol instructions + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + dw 0, 0, 0, 0 + + dw 0, 0, ToPalette( 8, 0, 0), ToPalette(31, 0, 0) // A (red) + dw 0, 0, ToPalette( 0, 0, 8), ToPalette( 6, 6, 31) // X (blue) + dw 0, 0, ToPalette( 6, 4, 6), ToPalette(25, 20, 25) // L + dw 0, 0, ToPalette( 6, 4, 6), ToPalette(25, 20, 25) // R + + constant Palette.size = pc() - Palette + assert(Palette.size == 16 * 4 * 2) +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/mouse-cycle-sensitivity-test.asm b/roms/snes-test-roms/src/hardware-tests/mouse-cycle-sensitivity-test.asm new file mode 100644 index 00000000..79e1da21 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/mouse-cycle-sensitivity-test.asm @@ -0,0 +1,360 @@ +// Nintendo Mouse Cycle Sensitivity Test. +// +// Used to test: +// * The initial mouse sensitivity value. +// (Answer: It has an inconsistent starting value.) +// * Does the power-on uninitialised mouse sensitivity value increment by one +// after the first cycle-sensitivity command. +// (Answer: Yes, it increases by 1 for my Nintendo mouse.) +// * If I can increment the sensitivity more than once per latch +// (Answer: yes) +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "MOUSE SENSITIVITY" +define VERSION = 1 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rodata0, 0x818000, 0x81ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + +allocate(mouseData, zeropage, 1) + +allocate(mouseConnected, zeropage, 2) + +constant TEST_DATA_SIZE = 9 +allocate(mouseTestData, zeropage, TEST_DATA_SIZE) + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + TextBuffer.VBlank() +} + +include "../vblank_interrupts.inc" + + +// Manually read the 2nd byte of the mouse data +// +// OUT: mouseData[port] = 2nd mouse data byte +// +// DB = registers +macro ReadMouse(evaluate port) { + assert8a() + assert16i() + assert({port} == 0 || {port} == 1) + + stz.b mouseData + + // latch joypad ports + lda.b #JOYSER0.latch + sta.w JOYSER0 + stz.w JOYSER0 + + + variable _i = 0; + while _i < 8 { + lda.w JOYSER0 + {port} + + _i = _i + 1 + } + + variable _i = 0; + while _i < 8 { + lda.w JOYSER0 + {port} + lsr + rol.b mouseData + + _i = _i + 1 + } +} + + + +// Cycle the mouse sensitivity `nSpeedCycles`, then read the mouse sensitivity bits +// +// OUT: A = sensitivity +// DB = registers +macro CycleAndReadSensitivity(evaluate port, evaluate nSpeedCycles) { + assert8a() + assert16i() + assert({port} == 0 || {port} == 1) + + + // latch ports and cycle mouse speed + lda.b #JOYSER0.latch + sta.w JOYSER0 + + assert({nSpeedCycles} <= 10) + variable _i = {nSpeedCycles} + while _i > 0 { + lda.w JOYSER0 + {port} + _i = _i - 1 + } + + stz.w JOYSER0 + + + // Skip unneeded bits + variable _i = 0; + while _i < 10 { + lda.w JOYSER0 + {port} + nop // Required for good reads + nop // Required for good reads + + _i = _i + 1 + } + + // Read sensitivity bits + lda.w JOYSER0 + {port} + nop // Required for good reads + lsr + lda.w JOYSER0 + {port} + and.b #1 + bcc + + ora.b #2 + + +} + + +macro Test(evaluate port) { + assert({port} == 0 || {port} == 1) + + ReadMouse({port}) + + lda.b mouseData + and.b #JOYL.type.mask + cmp.b #JOYL.type.mouse + beq + + // not a mouse + stz.b mouseConnected + {port} + jmp Return{#} + + + + // Mouse connected + // Check if mouse was not connected on the previous read + lda.b mouseConnected + {port} + beq + + jmp Return{#} + + + + // Mouse connected + + lda.b #1 + sta.b mouseConnected + {port} + + +Mouse_Connected_{port}: + CycleAndReadSensitivity({port}, 1) + sta.b mouseTestData + 0 + + CycleAndReadSensitivity({port}, 1) + sta.b mouseTestData + 1 + + CycleAndReadSensitivity({port}, 1) + sta.b mouseTestData + 2 + + CycleAndReadSensitivity({port}, 1) + sta.b mouseTestData + 3 + + + CycleAndReadSensitivity({port}, 2) + sta.b mouseTestData + 4 + + CycleAndReadSensitivity({port}, 2) + sta.b mouseTestData + 5 + + CycleAndReadSensitivity({port}, 2) + sta.b mouseTestData + 6 + + CycleAndReadSensitivity({port}, 3) + sta.b mouseTestData + 7 + + CycleAndReadSensitivity({port}, 8) + sta.b mouseTestData + 8 + + assert(TEST_DATA_SIZE == 9) + + + // Print test data + + TextBuffer.PrintStringLiteral("P") + + lda.b #{port} + 1 + jsr TextBuffer.PrintOneHexDigitSpace_8A + + TextBuffer.PrintStringLiteral(" ") + + // Print original sensitivity bits + lda.b mouseData + lsr + lsr + lsr + lsr + and.b #3 + jsr TextBuffer.PrintOneHexDigitSpace_8A + + TextBuffer.PrintStringLiteral(" ") + + ldx.w #0 + - + phx + + cpx.w #4 + bne + + phx + TextBuffer.PrintStringLiteral(" ") + plx + + + + lda.b mouseTestData,x + jsr TextBuffer.PrintOneHexDigitSpace_8A + + plx + inx + cpx.w #TEST_DATA_SIZE + bcc - + + + ldx.w TextBuffer.cursorIndex + cpx.w #(TextBuffer.MARGIN_TOP + TextBuffer.N_TEXT_ROWS - 1) * TextBuffer.BUFFER_WIDTH - 1 + bcc + + TextBuffer.SetCursor(0, TEST_DATA_YPOS - 1) + + + jsr TextBuffer.NewLine + +Return{#}: +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + + TextBuffer.SetCursor(0, 1) + TextBuffer.PrintStringLiteral("Nintendo Mouse\nCycle Sensitivity Test v{VERSION}") + + TextBuffer.SetCursor(0, 4) + TextBuffer.PrintStringLiteral("Plug + unplug mouse\n\n") + + constant TEST_DATA_YPOS = 7 + + EnableVblankInterrupts_NoAutoJoypad() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + MainLoop: + jsr WaitFrame + + Test(0) + Test(1) + + jmp MainLoop +} + + +namespace Resources { + +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/object-dropout-test.asm b/roms/snes-test-roms/src/hardware-tests/object-dropout-test.asm new file mode 100644 index 00000000..e32136a2 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/object-dropout-test.asm @@ -0,0 +1,339 @@ +// Object dropout test +// +// CHANGELOG: +// +// v2: +// * Added RangeOverflowTest_Flipped test +// +// v3: +// * Added X256BugTest_TilesPerScanlineLimit +// * Moved some sprites down 4px on sprites-per-scanline test to show the expected sprite +// position if there were no sprite/tile per scanline limits +// +// +// SPDX-FileCopyrightText: © 2024 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "OBJECT DROPOUT TEST" +define VERSION = 3 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +constant VRAM_OBJ_TILES_WADDR = $6000 + +constant SCREEN_WIDTH = 256 +constant SCREEN_HEIGHT = 224 + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +// VBlank routine. +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() +} + +include "../vblank_interrupts.inc" + + + +// Setup PPU registers and load data to the PPU. +// +// REQUIRES: force-blank, PPU registers reset +a8() +i16() +code() +function SetupPpu { + stz.w BGMODE + + lda.b #OBSEL.size.s8_32 | (VRAM_OBJ_TILES_WADDR / OBSEL.base.walign) << OBSEL.base.shift + sta.w OBSEL + + ldx.w #VRAM_OBJ_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Obj_Tiles) + + stz.w CGADD + stz.w CGDATA + stz.w CGDATA + + lda.b #128 + sta.w CGADD + Dma.ForceBlank.ToCgram(Resources.Obj_Palette) + + stz.w OAMADDL + stz.w OAMADDH + Dma.ForceBlank.ToOam(Resources.Obj_Oam) + + lda.b #TM.obj + sta.w TM + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr SetupPpu + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + MainLoop: + jsr WaitFrame + jmp MainLoop +} + + + +namespace Resources { + insert Obj_Tiles, "../../gen/obj-tests/hex8-4bpp-tiles.tiles" + + +Obj_Palette: + macro _P(evaluate rgb) { + evaluate r = (({rgb} >> 16) & 0xff) >> 3 + evaluate g = (({rgb} >> 8) & 0xff) >> 3 + evaluate b = (({rgb} >> 0) & 0xff) >> 3 + + dw 0, ToPalette({r}, {g}, {b}), ToPalette({r}, {g}, {b}) + fill (16 - 3) * 2 + } + _P($cc3333) // hsl( 0, 60, 50) + _P($ccad33) // hsl( 45, 60, 50) + _P($80cc33) // hsl( 90, 60, 50) + _P($33cc59) // hsl(135, 60, 50) + _P($33cccc) // hsl(180, 60, 50) + _P($3359cc) // hsl(225, 60, 50) + _P($8033cc) // hsl(270, 60, 50) + _P($cc33a6) // hsl(315, 60, 50) + +constant Obj_Palette.size = pc() - Obj_Palette + + + +variable __nObjects = 0 + +macro _obj(evaluate x, evaluate y, evaluate tile) { + db {x}, {y}, {tile}, (({tile} & 7) << 2) + __nObjects = __nObjects + 1 +} + +macro _obj_flipped(evaluate x, evaluate y, evaluate tile) { + db {x}, {y}, {tile}, (({tile} & 7) << 2) | OamFormat.attr.hFlip | OamFormat.attr.vFlip + __nObjects = __nObjects + 1 +} + + +Obj_Oam: + // 32 sprites per scanline overflow test + namespace TimeOverflowTest { + constant N_SPRITES = 32 + 4 + constant N_LEFT_RIGHT = 8 + constant SPACING = 10 + constant C_SPACING = 2 + constant LEFT_X = 12 + constant Y_POS = 8 + + constant CENTER_INDEX = N_LEFT_RIGHT + constant RIGHT_INDEX = N_SPRITES - N_LEFT_RIGHT + constant N_CENTER = (N_SPRITES - N_LEFT_RIGHT * 2) + + constant RIGHT_X = SCREEN_WIDTH - N_LEFT_RIGHT * SPACING - LEFT_X + constant CENTER_X = (SCREEN_WIDTH - N_CENTER * C_SPACING - 8) / 2 + + variable _i = 0 + while _i < N_SPRITES { + if _i < CENTER_INDEX { + _obj(LEFT_X + _i * SPACING, Y_POS, _i) + } else if _i < RIGHT_INDEX { + _obj(CENTER_X + (_i - CENTER_INDEX) * C_SPACING, Y_POS + 4, _i) + } else { + _obj(RIGHT_X + (_i - RIGHT_INDEX) * SPACING, Y_POS, _i) + } + + _i = _i + 1 + } + } + + // 34 tile-slivers per scanline overflow test + namespace RangeOverflowTest { + constant N_SPRITES = 12 + constant X_SPACING = 16 + constant Y_SPACING = 3 + + constant X_START = (SCREEN_WIDTH - X_SPACING * (N_SPRITES - 1) - 32) / 2 + constant Y_START = 32 + + variable _i = 0 + while _i < N_SPRITES { + if _i < N_SPRITES / 2 { + variable _y = Y_START + _i * Y_SPACING + } else { + variable _y = Y_START + (N_SPRITES - _i) * Y_SPACING + } + + _obj(X_START + _i * X_SPACING, _y, _i) + + _i = _i + 1 + } + } + + // 34 tile-slivers per scanline overflow test + namespace RangeOverflowTest_Flipped { + constant N_SPRITES = 12 + constant X_SPACING = 16 + constant Y_SPACING = 3 + + constant X_START = (SCREEN_WIDTH - X_SPACING * (N_SPRITES - 1) - 32) / 2 + constant Y_START = 88 + + variable _i = 0 + while _i < N_SPRITES { + if _i < N_SPRITES / 2 { + variable _y = Y_START + _i * Y_SPACING + } else { + variable _y = Y_START + (N_SPRITES - _i) * Y_SPACING + } + + _obj_flipped(X_START + _i * X_SPACING, _y, _i) + + _i = _i + 1 + } + } + + // If a sprite has an X position of 256, it counts towards the 32 sprites per scanline limit + namespace X256BugTest_SpritesPerScanlineLimit { + constant N_OFFSCREEN = 8 + constant N_ONSCREEN = 32 + + constant X_SPACING = 8 + + constant Y_POS = 144 + + variable _i = 0 + while _i < N_OFFSCREEN { + _obj(256, Y_POS + 4, _i) + _i = _i + 1 + } + while _i < N_OFFSCREEN + N_ONSCREEN { + _obj((_i - N_OFFSCREEN) * X_SPACING, Y_POS, _i) + _i = _i + 1 + } + } + + // If a sprite has an X position of 256, all tiles in the sprite count towards the 34 tile-slivers per scanline overflow test + namespace X256BugTest_TilesPerScanlineLimit { + constant N_OFFSCREEN = 4 + constant N_ONSCREEN = 8 + constant N_SPRITES = N_OFFSCREEN + N_ONSCREEN + + constant X_SPACING = 32 + + constant Y_POS = X256BugTest_SpritesPerScanlineLimit.Y_POS + 32 + 8 + + assert(N_SPRITES < 32) + + variable _i = 0 + while _i < N_ONSCREEN { + _obj(_i * X_SPACING, Y_POS, _i) + _i = _i + 1 + } + while _i < N_SPRITES { + _obj(256, Y_POS + 4, _i) + _i = _i + 1 + } + } + + fill (128 - __nObjects) * 4, -16 + +Obj_OamHiTable: + namespace TimeOverflowTest { + assert(N_SPRITES % 4 == 0) + fill N_SPRITES / 4, 0 + } + namespace RangeOverflowTest { + assert(N_SPRITES % 4 == 0) + fill N_SPRITES / 4, %10101010 + } + namespace RangeOverflowTest_Flipped { + assert(N_SPRITES % 4 == 0) + fill N_SPRITES / 4, %10101010 + } + namespace X256BugTest_SpritesPerScanlineLimit { + assert(N_OFFSCREEN % 4 == 0) + fill N_OFFSCREEN / 4, %11110101 // half large and half small + + assert(N_ONSCREEN % 4 == 0) + fill N_ONSCREEN / 4, 0 + } + namespace X256BugTest_TilesPerScanlineLimit { + assert(N_ONSCREEN % 4 == 0) + fill N_ONSCREEN / 4, %10101010 + + assert(N_OFFSCREEN % 4 == 0) + fill N_OFFSCREEN / 4, %11110101 // half large and half small + } + fill (128 - __nObjects) / 4, 0 + +constant Obj_Oam.size = pc() - Obj_Oam +assert(Obj_Oam.size == 544) + +} + diff --git a/roms/snes-test-roms/src/hardware-tests/reset-position-test.asm b/roms/snes-test-roms/src/hardware-tests/reset-position-test.asm new file mode 100644 index 00000000..0b617d6a --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/reset-position-test.asm @@ -0,0 +1,270 @@ +// Reset position test +// +// This test determines the PPU position at reset using the PPU H/V counters and spinloop cycle +// counting. +// +// SPDX-FileCopyrightText: © 2023 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2023 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "RESET POSITION TEST" +define VERSION = 1 +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan + + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80bfff) +createDataBlock(rodata0, 0x80c000, 0x80ff80) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(stack, 0x7e0100, 0x7e01ff) +createRamBlock(lowram, 0x7e0200, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant DISPLAY_HEIGHT = 224 + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../reset_registers.inc" +include "../textbuffer.inc" + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + +constant N_HBLANKS_TO_COUNT = 36 + + +// zero-page temporary variables (used by TextBuffer) +allocate(zpTmp0, zeropage, 2) +allocate(zpTmpPtr, zeropage, 3) + + +// Test result variables +allocate(startOpvct, lowram, 2) +allocate(startOphct, lowram, 2) + +allocate(hblankCountAtVBlank, lowram, 2) + +allocate(cycleCounts, lowram, N_HBLANKS_TO_COUNT) + + +// DP = 0 +// DB = 0 +// SP = 0x01ff +// e = 1 +// d = 0 +// i = 1 +a8() +i8() +code() +function ResetHandler { + // Latch PPU counters as early as possible + lda.w SLHV + + clc + xce + + + // Start spin-loop cycle counting to H-blank start time + rep #$30 +a16() + lda.w #HVBJOY & 0xff00 + tcd +// DP = 0x4200 + + sep #$30 +a8() +i8() + + variable _i = 0 + while _i < N_HBLANKS_TO_COUNT { + ldx.b #0 + + if _i != 0 { + // Wait until the end of H-Blank + assert(HVBJOY.hBlank == 0x40) + - + inx + bit.b HVBJOY + bvs - + } + + // Wait until the start of H-Blank + assert(HVBJOY.hBlank == 0x40) + - + inx + bit.b HVBJOY + bvc - + + stx.w cycleCounts + _i + + _i = _i + 1 + } + + + rep #$30 +a16() +i16() + lda.w #0 + tcd +// DP = 0 + + sep #$20 +a8() + + + // Save PPU H/V counters + lda.w OPVCT + sta.w startOpvct + lda.w OPVCT + and.b #OPVCT.mask >> 8 + sta.w startOpvct + 1 + + lda.w OPHCT + sta.w startOphct + lda.w OPHCT + and.b #OPHCT.mask >> 8 + sta.w startOphct + 1 + + + // Measure the number of h-blanks until the start of VBlank + + // Assumes the PPU is not in H-Blank at the start of this loop + ldx.w #N_HBLANKS_TO_COUNT + Loop: + // Wait until the start of H-Blank + assert(HVBJOY.hBlank == 0x40) + - + bit.w HVBJOY + bvc - + + // Wait until the end of H-Blank + assert(HVBJOY.hBlank == 0x40) + - + bit.w HVBJOY + bvs - + + inx + + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bpl Loop + + stx.w hblankCountAtVBlank + + + + // Setup PPU + jsr ResetRegisters + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Palette) + + + + // Print test results + jsr TextBuffer.ClearCharBufferAndResetCursor + jsr TextBuffer.ClearAttrBuffer + + TextBuffer.PrintStringLiteral("\nReset position test v{VERSION}\n\n\n") + + TextBuffer.PrintStringLiteral("OPVCT: 0x") + ldy.w startOpvct + jsr TextBuffer.PrintHexSpace_16Y + + TextBuffer.PrintStringLiteral(" OPHCT: 0x") + ldy.w startOphct + jsr TextBuffer.PrintHexSpace_16Y + + TextBuffer.PrintStringLiteral("\n\nHBlanks until VBlank: 0x") + ldy.w hblankCountAtVBlank + jsr TextBuffer.PrintHexSpace_16Y + + + TextBuffer.PrintStringLiteral("\n\n\nLoops until HBlank:\n\n") + + ldx.w #0 + - + phx + + lda.w cycleCounts,x + jsr TextBuffer.PrintHexSpace_8A + + plx + inx + cpx.w #N_HBLANKS_TO_COUNT + bcc - + + jsr TextBuffer.TransferFontAndBuffersToVram + + + + lda.b #0xf + sta.w INIDISP + + - + wai + bra - +} + + +rodata(rodata0) +Palette: + // BG1 palette + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) + +constant Palette.size = pc() - Palette + + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/rumble-controller-latching.asm b/roms/snes-test-roms/src/hardware-tests/rumble-controller-latching.asm new file mode 100644 index 00000000..b54925b8 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/rumble-controller-latching.asm @@ -0,0 +1,436 @@ +// A test to determine what the Rumble Controller does when the controller is +// latched (pin 3 (OUT0) of the controller port is pulsed). +// +// Mesen, MiSTer and the PDF spec document have different behaviours when +// `JOYOUT.bit0` is pulsed. +// +// * The [2.0 spec doc](https://github.com/LimitedRunGames-Tech/snes-rumble/tree/main/docs) +// says the 16-bit buffer should be cleared. +// It does not state if the motors should stop. +// +// * SNES_MiSTer clears the 16-bit buffer and stops the motors. +// https://github.com/MiSTer-devel/SNES_MiSTer/blob/1613eea55235eb5f0aca16c73c5200161ced3cb2/rtl/ioport.sv#L74 +// +// * Mesen does neither. +// https://github.com/nesdev-org/MesenCE/blob/4b8669d34bba11b4dae057ac0b234714a7f7638d/Core/SNES/Input/SnesRumbleController.cpp#L28 +// +// +// This test contains 4 different write tests to determine the latching +// behaviour of a real Rumble Controller: +// +// * **D-PAD*: Writes 16 bits of data after auto-read has completed. +// +// * **ABXY**: Writes 8 bits of data, latches the controller, +// then writes the final 8 bits of data. +// +// * **L/R**: Write 16 bits of data then latches the controller. +// +// * **SELECT**: Tests if the rumble controller clears the internal 16-bit +// shift register after activating the rumble motors. +// +// It writes `$727200` to the shift register. +// * If the shift register is cleared after activating the motors, the SR +// will be `$0000` and the motors will remain active. +// * If the shift register is not cleared after activating the motors, the +// SR will be `$7200` and the motors will stop. +// +// If the controller continues to rumble after the buttons have been released, +// the **START** button will send a no-rumble command to the rumble controller. +// +// +// SPDX-FileCopyrightText: © 2026 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2024 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "RUMBLE CONTROLLER" +define VERSION = 2 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rodata0, 0x818000, 0x81ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + + +constant RUMBLE_SENTRY = %01110010 + + +// Write the rumble data normally. +// +// IN: A = rumble data +a8() +i16() +// DB = $80 +code() +function WriteNormally { + pha + + lda.b #RUMBLE_SENTRY + jsr WriteIoByte + + pla + jmp WriteIoByte +} + + +// Write the 8-bit rumble sentry, latch the controller then write +// the 8-bit rumble data. +// +// IN: A = rumble data +a8() +i16() +// DB = $80 +code() +function Write8LatchWrite8 { + pha + + lda.b #RUMBLE_SENTRY + jsr WriteIoByte + + // Delay + ldx.w #200 + - + dex + bne - + + + // Latch the joypad inbetween the two writes + lda.b #JOYSER0.latch + sta.w JOYSER0 + stz.w JOYSER0 + + // Delay + ldx.w #200 + - + dex + bne - + + pla + jmp WriteIoByte +} + + +// Write the rumble data normally, them immediately latch the controller. +// +// IN: A = rumble data +a8() +i16() +// DB = $80 +code() +function Write16Latch { + pha + + lda.b #RUMBLE_SENTRY + jsr WriteIoByte + + pla + jsr WriteIoByte + + // Latch the joypad + lda.b #JOYSER0.latch + sta.w JOYSER0 + stz.w JOYSER0 + + rts +} + + +// Test if the internal 16 bit shift register is cleared after +// the rumble motors are active (SELECT test). +// +// IN: A = rumble data +a8() +i16() +// DB = $80 +code() +function SrClearOnRumbleTest { + lda.b #RUMBLE_SENTRY + jsr WriteIoByte + + lda.b #RUMBLE_SENTRY + jsr WriteIoByte + + // Write 8 zero bits really quickly + stz.w WRIO + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + bit.w JOYSER0 + + lda.b #0xff + sta.w WRIO + + rts +} + + +// Writes 8 bits of data to the rumble controller. +// +// NOTE: This is not the fastest way to write the data. +// It is designed to only modify bit 6 of WRIO. +// +// IN: A = byte +a8() +i16() +// DB = $80 +code() +function WriteIoByte { + sep #$30 +a8() +i8() + + ldy.b #8 + Loop: + asl + ldx.b #~$40 + bcc + + ldx.b #$ff + + + stx.w WRIO + bit.w JOYSER0 + + dey + bne Loop + + ldx.b #$ff + stx.w WRIO + + rep #$10 +i16() + rts +} + + +TestInstructions: + db "Rumble Controller Latch Test" + db "v{VERSION}\n" + db "\n" + db "\n" + db "\n" + db "D-PAD: Write normally\n" + db "\n" + db "ABXY: Latch after 8 bits\n" + db "\n" + db "L/R: Latch after 16 bits\n" + db "\n" + db "SELECT: SR cleared test\n" + db "\n" + db "START: Stop rumble\n" + db 0 + + +a8() +i16() +// DB = $80 +code() +function RunTest { + lda.w joypadCurrent + 1 + bit.b #JOYH.up + beq + + lda.b #0xff + jmp WriteNormally + + + bit.b #JOYH.down + beq + + lda.b #0x22 + jmp WriteNormally + + + bit.b #JOYH.left + beq + + lda.b #0x0f + jmp WriteNormally + + + bit.b #JOYH.right + beq + + lda.b #0xf0 + jmp WriteNormally + + + + bit.b #JOYH.b + beq + + lda.b #0x22 + jmp Write8LatchWrite8 + + + bit.b #JOYH.y + beq + + lda.b #0x0f + jmp Write8LatchWrite8 + + + + + lda.w joypadCurrent + + bit.b #JOYL.x + beq + + lda.b #0xff + jmp Write8LatchWrite8 + + + bit.b #JOYL.a + beq + + lda.b #0xf0 + jmp Write8LatchWrite8 + + + + bit.b #JOYL.l + beq + + lda.b #0x0f + jmp Write16Latch + + + bit.b #JOYL.r + beq + + lda.b #0xf0 + jmp Write16Latch + + + + + lda.w joypadCurrent + 1 + bit.b #JOYH.select + beq + + jmp SrClearOnRumbleTest + + + bit.b #JOYH.start + beq + + lda.b #0 + jmp WriteNormally + + + + rts +} + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + TextBuffer.VBlank() +} + +define VBLANK_READS_JOYPAD = 1 + +include "../vblank_interrupts.inc" + + + +au() +iu() +// DB = $80 +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + + TextBuffer.SetCursor(0, 1) + TextBuffer.PrintString(TestInstructions) + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + MainLoop: + jsr WaitFrame + + jsr RunTest + + jmp MainLoop +} + + +namespace Resources { + +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + diff --git a/roms/snes-test-roms/src/hardware-tests/vram-mid-scanline-test.asm b/roms/snes-test-roms/src/hardware-tests/vram-mid-scanline-test.asm new file mode 100644 index 00000000..b8afafa8 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/vram-mid-scanline-test.asm @@ -0,0 +1,173 @@ +// A simple test to see what happens to VRAM writes outside of the +// Vertical Blanking period. +// +// Test output: +// * WHITE: VRAM writes are ignored +// * RED tiles: VRAM writes change VRAM (and/or corrupt VRAM) +// * BLANK: Test crashed +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "VRAM MID SCANLINE TEST" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + +constant VRAM_BG1_TILES_WADDR = 0x1000 +constant VRAM_BG1_MAP_WADDR = 0x0000 + + +// This demo does not use VBlank Interrupts. +constant NmiHandler = BreakHandler + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + + // Setup PPU + + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + jsr ClearVramOamAndCgram + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + + // Transfer tiles to VRAM + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVram(Resources.Tiles_2bpp) + + + // Transfer palettes to CGRAM + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + + // Enable display, full brightness. + lda.b #0x0f + sta.w INIDISP + + + + MainLoop: + // Wait until VBlank + assert(HVBJOY.vBlank == 0x80) + - + lda.w HVBJOY + bpl - + + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + // Wait until VBlank ends + assert(HVBJOY.vBlank == 0x80) + - + lda.w HVBJOY + bmi - + + constant LOOP_COUNT = 3072 + assert(LOOP_COUNT * 10 < 1340 / 8 * 200) + ldy.w #0x1234 + ldx.w #LOOP_COUNT + CorruptionLoop: + sty.w VMDATA + + dex + bne CorruptionLoop + + + // Assert not in VBlank + assert(HVBJOY.vBlank == 0x80) + lda.w HVBJOY + bpl + + brk #HVBJOY + + + + + jmp MainLoop +} + + +namespace Resources { + + +Tiles_2bpp: + fill 16, 0xffff +constant Tiles_2bpp.size = pc() - Tiles_2bpp + + +Palette: + variable i = 0 + while i < 256 { + if i == 3 { + dw ToPalette(31, 31, 31) + } else { + dw ToPalette(31, 0, 0) + } + i = i + 1 + } +constant Palette.size = pc() - Palette +} + +finalizeMemory() + + diff --git a/roms/snes-test-roms/src/hardware-tests/wrmpyb-in-flight.asm b/roms/snes-test-roms/src/hardware-tests/wrmpyb-in-flight.asm new file mode 100644 index 00000000..d6373842 --- /dev/null +++ b/roms/snes-test-roms/src/hardware-tests/wrmpyb-in-flight.asm @@ -0,0 +1,651 @@ +// This code tests what happens when you write to the `WRMPYB` register while a previous +// multiplication is still being processed by the 5A22. Each test input is processed 8 times, +// with a differing number of CPU cycles between `WEMPYB` writes. +// +// +// TEST INPUTS: +// A = value to write to `WRMPYA` +// B1 = the first write to `WRMPYB` +// B2 = the second write to `WRMPYB` after 2-9 CPU cycles +// +// TEST OUTPUTS: +// 2cy = The `RDMPY` output when there are 2 CPU cycles between `WRMPYB` writes +// (after waiting 8+ cycles after the second `WRMPYB` write) +// ... +// 9cy = The `RDMPY` output when there are 9 CPU cycles between `WRMPYB` writes +// +// +// Controls: +// B / Y - change selected value +// D-Pad - adjust selected value +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define ROM_NAME = "WRMPYB IN FLIGHT" +define VERSION = 0 + +architecture wdc65816-strict + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) +createCodeBlock(rodata0, 0x818000, 0x81ffff) + +createRamBlock(zeropage, 0x00, 0xff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0xfeffff) + + +constant VRAM_BG1_MAP_WADDR = 0x0000 +constant VRAM_BG1_TILES_WADDR = 0x1000 + +constant VRAM_TEXTBUFFER_MAP_WADDR = VRAM_BG1_MAP_WADDR +constant VRAM_TEXTBUFFER_TILES_WADDR = VRAM_BG1_TILES_WADDR + + +define USES_IRQ_INTERRUPTS + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" +include "../textbuffer.inc" + + +// zero-page temporary word variables +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) +allocate(zpTmp2, zeropage, 2) +allocate(zpTmp3, zeropage, 2) + +// zero-page temporary far pointer +allocate(zpTmpPtr, zeropage, 3) + + + +constant N_TESTS = 10 + +constant BYTES_PER_TEST = 19 + + + +// Buffer to store the text results to +allocate(results, lowram, 1024) +assert(N_TESTS * BYTES_PER_TEST < 1024) + + + +// The three input values for the test +// (3x uint8) +allocate(test_a, lowram, 1) +allocate(test_b1, lowram, 1) +allocate(test_b2, lowram, 1) + +constant testInputs = test_a +constant testInputs.size = 3 + + +// The currently selected value for controller input +// (byte index into testInputs) +allocate(selectedInput, lowram, 1) + + + +// Loop Counter when printing results +// (uint8) +allocate(loopCounter, lowram, 1) + + + +// Taken from Anomie's timing document +constant DRAM_REFRESH_CYCLE = 538 + +// Horizontal IRQ position. +// +// This position is after the DRAM refresh to ensure DRAM refresh does not interfere with the test. +// +// If `IRQ_X_POS` is between 53 and 62 (inclusive), the test output changes every frame as the +// DRAM refresh occurs in the middle of one or more tests. +// +constant IRQ_X_POS = DRAM_REFRESH_CYCLE / 4 + 10 + + +// IRQ ISR +// +// Does nothing. +// Used to synchronise the test to ensure the DRAM refresh does not occur in the middle of the test. +// +// DP unknown +// DB unknown +au() +iu() +code() +function IrqHandler { + sep #$20 +a8() + pha + lda.l TIMEUP + pla + + rti +} + + + +// VBlank routine +// +// REQUIRES: 8 bit A, 16 bit Index, DB = 0x80, DP = 0 +macro VBlank() { + assert8a() + assert16i() + + TextBuffer.VBlank() +} + +define VBLANK_READS_JOYPAD + +include "../vblank_interrupts.inc" + + + +// Wait 8 cycles and log the value of `RDMPY` to `WMDATA` +// +// KEEP: A, Y +// +// DB = registers +// DP = 0x4200 +inline RunOneTest.__WaitAndLogRDMPY_dp4200() { + assert16a() + assert8i() + + // Wait 8 cycles + nop + nop + nop + nop + + // MUST NOT CHANGE the A or Y registers + + // Log `RDMPY` to `WMDATA` + ldx.b RDMPYL + stx.w WMDATA + ldx.b RDMPYH + stx.w WMDATA +} + + + +// Process a single `WRMPYB` test, storing the results in `WMDATA` +// +// REQUIRES: H-IRQ enabled with HTIME = IRQ_X_POS +// +// INPUT: A = WRMPYA +// INPUT: X = First WRMPYB value +// INPUT: Y = Second WRMPYB value +// INPUT: WMADD = Buffer to store the results into +// +// OUTPUT: WMADD = buffer after test results +// +// DB = registers +a8() +i8() +code() +function RunOneTest { + // Access multiplication registers via direct page + pea WRMPYA & 0xff00 + pld +// DP = $4200 + + // Using Y to retrieve `RDMPY` (and to log inputs) + + // Log inputs + sta.w WMDATA // WRMPYA + stx.w WMDATA // First WRMPYB write + sty.w WMDATA // Second WRMPYB write + + + // Transfer X to high byte of A (keep low byte of A unchanged) + xba + txa + xba + + rep #$20 +a16() + + // AA = `WRMPYA` and first `WRMPYB` + // Y = second `WRMPYB` value + + + // Using `wai` to sleep until after the DRAM-refresh to ensure the DRAM-refresh does + // not interfere with the test. + + + // Wait 2 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + sty.b WRMPYB // 2 cycles reading `sty.b $03` + __WaitAndLogRDMPY_dp4200() + + + // Wait 3 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + sty.w WRMPYB // 3 cycles reading `sty.w $4203` + __WaitAndLogRDMPY_dp4200() + + + // Wait 4 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + sty.b WRMPYB // 2 cycles reading `sty.b $03` + __WaitAndLogRDMPY_dp4200() + + + // Wait 5 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + sty.w WRMPYB // 3 cycles reading `sty.w $4203` + __WaitAndLogRDMPY_dp4200() + + + // Wait 6 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + nop // 2 cycles + sty.b WRMPYB // 2 cycles reading `sty.b $03` + __WaitAndLogRDMPY_dp4200() + + + // Wait 7 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + nop // 2 cycles + sty.w WRMPYB // 3 cycles reading `sty.w $4203` + __WaitAndLogRDMPY_dp4200() + + + // Wait 8 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + nop // 2 cycles + nop // 2 cycles + sty.b WRMPYB // 2 cycles reading `sty.b $03` + __WaitAndLogRDMPY_dp4200() + + + // Wait 9 cycles between WRMPYB writes + wai + sta.b WRMPYA // Also sets WRMPYB + nop // 2 cycles + nop // 2 cycles + nop // 2 cycles + sty.w WRMPYB // 3 cycles reading `sty.w $4203` + __WaitAndLogRDMPY_dp4200() + + + sep #$30 +a8() +i8() + pea 0 + pld +// DP = 0 + rts +} + + + +// Preform the `WRMPYB` tests +// +// DB = registers +a8() +i16() +code() +function RunTests { + + // Set `WMDATA` address to `results` + ldx.w #results + lda.b #results >> 16 + stx.w WMADD + sta.w WMADD + 2 + + + // Wait until the start of a new frame + - + assert(HVBJOY.vBlank == 0x80) + bit.w HVBJOY + bmi - + + + // Setup IRQ interrupts + + ldx.w #IRQ_X_POS + stx.w HTIME + + // Enable IRQ Interrupts (and disable NMI interrupts) + lda.b #NMITIMEN.hCounter + sta.w NMITIMEN + + cli + wai + + + sep #$30 +a8() +i8() + assert(N_TESTS == 1 + 9) + + lda.w test_a + ldx.w test_b1 + ldy.w test_b2 + jsr RunOneTest + + variable _i = 0 + while _i < 9 { + lda.w test_a + ldx.w test_b1 + ldy.b #0x80 >> _i + jsr RunOneTest + + _i = _i + 1 + } + + + rep #$10 +i16() + + // Disable IRQ interrupts and re-enable VBlank interrupts + stz.w NMITIMEN + EnableVblankInterrupts() + + rts +} + + + +// Print the results to the TextBuffer. +// +// DB = registers +a8() +i16() +code() +function PrintResults { + + // Set `WMDATA` address to `results` + ldx.w #results + lda.b #results >> 16 + stx.w WMADD + sta.w WMADD + 2 + + + // Print the "selectedInput" cursor + TextBuffer.SetCursor(0, 0) + + lda.b #0 + CursorLoop: + sta.w loopCounter + + cmp.w selectedInput + bne + + TextBuffer.PrintStringLiteral("__ ") + bra ++ + + + TextBuffer.PrintStringLiteral(" ") + + + + lda.w loopCounter + inc + cmp.b #testInputs.size + bcc CursorLoop + + + // Print header + TextBuffer.SetCursor(0, 1) + TextBuffer.PrintStringLiteral(" A B1 B2 2cy 3cy 4cy 5cy") + TextBuffer.PrintStringLiteral(" 6cy 7cy 8cy 9cy") + + jsr TextBuffer.NewLine + + + // Print test results + lda.b #N_TESTS + sta.w loopCounter + + Loop: + assert(BYTES_PER_TEST == 3 + 8 * 2) + + jsr _PrintByte + jsr _PrintByte + jsr _PrintByte + + jsr _PrintWord + jsr _PrintWord + jsr _PrintWord + jsr _PrintWord + + TextBuffer.PrintStringLiteral(" ") + + jsr _PrintWord + jsr _PrintWord + jsr _PrintWord + jsr _PrintWord + + dec.w loopCounter + bne Loop + + rts +} + + + +// Print the next byte from `WMDATA` to the TextBuffer +// +// INPUT: WMADD = byte to print +// OUTPUT: WMADD = data after byte +// +// DB = registers +a8() +i16() +code() +function _PrintByte { + lda.w WMDATA + jmp TextBuffer.PrintHexSpace_8A +} + + + +// Print the next word from `WMDATA` to the TextBuffer +// +// INPUT: WMADD = byte to print +// OUTPUT: WMADD = data after byte +// +// DB = registers +a8() +i16() +code() +function _PrintWord { + lda.w WMDATA + xba + lda.w WMDATA + xba + tay + jmp TextBuffer.PrintHexSpace_16Y +} + + + +// Process control pad +// +// DB = registers +a8() +i16() +code() +function ProcessJoypad { + sep #$10 +i8() + ldx.w selectedInput + + // Process B and Y buttons + lda.w joypadPressed + 1 + bit.b #JOYH.b + beq + + inx + + + bit.b #JOYH.y + beq + + dex + bpl + + ldx.b #testInputs.size - 1 + + + + cpx.b #testInputs.size + bcc + + ldx.b #0 + + + stx.w selectedInput + + + // Process D-Pad + + lda.w joypadPressed + 1 + bit.b #JOYH.left + beq + + dec.w testInputs,x + + + + bit.b #JOYH.right + beq + + inc.w testInputs,x + + + + bit.b #JOYH.up + beq + + lda.w testInputs,x + clc + adc.b #0x10 + sta.w testInputs,x + + lda.w joypadPressed + 1 + + + + bit.b #JOYH.down + beq + + lda.w testInputs,x + sec + sbc.b #0x10 + sta.w testInputs,x + + lda.w joypadPressed + 1 + + + + rep #$10 +i16() + + rts +} + + + +au() +iu() +code() +function Main { + rep #$30 + sep #$20 +a8() +i16() + // Setup PPU + lda.b #INIDISP.force | 0x0f + sta.w INIDISP + + lda.b #BGMODE.mode0 + sta.w BGMODE + + lda.b #TM.bg1 + sta.w TM + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + stz.w CGADD + Dma.ForceBlank.ToCgram(Resources.Palette) + + jsr TextBuffer.InitAndTransferToVram + + + EnableVblankInterrupts() + + jsr WaitFrame + + lda.b #0x0f + sta.w INIDISP + + + // Set initial test values + lda.b #0xff + sta.w test_a + + lda.b #0xff + sta.w test_b1 + sta.w test_b2 + + + MainLoop: + jsr WaitFrame + + jsr ProcessJoypad + jsr RunTests + jsr PrintResults + + jmp MainLoop +} + + +namespace Resources { + +Palette: + dw ToPalette(0, 0, 0) + dw ToPalette(31, 31, 31) +constant Palette.size = pc() - Palette +} + +finalizeMemory() + + + diff --git a/roms/snes-test-roms/src/nmi_handler.inc b/roms/snes-test-roms/src/nmi_handler.inc new file mode 100644 index 00000000..b6df2c26 --- /dev/null +++ b/roms/snes-test-roms/src/nmi_handler.inc @@ -0,0 +1,73 @@ +// nmi_handler.inc +// =============== +// +// NMI Interrupt Service Routine. +// +// SPDX-FileCopyrightText: © 2020 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2020 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +// NMI ISR +// +// This NMI handler is designed to be 4 master cycles slower on +// non-interlace frames to help stabilize the horizontal position in +// which the IRQ ISR is executed. +// +// REQUIRES: fastROM enabled +au() +iu() +code() +function NmiHandler { + assert((pc() >> 16) == 0x80 && (pc() & 0xffff) >= 0x8000) + assert(ROM_SPEED.{ROM_SPEED} == ROM_SPEED.fast) + + jml Nmi_Fast +Nmi_Fast: + + sep #$20 +a8() + pha + + assert(STAT78.interlace == 0x80) + bit.w STAT78 + bmi + + // 2 fast (branch not taken) + // 4 fast (2x nop) + // 3 fast (bra) + // = (9*6) = 54 master cycles + nop + nop + bra ++ + + + // Have to use long addressing, DP and DB is unknown + + // 3 fast (branch taken) + // 4 fast, 1 slow (lda long WorkRAM) + // = (7*6 + 1*8) = 50 master cycles + lda.b 0x7e0000 + + + + pla + rti +} diff --git a/roms/snes-test-roms/src/reset_handler.inc b/roms/snes-test-roms/src/reset_handler.inc new file mode 100644 index 00000000..47d4902f --- /dev/null +++ b/roms/snes-test-roms/src/reset_handler.inc @@ -0,0 +1,211 @@ +// reset_handler.inc +// ================= +// +// Code to being the SNES into a consistent state upon reset. +// +// This code requires: +// * A ROM block called `code` that is accessible by DB 0 +// * A RAM block called `stack` that is accessible by DB 0 +// +// This code also requires the following optional defines: +// +// * ROM_SPEED - the speed of the ROM (slow (default), fast) +// +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +include "reset_registers.inc" + + +au() +iu() +code() + +// ensure ResetHandler is accessible by interrupt vectors +assert(pc() & 0x3fffff < 0x010000) +assert(pc() & 0x00ffff >= 0x008000) + +constant STACK_SIZE = __MEMORY__.ramBlocks.stack.end - __MEMORY__.ramBlocks.stack.start + 1 +constant STACK_BOTTOM = __MEMORY__.ramBlocks.stack.end +assert((STACK_BOTTOM & 0xffff) < 0x2000) +assert((STACK_BOTTOM >> 16) == 0 || (STACK_BOTTOM >> 16) == 0x7e) + +allocate(STACK_TOP, stack, STACK_SIZE) + + +// Reset the SNES, initializing the registers and clearing all the memory. +function ResetHandler { + + jml reset +reset: + + sei + clc + xce // Switch to native mode + + rep #$38 // 16 bit A, 16 bit Index, Decimal mode off +a16() +i16() + ldx.w #STACK_BOTTOM + txs // Setup stack + + lda.w #$0000 + tcd // Reset Direct Page + + sep #$20 +a8() + + // Set Data Bank + + lda.b #REGISTER_DB + pha + plb + + + // ROM access time + if ROM_SPEED.{ROM_SPEED} == 0x10 { + lda.b #MEMSEL.fastrom + sta.w MEMSEL + + } else { + stz.w MEMSEL + } + + + // This will also disable screen and interrupts + jsr ClearVramOamAndCgram + + + // Clear the WRAM + // Setup DMA Channel 0 for WRAM + ldx.w #0 + stx.w WMADDL + stz.w WMADDH + + ldy.w #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one | (WMDATA << 8) + sty.w DMAP0 // also sets BBAD0 + + // X = 0 + stx.w DAS0 + + ldx.w #SnesHeader.EmptyBytes + stx.w A1T0 + stz.w A1B0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // DSA0 is 0, no need to set it again + sta.w MDMAEN + + jsr ResetRegisters + + jml Main +} + + +// Clears the VRAM, OAM and CGRAM. +// +// Fills the VRAM and CGRAM with 0 bytes. +// Moves all of the OAM sprites offscreen. +// +// NOTE: This routine immediately sets screen blank +// +// REQUIRES: none +// MODIFIES: Disables Interrupts and HDMA, enables Force Blank +au() +iu() +code() +function ClearVramOamAndCgram { + php + phd + phb + + pea (REGISTER_DB << 8) | $20 + plp + plb +a8() +i16() + + // Disable interrupts and HDMA + stz.w NMITIMEN + stz.w HDMAEN + + lda.b #INIDISP.force + sta.w INIDISP + + + // Fill VRAM with 0 bytes + ldx.w #0 + ldy.w #0 + jsr Dma.ForceBlank.ClearVram + + + // Fill palette with 0 bytes + ldx.w #0 + ldy.w #0 + jsr Dma.ForceBlank.ClearCgram + + + // Move all objects in the OAM offscreen + rep #$30 +a16() + lda.w #$2100 + tcd + + sep #$30 +a8() +i8() + stz.b OAMADDL + stz.b OAMADDH + + ldx.b #$80 + ldy.b #240 + + lda.b #128 +- + stx.b OAMDATA // X + sty.b OAMDATA // Y + stz.b OAMDATA + stz.b OAMDATA // Character + Flags + + dec + bne - + + lda.b #%01010101 + ldx.b #128 / 4 +- + sta.b OAMDATA // Data table + dex + bne - + + plb + pld + plp + rts +} + +// vim: ft=bass-65816 ts=4 sw=4 et: + diff --git a/roms/snes-test-roms/src/reset_registers.inc b/roms/snes-test-roms/src/reset_registers.inc new file mode 100644 index 00000000..9cffcd3a --- /dev/null +++ b/roms/snes-test-roms/src/reset_registers.inc @@ -0,0 +1,135 @@ +// reset_registers.inc +// =================== +// +// A subroutine to reset the registers to a good initial state. +// +// SPDX-FileCopyrightText: © 2016 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2016 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +// Reset the registers to a good initial state. +// +// REQUIRES: Requires 6 bytes of stack space +au() +iu() +code() +function ResetRegisters { + php + phd + + rep #$30 +a16() + lda.w #0x2100 + tcd + + sep #$30 +a8() +i8() + + // Disable interrupts and HDMA + // A = 0 + sta.l NMITIMEN + sta.l HDMAEN + + // Reset IO pins + lda.b #0xff + sta.l WRIO + + + // Force Screen Blank + lda.b #INIDISP.force + sta.b INIDISP + + + stz.b OBSEL + + + // Registers $210d - $2114 + // BG Scroll Locations - Write twice + // horizontal offset set to 0 + // vertical offset set to -1 + ldx.b #0x2114 - 0x210d - 1 + lda.b #0xff +- + stz.b 0x0d,x + stz.b 0x0d,x + sta.b 0x0e,x + sta.b 0x0e,x + dex + dex + bpl - + + // Registers $2105 - $210c + // BG settings and VRAM base addresses + ldx.b #$210c - $2105 +- + stz.b $05,x + dex + bpl - + + // Skipping Mode 7 as any programmer using that mode + // will set those registers anyway. + + // Increment VRAM by 1 word on reading/writing the high byte of VRAM + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.b VMAIN + + // Registers $2123 - $2133 + // Window Settings, BG/OBJ designation, Color Math, Screen Mode + // All disabled + ldx.b #0x2133 - 0x2123 +- + stz.b 0x23,x + dex + bpl - + + + lda.b #CGWSEL.prevent.always + sta.b CGWSEL + + // Set Fixed color data to black + lda.b #COLDATA.plane.all | 0 + sta.b COLDATA + + + + // reset all of the DMA registers + // Registers $4300 - $437f + rep #$20 +a16() + lda.w #0x4300 + tcd + + ldx.b #0x7e +- + stz.b 0,x + dex + dex + bpl - + + pld + plp + rts +} + diff --git a/roms/snes-test-roms/src/textbuffer.inc b/roms/snes-test-roms/src/textbuffer.inc new file mode 100644 index 00000000..27a3c7c4 --- /dev/null +++ b/roms/snes-test-roms/src/textbuffer.inc @@ -0,0 +1,742 @@ +// textbuffer.inc +// ============== +// +// A simple split-buffer text buffer for printing monospace text and hexadecimal numbers. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +namespace TextBuffer { + + +// The bank to store the font and the string literals. +if !{defined TextBuffer.STRING_BLOCK} { + define STRING_BLOCK = rodata0 +} + + +constant BUFFER_WIDTH = 32 +constant BUFFER_HEIGHT = 32 +constant N_BUFFER_CELLS = BUFFER_WIDTH * BUFFER_HEIGHT + + + +if !{defined CUSTOM_TEXTBUFFER_MARGINS} { + constant MARGIN_LEFT = 2 + constant MARGIN_RIGHT = 2 + + constant MARGIN_TOP = 1 + constant N_TEXT_ROWS = 26 +} + +assert(MARGIN_LEFT >= 0) +assert(MARGIN_RIGHT >= 0) +assert(MARGIN_TOP >= 0) +assert(N_TEXT_ROWS >= 0) + +constant N_TEXT_COLUMNS = BUFFER_WIDTH - MARGIN_LEFT - MARGIN_RIGHT + +constant STARTING_CURSOR_INDEX = MARGIN_TOP * BUFFER_WIDTH + MARGIN_LEFT + +assert(MARGIN_LEFT + N_TEXT_COLUMNS <= BUFFER_WIDTH) +assert(MARGIN_TOP + N_TEXT_ROWS <= BUFFER_HEIGHT) + + + +// Set default attribute to high priority, palette 0 +constant DEFAULT_ATTR = TilemapH.order + + + +// If zero, `charBuffer` will be transferred to VRAM on the next VBlank. +// +// (byte flag) +allocate(charBufferClean, lowram, 1) + + +// If zero, `attrBuffer` will be transferred to VRAM on the next VBlank. +// +// (byte flag) +allocate(attrBufferClean, lowram, 1) + + +// Current cursor position +// +// (word index into `charBuffer`) +allocate(cursorIndex, lowram, 2) + +// Cursor position at the end of the current line +// +// (word index into `charBuffer`) +allocate(endOfLineIndex, lowram, 2) + + + + +// Character buffer +// +// The low-byte of the Tilemap entries. +// +// (u8[N_BUFFER_CELLS]) +allocate(charBuffer, wram7e, N_BUFFER_CELLS) +constant charBuffer.size = N_BUFFER_CELLS + + +// Character attribute buffer +// +// The high-byte of the Tilemap entries, handles palette and order. +// +// (u8[N_BUFFER_CELLS]) +allocate(attrBuffer, wram7e, N_BUFFER_CELLS) +constant attrBuffer.size = N_BUFFER_CELLS + + + + +// Font and Character Mapping +// ========================== + +// 1-bpp font tiles +rodata(rodata0) + insert Font_1bpp, "../gen/textbuffer/font-1bpp-tiles.tiles" + + include "../resources/textbuffer/font-1bpp-map.inc" + + + +// Initialise the TextBuffer subsystem and transfer font/buffers to VRAM +// +// NOTE: This function will not transfer a palette to CGRAM. +// +// REQUIRES: In force-blank +// +// DB = registers +a8() +i16() +code() +function InitAndTransferToVram { + jsr ClearCharBufferAndResetCursor + jsr ClearAttrBuffer + + jmp TransferFontAndBuffersToVram +} + + + +// Clear the character buffer and reset the cursor position +// +// DB = Low-RAM +a8() +i16() +code() +function ClearCharBufferAndResetCursor { + ldx.w #STARTING_CURSOR_INDEX + stx.w cursorIndex + + ldx.w #STARTING_CURSOR_INDEX + N_TEXT_COLUMNS + stx.w endOfLineIndex + + rep #$30 +a16() + + assert(charBuffer.size % 2 == 0) + ldx.w #charBuffer.size - 2 + lda.w #0 + Loop: + sta.l charBuffer,x + dex + dex + bpl Loop + + sep #$20 +a8() + + // Transfer `charBuffer` to VRAM on the next VBlank + stz.w charBufferClean + + rts +} + + + +// Clear the attribute buffer +// +// DB = Low-RAM +a8() +i16() +code() +function ClearAttrBuffer { + + rep #$30 +a16() + + assert(attrBuffer.size % 2 == 0) + ldx.w #attrBuffer.size - 2 + lda.w #DEFAULT_ATTR | (DEFAULT_ATTR << 8) + Loop: + sta.l attrBuffer,x + dex + dex + bpl Loop + + sep #$20 +a8() + + // Transfer `attrBuffer` to VRAM on the next VBlank + stz.w attrBufferClean + + rts +} + + + +// Transfer the font and the buffers to VRAM +// +// REQUIRES: force-blank +// +// DB = registers +a8() +i16() +code() +function TransferFontAndBuffersToVram { + + // Use VMAIN to convert 1bpp font to 2bpp tile data + ldx.w #VRAM_TEXTBUFFER_TILES_WADDR + stx.w VMADD + Dma.ForceBlank.ToVramL(Font_1bpp) + + ldx.w #VRAM_TEXTBUFFER_TILES_WADDR + ldy.w #Font_1bpp.size + jsr Dma.ForceBlank.ClearVramH + + + // Transfer buffers to VRAM + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVramL(charBuffer) + + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + Dma.ForceBlank.ToVramH(attrBuffer) + + + // Mark buffers are unchanged + lda.b #1 + sta.w charBufferClean + sta.w attrBufferClean + + rts +} + + + +// TextBuffer VBlank routine. +// +// Transfers buffers to VRAM if they have changed. +// +// In: V-Blank +// +// DB = 0x80 +macro VBlank() { + assert8a() + assert16i() + + // Transfer `charBuffer` to VRAM if `charBufferClean` is zero + lda.w TextBuffer.charBufferClean + bne SkipCharBuffer + // Transfer `charBuffer` to the low-bytes of VRAM at word-address `VRAM_TEXTBUFFER_MAP_WADDR`. + + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + + assert(VMAIN.incrementMode.low | VMAIN.increment.by1 == 0) + stz.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAL << 8) + stx.w DMAP0 // also set BBAD0 + + ldx.w #TextBuffer.charBuffer + stx.w A1T0 + lda.b #TextBuffer.charBuffer >> 16 + sta.w A1B0 + + ldx.w #TextBuffer.charBuffer.size + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // A is non-zero + sta.w TextBuffer.charBufferClean +SkipCharBuffer: + + + // Transfer `attrBuffer` to VRAM if `attrBufferClean` is zero + lda.w TextBuffer.attrBufferClean + bne SkipAttrBuffer + // Transfer `attrBuffer` to the high-bytes of VRAM at word-address `VRAM_TEXTBUFFER_MAP_WADDR`. + + ldx.w #VRAM_TEXTBUFFER_MAP_WADDR + stx.w VMADD + + lda.b #VMAIN.incrementMode.high | VMAIN.increment.by1 + sta.w VMAIN + + ldx.w #DMAP.direction.toPpu | DMAP.transfer.one | (VMDATAH << 8) + stx.w DMAP0 // also set BBAD0 + + ldx.w #TextBuffer.attrBuffer + stx.w A1T0 + lda.b #TextBuffer.attrBuffer >> 16 + sta.w A1B0 + + ldx.w #TextBuffer.attrBuffer.size + stx.w DAS0 + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + // A is non-zero + sta.w TextBuffer.attrBufferClean +SkipAttrBuffer: +} + + + +// Set the cursor to a fixed location +// +// DB = low-RAM +macro SetCursor(evaluate x, evaluate y) { + assert16i() + + assert({x} >= 0 && {x} < TextBuffer.N_TEXT_COLUMNS) + assert({y} >= 0 && {y} < TextBuffer.N_TEXT_ROWS) + + ldx.w #({y} + TextBuffer.MARGIN_TOP) * TextBuffer.BUFFER_WIDTH + ({x} + TextBuffer.MARGIN_LEFT) + stx.w TextBuffer.cursorIndex + + ldx.w #({y} + TextBuffer.MARGIN_TOP) * TextBuffer.BUFFER_WIDTH + (TextBuffer.MARGIN_LEFT + TextBuffer.N_TEXT_COLUMNS) + stx.w TextBuffer.endOfLineIndex +} + + + +// Move the cursor to a given location +// +// INPUT: X = x-position (u8) +// INPUT: Y = y-position (u8) +// +// DB = low-RAM +a8() +iu() +code() +function SetCursor { +constant _tmpWord = zpTmp0 + +assertPowerOfTwo(BUFFER_WIDTH) +assertPowerOfTwo(BUFFER_HEIGHT) +constant CURSOR_INDEX_ROW_MASK = (BUFFER_HEIGHT - 1) * BUFFER_WIDTH + + php + + sep #$10 +i8() + + // clear high byte of A + tdc + + txa + cmp.b #N_TEXT_COLUMNS + bcc + + lda.b #0 + clc + + + // carry clear + adc.b #MARGIN_LEFT + + sta.b _tmpWord + stz.b _tmpWord + 1 + + + tya + cmp.b #N_TEXT_ROWS + bcc + + lda.b #0 + clc + + + // carry clear + adc.b #MARGIN_TOP + + rep #$30 +a16() + // A.h clear (from `tdc` above) + assert(BUFFER_WIDTH == 1 << 5) + asl + asl + asl + asl + asl + ora.b _tmpWord + + sta.w cursorIndex + + and.w #CURSOR_INDEX_ROW_MASK + ora.w #MARGIN_LEFT + N_TEXT_COLUMNS + sta.w endOfLineIndex + + + plp + rts +} + + + +// Advance the cursor to the next line and clear the new line. +// +// DB = low-RAM +a8() +i16() +code() +function NewLine { + +assertPowerOfTwo(BUFFER_WIDTH) +assertPowerOfTwo(BUFFER_HEIGHT) +constant CURSOR_INDEX_ROW_MASK = (BUFFER_HEIGHT - 1) * BUFFER_WIDTH + +constant LAST_ROW = MARGIN_TOP + N_TEXT_ROWS - 1 +assert(LAST_ROW * BUFFER_WIDTH + MARGIN_LEFT + N_TEXT_COLUMNS <= N_BUFFER_CELLS) + +// `NewLine` does not work correctly if there is no margin on the right. +assert(MARGIN_RIGHT >= 1) + + + rep #$20 +a16() + lda.w cursorIndex + and.w #CURSOR_INDEX_ROW_MASK + clc + adc.w #BUFFER_WIDTH + MARGIN_LEFT + + cmp.w #(LAST_ROW + 1) * BUFFER_WIDTH + bcc + + lda.w #STARTING_CURSOR_INDEX + + + sta.w cursorIndex + tax + + // Clear the line and advance X to `endOfLineIndex` + assert(N_TEXT_COLUMNS % 2 == 0) + ldy.w #N_TEXT_COLUMNS / 2 + lda.w #Font.SPACE | (Font.SPACE << 8) + Loop: + sta.l charBuffer,x + inx + inx + dey + bne Loop + + // X = cursorIndex + N_TEXT_COLUMNS + stx.w endOfLineIndex + + sep #$20 +a8() + rts +} + + + +// Print a string from a label +// +// DB = low-RAM +macro PrintString(label) { + assert8a() + assert16i() + + ldx.w #{label} + lda.b #({label}) >> 16 + jsr TextBuffer.PrintString +} + + + +// Print a string literal +// +// DB = low-RAM +inline PrintStringLiteral(s) { + assert8a() + assert16i() + + pushBlock() + rodata({TextBuffer.STRING_BLOCK}) + String{#}: + db {s}, 0 + popBlock() + + ldx.w #String{#} + lda.b #String{#} >> 16 + jsr TextBuffer.PrintString +} + + + +// Print a string +// +// INPUT: A:X - far address of string +// +// NOTE: Uses `zpTmpPtr` +// +// DB = low-RAM +a8() +i16() +code() +function PrintString { + stx.b zpTmpPtr + sta.b zpTmpPtr + 2 + + + lda [zpTmpPtr] + beq EmptyString + + ldx.w cursorIndex + + ldy.w #0 + Loop: + assert(Font.NEW_LINE + 1 == Font.FIRST_INVALID_CHARACTER) + cmp.b #Font.NEW_LINE + beq NewLineCharacter + bcc + + lda.b #' ' + + + + sta.l charBuffer,x + inx + + // Test if the cursor is at the end of the line + cpx.w endOfLineIndex + bcc + + NewLineCharacter: + // Confirm this works with very long strings:: + phy + jsr NewLine + ldx.w cursorIndex + ply + + + + iny + lda [zpTmpPtr],y + bne Loop + + + stx.w cursorIndex + + // Transfer `charBuffer` to VRAM on the next VBlank + stz.w charBufferClean + +EmptyString: + rts +} + + + +// Print a single hexadecimal digit, followed by a space or new line +// +// INPUT: A - 8 bit value +// +// DB = low-RAM +a8() +i16() +code() +function PrintOneHexDigitSpace_8A { +constant _tmp = zpTmp0 + + assert(Font.ZERO + 10 == Font.CAPITAL_A) + + ldx.w cursorIndex + inx + cpx.w endOfLineIndex + bcc + + sta.b _tmp + jsr NewLine + ldx.w cursorIndex + inx + lda.b _tmp + + + +AfterX: + and.b #0x0f + clc + adc.b #Font.ZERO + sta.l charBuffer - 1,x + + + // Print a space or new line + inx + cpx.w endOfLineIndex + bcc + + jsr NewLine + bra ++ + + + stx.w cursorIndex + + lda.b #Font.SPACE + sta.l charBuffer - 1,x + + + + // Transfer `charBuffer` to VRAM on the next VBlank + stz.w charBufferClean + + rts +} + + + +// Print an 8-bit hexadecimal string, followed by a space or new line +// +// INPUT: A - 8 bit value +// +// DB = low-RAM +a8() +i16() +code() +function PrintHexSpace_8A { +constant _tmp = zpTmp0 + + assert(Font.ZERO + 10 == Font.CAPITAL_A) + + ldx.w cursorIndex + inx + cpx.w endOfLineIndex + bcc + + sta.b _tmp + jsr NewLine + ldx.w cursorIndex + inx + lda.b _tmp + + + inx + +AfterX: + tay + + lsr + lsr + lsr + lsr + clc + adc.b #Font.ZERO + sta.l charBuffer - 2,x + + + tya + and.b #0x0f + clc + adc.b #Font.ZERO + sta.l charBuffer - 1,x + + + // Print a space or new line + inx + cpx.w endOfLineIndex + bcc + + jsr NewLine + bra ++ + + + stx.w cursorIndex + + lda.b #Font.SPACE + sta.l charBuffer - 1,x + + + + // Transfer `charBuffer` to VRAM on the next VBlank + stz.w charBufferClean + + rts +} + + + +// Print a 16-bit hexadecimal string, followed by a space or new line +// +// INPUT: Y - 16 bit value +// +// DB = low-RAM +a8() +i16() +code() +function PrintHexSpace_16Y { + sty.b zpTmp0 + +FallThrough: +} + + + +// Print a 16-bit hexadecimal string, followed by a space or new line +// +// INPUT: Y - 16 bit value +// +// DB = low-RAM +function PrintHexSpace_16_zpTmp0 { + assert(PrintHexSpace_16Y.FallThrough == pc()) + + assert(Font.ZERO + 10 == Font.CAPITAL_A) + + ldx.w cursorIndex + inx + inx + inx + cpx.w endOfLineIndex + bcc + + jsr NewLine + ldx.w cursorIndex + inx + inx + inx + + + inx + + + lda.b zpTmp0 + 1 + lsr + lsr + lsr + lsr + clc + adc.b #Font.ZERO + sta.l charBuffer - 4,x + + + lda.b zpTmp0 + 1 + and.b #0x0f + clc + adc.b #Font.ZERO + sta.l charBuffer - 3,x + + + lda.b zpTmp0 + jmp PrintHexSpace_8A.AfterX +} + +} + diff --git a/roms/snes-test-roms/src/vblank_interrupts.inc b/roms/snes-test-roms/src/vblank_interrupts.inc new file mode 100644 index 00000000..f355bd88 --- /dev/null +++ b/roms/snes-test-roms/src/vblank_interrupts.inc @@ -0,0 +1,252 @@ +// vblank_interrupts.inc +// ===================== +// +// A simple NMI interrupt handler. +// +// NOTE: This file must be included after a `VBlank()` macro is defined and before the +// `EnableVblankInterrupts()` macro is invoked. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + + +// Execute V-Blank Routine flag +// +// The VBlank routine will be executed if this value is non-zero. +// +// (byte flag) +allocate(__vBlankFlag, lowram, 1) + + +// Frame counter. Incremented every NMI interrupt +// (uint32) +allocate(frameCounter, lowram, 4) + + + +if {defined VBLANK_READS_JOYPAD} { + // The current state of the joypad + allocate(joypadCurrent, lowram, 2) + + // The newly pressed buttons on this frame + allocate(joypadPressed, lowram, 2) +} + + + +// Enable VBlank interrupts. +// +// NOTE: This macro disabled IRQ interrupts. +// +// This is a macro, it should only be included once inside the Setup routine. +// +// REQUIRES: DB access low-RAM +macro EnableVblankInterrupts() { + + // Do not process VBlank routine on the next VBlank Interrupt + stz.w __vBlankFlag + + // Clear NMI flag + lda.w RDNMI + + lda.b #NMITIMEN.vBlank | NMITIMEN.autoJoy + sta.w NMITIMEN +} + + + +// Enable VBlank interrupts with auto joypad read disabled +// +// NOTE: This macro disables IRQ interrupts and Auto-Joypad read. +// +// This is a macro, it should only be included once inside the Setup routine. +// +// REQUIRES: DB access low-RAM +macro EnableVblankInterrupts_NoAutoJoypad() { + + // Do not process VBlank routine on the next VBlank Interrupt + stz.w __vBlankFlag + + // Clear NMI flag + lda.w RDNMI + + lda.b #NMITIMEN.vBlank + sta.w NMITIMEN +} + + + +// Wait until the start of a new display frame +// (or the end of the VBlank routine (NmiHandler)). +// +// REQUIRES: NMI enabled, DB access low-RAM +au() +iu() +code() +function WaitFrame { + php + sep #$20 +a8() + + lda.b #1 + sta.w __vBlankFlag + + + // Loop until `__vBlankFlag` is clear + Loop: + wai + + lda.w __vBlankFlag + bne Loop + + plp + + rts +} + + + +// NMI ISR +// +// Invokes `VBlank()` macro if the main-loop is inside `WaitFrame`. +au() +iu() +code() +function NmiHandler { + // Ensure we are in bank 0x00 or 0x80 + assert((pc() >> 16) | 0x80 == 0x80) + + + // Jump to FastROM bank (if this ISR is in a FastROM address) + if pc() >> 16 == 0x80 { + jml FastRomNmiHandler + FastRomNmiHandler: + } + + + // Save CPU state + rep #$30 +a16() +i16() + pha + phx + phy + phd + phb + + + phk + plb +// DB = 0x00 or 0x80 + + lda.w #0 + tcd +// DP = 0 + + + sep #$20 +a8() + + // Only execute the VBlank routine if `__vBlankFlag` is non-zero. + // (prevents corruption during force-blank setup or a lag frame) + lda.w __vBlankFlag + bne + + jmp EndVBlankRoutine + + + // Clear VBlank flag. + // * Prevents the NMI ISR from executing VBlank code during lag-frames + // * Signals to the main-loop that the VBlank routine has been executed. + // + // (Can be placed after the `VBlank` macro if the VBlank macro WILL NEVER take more than + // 260 scanlines of execution time) + stz.w __vBlankFlag + + + // Execute VBlank routine + VBlank() + + + assert8a() + + + if {defined VBLANK_READS_JOYPAD} { + // Wait until Auto-Joy is ready + lda.b #HVBJOY.autoJoy + - + assert8a() + bit.w HVBJOY + bne - + + rep #$30 + a16() + i16() + + // Test joypad type bits and ignore anything that is not a standard controller + lda.w JOY1 + bit.w #JOY.type.mask + beq + + lda.w #0 + + + + // Save current and retrieve old `joypadCurrent` + tay + lda.w joypadCurrent + sty.w joypadCurrent + + // Calculate newly pressed buttons + // A = old joypadCurrent + eor.w #0xffff + and.w joypadCurrent + sta.w joypadPressed + } + +au() +iu() +EndVBlankRoutine: + + rep #$30 +a16() +i16() + + // Increment 32 bit frameCounter + inc.w frameCounter + bne + + inc.w frameCounter + 2 + + + + + // Restore CPU state + assert16a() + assert16i() + plb + pld + ply + plx + pla + + rti +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/_vmain-tile-buffer-demo.inc b/roms/snes-test-roms/src/vmain-address-remapping/_vmain-tile-buffer-demo.inc new file mode 100644 index 00000000..c51157a1 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/_vmain-tile-buffer-demo.inc @@ -0,0 +1,806 @@ +// Common code for the VMAIN address remapping test roms. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define MEMORY_MAP = LOROM +define ROM_SIZE = 1 +define ROM_SPEED = fast +define REGION = Japan +define VERSION = 1 + + +architecture wdc65816-strict + + +include "../common.inc" + + +createCodeBlock(code, 0x808000, 0x80ffaf) + +createRamBlock(zeropage, 0x000000, 0x0000ff) +createRamBlock(lowram, 0x7e0100, 0x7e1f7f) +createRamBlock(stack, 0x7e1f80, 0x7e1fff) +createRamBlock(wram7e, 0x7e2000, 0x7effff) + + +include "../reset_handler.inc" +include "../break_handler.inc" +include "../dma_forceblank.inc" + + + +if !{defined MODE7} { + // VRAM Map + constant VRAM_BG1_TILES_WADDR = 0x0000 + constant VRAM_BG1_MAP_WADDR = 0x7c00 // 32x32 + + // The size of a single tilemap + constant TILEMAP_WIDTH = 32 + constant TILEMAP_HEIGHT = 32 + + constant BUFFER_WIDTH_PX = 256 + constant BUFFER_HEIGHT_PX = 224 + +} else { + // Mode 7 + + constant BITS_PER_PIXEL = 8 + constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + constant M7_TILEMAP_WIDTH = 128 + constant M7_TILEMAP_HEIGHT = 128 + + constant BUFFER_WIDTH_PX = 128 + constant BUFFER_HEIGHT_PX = 112 +} + +constant BUFFER_SIZE = BUFFER_WIDTH_PX * BUFFER_HEIGHT_PX * BITS_PER_PIXEL / 8 + + + +// Temporary zero-page word variables +// Used by the SetPixel routine +// (word) +allocate(zpTmp0, zeropage, 2) +allocate(zpTmp1, zeropage, 2) + + +// `SetPixel` pixel colour. +// (zeropage byte) +allocate(SetPixel.pixelColour, zeropage, 1) + + + +// Byte variables used by DrawLine routine +allocate(DrawLine.zpTmpB0, zeropage, 1) +allocate(DrawLine.zpTmpB1, zeropage, 1) +allocate(DrawLine.zpTmpB2, zeropage, 1) +allocate(DrawLine.zpTmpB3, zeropage, 1) +allocate(DrawLine.zpTmpB4, zeropage, 1) +allocate(DrawLine.zpTmpB5, zeropage, 1) + +// Word variables used by the DrawLine routine +allocate(DrawLine.zpWord0, zeropage, 2) +allocate(DrawLine.zpWord1, zeropage, 2) +allocate(DrawLine.zpWord2, zeropage, 2) +allocate(DrawLine.zpWord3, zeropage, 2) +allocate(DrawLine.zpWord4, zeropage, 2) + + +// Current position in `LineList` +// (word index) +allocate(lineIndex, lowram, 2) + + + + +// Tile buffer +allocate(tileBuffer, wram7e, BUFFER_SIZE) +constant tileBuffer.size = BUFFER_SIZE + + + +// VBlank routine +macro VBlank() { + // Empty - no VBlank routine +} + +include "../vblank_interrupts.inc" + + + +au() +iu() +code() +function Main { + sei + + rep #$30 + sep #$20 +a8() +i16() + phk + plb +// DB = 0x80 + + + // Force blank + lda.b #INIDISP.force | 0xf + sta.w INIDISP + + + // Set PPU registers + + if !{defined MODE7} { + // Set BGMODE + if BITS_PER_PIXEL == 1 || BITS_PER_PIXEL == 2 { + lda.b #BGMODE.mode0 + } else if BITS_PER_PIXEL == 4 { + lda.b #BGMODE.mode1 + } else if BITS_PER_PIXEL == 8 { + lda.b #BGMODE.mode3 + } else { + error "Unknown BITS_PER_PIXEL" + } + sta.w BGMODE + + + lda.b #(VRAM_BG1_MAP_WADDR / BGXSC.base.walign) << BGXSC.base.shift | BGXSC.map.s32x32 + sta.w BG1SC + + lda.b #(VRAM_BG1_TILES_WADDR / BG12NBA.walign) << BG12NBA.bg1.shift + sta.w BG12NBA + + } else { + // Mode 7 + + lda.b #7 + sta.w BGMODE + + stz.w M7SEL + + + // Initialize Mode 7 matrix + lda.b #MODE7_MATRIX_A + sta.w M7A + lda.b #MODE7_MATRIX_A >> 8 + sta.w M7A + lda.b #MODE7_MATRIX_B + sta.w M7B + lda.b #MODE7_MATRIX_B >> 8 + sta.w M7B + lda.b #MODE7_MATRIX_C + sta.w M7C + lda.b #MODE7_MATRIX_C >> 8 + sta.w M7C + lda.b #MODE7_MATRIX_D + sta.w M7D + lda.b #MODE7_MATRIX_D >> 8 + sta.w M7D + + stz.w M7X + stz.w M7X + stz.w M7Y + stz.w M7Y + } + + lda.b #TM.bg1 + sta.w TM + + + + lda.b #0x7e + pha + plb +// DB = 0x7e + jsr ClearTileBuffer + jsr DrawImage + phk + plb +// DB = 0x80 + + + + // Transfer data to PPU + stz.w CGADD + Dma.ForceBlank.ToCgram(Palette) + + jsr GenerateTilemap + + jsr TransferTileBufferToVram + + + EnableVblankInterrupts() + jsr WaitFrame + + // Enable screen, full brightness (in VBlank) + lda.b #15 + sta.w INIDISP + + + MainLoop: + wai + bra MainLoop +} + + +if !{defined MODE7} { + +// Generate the BG1 tilemap in VRAM. +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +a8() +i16() +code() +function GenerateTilemap { + +constant N_TILES = tileBuffer.size / BITS_PER_PIXEL / 8 +constant BUFFER_TILE_HEIGHT = N_TILES / TILEMAP_WIDTH + +assert(BUFFER_TILE_HEIGHT < TILEMAP_HEIGHT) + + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + + ldx.w #VRAM_BG1_MAP_WADDR + stx.w VMADD + + + // Fill tilemap with sequential tiles + ldx.w #0 + - + stx.w VMDATA + inx + cpx.w #N_TILES + bne - + + + // Fill the rest of the tilemap with zeros + ldx.w #0 + ldy.w #(TILEMAP_HEIGHT - BUFFER_TILE_HEIGHT) * TILEMAP_WIDTH + - + stx.w VMDATA + dey + bne - + + rts +} + +} + + + +// Clear the tile buffer +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function ClearTileBuffer { + rep #$30 +a16() + + assert(tileBuffer.size % 2 == 0) + + ldx.w #tileBuffer.size - 2 + Loop: + stz.w tileBuffer,x + dex + dex + bne Loop + + stz.w tileBuffer + + sep #$20 +a8() + rts +} + + + +// Draw an image to the tile buffer +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function DrawImage { + + ldx.w #0 + Loop: + stx.w lineIndex + jsr DrawLine + + ldx.w lineIndex + inx + inx + inx + inx + inx + cpx.w #LineList.size + bcc Loop + + rts +} + + + +// Draw a pixel to the buffer (with bounds checking) +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position +// Y = y-position +// A = pixel colour +a8() +i16() +code() +function SetPixelWithBoundsChecking { + // Clip index registers to 8 bits + sep #$10 +i8() + cpy.b #BUFFER_HEIGHT_PX + rep #$10 +a16() + bcs + + jmp SetPixel + + + rts +} + + +code() +namespace DrawLine { +a8() +i16() +InvalidInput: + rts +} + + + +// Draw a line to the tile buffer +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = index into `LineList` +a8() +i16() +code() +function DrawLine { + +constant _xPos = zpTmpB0 +constant _yPos = zpTmpB1 +constant _targetX = zpTmpB2 +constant _targetY = zpTmpB3 + +constant _iy = zpTmpB4 + + +// Word variables +// _dx and _dy are word variables as they simplify the creation of _a, _b & _d below +constant _dx = zpWord0 +constant _dy = zpWord1 + +constant _a = zpWord2 +constant _b = zpWord3 +constant _d = zpWord4 + + + // Line drawing code is based on Bresenham's line algorithm. + + // Load variables from Line List (exiting early if y1 or y2 id out of bounds) + lda.l LineList.x1,x + sta.b _xPos + + lda.l LineList.y1,x + cmp.b #BUFFER_HEIGHT_PX + bcs InvalidInput + sta.b _yPos + + lda.l LineList.x2,x + sta.b _targetX + + lda.l LineList.y2,x + cmp.b #BUFFER_HEIGHT_PX + bcs InvalidInput + sta.b _targetY + + lda.l LineList.colour,x + sta.b SetPixel.pixelColour + + + + // if _xPos >= _targetX: + // swap position and target + // _dx = abs(_xPos - targetX) + lda.b _xPos + sec + sbc.b _targetX + bcc + + // _xPos >= _targetX + sta.b _dx + + // Swap position and target + assert16i() + assert(_xPos + 1 == _yPos) + assert(_targetX + 1 == _targetY) + ldx.b _xPos + ldy.b _targetX + + sty.b _xPos + stx.b _targetX + + bra ++ + + + + // _xPos < _targetX + + eor.b #0xff + inc + sta.b _dx + + + stz.b _dx + 1 + + + // _dy = abs(_yPos - targetY) + // _iy = _yPos < targetY ? 1 : -1 + lda.b _yPos + sec + sbc.b _targetY + bcc + + // _yPos >= _targetY + sta.b _dy + + lda.b #-1 + + bra ++ + + + + // _yPos < _targetY + + eor.b #0xff + inc + sta.b _dy + + lda.b #1 + + + sta.b _iy + stz.b _dy + 1 + + + + lda.b _dx + cmp.b _dy + bcc SteepLine + // Shallow Line dx >= dy + + // _a = (_dy - _dx) * 2 + // _b = _dy * 2 + // _d = _b - dx + rep #$30 + a16() + lda.b _dy + sec + sbc.b _dx + asl + sta.b _a + + lda.b _dy + asl + sta.b _b + + sec + sbc.b _dx + sta.b _d + + + a16() + ShallowLoop: + sep #$20 + a8() + + ldx.b _xPos + ldy.b _yPos + jsr SetPixel + + lda.b _xPos + cmp.b _targetX + beq Return + + inc + sta.b _xPos + + rep #$20 + a16() + + lda.b _d + bmi + + beq + + // _d > 0 + clc + adc.b _a + sta.b _d + + sep #$20 + a8() + lda.b _yPos + clc + adc.b _iy + sta.b _yPos + cmp.b #BUFFER_HEIGHT_PX + bcs Return + + bra ShallowLoop + + + + a16() + // _d <= 0 + clc + adc.b _b + sta.b _d + + bra ShallowLoop + + + SteepLine: + // dx < dy + + // _a = (_dx - _dy) * 2 + // _b = _dx * 2 + // _d = _b - dy + rep #$30 + a16() + lda.b _dx + sec + sbc.b _dy + asl + sta.b _a + + lda.b _dx + asl + sta.b _b + + sec + sbc.b _dy + sta.b _d + + a16() + SteepLoop: + sep #$20 + a8() + ldx.b _xPos + ldy.b _yPos + jsr SetPixel + + lda.b _yPos + cmp.b _targetY + beq Return + + clc + adc.b _iy + sta.b _yPos + + rep #$20 + a16() + + lda.b _d + bmi + + beq + + // _d > 0 + clc + adc.b _a + sta.b _d + + sep #$20 + a8() + // No need to preform a bounds check on _xPos + inc.b _xPos + + bra SteepLoop + + a16() + + + // _d <= 0 + clc + adc.b _b + sta.b _d + + bra SteepLoop + +a8() +Return: + rts +} + + + +// Palette +// ======= + +if BITS_PER_PIXEL == 1 { + Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 31, 31) + + fill 512 - 2 * 2, 0x1c + constant Palette.size = pc() - Palette + + constant N_COLORS = 1 + + +} else if BITS_PER_PIXEL == 2 { + Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 31, 31) + dw ToPalette(31, 0, 0) + dw ToPalette( 0, 31, 0) + + fill 512 - 2 * 4, 0x1c + constant Palette.size = pc() - Palette + + constant N_COLORS = 4 + + +} else if BITS_PER_PIXEL == 4 { + // ::TODO better palette:: + Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 31, 31) + dw ToPalette(31, 0, 0) + dw ToPalette(15, 0, 0) + dw ToPalette( 0, 31, 0) + dw ToPalette( 0, 15, 0) + dw ToPalette( 0, 0, 31) + dw ToPalette( 0, 0, 15) + dw ToPalette(31, 31, 0) + dw ToPalette(15, 15, 0) + dw ToPalette( 0, 31, 31) + dw ToPalette( 0, 15, 15) + dw ToPalette(31, 0, 31) + + fill 512 - 2 * 13, 0x1c + constant Palette.size = pc() - Palette + + constant N_COLORS = 13 + + +} else if BITS_PER_PIXEL == 8 { + // ::TODO better palette:: + Palette: + dw ToPalette( 0, 0, 0) + dw ToPalette(31, 31, 31) + dw ToPalette(20, 20, 20) + dw ToPalette(10, 10, 10) + dw ToPalette(31, 0, 0) + dw ToPalette(15, 0, 0) + dw ToPalette( 0, 31, 0) + dw ToPalette( 0, 15, 0) + dw ToPalette( 0, 0, 31) + dw ToPalette( 0, 0, 15) + dw ToPalette(31, 31, 0) + dw ToPalette(15, 15, 0) + dw ToPalette( 0, 31, 31) + dw ToPalette( 0, 15, 15) + dw ToPalette(31, 0, 31) + dw ToPalette(15, 0, 15) + dw ToPalette(31, 15, 0) + dw ToPalette(15, 31, 0) + dw ToPalette( 0, 31, 15) + dw ToPalette( 0, 15, 31) + dw ToPalette(31, 0, 15) + dw ToPalette(15, 0, 31) + dw ToPalette(31, 23, 15) + dw ToPalette(15, 31, 23) + dw ToPalette(23, 15, 31) + + fill 512 - 2 * 25, 0x1c + constant Palette.size = pc() - Palette + + constant N_COLORS = 25 + + +} else { + error "Invalid BITS_PER_PIXEL value" +} + +assert(Palette.size == 256 * 2) + + + +// Line List +// ========= + +LineList: +namespace LineList { + // Data format: x1, y1, x2, y2, colour + constant x1 = LineList + 0 + constant y1 = LineList + 1 + constant x2 = LineList + 2 + constant y2 = LineList + 3 + constant colour = LineList + 4 + + constant elementSize = 5 + + + // ::TODO draw an picture:: + + if N_COLORS > 1 { + assert(24 % (N_COLORS - 1) == 0) + } + + variable _c = 1 + variable _t = 0 + + inline addLine(evaluate x2, evaluate y2) { + db BUFFER_WIDTH_PX / 2, BUFFER_HEIGHT_PX / 2, {x2}, {y2}, _c + + _t = _t + 1 + if _t >= 5 { + _t = 0 + + _c = _c + 1 + if _c >= N_COLORS { + _c = 1 + } + } + } + + variable _y = 0 + while _y < BUFFER_HEIGHT_PX { + addLine(0, _y) + + _y = _y + 8 + } + + variable _x = 0 + while _x < BUFFER_WIDTH_PX { + addLine(_x, BUFFER_HEIGHT_PX - 1) + + _x = _x + 8 + } + + variable _y = BUFFER_HEIGHT_PX - 1 + while _y > 0 { + addLine(BUFFER_WIDTH_PX - 1, _y) + + _y = _y - 8 + } + + variable _x = BUFFER_WIDTH_PX - 1 + while _x > 0 { + addLine(_x, 0) + + _x = _x - 8 + } +} +constant LineList.size = pc() - LineList + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-no-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-no-remapping.asm new file mode 100644 index 00000000..fadca829 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-no-remapping.asm @@ -0,0 +1,221 @@ +// A demonstration of a 1bpp tile buffer with no VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 1BPP NO REMAP" + + +constant BITS_PER_PIXEL = 1 + +constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Set a pixel in the 1bpp tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte flag, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos / 8 * TILEMAP_WIDTH * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | (yPos % 8) + // ... = ((yPos & 0xf8) << 5) | (xPos & 0xf8) | (yPos & 7) + + tya + assert(TILEMAP_WIDTH * TILE_SIZE_IN_BYTES / 8 == 0x100 >> 3) + and.w #0xf8 + xba + lsr + lsr + lsr + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1) + txa + and.w #0xf8 + ora.b _tmp + sta.b _tmp + + tya + and.w #7 + ora.b _tmp + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + beq Zero + // Draw a 1 bit + // tileBuffer[Y] = tileBuffer[Y] | ShiftTable[x] + + lda.w tileBuffer,y + ora.l ShiftTable,x + sta.w tileBuffer,y + + bra EndIf + Zero: + // Draw a 0 bit + // tileBuffer[Y] = tileBuffer[Y] & InverseShiftTable[x] + + lda.w tileBuffer,y + and.l InverseShiftTable,x + sta.w tileBuffer,y + EndIf: + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer bitplane 0 to VRAM + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + + // Transfer bitplane 1 to VRAM (with a fixed value of 0) + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #Resources.ZeroByte + stx.w A1T0 + lda.b #Resources.ZeroByte >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +namespace Resources { + +ZeroByte: + db 0 +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-with-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-with-remapping.asm new file mode 100644 index 00000000..2e3c12f2 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-1bpp-with-remapping.asm @@ -0,0 +1,216 @@ +// A demonstration of a 1bpp tile buffer with VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 1BPP REMAPPING" + + +constant BITS_PER_PIXEL = 1 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Set a pixel in the 1bpp VMAIN remapped tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte flag, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear the high byte of both index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL) | (xPos / 8) + // ... = (yPos << 5) | (xPos >> 3) + + assert(BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL == 0x100 >> 3) + tya + xba + lsr + lsr + lsr + sta.b _tmp + + assert(8 == 1 << 3) + txa + lsr + lsr + lsr + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + beq Zero + // Draw a 1 bit + // tileBuffer[Y] = tileBuffer[Y] | ShiftTable[x] + + lda.w tileBuffer,y + ora.l ShiftTable,x + sta.w tileBuffer,y + + bra EndIf + Zero: + // Draw a 0 bit + // tileBuffer[Y] = tileBuffer[Y] & InverseShiftTable[x] + + lda.w tileBuffer,y + and.l InverseShiftTable,x + sta.w tileBuffer,y + EndIf: + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer bitplane 0 to VRAM (with remapping) + lda.b #VMAIN.remap._8bits | VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + + // Fill bitplane 1 with zeros + lda.b #VMAIN.remap._8bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.fixed | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #Resources.ZeroByte + stx.w A1T0 + lda.b #Resources.ZeroByte >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +namespace Resources { + +ZeroByte: + db 0 +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-no-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-no-remapping.asm new file mode 100644 index 00000000..b4d44997 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-no-remapping.asm @@ -0,0 +1,212 @@ +// A demonstration of a 2bpp tile buffer with no VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 2BPP NO REMAP" + + +constant BITS_PER_PIXEL = 2 + +constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(evaluate offset) { + assert8a() + assert16i() + + beq Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the 2bpp tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos / 8 * TILEMAP_WIDTH * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | ((yPos % 8) * 2) + // ... = ((yPos & 0xf8) << 6) | ((xPos & 0xf8) << 1) | ((yPos & 7) << 1) + + tya + assert(TILEMAP_WIDTH * TILE_SIZE_IN_BYTES / 8 == 0x100 >> 2) + and.w #0xf8 + xba + lsr + lsr + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1 << 1) + txa + and.w #0xf8 + asl + ora.b _tmp + sta.b _tmp + + tya + and.w #7 + asl + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(1) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-split-with-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-split-with-remapping.asm new file mode 100644 index 00000000..c7565f57 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-split-with-remapping.asm @@ -0,0 +1,238 @@ +// A demonstration of a 2bpp split-bitplane tile buffer with VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 2BPP SP REMAP" + + +constant BITS_PER_PIXEL = 2 + + +include "_vmain-tile-buffer-demo.inc" + + +// Split the tileBuffer in two +constant tileBuffer_bitplane0.size = tileBuffer.size / 2 +constant tileBuffer_bitplane1.size = tileBuffer.size / 2 + +constant tileBuffer_bitplane0 = tileBuffer +constant tileBuffer_bitplane1 = tileBuffer + tileBuffer.size / 2 + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: buffer = the buffer to write to +macro _DrawBit(buffer) { + assert8a() + assert16i() + + beq Zero_{#} + // Draw a 1 bit + // buffer[Y] |= ShiftTable[x] + + lda.w {buffer},y + ora.l ShiftTable,x + sta.w {buffer},y + + bra EndIf_{#} + + Zero_{#}: + // Draw a 0 bit + // buffer[Y] &= InverseShiftTable[x] + + lda.w {buffer},y + and.l InverseShiftTable,x + sta.w {buffer},y + EndIf_{#}: +} + + + +// Set a pixel in the 2bpp split-bitplane VMAIN remapped tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear the high byte of both index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8) | (xPos / 8) + // ... = (yPos << 5) | (xPos >> 3) + + assert(BUFFER_WIDTH_PX / 8 == 0x100 >> 3) + tya + xba + lsr + lsr + lsr + sta.b _tmp + + assert(8 == 1 << 3) + txa + lsr + lsr + lsr + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = buffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(tileBuffer_bitplane0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(tileBuffer_bitplane1) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer bitplane 0 + lda.b #VMAIN.remap._8bits | VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #tileBuffer_bitplane0 + stx.w A1T0 + lda.b #tileBuffer_bitplane0 >> 16 + sta.w A1B0 + + ldx.w #tileBuffer_bitplane0.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + + // Transfer bitplane 1 + lda.b #VMAIN.remap._8bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + // DMAP0 is at the correct value + + lda.b #VMDATAH + sta.w BBAD0 + + // A1T0 & A1BO point to the correct address + assert(tileBuffer_bitplane0 + tileBuffer_bitplane0.size == tileBuffer_bitplane1) + + ldx.w #tileBuffer_bitplane1.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-with-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-with-remapping.asm new file mode 100644 index 00000000..0a5c5ac2 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-2bpp-with-remapping.asm @@ -0,0 +1,204 @@ +// A demonstration of a 2bpp tile buffer with VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 2BPP REMAPPING" + + +constant BITS_PER_PIXEL = 2 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(evaluate offset) { + assert8a() + assert16i() + + beq Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL) | (xPos / 8 * BITS_PER_PIXEL) + // ... = (yPos << 6) | ((xPos & 0xf8) >> 2) + + assert(BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL == 0x100 >> 2) + tya + xba + lsr + lsr + sta.b _tmp + + assert(8 / BITS_PER_PIXEL == 1 << 2) + txa + and.w #0xf8 + lsr + lsr + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(1) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer 2bpp tileBuffer to VRAM (with remapping) + lda.b #VMAIN.remap._8bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping-word.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping-word.asm new file mode 100644 index 00000000..7672180b --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping-word.asm @@ -0,0 +1,223 @@ +// A demonstration of a 4bpp tile buffer with no VMAIN remapping, writing two bytes at a time. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 4BPP NO REMAP W" + + +constant BITS_PER_PIXEL = 4 + +constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Set a pixel in the 4bpp no remapping tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 +constant _tableIndex1 = zpTmp1 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos / 8 * TILEMAP_WIDTH * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | ((yPos % 8) * 2) + // ... = ((yPos & 0xf8) << 7) | ((xPos & 0xf8) << 2) | ((yPos & 7) << 1) + + tya + assert(TILEMAP_WIDTH * TILE_SIZE_IN_BYTES / 8 == 0x100 >> 1) + and.w #0xf8 + xba + lsr + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1 << 2) + txa + and.w #0xf8 + asl + asl + ora.b _tmp + sta.b _tmp + + tya + and.w #7 + asl + ora.b _tmp + + tay + + + // tableIndex0 = (((X & 7) << 2) | (pixelColour & 3)) * 2 + // tableIndex1 = (((X & 7) << 2) | ((pixelColour >> 2) & 3)) * 2 + sep #$20 +a8() + // Set high byte of A to 0 + tdc + + txa + and.b #7 + asl + asl + sta.b _tmp + + lda.b pixelColour + and.b #3 + ora.b _tmp + asl + tax + + + lda.b pixelColour + lsr + lsr + and.b #3 + ora.b _tmp + asl + + rep #$30 +a16() + + sta.b _tableIndex1 + + + lda.w tileBuffer + 0,y + and.l MaskTable,x + ora.l PlotTable,x + sta.w tileBuffer + 0,y + + + ldx.b _tableIndex1 + + lda.w tileBuffer + 16,y + and.l MaskTable,x + ora.l PlotTable,x + sta.w tileBuffer + 16,y + + + sep #$20 +a8() + + rts +} + + + +// Table of bits to set for each sub-x position and bit-pair. +// +// Index format: xxxpp0 +// xxx = xpos +// pp = pixel value of bitplane pairs 0&1 or 3&4. +PlotTable: +variable _s = 0 +while _s < 8 { + variable _c = 0 + while _c < 4 { + db ((_c >> 0) & 1) << (7 - _s) + db ((_c >> 1) & 1) << (7 - _s) + + _c = _c + 1 + } + + _s = _s + 1 +} + + +// Table of bits to set for each sub-x position and bit-pair. +// +// Index format is the same as `PlotTable` +MaskTable: +variable _s = 0 +while _s < 8 { + variable _c = 0 + while _c < 4 { + db ~(1 << (7 - _s)) + db ~(1 << (7 - _s)) + + _c = _c + 1 + } + + _s = _s + 1 +} + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping.asm new file mode 100644 index 00000000..46e9b690 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-no-remapping.asm @@ -0,0 +1,219 @@ +// A demonstration of a 4bpp tile buffer with no VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 4BPP NO REMAP" + + +constant BITS_PER_PIXEL = 4 + +constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(evaluate offset) { + assert8a() + assert16i() + + beq Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the 4bpp no remapping tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos / 8 * TILEMAP_WIDTH * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | ((yPos % 8) * 2) + // ... = ((yPos & 0xf8) << 7) | ((xPos & 0xf8) << 2) | ((yPos & 7) << 1) + + tya + assert(TILEMAP_WIDTH * TILE_SIZE_IN_BYTES / 8 == 0x100 >> 1) + and.w #0xf8 + xba + lsr + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1 << 2) + txa + and.w #0xf8 + asl + asl + ora.b _tmp + sta.b _tmp + + tya + and.w #7 + asl + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(1) + + lda.b pixelColour + bit.b #1 << 2 + _DrawBit(16) + + lda.b pixelColour + bit.b #1 << 3 + _DrawBit(17) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping-word.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping-word.asm new file mode 100644 index 00000000..a1e89631 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping-word.asm @@ -0,0 +1,214 @@ +// A demonstration of a 4bpp tile buffer with VMAIN remapping, writing two bytes at a time. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 4BPP NO REMAP W" + + +constant BITS_PER_PIXEL = 4 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Set a pixel in the 4bpp VMAIN remapped tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 +constant _tableIndex1 = zpTmp1 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL) | (xPos / 8 * BITS_PER_PIXEL) + // ... = (yPos << 7) | ((xPos & 0xf8) >> 1) + + assert(BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL == 0x100 >> 1) + tya + xba + lsr + sta.b _tmp + + assert(8 / BITS_PER_PIXEL == 1 << 1) + txa + and.w #0xf8 + lsr + ora.b _tmp + + tay + + + // tableIndex0 = (((X & 7) << 2) | (pixelColour & 3)) * 2 + // tableIndex1 = (((X & 7) << 2) | ((pixelColour >> 2) & 3)) * 2 + sep #$20 +a8() + // Set high byte of A to 0 + tdc + + txa + and.b #7 + asl + asl + sta.b _tmp + + lda.b pixelColour + and.b #3 + ora.b _tmp + asl + tax + + + lda.b pixelColour + lsr + lsr + and.b #3 + ora.b _tmp + asl + + rep #$30 +a16() + + sta.b _tableIndex1 + + + lda.w tileBuffer + 0,y + and.l MaskTable,x + ora.l PlotTable,x + sta.w tileBuffer + 0,y + + + ldx.b _tableIndex1 + + lda.w tileBuffer + 2,y + and.l MaskTable,x + ora.l PlotTable,x + sta.w tileBuffer + 2,y + + + sep #$20 +a8() + + rts +} + + + +// Table of bits to set for each sub-x position and bit-pair. +// +// Index format: xxxpp0 +// xxx = xpos +// pp = pixel value of bitplane pairs 0&1 or 3&4. +PlotTable: +variable _s = 0 +while _s < 8 { + variable _c = 0 + while _c < 4 { + db ((_c >> 0) & 1) << (7 - _s) + db ((_c >> 1) & 1) << (7 - _s) + + _c = _c + 1 + } + + _s = _s + 1 +} + + +// Table of bits to set for each sub-x position and bit-pair. +// +// Index format is the same as `PlotTable` +MaskTable: +variable _s = 0 +while _s < 8 { + variable _c = 0 + while _c < 4 { + db ~(1 << (7 - _s)) + db ~(1 << (7 - _s)) + + _c = _c + 1 + } + + _s = _s + 1 +} + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer 4bpp tileBuffer to VRAM (with remapping) + lda.b #VMAIN.remap._9bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping.asm new file mode 100644 index 00000000..f7236690 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-4bpp-with-remapping.asm @@ -0,0 +1,210 @@ +// A demonstration of a 4bpp tile buffer with VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 4BPP REMAPPING" + + +constant BITS_PER_PIXEL = 4 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(evaluate offset) { + assert8a() + assert16i() + + beq Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the 4bpp VMAIN remapped tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL) | (xPos / 8 * BITS_PER_PIXEL) + // ... = (yPos << 7) | ((xPos & 0xf8) >> 1) + + assert(BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL == 0x100 >> 1) + tya + xba + lsr + sta.b _tmp + + assert(8 / BITS_PER_PIXEL == 1 << 1) + txa + and.w #0xf8 + lsr + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(1) + + lda.b pixelColour + bit.b #1 << 2 + _DrawBit(2) + + lda.b pixelColour + bit.b #1 << 3 + _DrawBit(3) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer 4bpp tileBuffer to VRAM (with remapping) + lda.b #VMAIN.remap._9bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-no-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-no-remapping.asm new file mode 100644 index 00000000..04e2a3a9 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-no-remapping.asm @@ -0,0 +1,233 @@ +// A demonstration of an 8bpp tile buffer with no VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 8BPP NO REMAP" + + +constant BITS_PER_PIXEL = 8 + +constant TILE_SIZE_IN_BYTES = BITS_PER_PIXEL * 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: branch = the branch instruction to use when branching to zero +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(define branch, evaluate offset) { + assert8a() + assert16i() + + {branch} Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the 8bpp tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + // bufferIndex (Y) = (yPos / 8 * TILEMAP_WIDTH * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | ((yPos % 8) * 2) + // ... = ((yPos & 0xf8) << 8) | ((xPos & 0xf8) << 3) | ((yPos & 7) << 1) + + tya + assert(TILEMAP_WIDTH * TILE_SIZE_IN_BYTES / 8 == 0x100) + and.w #0xf8 + xba + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1 << 3) + txa + and.w #0xf8 + asl + asl + asl + ora.b _tmp + sta.b _tmp + + tya + and.w #7 + asl + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(beq, 0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(beq, 1) + + lda.b pixelColour + bit.b #1 << 2 + _DrawBit(beq, 16) + + lda.b pixelColour + bit.b #1 << 3 + _DrawBit(beq, 17) + + lda.b pixelColour + bit.b #1 << 4 + _DrawBit(beq, 32) + + lda.b pixelColour + bit.b #1 << 5 + _DrawBit(beq, 33) + + bit.b pixelColour + _DrawBit(bvc, 48) + + bit.b pixelColour + _DrawBit(bpl, 49) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-with-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-with-remapping.asm new file mode 100644 index 00000000..3aa29453 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-8bpp-with-remapping.asm @@ -0,0 +1,223 @@ +// A demonstration of an 8bpp tile buffer with VMAIN remapping. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN 8BPP REMAPPING" + + +constant BITS_PER_PIXEL = 8 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Write a single bit to the tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: Y = buffer index +// INPUT: X = index into `ShiftTable` and `InverseShiftTable` +// INPUT: zero flag = bit value +// +// PARAM: branch = the branch instruction to use when branching to zero +// PARAM: offset = the offset (within `tileBuffer`) for the current bit. +macro _DrawBit(define branch, evaluate offset) { + assert8a() + assert16i() + + {branch} Zero_{#} + // Draw a 1 bit + // tileBuffer[Y + offset] |= ShiftTable[x] + + lda.w tileBuffer + {offset},y + ora.l ShiftTable,x + sta.w tileBuffer + {offset},y + + bra EndIf_{#} + Zero_{#}: + // Draw a 0 bit + // tileBuffer[Y + offset] &= InverseShiftTable[x] + + lda.w tileBuffer + {offset},y + and.l InverseShiftTable,x + sta.w tileBuffer + {offset},y + EndIf_{#}: +} + + + +// Set a pixel in the 8bpp VMAIN remapped tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + // Clear high byte of index registers + sep #$10 +i8() + rep #$30 +a16() +i16() + + // bufferIndex (Y) = (yPos * BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL) | (xPos / 8 * BITS_PER_PIXEL) + // ... = (yPos << 8) | (xPos & 0xf8) + + assert(BUFFER_WIDTH_PX / 8 * BITS_PER_PIXEL == 0x100) + tya + xba + sta.b _tmp + + assert(8 / BITS_PER_PIXEL == 1) + txa + and.w #0xf8 + ora.b _tmp + + tay + + + // bit shift index (X) = X & 7 + txa + and.w #7 + tax + + + sep #$20 +a8() + + // Y = tileBuffer index + // X = bit shift index + + lda.b pixelColour + bit.b #1 << 0 + _DrawBit(beq, 0) + + lda.b pixelColour + bit.b #1 << 1 + _DrawBit(beq, 1) + + lda.b pixelColour + bit.b #1 << 2 + _DrawBit(beq, 2) + + lda.b pixelColour + bit.b #1 << 3 + _DrawBit(beq, 3) + + lda.b pixelColour + bit.b #1 << 4 + _DrawBit(beq, 4) + + lda.b pixelColour + bit.b #1 << 5 + _DrawBit(beq, 5) + + bit.b pixelColour + _DrawBit(bvc, 6) + + bit.b pixelColour + _DrawBit(bpl, 7) + + rts +} + + +ShiftTable: + db 1 << 7 + db 1 << 6 + db 1 << 5 + db 1 << 4 + db 1 << 3 + db 1 << 2 + db 1 << 1 + db 1 << 0 + + +InverseShiftTable: + db ~(1 << 7) + db ~(1 << 6) + db ~(1 << 5) + db ~(1 << 4) + db ~(1 << 3) + db ~(1 << 2) + db ~(1 << 1) + db ~(1 << 0) + + + +// Transfer the tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Transfer 8bpp tileBuffer to VRAM (with remapping) + lda.b #VMAIN.remap._10bits | VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #VRAM_BG1_TILES_WADDR + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.two + sta.w DMAP0 + + lda.b #VMDATA + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-no-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-no-remapping.asm new file mode 100644 index 00000000..ecf8d099 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-no-remapping.asm @@ -0,0 +1,207 @@ +// A demonstration of a Mode 7 tile buffer with no VMAIN remapping. +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN MODE7 NO REMAP" + + +define MODE7 + +constant MODE7_MATRIX_A = 0x0080 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0080 + + +include "_vmain-tile-buffer-demo.inc" + + + +// Set a pixel in the mode 7 tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < BUFFER_WIDTH_PX) +// Y = y-position (MUST BE < BUFFER_HEIGHT_PX) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + rep #$30 +a16() +i16() + // bufferIndex (Y) = (yPos / 8 * BUFFER_WIDTH_PX / 8 * TILE_SIZE_IN_BYTES) | (xPos / 8 * TILE_SIZE_IN_BYTES) | ((yPos % 8) * 8) | (xPos / 8) + // ... = ((yPos & 0x78) << 8) | ((xPos & 0x78) << 3) | ((yPos & 7) << 3) | (xPos & 7) + + + tya + assert(BUFFER_WIDTH_PX / 8 * TILE_SIZE_IN_BYTES / 8 == 0x100 >> 1) + and.w #0x78 + xba + lsr + sta.b _tmp + + assert(TILE_SIZE_IN_BYTES / 8 == 1 << 3) + txa + and.w #0x78 + asl + asl + asl + ora.b _tmp + sta.b _tmp + + assert(8 == 1 << 3) + tya + and.w #7 + asl + asl + asl + ora.b _tmp + sta.b _tmp + + txa + and.w #7 + ora.b _tmp + + tay + + + sep #$20 +a8() + + // Y = tileBuffer index + + lda.b pixelColour + sta.w tileBuffer,y + + rts +} + + + +// Generate the Mode7 tilemap in VRAM. +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +a8() +i16() +code() +function GenerateTilemap { +constant _tmp = zpTmp0 + + // Access Mode 7 tilemap + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + + sep #$30 +i8() + + lda.b #0 + + ldy.b #0 + YLoop: + sta.b _tmp + + rep #$20 + a16() + // VMADD = y * M7_TILEMAP_WIDTH + assert(M7_TILEMAP_WIDTH == 0x100 >> 1) + tya + xba + lsr + sta.w VMADD + + sep #$20 + a8() + lda.b _tmp + + + ldx.b #BUFFER_WIDTH_PX / 8 + + XLoop: + sta.w VMDATAL + inc + dex + bne XLoop + + iny + cpy.b #BUFFER_HEIGHT_PX / 8 + bcc YLoop + + rep #$10 +i16() + rts +} + + + +// Transfer the Mode 7 tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Access Mode 7 tiles + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #0 + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + ldx.w #tileBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-tilemap.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-tilemap.asm new file mode 100644 index 00000000..9d080798 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-tilemap.asm @@ -0,0 +1,216 @@ +// A demonstration of a simple fullscreen 128x112px chunky pixel image buffer +// created by storing the image data in the mode 7 tilemap. +// +// As the mode 7 tilemap is a 128x128px contiguous grid, there is no need +// for `VMAIN` address remapping and the whole image can be transferred +// to VRAM in a single DMA transfer. +// +// To turn the tilemap into pixels on the screen the Mode 7 tiles is filled +// with solid tiles for each of the 256 colours. +// +// To turn the tilemap into visible pixels, the Mode 7 tile data is filled with +// solid tiles representing each of the 256 colours. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN MODE7 TM IMAGE" + + +define MODE7 + +define CUSTOM_MODE7_MATRIX + +constant MODE7_MATRIX_A = 0x0400 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0400 + + +include "_vmain-tile-buffer-demo.inc" + + +assert(BUFFER_WIDTH_PX == M7_TILEMAP_WIDTH) +assert(BUFFER_HEIGHT_PX <= M7_TILEMAP_HEIGHT) + + +constant imageBuffer = tileBuffer +constant imageBuffer.size = tileBuffer.size + + +// Set a pixel in the image buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < M7_TILEMAP_WIDTH) +// Y = y-position (MUST BE < M7_TILEMAP_HEIGHT) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + rep #$30 +a16() +i16() + // bufferIndex (Y) = ((yPos % M7_TILEMAP_HEIGHT) * M7_TILEMAP_WIDTH) | (xPos % M7_TILEMAP_WIDTH) + // ... = ((yPos & 0x7F) << 7) | (xPos & 0x7F) + + + tya + assert(M7_TILEMAP_WIDTH == 0x100 >> 1) + and.w #0x7F + xba + lsr + sta.b _tmp + + txa + and.w #0x7F + ora.b _tmp + sta.b _tmp + + tay + + + sep #$20 +a8() + + // Y = imageBuffer index + + lda.b pixelColour + sta.w imageBuffer,y + + rts +} + + + +// Generate the Mode 7 tile data in VRAM. +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +// +// Uses DMA channel 0 +a8() +i16() +code() +function GenerateTileData { +constant _tile = zpTmp0 + + // Access Mode 7 tiles + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.high + sta.w VMAIN + + ldx.w #0 + stx.w VMADD + + + // Prep DMA registers (fixed transfer to VMDATAH) + + lda.b #DMAP.fixed | DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #_tile + stx.w A1T0 + assert(_tile >> 16 == 0) + stz.w A1B0 + + + // for _tile = 0 to 255: + // Transfer TILE_SIZE_IN_BYTES copies of _tile to VRAM + + stz.b _tile + + lda.b #MDMAEN.dma0 + + Loop: + ldx.w #TILE_SIZE_IN_BYTES + stx.w DAS0 + + sta.w MDMAEN + + inc.b _tile + bne Loop + + rts +} + + + +// Transfer the image buffer to the Mode 7 tilemap in VRAM. +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// Uses DMA channel 0 +a8() +i16() +code() +function TransferImageBufferToVram { + + // Access Mode 7 tilemap + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + ldx.w #0 + stx.w VMADD + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAL + sta.w BBAD0 + + ldx.w #imageBuffer + stx.w A1T0 + lda.b #imageBuffer >> 16 + sta.w A1B0 + + ldx.w #imageBuffer.size + stx.w DAS0 + + + lda.b #MDMAEN.dma0 + sta.w MDMAEN + + rts +} + + + +constant GenerateTilemap = GenerateTileData +constant TransferTileBufferToVram = TransferImageBufferToVram + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.asm new file mode 100644 index 00000000..68dae3a6 --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.asm @@ -0,0 +1,212 @@ +// A demonstration of a Mode 7 tile buffer with 10bit VMAIN remapping. +// +// Special thanks to nocash, for mentioning `VMAIN` remapping can be +// used with Mode 7 tiles in `fullsnes.txt`. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN MODE7 REMAP 10" + + +define MODE7 + +constant MODE7_MATRIX_A = 0x0080 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0080 + + +include "_vmain-tile-buffer-demo.inc" + + +assert(BUFFER_WIDTH_PX == M7_TILEMAP_WIDTH) +assert(BUFFER_HEIGHT_PX <= M7_TILEMAP_HEIGHT) + + + +// Set a pixel in the mode 7 tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < M7_TILEMAP_WIDTH) +// Y = y-position (MUST BE < M7_TILEMAP_HEIGHT) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + rep #$30 +a16() +i16() + // bufferIndex (Y) = ((yPos % 128) * BUFFER_WIDTH_PX) | (xPos % BUFFER_WIDTH_PX) + // ... = ((yPos & 0x7F) << 7) | (xPos & 0x7F) + + tya + assert(BUFFER_WIDTH_PX == 0x100 >> 1) + and.w #0x7F + xba + lsr + sta.b _tmp + + txa + and.w #0x7F + ora.b _tmp + sta.b _tmp + + tay + + + sep #$20 +a8() + + // Y = tileBuffer index + + lda.b pixelColour + sta.w tileBuffer,y + + rts +} + + + +// Generate the Mode7 tilemap in VRAM. +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +a8() +i16() +code() +function GenerateTilemap { +constant _tmp = zpTmp0 + + // Access Mode 7 tilemap + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + + sep #$30 +i8() + + stz.b _tmp + + ldy.b #0 + YLoop: + rep #$20 + a16() + // VMADD = y * M7_TILEMAP_WIDTH + assert(M7_TILEMAP_WIDTH == 0x100 >> 1) + tya + xba + lsr + sta.w VMADD + + sep #$20 + a8() + + lda.b _tmp + + ldx.b #BUFFER_WIDTH_PX / 8 + + XLoop: + sta.w VMDATAL + + clc + adc.b #0x10 + + dex + bne XLoop + + inc.b _tmp + + iny + cpy.b #BUFFER_HEIGHT_PX / 8 + bcc YLoop + + rep #$10 +i16() + rts +} + + + +// Transfer the Mode 7 tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Access Mode 7 tiles (with remapping) + lda.b #VMAIN.remap._10bits | VMAIN.increment.by128 | VMAIN.incrementMode.high + sta.w VMAIN + + + // Setup DMA channel 0 + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + + // for y = 0 to BUFFER_HEIGHT_PX - 1: + // VMADD = y + // DMA transfer to VRAM + + ldx.w #BUFFER_WIDTH_PX + lda.b #MDMAEN.dma0 + + ldy.w #0 + Loop: + sty.w VMADD + + stx.w DAS0 + + sta.w MDMAEN + + iny + cpy.w #BUFFER_HEIGHT_PX + bcc Loop + + rts +} + + diff --git a/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.asm b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.asm new file mode 100644 index 00000000..13beccfd --- /dev/null +++ b/roms/snes-test-roms/src/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.asm @@ -0,0 +1,213 @@ +// A demonstration of a Mode 7 tile buffer with 8 bit VMAIN remapping. +// +// Special thanks to nocash, for mentioning `VMAIN` remapping can be +// used with Mode 7 tiles in `fullsnes.txt`. +// +// +// SPDX-FileCopyrightText: © 2022 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2022 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +define ROM_NAME = "VMAIN MODE7 REMAP 8" + +define MODE7 + +constant MODE7_MATRIX_A = 0x0080 +constant MODE7_MATRIX_B = 0 +constant MODE7_MATRIX_C = 0 +constant MODE7_MATRIX_D = 0x0080 + + +include "_vmain-tile-buffer-demo.inc" + + +assert(BUFFER_WIDTH_PX == M7_TILEMAP_WIDTH) +assert(BUFFER_HEIGHT_PX <= M7_TILEMAP_HEIGHT) + + + +// Set a pixel in the mode 7 tile buffer +// +// ASSUMES: inputs are in bounds +// +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +// +// INPUT: X = x-position (MUST BE < M7_TILEMAP_WIDTH) +// Y = y-position (MUST BE < M7_TILEMAP_HEIGHT) +// SetPixel.pixelColour = pixel colour (zeropage byte, unmodified by this function) +// +// KEEP: pixelColour +a8() +i16() +code() +function SetPixel { +constant _tmp = zpTmp0 + + + rep #$30 +a16() +i16() + // bufferIndex (Y) = ((yPos % 128) * BUFFER_WIDTH_PX) | (xPos % BUFFER_WIDTH_PX) + // ... = ((yPos & 0x7F) << 7) | (xPos & 0x7F) + + tya + assert(BUFFER_WIDTH_PX == 0x100 >> 1) + and.w #0x7F + xba + lsr + sta.b _tmp + + txa + and.w #0x7F + ora.b _tmp + sta.b _tmp + + tay + + + sep #$20 +a8() + + // Y = tileBuffer index + + lda.b pixelColour + sta.w tileBuffer,y + + rts +} + + + +// Generate the Mode7 tilemap in VRAM. +// +// REQUIRES: Force-blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB access registers +a8() +i16() +code() +function GenerateTilemap { +constant _tmp = zpTmp0 + + // Access Mode 7 tilemap + lda.b #VMAIN.increment.by1 | VMAIN.incrementMode.low + sta.w VMAIN + + + sep #$30 +i8() + + stz.b _tmp + + ldy.b #0 + YLoop: + rep #$20 + a16() + // VMADD = y * M7_TILEMAP_WIDTH + assert(M7_TILEMAP_WIDTH == 0x100 >> 1) + tya + xba + lsr + sta.w VMADD + + sep #$20 + a8() + + lda.b _tmp + + ldx.b #BUFFER_WIDTH_PX / 8 + + XLoop: + sta.w VMDATAL + + clc + adc.b #4 + + dex + bne XLoop + + + lda.b _tmp + inc + bit.b #%00000100 + beq + + clc + adc.b #%00111100 + + + sta.b _tmp + + iny + cpy.b #BUFFER_HEIGHT_PX / 8 + bcc YLoop + + rep #$10 +i16() + rts +} + + + +// Transfer the Mode 7 tile buffer to VRAM +// +// REQUIRES: Force blank +// REQUIRES: 8 bit A, 16 bit Index, DP = 0, DB = 0x7e +a8() +i16() +code() +function TransferTileBufferToVram { + + // Access Mode 7 tiles (with remapping) + lda.b #VMAIN.remap._8bits | VMAIN.increment.by32 | VMAIN.incrementMode.high + sta.w VMAIN + + + lda.b #DMAP.direction.toPpu | DMAP.transfer.one + sta.w DMAP0 + + lda.b #VMDATAH + sta.w BBAD0 + + ldx.w #tileBuffer + stx.w A1T0 + lda.b #tileBuffer >> 16 + sta.w A1B0 + + + ldx.w #BUFFER_WIDTH_PX + lda.b #MDMAEN.dma0 + + variable _y = 0 + while _y < BUFFER_HEIGHT_PX { + ldy.w #((_y & 0xe0) << 7) | (_y & 0x1f) + sty.w VMADD + + stx.w DAS0 + + sta.w MDMAEN + + _y = _y + 1 + } + + rts +} + + diff --git a/roms/snes-test-roms/src/wait.inc b/roms/snes-test-roms/src/wait.inc new file mode 100644 index 00000000..d735f648 --- /dev/null +++ b/roms/snes-test-roms/src/wait.inc @@ -0,0 +1,189 @@ +// Simple delay macros/functions +// +// SPDX-FileCopyrightText: © 2019 Marcus Rowe +// SPDX-License-Identifier: Zlib +// +// Copyright © 2019 Marcus Rowe +// +// This software is provided 'as-is', without any express or implied warranty. +// In no event will the authors be held liable for any damages arising from the +// use of this software. +// +// Permission is granted to anyone to use this software for any purpose, including +// commercial applications, and to alter it and redistribute it freely, subject to +// the following restrictions: +// +// 1. The origin of this software must not be misrepresented; you must not +// claim that you wrote the original software. If you use this software in +// a product, an acknowledgment in the product documentation would be +// appreciated but is not required. +// +// 2. Altered source versions must be plainly marked as such, and must not be +// misrepresented as being the original software. +// +// 3. This notice may not be removed or altered from any source distribution. + + +code() +_wait_rom: +allocate(_wait_ram, lowram, 1) +allocate(_wait_zp, zeropage, 1) + + +// Wait 12 master cycles +// REQUIRES: in fastROM +inline w12() { + nop // 2 fast +} + +// Wait 18 master cycles +// REQUIRES: in fastROM +inline w18() { + rep #0 // 3 fast +} + +// Wait 20 master cycles +// REQUIRES: 8 bit A, DP = 0, in fastROM +// MODIFIES: n, v +inline w20() { + assert8a() + + bit.b _wait_zp // 2 fast, 1 slow +} + +// Wait 24 master cycles +// REQUIRES: in fastROM +inline w24() { + nop + nop // 4 fast +} + +// Wait 26 master cycles +// REQUIRES: 8 bit A, DB = 0x80, in fastROM +// MODIFIES: n, v +inline w26() { + assert8a() + bit.w _wait_ram // 3 fast, 1 slow +} + +// Wait 28 master cycles +// REQUIRES: 16 bit Index, DP = 0, in fastROM +// MODIFIES: Y, P +inline w28() { + assert16i() + ldy.b _wait_zp // 2 fast, 2 slow +} +// Wait 30 master cycles +// REQUIRES: 16 bit Index, DB = 0x80, in fastROM +// MODIFIES: Y, P +inline w30() { + assert16i() + ldy.w _wait_rom // 5 fast +} + +// Wait 32 master cycles +// REQUIRES: 8 bit A, DB = 0x80, in fastROM +// MODIFIES: A, P +inline w32() { + assert8a() + lda.l _wait_ram // 4 fast, 1 slow +} + +// Wait 34 master cycles +// REQUIRES: 8 bit A, DP = 0, in fastROM +// MODIFIES: Y, P +inline w34() { + assert8a() + dec.b _wait_zp // 3 fast, 2 slow +} + +// Wait 36 master cycles +// REQUIRES: in fastROM +inline w36() { + w18() + w18() +} + +// Wait 36 master cycles +// REQUIRES: 8 bit A, DP = 0, in fastROM +inline w38() { + w20() + w18() +} + +// Wait 40 master cycles +// REQUIRES: 8 bit A, DP = 0, in fastROM +inline w40() { + w20() + w20() +} + +// Wait 42 master cycles +// REQUIRES: in fastROM +inline w42() { + w18() + w24() +} + +// Wait 44 master cycles +// REQUIRES: 8 bit A, DB = 0x80, in fastROM +inline w44() { + w18() + w26() +} + +// Wait 46 master cycles +// REQUIRES: 16 bit Index, DP = 0, in fastROM +inline w46() { + w18() + w28() +} + +// Wait 48 master cycles +// REQUIRES: 16 bit Index, DB = 0x80, in fastROM +inline w48() { + w18() + w30() +} + + +// Wait exactly A scanlines +// REQUIRES: DB = 0x80, fastROM active +// INPUT: A = number of scanlines to wait (must be >= 2) +au() +iu() +code() +function WaitScanlines_A { + php + sep #$30 +a8() +i8() + tax + dex + + rep #$10 +i16() + + Loop: + lda.b #42 + - + dec + bne - + + w28() + + dex + bne Loop + + + lda.b #37 + - + dec + bne - + + w28() + + plp + rts +} + diff --git a/roms/snes-test-roms/tools/_snes.py b/roms/snes-test-roms/tools/_snes.py new file mode 100644 index 00000000..d6c94956 --- /dev/null +++ b/roms/snes-test-roms/tools/_snes.py @@ -0,0 +1,358 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# vim: set fenc=utf-8 ai ts=4 sw=4 sts=4 et: +# +# +# SPDX-FileCopyrightText: © 2020 Marcus Rowe +# SPDX-License-Identifier: Zlib +# +# Copyright © 2020 Marcus Rowe +# +# This software is provided 'as-is', without any express or implied warranty. +# In no event will the authors be held liable for any damages arising from the +# use of this software. +# +# Permission is granted to anyone to use this software for any purpose, including +# commercial applications, and to alter it and redistribute it freely, subject to +# the following restrictions: +# +# 1. The origin of this software must not be misrepresented; you must not +# claim that you wrote the original software. If you use this software in +# a product, an acknowledgment in the product documentation would be +# appreciated but is not required. +# +# 2. Altered source versions must be plainly marked as such, and must not be +# misrepresented as being the original software. +# +# 3. This notice may not be removed or altered from any source distribution. + + +import itertools +from collections import namedtuple + + +TileMapEntry = namedtuple("TileMapEntry", ("tile_id", "palette_id", "hflip", "vflip")) + + +def convert_snes_tileset(tiles, bpp): + out = bytearray() + + for tile in tiles: + for b in range(0, bpp, 2): + for y in range(0, 8): + for bi in range(b, min(b + 2, bpp)): + byte = 0 + mask = 1 << bi + for x in range(0, 8): + byte <<= 1 + if tile[x + y * 8] & mask: + byte |= 1 + out.append(byte) + return out + + +def convert_rgb_color(c): + r, g, b = c + + b = (b >> 3) & 31 + g = (g >> 3) & 31 + r = (r >> 3) & 31 + return (b << 10) | (g << 5) | r + + +def is_small_tile_not_transparent(image, transparent_color, xpos, ypos): + """Returns True if the tile contains a non-transparent pixel""" + + if xpos + 8 > image.width or ypos + 8 > image.height: + raise ValueError(f"position out of bounds: {xpos}, {ypos}") + + return any( + convert_rgb_color(image.getpixel((x, y))) != transparent_color + for y in range(ypos, ypos + 8) + for x in range(xpos, xpos + 8) + ) + + +def extract_tileset_tiles(image): + """Extracts 8x8px tiles from the image.""" + + if image.mode != "RGB": + image = image.convert("RGB") + + if image.width % 8 != 0: + raise ValueError("Image height MUST BE multiple of 8") + + if image.height % 8 != 0: + raise ValueError("Image height MUST BE multiple of 8") + + for ty in range(0, image.height, 8): + for tx in range(0, image.width, 8): + tile_data = list() + + for y in range(ty, ty + 8): + for x in range(tx, tx + 8): + tile_data.append(convert_rgb_color(image.getpixel((x, y)))) + + yield tile_data + + +def extract_small_tile(image, xpos, ypos): + if xpos + 8 > image.width or ypos + 8 > image.height: + raise ValueError(f"position out of bounds: {xpos}, {ypos}") + + return [ + convert_rgb_color(image.getpixel((x, y))) + for y in range(ypos, ypos + 8) + for x in range(xpos, xpos + 8) + ] + + +def extract_large_tile(image, xpos, ypos): + if xpos + 16 > image.width or ypos + 16 > image.height: + raise ValueError(f"position out of bounds: {xpos}, {ypos}") + + return [ + convert_rgb_color(image.getpixel((x, y))) + for y in range(ypos, ypos + 16) + for x in range(xpos, xpos + 16) + ] + + +def extract_tilemap_tiles(image): + """Extracts 8x8px tiles from the image, in the same order as a SNES tilemap.""" + + if image.mode != "RGB": + image = image.convert("RGB") + + if image.width % 256 != 0: + raise ValueError("Image width MUST BE a multiple of 256") + + if image.height % 256 != 0: + raise ValueError("Image height MUST BE a multiple of 256") + + if image.width > 512 or image.height > 512: + raise ValueError("Maximum image size is 512x512 pixels") + + t_width = image.width // 8 + t_height = image.height // 8 + + img_data = image.getdata() + + for screen_y in range(t_height // 32): + for screen_x in range(t_width // 32): + for ty in range(32): + ty = screen_y * 256 + ty * 8 + for tx in range(32): + tx = screen_x * 256 + tx * 8 + + tile_data = list() + + for y in range(ty, ty + 8): + for x in range(tx, tx + 8): + tile_data.append(convert_rgb_color(image.getpixel((x, y)))) + + yield tile_data + + +def create_palettes_map(image, bpp, pad_palette_data=None): + # Returns palettes_map + + if image.mode != "RGB": + image = image.convert("RGB") + + colors_per_palette = 1 << bpp + max_colors = min(colors_per_palette * 8, 256) + + if image.width != 16: + raise ValueError("Palette Image MUST BE 16 px in width") + + if image.width * image.height > max_colors: + raise ValueError(f"Palette Image has too many colours (max {max_colors})") + + image_data = image.getdata() + + palettes_map = list() + + for p in range(len(image_data) // colors_per_palette): + pal_map = dict() + + for x in range(colors_per_palette): + c = convert_rgb_color(image_data[p * colors_per_palette + x]) + if c not in pal_map: + pal_map[c] = x + + palettes_map.append(pal_map) + + return palettes_map + + +def convert_palette_image(image): + palette_data = bytearray() + + for c in image.getdata(): + u16 = convert_rgb_color(c) + + palette_data.append(u16 & 0xFF) + palette_data.append(u16 >> 8) + + return palette_data + + +def get_palette_id(tile, palette_map): + # Returns a tuple of (palette_id, palette_map) + for palette_id, pal_map in enumerate(palette_map): + if all([c in pal_map for c in tile]): + return palette_id, pal_map + + return None, None + + +_H_FLIP_ORDER_SMALL = [ + (y * 8 + x) for y, x in itertools.product(range(8), reversed(range(8))) +] +_V_FLIP_ORDER_SMALL = [ + (y * 8 + x) for y, x in itertools.product(reversed(range(8)), range(8)) +] + + +def hflip_tile(tile): + return bytes([tile[i] for i in _H_FLIP_ORDER_SMALL]) + + +def vflip_tile(tile): + return bytes([tile[i] for i in _V_FLIP_ORDER_SMALL]) + + +_H_FLIP_ORDER_LARGE = [ + (y * 16 + x) for y, x in itertools.product(range(16), reversed(range(16))) +] +_V_FLIP_ORDER_LARGE = [ + (y * 16 + x) for y, x in itertools.product(reversed(range(16)), range(16)) +] + + +def hflip_large_tile(tile): + return bytes([tile[i] for i in _H_FLIP_ORDER_LARGE]) + + +def vflip_large_tile(tile): + return bytes([tile[i] for i in _V_FLIP_ORDER_LARGE]) + + +def split_large_tile(tile): + return ( + [tile[y * 16 + x] for y in range(0, 8) for x in range(0, 8)], + [tile[y * 16 + x] for y in range(0, 8) for x in range(8, 16)], + [tile[y * 16 + x] for y in range(8, 16) for x in range(0, 8)], + [tile[y * 16 + x] for y in range(8, 16) for x in range(8, 16)], + ) + + +def convert_tilemap_and_tileset(tiles, palettes_map): + # Returns a tuple(tilemap, tileset) + + invalid_tiles = list() + + tilemap = list() + tileset = list() + + tileset_map = dict() + + for tile_index, tile in enumerate(tiles): + palette_id, pal_map = get_palette_id(tile, palettes_map) + + if pal_map: + # Must be bytes() here as a dict() key must be immutable + tile_data = bytes([pal_map[c] for c in tile]) + + tile_match = tileset_map.get(tile_data, None) + if tile_match is None: + tile_id = len(tileset) + tile_match = tile_id, False, False + + tileset.append(tile_data) + + h_tile_data = hflip_tile(tile_data) + v_tile_data = vflip_tile(tile_data) + hv_tile_data = vflip_tile(h_tile_data) + + tileset_map[tile_data] = tile_match + tileset_map.setdefault(h_tile_data, (tile_id, True, False)) + tileset_map.setdefault(v_tile_data, (tile_id, False, True)) + tileset_map.setdefault(hv_tile_data, (tile_id, True, True)) + + tilemap.append( + TileMapEntry( + tile_id=tile_match[0], + palette_id=palette_id, + hflip=tile_match[1], + vflip=tile_match[2], + ) + ) + else: + invalid_tiles.append(tile_index) + + if invalid_tiles: + raise ValueError(f"Cannot find palette for tiles {invalid_tiles}") + + return tilemap, tileset + + +def create_tilemap_data(tilemap, default_order): + data = bytearray() + + assert len(tilemap) % 32 * 32 == 0 + + for t in tilemap: + data.append(t.tile_id & 0xFF) + data.append( + ((t.tile_id & 0x3FF) >> 8) + | ((t.palette_id & 7) << 2) + | (bool(default_order) << 5) + | (bool(t.hflip) << 6) + | (bool(t.vflip) << 7) + ) + + return data + + +def create_tilemap_data_low(tilemap): + data = bytearray() + + assert len(tilemap) % 32 * 32 == 0 + + for t in tilemap: + data.append(t.tile_id & 0xFF) + + return data + + +def create_tilemap_data_high(tilemap, default_order): + data = bytearray() + + assert len(tilemap) % 32 * 32 == 0 + + for t in tilemap: + data.append( + ((t.tile_id & 0x3FF) >> 8) + | ((t.palette_id & 7) << 2) + | (bool(default_order) << 5) + | (bool(t.hflip) << 6) + | (bool(t.vflip) << 7) + ) + + return data + + +def image_to_snes(image, palette_image, bpp): + # Return (tilemap, tile_data, palette_data) + + tilemap, tileset = convert_tilemap_and_tileset( + extract_tilemap_tiles(image), create_palettes_map(palette_image, bpp) + ) + + tile_data = convert_snes_tileset(tileset, bpp) + + palette_data = convert_palette_image(palette_image) + + return tilemap, tile_data, palette_data diff --git a/roms/snes-test-roms/tools/image2snes.py b/roms/snes-test-roms/tools/image2snes.py new file mode 100644 index 00000000..4219bad5 --- /dev/null +++ b/roms/snes-test-roms/tools/image2snes.py @@ -0,0 +1,95 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# vim: set fenc=utf-8 ai ts=4 sw=4 sts=4 et: +# +# +# SPDX-FileCopyrightText: © 2020 Marcus Rowe +# SPDX-License-Identifier: Zlib +# +# Copyright © 2020 Marcus Rowe +# +# This software is provided 'as-is', without any express or implied warranty. +# In no event will the authors be held liable for any damages arising from the +# use of this software. +# +# Permission is granted to anyone to use this software for any purpose, including +# commercial applications, and to alter it and redistribute it freely, subject to +# the following restrictions: +# +# 1. The origin of this software must not be misrepresented; you must not +# claim that you wrote the original software. If you use this software in +# a product, an acknowledgment in the product documentation would be +# appreciated but is not required. +# +# 2. Altered source versions must be plainly marked as such, and must not be +# misrepresented as being the original software. +# +# 3. This notice may not be removed or altered from any source distribution. + + +import PIL.Image +import argparse + + +from _snes import image_to_snes, create_tilemap_data + + +FORMATS_BPP = { + "2bpp": 2, + "4bpp": 4, + "8bpp": 8, +} + + +def parse_arguments(): + parser = argparse.ArgumentParser() + parser.add_argument( + "-f", "--format", required=True, choices=FORMATS_BPP.keys(), help="tile format" + ) + parser.add_argument( + "-t", "--tileset-output", required=True, help="tileset output file" + ) + parser.add_argument( + "-m", "--tilemap-output", required=True, help="tilemap output file" + ) + parser.add_argument( + "-p", "--palette-output", required=True, help="palette output file" + ) + parser.add_argument( + "--high-priority", + required=False, + action="store_true", + help="increase tilemap priority", + ) + parser.add_argument("image_filename", action="store", help="Indexed png image") + parser.add_argument("palette_image", action="store", help="Palette png image") + + args = parser.parse_args() + + return args + + +def main(): + args = parse_arguments() + + bpp = FORMATS_BPP[args.format] + + image = PIL.Image.open(args.image_filename) + palette_image = PIL.Image.open(args.palette_image) + + tilemap, tileset_data, palette_data = image_to_snes(image, palette_image, bpp) + + tilemap_data = create_tilemap_data(tilemap, args.high_priority) + + with open(args.tileset_output, "wb") as fp: + fp.write(tileset_data) + + with open(args.tilemap_output, "wb") as fp: + fp.write(tilemap_data) + + with open(args.palette_output, "wb") as fp: + fp.write(palette_data) + + +if __name__ == "__main__": + main() diff --git a/roms/snes-test-roms/tools/png2snes.py b/roms/snes-test-roms/tools/png2snes.py new file mode 100644 index 00000000..a49efe32 --- /dev/null +++ b/roms/snes-test-roms/tools/png2snes.py @@ -0,0 +1,153 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# vim: set fenc=utf-8 ai ts=4 sw=4 sts=4 et: +# +# +# SPDX-FileCopyrightText: © 2020 Marcus Rowe +# SPDX-License-Identifier: Zlib +# +# Copyright © 2020 Marcus Rowe +# +# This software is provided 'as-is', without any express or implied warranty. +# In no event will the authors be held liable for any damages arising from the +# use of this software. +# +# Permission is granted to anyone to use this software for any purpose, including +# commercial applications, and to alter it and redistribute it freely, subject to +# the following restrictions: +# +# 1. The origin of this software must not be misrepresented; you must not +# claim that you wrote the original software. If you use this software in +# a product, an acknowledgment in the product documentation would be +# appreciated but is not required. +# +# 2. Altered source versions must be plainly marked as such, and must not be +# misrepresented as being the original software. +# +# 3. This notice may not be removed or altered from any source distribution. + + +import PIL.Image +import argparse +import struct + + +from _snes import convert_rgb_color, convert_snes_tileset + + +def convert_palette(palette, max_colors): + if not palette: + raise ValueError("Image must have a palette") + + data_type, pdata = palette.getdata() + + if data_type != "RGB": + raise ValueError("Image palette is invalid") + + n_colors = len(pdata) / 3 + if n_colors > max_colors: + raise ValueError("Image palette has too many colors") + + snes_pal_data = bytearray() + + for c in struct.iter_unpack("BBB", pdata): + u16 = convert_rgb_color(c) + + snes_pal_data.append(u16 & 0xFF) + snes_pal_data.append(u16 >> 8) + + assert len(snes_pal_data) == n_colors * 2 + return snes_pal_data + + +def extract_tiles(image): + if image.width % 8 != 0 or image.height % 8 != 0: + raise ValueError("Image width MUST BE a multiple of 8") + + if image.height % 8 != 0: + raise ValueError("Image height MUST BE a multiple of 8") + + t_width = image.width // 8 + t_height = image.height // 8 + + img_data = image.getdata() + + for ty in range(t_height): + ty *= 8 + for tx in range(t_width): + tx *= 8 + + tile_data = bytearray() + + for y in range(ty, ty + 8): + for x in range(tx, tx + 8): + tile_data.append(image.getpixel((x, y))) + + yield tile_data + + +def convert_mode7_tileset(tiles): + out = bytes().join(tiles) + + if len(out) > 256 * 64: + raise ValueError("Too many tiles in image") + + return out + + +FORMATS = { + "m7": convert_mode7_tileset, + "mode7": convert_mode7_tileset, + "1bpp": lambda tiles: convert_snes_tileset(tiles, 1), + "2bpp": lambda tiles: convert_snes_tileset(tiles, 2), + "3bpp": lambda tiles: convert_snes_tileset(tiles, 3), + "4bpp": lambda tiles: convert_snes_tileset(tiles, 4), + "8bpp": lambda tiles: convert_snes_tileset(tiles, 8), +} + + +def parse_arguments(): + parser = argparse.ArgumentParser() + parser.add_argument( + "-f", "--format", required=True, choices=FORMATS.keys(), help="tile format" + ) + parser.add_argument( + "-t", "--tileset-output", required=True, help="tileset output file" + ) + parser.add_argument( + "-p", "--palette-output", required=True, help="palette output file" + ) + parser.add_argument( + "-c", + "--max-colors", + required=False, + type=int, + default=256, + help="maximum number of colors", + ) + parser.add_argument("image_filename", action="store", help="Indexed png image") + + args = parser.parse_args() + + return args + + +def main(): + args = parse_arguments() + + tile_converter = FORMATS[args.format] + + image = PIL.Image.open(args.image_filename) + + palette = convert_palette(image.palette, args.max_colors) + tileset = tile_converter(extract_tiles(image)) + + with open(args.tileset_output, "wb") as fp: + fp.write(tileset) + + with open(args.palette_output, "wb") as fp: + fp.write(palette) + + +if __name__ == "__main__": + main() diff --git a/roms/snes-test-roms/tools/write-sfc-checksum.py b/roms/snes-test-roms/tools/write-sfc-checksum.py new file mode 100644 index 00000000..f86b9204 --- /dev/null +++ b/roms/snes-test-roms/tools/write-sfc-checksum.py @@ -0,0 +1,219 @@ +#!/usr/bin/env python3 +# -*- coding: utf-8 -*- +# vim: set fenc=utf-8 ai ts=4 sw=4 sts=4 et: + + +# A simple python script that calculates and writes the SNES header checksum +# (and checksum complement) into the header of a homebrew SNES ROM. +# +# This script is intended to be used on homebrew SNES executables that were +# created with my `snes_header.inc` include file. +# +# WARNING: This script will modify the input file. +# +# +# SPDX-FileCopyrightText: © 2022 Marcus Rowe +# SPDX-License-Identifier: Zlib +# +# Copyright © 2022 Marcus Rowe +# +# This software is provided 'as-is', without any express or implied warranty. +# In no event will the authors be held liable for any damages arising from the +# use of this software. +# +# Permission is granted to anyone to use this software for any purpose, including +# commercial applications, and to alter it and redistribute it freely, subject to +# the following restrictions: +# +# 1. The origin of this software must not be misrepresented; you must not +# claim that you wrote the original software. If you use this software in +# a product, an acknowledgment in the product documentation would be +# appreciated but is not required. +# +# 2. Altered source versions must be plainly marked as such, and must not be +# misrepresented as being the original software. +# +# 3. This notice may not be removed or altered from any source distribution. + + +import os.path +import sys +import argparse + + +MIN_ROM_SIZE = 64 * 1024 +MAX_ROM_SIZE = 4 * 1024 * 1024 + + +def check_header_exists(rom_data, header_offset, expected_map_mode): + """ + Checks that `rom_data` contains an unaltered header that is created by `snes_header.inc`. + + Returns true if header matches expected values + """ + + # snes_header.inc creates a header with a blank maker code, blank game code and no expansion chips. + EXPECTED_START = (6 * b"\x20") + bytes(7) + + EXPECTED_CHECKSUM = b"\xaa\xaa\x55\x55" + + if rom_data[header_offset : header_offset + 13] != EXPECTED_START: + return False + + if rom_data[header_offset + 0x25] & 0xEF != expected_map_mode: + return False + + if rom_data[header_offset + 0x2A] != 0x33: + return False + + # Do not write to files that have changed the checksum bytes (from what is defined in `snes_header`.inc`). + if rom_data[header_offset + 0x2C : header_offset + 0x30] != EXPECTED_CHECKSUM: + return False + + return True + + +def calculate_checksum(rom_data, bank_size, header_offset, expected_map_mode): + """ + Calculate checksum. + + Throws an exception if input is invalid. + + Returns *bytes of length 4* containing checksum and checksum complement. + """ + + rom_size = len(rom_data) + + # Confirm there is no copier header + if rom_size % bank_size != 0: + raise RuntimeError( + f"sfc file is an invalid size (expected a multiple of {bank_size // 1024} KiB)." + ) + + if rom_size < MIN_ROM_SIZE: + raise RuntimeError(f"sfc file is too small (min {MIN_ROM_SIZE // 1024} KiB).") + + if rom_size > 4 * MAX_ROM_SIZE: + raise RuntimeError(f"sfc file is too large (max {MAX_ROM_SIZE // 1024} KiB).") + + # Confirm there is an SFC header in this file + if not check_header_exists(rom_data, header_offset, expected_map_mode): + raise RuntimeError( + "Could not find header. Header must match `snes_header.inc` (and the checksum bytes MUST be unmodified). Is the --hirom/--lorom argument correct?" + ) + + # Check if a cartridge can be created with 2 power-of-two ROM chips + if rom_size.bit_count() > 2: + raise RuntimeError("sfc file is an invalid size (cannot fit on 2 ROM chips)") + + if rom_size.bit_count() == 1: + checksum = sum(rom_data) + else: + # If the sfc file is not a power of two, it is split in two. + # The first part contains the largest power-of-two bytes. + # The second part is repeated until the ROM size is a power-of-two. + + largest_power_of_two = 1 << (rom_size.bit_length() - 1) + + if largest_power_of_two <= bank_size: + # The "Remove old checksum" code below will only work correctly if the checksum is in the first part. + raise RuntimeError("sfc file is too small.") + + first_part_checksum = sum(rom_data[0:largest_power_of_two]) + + remaining = rom_size - largest_power_of_two + assert remaining > 0 + assert remaining.bit_count() == 1 + assert largest_power_of_two % remaining == 0 + + remaining_checksum = sum(rom_data[largest_power_of_two:]) + remaining_count = largest_power_of_two // remaining + + checksum = first_part_checksum + remaining_checksum * remaining_count + + # Remove old checksum and old complement from checksum + checksum -= rom_data[header_offset + 0x2C] + checksum -= rom_data[header_offset + 0x2D] + checksum -= rom_data[header_offset + 0x2E] + checksum -= rom_data[header_offset + 0x2F] + # Add expected `checksum + complement` value to checksum + checksum += 0xFF + checksum += 0xFF + + # Write checksum and complement + checksum = checksum & 0xFFFF + complement = checksum ^ 0xFFFF + + return complement.to_bytes(2, byteorder="little", signed=False) + checksum.to_bytes( + 2, byteorder="little", signed=False + ) + + +def write_sfc_checksum(sfc_filename, bank_size, header_offset, expected_map_mode): + """ + Calculates and writes the checksum for `sfc_filename`. + Throws an exception on error. + """ + + ext = os.path.splitext(sfc_filename)[1] + if ext != ".sfc": + raise RuntimeError("Expected a file with a .sfc extension") + + with open(sfc_filename, "r+b") as fp: + rom_data = fp.read(MAX_ROM_SIZE) + + # Test if fp is not at the end of the file + if fp.read(1): + raise RuntimeError( + f"sfc file is too large (max {MAX_ROM_SIZE // 1024} KiB)." + ) + + checksum_bytes = calculate_checksum( + rom_data, bank_size, header_offset, expected_map_mode + ) + + # Write checksum + fp.seek(header_offset + 0x2C) + fp.write(checksum_bytes) + + +def parse_arguments(): + parser = argparse.ArgumentParser( + allow_abbrev=False, + description="Calculates and writes the SNES header checksum into the header of a homebrew SNES ROM.", + epilog="Distributed under the zlib License, see the script source code for more details.", + ) + + mgroup = parser.add_mutually_exclusive_group(required=True) + mgroup.add_argument( + "--lorom", action="store_true", help="sfc file uses LOROM mapping" + ) + mgroup.add_argument( + "--hirom", action="store_true", help="sfc file uses HIROM mapping" + ) + + parser.add_argument( + "sfc_filename", action="store", help="sfc file (MODIFIED IN PLACE)" + ) + + # Print full help message if there is no arguments + if len(sys.argv) > 1: + return parser.parse_args() + else: + parser.parse_args(["--help"]) + sys.exit("Expected arguments") + + +def main(): + args = parse_arguments() + + if args.lorom: + write_sfc_checksum(args.sfc_filename, 32 * 1024, 0x007FB0, 0x20) + elif args.hirom: + write_sfc_checksum(args.sfc_filename, 64 * 1024, 0x00FFB0, 0x21) + else: + raise RuntimeError("Unknown mapping type") + + +if __name__ == "__main__": + main() diff --git a/roms/snes-tests/.markdownlint-cli2.yaml b/roms/snes-tests/.markdownlint-cli2.yaml new file mode 100644 index 00000000..fdae7462 --- /dev/null +++ b/roms/snes-tests/.markdownlint-cli2.yaml @@ -0,0 +1,4 @@ +config: + MD001: false + MD013: false + MD041: false diff --git a/roms/snes-tests/LICENSE b/roms/snes-tests/LICENSE new file mode 100644 index 00000000..dd9dc05e --- /dev/null +++ b/roms/snes-tests/LICENSE @@ -0,0 +1,21 @@ +MIT License + +Copyright (c) 2023 gilyon + +Permission is hereby granted, free of charge, to any person obtaining a copy +of this software and associated documentation files (the "Software"), to deal +in the Software without restriction, including without limitation the rights +to use, copy, modify, merge, publish, distribute, sublicense, and/or sell +copies of the Software, and to permit persons to whom the Software is +furnished to do so, subject to the following conditions: + +The above copyright notice and this permission notice shall be included in all +copies or substantial portions of the Software. + +THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR +IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE +AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER +LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, +OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE +SOFTWARE. diff --git a/roms/snes-tests/Makefile b/roms/snes-tests/Makefile new file mode 100644 index 00000000..a54512ac --- /dev/null +++ b/roms/snes-tests/Makefile @@ -0,0 +1,7 @@ +all: + $(MAKE) -C cputest + $(MAKE) -C spctest + +package: all + rm -f snes-tests.zip + zip -r snes-tests.zip * -x "*.o" "*.spc" diff --git a/roms/snes-tests/README.md b/roms/snes-tests/README.md new file mode 100644 index 00000000..bc08f2f4 --- /dev/null +++ b/roms/snes-tests/README.md @@ -0,0 +1,15 @@ +# SNES-tests + +ROMs for performing comprehensive tests of the 65C816 and SPC-700 CPUs on the Super Nintendo Entertainment System. + +See the README files in the cputest and spctest directories for more information. + +## Releases + +Download from the [releases page](https://github.com/gilyon/snes-tests/releases). + +The release zip contains: + +- The .sfc ROM files +- Autogenerated tests.txt files, containing the full list of tests and input/output register and memory values for each. +- Autogenerated assembly files containing the tests diff --git a/roms/snes-tests/UPSTREAM.md b/roms/snes-tests/UPSTREAM.md new file mode 100644 index 00000000..6f278382 --- /dev/null +++ b/roms/snes-tests/UPSTREAM.md @@ -0,0 +1,9 @@ +Source: + +Imported from the upstream release archive that includes prebuilt ROM binaries +needed by the SNES rom_test harness. + +- Upstream repository commit: `5ecdf555da920f0bd7b157542141965a8120186d` +- Imported archive: `snes-tests.zip` +- Original contents retained from the release bundle, including LICENSE and + source files under `cputest/` and `spctest/` diff --git a/roms/snes-tests/cputest/.gitignore b/roms/snes-tests/cputest/.gitignore new file mode 100644 index 00000000..422a59be --- /dev/null +++ b/roms/snes-tests/cputest/.gitignore @@ -0,0 +1,5 @@ +tests*.inc +tests*.txt +tests*.map +tests_table.inc + diff --git a/roms/snes-tests/cputest/Makefile b/roms/snes-tests/cputest/Makefile new file mode 100644 index 00000000..1cdbd225 --- /dev/null +++ b/roms/snes-tests/cputest/Makefile @@ -0,0 +1,24 @@ +all: full basic + +full: cputest-full.sfc + +basic: cputest-basic.sfc + + +tests-full.inc tests-full.txt: make_cpu_tests.py + python3 make_cpu_tests.py + +tests-basic.inc tests-basic.txt: make_cpu_tests.py + python3 make_cpu_tests.py --basic + +cputest-full.o: main.asm tests-full.inc font.bin + ca65 main.asm -o cputest-full.o + +cputest-basic.o: main.asm tests-basic.inc font.bin + ca65 -D basic main.asm -o cputest-basic.o + +cputest-full.sfc: cputest-full.o lorom.cfg + ld65 -C lorom.cfg -o cputest-full.sfc cputest-full.o -m tests-full.map -vm + +cputest-basic.sfc: cputest-basic.o lorom.cfg + ld65 -C lorom.cfg -o cputest-basic.sfc cputest-basic.o -m tests-basic.map -vm diff --git a/roms/snes-tests/cputest/README.md b/roms/snes-tests/cputest/README.md new file mode 100644 index 00000000..400ec75b --- /dev/null +++ b/roms/snes-tests/cputest/README.md @@ -0,0 +1,54 @@ +# 65C816 test ROM + +This is an SNES ROM that performs comprehensive testing of the 65C816 instruction set. + +There are two versions of the ROM: + +- cputest-full.sfc performs all the tests. +- cputest-basic.sfc skips some of the tests unlikely to be used by games, such as wrapping behavior in emulation mode. + +If a test fails, see the autogenerated tests-\*.txt or tests-\*.inc files for details about the test. + +### The ROM tests the following + +- All 65C816 opcodes except STP and WAI +- Each instruction is tested in all supported addressing modes +- Multiple tests per instruction, designed to test edge cases and correct flag result +- Wrapping behavior of various addressing modes for all instructions, with and without emulation mode + +### The ROM does *not* test + +- Cycle count taken by instructions, or other timing-related behavior +- Hardware interrupts +- Memory-mapped registers + +## Building + +The required tools are ca65/ld65 and Python 3. + +Either use the Makefile by running `make`, or run: + + python3 make_cpu_tests.py + ca65 main.asm -o cputest.o + ld65 -C lorom.cfg -o cputest.sfc cputest.o + +The above will generate the full sfc. For only basic tests, add `--basic` to the Python command, and `-D basic` to the ca65 command. + +## FAQ + +### How do I find out what a test does? + +The autogenerated tests-\*.txt file (generated when building and available in the release zip) contains a +description of each test, including the input and expected output register/memory values. For more +details, see the autogenerated tests-full.inc or tests-basic.inc assembly file. To debug a test, look for its +address in tests.map. + +### What undocumented behavior is testsed? + +- In emulation mode with S=$1FF, the PLB instruction should read from $200 instead of $100. This is despite +the fact that the CPU manual doesn't list it with the instructions that can access outside the stack page. +- In emulation mode when the low byte of D is nonzero, the (direct,X) addressing mode behaves strangely: + The low byte of the indirect address is read from `direct_addr+X+D` without page wrapping (as expected). The high byte is read from `direct_addr+X+D+1`, but the +1 is done *with* wrapping within the page. + For example: Emulation=1, D=$11A, X=$EE, and the instruction is `lda ($F7,X)`. Here $F7 + $11A + $EE = $2FF. The low byte of the address is read from $2FF and the high byte from $200. + This behavior only applies to this addressing mode, and not to other indirect modes. +- The behavior of decimal mode isn't fully documented. See appendix A of [this document](http://www.6502.org/tutorials/decimal_mode.html#A) for a full specification. diff --git a/roms/snes-tests/cputest/cputest-basic.sfc b/roms/snes-tests/cputest/cputest-basic.sfc new file mode 100644 index 00000000..27a1e853 Binary files /dev/null and b/roms/snes-tests/cputest/cputest-basic.sfc differ diff --git a/roms/snes-tests/cputest/cputest-full.sfc b/roms/snes-tests/cputest/cputest-full.sfc new file mode 100644 index 00000000..5b9c101e Binary files /dev/null and b/roms/snes-tests/cputest/cputest-full.sfc differ diff --git a/roms/snes-tests/cputest/font.bin b/roms/snes-tests/cputest/font.bin new file mode 100644 index 00000000..05af94b8 Binary files /dev/null and b/roms/snes-tests/cputest/font.bin differ diff --git a/roms/snes-tests/cputest/lorom.cfg b/roms/snes-tests/cputest/lorom.cfg new file mode 100644 index 00000000..e338031d --- /dev/null +++ b/roms/snes-tests/cputest/lorom.cfg @@ -0,0 +1,39 @@ +# ca65 linker config + +# Physical areas of memory +# Names need not match, but it makes it easier to remember if they do. +MEMORY { + ZEROPAGE: start = 0, size = $100; + BSS: start = $200, size = $1800; + ROM: start = $8000, size = $8000, fill = yes; + BANK1: start = $18000, size = $8000, fill = yes; + BANK2: start = $28000, size = $8000, fill = yes; + BANK3: start = $38000, size = $8000, fill = yes; + BANK4: start = $48000, size = $8000, fill = yes; + BANK5: start = $58000, size = $8000, fill = yes; + BANK6: start = $68000, size = $8000, fill = yes; + BANK7: start = $78000, size = $8000, fill = yes; +} + +# Logical areas code/data can be put into. +SEGMENTS { + ZEROPAGE: load = ZEROPAGE, type = zp; + BSS: load = BSS, type = bss, align = $100; + + CODE: load = ROM, align = $8000; + RODATA: load = ROM; + TEST_DATA: load = ROM, start = $FFA0; + HEADER: load = ROM, start = $FFC0; + ROMINFO: load = ROM, start = $FFD5, optional = yes; + VECTORS: load = ROM, start = $FFE0; + + # The extra banks + BANK1: load = BANK1, align = $8000, optional = yes; + BANK2: load = BANK2, align = $8000, optional = yes; + BANK3: load = BANK3, align = $8000, optional = yes; + BANK4: load = BANK4, align = $8000, optional = yes; + BANK5: load = BANK5, align = $8000, optional = yes; + BANK6: load = BANK6, align = $8000, optional = yes; + BANK7: load = BANK7, align = $8000, optional = yes; +} + diff --git a/roms/snes-tests/cputest/main.asm b/roms/snes-tests/cputest/main.asm new file mode 100644 index 00000000..98f2e79b --- /dev/null +++ b/roms/snes-tests/cputest/main.asm @@ -0,0 +1,467 @@ +.p816 +.i16 +.a8 + +.segment "HEADER" + .byte "65C816 TEST " +.segment "ROMINFO" ; $FFD5 + .byte $30 ; LoROM + .byte 0 ; no battery/chips + .byte $08 ; 256K + .byte 0, 0, 0, 0 + .word $0000, $FFFF ;checksum+complement + +native_brk_handler = $1000 +native_cop_handler = $1004 +emulation_brk_handler = $1008 +emulation_cop_handler = $100C +vblank_every_n_tests = 10 + +.segment "VECTORS" + .word 0, 0, native_cop_handler, native_brk_handler, 0, 0, 0, 0 + .word 0, 0, emulation_cop_handler, 0, 0, 0, main, emulation_brk_handler + +.segment "ZEROPAGE" +.res $10 +test_num: .word 0 +result_a: .word 0 +result_x: .word 0 +result_y: .word 0 +result_p: .word 0 +result_s: .word 0 +result_d: .word 0 +result_dbr: .byte 0 +retaddr: .word 0 ; return address from bankN_save_results +vblank_counter: .byte 0 ; wait for vblank when it reaches 0 + +.segment "CODE" + + +main: + clc + xce + sei + rep #$18 ; 16 bit X/Y + sep #$20 ; 8 bit A + ldx #$01EF + txs + + jsr init + + ldx #$ffff + stx test_num + jmp start_tests + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init: + jsr init_regs + jsr init_video_mem + jsr init_mem + + ldx #txt_running + ldy #$21 + jsr write_text + + ldx #txt_testnum + ldy #$61 + jsr write_text + + lda #$0F ; screen on + sta $2100 + + jsr wait_for_vblank + + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init_regs: + lda #$8F ; screen off + sta $2100 + + stz $2105 ; BG mode 0, 8x8 tiles + stz $2106 ; No mosaic + stz $2107 ; BG1: 32x32 tilemap at address 0 + lda #$04 + sta $210B ; BG1 tiles at byte $8000 / word $4000 + stz $210D ; BG1HOFS = 0 + stz $210D + lda #$FF + sta $210E ; BG1VOFS = -1 + sta $210E + lda #$80 + sta $2115 ; VMAIN: inc address by 1 after high byte + stz $2121 ; Palette addr = 0 + stz $2122 + stz $2122 ; palette 0 = black + lda #$FF + sta $2122 + sta $2122 ; palette 1 = white + lda #$01 + sta $212C ; enable BG1 + stz $212D ; disable subscreen + stz $212E ; no window masking + stz $2130 ; no window force black + lda #$30 + sta $2131 ; no color math + stz $2133 ; no hires/interlace/overscan + lda #$01 + sta $4200 ; no NMI/IRQ, joypad autoread enabled + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init_video_mem: + ; clear vmem + stz $2116 + stz $2117 ; VADDR = 0 + + lda #$09 + sta $4300 ; DMA0: to ppu, write to 2 registers, no increment + lda #$18 + sta $4301 ; DMA0: Write to PPU 2118/2119 (VMDATA) + lda #zero + sta $4303 + lda #^zero + sta $4304 + stz $4305 + stz $4306 ; 65536 bytes + lda #$01 + sta $420B ; run DMA0 + + ; copy font to vmem + stz $2116 + lda #$40 + sta $2117 ; VADDR = $4000 (word address) + lda #$01 + sta $4300 ; DMA0: to ppu, 2 bytes->2 registers, inc by 1 + lda #font + sta $4303 + lda #^font + sta $4304 + stz $4305 + lda #$08 + sta $4306 ; 2048 bytes + lda #$01 + sta $420B ; run DMA0 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init_mem: + ; Put STP opcodes in some places in case of errant jumps or software interrupts + lda #$DB + ; BRK/COP handlers + sta $1000 + sta $1004 + sta $1008 + sta $100C + + lda #$01 + sta vblank_counter + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 0:x = text (null-terminated). y = vmem word address +write_text: + sty $2116 +@loop: + lda $00,x + beq @end + sta $2118 + stz $2119 + inx + bra @loop +@end: + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; a = val. y = vmem word address +write_hex8: + sty $2116 + pha + lsr a + lsr a + lsr a + lsr a + clc + jsr @write_digit + pla + and #$0F +@write_digit: ; write hex digit in A + cmp #$0A + bcc @num + clc + adc #'A'-$0A-'0' +@num: + clc + adc #'0' + sta $2118 + stz $2119 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +; 0:x = address. y = vmem word address +write_hex16: + lda $01,x + jsr write_hex8 + lda $00,x + iny + iny + jsr write_hex8 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; x = new test num +init_test: + ; Check that we haven't skipped a test + dex + cpx test_num + beq @ok + + ; ** Invalid test order - possibly an errant jump ** + clc + xce + sei + rep #$18 ; 16 bit X/Y + sep #$20 ; 8 bit A + ldx #$01EF + txs + + jsr wait_for_vblank + jsr update_test_num + ldx #txt_fail + ldy #$32 + jsr write_text + ldx #txt_skipped + ldy #$A1 + jsr write_text +@end: + jmp @end + +@ok: + inx + stx test_num + + ; Every N tests, wait for vblank. This is done to ensure that we're only updating the + ; screen during vblank so that the update takes effect. + dec vblank_counter + bne @after_vblank + jsr wait_for_vblank + lda #vblank_every_n_tests + sta vblank_counter +@after_vblank: + + jsr update_test_num + rtl + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; Save the register values, and reset state (D, DBR, etc.) +save_results: + ; p register was already saved, and emulation mode was cleared. + sei + rep #$38 + .a16 + .i16 + phd + pha + lda #$0000 + tcd + pla + sta result_a + stx result_x + sty result_y + plx ; d register + stx result_d + tsc ; original S value minus 3 (due to jsl). + inc a + inc a + inc a + sta result_s + + sep #$20 + .a8 + phb + pla + sta result_dbr + lda #$00 + pha + plb + rtl + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +success: + jsr wait_for_vblank + jsr update_test_num + + ldx #txt_success + ldy #$32 + jsr write_text + +@end: jmp @end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +update_test_num: + ldx #test_num + ldy #$6E + jmp write_hex16 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +fail: + ldx #$1ef + txs ; in case s is invalid + jsr wait_for_vblank + jsr update_test_num + + ldx #txt_fail + ldy #$32 + jsr write_text + ldx #txt_a + ldy #$A1 + jsr write_text + ldx #txt_x + ldy #$C1 + jsr write_text + ldx #txt_y + ldy #$E1 + jsr write_text + ldx #txt_p + ldy #$101 + jsr write_text + ldx #txt_s + ldy #$121 + jsr write_text + + lda result_p + ldy #$105 + jsr write_hex8 + + ldx #result_a + ldy #$A5 + jsr write_hex16 + + ldx #result_x + ldy #$C5 + jsr write_hex16 + + ldx #result_y + ldy #$E5 + jsr write_hex16 + + ldx #result_s + ldy #$125 + jsr write_hex16 + + + jsr wait_for_key + jsr wait_for_vblank + jsr init + + ; jump to next test + + rep #$20 + .a16 + lda test_num + inc a + asl a ; A = (test_num+1) * 2 + sec + adc test_num ; A = (test_num+1) * 3 + tax + sep #$20 + .a8 + ldy tests_table,x ; y = test offset + lda tests_table+2,x ; a = test bank + pha + dey ; the return address should be 1 less than the target + phy + rtl ; actually a jump to the next test + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +wait_for_key: + ldx #txt_press + ldy #$341 + jsr write_text +@wait_press: + lda $4212 + bit #$01 + bne @wait_press ; wait for joypad auto-read to finish + lda $4218 ; joypad 1 low byte + bpl @wait_press + +@wait_release: + lda $4212 + bit #$01 + bne @wait_release ; wait for joypad auto-read to finish + lda $4218 ; joypad 1 low byte + bmi @wait_release + + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +wait_for_vblank: +@wait1: + bit $4210 + bmi @wait1 +@wait2: + bit $4210 + bpl @wait2 + rts + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +.ifdef basic + .include "tests-basic.inc" +.else + .include "tests-full.inc" +.endif + + +.segment "RODATA" +txt_running: .byte "Running tests...", 0 +txt_success: .byte "Success", 0 +txt_fail: .byte "Failed", 0 +txt_skipped: .byte "Invalid test order", 0 +txt_testnum: .byte "Test number:", 0 +txt_press: .byte "Press A for next tests...", 0 +txt_a: .byte "A = ", 0 +txt_x: .byte "X = ", 0 +txt_y: .byte "Y = ", 0 +txt_p: .byte "P = ", 0 +txt_s: .byte "S = ", 0 +zero: + .byte 0, 0 +font: + .incbin "font.bin" + +tests_table: + .include "tests_table.inc" + .faraddr success + +.segment "TEST_DATA" ; At address FFA0. Used by some tests +test_addr: ; $FFA0 + .word $1212 +test_target: ; $FFA2 + .word $8000 +test_target24: ; $FFA4 + .word $8000 + .byte $7E diff --git a/roms/snes-tests/cputest/make_cpu_tests.py b/roms/snes-tests/cputest/make_cpu_tests.py new file mode 100644 index 00000000..bcc5e7fb --- /dev/null +++ b/roms/snes-tests/cputest/make_cpu_tests.py @@ -0,0 +1,2177 @@ +from textwrap import dedent +import re +import sys + +test_num = 0 +bank_num = 0 +tests_in_bank = 0 +basic_tests_only = False +asm_code = [] +tests_txt = [] + +# Limit tests per bank to not exceed 32KB. Bank 0 has less room due to other code and data in it. +TESTS_IN_BANK0 = 230 +TESTS_PER_BANK = 360 + + +# emulation mode flag (E) is treated as a 9th bit here for convenience +FLAGS_MAP = { + "C": 1, + "Z": 2, + "I": 4, + "D": 8, + "X": 0x10, + "B": 0x10, + "M": 0x20, + "V": 0x40, + "N": 0x80, + "E": 0x100, +} + +FLAG_M = 0x20 +FLAG_X = 0x10 +FLAG_E = 0x100 # not a real flag + +OPCODE_STP = 0xDB + +# Addressing modes +A_IMM = 0 # #$12 or #$1234 +A_ACCUM = 1 # a +A_ABS = 2 # $1234 +A_ABS_X = 3 # $1234,x +A_ABS_Y = 4 # $1234,y +A_DIR = 5 # $12 +A_DIR_X = 6 # $12,x +A_DIR_Y = 7 # $12,y +A_IND_DIR = 8 # ($12) +A_IND_LONG_DIR = 9 # [$12] +A_DIR_X_IND = 10 # ($12,x) +A_IND_DIR_Y = 11 # ($12),y +A_IND_LONG_DIR_Y = 12 # [$12],y +A_LONG = 13 # $123456 +A_LONG_X = 14 # $123456,x +A_STACK_S = 15 # $12,s +A_IND_STACK_S_Y = 16 # ($12,s),y + +A_IND_ABS = 17 # ($1234) - jmp only +A_ABS_X_IND = 18 # ($1234,x) - jmp/jsr only +A_IND_LONG_ABS = 19 # [$1234] - jmp (a.k.a. jml) only + +# Others for specific instructions: implied, rel8, rel16, source+dest, + + +# Modes for read-only instructions like lda or eor +READ_MODES = [ + A_IMM, + A_DIR_X_IND, + A_STACK_S, + A_DIR, + A_IND_LONG_DIR, + A_ABS, + A_LONG, + A_IND_DIR_Y, + A_IND_DIR, + A_IND_STACK_S_Y, + A_DIR_X, + A_IND_LONG_DIR_Y, + A_ABS_Y, + A_ABS_X, + A_LONG_X, +] + + +# Instructions whose operand size depends on the X flag +_ins_index_size = set( + ( + "cpx cpy dex dey inx iny ldx ldy phx phy plx ply stx sty tax tay tsx txy tyx".split() + ) +) +# Instructions whose operand size depends on the M flag +_ins_acc_size = set( + ( + "adc and asl bit cmp dec eor inc lda lsr ora pha pla rol ror sbc sta stz trb tsb txa tya".split() + ) +) + +_re_leading_space = re.compile(r"^[ \t]+.", re.MULTILINE) + +UNDOCUMENTED_COMMENT = ( + "This tests undocumented behavior - see the cputest README file for details" +) + + +def add_asm(code): + code = dedent(code) + if not _re_leading_space.search(code): + # all lines are unindented, so add indentation + code = " " + code.replace("\n", "\n ") + + asm_code.append(code) + + +def flags(p, default=None, add=None): + """Return flags byte, converting from string and adding `add` if needed""" + if p is None: + return flags(default or 0, add=add) + if isinstance(p, int): + ret = p + else: + ret = sum(FLAGS_MAP[c] for c in set(p)) + if add is not None: + ret |= flags(add) + return ret + + +def next_bank_if_needed(): + if (bank_num == 0 and tests_in_bank == TESTS_IN_BANK0) or ( + bank_num != 0 and tests_in_bank == TESTS_PER_BANK + ): + next_bank() + + +def test( + ins, + a=0x1234, + x=0x3456, + y=0x5678, + p=None, + ea=None, + ex=None, + ey=None, + ep=None, + dbr=None, + edbr=None, + d=None, + ed=None, + s=None, + es=None, + before_regs=None, + before_ins=None, + after_ins=None, + after_checks=None, + ins_name=None, + comment=None, + advanced=None, + **kwargs, +): + """Test the given instruction, setting registers/memory before and checking them after. + + - ins is the instruction to execute + - a, x, y, p, s, d, dbr are the input register values + - e* are the expected output values. If None then they should be the same as input (for a,x,y). + - mem_abcdef means this is the input value in memory location $ABCDEF. + - emem_abcdef is the expected output value in this memory location. + - before_regs, before_ins, after_ins, after_checks are used to add additional assembly code + at specific points. + - ins_name will be written instead of the ins in tests.txt if provided. It doesn't + affect the ROM. + - comment wil be written to texts.txt. + - advanced is true for an advanced test, i.e. for behavior not likely to be used in games. + The default (when advanced is None) is that tests with E=1 are considered advanced. + """ + + global test_num, tests_in_bank + + p = flags(p) + ep = flags(ep, p) + + if advanced is None: + advanced = bool(p & FLAG_E) + if advanced and basic_tests_only: + return + + next_bank_if_needed() + + if ea is None: + ea = a + if ex is None: + ex = x + if (p | ep) & (FLAG_X | FLAG_E): + ex &= 0xFF + if ey is None: + ey = y + if (p | ep) & (FLAG_X | FLAG_E): + ey &= 0xFF + + mem_input = [] + mem_output = {} + for k, v in kwargs.items(): + if k.startswith("mem_"): + mem_input.append((int(k[4:], 16), v)) + elif k.startswith("memw_"): + addr = int(k[5:], 16) + mem_input.append((addr, v & 0xFF)) + mem_input.append((addr + 1, v >> 8)) + elif k.startswith("emem_"): + mem_output[int(k[5:], 16)] = v + elif k.startswith("ememw_"): + addr = int(k[6:], 16) + mem_output[addr] = v & 0xFF + mem_output[addr + 1] = v >> 8 + else: + assert False, "Invalid keyword: " + k + + # assumption: 16-bit indexes, 8-bit accum + if comment is not None: + asm_code.append(f"; {comment}") + add_asm(f"""\ + test{test_num:04x}: + .export test{test_num:04x}: far + ldx #${test_num:02x} + jsl init_test""") + + if before_regs: + add_asm(before_regs) + for loc, val in mem_input: + # if loc not in mem_output: + # mem_output[loc] = val + add_asm(f"lda #${val:02x}") + add_asm(f"sta ${loc:06x}") + + if dbr is not None: + add_asm(f"""\ + lda #${dbr:02x} + pha + plb""") + add_asm("""\ + rep #$20 + .a16""") + if d: + add_asm(f"""\ + lda #${d:04x} + tcd""") + if s is not None: + add_asm(f"""\ + ldx #${s:04x} + txs""") + add_asm(f"""\ + lda #${a:04x} + ldx #${x:04x} + ldy #${y:04x}""") + if p & FLAG_E: + add_asm("sec") + add_asm("xce") + add_asm(f"""\ + rep #${~p & 0xFF:02x} + sep #${p & 0xFF:02x}""") + if p & (FLAG_E | FLAG_M): + add_asm(".a8") + if p & (FLAG_E | FLAG_X): + add_asm(".i8") + + if before_ins: + add_asm(before_ins) + add_asm(ins) + if after_ins: + add_asm(after_ins) + add_asm(f"""\ + jsr bank{bank_num}_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #${ex:04x} + bne @to_fail + cpy #${ey:04x} + bne @to_fail + ldx result_p + cpx #${ep:04x} + bne @to_fail + ldx result_a + cpx #${ea:04x} + bne @to_fail""") + if es is not None: + add_asm(f"""\ + ldx result_s + cpx #${es:04x} + bne @to_fail""") + if edbr is not None: + add_asm(f"""\ + lda result_dbr + cmp #${edbr:02x} + bne @to_fail""") + if ed is not None: + add_asm(f"""\ + ldx result_d + cpx #${ed:04x} + bne @to_fail""") + + for loc, val in mem_output.items(): + if val is not None: + add_asm(f"""\ + lda ${loc:06x} + cmp #${val:02x} + bne @to_fail""") + + if es is not None: + # We expect S to change, so restore the original value now + add_asm("""\ + ldx #$1EF + txs""") + if after_checks: + add_asm(after_checks) + + add_asm("""\ + bra @next_test + @to_fail: + jml fail + @next_test: + """) + + tests_txt.append(f"Test {test_num:04x}: {ins_name or ins}") + inputs = ( + f"A=${a:04x} X=${x:04x} Y=${y:04x} P=${p & 0xFF:02x} E={1 if p & FLAG_E else 0}" + ) + if s is not None: + inputs += f" S=${s:04x}" + if dbr is not None: + inputs += f" DBR=${dbr:02x}" + if d is not None: + inputs += f" D=${d:04x}" + if mem_input: + inputs += " " + " ".join(f"(${loc:06x})=${val:02x}" for loc, val in mem_input) + outputs = f"A=${ea:04x} X=${ex:04x} Y=${ey:04x} P=${ep & 0xFF:02x} E={1 if ep & FLAG_E else 0}" + if es is not None: + outputs += f" S={es:04x}" + if edbr is not None: + outputs += f" DBR={edbr:02x}" + if ed is not None: + outputs += f" D={ed:04x}" + if mem_output: + outputs += " " + " ".join( + f"(${loc:06x})=${val:02x}" + for loc, val in mem_output.items() + if val is not None + ) + + tests_txt.append(f" Input: {inputs}") + tests_txt.append(f" Expected output: {outputs}") + if before_regs or before_ins or after_ins or after_checks: + tests_txt.append( + " Additional initialization or checks are performed - see assembly" + ) + if comment is not None: + tests_txt.append(f" Note: {comment}") + + test_num += 1 + tests_in_bank += 1 + + +def test_ins_with_modes(ins, modes, val, result=None, p="", ep=None, **kwargs): + """Test an instruction in all the specified modes. + val is the input value of memory/immediate for the operand. result (if given) is the expected output value. + Other parameters are passed to test(). + + Each instruction should be tested with all supported modes at least once for 16-bit and once for 8-bit. + Additional tests can be performed on less modes to save space. + """ + + def do_test(operand, add_flag="", mem=None, **kwargs2): + full_ins = ins + " " + operand + kwargs3 = kwargs.copy() + kwargs3.update(kwargs2) + if mem is not None: + suffix = "" if bits == 8 else "w" + kwargs3[f"mem{suffix}_{mem:06x}"] = val + kwargs3[f"emem{suffix}_{mem:06x}"] = result + p2 = flags(p, add=add_flag) + ep2 = flags(ep, p, add=add_flag) + if flags(add_flag) & FLAG_E: + ep2 |= FLAG_M | FLAG_X # these are always on in emulation mode + test(full_ins, p=p2, ep=ep2, **kwargs3) + + if result is None: + result = val + + p = flags(p) + ep = flags(ep, p) + + operand_uses_x_size = ins in _ins_index_size + operand_uses_m_size = ins in _ins_acc_size + if operand_uses_x_size: + bits = 8 if p & FLAG_X else 16 + elif operand_uses_m_size: + bits = 8 if p & FLAG_M else 16 + else: + assert False, ( + "This function is only called on instructions with operands of variable size" + ) + + for mode in modes: + if mode == A_IMM: + assert result == val + do_test(f"#${val:02x}") # may be 8-bit or 16-bit, depending on flags + elif mode == A_ACCUM: + if bits == 16: + do_test("a", a=val, ea=result) + else: # 8-bit: add some data in high bits to see it doesn't change + do_test("a", a=val | 0x1200, ea=result | 0x1200) + elif mode == A_ABS: + do_test("$FFFF", dbr=0x7E, mem=0x7EFFFF) + if bits == 8: + do_test( + "$FFFF", dbr=0x7E, mem=0x7EFFFF, add_flag="E" + ) # works the same in emulation mode + elif mode == A_ABS_X: + if not operand_uses_x_size or bits == 16: + do_test("$FFFF,x", x=0x300, dbr=0x7E, mem=0x7F02FF) # 16 bit index + if not operand_uses_x_size or bits == 8: + do_test( + "$FFFF,x", x=0x1230, dbr=0x7E, mem=0x7F002F, add_flag="X" + ) # 8 bit index + if bits == 8: + do_test( + "$FFFF,x", x=0x1230, dbr=0x7E, mem=0x7F002F, add_flag="E" + ) # emulation mode (8 bit index) + elif mode == A_ABS_Y: + if not operand_uses_x_size or bits == 16: + do_test("$FFFF,y", y=0x300, dbr=0x7E, mem=0x7F02FF) # 16 bit index + if not operand_uses_x_size or bits == 8: + do_test( + "$FFFF,y", y=0x1230, dbr=0x7E, mem=0x7F002F, add_flag="X" + ) # 8 bit index + if bits == 8: + do_test( + "$FFFF,y", y=0x1230, dbr=0x7E, mem=0x7F002F, add_flag="E" + ) # emulation mode (8 bit index) + elif mode == A_DIR: + # set DBR to 7F to make sure the actual read is done from bank 0 and not DBR. + do_test("$34", mem=0x33, d=0xFFFF, dbr=0x7F) + if bits == 8: + # Note: although supposedly E=1 and DL=0 wraps within the page, wrapping will never happen for DL=0 so this is meaningless. + do_test("$34", mem=0x33, d=0xFFFF, dbr=0x7F, add_flag="E") + elif mode == A_DIR_X: + if not operand_uses_x_size or bits == 16: + do_test("$02,x", x=0x133, mem=0x134, d=0xFFFF, dbr=0x7F) # 16 bit index + if not operand_uses_x_size or bits == 8: + do_test( + "$02,x", x=0x1232, mem=0x33, d=0xFFFF, dbr=0x7F, add_flag="X" + ) # 8 bit index + if bits == 8: + # E=1: Wraps in page for DL=0, or bank for DL!=0 + do_test("$02,x", x=0x32, mem=0x33, d=0xFFFF, dbr=0x7F, add_flag="E") + do_test("$FF,x", x=0x34, mem=0x133, d=0x0100, dbr=0x7F, add_flag="E") + elif mode == A_DIR_Y: + assert operand_uses_x_size # only ldx, stx + if bits == 16: + do_test("$02,y", y=0x133, mem=0x134, d=0xFFFF, dbr=0x7F) # 16 bit index + if bits == 8: + do_test( + "$02,y", y=0x1232, mem=0x33, d=0xFFFF, dbr=0x7F, add_flag="X" + ) # 8 bit index + # E=1: Wraps in page for DL=0, or bank for DL!=0 + do_test("$02,y", y=0x32, mem=0x33, d=0xFFFF, dbr=0x7F, add_flag="E") + do_test("$FF,y", y=0x34, mem=0x133, d=0x0100, dbr=0x7F, add_flag="E") + elif mode == A_IND_DIR: + do_test("($34)", mem=0x7F1234, d=0xFFFF, memw_0033=0x1234, dbr=0x7F) + # There doesn't seem to be a way to test bank 0 wrapping due to wram mirroring + if bits == 16: # test no bank wrapping at destination + do_test( + "($34)", + mem=0x7EFFFF, + d=0xFFFF, + memw_0033=0xFFFF, + dbr=0x7E, + advanced=True, + ) + if bits == 8: + # E=1, DL=0: Wraps in page + do_test( + "($FF)", + mem=0x7F1234, + d=0x0100, + mem_01FF=0x34, + mem_0100=0x12, + dbr=0x7F, + add_flag="E", + ) + # No page wrap with DL != 0. The write at 100 is to make sure we don't use it: + do_test( + "($FE)", + mem=0x7F1234, + d=0x0101, + memw_01FF=0x1234, + mem_0100=0x00, + dbr=0x7F, + add_flag="E", + ) + elif mode == A_IND_LONG_DIR: + do_test("[$34]", mem=0x7F1234, d=0xFFFF, memw_0033=0x1234, mem_0035=0x7F) + # There doesn't seem to be a way to test bank 0 wrapping due to wram mirroring + if bits == 16: # test no bank wrapping at destination + do_test( + "[$34]", + mem=0x7EFFFF, + d=0xFFFF, + memw_0033=0xFFFF, + mem_0035=0x7E, + advanced=True, + ) + if bits == 8: + # E=1: No wrapping in page, even with DL=0 + do_test( + "[$FF]", + mem=0x7F1234, + d=0x0100, + memw_01FF=0x1234, + mem_0201=0x7F, + add_flag="E", + ) + elif mode == A_DIR_X_IND: + assert operand_uses_m_size + # $00FFA0 contains a pointer to $1212. Use it to test bank 0 wrapping + do_test("($10,x)", mem=0x7F1212, d=0xFFFF, x=0xFF91, dbr=0x7F) + if bits == 16: # test no bank wrapping at destination + do_test( + "($10,x)", + mem=0x7EFFFF, + d=0xFF00, + x=0x123, + memw_0033=0xFFFF, + dbr=0x7E, + advanced=True, + ) + + # 8 bit index + do_test("($90,x)", mem=0x7F1212, x=0x1210, d=0xFF00, dbr=0x7F, add_flag="X") + + if bits == 8: + # E=1, DL=0: Wraps in page + do_test( + "($EF,x)", + mem=0x7F1234, + x=0x10, + d=0x0100, + mem_01FF=0x34, + mem_0100=0x12, + dbr=0x7F, + add_flag="E", + ) + do_test( + "($F0,x)", + mem=0x7F1234, + x=0x10, + d=0x0100, + memw_0100=0x1234, + dbr=0x7F, + add_flag="E", + ) + + # With E=1, DL != 0: There is no wrapping for the dp+D+X calculation, but the +1 addition for the high byte DOES wrap. + # This behavior is undocumented. + do_test( + "($F6,x)", + mem=0x7F1234, + x=0xEE, + d=0x011A, + memw_02FE=0x1234, + dbr=0x7F, + add_flag="E", + ) + do_test( + "($F7,x)", + mem=0x7F1234, + x=0xEE, + d=0x011A, + mem_02FF=0x34, + mem_0200=0x12, + dbr=0x7F, + add_flag="E", + comment=UNDOCUMENTED_COMMENT, + ) + elif mode == A_IND_DIR_Y: + assert operand_uses_m_size + do_test( + "($34),y", mem=0x7F0FDC, y=0x1100, d=0xFFFF, memw_0033=0xFEDC, dbr=0x7E + ) + # 8 bit index + do_test( + "($34),y", + mem=0x7FFEEC, + y=0x1110, + d=0xFFFF, + memw_0033=0xFEDC, + dbr=0x7F, + add_flag="X", + ) + # There doesn't seem to be a way to test bank 0 wrapping due to wram mirroring + if bits == 16: # test no bank wrapping at destination + do_test( + "($34),y", + mem=0x7EFFFF, + d=0xFFFF, + y=0x1111, + memw_0033=0xEEEE, + dbr=0x7E, + advanced=True, + ) + if bits == 8: + # E=1, DL=0: Wraps in page + do_test( + "($FF),y", + mem=0x7F1244, + y=0x10, + d=0x0100, + mem_01FF=0x34, + mem_0100=0x12, + dbr=0x7F, + add_flag="E", + ) + # No page wrap with DL != 0. The write at 100 is to make sure we don't use it: + do_test( + "($FE),y", + mem=0x7F1244, + y=0x10, + d=0x0101, + memw_01FF=0x1234, + mem_0100=0x00, + dbr=0x7F, + add_flag="E", + ) + elif mode == A_IND_LONG_DIR_Y: + assert operand_uses_m_size + do_test( + "[$34],y", + mem=0x7F0FDC, + y=0x1100, + d=0xFFFF, + memw_0033=0xFEDC, + mem_0035=0x7E, + ) + # There doesn't seem to be a way to test bank 0 wrapping due to wram mirroring + + # 8 bit index + do_test( + "[$34],y", + mem=0x7FFEEC, + y=0x1110, + d=0xFFFF, + memw_0033=0xFEDC, + mem_0035=0x7F, + add_flag="X", + ) + if bits == 16: # test no bank wrapping at destination + do_test( + "[$34],y", + mem=0x7EFFFF, + d=0xFFFF, + y=0x1111, + memw_0033=0xEEEE, + mem_0035=0x7E, + advanced=True, + ) + if bits == 8: + # E=1: No wrapping in page, even with DL=0 + do_test( + "[$FF],y", + mem=0x7F1244, + y=0x10, + d=0x0100, + memw_01FF=0x1234, + mem_0201=0x7F, + add_flag="E", + ) + elif mode == A_LONG: + do_test("$7EFFFF", mem=0x7EFFFF) + if bits == 8: + do_test( + "$7EFFFF", mem=0x7EFFFF, add_flag="E" + ) # works the same in emulation mode + elif mode == A_LONG_X: + assert operand_uses_m_size + do_test("$7EFFFF,x", x=0x300, mem=0x7F02FF) # 16 bit index + do_test("$7EFFFF,x", x=0x1230, mem=0x7F002F, add_flag="X") # 8 bit index + if bits == 8: + do_test( + "$7EFFFF,x", x=0x1230, mem=0x7F002F, add_flag="E" + ) # emulation mode (8 bit index) + elif mode == A_STACK_S: + # currently s = 1ef + do_test("$12,s", mem=0x201) + if bits == 8: + # E=1: Can leave the stack page. + do_test("$12,s", mem=0x201, add_flag="E") + elif mode == A_IND_STACK_S_Y: + # currently s = 1ef + assert operand_uses_m_size + do_test("($10,s),y", mem=0x7F0FDC, y=0x1100, memw_01FF=0xFEDC, dbr=0x7E) + # 8 bit index + do_test( + "($10,s),y", + mem=0x7FFEEC, + y=0x1110, + memw_01FF=0xFEDC, + dbr=0x7F, + add_flag="X", + ) + # There doesn't seem to be a way to test bank 0 wrapping due to wram mirroring + if bits == 16: # test no bank wrapping at destination + do_test( + "($10,s),y", + mem=0x7EFFFF, + y=0x1111, + memw_01FF=0xEEEE, + dbr=0x7E, + advanced=True, + ) + if bits == 8: + # E=1: Can leave the stack page. + do_test( + "($12,s),y", + mem=0x7FFEEC, + y=0x1110, + memw_0201=0xFEDC, + dbr=0x7F, + add_flag="E", + ) + + +def jml_to_label_instructions(addr, label): + """Return asm code that writes a jmp long (jml) instruction to the specified label at the specified address""" + return f"""\ + lda #$5C ; jmp long opcode + sta ${addr:04x} + lda #<{label} + sta ${addr + 1:04x} + lda #>{label} + sta ${addr + 2:04x} + lda #^{label} + sta ${addr + 3:04x}""" + + +def jml_to_ok_instructions(addr): + """Return asm code that writes a jmp long (jml) instruction to the @ok label at the specified address""" + return jml_to_label_instructions(addr, "@ok") + + +def adc_binary_tests(): + test_ins_with_modes("adc", READ_MODES, a=0x1234, val=0xEDCB, ea=0, p="C", ep="CZ") + test_ins_with_modes("adc", [A_IMM], a=0x6789, val=0x2000, ea=0x8789, p="", ep="VN") + test_ins_with_modes("adc", [A_IMM], a=0x8000, val=0x8000, ea=0, p="ZIVN", ep="CZIV") + test_ins_with_modes("adc", [A_IMM], a=0x9000, val=0xE000, ea=0x7001, p="C", ep="CV") + + test_ins_with_modes( + "adc", READ_MODES, a=0x1112, val=0xED, ea=0x1100, p="MC", ep="MCZ" + ) + test_ins_with_modes("adc", [A_IMM], a=0x1167, val=0x20, ea=0x1187, p="M", ep="MVN") + test_ins_with_modes( + "adc", [A_IMM], a=0x1180, val=0x80, ea=0x1100, p="MZIVN", ep="MCZIV" + ) + test_ins_with_modes("adc", [A_IMM], a=0x1190, val=0xE0, ea=0x1171, p="MC", ep="MCV") + + +def adc_decimal_tests(): + # The V flag is binary overflow for the sum of the most significant nibbles + carry from lower nibbles. + test_ins_with_modes("adc", READ_MODES, a=0x1234, val=0x8765, ea=0, p="DC", ep="DCZ") + test_ins_with_modes( + "adc", [A_IMM], a=0x3550, val=0x4470, ea=0x8020, p="D", ep="DNV" + ) + test_ins_with_modes("adc", [A_IMM], a=0x4000, val=0x3999, ea=0x7999, p="D", ep="D") + test_ins_with_modes( + "adc", [A_IMM], a=0xDCBA, val=0xDBCA, ea=0x1EEA, p="D", ep="DC", advanced=True + ) + + test_ins_with_modes( + "adc", READ_MODES, a=0xCC12, val=0x87, ea=0xCC00, p="DMC", ep="DMCZ" + ) + test_ins_with_modes( + "adc", [A_IMM], a=0xCC40, val=0x40, ea=0xCC80, p="DM", ep="DMNV" + ) + test_ins_with_modes("adc", [A_IMM], a=0xCC40, val=0x39, ea=0xCC79, p="DM", ep="DM") + test_ins_with_modes( + "adc", [A_IMM], a=0xCCDC, val=0xDB, ea=0xCC1D, p="DM", ep="DMC", advanced=True + ) + + +def and_tests(): + test_ins_with_modes( + "and", READ_MODES, a=0xFEFF, val=0xEF5C, p="", ea=0xEE5C, ep="N" + ) + test_ins_with_modes("and", [A_IMM], a=0x5555, val=0xAAAA, p="", ea=0x0000, ep="Z") + test_ins_with_modes( + "and", [A_IMM], a=0x1234, val=0x4300, p="CZIDVN", ea=0x0200, ep="CIDV" + ) + + test_ins_with_modes( + "and", READ_MODES, a=0x12FE, val=0xDF, p="M", ea=0x12DE, ep="MN" + ) + test_ins_with_modes("and", [A_IMM], a=0x5555, val=0xAA, p="M", ea=0x5500, ep="MZ") + + +def asl_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + test_ins_with_modes("asl", modes, 0x8000, 0x0000, p="", ep="ZC") + test_ins_with_modes("asl", modes, 0x4111, 0x8222, p="CZIDVN", ep="IDVN") + + test_ins_with_modes("asl", modes, 0x80, 0x00, p="M", ep="MZC") + test_ins_with_modes("asl", modes, 0x41, 0x82, p="CZIDMVN", ep="IDMVN") + + +def bit_tests(): + # immediate mode doesn't set N and V flags + test_ins_with_modes("bit", [A_IMM], 0x1234, a=0x9377, p="CZIDVN", ep="CIDVN") + test_ins_with_modes("bit", [A_IMM], 0xAAAA, a=0x5555, p="", ep="Z") + test_ins_with_modes("bit", [A_IMM], 0xAA, a=0x56, p="M", ep="M") + test_ins_with_modes("bit", [A_IMM], 0xAA, a=0x55, p="M", ep="MZ") + + modes = [A_DIR, A_ABS, A_DIR_X, A_ABS_X] + test_ins_with_modes("bit", modes, 0x5234, a=0x9377, p="CZIDVN", ep="CIDV") + test_ins_with_modes("bit", modes, 0xAAAA, a=0x5555, p="", ep="NZ") + test_ins_with_modes("bit", modes, 0x52, a=0x93, p="M", ep="MV") + test_ins_with_modes("bit", modes, 0xAA, a=0x55, p="M", ep="MZN") + + +def branch_tests(): + def test_branch_taken(ins, opcode, p): + # branch forward: 7effc0 = B?? +127. 7e0041 = jml @ok. 7effc2 = STP + before = jml_to_ok_instructions(0x7E0041) + after = f""" + jsr bank{bank_num}_save_results + bra @to_fail + @ok:""" + test( + "jml $7EFFC0", + ins_name=f"{ins} +127", + before_regs=before, + after_ins=after, + mem_7effc0=opcode, + mem_7effc1=127, + mem_7effc2=OPCODE_STP, + mem_7f0041=OPCODE_STP, + p=p, + ) + + # branch backwards: 7f0040 = B?? -128. 7fffc2 = jml @ok. 7f0042 = STP + before = jml_to_ok_instructions(0x7FFFC2) + after = "@ok:" + test( + "jml $7F0040", + ins_name=f"{ins} -128", + before_regs=before, + after_ins=after, + mem_7f0040=opcode, + mem_7f0041=0x80, + mem_7f0042=OPCODE_STP, + mem_7effc2=OPCODE_STP, + p=p, + ) + + def test_branch_not_taken(ins, p): + after = f"""\ + bra @ok + @not_ok: + jsr bank{bank_num}_save_results + bra @to_fail + @ok: + """ + test(f"{ins} @not_ok", after_ins=after, p=p) + + test_branch_taken("bra", 0x80, p="") + + test_branch_taken("bcc", 0x90, p="") + test_branch_not_taken("bcc", p="C") + test_branch_taken("bcs", 0xB0, p="CZIDXMVNE") + test_branch_not_taken("bcs", p="") + + test_branch_taken("bne", 0xD0, p="") + test_branch_not_taken("bne", p="Z") + test_branch_taken("beq", 0xF0, p="Z") + test_branch_not_taken("beq", p="") + + test_branch_taken("bpl", 0x10, p="") + test_branch_not_taken("bpl", p="N") + test_branch_taken("bmi", 0x30, p="N") + test_branch_not_taken("bmi", p="") + + test_branch_taken("bvc", 0x50, p="") + test_branch_not_taken("bvc", p="V") + test_branch_taken("bvs", 0x70, p="V") + test_branch_not_taken("bvs", p="") + + +def brk_cop_tests(): + after = "@ok:" + + # Addresses 1000,1004,1008,100C are the BRK/COP handler addresses + for ins_name, opcode, native_addr, emul_addr in [ + ("brk", 0x00, 0x1000, 0x1008), + ("cop #$DB", 0x02, 0x1004, 0x100C), + ]: + before = jml_to_ok_instructions(native_addr) + after_checks = f"""\ + lda #${OPCODE_STP:02x} + sta ${native_addr:02x}""" # stop on further calls + test( + "jml $7e8000", + ins_name=ins_name, + mem_7e8000=opcode, + mem_7e8001=OPCODE_STP, + p="DCZ", + ep="ICZ", + es=0x1EB, + emem_1ef=0x7E, + ememw_1ed=0x8002, + emem_1ec=flags("DCZ"), + before_regs=before, + after_ins=after, + after_checks=after_checks, + ) + + before = jml_to_ok_instructions(emul_addr) + after_checks = f"""\ + lda #${OPCODE_STP:02x} + sta ${emul_addr:02x}""" # stop on further calls + # E=1: Don't push pbr, stack writes wrap in page 1 + test( + "jml $7e8000", + ins_name=ins_name, + mem_7e8000=opcode, + mem_7e8001=OPCODE_STP, + p="DCZE", + ep="ICZMXE", + s=0x100, + es=0x1FD, + emem_1ff=0x02, + emem_100=0x80, + emem_1fe=flags("DCZMX"), + before_regs=before, + after_ins=after, + after_checks=after_checks, + ) + + +def brl_tests(): + OPCODE_BRL = 0x82 + + # branch forward: 7ef000 = BRL +$7FFF. 7e7002 = jml @ok. 7e7002 = STP + before = jml_to_ok_instructions(0x7E7002) + after = "@ok:" + test( + "jml $7EF000", + ins_name="BRL +$7FFF", + before_regs=before, + after_ins=after, + mem_7ef000=OPCODE_BRL, + memw_7ef001=0x7FFF, + mem_7ef003=OPCODE_STP, + mem_7f7002=OPCODE_STP, + p="", + ) + + +def clear_set_tests(): + test("clc", p="CZIDXMVN", ep="ZIDXMVN") + test("clc", p="", ep="") + test("cld", p="CZIDXMVN", ep="CZIXMVN") + test("cld", p="", ep="") + test("cli", p="CZIDXMVN", ep="CZDXMVN") + test("cli", p="", ep="") + test("clv", p="CZIDXMVN", ep="CZIDXMN") + test("clv", p="", ep="") + test("sec", p="", ep="C") + test("sec", p=0xFF, ep=0xFF) + test("sed", p="", ep="D") + test("sed", p=0xFF, ep=0xFF) + test("sei", p="", ep="I") + test("sei", p=0xFF, ep=0xFF) + + +def cmp_tests(): + modes_a = [ + A_IMM, + A_DIR_X_IND, + A_STACK_S, + A_DIR, + A_IND_LONG_DIR, + A_ABS, + A_LONG, + A_IND_DIR_Y, + A_IND_DIR, + A_IND_STACK_S_Y, + A_DIR_X, + A_IND_LONG_DIR_Y, + A_ABS_Y, + A_ABS_X, + A_LONG_X, + ] + modes_xy = [A_IMM, A_DIR, A_ABS] + + def do_test16(val1, val2, p, ep): + test_ins_with_modes("cmp", modes_a, a=val1, val=val2, p=p, ep=ep) + test_ins_with_modes("cpx", modes_xy, x=val1, val=val2, p=p, ep=ep) + test_ins_with_modes("cpy", modes_xy, y=val1, val=val2, p=p, ep=ep) + + def do_test8(val1, val2, p, ep): + test_ins_with_modes("cmp", modes_a, a=val1, val=val2, p=p + "M", ep=ep + "M") + test_ins_with_modes( + "cpx", modes_xy, x=val1, val=val2, ex=val1 & 0xFF, p=p + "X", ep=ep + "X" + ) + test_ins_with_modes( + "cpy", modes_xy, y=val1, val=val2, ey=val1 & 0xFF, p=p + "X", ep=ep + "X" + ) + + do_test16(0xABCD, 0xABCD, p="", ep="ZC") + do_test16(0xABCC, 0xABCD, p="CZIDVN", ep="IDVN") + + do_test8(0xABCD, 0xCD, p="", ep="ZC") + do_test8(0xABCC, 0xCD, p="CZIDVN", ep="IDVN") + + +def dec_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + + def do_test(val, result, p, ep, bits=16): + is8 = bits == 8 + test_ins_with_modes( + "dec", modes, val, result, p=p + is8 * "M", ep=ep + is8 * "M" + ) + test("dex", x=val, ex=result, p=p + is8 * "X", ep=ep + is8 * "X") + test("dey", y=val, ey=result, p=p + is8 * "X", ep=ep + is8 * "X") + + do_test(0x0001, 0x0000, p="", ep="Z") + do_test(0x0000, 0xFFFF, p="CZIDVN", ep="CIDVN") + + do_test(0x01, 0x00, p="", ep="Z", bits=8) + do_test(0x00, 0xFF, p="CZIDVN", ep="CIDVN", bits=8) + + +def eor_tests(): + test_ins_with_modes( + "eor", READ_MODES, a=0xFEFF, val=0x6F8C, p="", ea=0x9173, ep="N" + ) + test_ins_with_modes("eor", [A_IMM], a=0xAAAA, val=0xAAAA, p="", ea=0x0000, ep="Z") + test_ins_with_modes( + "eor", [A_IMM], a=0x1234, val=0x4334, p="CZIDVN", ea=0x5100, ep="CIDV" + ) + + test_ins_with_modes( + "eor", READ_MODES, a=0x12FE, val=0x6F, p="M", ea=0x1291, ep="MN" + ) + test_ins_with_modes("eor", [A_IMM], a=0xAAAA, val=0xAA, p="M", ea=0xAA00, ep="MZ") + + +def inc_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + + def do_test(val, result, p, ep, bits=16): + is8 = bits == 8 + test_ins_with_modes( + "inc", modes, val, result, p=p + is8 * "M", ep=ep + is8 * "M" + ) + test("inx", x=val, ex=result, p=p + is8 * "X", ep=ep + is8 * "X") + test("iny", y=val, ey=result, p=p + is8 * "X", ep=ep + is8 * "X") + + do_test(0xFFFF, 0x0000, p="", ep="Z") + do_test(0x7FFF, 0x8000, p="CZIDVN", ep="CIDVN") + + do_test(0xFF, 0x00, p="", ep="Z", bits=8) + do_test(0x7F, 0x80, p="CZIDVN", ep="CIDVN", bits=8) + + +def jmp_tests(): + # All modes jump to $7e8000, which contains a jml to @ok. + before = jml_to_ok_instructions(0x7E8000) + after = f""" + jsr bank{bank_num}_save_results + bra @to_fail + @ok:""" + + # jmp abs (opcode=0x4C): jump from 7e7000. + test( + "jml $7e7000", + ins_name="jmp $8000", + mem_7e7000=0x4C, + memw_7e7001=0x8000, + mem_7e7003=OPCODE_STP, + before_regs=before, + after_ins=after, + ) + + # jmp long (a.k.a. jml) + test("jml $7e8000", before_regs=before, after_ins=after, p="CZIDXMVNE") + + # jmp (abs) - opcode=0x6C. Reads from bank 0. Target stored at test_target (00:FFA2) + test( + "jml $7e7000", + ins_name="jmp ($FFA2)", + dbr=0x7F, + mem_7e7000=0x6C, + memw_7e7001=0xFFA2, + mem_7e7003=OPCODE_STP, + before_regs=before, + after_ins=after, + ) + + # jmp [abs] - opcode=0xDC. Reads from bank 0. Target stored at test_target24 (00:FFA4) + test("jml [$FFA4]", dbr=0x7F, before_regs=before, after_ins=after) + + # jmp (abs,x) - opcode=0x7C. Reads from PBR bank. jump from 7e7000, target stored at 7e5000. Wrap in bank. + test( + "jml $7e7000", + ins_name="jmp ($F000,x)", + mem_7e7000=0x7C, + memw_7e7001=0xF000, + x=0x6000, + mem_7e7003=OPCODE_STP, + memw_7e5000=0x8000, + dbr=0x7F, + before_regs=before, + after_ins=after, + ) + # with 8 bit index. Target at 7e0080 + test( + "jml $7e7000", + ins_name="jmp ($FFFF,x)", + mem_7e7000=0x7C, + memw_7e7001=0xFFFF, + x=0x81, + mem_7e7003=OPCODE_STP, + memw_7e0080=0x8000, + dbr=0x7F, + before_regs=before, + after_ins=after, + p="X", + ) + # with E=1 + test( + "jml $7e7000", + ins_name="jmp ($FFFF,x)", + mem_7e7000=0x7C, + memw_7e7001=0xFFFF, + x=0x81, + mem_7e7003=OPCODE_STP, + memw_7e0080=0x8000, + dbr=0x7F, + before_regs=before, + after_ins=after, + p="E", + ep="MXE", + ) + + +def jsr_tests(): + # All modes jump to $7e8000, which contains a jml to @ok. + before = jml_to_ok_instructions(0x7E8000) + after = "@ok:" + + # jsr abs (opcode=0x20). + test( + "jml $7e7000", + ins_name="jsr $8000", + mem_7e7000=0x20, + memw_7e7001=0x8000, + mem_7e7003=OPCODE_STP, + ememw_01ee=0x7002, + es=0x1ED, + before_regs=before, + after_ins=after, + ) + # With E=1, the stack pushes wrap within page 1 + test( + "jml $7e7000", + ins_name="jsr $8000", + mem_7e7000=0x20, + memw_7e7001=0x8000, + mem_7e7003=OPCODE_STP, + s=0x100, + p="CZIDXMVNE", + emem_01ff=0x02, + emem_0100=0x70, + es=0x1FE, + before_regs=before, + after_ins=after, + ) + + # jsl long (opcode=0x22), a.k.a. jsr + test( + "jml $7f7000", + ins_name="jsl $FE8000", + mem_7f7000=0x22, + memw_7f7001=0x8000, + mem_7f7003=0x7E, + mem_7f7004=OPCODE_STP, + ememw_01ed=0x7003, + emem_01ef=0x7F, + es=0x1EC, + before_regs=before, + after_ins=after, + ) + # With E=1, the stack pushes can write outside page 1 + test( + "jml $7f7000", + ins_name="jsl $FE8000", + mem_7f7000=0x22, + memw_7f7001=0x8000, + mem_7f7003=0x7E, + mem_7f7004=OPCODE_STP, + s=0x100, + p="CZIDXMVNE", + ememw_00fe=0x7003, + emem_0100=0x7F, + es=0x1FD, + before_regs=before, + after_ins=after, + ) + + # jsr (abs,x) (opcode=0xFC). Reads from PBR bank. Target addr at $7E5000. + test( + "jml $7e7000", + ins_name="jsr ($F000,x)", + mem_7e7000=0xFC, + memw_7e7001=0xF000, + mem_7e7003=OPCODE_STP, + x=0x6000, + memw_7e5000=0x8000, + ememw_01ee=0x7002, + es=0x1ED, + dbr=0x7F, + before_regs=before, + after_ins=after, + ) + # 8-bt index. Target at 7e0080 + test( + "jml $7e7000", + ins_name="jsr ($FFFF,x)", + mem_7e7000=0xFC, + memw_7e7001=0xFFFF, + mem_7e7003=OPCODE_STP, + x=0x81, + memw_7e0080=0x8000, + p="X", + ememw_01ee=0x7002, + es=0x1ED, + dbr=0x7F, + before_regs=before, + after_ins=after, + ) + # With E=1, the stack pushes can write outside page 1 + test( + "jml $7e7000", + ins_name="jsr ($FFFF,x)", + mem_7e7000=0xFC, + memw_7e7001=0xFFFF, + mem_7e7003=OPCODE_STP, + x=0x81, + memw_7e0080=0x8000, + p="MXE", + s=0x100, + ememw_00ff=0x7002, + es=0x1FE, + dbr=0x7F, + before_regs=before, + after_ins=after, + ) + + +def ld_tests(): + modes_a = [ + A_IMM, + A_DIR_X_IND, + A_STACK_S, + A_DIR, + A_IND_LONG_DIR, + A_ABS, + A_LONG, + A_IND_DIR_Y, + A_IND_DIR, + A_IND_STACK_S_Y, + A_DIR_X, + A_IND_LONG_DIR_Y, + A_ABS_Y, + A_ABS_X, + A_LONG_X, + ] + modes_x = [A_IMM, A_DIR, A_ABS, A_DIR_Y, A_ABS_Y] + modes_y = [A_IMM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + + def do_test(val, p, ep, bits=16): + is8 = bits == 8 + test_ins_with_modes( + "lda", + modes_a, + val, + a=0x1234, + ea=val + is8 * 0x1200, + p=p + is8 * "M", + ep=ep + is8 * "M", + ) + test_ins_with_modes( + "ldx", modes_x, val, x=0x1234, ex=val, p=p + is8 * "X", ep=ep + is8 * "X" + ) + test_ins_with_modes( + "ldy", modes_y, val, y=0x1234, ey=val, p=p + is8 * "X", ep=ep + is8 * "X" + ) + + do_test(0x8000, p="Z", ep="N") + do_test(0x0000, p="CZIDVN", ep="CZIDV") + do_test(0x80, p="Z", ep="N", bits=8) + do_test(0x00, p="CZIDVN", ep="CZIDV", bits=8) + + +def lsr_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + test_ins_with_modes("lsr", modes, 0x0001, 0x0000, p="", ep="ZC") + test_ins_with_modes("lsr", modes, 0x4222, 0x2111, p="CZIDVN", ep="IDV") + + test_ins_with_modes("lsr", modes, 0x01, 0x00, p="M", ep="MZC") + test_ins_with_modes("lsr", modes, 0x42, 0x21, p="CZIDMVN", ep="IDMV") + + +def mvn_tests(): + # move between banks. Wrap in each bank. + test( + "mvn #$7e, #$7f", + x=0xFFFF, + y=0xFFFE, + a=3, + edbr=0x7F, + ea=0xFFFF, + ex=0x0003, + ey=0x0002, + mem_7effff=0x21, + mem_7e0000=0x22, + mem_7e0001=0x23, + mem_7e0002=0x24, + mem_7f0001=0x00, + mem_7f0002=0x99, + emem_7ffffe=0x21, + emem_7fffff=0x22, + emem_7f0000=0x23, + emem_7f0001=0x24, + emem_7f0002=0x99, + ) + + # 16-bit accum even in 8-bit mode. Also test overlapping move backward. + test( + "mvn #$7f, #$7f", + x=5, + y=0, + a=0x1FF, + edbr=0x7F, + ea=0xFFFF, + ex=0x0205, + ey=0x0200, + mem_7f0005=0x31, + mem_7f0204=0x32, + mem_7f0200=0x99, + emem_7f0000=0x31, + emem_7f01ff=0x32, + emem_7f0200=0x99, + p="CZIDMVN", + ) + + # Overlapping move forward - will create a repeating pattern + test( + "mvn #$7f, #$7f", + x=0, + y=2, + a=0x1FF, + edbr=0x7F, + ea=0xFFFF, + ex=0x200, + ey=0x202, + mem_7f0000=0x41, + mem_7f0001=0x42, + emem_7f0200=0x41, + emem_7f0201=0x42, + ) + + # 8 bit indexes: Wrap in page 0 + test( + "mvn #$7e, #$7f", + x=0x05FF, + y=0x05FE, + a=3, + edbr=0x7F, + ea=0xFFFF, + ex=0x0003, + ey=0x0002, + p="X", + mem_7e00ff=0x51, + mem_7e0000=0x52, + mem_7e0001=0x53, + mem_7e0002=0x54, + mem_7f0001=0x00, + mem_7f0002=0x99, + emem_7f00fe=0x51, + emem_7f00ff=0x52, + emem_7f0000=0x53, + emem_7f0001=0x54, + emem_7f0002=0x99, + ) + + +def mvp_tests(): + # move between banks. Wrap in each bank. + test( + "mvp #$7e, #$7f", + x=0x0002, + y=0x0001, + a=3, + edbr=0x7F, + ea=0xFFFF, + ex=0xFFFE, + ey=0xFFFD, + mem_7effff=0x21, + mem_7e0000=0x22, + mem_7e0001=0x23, + mem_7e0002=0x24, + mem_7f0001=0x00, + mem_7ffffd=0x99, + emem_7ffffe=0x21, + emem_7fffff=0x22, + emem_7f0000=0x23, + emem_7f0001=0x24, + emem_7ffffd=0x99, + ) + + # 16-bit accum even in 8-bit mode. Also test overlapping move forward. + test( + "mvp #$7f, #$7f", + x=0x1FF, + y=0x204, + a=0x1FF, + edbr=0x7F, + ea=0xFFFF, + ex=0xFFFF, + ey=0x0004, + mem_7f0000=0x31, + mem_7f01ff=0x32, + mem_7f0004=0x99, + emem_7f0005=0x31, + emem_7f0204=0x32, + emem_7f0004=0x99, + p="CZIDMVN", + ) + + # Overlapping move backward - will create a repeating pattern + test( + "mvp #$7f, #$7f", + x=0x201, + y=0x1FF, + a=0x1FF, + edbr=0x7F, + ea=0xFFFF, + ex=0x0001, + ey=0xFFFF, + mem_7f0200=0x41, + mem_7f0201=0x42, + emem_7f0000=0x41, + emem_7f0001=0x42, + ) + + # 8 bit indexes: Wrap in page 0 + test( + "mvp #$7e, #$7f", + x=0x0502, + y=0x0501, + a=3, + edbr=0x7F, + ea=0xFFFF, + ex=0x00FE, + ey=0x00FD, + p="X", + mem_7e00ff=0x51, + mem_7e0000=0x52, + mem_7e0001=0x53, + mem_7e0002=0x54, + mem_7f0001=0x00, + mem_7f0002=0x99, + emem_7f00fe=0x51, + emem_7f00ff=0x52, + emem_7f0000=0x53, + emem_7f0001=0x54, + emem_7f0002=0x99, + ) + + +def nop_wdm_tests(): + for ins in ("nop", "wdm $AB"): + test(ins, p="") + test(ins, p="CZIDXMVNE") + + +def ora_tests(): + test_ins_with_modes( + "ora", READ_MODES, a=0x2318, val=0xB939, p="", ea=0xBB39, ep="N" + ) + test_ins_with_modes("ora", [A_IMM], a=0x0000, val=0x0000, p="", ea=0x0000, ep="Z") + test_ins_with_modes( + "ora", [A_IMM], a=0x1200, val=0x4300, p="CZIDVN", ea=0x5300, ep="CIDV" + ) + + test_ins_with_modes( + "ora", READ_MODES, a=0x1298, val=0x39, p="M", ea=0x12B9, ep="MN" + ) + test_ins_with_modes("ora", [A_IMM], a=0xAA00, val=0x00, p="M", ea=0xAA00, ep="MZ") + + +def pea_tests(): + test("pea $ABCD", ememw_01ee=0xABCD, es=0x1ED) + # E=1: Can push outside page 1 + test("pea $9876", s=0x100, ememw_00ff=0x9876, es=0x1FE, p="CZIDXMVNE") + + +def pei_tests(): + # set DBR to 7F to make sure the actual read is done from bank 0 and not DBR. + test("pei ($34)", memw_33=0x8765, d=0xFFFF, dbr=0x7F, ememw_01ee=0x8765, es=0x1ED) + # E=1: Can leave stack page 1 and direct page + test( + "pei ($ff)", + memw_2ff=0x7654, + d=0x0200, + dbr=0x7F, + s=0x100, + ememw_00ff=0x7654, + es=0x1FE, + p="CZIDXMVNE", + ) + + +def per_tests(): + before = jml_to_ok_instructions(0x7E7003) + after = "@ok:" + OPCODE_PER = 0x62 + + test( + "jml $7e7000", + ins_name="per -$8000", + mem_7e7000=OPCODE_PER, + memw_7e7001=0x8000, + ememw_01ee=0xF003, + es=0x1ED, + before_regs=before, + after_ins=after, + ) + test( + "jml $7e7000", + ins_name="per +$7FFF", + mem_7e7000=OPCODE_PER, + memw_7e7001=0x7FFF, + ememw_01ee=0xF002, + es=0x1ED, + before_regs=before, + after_ins=after, + ) + # E=1: Can push outside page 1 + test( + "jml $7e7000", + ins_name="per -$8000", + mem_7e7000=OPCODE_PER, + memw_7e7001=0x8000, + p="CZIDXMVNE", + s=0x100, + ememw_00ff=0xF003, + es=0x1FE, + before_regs=before, + after_ins=after, + ) + + +def push_tests(): + test("pha", a=0x9876, es=0x1ED, ememw_1ee=0x9876) + test("pha", a=0x8765, es=0x1EE, emem_1ef=0x65, p="CZIDVNM") + test("pha", a=0x5678, s=0x100, es=0x1FF, emem_100=0x78, p="MXE") + + test("phx", x=0x9876, es=0x1ED, ememw_1ee=0x9876) + test("phx", x=0x23, es=0x1EE, emem_1ef=0x23, p="CZIDVNX") + test("phx", x=0x34, s=0x100, es=0x1FF, emem_100=0x34, p="MXE") + + test("phy", y=0x1324, es=0x1ED, ememw_1ee=0x1324) + test("phy", y=0x35, es=0x1EE, emem_1ef=0x35, p="CZIDVNX") + test("phy", y=0x46, s=0x100, es=0x1FF, emem_100=0x46, p="MXE") + + test("phb", dbr=0x7F, es=0x1EE, emem_1ef=0x7F) + test("phb", dbr=0x7F, s=0x100, es=0x1FF, emem_100=0x7F, p="CZIDVNMXE") + + test("phd", d=0x6543, es=0x1ED, ememw_1ee=0x6543) + # PHD with E=1 can leave the stack page + test("phd", d=0x1357, s=0x100, es=0x1FE, ememw_0ff=0x1357, p="CZIDVNMXE") + + OPCODE_PHK = 0x4B + test( + "jml $7e8000", + ins_name="phk", + mem_7e8000=OPCODE_PHK, + es=0x1EE, + emem_1ef=0x7E, + before_regs=jml_to_ok_instructions(0x7E8001), + after_ins="@ok:", + ) + test( + "jml $7e8000", + ins_name="phk", + mem_7e8000=OPCODE_PHK, + s=0x100, + es=0x1FF, + emem_100=0x7E, + p="CZIDVNMXE", + before_regs=jml_to_ok_instructions(0x7E8001), + after_ins="@ok:", + ) + + test("php", p="DZ", es=0x1EE, emem_1ef=flags("DZ")) + test("php", p="CZIDVNMXE", s=0x100, es=0x1FF, emem_100=flags("CZIDVNMX")) + + +def pull_axy_tests(): + def do_test(val, bits=16, p="", ep="", **kwargs): + is8 = bits == 8 + test( + "pla", + a=0x1234, + ea=val + 0x1200 * is8, + p=p + "M" * is8, + ep=ep + "M" * is8, + **kwargs, + ) + test("plx", ex=val, p=p + "X" * is8, ep=ep + "X" * is8, **kwargs) + test("ply", ey=val, p=p + "X" * is8, ep=ep + "X" * is8, **kwargs) + + do_test(0xFEDC, memw_1f0=0xFEDC, es=0x1F1, ep="N") + do_test(0x0000, memw_1f0=0x0000, es=0x1F1, p="", ep="Z") + do_test(0xEF, memw_1f0=0xEF, es=0x1F0, p="CZIDVN", ep="CIDVN", bits=8) + do_test(0x00, memw_1f0=0x00, es=0x1F0, p="", ep="Z", bits=8) + + # E=1: wrap in page 1 + do_test(0xCE, mem_100=0xCE, s=0x1FF, es=0x100, p="MXE", ep="MXEN", bits=8) + + +def pull_misc_tests(): + test("plb", mem_1f0=0xFE, es=0x1F0, edbr=0xFE, ep="N") + test("plb", mem_1f0=0x00, es=0x1F0, edbr=0x00, p="CIDVNMX", ep="CZIDVMX") + # E=1: No wrapping in page 1 + test( + "plb", + mem_200=0x3D, + s=0x1FF, + es=0x100, + edbr=0x3D, + p="MXE", + ep="MXE", + comment=UNDOCUMENTED_COMMENT, + ) + + test("pld", memw_1f0=0x9753, es=0x1F1, ed=0x9753, ep="N") + test( + "pld", memw_1f0=0x0000, es=0x1F1, d=0x9999, ed=0x0000, p="CIDVNMX", ep="CZIDVMX" + ) + # E=1: No wrapping in page 1 + test("pld", memw_200=0x1356, s=0x1FF, es=0x101, ed=0x1356, p="MXE", ep="MXE") + + test("plp", mem_1f0=0, es=0x1F0, p="CZIDVNMX", ep="") + test("plp", mem_1f0=flags("MZC"), es=0x1F0, p="", ep="MZC") + # setting x=1 clears high bytes of X,Y + test( + "plp", + mem_1f0=flags("X"), + es=0x1F0, + x=0x2345, + y=0x3456, + ex=0x45, + ey=0x56, + p="", + ep="X", + ) + # E=1: Wrap in page 1, force X and M to 1 + test("plp", mem_100=flags("CV"), s=0x1FF, es=0x100, p="MXE", ep="CVMXE") + + +def rep_set_tests(): + # Setting X=1 should clear high byte of x,y + test( + "sep #$FF", + a=0x1234, + x=0x3456, + y=0x5678, + ea=0x1234, + ex=0x56, + ey=0x78, + p=0, + ep=0xFF, + ) + test("sep #$0F", p=0x11, ep=0x1F) + test("rep #$F0", p=0xFF, ep=0x0F) + test("rep #$0F", p=0xFF, ep=0xF0) + test("rep #$38", p="MXDZE", ep="MXZE", advanced=False) # Can't clear M,X when E=1 + + +def rol_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + test_ins_with_modes("rol", modes, 0x8000, 0x0000, p="", ep="ZC") + test_ins_with_modes("rol", modes, 0x4111, 0x8223, p="CZIDVN", ep="IDVN") + + test_ins_with_modes("rol", modes, 0x80, 0x00, p="M", ep="MZC") + test_ins_with_modes("rol", modes, 0x41, 0x83, p="CZIDMVN", ep="IDMVN") + + +def ror_tests(): + modes = [A_ACCUM, A_DIR, A_ABS, A_DIR_X, A_ABS_X] + test_ins_with_modes("ror", modes, 0x0001, 0x0000, p="", ep="ZC") + test_ins_with_modes("ror", modes, 0x4222, 0xA111, p="CZIDVN", ep="IDVN") + + test_ins_with_modes("ror", modes, 0x01, 0x00, p="M", ep="MZC") + test_ins_with_modes("ror", modes, 0x42, 0xA1, p="CZIDMVN", ep="IDMVN") + + +def rts_rtl_rti_tests(): + before = jml_to_ok_instructions(0x7E0000) + after = "@ok:" + + # RTS. Return from 7e8000 to 7e0000. The stored PC is ffff. + OPCODE_RTS = 0x60 + test( + "jml $7e8000", + ins_name="rts", + mem_7e8000=OPCODE_RTS, + memw_1f0=0xFFFF, + es=0x1F1, + before_regs=before, + after_ins=after, + ) + # E=1: Wraps in stack page 1 + test( + "jml $7e8000", + ins_name="rts", + mem_7e8000=OPCODE_RTS, + memw_100=0xFFFF, + s=0x1FF, + es=0x101, + p="CZIDXMVNE", + before_regs=before, + after_ins=after, + ) + + # RTL. Return to 7e0000. The stored PC is 7e:ffff. + test( + "rtl", + memw_1f0=0xFFFF, + mem_1f2=0x7E, + es=0x1F2, + before_regs=before, + after_ins=after, + ) + # E=1: No stack page 1 wrapping + # In case of incorrect wrapping, add a "bad" target + after_rtl = f"""\ + @not_ok: + jsr bank{bank_num}_save_results + bra @to_fail + @ok:""" + before_rtl = before + "\n" + jml_to_label_instructions(0x7F1000, "@not_ok") + test( + "rtl", + memw_200=0xFFFF, + mem_202=0x7E, + memw_100=0x0FFF, + mem_102=0x7F, + p="CZIDXMVNE", + s=0x1FF, + es=0x102, + before_regs=before_rtl, + after_ins=after_rtl, + ) + + # RTI. Return to 7e0000. The stored PC is 7e:0000. + test( + "rti", + mem_1f0=flags("DN"), + memw_1f1=0x0000, + mem_1f3=0x7E, + es=0x1F3, + p="CZ", + ep="DN", + before_regs=before, + after_ins=after, + ) + # E=1: Wraps in stack page 1, doesn't pull pbr + OPCODE_RTI = 0x40 + test( + "jml $7e8000", + ins_name="rts", + mem_7e8000=OPCODE_RTI, + mem_100=flags("DN"), + memw_101=0x0000, + s=0x1FF, + es=0x102, + p="CZE", + ep="DNXME", + before_regs=before, + after_ins=after, + ) + + +def sbc_binary_tests(): + test_ins_with_modes("sbc", READ_MODES, a=0x9090, val=0x908F, ea=0, p="", ep="CZ") + test_ins_with_modes("sbc", [A_IMM], a=0x9090, val=0x2000, ea=0x7090, p="C", ep="CV") + test_ins_with_modes( + "sbc", [A_IMM], a=0x1234, val=0x1235, ea=0xFFFF, p="CZIV", ep="IN" + ) + test_ins_with_modes("sbc", [A_IMM], a=0x7000, val=0xA000, ea=0xCFFF, p="", ep="NV") + + test_ins_with_modes( + "sbc", READ_MODES, a=0xCC90, val=0x8F, ea=0xCC00, p="M", ep="MCZ" + ) + test_ins_with_modes("sbc", [A_IMM], a=0xCC90, val=0x20, ea=0xCC70, p="MC", ep="MCV") + test_ins_with_modes( + "sbc", [A_IMM], a=0xCC12, val=0x13, ea=0xCCFF, p="MCZIV", ep="MIN" + ) + test_ins_with_modes("sbc", [A_IMM], a=0xCC70, val=0xA0, ea=0xCCCF, p="M", ep="MNV") + + +def sbc_decimal_tests(): + # The V flag is the same result as for binary subtraction + test_ins_with_modes("sbc", READ_MODES, a=0x9090, val=0x9089, ea=0, p="D", ep="DCZ") + test_ins_with_modes( + "sbc", [A_IMM], a=0x0000, val=0x0001, ea=0x9999, p="DC", ep="DN" + ) + test_ins_with_modes( + "sbc", [A_IMM], a=0x1000, val=0x9000, ea=0x2000, p="DC", ep="DV" + ) + test_ins_with_modes("sbc", [A_IMM], a=0x1000, val=0x9001, ea=0x1999, p="DC", ep="D") + test_ins_with_modes( + "sbc", [A_IMM], a=0xAB1D, val=0xF1E2, ea=0x59DB, p="DC", ep="D", advanced=True + ) + + test_ins_with_modes( + "sbc", READ_MODES, a=0xCC90, val=0x89, ea=0xCC00, p="DM", ep="DMCZ" + ) + test_ins_with_modes( + "sbc", [A_IMM], a=0xCC00, val=0x01, ea=0xCC99, p="DMC", ep="DMN" + ) + test_ins_with_modes( + "sbc", [A_IMM], a=0xCC10, val=0x90, ea=0xCC20, p="DMC", ep="DMV" + ) + test_ins_with_modes("sbc", [A_IMM], a=0xCC10, val=0x91, ea=0xCC19, p="DMC", ep="DM") + test_ins_with_modes( + "sbc", [A_IMM], a=0xCCAB, val=0xF1, ea=0xCC5A, p="DMC", ep="DM", advanced=True + ) + + +def st_tests(): + modes_a = [ + A_DIR_X_IND, + A_STACK_S, + A_DIR, + A_IND_LONG_DIR, + A_ABS, + A_LONG, + A_IND_DIR_Y, + A_IND_DIR, + A_IND_STACK_S_Y, + A_DIR_X, + A_IND_LONG_DIR_Y, + A_ABS_Y, + A_ABS_X, + A_LONG_X, + ] + modes_x = [A_DIR, A_ABS, A_DIR_Y] + modes_y = [A_DIR, A_ABS, A_DIR_X] + + def do_test(val, p, bits=16): + is8 = bits == 8 + orig_val = 0x12 if is8 else 0x1234 + test_ins_with_modes( + "sta", modes_a, orig_val, result=val, a=val + is8 * 0x5500, p=p + is8 * "M" + ) + test_ins_with_modes( + "stx", modes_x, orig_val, result=val, x=val, ex=val, p=p + is8 * "X" + ) + test_ins_with_modes( + "sty", modes_y, orig_val, result=val, y=val, ey=val, p=p + is8 * "X" + ) + + do_test(0x8000, p="") + do_test(0x8000, p="CZIDVN") + do_test(0x00, p="", bits=8) + do_test(0x00, p="CZIDVN", bits=8) + + modes_z = [A_DIR, A_DIR_X, A_ABS, A_ABS_X] + test_ins_with_modes("stz", modes_z, 0x1234, result=0, p="") + test_ins_with_modes("stz", modes_z, 0x1234, result=0, p="CZIDVN") + test_ins_with_modes("stz", modes_z, 0x12, result=0, p="M") + + +def trb_tests(): + modes = [A_DIR, A_ABS] + test_ins_with_modes( + "trb", modes, 0x9234, a=0x1630, result=0x8004, p="CZIDVN", ep="CIDVN" + ) + test_ins_with_modes("trb", modes, 0xAAAA, a=0x5555, result=0xAAAA, p="", ep="Z") + + test_ins_with_modes( + "trb", modes, 0x92, a=0x16, result=0x80, p="CZIDMVN", ep="CIDMVN" + ) + test_ins_with_modes("trb", modes, 0xAA, a=0x55, result=0xAA, p="M", ep="MZ") + + +def tsb_tests(): + modes = [A_DIR, A_ABS] + test_ins_with_modes( + "tsb", modes, 0x9234, a=0x1630, result=0x9634, p="CZIDVN", ep="CIDVN" + ) + test_ins_with_modes("tsb", modes, 0xAAAA, a=0x5555, result=0xFFFF, p="", ep="Z") + + test_ins_with_modes( + "tsb", modes, 0x92, a=0x16, result=0x96, p="CZIDMVN", ep="CIDMVN" + ) + test_ins_with_modes("tsb", modes, 0xAA, a=0x55, result=0xFF, p="M", ep="MZ") + + +def transfer_axy_tests(): + test("tax", a=0x8765, x=0x5678, ex=0x8765, p="", ep="N") + test("tax", a=0x0000, x=0x5678, ex=0x0000, p="", ep="Z") + test( + "tax", a=0x1234, x=0x5678, ex=0x1234, p="CZIDMVN", ep="CIDMV" + ) # 8 bit A - transfers 16 bits + test("tax", a=0x87AB, x=0x5678, ex=0xAB, p="X", ep="XN") + + test("tay", a=0x8765, y=0x5678, ey=0x8765, p="", ep="N") + test("tay", a=0x0000, y=0x5678, ey=0x0000, p="", ep="Z") + test( + "tay", a=0x1234, y=0x5678, ey=0x1234, p="CZIDMVN", ep="CIDMV" + ) # 8 bit A - transfers 16 bits + test("tay", a=0x87AB, y=0x5678, ey=0xAB, p="X", ep="XN") + + test("txa", x=0x9876, a=0x1234, ea=0x9876, p="", ep="N") + test("txa", x=0x0000, a=0x1234, ea=0x0000, p="", ep="Z") + test( + "txa", x=0x00CD, a=0x1234, ea=0xCD, p="CZIDXVN", ep="CIDXV" + ) # 8 bit X - transfers 16 bits + test( + "txa", x=0xABCD, a=0x1234, ea=0x12CD, p="M", ep="MN" + ) # 8 bit A - transfers 8 bits + test( + "txa", x=0xAB00, a=0x1234, ea=0x1200, p="M", ep="MZ" + ) # 8 bit A - transfers 8 bits + + test("tya", y=0x9876, a=0x1234, ea=0x9876, p="", ep="N") + test("tya", y=0x0000, a=0x1234, ea=0x0000, p="", ep="Z") + test( + "tya", y=0x00CD, a=0x1234, ea=0xCD, p="CZIDXVN", ep="CIDXV" + ) # 8 bit Y - transfers 16 bits + test( + "tya", y=0xABCD, a=0x1234, ea=0x12CD, p="M", ep="MN" + ) # 8 bit A - transfers 8 bits + test( + "tya", y=0xAB00, a=0x1234, ea=0x1200, p="M", ep="MZ" + ) # 8 bit A - transfers 8 bits + + test("txy", x=0x8765, y=0x5678, ey=0x8765, p="", ep="N") + test("txy", x=0x0000, y=0x5678, ey=0x0000, p="CIDMVN", ep="ZCIDMV") + test("txy", x=0x98, y=0, ey=0x98, p="X", ep="XN") + test("txy", x=0, y=0x98, ey=0, p="X", ep="XZ") + + test("tyx", y=0x8765, x=0x5678, ex=0x8765, p="", ep="N") + test("tyx", y=0x0000, x=0x5678, ex=0x0000, p="CIDMVN", ep="ZCIDMV") + test("tyx", y=0x98, x=0, ex=0x98, p="X", ep="XN") + test("tyx", y=0, x=0x98, ex=0, p="X", ep="XZ") + + +def transfer_misc_tests(): + test("tsx", ex=0x1EF, p="CZIDMVN", ep="CIDMV") + test("tsx", s=0x200, es=0x200, ex=0, p="X", ep="XZ") + test("tsx", ex=0xEF, p="X", ep="XN") + + test("tsc", ea=0x1EF, p="CZIDXVN", ep="CIDXV") + test("tsc", a=0x1234, s=0x200, es=0x200, ea=0x200, p="M", ep="M") + # Test TSC flag setting + after = """\ + bne @not_ok + iny + @not_ok: + ldx #$1ef + txs""" + test("tsc", s=0, y=0, ea=0, ey=1, ex=0x1EF, after_ins=after) + after = """\ + bpl @not_ok + iny + @not_ok: + ldx #$1ef + txs""" + test("tsc", s=0x8000, y=0, ea=0x8000, ey=1, ex=0x1EF, after_ins=after) + + test("txs", x=0x200, es=0x200, p="CZIDMVN", ep="CZIDMVN") + test("txs", x=0xFF, es=0x1FF, p="MXE", ep="MXE") + + test("tcs", a=0x200, es=0x200, p="CZIDMVN", ep="CZIDMVN") + test("tcs", a=0x77FF, es=0x1FF, p="MXE", ep="MXE") + + test("tcd", a=0, d=0x1234, ed=0, p="", ep="Z") + test("tcd", a=0x9876, ed=0x9876, p="CZIDMV", ep="CIDMVN") + test("tcd", a=0x9876, ed=0x9876, p="MXE", ep="MXEN") + + test("tdc", a=0, d=0x9876, ea=0x9876, p="M", ep="MN") + test("tdc", a=0x1234, d=0, ea=0, p="CIDXVN", ep="CZIDXV") + + +def xba_tests(): + test("xba", a=0x9812, ea=0x1298, p="", ep="N") + test("xba", a=0x00AA, ea=0xAA00, p="", ep="Z") + test("xba", a=0x9812, ea=0x1298, p="CZIDXMVNE", ep="CIDXMVNE") + + +def xce_tests(): + test("xce", p="", ep="") + test("xce", p="ZIDXMVN", ep="ZIDXMVN") + test("xce", x=0x1234, ex=0x34, y=0x4567, ey=0x67, p="C", ep="MXE") + test("xce", p="MXE", ep="MXC", advanced=False) + test("xce", p="C", s=0x3FF, es=0x1FF, ep="MXE") + + +def additional_tests(): + "Tests not on a specific instruction" + + # Test PC wrapping + OPCODE_NOP = 0xEA + # In case of incorrect wrapping, add a "bad" target + after = f"""\ + @not_ok: + jsr bank{bank_num}_save_results + bra @to_fail + @ok:""" + before = ( + jml_to_ok_instructions(0x7E0000) + + "\n" + + jml_to_label_instructions(0x7F0000, "@not_ok") + ) + test( + "jml $7EFFFF", + ins_name="nop ; test PC wrapping from $FFFF", + before_regs=before, + after_ins=after, + mem_7effff=OPCODE_NOP, + ) + + +# CZIDXMVN +def add_all_tests(): + additional_tests() + adc_binary_tests() + and_tests() + asl_tests() + bit_tests() + branch_tests() + brk_cop_tests() + brl_tests() + clear_set_tests() + cmp_tests() + dec_tests() + eor_tests() + inc_tests() + jmp_tests() + jsr_tests() + ld_tests() + lsr_tests() + mvn_tests() + mvp_tests() + ora_tests() + nop_wdm_tests() + pea_tests() + pei_tests() + per_tests() + pull_axy_tests() + pull_misc_tests() + push_tests() + rep_set_tests() + rol_tests() + ror_tests() + rts_rtl_rti_tests() + sbc_binary_tests() + st_tests() + trb_tests() + tsb_tests() + transfer_axy_tests() + transfer_misc_tests() + xba_tests() + xce_tests() + + # Do decimal tests at end because the behavior is partially undocumented + adc_decimal_tests() + sbc_decimal_tests() + + +def init_bank(): + add_asm(f"""\ + bank{bank_num}_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + """) + + +def next_bank(): + global bank_num, tests_in_bank + bank_num += 1 + tests_in_bank = 0 + add_asm(f"""\ + jml test{test_num:04x} + + .segment "BANK{bank_num}" + """) + init_bank() + + +def write_table(): + with open("tests_table.inc", "w") as f: + for i in range(test_num): + f.write(f".faraddr test{i:04x}\n") + + +def handle_cmdline(): + global basic_tests_only + + for arg in sys.argv[1:]: + if arg in ("-h", "--help"): + print(f"Usage: {sys.argv[0]} [--basic]") + print() + print("--basic: Generate basic tests only") + sys.exit(2) + elif arg == "--basic": + basic_tests_only = True + else: + print("Unknown command line argument") + sys.exit(2) + + +def main(): + handle_cmdline() + + tests_txt.append("Auto-generated by make_cpu_tests.py\n") + + asm_code.append("; Auto-generated by make_cpu_tests.py\n") + init_bank() + add_asm("start_tests:\n") + + add_all_tests() + + suffix = "-basic" if basic_tests_only else "-full" + with open(f"tests{suffix}.txt", "w") as f: + f.write("\n".join(tests_txt) + "\n") + + add_asm("jml success") + with open(f"tests{suffix}.inc", "w") as f: + f.write("\n".join(asm_code) + "\n") + + write_table() + + +main() diff --git a/roms/snes-tests/cputest/tests-basic.inc b/roms/snes-tests/cputest/tests-basic.inc new file mode 100644 index 00000000..9920d920 --- /dev/null +++ b/roms/snes-tests/cputest/tests-basic.inc @@ -0,0 +1,45699 @@ +; Auto-generated by make_cpu_tests.py + +bank0_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + + start_tests: + +test0000: +.export test0000: far + ldx #$00 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$5C ; jmp long opcode + sta $7f0000 + lda #<@not_ok + sta $7f0001 + lda #>@not_ok + sta $7f0002 + lda #^@not_ok + sta $7f0003 + lda #$ea + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFFF +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0001: +.export test0001: far + ldx #$01 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc #$edcb + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0002: +.export test0002: far + ldx #$02 + jsl init_test + lda #$cb + sta $7f1212 + lda #$ed + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$fe + sep #$01 + adc ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$cb + bne @to_fail + lda $7f1213 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0003: +.export test0003: far + ldx #$03 + jsl init_test + lda #$cb + sta $7f1212 + lda #$ed + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$cb + bne @to_fail + lda $7f1213 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0004: +.export test0004: far + ldx #$04 + jsl init_test + lda #$cb + sta $000201 + lda #$ed + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$cb + bne @to_fail + lda $000202 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0005: +.export test0005: far + ldx #$05 + jsl init_test + lda #$cb + sta $000033 + lda #$ed + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$cb + bne @to_fail + lda $000034 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0006: +.export test0006: far + ldx #$06 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cb + sta $7f1234 + lda #$ed + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$cb + bne @to_fail + lda $7f1235 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0007: +.export test0007: far + ldx #$07 + jsl init_test + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0008: +.export test0008: far + ldx #$08 + jsl init_test + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0009: +.export test0009: far + ldx #$09 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000a: +.export test000a: far + ldx #$0a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000b: +.export test000b: far + ldx #$0b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cb + sta $7f1234 + lda #$ed + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$cb + bne @to_fail + lda $7f1235 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000c: +.export test000c: far + ldx #$0c + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000d: +.export test000d: far + ldx #$0d + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000e: +.export test000e: far + ldx #$0e + jsl init_test + lda #$cb + sta $000134 + lda #$ed + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$fe + sep #$01 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$cb + bne @to_fail + lda $000135 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000f: +.export test000f: far + ldx #$0f + jsl init_test + lda #$cb + sta $000033 + lda #$ed + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$cb + bne @to_fail + lda $000034 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0010: +.export test0010: far + ldx #$10 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0011: +.export test0011: far + ldx #$11 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0012: +.export test0012: far + ldx #$12 + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$fe + sep #$01 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0013: +.export test0013: far + ldx #$13 + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$ee + sep #$11 + .i8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0014: +.export test0014: far + ldx #$14 + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fe + sep #$01 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0015: +.export test0015: far + ldx #$15 + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0016: +.export test0016: far + ldx #$16 + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fe + sep #$01 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0017: +.export test0017: far + ldx #$17 + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0018: +.export test0018: far + ldx #$18 + jsl init_test + rep #$20 + .a16 + lda #$6789 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + adc #$2000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c0 + bne @to_fail + ldx result_a + cpx #$8789 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0019: +.export test0019: far + ldx #$19 + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$39 + sep #$c6 + adc #$8000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0047 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001a: +.export test001a: far + ldx #$1a + jsl init_test + rep #$20 + .a16 + lda #$9000 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc #$e000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0041 + bne @to_fail + ldx result_a + cpx #$7001 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001b: +.export test001b: far + ldx #$1b + jsl init_test + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc #$ed + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001c: +.export test001c: far + ldx #$1c + jsl init_test + lda #$ed + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$ff91 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1212 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001d: +.export test001d: far + ldx #$1d + jsl init_test + lda #$ed + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1112 + ldx #$1210 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1212 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001e: +.export test001e: far + ldx #$1e + jsl init_test + lda #$ed + sta $000201 + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000201 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001f: +.export test001f: far + ldx #$1f + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0020: +.export test0020: far + ldx #$20 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$ed + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0021: +.export test0021: far + ldx #$21 + jsl init_test + lda #$ed + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0022: +.export test0022: far + ldx #$22 + jsl init_test + lda #$ed + sta $7effff + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0023: +.export test0023: far + ldx #$23 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$ed + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0024: +.export test0024: far + ldx #$24 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$ed + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0025: +.export test0025: far + ldx #$25 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0026: +.export test0026: far + ldx #$26 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$ed + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0027: +.export test0027: far + ldx #$27 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$ed + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0028: +.export test0028: far + ldx #$28 + jsl init_test + lda #$ed + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$0133 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000134 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0029: +.export test0029: far + ldx #$29 + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$1232 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002a: +.export test002a: far + ldx #$2a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$ed + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002b: +.export test002b: far + ldx #$2b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$ed + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002c: +.export test002c: far + ldx #$2c + jsl init_test + lda #$ed + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$0300 + rep #$de + sep #$21 + .a8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002d: +.export test002d: far + ldx #$2d + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1230 + rep #$ce + sep #$31 + .a8 + .i8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002e: +.export test002e: far + ldx #$2e + jsl init_test + lda #$ed + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$0300 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002f: +.export test002f: far + ldx #$2f + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0030: +.export test0030: far + ldx #$30 + jsl init_test + lda #$ed + sta $7f02ff + rep #$20 + .a16 + lda #$1112 + ldx #$0300 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0031: +.export test0031: far + ldx #$31 + jsl init_test + lda #$ed + sta $7f002f + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0032: +.export test0032: far + ldx #$32 + jsl init_test + rep #$20 + .a16 + lda #$1167 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + adc #$20 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e0 + bne @to_fail + ldx result_a + cpx #$1187 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0033: +.export test0033: far + ldx #$33 + jsl init_test + rep #$20 + .a16 + lda #$1180 + ldx #$3456 + ldy #$5678 + rep #$19 + sep #$e6 + .a8 + adc #$80 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0067 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0034: +.export test0034: far + ldx #$34 + jsl init_test + rep #$20 + .a16 + lda #$1190 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc #$e0 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0061 + bne @to_fail + ldx result_a + cpx #$1171 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0035: +.export test0035: far + ldx #$35 + jsl init_test + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and #$ef5c + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0036: +.export test0036: far + ldx #$36 + jsl init_test + lda #$5c + sta $7f1212 + lda #$ef + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + and ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1212 + cmp #$5c + bne @to_fail + lda $7f1213 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0037: +.export test0037: far + ldx #$37 + jsl init_test + lda #$5c + sta $7f1212 + lda #$ef + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1212 + cmp #$5c + bne @to_fail + lda $7f1213 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0038: +.export test0038: far + ldx #$38 + jsl init_test + lda #$5c + sta $000201 + lda #$ef + sta $000202 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000201 + cmp #$5c + bne @to_fail + lda $000202 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0039: +.export test0039: far + ldx #$39 + jsl init_test + lda #$5c + sta $000033 + lda #$ef + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000033 + cmp #$5c + bne @to_fail + lda $000034 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003a: +.export test003a: far + ldx #$3a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$5c + sta $7f1234 + lda #$ef + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1234 + cmp #$5c + bne @to_fail + lda $7f1235 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003b: +.export test003b: far + ldx #$3b + jsl init_test + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003c: +.export test003c: far + ldx #$3c + jsl init_test + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003d: +.export test003d: far + ldx #$3d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003e: +.export test003e: far + ldx #$3e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003f: +.export test003f: far + ldx #$3f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$5c + sta $7f1234 + lda #$ef + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1234 + cmp #$5c + bne @to_fail + lda $7f1235 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0040: +.export test0040: far + ldx #$40 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0041: +.export test0041: far + ldx #$41 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0042: +.export test0042: far + ldx #$42 + jsl init_test + lda #$5c + sta $000134 + lda #$ef + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000134 + cmp #$5c + bne @to_fail + lda $000135 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0043: +.export test0043: far + ldx #$43 + jsl init_test + lda #$5c + sta $000033 + lda #$ef + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000033 + cmp #$5c + bne @to_fail + lda $000034 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0044: +.export test0044: far + ldx #$44 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0045: +.export test0045: far + ldx #$45 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0046: +.export test0046: far + ldx #$46 + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0047: +.export test0047: far + ldx #$47 + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0048: +.export test0048: far + ldx #$48 + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0049: +.export test0049: far + ldx #$49 + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004a: +.export test004a: far + ldx #$4a + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004b: +.export test004b: far + ldx #$4b + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004c: +.export test004c: far + ldx #$4c + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and #$aaaa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004d: +.export test004d: far + ldx #$4d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + and #$4300 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004e: +.export test004e: far + ldx #$4e + jsl init_test + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and #$df + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004f: +.export test004f: far + ldx #$4f + jsl init_test + lda #$df + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1212 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0050: +.export test0050: far + ldx #$50 + jsl init_test + lda #$df + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$12fe + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1212 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0051: +.export test0051: far + ldx #$51 + jsl init_test + lda #$df + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000201 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0052: +.export test0052: far + ldx #$52 + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0053: +.export test0053: far + ldx #$53 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$df + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0054: +.export test0054: far + ldx #$54 + jsl init_test + lda #$df + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0055: +.export test0055: far + ldx #$55 + jsl init_test + lda #$df + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0056: +.export test0056: far + ldx #$56 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$df + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0057: +.export test0057: far + ldx #$57 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$df + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0058: +.export test0058: far + ldx #$58 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0059: +.export test0059: far + ldx #$59 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$df + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005a: +.export test005a: far + ldx #$5a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$df + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005b: +.export test005b: far + ldx #$5b + jsl init_test + lda #$df + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000134 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005c: +.export test005c: far + ldx #$5c + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005d: +.export test005d: far + ldx #$5d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$df + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005e: +.export test005e: far + ldx #$5e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$df + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005f: +.export test005f: far + ldx #$5f + jsl init_test + lda #$df + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0060: +.export test0060: far + ldx #$60 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0061: +.export test0061: far + ldx #$61 + jsl init_test + lda #$df + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0062: +.export test0062: far + ldx #$62 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0063: +.export test0063: far + ldx #$63 + jsl init_test + lda #$df + sta $7f02ff + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0064: +.export test0064: far + ldx #$64 + jsl init_test + lda #$df + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0065: +.export test0065: far + ldx #$65 + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0066: +.export test0066: far + ldx #$66 + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0067: +.export test0067: far + ldx #$67 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0068: +.export test0068: far + ldx #$68 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0069: +.export test0069: far + ldx #$69 + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006a: +.export test006a: far + ldx #$6a + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006b: +.export test006b: far + ldx #$6b + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006c: +.export test006c: far + ldx #$6c + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006d: +.export test006d: far + ldx #$6d + jsl init_test + rep #$20 + .a16 + lda #$4111 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$8222 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006e: +.export test006e: far + ldx #$6e + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$22 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006f: +.export test006f: far + ldx #$6f + jsl init_test + lda #$11 + sta $7effff + lda #$41 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0070: +.export test0070: far + ldx #$70 + jsl init_test + lda #$11 + sta $000134 + lda #$41 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$22 + bne @to_fail + lda $000135 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0071: +.export test0071: far + ldx #$71 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$22 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0072: +.export test0072: far + ldx #$72 + jsl init_test + lda #$11 + sta $7f02ff + lda #$41 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$22 + bne @to_fail + lda $7f0300 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0073: +.export test0073: far + ldx #$73 + jsl init_test + lda #$11 + sta $7f002f + lda #$41 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$22 + bne @to_fail + lda $7f0030 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0074: +.export test0074: far + ldx #$74 + jsl init_test + rep #$20 + .a16 + lda #$1280 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0075: +.export test0075: far + ldx #$75 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0076: +.export test0076: far + ldx #$76 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0077: +.export test0077: far + ldx #$77 + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0078: +.export test0078: far + ldx #$78 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0079: +.export test0079: far + ldx #$79 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007a: +.export test007a: far + ldx #$7a + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007b: +.export test007b: far + ldx #$7b + jsl init_test + rep #$20 + .a16 + lda #$1241 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1282 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007c: +.export test007c: far + ldx #$7c + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007d: +.export test007d: far + ldx #$7d + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007e: +.export test007e: far + ldx #$7e + jsl init_test + lda #$41 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007f: +.export test007f: far + ldx #$7f + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0080: +.export test0080: far + ldx #$80 + jsl init_test + lda #$41 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0081: +.export test0081: far + ldx #$81 + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0082: +.export test0082: far + ldx #$82 + jsl init_test + rep #$20 + .a16 + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit #$1234 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0083: +.export test0083: far + ldx #$83 + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit #$aaaa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0084: +.export test0084: far + ldx #$84 + jsl init_test + rep #$20 + .a16 + lda #$0056 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$0056 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0085: +.export test0085: far + ldx #$85 + jsl init_test + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0086: +.export test0086: far + ldx #$86 + jsl init_test + lda #$34 + sta $000033 + lda #$52 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0087: +.export test0087: far + ldx #$87 + jsl init_test + lda #$34 + sta $7effff + lda #$52 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7effff + cmp #$34 + bne @to_fail + lda $7f0000 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0088: +.export test0088: far + ldx #$88 + jsl init_test + lda #$34 + sta $000134 + lda #$52 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000134 + cmp #$34 + bne @to_fail + lda $000135 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0089: +.export test0089: far + ldx #$89 + jsl init_test + lda #$34 + sta $000033 + lda #$52 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008a: +.export test008a: far + ldx #$8a + jsl init_test + lda #$34 + sta $7f02ff + lda #$52 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7f02ff + cmp #$34 + bne @to_fail + lda $7f0300 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008b: +.export test008b: far + ldx #$8b + jsl init_test + lda #$34 + sta $7f002f + lda #$52 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7f002f + cmp #$34 + bne @to_fail + lda $7f0030 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008c: +.export test008c: far + ldx #$8c + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008d: +.export test008d: far + ldx #$8d + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + lda $7f0000 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008e: +.export test008e: far + ldx #$8e + jsl init_test + lda #$aa + sta $000134 + lda #$aa + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000134 + cmp #$aa + bne @to_fail + lda $000135 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008f: +.export test008f: far + ldx #$8f + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0092 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0090: +.export test0090: far + ldx #$90 + jsl init_test + lda #$aa + sta $7f02ff + lda #$aa + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7f02ff + cmp #$aa + bne @to_fail + lda $7f0300 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0091: +.export test0091: far + ldx #$91 + jsl init_test + lda #$aa + sta $7f002f + lda #$aa + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0092 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7f002f + cmp #$aa + bne @to_fail + lda $7f0030 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0092: +.export test0092: far + ldx #$92 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0093: +.export test0093: far + ldx #$93 + jsl init_test + lda #$52 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7effff + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0094: +.export test0094: far + ldx #$94 + jsl init_test + lda #$52 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000134 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0095: +.export test0095: far + ldx #$95 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0070 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0096: +.export test0096: far + ldx #$96 + jsl init_test + lda #$52 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7f02ff + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0097: +.export test0097: far + ldx #$97 + jsl init_test + lda #$52 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0070 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7f002f + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0098: +.export test0098: far + ldx #$98 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0099: +.export test0099: far + ldx #$99 + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009a: +.export test009a: far + ldx #$9a + jsl init_test + lda #$aa + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000134 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009b: +.export test009b: far + ldx #$9b + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009c: +.export test009c: far + ldx #$9c + jsl init_test + lda #$aa + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7f02ff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009d: +.export test009d: far + ldx #$9d + jsl init_test + lda #$aa + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7f002f + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009e: +.export test009e: far + ldx #$9e + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$80 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009f: +.export test009f: far + ldx #$9f + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$80 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a0: +.export test00a0: far + ldx #$a0 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$90 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a1: +.export test00a1: far + ldx #$a1 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$90 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a2: +.export test00a2: far + ldx #$a2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + bcc @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0001 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a3: +.export test00a3: far + ldx #$a3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bcs @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a4: +.export test00a4: far + ldx #$a4 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$d0 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a5: +.export test00a5: far + ldx #$a5 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$d0 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a6: +.export test00a6: far + ldx #$a6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + bne @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a7: +.export test00a7: far + ldx #$a7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$f0 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a8: +.export test00a8: far + ldx #$a8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$f0 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a9: +.export test00a9: far + ldx #$a9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + beq @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00aa: +.export test00aa: far + ldx #$aa + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$10 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ab: +.export test00ab: far + ldx #$ab + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$10 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ac: +.export test00ac: far + ldx #$ac + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + bpl @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ad: +.export test00ad: far + ldx #$ad + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$30 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ae: +.export test00ae: far + ldx #$ae + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$30 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00af: +.export test00af: far + ldx #$af + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bmi @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b0: +.export test00b0: far + ldx #$b0 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$50 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b1: +.export test00b1: far + ldx #$b1 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$50 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b2: +.export test00b2: far + ldx #$b2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + bvc @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b3: +.export test00b3: far + ldx #$b3 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$70 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b4: +.export test00b4: far + ldx #$b4 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$70 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + jml $7F0040 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b5: +.export test00b5: far + ldx #$b5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bvs @not_ok + bra @ok +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b6: +.export test00b6: far + ldx #$b6 + jsl init_test + lda #$5C ; jmp long opcode + sta $1000 + lda #<@ok + sta $1001 + lda #>@ok + sta $1002 + lda #^@ok + sta $1003 + lda #$00 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f4 + sep #$0b + jml $7e8000 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0007 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01eb + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + lda $0001ed + cmp #$02 + bne @to_fail + lda $0001ee + cmp #$80 + bne @to_fail + lda $0001ec + cmp #$0b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $1000 + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b7: +.export test00b7: far + ldx #$b7 + jsl init_test + lda #$5C ; jmp long opcode + sta $1004 + lda #<@ok + sta $1005 + lda #>@ok + sta $1006 + lda #^@ok + sta $1007 + lda #$02 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f4 + sep #$0b + jml $7e8000 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0007 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01eb + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + lda $0001ed + cmp #$02 + bne @to_fail + lda $0001ee + cmp #$80 + bne @to_fail + lda $0001ec + cmp #$0b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $1004 + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b8: +.export test00b8: far + ldx #$b8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7002 + lda #<@ok + sta $7e7003 + lda #>@ok + sta $7e7004 + lda #^@ok + sta $7e7005 + lda #$82 + sta $7ef000 + lda #$ff + sta $7ef001 + lda #$7f + sta $7ef002 + lda #$db + sta $7ef003 + lda #$db + sta $7f7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EF000 + @ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b9: +.export test00b9: far + ldx #$b9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + clc + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fe + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ba: +.export test00ba: far + ldx #$ba + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + clc + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bb: +.export test00bb: far + ldx #$bb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cld + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00f7 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bc: +.export test00bc: far + ldx #$bc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cld + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bd: +.export test00bd: far + ldx #$bd + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cli + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fb + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00be: +.export test00be: far + ldx #$be + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cli + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bf: +.export test00bf: far + ldx #$bf + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + clv + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00bf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c0: +.export test00c0: far + ldx #$c0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + clv + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c1: +.export test00c1: far + ldx #$c1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sec + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0001 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c2: +.export test00c2: far + ldx #$c2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sec + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c3: +.export test00c3: far + ldx #$c3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sed + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c4: +.export test00c4: far + ldx #$c4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sed + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c5: +.export test00c5: far + ldx #$c5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sei + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0004 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c6: +.export test00c6: far + ldx #$c6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sei + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c7: +.export test00c7: far + ldx #$c7 + jsl init_test + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp #$abcd + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c8: +.export test00c8: far + ldx #$c8 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c9: +.export test00c9: far + ldx #$c9 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcd + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ca: +.export test00ca: far + ldx #$ca + jsl init_test + lda #$cd + sta $000201 + lda #$ab + sta $000202 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + lda $000202 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cb: +.export test00cb: far + ldx #$cb + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cc: +.export test00cc: far + ldx #$cc + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cd: +.export test00cd: far + ldx #$cd + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ce: +.export test00ce: far + ldx #$ce + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cf: +.export test00cf: far + ldx #$cf + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d0: +.export test00d0: far + ldx #$d0 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d1: +.export test00d1: far + ldx #$d1 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d2: +.export test00d2: far + ldx #$d2 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d3: +.export test00d3: far + ldx #$d3 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d4: +.export test00d4: far + ldx #$d4 + jsl init_test + lda #$cd + sta $000134 + lda #$ab + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + cmp $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + lda $000135 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d5: +.export test00d5: far + ldx #$d5 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d6: +.export test00d6: far + ldx #$d6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d7: +.export test00d7: far + ldx #$d7 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d8: +.export test00d8: far + ldx #$d8 + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + cmp $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d9: +.export test00d9: far + ldx #$d9 + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + cmp $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00da: +.export test00da: far + ldx #$da + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + cmp $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00db: +.export test00db: far + ldx #$db + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00dc: +.export test00dc: far + ldx #$dc + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + cmp $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00dd: +.export test00dd: far + ldx #$dd + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00de: +.export test00de: far + ldx #$de + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx #$abcd + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00df: +.export test00df: far + ldx #$df + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e0: +.export test00e0: far + ldx #$e0 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e1: +.export test00e1: far + ldx #$e1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy #$abcd + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e2: +.export test00e2: far + ldx #$e2 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e3: +.export test00e3: far + ldx #$e3 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e4: +.export test00e4: far + ldx #$e4 + jsl init_test + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp #$abcd + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e5: +.export test00e5: far + ldx #$e5 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test00e6 + +.segment "BANK1" + +bank1_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test00e6: +.export test00e6: far + ldx #$e6 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcc + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e7: +.export test00e7: far + ldx #$e7 + jsl init_test + lda #$cd + sta $000201 + lda #$ab + sta $000202 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + lda $000202 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e8: +.export test00e8: far + ldx #$e8 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e9: +.export test00e9: far + ldx #$e9 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ea: +.export test00ea: far + ldx #$ea + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00eb: +.export test00eb: far + ldx #$eb + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ec: +.export test00ec: far + ldx #$ec + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ed: +.export test00ed: far + ldx #$ed + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ee: +.export test00ee: far + ldx #$ee + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ef: +.export test00ef: far + ldx #$ef + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f0: +.export test00f0: far + ldx #$f0 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f1: +.export test00f1: far + ldx #$f1 + jsl init_test + lda #$cd + sta $000134 + lda #$ab + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + lda $000135 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f2: +.export test00f2: far + ldx #$f2 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f3: +.export test00f3: far + ldx #$f3 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f4: +.export test00f4: far + ldx #$f4 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f5: +.export test00f5: far + ldx #$f5 + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f6: +.export test00f6: far + ldx #$f6 + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f7: +.export test00f7: far + ldx #$f7 + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f8: +.export test00f8: far + ldx #$f8 + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f9: +.export test00f9: far + ldx #$f9 + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fa: +.export test00fa: far + ldx #$fa + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fb: +.export test00fb: far + ldx #$fb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fc: +.export test00fc: far + ldx #$fc + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fd: +.export test00fd: far + ldx #$fd + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fe: +.export test00fe: far + ldx #$fe + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ff: +.export test00ff: far + ldx #$ff + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0100: +.export test0100: far + ldx #$100 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0101: +.export test0101: far + ldx #$101 + jsl init_test + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0102: +.export test0102: far + ldx #$102 + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0103: +.export test0103: far + ldx #$103 + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcd + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0104: +.export test0104: far + ldx #$104 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0105: +.export test0105: far + ldx #$105 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0106: +.export test0106: far + ldx #$106 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0107: +.export test0107: far + ldx #$107 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0108: +.export test0108: far + ldx #$108 + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0109: +.export test0109: far + ldx #$109 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010a: +.export test010a: far + ldx #$10a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010b: +.export test010b: far + ldx #$10b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010c: +.export test010c: far + ldx #$10c + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010d: +.export test010d: far + ldx #$10d + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010e: +.export test010e: far + ldx #$10e + jsl init_test + lda #$cd + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010f: +.export test010f: far + ldx #$10f + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0110: +.export test0110: far + ldx #$110 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0111: +.export test0111: far + ldx #$111 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0112: +.export test0112: far + ldx #$112 + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0113: +.export test0113: far + ldx #$113 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0114: +.export test0114: far + ldx #$114 + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0115: +.export test0115: far + ldx #$115 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0116: +.export test0116: far + ldx #$116 + jsl init_test + lda #$cd + sta $7f02ff + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0117: +.export test0117: far + ldx #$117 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0118: +.export test0118: far + ldx #$118 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0119: +.export test0119: far + ldx #$119 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011a: +.export test011a: far + ldx #$11a + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011b: +.export test011b: far + ldx #$11b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011c: +.export test011c: far + ldx #$11c + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011d: +.export test011d: far + ldx #$11d + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011e: +.export test011e: far + ldx #$11e + jsl init_test + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011f: +.export test011f: far + ldx #$11f + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0120: +.export test0120: far + ldx #$120 + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcc + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0121: +.export test0121: far + ldx #$121 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0122: +.export test0122: far + ldx #$122 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0123: +.export test0123: far + ldx #$123 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0124: +.export test0124: far + ldx #$124 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0125: +.export test0125: far + ldx #$125 + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0126: +.export test0126: far + ldx #$126 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0127: +.export test0127: far + ldx #$127 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0128: +.export test0128: far + ldx #$128 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0129: +.export test0129: far + ldx #$129 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012a: +.export test012a: far + ldx #$12a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012b: +.export test012b: far + ldx #$12b + jsl init_test + lda #$cd + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012c: +.export test012c: far + ldx #$12c + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012d: +.export test012d: far + ldx #$12d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012e: +.export test012e: far + ldx #$12e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012f: +.export test012f: far + ldx #$12f + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0130: +.export test0130: far + ldx #$130 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0131: +.export test0131: far + ldx #$131 + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0132: +.export test0132: far + ldx #$132 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0133: +.export test0133: far + ldx #$133 + jsl init_test + lda #$cd + sta $7f02ff + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0134: +.export test0134: far + ldx #$134 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0135: +.export test0135: far + ldx #$135 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0136: +.export test0136: far + ldx #$136 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0137: +.export test0137: far + ldx #$137 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0138: +.export test0138: far + ldx #$138 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0139: +.export test0139: far + ldx #$139 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013a: +.export test013a: far + ldx #$13a + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013b: +.export test013b: far + ldx #$13b + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013c: +.export test013c: far + ldx #$13c + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013d: +.export test013d: far + ldx #$13d + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013e: +.export test013e: far + ldx #$13e + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013f: +.export test013f: far + ldx #$13f + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0140: +.export test0140: far + ldx #$140 + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0141: +.export test0141: far + ldx #$141 + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0142: +.export test0142: far + ldx #$142 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0001 + ldy #$5678 + rep #$ff + sep #$00 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0143: +.export test0143: far + ldx #$143 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0001 + rep #$ff + sep #$00 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0144: +.export test0144: far + ldx #$144 + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0145: +.export test0145: far + ldx #$145 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0146: +.export test0146: far + ldx #$146 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + lda $7f0000 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0147: +.export test0147: far + ldx #$147 + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$ff + bne @to_fail + lda $000135 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0148: +.export test0148: far + ldx #$148 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0149: +.export test0149: far + ldx #$149 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$ff + bne @to_fail + lda $7f0300 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014a: +.export test014a: far + ldx #$14a + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$ff + bne @to_fail + lda $7f0030 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014b: +.export test014b: far + ldx #$14b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$30 + sep #$cf + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ffff + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014c: +.export test014c: far + ldx #$14c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$30 + sep #$cf + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$ffff + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014d: +.export test014d: far + ldx #$14d + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014e: +.export test014e: far + ldx #$14e + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014f: +.export test014f: far + ldx #$14f + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0150: +.export test0150: far + ldx #$150 + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0151: +.export test0151: far + ldx #$151 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0152: +.export test0152: far + ldx #$152 + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0153: +.export test0153: far + ldx #$153 + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0154: +.export test0154: far + ldx #$154 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0001 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0155: +.export test0155: far + ldx #$155 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0001 + rep #$ef + sep #$10 + .i8 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0156: +.export test0156: far + ldx #$156 + jsl init_test + rep #$20 + .a16 + lda #$1200 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$12ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0157: +.export test0157: far + ldx #$157 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0158: +.export test0158: far + ldx #$158 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0159: +.export test0159: far + ldx #$159 + jsl init_test + lda #$00 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015a: +.export test015a: far + ldx #$15a + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015b: +.export test015b: far + ldx #$15b + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015c: +.export test015c: far + ldx #$15c + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015d: +.export test015d: far + ldx #$15d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ff + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015e: +.export test015e: far + ldx #$15e + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ff + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015f: +.export test015f: far + ldx #$15f + jsl init_test + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor #$6f8c + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0160: +.export test0160: far + ldx #$160 + jsl init_test + lda #$8c + sta $7f1212 + lda #$6f + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + eor ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1212 + cmp #$8c + bne @to_fail + lda $7f1213 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0161: +.export test0161: far + ldx #$161 + jsl init_test + lda #$8c + sta $7f1212 + lda #$6f + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1212 + cmp #$8c + bne @to_fail + lda $7f1213 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0162: +.export test0162: far + ldx #$162 + jsl init_test + lda #$8c + sta $000201 + lda #$6f + sta $000202 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000201 + cmp #$8c + bne @to_fail + lda $000202 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0163: +.export test0163: far + ldx #$163 + jsl init_test + lda #$8c + sta $000033 + lda #$6f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000033 + cmp #$8c + bne @to_fail + lda $000034 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0164: +.export test0164: far + ldx #$164 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8c + sta $7f1234 + lda #$6f + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1234 + cmp #$8c + bne @to_fail + lda $7f1235 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0165: +.export test0165: far + ldx #$165 + jsl init_test + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0166: +.export test0166: far + ldx #$166 + jsl init_test + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0167: +.export test0167: far + ldx #$167 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0168: +.export test0168: far + ldx #$168 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0169: +.export test0169: far + ldx #$169 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8c + sta $7f1234 + lda #$6f + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1234 + cmp #$8c + bne @to_fail + lda $7f1235 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016a: +.export test016a: far + ldx #$16a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016b: +.export test016b: far + ldx #$16b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016c: +.export test016c: far + ldx #$16c + jsl init_test + lda #$8c + sta $000134 + lda #$6f + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000134 + cmp #$8c + bne @to_fail + lda $000135 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016d: +.export test016d: far + ldx #$16d + jsl init_test + lda #$8c + sta $000033 + lda #$6f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000033 + cmp #$8c + bne @to_fail + lda $000034 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016e: +.export test016e: far + ldx #$16e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016f: +.export test016f: far + ldx #$16f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0170: +.export test0170: far + ldx #$170 + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0171: +.export test0171: far + ldx #$171 + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0172: +.export test0172: far + ldx #$172 + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0173: +.export test0173: far + ldx #$173 + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0174: +.export test0174: far + ldx #$174 + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0175: +.export test0175: far + ldx #$175 + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0176: +.export test0176: far + ldx #$176 + jsl init_test + rep #$20 + .a16 + lda #$aaaa + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor #$aaaa + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0177: +.export test0177: far + ldx #$177 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + eor #$4334 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$5100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0178: +.export test0178: far + ldx #$178 + jsl init_test + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor #$6f + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0179: +.export test0179: far + ldx #$179 + jsl init_test + lda #$6f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1212 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017a: +.export test017a: far + ldx #$17a + jsl init_test + lda #$6f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$12fe + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1212 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017b: +.export test017b: far + ldx #$17b + jsl init_test + lda #$6f + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000201 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017c: +.export test017c: far + ldx #$17c + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017d: +.export test017d: far + ldx #$17d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$6f + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017e: +.export test017e: far + ldx #$17e + jsl init_test + lda #$6f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017f: +.export test017f: far + ldx #$17f + jsl init_test + lda #$6f + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0180: +.export test0180: far + ldx #$180 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$6f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0181: +.export test0181: far + ldx #$181 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$6f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0182: +.export test0182: far + ldx #$182 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0183: +.export test0183: far + ldx #$183 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$6f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0184: +.export test0184: far + ldx #$184 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$6f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0185: +.export test0185: far + ldx #$185 + jsl init_test + lda #$6f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000134 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0186: +.export test0186: far + ldx #$186 + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0187: +.export test0187: far + ldx #$187 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$6f + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0188: +.export test0188: far + ldx #$188 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$6f + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0189: +.export test0189: far + ldx #$189 + jsl init_test + lda #$6f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018a: +.export test018a: far + ldx #$18a + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018b: +.export test018b: far + ldx #$18b + jsl init_test + lda #$6f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018c: +.export test018c: far + ldx #$18c + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018d: +.export test018d: far + ldx #$18d + jsl init_test + lda #$6f + sta $7f02ff + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018e: +.export test018e: far + ldx #$18e + jsl init_test + lda #$6f + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018f: +.export test018f: far + ldx #$18f + jsl init_test + rep #$20 + .a16 + lda #$aaaa + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor #$aa + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0190: +.export test0190: far + ldx #$190 + jsl init_test + rep #$20 + .a16 + lda #$ffff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0191: +.export test0191: far + ldx #$191 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0192: +.export test0192: far + ldx #$192 + jsl init_test + lda #$ff + sta $7effff + lda #$ff + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0193: +.export test0193: far + ldx #$193 + jsl init_test + lda #$ff + sta $000134 + lda #$ff + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0194: +.export test0194: far + ldx #$194 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0195: +.export test0195: far + ldx #$195 + jsl init_test + lda #$ff + sta $7f02ff + lda #$ff + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0196: +.export test0196: far + ldx #$196 + jsl init_test + lda #$ff + sta $7f002f + lda #$ff + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0197: +.export test0197: far + ldx #$197 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$ffff + ldy #$5678 + rep #$ff + sep #$00 + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0198: +.export test0198: far + ldx #$198 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$ffff + rep #$ff + sep #$00 + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0199: +.export test0199: far + ldx #$199 + jsl init_test + rep #$20 + .a16 + lda #$7fff + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019a: +.export test019a: far + ldx #$19a + jsl init_test + lda #$ff + sta $000033 + lda #$7f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019b: +.export test019b: far + ldx #$19b + jsl init_test + lda #$ff + sta $7effff + lda #$7f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019c: +.export test019c: far + ldx #$19c + jsl init_test + lda #$ff + sta $000134 + lda #$7f + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019d: +.export test019d: far + ldx #$19d + jsl init_test + lda #$ff + sta $000033 + lda #$7f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019e: +.export test019e: far + ldx #$19e + jsl init_test + lda #$ff + sta $7f02ff + lda #$7f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019f: +.export test019f: far + ldx #$19f + jsl init_test + lda #$ff + sta $7f002f + lda #$7f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a0: +.export test01a0: far + ldx #$1a0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$7fff + ldy #$5678 + rep #$30 + sep #$cf + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a1: +.export test01a1: far + ldx #$1a1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$7fff + rep #$30 + sep #$cf + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a2: +.export test01a2: far + ldx #$1a2 + jsl init_test + rep #$20 + .a16 + lda #$12ff + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a3: +.export test01a3: far + ldx #$1a3 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a4: +.export test01a4: far + ldx #$1a4 + jsl init_test + lda #$ff + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a5: +.export test01a5: far + ldx #$1a5 + jsl init_test + lda #$ff + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a6: +.export test01a6: far + ldx #$1a6 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a7: +.export test01a7: far + ldx #$1a7 + jsl init_test + lda #$ff + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a8: +.export test01a8: far + ldx #$1a8 + jsl init_test + lda #$ff + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a9: +.export test01a9: far + ldx #$1a9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$00ff + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01aa: +.export test01aa: far + ldx #$1aa + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$00ff + rep #$ef + sep #$10 + .i8 + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ab: +.export test01ab: far + ldx #$1ab + jsl init_test + rep #$20 + .a16 + lda #$127f + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ac: +.export test01ac: far + ldx #$1ac + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ad: +.export test01ad: far + ldx #$1ad + jsl init_test + lda #$7f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ae: +.export test01ae: far + ldx #$1ae + jsl init_test + lda #$7f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01af: +.export test01af: far + ldx #$1af + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b0: +.export test01b0: far + ldx #$1b0 + jsl init_test + lda #$7f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b1: +.export test01b1: far + ldx #$1b1 + jsl init_test + lda #$7f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b2: +.export test01b2: far + ldx #$1b2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$007f + ldy #$5678 + rep #$20 + sep #$df + .i8 + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b3: +.export test01b3: far + ldx #$1b3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$007f + rep #$20 + sep #$df + .i8 + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b4: +.export test01b4: far + ldx #$1b4 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$4c + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + lda #$db + sta $7e7003 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b5: +.export test01b5: far + ldx #$1b5 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$6c + sta $7e7000 + lda #$a2 + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b6: +.export test01b6: far + ldx #$1b6 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml [$FFA4] + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b7: +.export test01b7: far + ldx #$1b7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7c + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$f0 + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e5000 + lda #$80 + sta $7e5001 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$6000 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$6000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b8: +.export test01b8: far + ldx #$1b8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7c + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0081 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + jml $7e7000 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b9: +.export test01b9: far + ldx #$1b9 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$20 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + lda #$db + sta $7e7003 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ba: +.export test01ba: far + ldx #$1ba + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$22 + sta $7f7000 + lda #$00 + sta $7f7001 + lda #$80 + sta $7f7002 + lda #$7e + sta $7f7003 + lda #$db + sta $7f7004 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7f7000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ec + bne @to_fail + lda $0001ed + cmp #$03 + bne @to_fail + lda $0001ee + cmp #$70 + bne @to_fail + lda $0001ef + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bb: +.export test01bb: far + ldx #$1bb + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$fc + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$f0 + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e5000 + lda #$80 + sta $7e5001 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$6000 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$6000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bc: +.export test01bc: far + ldx #$1bc + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$fc + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0081 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + jml $7e7000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bd: +.export test01bd: far + ldx #$1bd + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda #$8000 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01be: +.export test01be: far + ldx #$1be + jsl init_test + lda #$00 + sta $7f1212 + lda #$80 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$fd + sep #$02 + lda ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bf: +.export test01bf: far + ldx #$1bf + jsl init_test + lda #$00 + sta $7f1212 + lda #$80 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c0: +.export test01c0: far + ldx #$1c0 + jsl init_test + lda #$00 + sta $000201 + lda #$80 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c1: +.export test01c1: far + ldx #$1c1 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c2: +.export test01c2: far + ldx #$1c2 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + lda #$80 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c3: +.export test01c3: far + ldx #$1c3 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c4: +.export test01c4: far + ldx #$1c4 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c5: +.export test01c5: far + ldx #$1c5 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c6: +.export test01c6: far + ldx #$1c6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c7: +.export test01c7: far + ldx #$1c7 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$80 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c8: +.export test01c8: far + ldx #$1c8 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c9: +.export test01c9: far + ldx #$1c9 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ca: +.export test01ca: far + ldx #$1ca + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$fd + sep #$02 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cb: +.export test01cb: far + ldx #$1cb + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cc: +.export test01cc: far + ldx #$1cc + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cd: +.export test01cd: far + ldx #$1cd + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ce: +.export test01ce: far + ldx #$1ce + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$fd + sep #$02 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cf: +.export test01cf: far + ldx #$1cf + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$ed + sep #$12 + .i8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d0: +.export test01d0: far + ldx #$1d0 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fd + sep #$02 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d1: +.export test01d1: far + ldx #$1d1 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d2: +.export test01d2: far + ldx #$1d2 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fd + sep #$02 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d3: +.export test01d3: far + ldx #$1d3 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d4: +.export test01d4: far + ldx #$1d4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx #$8000 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d5: +.export test01d5: far + ldx #$1d5 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d6: +.export test01d6: far + ldx #$1d6 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d7: +.export test01d7: far + ldx #$1d7 + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0133 + rep #$fd + sep #$02 + ldx $02,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d8: +.export test01d8: far + ldx #$1d8 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$0300 + rep #$fd + sep #$02 + ldx $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d9: +.export test01d9: far + ldx #$1d9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy #$8000 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01da: +.export test01da: far + ldx #$1da + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01db: +.export test01db: far + ldx #$1db + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01dc: +.export test01dc: far + ldx #$1dc + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$1234 + rep #$fd + sep #$02 + ldy $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01dd: +.export test01dd: far + ldx #$1dd + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$1234 + rep #$fd + sep #$02 + ldy $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01de: +.export test01de: far + ldx #$1de + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01df: +.export test01df: far + ldx #$1df + jsl init_test + lda #$00 + sta $7f1212 + lda #$00 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + lda ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e0: +.export test01e0: far + ldx #$1e0 + jsl init_test + lda #$00 + sta $7f1212 + lda #$00 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e1: +.export test01e1: far + ldx #$1e1 + jsl init_test + lda #$00 + sta $000201 + lda #$00 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e2: +.export test01e2: far + ldx #$1e2 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e3: +.export test01e3: far + ldx #$1e3 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + lda #$00 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e4: +.export test01e4: far + ldx #$1e4 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e5: +.export test01e5: far + ldx #$1e5 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e6: +.export test01e6: far + ldx #$1e6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e7: +.export test01e7: far + ldx #$1e7 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e8: +.export test01e8: far + ldx #$1e8 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$00 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e9: +.export test01e9: far + ldx #$1e9 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ea: +.export test01ea: far + ldx #$1ea + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01eb: +.export test01eb: far + ldx #$1eb + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ec: +.export test01ec: far + ldx #$1ec + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ed: +.export test01ed: far + ldx #$1ed + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ee: +.export test01ee: far + ldx #$1ee + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ef: +.export test01ef: far + ldx #$1ef + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f0: +.export test01f0: far + ldx #$1f0 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f1: +.export test01f1: far + ldx #$1f1 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f2: +.export test01f2: far + ldx #$1f2 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f3: +.export test01f3: far + ldx #$1f3 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f4: +.export test01f4: far + ldx #$1f4 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f5: +.export test01f5: far + ldx #$1f5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f6: +.export test01f6: far + ldx #$1f6 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f7: +.export test01f7: far + ldx #$1f7 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f8: +.export test01f8: far + ldx #$1f8 + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0133 + rep #$30 + sep #$cf + ldx $02,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f9: +.export test01f9: far + ldx #$1f9 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$0300 + rep #$30 + sep #$cf + ldx $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fa: +.export test01fa: far + ldx #$1fa + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fb: +.export test01fb: far + ldx #$1fb + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fc: +.export test01fc: far + ldx #$1fc + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fd: +.export test01fd: far + ldx #$1fd + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$1234 + rep #$30 + sep #$cf + ldy $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fe: +.export test01fe: far + ldx #$1fe + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$1234 + rep #$30 + sep #$cf + ldy $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ff: +.export test01ff: far + ldx #$1ff + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda #$80 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0200: +.export test0200: far + ldx #$200 + jsl init_test + lda #$80 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1212 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0201: +.export test0201: far + ldx #$201 + jsl init_test + lda #$80 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1212 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0202: +.export test0202: far + ldx #$202 + jsl init_test + lda #$80 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000201 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0203: +.export test0203: far + ldx #$203 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0204: +.export test0204: far + ldx #$204 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$80 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0205: +.export test0205: far + ldx #$205 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0206: +.export test0206: far + ldx #$206 + jsl init_test + lda #$80 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0207: +.export test0207: far + ldx #$207 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$80 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0208: +.export test0208: far + ldx #$208 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$80 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0209: +.export test0209: far + ldx #$209 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020a: +.export test020a: far + ldx #$20a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$80 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020b: +.export test020b: far + ldx #$20b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$80 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020c: +.export test020c: far + ldx #$20c + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000134 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020d: +.export test020d: far + ldx #$20d + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020e: +.export test020e: far + ldx #$20e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$80 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020f: +.export test020f: far + ldx #$20f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$80 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0210: +.export test0210: far + ldx #$210 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$dd + sep #$22 + .a8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0211: +.export test0211: far + ldx #$211 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$cd + sep #$32 + .a8 + .i8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0212: +.export test0212: far + ldx #$212 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0213: +.export test0213: far + ldx #$213 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0214: +.export test0214: far + ldx #$214 + jsl init_test + lda #$80 + sta $7f02ff + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0215: +.export test0215: far + ldx #$215 + jsl init_test + lda #$80 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0216: +.export test0216: far + ldx #$216 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx #$80 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0217: +.export test0217: far + ldx #$217 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0218: +.export test0218: far + ldx #$218 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0219: +.export test0219: far + ldx #$219 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$1232 + rep #$ed + sep #$12 + .i8 + ldx $02,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021a: +.export test021a: far + ldx #$21a + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + rep #$ed + sep #$12 + .i8 + ldx $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021b: +.export test021b: far + ldx #$21b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy #$80 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021c: +.export test021c: far + ldx #$21c + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021d: +.export test021d: far + ldx #$21d + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021e: +.export test021e: far + ldx #$21e + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021f: +.export test021f: far + ldx #$21f + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0220: +.export test0220: far + ldx #$220 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0221: +.export test0221: far + ldx #$221 + jsl init_test + lda #$00 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0222: +.export test0222: far + ldx #$222 + jsl init_test + lda #$00 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0223: +.export test0223: far + ldx #$223 + jsl init_test + lda #$00 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0224: +.export test0224: far + ldx #$224 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0225: +.export test0225: far + ldx #$225 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0226: +.export test0226: far + ldx #$226 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0227: +.export test0227: far + ldx #$227 + jsl init_test + lda #$00 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0228: +.export test0228: far + ldx #$228 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0229: +.export test0229: far + ldx #$229 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022a: +.export test022a: far + ldx #$22a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022b: +.export test022b: far + ldx #$22b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022c: +.export test022c: far + ldx #$22c + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022d: +.export test022d: far + ldx #$22d + jsl init_test + lda #$00 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022e: +.export test022e: far + ldx #$22e + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022f: +.export test022f: far + ldx #$22f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0230: +.export test0230: far + ldx #$230 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0231: +.export test0231: far + ldx #$231 + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0232: +.export test0232: far + ldx #$232 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + lda $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0233: +.export test0233: far + ldx #$233 + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0234: +.export test0234: far + ldx #$234 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0235: +.export test0235: far + ldx #$235 + jsl init_test + lda #$00 + sta $7f02ff + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0236: +.export test0236: far + ldx #$236 + jsl init_test + lda #$00 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0237: +.export test0237: far + ldx #$237 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0238: +.export test0238: far + ldx #$238 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0239: +.export test0239: far + ldx #$239 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023a: +.export test023a: far + ldx #$23a + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$1232 + rep #$20 + sep #$df + .i8 + ldx $02,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023b: +.export test023b: far + ldx #$23b + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + rep #$20 + sep #$df + .i8 + ldx $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023c: +.export test023c: far + ldx #$23c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy #$00 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023d: +.export test023d: far + ldx #$23d + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023e: +.export test023e: far + ldx #$23e + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023f: +.export test023f: far + ldx #$23f + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0240: +.export test0240: far + ldx #$240 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0241: +.export test0241: far + ldx #$241 + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0242: +.export test0242: far + ldx #$242 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0243: +.export test0243: far + ldx #$243 + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0244: +.export test0244: far + ldx #$244 + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + lsr $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0245: +.export test0245: far + ldx #$245 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + lsr $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0246: +.export test0246: far + ldx #$246 + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + lsr $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0247: +.export test0247: far + ldx #$247 + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + lsr $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0248: +.export test0248: far + ldx #$248 + jsl init_test + rep #$20 + .a16 + lda #$4222 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$2111 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0249: +.export test0249: far + ldx #$249 + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024a: +.export test024a: far + ldx #$24a + jsl init_test + lda #$22 + sta $7effff + lda #$42 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$11 + bne @to_fail + lda $7f0000 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024b: +.export test024b: far + ldx #$24b + jsl init_test + lda #$22 + sta $000134 + lda #$42 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + lsr $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$11 + bne @to_fail + lda $000135 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024c: +.export test024c: far + ldx #$24c + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lsr $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024d: +.export test024d: far + ldx #$24d + jsl init_test + lda #$22 + sta $7f02ff + lda #$42 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lsr $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$11 + bne @to_fail + lda $7f0300 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test024e + +.segment "BANK2" + +bank2_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test024e: +.export test024e: far + ldx #$24e + jsl init_test + lda #$22 + sta $7f002f + lda #$42 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$11 + bne @to_fail + lda $7f0030 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024f: +.export test024f: far + ldx #$24f + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0250: +.export test0250: far + ldx #$250 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0251: +.export test0251: far + ldx #$251 + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0252: +.export test0252: far + ldx #$252 + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0253: +.export test0253: far + ldx #$253 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0254: +.export test0254: far + ldx #$254 + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0255: +.export test0255: far + ldx #$255 + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0256: +.export test0256: far + ldx #$256 + jsl init_test + rep #$20 + .a16 + lda #$1242 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1221 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0257: +.export test0257: far + ldx #$257 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0258: +.export test0258: far + ldx #$258 + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0259: +.export test0259: far + ldx #$259 + jsl init_test + lda #$42 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025a: +.export test025a: far + ldx #$25a + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025b: +.export test025b: far + ldx #$25b + jsl init_test + lda #$42 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025c: +.export test025c: far + ldx #$25c + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025d: +.export test025d: far + ldx #$25d + jsl init_test + lda #$21 + sta $7effff + lda #$22 + sta $7e0000 + lda #$23 + sta $7e0001 + lda #$24 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$ffff + ldy #$fffe + rep #$ff + sep #$00 + mvn #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0003 + bne @to_fail + cpy #$0002 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7ffffe + cmp #$21 + bne @to_fail + lda $7fffff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$23 + bne @to_fail + lda $7f0001 + cmp #$24 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025e: +.export test025e: far + ldx #$25e + jsl init_test + lda #$31 + sta $7f0005 + lda #$32 + sta $7f0204 + lda #$99 + sta $7f0200 + rep #$20 + .a16 + lda #$01ff + ldx #$0005 + ldy #$0000 + rep #$10 + sep #$ef + .a8 + mvn #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0205 + bne @to_fail + cpy #$0200 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0000 + cmp #$31 + bne @to_fail + lda $7f01ff + cmp #$32 + bne @to_fail + lda $7f0200 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025f: +.export test025f: far + ldx #$25f + jsl init_test + lda #$41 + sta $7f0000 + lda #$42 + sta $7f0001 + rep #$20 + .a16 + lda #$01ff + ldx #$0000 + ldy #$0002 + rep #$ff + sep #$00 + mvn #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0200 + bne @to_fail + cpy #$0202 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0200 + cmp #$41 + bne @to_fail + lda $7f0201 + cmp #$42 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0260: +.export test0260: far + ldx #$260 + jsl init_test + lda #$51 + sta $7e00ff + lda #$52 + sta $7e0000 + lda #$53 + sta $7e0001 + lda #$54 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$05ff + ldy #$05fe + rep #$ef + sep #$10 + .i8 + mvn #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0003 + bne @to_fail + cpy #$0002 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f00fe + cmp #$51 + bne @to_fail + lda $7f00ff + cmp #$52 + bne @to_fail + lda $7f0000 + cmp #$53 + bne @to_fail + lda $7f0001 + cmp #$54 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0261: +.export test0261: far + ldx #$261 + jsl init_test + lda #$21 + sta $7effff + lda #$22 + sta $7e0000 + lda #$23 + sta $7e0001 + lda #$24 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7ffffd + rep #$20 + .a16 + lda #$0003 + ldx #$0002 + ldy #$0001 + rep #$ff + sep #$00 + mvp #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$fffe + bne @to_fail + cpy #$fffd + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7ffffe + cmp #$21 + bne @to_fail + lda $7fffff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$23 + bne @to_fail + lda $7f0001 + cmp #$24 + bne @to_fail + lda $7ffffd + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0262: +.export test0262: far + ldx #$262 + jsl init_test + lda #$31 + sta $7f0000 + lda #$32 + sta $7f01ff + lda #$99 + sta $7f0004 + rep #$20 + .a16 + lda #$01ff + ldx #$01ff + ldy #$0204 + rep #$10 + sep #$ef + .a8 + mvp #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ffff + bne @to_fail + cpy #$0004 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0005 + cmp #$31 + bne @to_fail + lda $7f0204 + cmp #$32 + bne @to_fail + lda $7f0004 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0263: +.export test0263: far + ldx #$263 + jsl init_test + lda #$41 + sta $7f0200 + lda #$42 + sta $7f0201 + rep #$20 + .a16 + lda #$01ff + ldx #$0201 + ldy #$01ff + rep #$ff + sep #$00 + mvp #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0001 + bne @to_fail + cpy #$ffff + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0000 + cmp #$41 + bne @to_fail + lda $7f0001 + cmp #$42 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0264: +.export test0264: far + ldx #$264 + jsl init_test + lda #$51 + sta $7e00ff + lda #$52 + sta $7e0000 + lda #$53 + sta $7e0001 + lda #$54 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$0502 + ldy #$0501 + rep #$ef + sep #$10 + .i8 + mvp #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00fe + bne @to_fail + cpy #$00fd + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f00fe + cmp #$51 + bne @to_fail + lda $7f00ff + cmp #$52 + bne @to_fail + lda $7f0000 + cmp #$53 + bne @to_fail + lda $7f0001 + cmp #$54 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0265: +.export test0265: far + ldx #$265 + jsl init_test + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora #$b939 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0266: +.export test0266: far + ldx #$266 + jsl init_test + lda #$39 + sta $7f1212 + lda #$b9 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + ora ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + lda $7f1213 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0267: +.export test0267: far + ldx #$267 + jsl init_test + lda #$39 + sta $7f1212 + lda #$b9 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$2318 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + lda $7f1213 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0268: +.export test0268: far + ldx #$268 + jsl init_test + lda #$39 + sta $000201 + lda #$b9 + sta $000202 + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000201 + cmp #$39 + bne @to_fail + lda $000202 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0269: +.export test0269: far + ldx #$269 + jsl init_test + lda #$39 + sta $000033 + lda #$b9 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + lda $000034 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026a: +.export test026a: far + ldx #$26a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7f1234 + lda #$b9 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + lda $7f1235 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026b: +.export test026b: far + ldx #$26b + jsl init_test + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026c: +.export test026c: far + ldx #$26c + jsl init_test + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026d: +.export test026d: far + ldx #$26d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026e: +.export test026e: far + ldx #$26e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026f: +.export test026f: far + ldx #$26f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$39 + sta $7f1234 + lda #$b9 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + lda $7f1235 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0270: +.export test0270: far + ldx #$270 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0271: +.export test0271: far + ldx #$271 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0272: +.export test0272: far + ldx #$272 + jsl init_test + lda #$39 + sta $000134 + lda #$b9 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000134 + cmp #$39 + bne @to_fail + lda $000135 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0273: +.export test0273: far + ldx #$273 + jsl init_test + lda #$39 + sta $000033 + lda #$b9 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + lda $000034 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0274: +.export test0274: far + ldx #$274 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0275: +.export test0275: far + ldx #$275 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0276: +.export test0276: far + ldx #$276 + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0277: +.export test0277: far + ldx #$277 + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0278: +.export test0278: far + ldx #$278 + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0279: +.export test0279: far + ldx #$279 + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027a: +.export test027a: far + ldx #$27a + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + rep #$20 + .a16 + lda #$2318 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027b: +.export test027b: far + ldx #$27b + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + rep #$20 + .a16 + lda #$2318 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027c: +.export test027c: far + ldx #$27c + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027d: +.export test027d: far + ldx #$27d + jsl init_test + rep #$20 + .a16 + lda #$1200 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ora #$4300 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$5300 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027e: +.export test027e: far + ldx #$27e + jsl init_test + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora #$39 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027f: +.export test027f: far + ldx #$27f + jsl init_test + lda #$39 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0280: +.export test0280: far + ldx #$280 + jsl init_test + lda #$39 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1298 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0281: +.export test0281: far + ldx #$281 + jsl init_test + lda #$39 + sta $000201 + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000201 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0282: +.export test0282: far + ldx #$282 + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0283: +.export test0283: far + ldx #$283 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0284: +.export test0284: far + ldx #$284 + jsl init_test + lda #$39 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0285: +.export test0285: far + ldx #$285 + jsl init_test + lda #$39 + sta $7effff + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0286: +.export test0286: far + ldx #$286 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0287: +.export test0287: far + ldx #$287 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0288: +.export test0288: far + ldx #$288 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0289: +.export test0289: far + ldx #$289 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028a: +.export test028a: far + ldx #$28a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028b: +.export test028b: far + ldx #$28b + jsl init_test + lda #$39 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000134 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028c: +.export test028c: far + ldx #$28c + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028d: +.export test028d: far + ldx #$28d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028e: +.export test028e: far + ldx #$28e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028f: +.export test028f: far + ldx #$28f + jsl init_test + lda #$39 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0290: +.export test0290: far + ldx #$290 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0291: +.export test0291: far + ldx #$291 + jsl init_test + lda #$39 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0292: +.export test0292: far + ldx #$292 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0293: +.export test0293: far + ldx #$293 + jsl init_test + lda #$39 + sta $7f02ff + rep #$20 + .a16 + lda #$1298 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0294: +.export test0294: far + ldx #$294 + jsl init_test + lda #$39 + sta $7f002f + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0295: +.export test0295: far + ldx #$295 + jsl init_test + rep #$20 + .a16 + lda #$aa00 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0296: +.export test0296: far + ldx #$296 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + nop + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0297: +.export test0297: far + ldx #$297 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + wdm $AB + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0298: +.export test0298: far + ldx #$298 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pea $ABCD + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$cd + bne @to_fail + lda $0001ef + cmp #$ab + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0299: +.export test0299: far + ldx #$299 + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pei ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$65 + bne @to_fail + lda $0001ef + cmp #$87 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029a: +.export test029a: far + ldx #$29a + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7003 + lda #<@ok + sta $7e7004 + lda #>@ok + sta $7e7005 + lda #^@ok + sta $7e7006 + lda #$62 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$03 + bne @to_fail + lda $0001ef + cmp #$f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029b: +.export test029b: far + ldx #$29b + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7003 + lda #<@ok + sta $7e7004 + lda #>@ok + sta $7e7005 + lda #^@ok + sta $7e7006 + lda #$62 + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$7f + sta $7e7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029c: +.export test029c: far + ldx #$29c + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pla + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$fedc + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029d: +.export test029d: far + ldx #$29d + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$fedc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029e: +.export test029e: far + ldx #$29e + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ply + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$fedc + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test029f: +.export test029f: far + ldx #$29f + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pla + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a0: +.export test02a0: far + ldx #$2a0 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a1: +.export test02a1: far + ldx #$2a1 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ply + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a2: +.export test02a2: far + ldx #$2a2 + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + pla + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$12ef + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a3: +.export test02a3: far + ldx #$2a3 + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + plx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ef + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a4: +.export test02a4: far + ldx #$2a4 + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ply + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ef + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a5: +.export test02a5: far + ldx #$2a5 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + pla + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a6: +.export test02a6: far + ldx #$2a6 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + plx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a7: +.export test02a7: far + ldx #$2a7 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ply + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a8: +.export test02a8: far + ldx #$2a8 + jsl init_test + lda #$fe + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plb + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + lda result_dbr + cmp #$fe + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a9: +.export test02a9: far + ldx #$2a9 + jsl init_test + lda #$00 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$02 + sep #$fd + .a8 + .i8 + plb + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + lda result_dbr + cmp #$00 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02aa: +.export test02aa: far + ldx #$2aa + jsl init_test + lda #$53 + sta $0001f0 + lda #$97 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pld + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx result_d + cpx #$9753 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ab: +.export test02ab: far + ldx #$2ab + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$9999 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$02 + sep #$fd + .a8 + .i8 + pld + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx result_d + cpx #$0000 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ac: +.export test02ac: far + ldx #$2ac + jsl init_test + lda #$00 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + plp + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ad: +.export test02ad: far + ldx #$2ad + jsl init_test + lda #$23 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plp + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ae: +.export test02ae: far + ldx #$2ae + jsl init_test + lda #$10 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$2345 + ldy #$3456 + rep #$ff + sep #$00 + plp + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0045 + bne @to_fail + cpy #$0056 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02af: +.export test02af: far + ldx #$2af + jsl init_test + rep #$20 + .a16 + lda #$9876 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pha + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$76 + bne @to_fail + lda $0001ef + cmp #$98 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b0: +.export test02b0: far + ldx #$2b0 + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + pha + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$65 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b1: +.export test02b1: far + ldx #$2b1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$9876 + ldy #$5678 + rep #$ff + sep #$00 + phx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$9876 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$76 + bne @to_fail + lda $0001ef + cmp #$98 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b2: +.export test02b2: far + ldx #$2b2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0023 + ldy #$5678 + rep #$20 + sep #$df + .i8 + phx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0023 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$23 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b3: +.export test02b3: far + ldx #$2b3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1324 + rep #$ff + sep #$00 + phy + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1324 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$24 + bne @to_fail + lda $0001ef + cmp #$13 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b4: +.export test02b4: far + ldx #$2b4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0035 + rep #$20 + sep #$df + .i8 + phy + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0035 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$35 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b5: +.export test02b5: far + ldx #$2b5 + jsl init_test + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + phb + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b6: +.export test02b6: far + ldx #$2b6 + jsl init_test + rep #$20 + .a16 + lda #$6543 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + phd + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$43 + bne @to_fail + lda $0001ef + cmp #$65 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b7: +.export test02b7: far + ldx #$2b7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8001 + lda #<@ok + sta $7e8002 + lda #>@ok + sta $7e8003 + lda #^@ok + sta $7e8004 + lda #$4b + sta $7e8000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e8000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b8: +.export test02b8: far + ldx #$2b8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f5 + sep #$0a + php + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000a + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$0a + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b9: +.export test02b9: far + ldx #$2b9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sep #$FF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ba: +.export test02ba: far + ldx #$2ba + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + sep #$0F + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bb: +.export test02bb: far + ldx #$2bb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rep #$F0 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$000f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bc: +.export test02bc: far + ldx #$2bc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rep #$0F + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00f0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bd: +.export test02bd: far + ldx #$2bd + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$c5 + sep #$3a + .a8 + .i8 + rep #$38 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02be: +.export test02be: far + ldx #$2be + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bf: +.export test02bf: far + ldx #$2bf + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c0: +.export test02c0: far + ldx #$2c0 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c1: +.export test02c1: far + ldx #$2c1 + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c2: +.export test02c2: far + ldx #$2c2 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c3: +.export test02c3: far + ldx #$2c3 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c4: +.export test02c4: far + ldx #$2c4 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c5: +.export test02c5: far + ldx #$2c5 + jsl init_test + rep #$20 + .a16 + lda #$4111 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$8223 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c6: +.export test02c6: far + ldx #$2c6 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$23 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c7: +.export test02c7: far + ldx #$2c7 + jsl init_test + lda #$11 + sta $7effff + lda #$41 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$23 + bne @to_fail + lda $7f0000 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c8: +.export test02c8: far + ldx #$2c8 + jsl init_test + lda #$11 + sta $000134 + lda #$41 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$23 + bne @to_fail + lda $000135 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c9: +.export test02c9: far + ldx #$2c9 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$23 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ca: +.export test02ca: far + ldx #$2ca + jsl init_test + lda #$11 + sta $7f02ff + lda #$41 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$23 + bne @to_fail + lda $7f0300 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cb: +.export test02cb: far + ldx #$2cb + jsl init_test + lda #$11 + sta $7f002f + lda #$41 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$23 + bne @to_fail + lda $7f0030 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cc: +.export test02cc: far + ldx #$2cc + jsl init_test + rep #$20 + .a16 + lda #$1280 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cd: +.export test02cd: far + ldx #$2cd + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ce: +.export test02ce: far + ldx #$2ce + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cf: +.export test02cf: far + ldx #$2cf + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d0: +.export test02d0: far + ldx #$2d0 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d1: +.export test02d1: far + ldx #$2d1 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d2: +.export test02d2: far + ldx #$2d2 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d3: +.export test02d3: far + ldx #$2d3 + jsl init_test + rep #$20 + .a16 + lda #$1241 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1283 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d4: +.export test02d4: far + ldx #$2d4 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d5: +.export test02d5: far + ldx #$2d5 + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d6: +.export test02d6: far + ldx #$2d6 + jsl init_test + lda #$41 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d7: +.export test02d7: far + ldx #$2d7 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rol $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d8: +.export test02d8: far + ldx #$2d8 + jsl init_test + lda #$41 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d9: +.export test02d9: far + ldx #$2d9 + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rol $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02da: +.export test02da: far + ldx #$2da + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02db: +.export test02db: far + ldx #$2db + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02dc: +.export test02dc: far + ldx #$2dc + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02dd: +.export test02dd: far + ldx #$2dd + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02de: +.export test02de: far + ldx #$2de + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02df: +.export test02df: far + ldx #$2df + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e0: +.export test02e0: far + ldx #$2e0 + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e1: +.export test02e1: far + ldx #$2e1 + jsl init_test + rep #$20 + .a16 + lda #$4222 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$a111 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e2: +.export test02e2: far + ldx #$2e2 + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e3: +.export test02e3: far + ldx #$2e3 + jsl init_test + lda #$22 + sta $7effff + lda #$42 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$11 + bne @to_fail + lda $7f0000 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e4: +.export test02e4: far + ldx #$2e4 + jsl init_test + lda #$22 + sta $000134 + lda #$42 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$11 + bne @to_fail + lda $000135 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e5: +.export test02e5: far + ldx #$2e5 + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e6: +.export test02e6: far + ldx #$2e6 + jsl init_test + lda #$22 + sta $7f02ff + lda #$42 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$11 + bne @to_fail + lda $7f0300 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e7: +.export test02e7: far + ldx #$2e7 + jsl init_test + lda #$22 + sta $7f002f + lda #$42 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$11 + bne @to_fail + lda $7f0030 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e8: +.export test02e8: far + ldx #$2e8 + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e9: +.export test02e9: far + ldx #$2e9 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ea: +.export test02ea: far + ldx #$2ea + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02eb: +.export test02eb: far + ldx #$2eb + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ec: +.export test02ec: far + ldx #$2ec + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ed: +.export test02ed: far + ldx #$2ed + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ee: +.export test02ee: far + ldx #$2ee + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ef: +.export test02ef: far + ldx #$2ef + jsl init_test + rep #$20 + .a16 + lda #$1242 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$12a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f0: +.export test02f0: far + ldx #$2f0 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f1: +.export test02f1: far + ldx #$2f1 + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f2: +.export test02f2: far + ldx #$2f2 + jsl init_test + lda #$42 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f3: +.export test02f3: far + ldx #$2f3 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + ror $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f4: +.export test02f4: far + ldx #$2f4 + jsl init_test + lda #$42 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f5: +.export test02f5: far + ldx #$2f5 + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + ror $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f6: +.export test02f6: far + ldx #$2f6 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$60 + sta $7e8000 + lda #$ff + sta $0001f0 + lda #$ff + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e8000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f7: +.export test02f7: far + ldx #$2f7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$ff + sta $0001f0 + lda #$ff + sta $0001f1 + lda #$7e + sta $0001f2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rtl + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f2 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f8: +.export test02f8: far + ldx #$2f8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$88 + sta $0001f0 + lda #$00 + sta $0001f1 + lda #$00 + sta $0001f2 + lda #$7e + sta $0001f3 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fc + sep #$03 + rti + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0088 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f3 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f9: +.export test02f9: far + ldx #$2f9 + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc #$908f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fa: +.export test02fa: far + ldx #$2fa + jsl init_test + lda #$8f + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fb: +.export test02fb: far + ldx #$2fb + jsl init_test + lda #$8f + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fc: +.export test02fc: far + ldx #$2fc + jsl init_test + lda #$8f + sta $000201 + lda #$90 + sta $000202 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$8f + bne @to_fail + lda $000202 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fd: +.export test02fd: far + ldx #$2fd + jsl init_test + lda #$8f + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fe: +.export test02fe: far + ldx #$2fe + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7f1234 + lda #$90 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ff: +.export test02ff: far + ldx #$2ff + jsl init_test + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0300: +.export test0300: far + ldx #$300 + jsl init_test + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0301: +.export test0301: far + ldx #$301 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0302: +.export test0302: far + ldx #$302 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0303: +.export test0303: far + ldx #$303 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8f + sta $7f1234 + lda #$90 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0304: +.export test0304: far + ldx #$304 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0305: +.export test0305: far + ldx #$305 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0306: +.export test0306: far + ldx #$306 + jsl init_test + lda #$8f + sta $000134 + lda #$90 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + sbc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$8f + bne @to_fail + lda $000135 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0307: +.export test0307: far + ldx #$307 + jsl init_test + lda #$8f + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0308: +.export test0308: far + ldx #$308 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0309: +.export test0309: far + ldx #$309 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030a: +.export test030a: far + ldx #$30a + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + sbc $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030b: +.export test030b: far + ldx #$30b + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + sbc $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030c: +.export test030c: far + ldx #$30c + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sbc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030d: +.export test030d: far + ldx #$30d + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030e: +.export test030e: far + ldx #$30e + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sbc $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030f: +.export test030f: far + ldx #$30f + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0310: +.export test0310: far + ldx #$310 + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + sbc #$2000 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0041 + bne @to_fail + ldx result_a + cpx #$7090 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0311: +.export test0311: far + ldx #$311 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$b8 + sep #$47 + sbc #$1235 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0084 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0312: +.export test0312: far + ldx #$312 + jsl init_test + rep #$20 + .a16 + lda #$7000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc #$a000 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c0 + bne @to_fail + ldx result_a + cpx #$cfff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0313: +.export test0313: far + ldx #$313 + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc #$8f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0314: +.export test0314: far + ldx #$314 + jsl init_test + lda #$8f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0315: +.export test0315: far + ldx #$315 + jsl init_test + lda #$8f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc90 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0316: +.export test0316: far + ldx #$316 + jsl init_test + lda #$8f + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0317: +.export test0317: far + ldx #$317 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0318: +.export test0318: far + ldx #$318 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0319: +.export test0319: far + ldx #$319 + jsl init_test + lda #$8f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031a: +.export test031a: far + ldx #$31a + jsl init_test + lda #$8f + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031b: +.export test031b: far + ldx #$31b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031c: +.export test031c: far + ldx #$31c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031d: +.export test031d: far + ldx #$31d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031e: +.export test031e: far + ldx #$31e + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031f: +.export test031f: far + ldx #$31f + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0320: +.export test0320: far + ldx #$320 + jsl init_test + lda #$8f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0321: +.export test0321: far + ldx #$321 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0322: +.export test0322: far + ldx #$322 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0323: +.export test0323: far + ldx #$323 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0324: +.export test0324: far + ldx #$324 + jsl init_test + lda #$8f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + sbc $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0325: +.export test0325: far + ldx #$325 + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0326: +.export test0326: far + ldx #$326 + jsl init_test + lda #$8f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0327: +.export test0327: far + ldx #$327 + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0328: +.export test0328: far + ldx #$328 + jsl init_test + lda #$8f + sta $7f02ff + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0329: +.export test0329: far + ldx #$329 + jsl init_test + lda #$8f + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032a: +.export test032a: far + ldx #$32a + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + sbc #$20 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0061 + bne @to_fail + ldx result_a + cpx #$cc70 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032b: +.export test032b: far + ldx #$32b + jsl init_test + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$98 + sep #$67 + .a8 + sbc #$13 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a4 + bne @to_fail + ldx result_a + cpx #$ccff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032c: +.export test032c: far + ldx #$32c + jsl init_test + rep #$20 + .a16 + lda #$cc70 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc #$a0 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e0 + bne @to_fail + ldx result_a + cpx #$cccf + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032d: +.export test032d: far + ldx #$32d + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + sta ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032e: +.export test032e: far + ldx #$32e + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032f: +.export test032f: far + ldx #$32f + jsl init_test + lda #$34 + sta $000201 + lda #$12 + sta $000202 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0330: +.export test0330: far + ldx #$330 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0331: +.export test0331: far + ldx #$331 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0332: +.export test0332: far + ldx #$332 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0333: +.export test0333: far + ldx #$333 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0334: +.export test0334: far + ldx #$334 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0335: +.export test0335: far + ldx #$335 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0336: +.export test0336: far + ldx #$336 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0337: +.export test0337: far + ldx #$337 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0338: +.export test0338: far + ldx #$338 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0339: +.export test0339: far + ldx #$339 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033a: +.export test033a: far + ldx #$33a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033b: +.export test033b: far + ldx #$33b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033c: +.export test033c: far + ldx #$33c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033d: +.export test033d: far + ldx #$33d + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033e: +.export test033e: far + ldx #$33e + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033f: +.export test033f: far + ldx #$33f + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0340: +.export test0340: far + ldx #$340 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0341: +.export test0341: far + ldx #$341 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0342: +.export test0342: far + ldx #$342 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0343: +.export test0343: far + ldx #$343 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$ff + sep #$00 + stx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0344: +.export test0344: far + ldx #$344 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$ff + sep #$00 + stx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0345: +.export test0345: far + ldx #$345 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$0133 + rep #$ff + sep #$00 + stx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0346: +.export test0346: far + ldx #$346 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$ff + sep #$00 + sty $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0347: +.export test0347: far + ldx #$347 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$ff + sep #$00 + sty $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0348: +.export test0348: far + ldx #$348 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$8000 + rep #$ff + sep #$00 + sty $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0349: +.export test0349: far + ldx #$349 + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + sta ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034a: +.export test034a: far + ldx #$34a + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034b: +.export test034b: far + ldx #$34b + jsl init_test + lda #$34 + sta $000201 + lda #$12 + sta $000202 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034c: +.export test034c: far + ldx #$34c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034d: +.export test034d: far + ldx #$34d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034e: +.export test034e: far + ldx #$34e + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034f: +.export test034f: far + ldx #$34f + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0350: +.export test0350: far + ldx #$350 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0351: +.export test0351: far + ldx #$351 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0352: +.export test0352: far + ldx #$352 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0353: +.export test0353: far + ldx #$353 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0354: +.export test0354: far + ldx #$354 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0355: +.export test0355: far + ldx #$355 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0356: +.export test0356: far + ldx #$356 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0357: +.export test0357: far + ldx #$357 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0358: +.export test0358: far + ldx #$358 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0359: +.export test0359: far + ldx #$359 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035a: +.export test035a: far + ldx #$35a + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035b: +.export test035b: far + ldx #$35b + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035c: +.export test035c: far + ldx #$35c + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035d: +.export test035d: far + ldx #$35d + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035e: +.export test035e: far + ldx #$35e + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035f: +.export test035f: far + ldx #$35f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$30 + sep #$cf + stx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0360: +.export test0360: far + ldx #$360 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$30 + sep #$cf + stx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0361: +.export test0361: far + ldx #$361 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$0133 + rep #$30 + sep #$cf + stx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0362: +.export test0362: far + ldx #$362 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$30 + sep #$cf + sty $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0363: +.export test0363: far + ldx #$363 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$30 + sep #$cf + sty $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0364: +.export test0364: far + ldx #$364 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$8000 + rep #$30 + sep #$cf + sty $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0365: +.export test0365: far + ldx #$365 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0366: +.export test0366: far + ldx #$366 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$5500 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0367: +.export test0367: far + ldx #$367 + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0368: +.export test0368: far + ldx #$368 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0369: +.export test0369: far + ldx #$369 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036a: +.export test036a: far + ldx #$36a + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036b: +.export test036b: far + ldx #$36b + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036c: +.export test036c: far + ldx #$36c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036d: +.export test036d: far + ldx #$36d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036e: +.export test036e: far + ldx #$36e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036f: +.export test036f: far + ldx #$36f + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0370: +.export test0370: far + ldx #$370 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0371: +.export test0371: far + ldx #$371 + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0372: +.export test0372: far + ldx #$372 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0373: +.export test0373: far + ldx #$373 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$12 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0374: +.export test0374: far + ldx #$374 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0375: +.export test0375: far + ldx #$375 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0376: +.export test0376: far + ldx #$376 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0377: +.export test0377: far + ldx #$377 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0378: +.export test0378: far + ldx #$378 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0379: +.export test0379: far + ldx #$379 + jsl init_test + lda #$12 + sta $7f02ff + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037a: +.export test037a: far + ldx #$37a + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037b: +.export test037b: far + ldx #$37b + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037c: +.export test037c: far + ldx #$37c + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037d: +.export test037d: far + ldx #$37d + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$1232 + rep #$ef + sep #$10 + .i8 + stx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037e: +.export test037e: far + ldx #$37e + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037f: +.export test037f: far + ldx #$37f + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0380: +.export test0380: far + ldx #$380 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0381: +.export test0381: far + ldx #$381 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0382: +.export test0382: far + ldx #$382 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$5500 + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0383: +.export test0383: far + ldx #$383 + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0384: +.export test0384: far + ldx #$384 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0385: +.export test0385: far + ldx #$385 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0386: +.export test0386: far + ldx #$386 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0387: +.export test0387: far + ldx #$387 + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0388: +.export test0388: far + ldx #$388 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0389: +.export test0389: far + ldx #$389 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038a: +.export test038a: far + ldx #$38a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038b: +.export test038b: far + ldx #$38b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038c: +.export test038c: far + ldx #$38c + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038d: +.export test038d: far + ldx #$38d + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038e: +.export test038e: far + ldx #$38e + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038f: +.export test038f: far + ldx #$38f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$12 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0390: +.export test0390: far + ldx #$390 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0391: +.export test0391: far + ldx #$391 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0392: +.export test0392: far + ldx #$392 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + sta $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0393: +.export test0393: far + ldx #$393 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0394: +.export test0394: far + ldx #$394 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0395: +.export test0395: far + ldx #$395 + jsl init_test + lda #$12 + sta $7f02ff + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0396: +.export test0396: far + ldx #$396 + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0397: +.export test0397: far + ldx #$397 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0398: +.export test0398: far + ldx #$398 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0399: +.export test0399: far + ldx #$399 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$1232 + rep #$20 + sep #$df + .i8 + stx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039a: +.export test039a: far + ldx #$39a + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039b: +.export test039b: far + ldx #$39b + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039c: +.export test039c: far + ldx #$39c + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039d: +.export test039d: far + ldx #$39d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + stz $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039e: +.export test039e: far + ldx #$39e + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039f: +.export test039f: far + ldx #$39f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a0: +.export test03a0: far + ldx #$3a0 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + stz $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a1: +.export test03a1: far + ldx #$3a1 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a2: +.export test03a2: far + ldx #$3a2 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a3: +.export test03a3: far + ldx #$3a3 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + stz $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a4: +.export test03a4: far + ldx #$3a4 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a5: +.export test03a5: far + ldx #$3a5 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a6: +.export test03a6: far + ldx #$3a6 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + stz $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a7: +.export test03a7: far + ldx #$3a7 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a8: +.export test03a8: far + ldx #$3a8 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a9: +.export test03a9: far + ldx #$3a9 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03aa: +.export test03aa: far + ldx #$3aa + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ab: +.export test03ab: far + ldx #$3ab + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + stz $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ac: +.export test03ac: far + ldx #$3ac + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ad: +.export test03ad: far + ldx #$3ad + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ae: +.export test03ae: far + ldx #$3ae + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + stz $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03af: +.export test03af: far + ldx #$3af + jsl init_test + lda #$34 + sta $000033 + lda #$92 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + trb $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $000033 + cmp #$04 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b0: +.export test03b0: far + ldx #$3b0 + jsl init_test + lda #$34 + sta $7effff + lda #$92 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + trb $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $7effff + cmp #$04 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b1: +.export test03b1: far + ldx #$3b1 + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + trb $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b2: +.export test03b2: far + ldx #$3b2 + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + trb $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + lda $7f0000 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b3: +.export test03b3: far + ldx #$3b3 + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + trb $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b4: +.export test03b4: far + ldx #$3b4 + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + trb $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b5: +.export test03b5: far + ldx #$3b5 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + trb $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test03b6 + +.segment "BANK3" + +bank3_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test03b6: +.export test03b6: far + ldx #$3b6 + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + trb $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b7: +.export test03b7: far + ldx #$3b7 + jsl init_test + lda #$34 + sta $000033 + lda #$92 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + tsb $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b8: +.export test03b8: far + ldx #$3b8 + jsl init_test + lda #$34 + sta $7effff + lda #$92 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + tsb $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $7effff + cmp #$34 + bne @to_fail + lda $7f0000 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b9: +.export test03b9: far + ldx #$3b9 + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tsb $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ba: +.export test03ba: far + ldx #$3ba + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tsb $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + lda $7f0000 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bb: +.export test03bb: far + ldx #$3bb + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsb $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bc: +.export test03bc: far + ldx #$3bc + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsb $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bd: +.export test03bd: far + ldx #$3bd + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsb $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03be: +.export test03be: far + ldx #$3be + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsb $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bf: +.export test03bf: far + ldx #$3bf + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$5678 + ldy #$5678 + rep #$ff + sep #$00 + tax + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c0: +.export test03c0: far + ldx #$3c0 + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$5678 + ldy #$5678 + rep #$ff + sep #$00 + tax + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c1: +.export test03c1: far + ldx #$3c1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tax + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$1234 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c2: +.export test03c2: far + ldx #$3c2 + jsl init_test + rep #$20 + .a16 + lda #$87ab + ldx #$5678 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tax + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ab + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$87ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c3: +.export test03c3: far + ldx #$3c3 + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tay + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c4: +.export test03c4: far + ldx #$3c4 + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tay + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c5: +.export test03c5: far + ldx #$3c5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tay + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1234 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c6: +.export test03c6: far + ldx #$3c6 + jsl init_test + rep #$20 + .a16 + lda #$87ab + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tay + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ab + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$87ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c7: +.export test03c7: far + ldx #$3c7 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$9876 + ldy #$5678 + rep #$ff + sep #$00 + txa + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$9876 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c8: +.export test03c8: far + ldx #$3c8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ff + sep #$00 + txa + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c9: +.export test03c9: far + ldx #$3c9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$00cd + ldy #$5678 + rep #$20 + sep #$df + .i8 + txa + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$00cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ca: +.export test03ca: far + ldx #$3ca + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$df + sep #$20 + .a8 + txa + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cb: +.export test03cb: far + ldx #$3cb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$ab00 + ldy #$5678 + rep #$df + sep #$20 + .a8 + txa + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ab00 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cc: +.export test03cc: far + ldx #$3cc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$9876 + rep #$ff + sep #$00 + tya + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$9876 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cd: +.export test03cd: far + ldx #$3cd + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tya + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ce: +.export test03ce: far + ldx #$3ce + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$00cd + rep #$20 + sep #$df + .i8 + tya + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$00cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cf: +.export test03cf: far + ldx #$3cf + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$df + sep #$20 + .a8 + tya + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d0: +.export test03d0: far + ldx #$3d0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$ab00 + rep #$df + sep #$20 + .a8 + tya + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$ab00 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d1: +.export test03d1: far + ldx #$3d1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$8765 + ldy #$5678 + rep #$ff + sep #$00 + txy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d2: +.export test03d2: far + ldx #$3d2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$12 + sep #$ed + .a8 + txy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d3: +.export test03d3: far + ldx #$3d3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0098 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + txy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0098 + bne @to_fail + cpy #$0098 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d4: +.export test03d4: far + ldx #$3d4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$0098 + rep #$ef + sep #$10 + .i8 + txy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d5: +.export test03d5: far + ldx #$3d5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$8765 + rep #$ff + sep #$00 + tyx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d6: +.export test03d6: far + ldx #$3d6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$0000 + rep #$12 + sep #$ed + .a8 + tyx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d7: +.export test03d7: far + ldx #$3d7 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$0098 + rep #$ef + sep #$10 + .i8 + tyx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0098 + bne @to_fail + cpy #$0098 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d8: +.export test03d8: far + ldx #$3d8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0098 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + tyx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d9: +.export test03d9: far + ldx #$3d9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03da: +.export test03da: far + ldx #$3da + jsl init_test + rep #$20 + .a16 + ldx #$0200 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tsx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03db: +.export test03db: far + ldx #$3db + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tsx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ef + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03dc: +.export test03dc: far + ldx #$3dc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + tsc + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$01ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03dd: +.export test03dd: far + ldx #$3dd + jsl init_test + rep #$20 + .a16 + ldx #$0200 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsc + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03de: +.export test03de: far + ldx #$3de + jsl init_test + rep #$20 + .a16 + ldx #$0000 + txs + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tsc + bne @not_ok + iny +@not_ok: + ldx #$1ef + txs + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$0001 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03df: +.export test03df: far + ldx #$3df + jsl init_test + rep #$20 + .a16 + ldx #$8000 + txs + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tsc + bpl @not_ok + iny +@not_ok: + ldx #$1ef + txs + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$0001 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e0: +.export test03e0: far + ldx #$3e0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0200 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + txs + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0200 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e1: +.export test03e1: far + ldx #$3e1 + jsl init_test + rep #$20 + .a16 + lda #$0200 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tcs + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e2: +.export test03e2: far + ldx #$3e2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + tcd + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tcd + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + ldx result_d + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e3: +.export test03e3: far + ldx #$3e3 + jsl init_test + rep #$20 + .a16 + lda #$9876 + ldx #$3456 + ldy #$5678 + rep #$90 + sep #$6f + .a8 + tcd + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + ldx result_d + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e4: +.export test03e4: far + ldx #$3e4 + jsl init_test + rep #$20 + .a16 + lda #$9876 + tcd + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tdc + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e5: +.export test03e5: far + ldx #$3e5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$22 + sep #$dd + .i8 + tdc + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e6: +.export test03e6: far + ldx #$3e6 + jsl init_test + rep #$20 + .a16 + lda #$9812 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xba + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1298 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e7: +.export test03e7: far + ldx #$3e7 + jsl init_test + rep #$20 + .a16 + lda #$00aa + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xba + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e8: +.export test03e8: far + ldx #$3e8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xce + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e9: +.export test03e9: far + ldx #$3e9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$01 + sep #$fe + .a8 + .i8 + xce + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fe + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ea: +.export test03ea: far + ldx #$3ea + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$4567 + rep #$fe + sep #$01 + xce + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0067 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03eb: +.export test03eb: far + ldx #$3eb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + xce + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0031 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ec: +.export test03ec: far + ldx #$3ec + jsl init_test + rep #$20 + .a16 + ldx #$03ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + xce + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ed: +.export test03ed: far + ldx #$3ed + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc #$8765 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ee: +.export test03ee: far + ldx #$3ee + jsl init_test + lda #$65 + sta $7f1212 + lda #$87 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$65 + bne @to_fail + lda $7f1213 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ef: +.export test03ef: far + ldx #$3ef + jsl init_test + lda #$65 + sta $7f1212 + lda #$87 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$65 + bne @to_fail + lda $7f1213 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f0: +.export test03f0: far + ldx #$3f0 + jsl init_test + lda #$65 + sta $000201 + lda #$87 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$65 + bne @to_fail + lda $000202 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f1: +.export test03f1: far + ldx #$3f1 + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$65 + bne @to_fail + lda $000034 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f2: +.export test03f2: far + ldx #$3f2 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$65 + sta $7f1234 + lda #$87 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$65 + bne @to_fail + lda $7f1235 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f3: +.export test03f3: far + ldx #$3f3 + jsl init_test + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f4: +.export test03f4: far + ldx #$3f4 + jsl init_test + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f5: +.export test03f5: far + ldx #$3f5 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f6: +.export test03f6: far + ldx #$3f6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f7: +.export test03f7: far + ldx #$3f7 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$65 + sta $7f1234 + lda #$87 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$65 + bne @to_fail + lda $7f1235 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f8: +.export test03f8: far + ldx #$3f8 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f9: +.export test03f9: far + ldx #$3f9 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fa: +.export test03fa: far + ldx #$3fa + jsl init_test + lda #$65 + sta $000134 + lda #$87 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$f6 + sep #$09 + adc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$65 + bne @to_fail + lda $000135 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fb: +.export test03fb: far + ldx #$3fb + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$65 + bne @to_fail + lda $000034 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fc: +.export test03fc: far + ldx #$3fc + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fd: +.export test03fd: far + ldx #$3fd + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fe: +.export test03fe: far + ldx #$3fe + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$f6 + sep #$09 + adc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ff: +.export test03ff: far + ldx #$3ff + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$e6 + sep #$19 + .i8 + adc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0400: +.export test0400: far + ldx #$400 + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$f6 + sep #$09 + adc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0401: +.export test0401: far + ldx #$401 + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0402: +.export test0402: far + ldx #$402 + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$f6 + sep #$09 + adc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0403: +.export test0403: far + ldx #$403 + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0404: +.export test0404: far + ldx #$404 + jsl init_test + rep #$20 + .a16 + lda #$3550 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + adc #$4470 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c8 + bne @to_fail + ldx result_a + cpx #$8020 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0405: +.export test0405: far + ldx #$405 + jsl init_test + rep #$20 + .a16 + lda #$4000 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + adc #$3999 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$7999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0406: +.export test0406: far + ldx #$406 + jsl init_test + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc #$87 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0407: +.export test0407: far + ldx #$407 + jsl init_test + lda #$87 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$ff91 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0408: +.export test0408: far + ldx #$408 + jsl init_test + lda #$87 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc12 + ldx #$1210 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0409: +.export test0409: far + ldx #$409 + jsl init_test + lda #$87 + sta $000201 + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040a: +.export test040a: far + ldx #$40a + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040b: +.export test040b: far + ldx #$40b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$87 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040c: +.export test040c: far + ldx #$40c + jsl init_test + lda #$87 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040d: +.export test040d: far + ldx #$40d + jsl init_test + lda #$87 + sta $7effff + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040e: +.export test040e: far + ldx #$40e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$87 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040f: +.export test040f: far + ldx #$40f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$87 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0410: +.export test0410: far + ldx #$410 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0411: +.export test0411: far + ldx #$411 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$87 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0412: +.export test0412: far + ldx #$412 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$87 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0413: +.export test0413: far + ldx #$413 + jsl init_test + lda #$87 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$0133 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0414: +.export test0414: far + ldx #$414 + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$1232 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0415: +.export test0415: far + ldx #$415 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$87 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0416: +.export test0416: far + ldx #$416 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$87 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0417: +.export test0417: far + ldx #$417 + jsl init_test + lda #$87 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$0300 + rep #$d6 + sep #$29 + .a8 + adc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0418: +.export test0418: far + ldx #$418 + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1230 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0419: +.export test0419: far + ldx #$419 + jsl init_test + lda #$87 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$0300 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041a: +.export test041a: far + ldx #$41a + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041b: +.export test041b: far + ldx #$41b + jsl init_test + lda #$87 + sta $7f02ff + rep #$20 + .a16 + lda #$cc12 + ldx #$0300 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041c: +.export test041c: far + ldx #$41c + jsl init_test + lda #$87 + sta $7f002f + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041d: +.export test041d: far + ldx #$41d + jsl init_test + rep #$20 + .a16 + lda #$cc40 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + adc #$40 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e8 + bne @to_fail + ldx result_a + cpx #$cc80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041e: +.export test041e: far + ldx #$41e + jsl init_test + rep #$20 + .a16 + lda #$cc40 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + adc #$39 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0028 + bne @to_fail + ldx result_a + cpx #$cc79 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041f: +.export test041f: far + ldx #$41f + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc #$9089 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0420: +.export test0420: far + ldx #$420 + jsl init_test + lda #$89 + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$ff91 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0421: +.export test0421: far + ldx #$421 + jsl init_test + lda #$89 + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$1210 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0422: +.export test0422: far + ldx #$422 + jsl init_test + lda #$89 + sta $000201 + lda #$90 + sta $000202 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$89 + bne @to_fail + lda $000202 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0423: +.export test0423: far + ldx #$423 + jsl init_test + lda #$89 + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0424: +.export test0424: far + ldx #$424 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7f1234 + lda #$90 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0425: +.export test0425: far + ldx #$425 + jsl init_test + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0426: +.export test0426: far + ldx #$426 + jsl init_test + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0427: +.export test0427: far + ldx #$427 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0428: +.export test0428: far + ldx #$428 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0429: +.export test0429: far + ldx #$429 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$89 + sta $7f1234 + lda #$90 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042a: +.export test042a: far + ldx #$42a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042b: +.export test042b: far + ldx #$42b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042c: +.export test042c: far + ldx #$42c + jsl init_test + lda #$89 + sta $000134 + lda #$90 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$0133 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$89 + bne @to_fail + lda $000135 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042d: +.export test042d: far + ldx #$42d + jsl init_test + lda #$89 + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$1232 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042e: +.export test042e: far + ldx #$42e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042f: +.export test042f: far + ldx #$42f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0430: +.export test0430: far + ldx #$430 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$0300 + rep #$f7 + sep #$08 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0431: +.export test0431: far + ldx #$431 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1230 + rep #$e7 + sep #$18 + .i8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0432: +.export test0432: far + ldx #$432 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0433: +.export test0433: far + ldx #$433 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0434: +.export test0434: far + ldx #$434 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0435: +.export test0435: far + ldx #$435 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0436: +.export test0436: far + ldx #$436 + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$01 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0088 + bne @to_fail + ldx result_a + cpx #$9999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0437: +.export test0437: far + ldx #$437 + jsl init_test + rep #$20 + .a16 + lda #$1000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$9000 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0048 + bne @to_fail + ldx result_a + cpx #$2000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0438: +.export test0438: far + ldx #$438 + jsl init_test + rep #$20 + .a16 + lda #$1000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$9001 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$1999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0439: +.export test0439: far + ldx #$439 + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc #$89 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043a: +.export test043a: far + ldx #$43a + jsl init_test + lda #$89 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$ff91 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043b: +.export test043b: far + ldx #$43b + jsl init_test + lda #$89 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc90 + ldx #$1210 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043c: +.export test043c: far + ldx #$43c + jsl init_test + lda #$89 + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043d: +.export test043d: far + ldx #$43d + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043e: +.export test043e: far + ldx #$43e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043f: +.export test043f: far + ldx #$43f + jsl init_test + lda #$89 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0440: +.export test0440: far + ldx #$440 + jsl init_test + lda #$89 + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0441: +.export test0441: far + ldx #$441 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0442: +.export test0442: far + ldx #$442 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0443: +.export test0443: far + ldx #$443 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0444: +.export test0444: far + ldx #$444 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0445: +.export test0445: far + ldx #$445 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0446: +.export test0446: far + ldx #$446 + jsl init_test + lda #$89 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0133 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0447: +.export test0447: far + ldx #$447 + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$1232 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0448: +.export test0448: far + ldx #$448 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0449: +.export test0449: far + ldx #$449 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044a: +.export test044a: far + ldx #$44a + jsl init_test + lda #$89 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$0300 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044b: +.export test044b: far + ldx #$44b + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044c: +.export test044c: far + ldx #$44c + jsl init_test + lda #$89 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044d: +.export test044d: far + ldx #$44d + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044e: +.export test044e: far + ldx #$44e + jsl init_test + lda #$89 + sta $7f02ff + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044f: +.export test044f: far + ldx #$44f + jsl init_test + lda #$89 + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0450: +.export test0450: far + ldx #$450 + jsl init_test + rep #$20 + .a16 + lda #$cc00 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$01 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a8 + bne @to_fail + ldx result_a + cpx #$cc99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0451: +.export test0451: far + ldx #$451 + jsl init_test + rep #$20 + .a16 + lda #$cc10 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$90 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0068 + bne @to_fail + ldx result_a + cpx #$cc20 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0452: +.export test0452: far + ldx #$452 + jsl init_test + rep #$20 + .a16 + lda #$cc10 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$91 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0028 + bne @to_fail + ldx result_a + cpx #$cc19 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml success diff --git a/roms/snes-tests/cputest/tests-basic.map b/roms/snes-tests/cputest/tests-basic.map new file mode 100644 index 00000000..b940f304 --- /dev/null +++ b/roms/snes-tests/cputest/tests-basic.map @@ -0,0 +1,2263 @@ +Modules list: +------------- +cputest-basic.o: + CODE Offs=000000 Size=004CB7 Align=00001 Fill=0000 + RODATA Offs=000000 Size=001571 Align=00001 Fill=0000 + BSS Offs=000000 Size=000000 Align=00001 Fill=0000 + DATA Offs=000000 Size=000000 Align=00001 Fill=0000 + ZEROPAGE Offs=000000 Size=000022 Align=00001 Fill=0000 + NULL Offs=000000 Size=000000 Align=00001 Fill=0000 + HEADER Offs=000000 Size=000015 Align=00001 Fill=0000 + ROMINFO Offs=000000 Size=00000B Align=00001 Fill=0000 + VECTORS Offs=000000 Size=000020 Align=00001 Fill=0000 + BANK1 Offs=000000 Size=0072B8 Align=00001 Fill=0000 + BANK2 Offs=000000 Size=0074B8 Align=00001 Fill=0000 + BANK3 Offs=000000 Size=002E44 Align=00001 Fill=0000 + TEST_DATA Offs=000000 Size=000007 Align=00001 Fill=0000 + + +Segment list: +------------- +Name Start End Size Align +---------------------------------------------------- +DATA 000000 000000 000000 00001 +NULL 000000 000000 000000 00001 +ZEROPAGE 000000 000021 000022 00001 +BSS 000200 000200 000000 00001 +CODE 008000 00CCB6 004CB7 00001 +RODATA 00CCB7 00E227 001571 00001 +TEST_DATA 00FFA0 00FFA6 000007 00001 +HEADER 00FFC0 00FFD4 000015 00001 +ROMINFO 00FFD5 00FFDF 00000B 00001 +VECTORS 00FFE0 00FFFF 000020 00001 +BANK1 018000 01F2B7 0072B8 00001 +BANK2 028000 02F4B7 0074B8 00001 +BANK3 038000 03AE43 002E44 00001 + + +Exports list by name: +--------------------- +test0000 008294 LF test0001 00830A LF +test0002 008344 LF test0003 0083A1 LF +test0004 0083FE LF test0005 00844F LF +test0006 0084A4 LF test0007 008509 LF +test0008 008563 LF test0009 0085BA LF +test000a 00861F LF test000b 008684 LF +test000c 0086E9 LF test000d 00874C LF +test000e 0087AF LF test000f 008808 LF +test0010 00885D LF test0011 0088C2 LF +test0012 008927 LF test0013 008981 LF +test0014 0089DB LF test0015 008A35 LF +test0016 008A8F LF test0017 008AE6 LF +test0018 008B3D LF test0019 008B77 LF +test001a 008BB1 LF test001b 008BEB LF +test001c 008C24 LF test001d 008C73 LF +test001e 008CC2 LF test001f 008D07 LF +test0020 008D52 LF test0021 008DA9 LF +test0022 008DF5 LF test0023 008E3E LF +test0024 008E95 LF test0025 008EEC LF +test0026 008F43 LF test0027 008F98 LF +test0028 008FED LF test0029 00903A LF +test002a 009085 LF test002b 0090DC LF +test002c 009133 LF test002d 00917F LF +test002e 0091CB LF test002f 009217 LF +test0030 009263 LF test0031 0092AC LF +test0032 0092F5 LF test0033 00932E LF +test0034 009367 LF test0035 0093A0 LF +test0036 0093DA LF test0037 009437 LF +test0038 009494 LF test0039 0094E5 LF +test003a 00953A LF test003b 00959F LF +test003c 0095F9 LF test003d 009650 LF +test003e 0096B5 LF test003f 00971A LF +test0040 00977F LF test0041 0097E2 LF +test0042 009845 LF test0043 00989E LF +test0044 0098F3 LF test0045 009958 LF +test0046 0099BD LF test0047 009A17 LF +test0048 009A71 LF test0049 009ACB LF +test004a 009B25 LF test004b 009B7C LF +test004c 009BD3 LF test004d 009C0D LF +test004e 009C47 LF test004f 009C80 LF +test0050 009CCF LF test0051 009D1E LF +test0052 009D63 LF test0053 009DAE LF +test0054 009E05 LF test0055 009E51 LF +test0056 009E9A LF test0057 009EF1 LF +test0058 009F48 LF test0059 009F9F LF +test005a 009FF4 LF test005b 00A049 LF +test005c 00A096 LF test005d 00A0E1 LF +test005e 00A138 LF test005f 00A18F LF +test0060 00A1DB LF test0061 00A227 LF +test0062 00A273 LF test0063 00A2BF LF +test0064 00A308 LF test0065 00A351 LF +test0066 00A38A LF test0067 00A3C2 LF +test0068 00A417 LF test0069 00A471 LF +test006a 00A4CA LF test006b 00A51F LF +test006c 00A579 LF test006d 00A5D3 LF +test006e 00A60B LF test006f 00A660 LF +test0070 00A6BA LF test0071 00A713 LF +test0072 00A768 LF test0073 00A7C2 LF +test0074 00A81C LF test0075 00A854 LF +test0076 00A89F LF test0077 00A8EB LF +test0078 00A938 LF test0079 00A983 LF +test007a 00A9CF LF test007b 00AA1B LF +test007c 00AA53 LF test007d 00AA9E LF +test007e 00AAEA LF test007f 00AB37 LF +test0080 00AB82 LF test0081 00ABCE LF +test0082 00AC1A LF test0083 00AC54 LF +test0084 00AC8E LF test0085 00ACC7 LF +test0086 00AD00 LF test0087 00AD55 LF +test0088 00ADAF LF test0089 00AE08 LF +test008a 00AE5D LF test008b 00AEB7 LF +test008c 00AF11 LF test008d 00AF66 LF +test008e 00AFC0 LF test008f 00B019 LF +test0090 00B06E LF test0091 00B0C8 LF +test0092 00B122 LF test0093 00B16D LF +test0094 00B1B9 LF test0095 00B206 LF +test0096 00B251 LF test0097 00B29D LF +test0098 00B2E9 LF test0099 00B334 LF +test009a 00B380 LF test009b 00B3CD LF +test009c 00B418 LF test009d 00B464 LF +test009e 00B4B0 LF test009f 00B520 LF +test00a0 00B58B LF test00a1 00B5FB LF +test00a2 00B666 LF test00a3 00B6A6 LF +test00a4 00B6E6 LF test00a5 00B756 LF +test00a6 00B7C1 LF test00a7 00B801 LF +test00a8 00B871 LF test00a9 00B8DC LF +test00aa 00B91C LF test00ab 00B98C LF +test00ac 00B9F7 LF test00ad 00BA37 LF +test00ae 00BAA7 LF test00af 00BB12 LF +test00b0 00BB52 LF test00b1 00BBC2 LF +test00b2 00BC2D LF test00b3 00BC6D LF +test00b4 00BCDD LF test00b5 00BD48 LF +test00b6 00BD88 LF test00b7 00BE0F LF +test00b8 00BE96 LF test00b9 00BF07 LF +test00ba 00BF3F LF test00bb 00BF77 LF +test00bc 00BFAF LF test00bd 00BFE7 LF +test00be 00C01F LF test00bf 00C057 LF +test00c0 00C08F LF test00c1 00C0C7 LF +test00c2 00C0FF LF test00c3 00C137 LF +test00c4 00C16F LF test00c5 00C1A7 LF +test00c6 00C1DF LF test00c7 00C217 LF +test00c8 00C251 LF test00c9 00C2AE LF +test00ca 00C30B LF test00cb 00C35C LF +test00cc 00C3B1 LF test00cd 00C416 LF +test00ce 00C470 LF test00cf 00C4C7 LF +test00d0 00C52C LF test00d1 00C591 LF +test00d2 00C5F6 LF test00d3 00C659 LF +test00d4 00C6BC LF test00d5 00C715 LF +test00d6 00C76A LF test00d7 00C7CF LF +test00d8 00C834 LF test00d9 00C88E LF +test00da 00C8E8 LF test00db 00C942 LF +test00dc 00C99C LF test00dd 00C9F3 LF +test00de 00CA4A LF test00df 00CA84 LF +test00e0 00CAD9 LF test00e1 00CB33 LF +test00e2 00CB6D LF test00e3 00CBC2 LF +test00e4 00CC1C LF test00e5 00CC56 LF +test00e6 01802E LF test00e7 01808B LF +test00e8 0180DC LF test00e9 018131 LF +test00ea 018196 LF test00eb 0181F0 LF +test00ec 018247 LF test00ed 0182AC LF +test00ee 018311 LF test00ef 018376 LF +test00f0 0183D9 LF test00f1 01843C LF +test00f2 018495 LF test00f3 0184EA LF +test00f4 01854F LF test00f5 0185B4 LF +test00f6 01860E LF test00f7 018668 LF +test00f8 0186C2 LF test00f9 01871C LF +test00fa 018773 LF test00fb 0187CA LF +test00fc 018804 LF test00fd 018859 LF +test00fe 0188B3 LF test00ff 0188ED LF +test0100 018942 LF test0101 01899C LF +test0102 0189D5 LF test0103 018A24 LF +test0104 018A73 LF test0105 018AB8 LF +test0106 018B03 LF test0107 018B5A LF +test0108 018BA6 LF test0109 018BEF LF +test010a 018C46 LF test010b 018C9D LF +test010c 018CF4 LF test010d 018D49 LF +test010e 018D9E LF test010f 018DEB LF +test0110 018E36 LF test0111 018E8D LF +test0112 018EE4 LF test0113 018F30 LF +test0114 018F7C LF test0115 018FC8 LF +test0116 019014 LF test0117 01905D LF +test0118 0190A6 LF test0119 0190DF LF +test011a 01912A LF test011b 019176 LF +test011c 0191AF LF test011d 0191FA LF +test011e 019246 LF test011f 01927F LF +test0120 0192CE LF test0121 01931D LF +test0122 019362 LF test0123 0193AD LF +test0124 019404 LF test0125 019450 LF +test0126 019499 LF test0127 0194F0 LF +test0128 019547 LF test0129 01959E LF +test012a 0195F3 LF test012b 019648 LF +test012c 019695 LF test012d 0196E0 LF +test012e 019737 LF test012f 01978E LF +test0130 0197DA LF test0131 019826 LF +test0132 019872 LF test0133 0198BE LF +test0134 019907 LF test0135 019950 LF +test0136 019989 LF test0137 0199D4 LF +test0138 019A20 LF test0139 019A59 LF +test013a 019AA4 LF test013b 019AF0 LF +test013c 019B28 LF test013d 019B7D LF +test013e 019BD7 LF test013f 019C30 LF +test0140 019C85 LF test0141 019CDF LF +test0142 019D39 LF test0143 019D71 LF +test0144 019DA9 LF test0145 019DE1 LF +test0146 019E36 LF test0147 019E90 LF +test0148 019EE9 LF test0149 019F3E LF +test014a 019F98 LF test014b 019FF2 LF +test014c 01A02A LF test014d 01A062 LF +test014e 01A09A LF test014f 01A0E5 LF +test0150 01A131 LF test0151 01A17E LF +test0152 01A1C9 LF test0153 01A215 LF +test0154 01A261 LF test0155 01A299 LF +test0156 01A2D1 LF test0157 01A309 LF +test0158 01A354 LF test0159 01A3A0 LF +test015a 01A3ED LF test015b 01A438 LF +test015c 01A484 LF test015d 01A4D0 LF +test015e 01A508 LF test015f 01A540 LF +test0160 01A57A LF test0161 01A5D7 LF +test0162 01A634 LF test0163 01A685 LF +test0164 01A6DA LF test0165 01A73F LF +test0166 01A799 LF test0167 01A7F0 LF +test0168 01A855 LF test0169 01A8BA LF +test016a 01A91F LF test016b 01A982 LF +test016c 01A9E5 LF test016d 01AA3E LF +test016e 01AA93 LF test016f 01AAF8 LF +test0170 01AB5D LF test0171 01ABB7 LF +test0172 01AC11 LF test0173 01AC6B LF +test0174 01ACC5 LF test0175 01AD1C LF +test0176 01AD73 LF test0177 01ADAD LF +test0178 01ADE7 LF test0179 01AE20 LF +test017a 01AE6F LF test017b 01AEBE LF +test017c 01AF03 LF test017d 01AF4E LF +test017e 01AFA5 LF test017f 01AFF1 LF +test0180 01B03A LF test0181 01B091 LF +test0182 01B0E8 LF test0183 01B13F LF +test0184 01B194 LF test0185 01B1E9 LF +test0186 01B236 LF test0187 01B281 LF +test0188 01B2D8 LF test0189 01B32F LF +test018a 01B37B LF test018b 01B3C7 LF +test018c 01B413 LF test018d 01B45F LF +test018e 01B4A8 LF test018f 01B4F1 LF +test0190 01B52A LF test0191 01B562 LF +test0192 01B5B7 LF test0193 01B611 LF +test0194 01B66A LF test0195 01B6BF LF +test0196 01B719 LF test0197 01B773 LF +test0198 01B7AB LF test0199 01B7E3 LF +test019a 01B81B LF test019b 01B870 LF +test019c 01B8CA LF test019d 01B923 LF +test019e 01B978 LF test019f 01B9D2 LF +test01a0 01BA2C LF test01a1 01BA64 LF +test01a2 01BA9C LF test01a3 01BAD4 LF +test01a4 01BB1F LF test01a5 01BB6B LF +test01a6 01BBB8 LF test01a7 01BC03 LF +test01a8 01BC4F LF test01a9 01BC9B LF +test01aa 01BCD3 LF test01ab 01BD0B LF +test01ac 01BD43 LF test01ad 01BD8E LF +test01ae 01BDDA LF test01af 01BE27 LF +test01b0 01BE72 LF test01b1 01BEBE LF +test01b2 01BF0A LF test01b3 01BF42 LF +test01b4 01BF7A LF test01b5 01BFEA LF +test01b6 01C05E LF test01b7 01C0B9 LF +test01b8 01C139 LF test01b9 01C1B9 LF +test01ba 01C23D LF test01bb 01C2CE LF +test01bc 01C362 LF test01bd 01C3F6 LF +test01be 01C430 LF test01bf 01C48D LF +test01c0 01C4EA LF test01c1 01C53B LF +test01c2 01C590 LF test01c3 01C5F5 LF +test01c4 01C64F LF test01c5 01C6A6 LF +test01c6 01C70B LF test01c7 01C770 LF +test01c8 01C7D5 LF test01c9 01C838 LF +test01ca 01C89B LF test01cb 01C8F4 LF +test01cc 01C949 LF test01cd 01C9AE LF +test01ce 01CA13 LF test01cf 01CA6D LF +test01d0 01CAC7 LF test01d1 01CB21 LF +test01d2 01CB7B LF test01d3 01CBD2 LF +test01d4 01CC29 LF test01d5 01CC63 LF +test01d6 01CCB8 LF test01d7 01CD12 LF +test01d8 01CD6B LF test01d9 01CDC5 LF +test01da 01CDFF LF test01db 01CE54 LF +test01dc 01CEAE LF test01dd 01CF07 LF +test01de 01CF61 LF test01df 01CF9B LF +test01e0 01CFF8 LF test01e1 01D055 LF +test01e2 01D0A6 LF test01e3 01D0FB LF +test01e4 01D160 LF test01e5 01D1BA LF +test01e6 01D211 LF test01e7 01D276 LF +test01e8 01D2DB LF test01e9 01D340 LF +test01ea 01D3A3 LF test01eb 01D406 LF +test01ec 01D45F LF test01ed 01D4B4 LF +test01ee 01D519 LF test01ef 01D57E LF +test01f0 01D5D8 LF test01f1 01D632 LF +test01f2 01D68C LF test01f3 01D6E6 LF +test01f4 01D73D LF test01f5 01D794 LF +test01f6 01D7CE LF test01f7 01D823 LF +test01f8 01D87D LF test01f9 01D8D6 LF +test01fa 01D930 LF test01fb 01D96A LF +test01fc 01D9BF LF test01fd 01DA19 LF +test01fe 01DA72 LF test01ff 01DACC LF +test0200 01DB05 LF test0201 01DB54 LF +test0202 01DBA3 LF test0203 01DBE8 LF +test0204 01DC33 LF test0205 01DC8A LF +test0206 01DCD6 LF test0207 01DD1F LF +test0208 01DD76 LF test0209 01DDCD LF +test020a 01DE24 LF test020b 01DE79 LF +test020c 01DECE LF test020d 01DF1B LF +test020e 01DF66 LF test020f 01DFBD LF +test0210 01E014 LF test0211 01E060 LF +test0212 01E0AC LF test0213 01E0F8 LF +test0214 01E144 LF test0215 01E18D LF +test0216 01E1D6 LF test0217 01E20F LF +test0218 01E25A LF test0219 01E2A6 LF +test021a 01E2F1 LF test021b 01E33D LF +test021c 01E376 LF test021d 01E3C1 LF +test021e 01E40D LF test021f 01E458 LF +test0220 01E4A4 LF test0221 01E4DD LF +test0222 01E52C LF test0223 01E57B LF +test0224 01E5C0 LF test0225 01E60B LF +test0226 01E662 LF test0227 01E6AE LF +test0228 01E6F7 LF test0229 01E74E LF +test022a 01E7A5 LF test022b 01E7FC LF +test022c 01E851 LF test022d 01E8A6 LF +test022e 01E8F3 LF test022f 01E93E LF +test0230 01E995 LF test0231 01E9EC LF +test0232 01EA38 LF test0233 01EA84 LF +test0234 01EAD0 LF test0235 01EB1C LF +test0236 01EB65 LF test0237 01EBAE LF +test0238 01EBE7 LF test0239 01EC32 LF +test023a 01EC7E LF test023b 01ECC9 LF +test023c 01ED15 LF test023d 01ED4E LF +test023e 01ED99 LF test023f 01EDE5 LF +test0240 01EE30 LF test0241 01EE7C LF +test0242 01EEB4 LF test0243 01EF09 LF +test0244 01EF63 LF test0245 01EFBC LF +test0246 01F011 LF test0247 01F06B LF +test0248 01F0C5 LF test0249 01F0FD LF +test024a 01F152 LF test024b 01F1AC LF +test024c 01F205 LF test024d 01F25A LF +test024e 02802E LF test024f 028088 LF +test0250 0280C0 LF test0251 02810B LF +test0252 028157 LF test0253 0281A4 LF +test0254 0281EF LF test0255 02823B LF +test0256 028287 LF test0257 0282BF LF +test0258 02830A LF test0259 028356 LF +test025a 0283A3 LF test025b 0283EE LF +test025c 02843A LF test025d 028486 LF +test025e 028512 LF test025f 02857C LF +test0260 0285D8 LF test0261 028664 LF +test0262 0286F0 LF test0263 02875A LF +test0264 0287B6 LF test0265 028842 LF +test0266 02887C LF test0267 0288D9 LF +test0268 028936 LF test0269 028987 LF +test026a 0289DC LF test026b 028A41 LF +test026c 028A9B LF test026d 028AF2 LF +test026e 028B57 LF test026f 028BBC LF +test0270 028C21 LF test0271 028C84 LF +test0272 028CE7 LF test0273 028D40 LF +test0274 028D95 LF test0275 028DFA LF +test0276 028E5F LF test0277 028EB9 LF +test0278 028F13 LF test0279 028F6D LF +test027a 028FC7 LF test027b 02901E LF +test027c 029075 LF test027d 0290AF LF +test027e 0290E9 LF test027f 029122 LF +test0280 029171 LF test0281 0291C0 LF +test0282 029205 LF test0283 029250 LF +test0284 0292A7 LF test0285 0292F3 LF +test0286 02933C LF test0287 029393 LF +test0288 0293EA LF test0289 029441 LF +test028a 029496 LF test028b 0294EB LF +test028c 029538 LF test028d 029583 LF +test028e 0295DA LF test028f 029631 LF +test0290 02967D LF test0291 0296C9 LF +test0292 029715 LF test0293 029761 LF +test0294 0297AA LF test0295 0297F3 LF +test0296 02982C LF test0297 029864 LF +test0298 02989D LF test0299 0298F0 LF +test029a 029952 LF test029b 0299D0 LF +test029c 029A4E LF test029d 029A9B LF +test029e 029AE8 LF test029f 029B35 LF +test02a0 029B82 LF test02a1 029BCF LF +test02a2 029C1C LF test02a3 029C69 LF +test02a4 029CB6 LF test02a5 029D03 LF +test02a6 029D50 LF test02a7 029D9D LF +test02a8 029DEA LF test02a9 029E38 LF +test02aa 029E86 LF test02ab 029EDA LF +test02ac 029F32 LF test02ad 029F7A LF +test02ae 029FC2 LF test02af 02A00A LF +test02b0 02A05B LF test02b1 02A0A5 LF +test02b2 02A0F6 LF test02b3 02A140 LF +test02b4 02A191 LF test02b5 02A1DB LF +test02b6 02A229 LF test02b7 02A27E LF +test02b8 02A2E9 LF test02b9 02A333 LF +test02ba 02A36C LF test02bb 02A3A5 LF +test02bc 02A3DE LF test02bd 02A417 LF +test02be 02A452 LF test02bf 02A48A LF +test02c0 02A4DF LF test02c1 02A539 LF +test02c2 02A592 LF test02c3 02A5E7 LF +test02c4 02A641 LF test02c5 02A69B LF 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(cputest-basic.o): +test0450 (cputest-basic.o): +test0451 (cputest-basic.o): +test0452 (cputest-basic.o): + diff --git a/roms/snes-tests/cputest/tests-basic.txt b/roms/snes-tests/cputest/tests-basic.txt new file mode 100644 index 00000000..7360be19 --- /dev/null +++ b/roms/snes-tests/cputest/tests-basic.txt @@ -0,0 +1,3368 @@ +Auto-generated by make_cpu_tests.py + +Test 0000: nop ; test PC wrapping from $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$ea + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 0001: adc #$edcb + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 0002: adc ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($7f1212)=$cb ($7f1213)=$ed + Expected output: A=$0000 X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$cb ($7f1213)=$ed +Test 0003: adc ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$11 E=0 DBR=$7f D=$ff00 ($7f1212)=$cb ($7f1213)=$ed + Expected output: A=$0000 X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$cb ($7f1213)=$ed +Test 0004: adc $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 ($000201)=$cb ($000202)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000201)=$cb ($000202)=$ed +Test 0005: adc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000033)=$cb ($000034)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$cb ($000034)=$ed +Test 0006: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cb ($7f1235)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cb ($7f1235)=$ed +Test 0007: adc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7e ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0008: adc $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0009: adc ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 000a: adc ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 000b: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cb ($7f1235)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cb ($7f1235)=$ed +Test 000c: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 000d: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 000e: adc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000134)=$cb ($000135)=$ed + Expected output: A=$0000 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$cb ($000135)=$ed +Test 000f: adc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$11 E=0 DBR=$7f D=$ffff ($000033)=$cb ($000034)=$ed + Expected output: A=$0000 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$cb ($000034)=$ed +Test 0010: adc [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 0011: adc [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 0012: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$01 E=0 DBR=$7e ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 0013: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$11 E=0 DBR=$7e ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 0014: adc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$01 E=0 DBR=$7e ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 0015: adc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$11 E=0 DBR=$7e ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 0016: adc $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$01 E=0 ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 0017: adc $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$11 E=0 ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 0018: adc #$2000 + Input: A=$6789 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$8789 X=$3456 Y=$5678 P=$c0 E=0 +Test 0019: adc #$8000 + Input: A=$8000 X=$3456 Y=$5678 P=$c6 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$47 E=0 +Test 001a: adc #$e000 + Input: A=$9000 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$7001 X=$3456 Y=$5678 P=$41 E=0 +Test 001b: adc #$ed + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 +Test 001c: adc ($10,x) + Input: A=$1112 X=$ff91 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($7f1212)=$ed + Expected output: A=$1100 X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$ed +Test 001d: adc ($90,x) + Input: A=$1112 X=$1210 Y=$5678 P=$31 E=0 DBR=$7f D=$ff00 ($7f1212)=$ed + Expected output: A=$1100 X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$ed +Test 001e: adc $12,s + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 ($000201)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($000201)=$ed +Test 001f: adc $34 + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$ed +Test 0020: adc [$34] + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$ed +Test 0021: adc $FFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7e ($7effff)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$ed +Test 0022: adc $7EFFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 ($7effff)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$ed +Test 0023: adc ($34),y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 0024: adc ($34),y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 0025: adc ($34) + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$ed +Test 0026: adc ($10,s),y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 0027: adc ($10,s),y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 0028: adc $02,x + Input: A=$1112 X=$0133 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000134)=$ed + Expected output: A=$1100 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$ed +Test 0029: adc $02,x + Input: A=$1112 X=$1232 Y=$5678 P=$31 E=0 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$ed +Test 002a: adc [$34],y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 002b: adc [$34],y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 002c: adc $FFFF,y + Input: A=$1112 X=$3456 Y=$0300 P=$21 E=0 DBR=$7e ($7f02ff)=$ed + Expected output: A=$1100 X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$ed +Test 002d: adc $FFFF,y + Input: A=$1112 X=$3456 Y=$1230 P=$31 E=0 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$ed +Test 002e: adc $FFFF,x + Input: A=$1112 X=$0300 Y=$5678 P=$21 E=0 DBR=$7e ($7f02ff)=$ed + Expected output: A=$1100 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$ed +Test 002f: adc $FFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$31 E=0 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$ed +Test 0030: adc $7EFFFF,x + Input: A=$1112 X=$0300 Y=$5678 P=$21 E=0 ($7f02ff)=$ed + Expected output: A=$1100 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$ed +Test 0031: adc $7EFFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$31 E=0 ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$ed +Test 0032: adc #$20 + Input: A=$1167 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1187 X=$3456 Y=$5678 P=$e0 E=0 +Test 0033: adc #$80 + Input: A=$1180 X=$3456 Y=$5678 P=$e6 E=0 + Expected output: A=$1100 X=$3456 Y=$5678 P=$67 E=0 +Test 0034: adc #$e0 + Input: A=$1190 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$1171 X=$3456 Y=$5678 P=$61 E=0 +Test 0035: and #$ef5c + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 +Test 0036: and ($10,x) + Input: A=$feff X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$5c ($7f1213)=$ef + Expected output: A=$ee5c X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$5c ($7f1213)=$ef +Test 0037: and ($90,x) + Input: A=$feff X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$5c ($7f1213)=$ef + Expected output: A=$ee5c X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$5c ($7f1213)=$ef +Test 0038: and $12,s + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($000201)=$5c ($000202)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($000201)=$5c ($000202)=$ef +Test 0039: and $34 + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$5c ($000034)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($000033)=$5c ($000034)=$ef +Test 003a: and [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$5c ($7f1235)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$5c ($7f1235)=$ef +Test 003b: and $FFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 003c: and $7EFFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 003d: and ($34),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 003e: and ($34),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 003f: and ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$5c ($7f1235)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$5c ($7f1235)=$ef +Test 0040: and ($10,s),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 0041: and ($10,s),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 0042: and $02,x + Input: A=$feff X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$5c ($000135)=$ef + Expected output: A=$ee5c X=$0133 Y=$5678 P=$80 E=0 ($000134)=$5c ($000135)=$ef +Test 0043: and $02,x + Input: A=$feff X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$5c ($000034)=$ef + Expected output: A=$ee5c X=$0032 Y=$0078 P=$90 E=0 ($000033)=$5c ($000034)=$ef +Test 0044: and [$34],y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 0045: and [$34],y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 0046: and $FFFF,y + Input: A=$feff X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 0047: and $FFFF,y + Input: A=$feff X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 0048: and $FFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 0049: and $FFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 004a: and $7EFFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 004b: and $7EFFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 004c: and #$aaaa + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 004d: and #$4300 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$0200 X=$3456 Y=$5678 P=$4d E=0 +Test 004e: and #$df + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 +Test 004f: and ($10,x) + Input: A=$12fe X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$df + Expected output: A=$12de X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$df +Test 0050: and ($90,x) + Input: A=$12fe X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$df + Expected output: A=$12de X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$df +Test 0051: and $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($000201)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$df +Test 0052: and $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$df +Test 0053: and [$34] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$df +Test 0054: and $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$df +Test 0055: and $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$df +Test 0056: and ($34),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 0057: and ($34),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 0058: and ($34) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$df +Test 0059: and ($10,s),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 005a: and ($10,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 005b: and $02,x + Input: A=$12fe X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$df + Expected output: A=$12de X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$df +Test 005c: and $02,x + Input: A=$12fe X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$df +Test 005d: and [$34],y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 005e: and [$34],y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 005f: and $FFFF,y + Input: A=$12fe X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$df + Expected output: A=$12de X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$df +Test 0060: and $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$df +Test 0061: and $FFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$df + Expected output: A=$12de X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$df +Test 0062: and $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$df +Test 0063: and $7EFFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$df + Expected output: A=$12de X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$df +Test 0064: and $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$df +Test 0065: and #$aa + Input: A=$5555 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$5500 X=$3456 Y=$5678 P=$22 E=0 +Test 0066: asl a + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 0067: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 0068: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0069: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 006a: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 006b: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 006c: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 006d: asl a + Input: A=$4111 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8222 X=$3456 Y=$5678 P=$cc E=0 +Test 006e: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$22 ($000034)=$82 +Test 006f: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$11 ($7f0000)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$22 ($7f0000)=$82 +Test 0070: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$11 ($000135)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$22 ($000135)=$82 +Test 0071: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$22 ($000034)=$82 +Test 0072: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$11 ($7f0300)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$22 ($7f0300)=$82 +Test 0073: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$11 ($7f0030)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$22 ($7f0030)=$82 +Test 0074: asl a + Input: A=$1280 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 0075: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 0076: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 0077: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 0078: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 0079: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 007a: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 007b: asl a + Input: A=$1241 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1282 X=$3456 Y=$5678 P=$ec E=0 +Test 007c: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$82 +Test 007d: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$82 +Test 007e: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$82 +Test 007f: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$82 +Test 0080: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$82 +Test 0081: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$82 +Test 0082: bit #$1234 + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$9377 X=$3456 Y=$5678 P=$cd E=0 +Test 0083: bit #$aaaa + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 +Test 0084: bit #$aa + Input: A=$0056 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$0056 X=$3456 Y=$5678 P=$20 E=0 +Test 0085: bit #$aa + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 +Test 0086: bit $34 + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$52 + Expected output: A=$9377 X=$3456 Y=$5678 P=$4d E=0 ($000033)=$34 ($000034)=$52 +Test 0087: bit $FFFF + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$52 + Expected output: A=$9377 X=$3456 Y=$5678 P=$4d E=0 ($7effff)=$34 ($7f0000)=$52 +Test 0088: bit $02,x + Input: A=$9377 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$52 + Expected output: A=$9377 X=$0133 Y=$5678 P=$4d E=0 ($000134)=$34 ($000135)=$52 +Test 0089: bit $02,x + Input: A=$9377 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$52 + Expected output: A=$9377 X=$0032 Y=$0078 P=$5d E=0 ($000033)=$34 ($000034)=$52 +Test 008a: bit $FFFF,x + Input: A=$9377 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$52 + Expected output: A=$9377 X=$0300 Y=$5678 P=$4d E=0 ($7f02ff)=$34 ($7f0300)=$52 +Test 008b: bit $FFFF,x + Input: A=$9377 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$52 + Expected output: A=$9377 X=$0030 Y=$0078 P=$5d E=0 ($7f002f)=$34 ($7f0030)=$52 +Test 008c: bit $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$82 E=0 ($000033)=$aa ($000034)=$aa +Test 008d: bit $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$82 E=0 ($7effff)=$aa ($7f0000)=$aa +Test 008e: bit $02,x + Input: A=$5555 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$aa ($000135)=$aa + Expected output: A=$5555 X=$0133 Y=$5678 P=$82 E=0 ($000134)=$aa ($000135)=$aa +Test 008f: bit $02,x + Input: A=$5555 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$0032 Y=$0078 P=$92 E=0 ($000033)=$aa ($000034)=$aa +Test 0090: bit $FFFF,x + Input: A=$5555 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$aa ($7f0300)=$aa + Expected output: A=$5555 X=$0300 Y=$5678 P=$82 E=0 ($7f02ff)=$aa ($7f0300)=$aa +Test 0091: bit $FFFF,x + Input: A=$5555 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$aa ($7f0030)=$aa + Expected output: A=$5555 X=$0030 Y=$0078 P=$92 E=0 ($7f002f)=$aa ($7f0030)=$aa +Test 0092: bit $34 + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$3456 Y=$5678 P=$60 E=0 ($000033)=$52 +Test 0093: bit $FFFF + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$52 + Expected output: A=$0093 X=$3456 Y=$5678 P=$60 E=0 ($7effff)=$52 +Test 0094: bit $02,x + Input: A=$0093 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$52 + Expected output: A=$0093 X=$0133 Y=$5678 P=$60 E=0 ($000134)=$52 +Test 0095: bit $02,x + Input: A=$0093 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$0032 Y=$0078 P=$70 E=0 ($000033)=$52 +Test 0096: bit $FFFF,x + Input: A=$0093 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$52 + Expected output: A=$0093 X=$0300 Y=$5678 P=$60 E=0 ($7f02ff)=$52 +Test 0097: bit $FFFF,x + Input: A=$0093 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$52 + Expected output: A=$0093 X=$0030 Y=$0078 P=$70 E=0 ($7f002f)=$52 +Test 0098: bit $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$a2 E=0 ($000033)=$aa +Test 0099: bit $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$a2 E=0 ($7effff)=$aa +Test 009a: bit $02,x + Input: A=$0055 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$aa + Expected output: A=$0055 X=$0133 Y=$5678 P=$a2 E=0 ($000134)=$aa +Test 009b: bit $02,x + Input: A=$0055 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0032 Y=$0078 P=$b2 E=0 ($000033)=$aa +Test 009c: bit $FFFF,x + Input: A=$0055 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$aa + Expected output: A=$0055 X=$0300 Y=$5678 P=$a2 E=0 ($7f02ff)=$aa +Test 009d: bit $FFFF,x + Input: A=$0055 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$aa + Expected output: A=$0055 X=$0030 Y=$0078 P=$b2 E=0 ($7f002f)=$aa +Test 009e: bra +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$80 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 009f: bra -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$80 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a0: bcc +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$90 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a1: bcc -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$90 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a2: bcc @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Additional initialization or checks are performed - see assembly +Test 00a3: bcs @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a4: bne +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$d0 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a5: bne -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$d0 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00a6: bne @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00a7: beq +127 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effc0)=$f0 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00a8: beq -128 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7f0040)=$f0 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00a9: beq @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00aa: bpl +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$10 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00ab: bpl -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$10 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00ac: bpl @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00ad: bmi +127 + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 ($7effc0)=$30 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00ae: bmi -128 + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 ($7f0040)=$30 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00af: bmi @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00b0: bvc +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$50 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00b1: bvc -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$50 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00b2: bvc @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00b3: bvs +127 + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 ($7effc0)=$70 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00b4: bvs -128 + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 ($7f0040)=$70 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00b5: bvs @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00b6: brk + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=0 ($7e8000)=$00 ($7e8001)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$07 E=0 S=01eb ($0001ef)=$7e ($0001ed)=$02 ($0001ee)=$80 ($0001ec)=$0b + Additional initialization or checks are performed - see assembly +Test 00b7: cop #$DB + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=0 ($7e8000)=$02 ($7e8001)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$07 E=0 S=01eb ($0001ef)=$7e ($0001ed)=$02 ($0001ee)=$80 ($0001ec)=$0b + Additional initialization or checks are performed - see assembly +Test 00b8: BRL +$7FFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7ef000)=$82 ($7ef001)=$ff ($7ef002)=$7f ($7ef003)=$db ($7f7002)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00b9: clc + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fe E=0 +Test 00ba: clc + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 00bb: cld + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$f7 E=0 +Test 00bc: cld + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 00bd: cli + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fb E=0 +Test 00be: cli + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 00bf: clv + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$bf E=0 +Test 00c0: clv + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 00c1: sec + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$01 E=0 +Test 00c2: sec + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 00c3: sed + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$08 E=0 +Test 00c4: sed + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 00c5: sei + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$04 E=0 +Test 00c6: sei + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 00c7: cmp #$abcd + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 +Test 00c8: cmp ($10,x) + Input: A=$abcd X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcd X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 00c9: cmp ($90,x) + Input: A=$abcd X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcd X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 00ca: cmp $12,s + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 ($000201)=$cd ($000202)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($000201)=$cd ($000202)=$ab +Test 00cb: cmp $34 + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 00cc: cmp [$34] + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 00cd: cmp $FFFF + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00ce: cmp $7EFFFF + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00cf: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00d0: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00d1: cmp ($34) + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 00d2: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00d3: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00d4: cmp $02,x + Input: A=$abcd X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$cd ($000135)=$ab + Expected output: A=$abcd X=$0133 Y=$5678 P=$03 E=0 ($000134)=$cd ($000135)=$ab +Test 00d5: cmp $02,x + Input: A=$abcd X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcd X=$0032 Y=$0078 P=$13 E=0 ($000033)=$cd ($000034)=$ab +Test 00d6: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00d7: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00d8: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00d9: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00da: cmp $FFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00db: cmp $FFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00dc: cmp $7EFFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00dd: cmp $7EFFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00de: cpx #$abcd + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 +Test 00df: cpx $34 + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 00e0: cpx $FFFF + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00e1: cpy #$abcd + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 +Test 00e2: cpy $34 + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 00e3: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00e4: cmp #$abcd + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 +Test 00e5: cmp ($10,x) + Input: A=$abcc X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcc X=$ff91 Y=$5678 P=$cc E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 00e6: cmp ($90,x) + Input: A=$abcc X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcc X=$0010 Y=$0078 P=$dc E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 00e7: cmp $12,s + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 ($000201)=$cd ($000202)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($000201)=$cd ($000202)=$ab +Test 00e8: cmp $34 + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 00e9: cmp [$34] + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 00ea: cmp $FFFF + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00eb: cmp $7EFFFF + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00ec: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00ed: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00ee: cmp ($34) + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 00ef: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00f0: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00f1: cmp $02,x + Input: A=$abcc X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$cd ($000135)=$ab + Expected output: A=$abcc X=$0133 Y=$5678 P=$cc E=0 ($000134)=$cd ($000135)=$ab +Test 00f2: cmp $02,x + Input: A=$abcc X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcc X=$0032 Y=$0078 P=$dc E=0 ($000033)=$cd ($000034)=$ab +Test 00f3: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 00f4: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 00f5: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$3456 Y=$0300 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00f6: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0056 Y=$0030 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00f7: cmp $FFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00f8: cmp $FFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00f9: cmp $7EFFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 00fa: cmp $7EFFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 00fb: cpx #$abcd + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 +Test 00fc: cpx $34 + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 00fd: cpx $FFFF + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 00fe: cpy #$abcd + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 +Test 00ff: cpy $34 + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 0100: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0101: cmp #$cd + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 +Test 0102: cmp ($10,x) + Input: A=$abcd X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$cd + Expected output: A=$abcd X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$cd +Test 0103: cmp ($90,x) + Input: A=$abcd X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$cd + Expected output: A=$abcd X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$cd +Test 0104: cmp $12,s + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 ($000201)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($000201)=$cd +Test 0105: cmp $34 + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($000033)=$cd +Test 0106: cmp [$34] + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$cd +Test 0107: cmp $FFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$cd +Test 0108: cmp $7EFFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$cd +Test 0109: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 010a: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 010b: cmp ($34) + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$cd +Test 010c: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 010d: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 010e: cmp $02,x + Input: A=$abcd X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$cd + Expected output: A=$abcd X=$0133 Y=$5678 P=$23 E=0 ($000134)=$cd +Test 010f: cmp $02,x + Input: A=$abcd X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$0032 Y=$0078 P=$33 E=0 ($000033)=$cd +Test 0110: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 0111: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 0112: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcd X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$cd +Test 0113: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$cd +Test 0114: cmp $FFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcd X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$cd +Test 0115: cmp $FFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$cd +Test 0116: cmp $7EFFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$cd + Expected output: A=$abcd X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$cd +Test 0117: cmp $7EFFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$cd +Test 0118: cpx #$cd + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 +Test 0119: cpx $34 + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 ($000033)=$cd +Test 011a: cpx $FFFF + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 ($7effff)=$cd +Test 011b: cpy #$cd + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 +Test 011c: cpy $34 + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 ($000033)=$cd +Test 011d: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 ($7effff)=$cd +Test 011e: cmp #$cd + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 +Test 011f: cmp ($10,x) + Input: A=$abcc X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$cd + Expected output: A=$abcc X=$ff91 Y=$5678 P=$ec E=0 ($7f1212)=$cd +Test 0120: cmp ($90,x) + Input: A=$abcc X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$cd + Expected output: A=$abcc X=$0010 Y=$0078 P=$fc E=0 ($7f1212)=$cd +Test 0121: cmp $12,s + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 ($000201)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($000201)=$cd +Test 0122: cmp $34 + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($000033)=$cd +Test 0123: cmp [$34] + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7f1234)=$cd +Test 0124: cmp $FFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$cd +Test 0125: cmp $7EFFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$cd +Test 0126: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 0127: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 0128: cmp ($34) + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7f1234)=$cd +Test 0129: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 012a: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 012b: cmp $02,x + Input: A=$abcc X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$cd + Expected output: A=$abcc X=$0133 Y=$5678 P=$ec E=0 ($000134)=$cd +Test 012c: cmp $02,x + Input: A=$abcc X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$0032 Y=$0078 P=$fc E=0 ($000033)=$cd +Test 012d: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 012e: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 012f: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcc X=$3456 Y=$0300 P=$ec E=0 ($7f02ff)=$cd +Test 0130: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0056 Y=$0030 P=$fc E=0 ($7f002f)=$cd +Test 0131: cmp $FFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcc X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$cd +Test 0132: cmp $FFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$cd +Test 0133: cmp $7EFFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$cd + Expected output: A=$abcc X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$cd +Test 0134: cmp $7EFFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$cd +Test 0135: cpx #$cd + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 +Test 0136: cpx $34 + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 ($000033)=$cd +Test 0137: cpx $FFFF + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 ($7effff)=$cd +Test 0138: cpy #$cd + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 +Test 0139: cpy $34 + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 ($000033)=$cd +Test 013a: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 ($7effff)=$cd +Test 013b: dec a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 013c: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$00 ($000034)=$00 +Test 013d: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 013e: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$02 E=0 ($000134)=$00 ($000135)=$00 +Test 013f: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$12 E=0 ($000033)=$00 ($000034)=$00 +Test 0140: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0141: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0142: dex + Input: A=$1234 X=$0001 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 +Test 0143: dey + Input: A=$1234 X=$3456 Y=$0001 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 +Test 0144: dec a + Input: A=$0000 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$ffff X=$3456 Y=$5678 P=$cd E=0 +Test 0145: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$ff ($000034)=$ff +Test 0146: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$ff ($7f0000)=$ff +Test 0147: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cd E=0 ($000134)=$ff ($000135)=$ff +Test 0148: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dd E=0 ($000033)=$ff ($000034)=$ff +Test 0149: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cd E=0 ($7f02ff)=$ff ($7f0300)=$ff +Test 014a: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dd E=0 ($7f002f)=$ff ($7f0030)=$ff +Test 014b: dex + Input: A=$1234 X=$0000 Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$ffff Y=$5678 P=$cd E=0 +Test 014c: dey + Input: A=$1234 X=$3456 Y=$0000 P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$ffff P=$cd E=0 +Test 014d: dec a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 +Test 014e: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$00 +Test 014f: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$00 +Test 0150: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$22 E=0 ($000134)=$00 +Test 0151: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=0 ($000033)=$00 +Test 0152: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$00 +Test 0153: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=0 ($7f002f)=$00 +Test 0154: dex + Input: A=$1234 X=$0001 Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 +Test 0155: dey + Input: A=$1234 X=$3456 Y=$0001 P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 +Test 0156: dec a + Input: A=$1200 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$12ff X=$3456 Y=$5678 P=$ed E=0 +Test 0157: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$ff +Test 0158: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$ff +Test 0159: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ed E=0 ($000134)=$ff +Test 015a: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=0 ($000033)=$ff +Test 015b: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ed E=0 ($7f02ff)=$ff +Test 015c: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=0 ($7f002f)=$ff +Test 015d: dex + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$00ff Y=$0078 P=$dd E=0 +Test 015e: dey + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$00ff P=$dd E=0 +Test 015f: eor #$6f8c + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 +Test 0160: eor ($10,x) + Input: A=$feff X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$8c ($7f1213)=$6f + Expected output: A=$9173 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$8c ($7f1213)=$6f +Test 0161: eor ($90,x) + Input: A=$feff X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$8c ($7f1213)=$6f + Expected output: A=$9173 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$8c ($7f1213)=$6f +Test 0162: eor $12,s + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($000201)=$8c ($000202)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$8c ($000202)=$6f +Test 0163: eor $34 + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$8c ($000034)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$8c ($000034)=$6f +Test 0164: eor [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8c ($7f1235)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$8c ($7f1235)=$6f +Test 0165: eor $FFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 0166: eor $7EFFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 0167: eor ($34),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 0168: eor ($34),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 0169: eor ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8c ($7f1235)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$8c ($7f1235)=$6f +Test 016a: eor ($10,s),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 016b: eor ($10,s),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 016c: eor $02,x + Input: A=$feff X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$8c ($000135)=$6f + Expected output: A=$9173 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$8c ($000135)=$6f +Test 016d: eor $02,x + Input: A=$feff X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$8c ($000034)=$6f + Expected output: A=$9173 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$8c ($000034)=$6f +Test 016e: eor [$34],y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 016f: eor [$34],y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 0170: eor $FFFF,y + Input: A=$feff X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 0171: eor $FFFF,y + Input: A=$feff X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 0172: eor $FFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 0173: eor $FFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 0174: eor $7EFFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 0175: eor $7EFFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 0176: eor #$aaaa + Input: A=$aaaa X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 0177: eor #$4334 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$5100 X=$3456 Y=$5678 P=$4d E=0 +Test 0178: eor #$6f + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 +Test 0179: eor ($10,x) + Input: A=$12fe X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$6f + Expected output: A=$1291 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$6f +Test 017a: eor ($90,x) + Input: A=$12fe X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$6f + Expected output: A=$1291 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$6f +Test 017b: eor $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($000201)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$6f +Test 017c: eor $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$6f +Test 017d: eor [$34] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$6f +Test 017e: eor $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$6f +Test 017f: eor $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$6f +Test 0180: eor ($34),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0181: eor ($34),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 0182: eor ($34) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$6f +Test 0183: eor ($10,s),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0184: eor ($10,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 0185: eor $02,x + Input: A=$12fe X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$6f + Expected output: A=$1291 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$6f +Test 0186: eor $02,x + Input: A=$12fe X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$6f +Test 0187: eor [$34],y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0188: eor [$34],y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 0189: eor $FFFF,y + Input: A=$12fe X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$6f + Expected output: A=$1291 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$6f +Test 018a: eor $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$6f +Test 018b: eor $FFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$6f + Expected output: A=$1291 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$6f +Test 018c: eor $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$6f +Test 018d: eor $7EFFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$6f + Expected output: A=$1291 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$6f +Test 018e: eor $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$6f +Test 018f: eor #$aa + Input: A=$aaaa X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$22 E=0 +Test 0190: inc a + Input: A=$ffff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 0191: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$00 ($000034)=$00 +Test 0192: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$ff ($7f0000)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0193: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$ff ($000135)=$ff + Expected output: A=$1234 X=$0133 Y=$5678 P=$02 E=0 ($000134)=$00 ($000135)=$00 +Test 0194: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$ff + Expected output: A=$1234 X=$0032 Y=$0078 P=$12 E=0 ($000033)=$00 ($000034)=$00 +Test 0195: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$ff ($7f0300)=$ff + Expected output: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0196: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$ff ($7f0030)=$ff + Expected output: A=$1234 X=$0030 Y=$0078 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0197: inx + Input: A=$1234 X=$ffff Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 +Test 0198: iny + Input: A=$1234 X=$3456 Y=$ffff P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 +Test 0199: inc a + Input: A=$7fff X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cd E=0 +Test 019a: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$00 ($000034)=$80 +Test 019b: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$ff ($7f0000)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$00 ($7f0000)=$80 +Test 019c: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$ff ($000135)=$7f + Expected output: A=$1234 X=$0133 Y=$5678 P=$cd E=0 ($000134)=$00 ($000135)=$80 +Test 019d: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$7f + Expected output: A=$1234 X=$0032 Y=$0078 P=$dd E=0 ($000033)=$00 ($000034)=$80 +Test 019e: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$ff ($7f0300)=$7f + Expected output: A=$1234 X=$0300 Y=$5678 P=$cd E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 019f: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$ff ($7f0030)=$7f + Expected output: A=$1234 X=$0030 Y=$0078 P=$dd E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 01a0: inx + Input: A=$1234 X=$7fff Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cd E=0 +Test 01a1: iny + Input: A=$1234 X=$3456 Y=$7fff P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cd E=0 +Test 01a2: inc a + Input: A=$12ff X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 +Test 01a3: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$00 +Test 01a4: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$00 +Test 01a5: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$ff + Expected output: A=$1234 X=$0133 Y=$5678 P=$22 E=0 ($000134)=$00 +Test 01a6: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=0 ($000033)=$00 +Test 01a7: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$ff + Expected output: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$00 +Test 01a8: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$ff + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=0 ($7f002f)=$00 +Test 01a9: inx + Input: A=$1234 X=$00ff Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 +Test 01aa: iny + Input: A=$1234 X=$3456 Y=$00ff P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 +Test 01ab: inc a + Input: A=$127f X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1280 X=$3456 Y=$5678 P=$ed E=0 +Test 01ac: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$80 +Test 01ad: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$80 +Test 01ae: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$7f + Expected output: A=$1234 X=$0133 Y=$5678 P=$ed E=0 ($000134)=$80 +Test 01af: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=0 ($000033)=$80 +Test 01b0: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$7f + Expected output: A=$1234 X=$0300 Y=$5678 P=$ed E=0 ($7f02ff)=$80 +Test 01b1: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$7f + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=0 ($7f002f)=$80 +Test 01b2: inx + Input: A=$1234 X=$007f Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0080 Y=$0078 P=$dd E=0 +Test 01b3: iny + Input: A=$1234 X=$3456 Y=$007f P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0080 P=$dd E=0 +Test 01b4: jmp $8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$4c ($7e7001)=$00 ($7e7002)=$80 ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 01b5: jmp ($FFA2) + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$6c ($7e7001)=$a2 ($7e7002)=$ff ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 01b6: jml [$FFA4] + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 01b7: jmp ($F000,x) + Input: A=$1234 X=$6000 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$7c ($7e7001)=$00 ($7e7002)=$f0 ($7e7003)=$db ($7e5000)=$00 ($7e5001)=$80 + Expected output: A=$1234 X=$6000 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 01b8: jmp ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$10 E=0 DBR=$7f ($7e7000)=$7c ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$10 E=0 + Additional initialization or checks are performed - see assembly +Test 01b9: jsr $8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$20 ($7e7001)=$00 ($7e7002)=$80 ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 01ba: jsl $FE8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f7000)=$22 ($7f7001)=$00 ($7f7002)=$80 ($7f7003)=$7e ($7f7004)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ec ($0001ed)=$03 ($0001ee)=$70 ($0001ef)=$7f + Additional initialization or checks are performed - see assembly +Test 01bb: jsr ($F000,x) + Input: A=$1234 X=$6000 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$fc ($7e7001)=$00 ($7e7002)=$f0 ($7e7003)=$db ($7e5000)=$00 ($7e5001)=$80 + Expected output: A=$1234 X=$6000 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 01bc: jsr ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$10 E=0 DBR=$7f ($7e7000)=$fc ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$10 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 01bd: lda #$8000 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 +Test 01be: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($7f1212)=$00 ($7f1213)=$80 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 01bf: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$12 E=0 DBR=$7f D=$ff00 ($7f1212)=$00 ($7f1213)=$80 + Expected output: A=$8000 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 01c0: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000201)=$00 ($000202)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$00 ($000202)=$80 +Test 01c1: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 01c2: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 ($7f1235)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 01c3: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 01c4: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 01c5: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 01c6: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 01c7: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 ($7f1235)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 01c8: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 01c9: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 01ca: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$8000 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 01cb: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$8000 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$00 ($000034)=$80 +Test 01cc: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 01cd: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 01ce: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 01cf: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$12 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 01d0: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 01d1: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$12 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 01d2: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 01d3: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 01d4: ldx #$8000 + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 +Test 01d5: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 01d6: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 01d7: ldx $02,y + Input: A=$1234 X=$1234 Y=$0133 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$8000 Y=$0133 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 01d8: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$0300 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$8000 Y=$0300 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 01d9: ldy #$8000 + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 +Test 01da: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 01db: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 01dc: ldy $02,x + Input: A=$1234 X=$0133 Y=$1234 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$8000 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 01dd: ldy $FFFF,x + Input: A=$1234 X=$0300 Y=$1234 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$8000 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 01de: lda #$00 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 +Test 01df: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$00 ($7f1213)=$00 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$4f E=0 ($7f1212)=$00 ($7f1213)=$00 +Test 01e0: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$00 ($7f1213)=$00 + Expected output: A=$0000 X=$0010 Y=$0078 P=$5f E=0 ($7f1212)=$00 ($7f1213)=$00 +Test 01e1: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$00 ($000202)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($000201)=$00 ($000202)=$00 +Test 01e2: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 01e3: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 ($7f1235)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7f1234)=$00 ($7f1235)=$00 +Test 01e4: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 01e5: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 01e6: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 01e7: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 01e8: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 ($7f1235)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7f1234)=$00 ($7f1235)=$00 +Test 01e9: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 01ea: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 01eb: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$0000 X=$0133 Y=$5678 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 01ec: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$0000 X=$0032 Y=$0078 P=$5f E=0 ($000033)=$00 ($000034)=$00 +Test 01ed: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 01ee: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 01ef: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$3456 Y=$0300 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01f0: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0056 Y=$0030 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 01f1: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$0300 Y=$5678 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01f2: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0030 Y=$0078 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 01f3: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$0300 Y=$5678 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01f4: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0030 Y=$0078 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 01f5: ldx #$00 + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 +Test 01f6: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 01f7: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 01f8: ldx $02,y + Input: A=$1234 X=$1234 Y=$0133 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0000 Y=$0133 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 01f9: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0000 Y=$0300 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01fa: ldy #$00 + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 +Test 01fb: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 01fc: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 01fd: ldy $02,x + Input: A=$1234 X=$0133 Y=$1234 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$0000 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 01fe: ldy $FFFF,x + Input: A=$1234 X=$0300 Y=$1234 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$0000 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01ff: lda #$80 + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 +Test 0200: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($7f1212)=$80 + Expected output: A=$1280 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$80 +Test 0201: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$32 E=0 DBR=$7f D=$ff00 ($7f1212)=$80 + Expected output: A=$1280 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$80 +Test 0202: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000201)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$80 +Test 0203: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$80 +Test 0204: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$80 +Test 0205: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$80 +Test 0206: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$80 +Test 0207: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 0208: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 0209: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$80 +Test 020a: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 020b: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 020c: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1280 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$80 +Test 020d: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$32 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$80 +Test 020e: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 020f: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 0210: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$22 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1280 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$80 +Test 0211: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$32 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$80 +Test 0212: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$22 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1280 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$80 +Test 0213: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$32 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$80 +Test 0214: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$80 + Expected output: A=$1280 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$80 +Test 0215: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$32 E=0 ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$80 +Test 0216: ldx #$80 + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 +Test 0217: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 ($000033)=$80 +Test 0218: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 ($7effff)=$80 +Test 0219: ldx $02,y + Input: A=$1234 X=$1234 Y=$1232 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0032 P=$90 E=0 ($000033)=$80 +Test 021a: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$12 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0080 Y=$0030 P=$90 E=0 ($7f002f)=$80 +Test 021b: ldy #$80 + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 +Test 021c: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 ($000033)=$80 +Test 021d: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 ($7effff)=$80 +Test 021e: ldy $02,x + Input: A=$1234 X=$1232 Y=$1234 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0080 P=$90 E=0 ($000033)=$80 +Test 021f: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$12 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0080 P=$90 E=0 ($7f002f)=$80 +Test 0220: lda #$00 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 +Test 0221: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$00 + Expected output: A=$1200 X=$ff91 Y=$5678 P=$6f E=0 ($7f1212)=$00 +Test 0222: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$00 + Expected output: A=$1200 X=$0010 Y=$0078 P=$7f E=0 ($7f1212)=$00 +Test 0223: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($000201)=$00 +Test 0224: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($000033)=$00 +Test 0225: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7f1234)=$00 +Test 0226: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7effff)=$00 +Test 0227: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7effff)=$00 +Test 0228: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 0229: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 022a: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7f1234)=$00 +Test 022b: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 022c: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 022d: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$00 + Expected output: A=$1200 X=$0133 Y=$5678 P=$6f E=0 ($000134)=$00 +Test 022e: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$0032 Y=$0078 P=$7f E=0 ($000033)=$00 +Test 022f: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 0230: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 0231: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1200 X=$3456 Y=$0300 P=$6f E=0 ($7f02ff)=$00 +Test 0232: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0056 Y=$0030 P=$7f E=0 ($7f002f)=$00 +Test 0233: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1200 X=$0300 Y=$5678 P=$6f E=0 ($7f02ff)=$00 +Test 0234: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=0 ($7f002f)=$00 +Test 0235: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 + Expected output: A=$1200 X=$0300 Y=$5678 P=$6f E=0 ($7f02ff)=$00 +Test 0236: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=0 ($7f002f)=$00 +Test 0237: ldx #$00 + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 +Test 0238: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 ($000033)=$00 +Test 0239: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 ($7effff)=$00 +Test 023a: ldx $02,y + Input: A=$1234 X=$1234 Y=$1232 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0032 P=$5f E=0 ($000033)=$00 +Test 023b: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0000 Y=$0030 P=$5f E=0 ($7f002f)=$00 +Test 023c: ldy #$00 + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 +Test 023d: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 ($000033)=$00 +Test 023e: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 ($7effff)=$00 +Test 023f: ldy $02,x + Input: A=$1234 X=$1232 Y=$1234 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0000 P=$5f E=0 ($000033)=$00 +Test 0240: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$df E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0000 P=$5f E=0 ($7f002f)=$00 +Test 0241: lsr a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 0242: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 0243: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0244: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 0245: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 0246: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0247: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0248: lsr a + Input: A=$4222 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$2111 X=$3456 Y=$5678 P=$4c E=0 +Test 0249: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$4c E=0 ($000033)=$11 ($000034)=$21 +Test 024a: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$22 ($7f0000)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$4c E=0 ($7effff)=$11 ($7f0000)=$21 +Test 024b: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$22 ($000135)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$4c E=0 ($000134)=$11 ($000135)=$21 +Test 024c: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$5c E=0 ($000033)=$11 ($000034)=$21 +Test 024d: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$22 ($7f0300)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$4c E=0 ($7f02ff)=$11 ($7f0300)=$21 +Test 024e: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$22 ($7f0030)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$5c E=0 ($7f002f)=$11 ($7f0030)=$21 +Test 024f: lsr a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 0250: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 0251: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 0252: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 0253: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 0254: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 0255: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 0256: lsr a + Input: A=$1242 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1221 X=$3456 Y=$5678 P=$6c E=0 +Test 0257: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$6c E=0 ($000033)=$21 +Test 0258: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$6c E=0 ($7effff)=$21 +Test 0259: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$6c E=0 ($000134)=$21 +Test 025a: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$7c E=0 ($000033)=$21 +Test 025b: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$6c E=0 ($7f02ff)=$21 +Test 025c: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$7c E=0 ($7f002f)=$21 +Test 025d: mvn #$7e, #$7f + Input: A=$0003 X=$ffff Y=$fffe P=$00 E=0 ($7effff)=$21 ($7e0000)=$22 ($7e0001)=$23 ($7e0002)=$24 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$0003 Y=$0002 P=$00 E=0 DBR=7f ($7ffffe)=$21 ($7fffff)=$22 ($7f0000)=$23 ($7f0001)=$24 ($7f0002)=$99 +Test 025e: mvn #$7f, #$7f + Input: A=$01ff X=$0005 Y=$0000 P=$ef E=0 ($7f0005)=$31 ($7f0204)=$32 ($7f0200)=$99 + Expected output: A=$ffff X=$0205 Y=$0200 P=$ef E=0 DBR=7f ($7f0000)=$31 ($7f01ff)=$32 ($7f0200)=$99 +Test 025f: mvn #$7f, #$7f + Input: A=$01ff X=$0000 Y=$0002 P=$00 E=0 ($7f0000)=$41 ($7f0001)=$42 + Expected output: A=$ffff X=$0200 Y=$0202 P=$00 E=0 DBR=7f ($7f0200)=$41 ($7f0201)=$42 +Test 0260: mvn #$7e, #$7f + Input: A=$0003 X=$05ff Y=$05fe P=$10 E=0 ($7e00ff)=$51 ($7e0000)=$52 ($7e0001)=$53 ($7e0002)=$54 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$0003 Y=$0002 P=$10 E=0 DBR=7f ($7f00fe)=$51 ($7f00ff)=$52 ($7f0000)=$53 ($7f0001)=$54 ($7f0002)=$99 +Test 0261: mvp #$7e, #$7f + Input: A=$0003 X=$0002 Y=$0001 P=$00 E=0 ($7effff)=$21 ($7e0000)=$22 ($7e0001)=$23 ($7e0002)=$24 ($7f0001)=$00 ($7ffffd)=$99 + Expected output: A=$ffff X=$fffe Y=$fffd P=$00 E=0 DBR=7f ($7ffffe)=$21 ($7fffff)=$22 ($7f0000)=$23 ($7f0001)=$24 ($7ffffd)=$99 +Test 0262: mvp #$7f, #$7f + Input: A=$01ff X=$01ff Y=$0204 P=$ef E=0 ($7f0000)=$31 ($7f01ff)=$32 ($7f0004)=$99 + Expected output: A=$ffff X=$ffff Y=$0004 P=$ef E=0 DBR=7f ($7f0005)=$31 ($7f0204)=$32 ($7f0004)=$99 +Test 0263: mvp #$7f, #$7f + Input: A=$01ff X=$0201 Y=$01ff P=$00 E=0 ($7f0200)=$41 ($7f0201)=$42 + Expected output: A=$ffff X=$0001 Y=$ffff P=$00 E=0 DBR=7f ($7f0000)=$41 ($7f0001)=$42 +Test 0264: mvp #$7e, #$7f + Input: A=$0003 X=$0502 Y=$0501 P=$10 E=0 ($7e00ff)=$51 ($7e0000)=$52 ($7e0001)=$53 ($7e0002)=$54 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$00fe Y=$00fd P=$10 E=0 DBR=7f ($7f00fe)=$51 ($7f00ff)=$52 ($7f0000)=$53 ($7f0001)=$54 ($7f0002)=$99 +Test 0265: ora #$b939 + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 +Test 0266: ora ($10,x) + Input: A=$2318 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$39 ($7f1213)=$b9 + Expected output: A=$bb39 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$39 ($7f1213)=$b9 +Test 0267: ora ($90,x) + Input: A=$2318 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$39 ($7f1213)=$b9 + Expected output: A=$bb39 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$39 ($7f1213)=$b9 +Test 0268: ora $12,s + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$39 ($000202)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$39 ($000202)=$b9 +Test 0269: ora $34 + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$39 ($000034)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$39 ($000034)=$b9 +Test 026a: ora [$34] + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$39 ($7f1235)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$39 ($7f1235)=$b9 +Test 026b: ora $FFFF + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 026c: ora $7EFFFF + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 026d: ora ($34),y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 026e: ora ($34),y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 026f: ora ($34) + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$39 ($7f1235)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$39 ($7f1235)=$b9 +Test 0270: ora ($10,s),y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 0271: ora ($10,s),y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 0272: ora $02,x + Input: A=$2318 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$39 ($000135)=$b9 + Expected output: A=$bb39 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$39 ($000135)=$b9 +Test 0273: ora $02,x + Input: A=$2318 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$39 ($000034)=$b9 + Expected output: A=$bb39 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$39 ($000034)=$b9 +Test 0274: ora [$34],y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 0275: ora [$34],y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 0276: ora $FFFF,y + Input: A=$2318 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 0277: ora $FFFF,y + Input: A=$2318 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 0278: ora $FFFF,x + Input: A=$2318 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 0279: ora $FFFF,x + Input: A=$2318 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 027a: ora $7EFFFF,x + Input: A=$2318 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 027b: ora $7EFFFF,x + Input: A=$2318 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 027c: ora #$00 + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 027d: ora #$4300 + Input: A=$1200 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$5300 X=$3456 Y=$5678 P=$4d E=0 +Test 027e: ora #$39 + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 +Test 027f: ora ($10,x) + Input: A=$1298 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$39 + Expected output: A=$12b9 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$39 +Test 0280: ora ($90,x) + Input: A=$1298 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$39 + Expected output: A=$12b9 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$39 +Test 0281: ora $12,s + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$39 +Test 0282: ora $34 + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$39 +Test 0283: ora [$34] + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$39 +Test 0284: ora $FFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$39 +Test 0285: ora $7EFFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$39 +Test 0286: ora ($34),y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 0287: ora ($34),y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 0288: ora ($34) + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$39 +Test 0289: ora ($10,s),y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 028a: ora ($10,s),y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 028b: ora $02,x + Input: A=$1298 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$39 + Expected output: A=$12b9 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$39 +Test 028c: ora $02,x + Input: A=$1298 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$39 +Test 028d: ora [$34],y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 028e: ora [$34],y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 028f: ora $FFFF,y + Input: A=$1298 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$39 + Expected output: A=$12b9 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$39 +Test 0290: ora $FFFF,y + Input: A=$1298 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$39 +Test 0291: ora $FFFF,x + Input: A=$1298 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$39 + Expected output: A=$12b9 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$39 +Test 0292: ora $FFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$39 +Test 0293: ora $7EFFFF,x + Input: A=$1298 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$39 + Expected output: A=$12b9 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$39 +Test 0294: ora $7EFFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$39 +Test 0295: ora #$00 + Input: A=$aa00 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$22 E=0 +Test 0296: nop + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 0297: wdm $AB + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 0298: pea $ABCD + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$cd ($0001ef)=$ab +Test 0299: pei ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$65 ($0001ef)=$87 +Test 029a: per -$8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$62 ($7e7001)=$00 ($7e7002)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$03 ($0001ef)=$f0 + Additional initialization or checks are performed - see assembly +Test 029b: per +$7FFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$62 ($7e7001)=$ff ($7e7002)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$f0 + Additional initialization or checks are performed - see assembly +Test 029c: pla + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$fedc X=$3456 Y=$5678 P=$80 E=0 S=01f1 +Test 029d: plx + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$1234 X=$fedc Y=$5678 P=$80 E=0 S=01f1 +Test 029e: ply + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$1234 X=$3456 Y=$fedc P=$80 E=0 S=01f1 +Test 029f: pla + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 S=01f1 +Test 02a0: plx + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 S=01f1 +Test 02a1: ply + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 S=01f1 +Test 02a2: pla + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$12ef X=$3456 Y=$5678 P=$ed E=0 S=01f0 +Test 02a3: plx + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$1234 X=$00ef Y=$0078 P=$dd E=0 S=01f0 +Test 02a4: ply + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$00ef P=$dd E=0 S=01f0 +Test 02a5: pla + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 S=01f0 +Test 02a6: plx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 S=01f0 +Test 02a7: ply + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 S=01f0 +Test 02a8: plb + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$fe + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 S=01f0 DBR=fe +Test 02a9: plb + Input: A=$1234 X=$3456 Y=$5678 P=$fd E=0 ($0001f0)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7f E=0 S=01f0 DBR=00 +Test 02aa: pld + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$53 ($0001f1)=$97 + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 S=01f1 D=9753 +Test 02ab: pld + Input: A=$1234 X=$3456 Y=$5678 P=$fd E=0 D=$9999 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7f E=0 S=01f1 D=0000 +Test 02ac: plp + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 ($0001f0)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$00 E=0 S=01f0 +Test 02ad: plp + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$23 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 S=01f0 +Test 02ae: plp + Input: A=$1234 X=$2345 Y=$3456 P=$00 E=0 ($0001f0)=$10 + Expected output: A=$1234 X=$0045 Y=$0056 P=$10 E=0 S=01f0 +Test 02af: pha + Input: A=$9876 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$9876 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$76 ($0001ef)=$98 +Test 02b0: pha + Input: A=$8765 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$8765 X=$3456 Y=$5678 P=$ef E=0 S=01ee ($0001ef)=$65 +Test 02b1: phx + Input: A=$1234 X=$9876 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$9876 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$76 ($0001ef)=$98 +Test 02b2: phx + Input: A=$1234 X=$0023 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0023 Y=$0078 P=$df E=0 S=01ee ($0001ef)=$23 +Test 02b3: phy + Input: A=$1234 X=$3456 Y=$1324 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$1324 P=$00 E=0 S=01ed ($0001ee)=$24 ($0001ef)=$13 +Test 02b4: phy + Input: A=$1234 X=$3456 Y=$0035 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0035 P=$df E=0 S=01ee ($0001ef)=$35 +Test 02b5: phb + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ee ($0001ef)=$7f +Test 02b6: phd + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 D=$6543 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$43 ($0001ef)=$65 +Test 02b7: phk + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e8000)=$4b + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ee ($0001ef)=$7e + Additional initialization or checks are performed - see assembly +Test 02b8: php + Input: A=$1234 X=$3456 Y=$5678 P=$0a E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$0a E=0 S=01ee ($0001ef)=$0a +Test 02b9: sep #$FF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 02ba: sep #$0F + Input: A=$1234 X=$3456 Y=$5678 P=$11 E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$1f E=0 +Test 02bb: rep #$F0 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$0f E=0 +Test 02bc: rep #$0F + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$f0 E=0 +Test 02bd: rep #$38 + Input: A=$1234 X=$3456 Y=$5678 P=$3a E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 +Test 02be: rol a + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 02bf: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 02c0: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02c1: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 02c2: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 02c3: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02c4: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 02c5: rol a + Input: A=$4111 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8223 X=$3456 Y=$5678 P=$cc E=0 +Test 02c6: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$23 ($000034)=$82 +Test 02c7: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$11 ($7f0000)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$23 ($7f0000)=$82 +Test 02c8: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$11 ($000135)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$23 ($000135)=$82 +Test 02c9: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$23 ($000034)=$82 +Test 02ca: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$11 ($7f0300)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$23 ($7f0300)=$82 +Test 02cb: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$11 ($7f0030)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$23 ($7f0030)=$82 +Test 02cc: rol a + Input: A=$1280 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 02cd: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 02ce: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 02cf: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 02d0: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 02d1: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 02d2: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 02d3: rol a + Input: A=$1241 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1283 X=$3456 Y=$5678 P=$ec E=0 +Test 02d4: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$83 +Test 02d5: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$83 +Test 02d6: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$83 +Test 02d7: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$83 +Test 02d8: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$83 +Test 02d9: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$83 +Test 02da: ror a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 02db: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 02dc: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02dd: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 02de: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 02df: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02e0: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 02e1: ror a + Input: A=$4222 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$a111 X=$3456 Y=$5678 P=$cc E=0 +Test 02e2: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$11 ($000034)=$a1 +Test 02e3: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$22 ($7f0000)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$11 ($7f0000)=$a1 +Test 02e4: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$22 ($000135)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$11 ($000135)=$a1 +Test 02e5: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$11 ($000034)=$a1 +Test 02e6: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$22 ($7f0300)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$11 ($7f0300)=$a1 +Test 02e7: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$22 ($7f0030)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$11 ($7f0030)=$a1 +Test 02e8: ror a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 02e9: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 02ea: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 02eb: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 02ec: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 02ed: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 02ee: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 02ef: ror a + Input: A=$1242 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$12a1 X=$3456 Y=$5678 P=$ec E=0 +Test 02f0: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$a1 +Test 02f1: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$a1 +Test 02f2: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$a1 +Test 02f3: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$a1 +Test 02f4: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$a1 +Test 02f5: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$a1 +Test 02f6: rts + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e8000)=$60 ($0001f0)=$ff ($0001f1)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01f1 + Additional initialization or checks are performed - see assembly +Test 02f7: rtl + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$ff ($0001f1)=$ff ($0001f2)=$7e + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01f2 + Additional initialization or checks are performed - see assembly +Test 02f8: rti + Input: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($0001f0)=$88 ($0001f1)=$00 ($0001f2)=$00 ($0001f3)=$7e + Expected output: A=$1234 X=$3456 Y=$5678 P=$88 E=0 S=01f3 + Additional initialization or checks are performed - see assembly +Test 02f9: sbc #$908f + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 02fa: sbc ($10,x) + Input: A=$9090 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$8f ($7f1213)=$90 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$8f ($7f1213)=$90 +Test 02fb: sbc ($90,x) + Input: A=$9090 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$8f ($7f1213)=$90 + Expected output: A=$0000 X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$8f ($7f1213)=$90 +Test 02fc: sbc $12,s + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$8f ($000202)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000201)=$8f ($000202)=$90 +Test 02fd: sbc $34 + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$8f ($000034)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$8f ($000034)=$90 +Test 02fe: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8f ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$8f ($7f1235)=$90 +Test 02ff: sbc $FFFF + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0300: sbc $7EFFFF + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0301: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 0302: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 0303: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8f ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$8f ($7f1235)=$90 +Test 0304: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 0305: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 0306: sbc $02,x + Input: A=$9090 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$8f ($000135)=$90 + Expected output: A=$0000 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$8f ($000135)=$90 +Test 0307: sbc $02,x + Input: A=$9090 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$8f ($000034)=$90 + Expected output: A=$0000 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$8f ($000034)=$90 +Test 0308: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 0309: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 030a: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 030b: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 030c: sbc $FFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 030d: sbc $FFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 030e: sbc $7EFFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 030f: sbc $7EFFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 0310: sbc #$2000 + Input: A=$9090 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$7090 X=$3456 Y=$5678 P=$41 E=0 +Test 0311: sbc #$1235 + Input: A=$1234 X=$3456 Y=$5678 P=$47 E=0 + Expected output: A=$ffff X=$3456 Y=$5678 P=$84 E=0 +Test 0312: sbc #$a000 + Input: A=$7000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$cfff X=$3456 Y=$5678 P=$c0 E=0 +Test 0313: sbc #$8f + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 +Test 0314: sbc ($10,x) + Input: A=$cc90 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$8f + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$8f +Test 0315: sbc ($90,x) + Input: A=$cc90 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$8f + Expected output: A=$cc00 X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$8f +Test 0316: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($000201)=$8f +Test 0317: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$8f +Test 0318: sbc [$34] + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$8f +Test 0319: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$8f +Test 031a: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$8f +Test 031b: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 031c: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 031d: sbc ($34) + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$8f +Test 031e: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 031f: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 0320: sbc $02,x + Input: A=$cc90 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$8f + Expected output: A=$cc00 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$8f +Test 0321: sbc $02,x + Input: A=$cc90 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$8f +Test 0322: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 0323: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 0324: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$8f + Expected output: A=$cc00 X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$8f +Test 0325: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$8f +Test 0326: sbc $FFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$8f + Expected output: A=$cc00 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$8f +Test 0327: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$8f +Test 0328: sbc $7EFFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$8f + Expected output: A=$cc00 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$8f +Test 0329: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$8f +Test 032a: sbc #$20 + Input: A=$cc90 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$cc70 X=$3456 Y=$5678 P=$61 E=0 +Test 032b: sbc #$13 + Input: A=$cc12 X=$3456 Y=$5678 P=$67 E=0 + Expected output: A=$ccff X=$3456 Y=$5678 P=$a4 E=0 +Test 032c: sbc #$a0 + Input: A=$cc70 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$cccf X=$3456 Y=$5678 P=$e0 E=0 +Test 032d: sta ($10,x) + Input: A=$8000 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$00 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 032e: sta ($90,x) + Input: A=$8000 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$0010 Y=$0078 P=$10 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 032f: sta $12,s + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$34 ($000202)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$00 ($000202)=$80 +Test 0330: sta $34 + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 0331: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 0332: sta $FFFF + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0333: sta $7EFFFF + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0334: sta ($34),y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0335: sta ($34),y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0336: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 0337: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0338: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0339: sta $02,x + Input: A=$8000 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$8000 X=$0133 Y=$5678 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 033a: sta $02,x + Input: A=$8000 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$0032 Y=$0078 P=$10 E=0 ($000033)=$00 ($000034)=$80 +Test 033b: sta [$34],y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 033c: sta [$34],y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 033d: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$3456 Y=$0300 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 033e: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0056 Y=$0030 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 033f: sta $FFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 0340: sta $FFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 0341: sta $7EFFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 0342: sta $7EFFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 0343: stx $34 + Input: A=$1234 X=$8000 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 0344: stx $FFFF + Input: A=$1234 X=$8000 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0345: stx $02,y + Input: A=$1234 X=$8000 Y=$0133 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$8000 Y=$0133 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 0346: sty $34 + Input: A=$1234 X=$3456 Y=$8000 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 0347: sty $FFFF + Input: A=$1234 X=$3456 Y=$8000 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0348: sty $02,x + Input: A=$1234 X=$0133 Y=$8000 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$8000 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 0349: sta ($10,x) + Input: A=$8000 X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$cf E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 034a: sta ($90,x) + Input: A=$8000 X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$0010 Y=$0078 P=$df E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 034b: sta $12,s + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$34 ($000202)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$00 ($000202)=$80 +Test 034c: sta $34 + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 034d: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 034e: sta $FFFF + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 034f: sta $7EFFFF + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0350: sta ($34),y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0351: sta ($34),y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0352: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 0353: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0354: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0355: sta $02,x + Input: A=$8000 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$8000 X=$0133 Y=$5678 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 0356: sta $02,x + Input: A=$8000 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$0032 Y=$0078 P=$df E=0 ($000033)=$00 ($000034)=$80 +Test 0357: sta [$34],y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0358: sta [$34],y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0359: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$3456 Y=$0300 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 035a: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0056 Y=$0030 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 035b: sta $FFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 035c: sta $FFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 035d: sta $7EFFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 035e: sta $7EFFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 035f: stx $34 + Input: A=$1234 X=$8000 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 0360: stx $FFFF + Input: A=$1234 X=$8000 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0361: stx $02,y + Input: A=$1234 X=$8000 Y=$0133 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$8000 Y=$0133 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 0362: sty $34 + Input: A=$1234 X=$3456 Y=$8000 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 0363: sty $FFFF + Input: A=$1234 X=$3456 Y=$8000 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0364: sty $02,x + Input: A=$1234 X=$0133 Y=$8000 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$8000 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 0365: sta ($10,x) + Input: A=$5500 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$12 + Expected output: A=$5500 X=$ff91 Y=$5678 P=$20 E=0 ($7f1212)=$00 +Test 0366: sta ($90,x) + Input: A=$5500 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$30 E=0 ($7f1212)=$00 +Test 0367: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$00 +Test 0368: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000033)=$00 +Test 0369: sta [$34] + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7f1234)=$00 +Test 036a: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 036b: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 036c: sta ($34),y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 036d: sta ($34),y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 036e: sta ($34) + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7f1234)=$00 +Test 036f: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 0370: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 0371: sta $02,x + Input: A=$5500 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$5500 X=$0133 Y=$5678 P=$20 E=0 ($000134)=$00 +Test 0372: sta $02,x + Input: A=$5500 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$30 E=0 ($000033)=$00 +Test 0373: sta [$34],y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 0374: sta [$34],y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 0375: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$3456 Y=$0300 P=$20 E=0 ($7f02ff)=$00 +Test 0376: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$30 E=0 ($7f002f)=$00 +Test 0377: sta $FFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 0378: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 0379: sta $7EFFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 037a: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 037b: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$10 E=0 ($000033)=$00 +Test 037c: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$10 E=0 ($7effff)=$00 +Test 037d: stx $02,y + Input: A=$1234 X=$0000 Y=$1232 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$10 E=0 ($000033)=$00 +Test 037e: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$10 E=0 ($000033)=$00 +Test 037f: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$10 E=0 ($7effff)=$00 +Test 0380: sty $02,x + Input: A=$1234 X=$1232 Y=$0000 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$10 E=0 ($000033)=$00 +Test 0381: sta ($10,x) + Input: A=$5500 X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$12 + Expected output: A=$5500 X=$ff91 Y=$5678 P=$ef E=0 ($7f1212)=$00 +Test 0382: sta ($90,x) + Input: A=$5500 X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$ff E=0 ($7f1212)=$00 +Test 0383: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$00 +Test 0384: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000033)=$00 +Test 0385: sta [$34] + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7f1234)=$00 +Test 0386: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 +Test 0387: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 +Test 0388: sta ($34),y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 0389: sta ($34),y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 038a: sta ($34) + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7f1234)=$00 +Test 038b: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 038c: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 038d: sta $02,x + Input: A=$5500 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$5500 X=$0133 Y=$5678 P=$ef E=0 ($000134)=$00 +Test 038e: sta $02,x + Input: A=$5500 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$ff E=0 ($000033)=$00 +Test 038f: sta [$34],y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 0390: sta [$34],y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 0391: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$3456 Y=$0300 P=$ef E=0 ($7f02ff)=$00 +Test 0392: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$ff E=0 ($7f002f)=$00 +Test 0393: sta $FFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 +Test 0394: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=0 ($7f002f)=$00 +Test 0395: sta $7EFFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 +Test 0396: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=0 ($7f002f)=$00 +Test 0397: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$df E=0 ($000033)=$00 +Test 0398: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$df E=0 ($7effff)=$00 +Test 0399: stx $02,y + Input: A=$1234 X=$0000 Y=$1232 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$df E=0 ($000033)=$00 +Test 039a: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$df E=0 ($000033)=$00 +Test 039b: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$df E=0 ($7effff)=$00 +Test 039c: sty $02,x + Input: A=$1234 X=$1232 Y=$0000 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$df E=0 ($000033)=$00 +Test 039d: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$00 +Test 039e: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$00 E=0 ($000134)=$00 ($000135)=$00 +Test 039f: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$10 E=0 ($000033)=$00 ($000034)=$00 +Test 03a0: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 03a1: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 03a2: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 03a3: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$00 +Test 03a4: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cf E=0 ($000134)=$00 ($000135)=$00 +Test 03a5: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$df E=0 ($000033)=$00 ($000034)=$00 +Test 03a6: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$00 +Test 03a7: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 03a8: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 03a9: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($000033)=$00 +Test 03aa: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$20 E=0 ($000134)=$00 +Test 03ab: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$30 E=0 ($000033)=$00 +Test 03ac: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 03ad: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 03ae: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 03af: trb $34 + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$04 ($000034)=$80 +Test 03b0: trb $FFFF + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$04 ($7f0000)=$80 +Test 03b1: trb $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$aa ($000034)=$aa +Test 03b2: trb $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$aa ($7f0000)=$aa +Test 03b3: trb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$80 +Test 03b4: trb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$80 +Test 03b5: trb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$aa +Test 03b6: trb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$aa +Test 03b7: tsb $34 + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$34 ($000034)=$96 +Test 03b8: tsb $FFFF + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$34 ($7f0000)=$96 +Test 03b9: tsb $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$ff ($000034)=$ff +Test 03ba: tsb $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$ff ($7f0000)=$ff +Test 03bb: tsb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$96 +Test 03bc: tsb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$96 +Test 03bd: tsb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$ff +Test 03be: tsb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$ff +Test 03bf: tax + Input: A=$8765 X=$5678 Y=$5678 P=$00 E=0 + Expected output: A=$8765 X=$8765 Y=$5678 P=$80 E=0 +Test 03c0: tax + Input: A=$0000 X=$5678 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$0000 Y=$5678 P=$02 E=0 +Test 03c1: tax + Input: A=$1234 X=$5678 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$1234 Y=$5678 P=$6d E=0 +Test 03c2: tax + Input: A=$87ab X=$5678 Y=$5678 P=$10 E=0 + Expected output: A=$87ab X=$00ab Y=$0078 P=$90 E=0 +Test 03c3: tay + Input: A=$8765 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$8765 X=$3456 Y=$8765 P=$80 E=0 +Test 03c4: tay + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$0000 P=$02 E=0 +Test 03c5: tay + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$3456 Y=$1234 P=$6d E=0 +Test 03c6: tay + Input: A=$87ab X=$3456 Y=$5678 P=$10 E=0 + Expected output: A=$87ab X=$0056 Y=$00ab P=$90 E=0 +Test 03c7: txa + Input: A=$1234 X=$9876 Y=$5678 P=$00 E=0 + Expected output: A=$9876 X=$9876 Y=$5678 P=$80 E=0 +Test 03c8: txa + Input: A=$1234 X=$0000 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$0000 Y=$5678 P=$02 E=0 +Test 03c9: txa + Input: A=$1234 X=$00cd Y=$5678 P=$df E=0 + Expected output: A=$00cd X=$00cd Y=$0078 P=$5d E=0 +Test 03ca: txa + Input: A=$1234 X=$abcd Y=$5678 P=$20 E=0 + Expected output: A=$12cd X=$abcd Y=$5678 P=$a0 E=0 +Test 03cb: txa + Input: A=$1234 X=$ab00 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$ab00 Y=$5678 P=$22 E=0 +Test 03cc: tya + Input: A=$1234 X=$3456 Y=$9876 P=$00 E=0 + Expected output: A=$9876 X=$3456 Y=$9876 P=$80 E=0 +Test 03cd: tya + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$0000 P=$02 E=0 +Test 03ce: tya + Input: A=$1234 X=$3456 Y=$00cd P=$df E=0 + Expected output: A=$00cd X=$0056 Y=$00cd P=$5d E=0 +Test 03cf: tya + Input: A=$1234 X=$3456 Y=$abcd P=$20 E=0 + Expected output: A=$12cd X=$3456 Y=$abcd P=$a0 E=0 +Test 03d0: tya + Input: A=$1234 X=$3456 Y=$ab00 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$ab00 P=$22 E=0 +Test 03d1: txy + Input: A=$1234 X=$8765 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$8765 Y=$8765 P=$80 E=0 +Test 03d2: txy + Input: A=$1234 X=$0000 Y=$5678 P=$ed E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$6f E=0 +Test 03d3: txy + Input: A=$1234 X=$0098 Y=$0000 P=$10 E=0 + Expected output: A=$1234 X=$0098 Y=$0098 P=$90 E=0 +Test 03d4: txy + Input: A=$1234 X=$0000 Y=$0098 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$12 E=0 +Test 03d5: tyx + Input: A=$1234 X=$5678 Y=$8765 P=$00 E=0 + Expected output: A=$1234 X=$8765 Y=$8765 P=$80 E=0 +Test 03d6: tyx + Input: A=$1234 X=$5678 Y=$0000 P=$ed E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$6f E=0 +Test 03d7: tyx + Input: A=$1234 X=$0000 Y=$0098 P=$10 E=0 + Expected output: A=$1234 X=$0098 Y=$0098 P=$90 E=0 +Test 03d8: tyx + Input: A=$1234 X=$0098 Y=$0000 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$12 E=0 +Test 03d9: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$01ef Y=$5678 P=$6d E=0 +Test 03da: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 S=$0200 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 S=0200 +Test 03db: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$00ef Y=$0078 P=$90 E=0 +Test 03dc: tsc + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 + Expected output: A=$01ef X=$0056 Y=$0078 P=$5d E=0 +Test 03dd: tsc + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 S=$0200 + Expected output: A=$0200 X=$3456 Y=$5678 P=$20 E=0 S=0200 +Test 03de: tsc + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 S=$0000 + Expected output: A=$0000 X=$01ef Y=$0001 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 03df: tsc + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 S=$8000 + Expected output: A=$8000 X=$01ef Y=$0001 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 03e0: txs + Input: A=$1234 X=$0200 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$0200 Y=$5678 P=$ef E=0 S=0200 +Test 03e1: tcs + Input: A=$0200 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$0200 X=$3456 Y=$5678 P=$ef E=0 S=0200 +Test 03e2: tcd + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 D=$1234 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 D=0000 +Test 03e3: tcd + Input: A=$9876 X=$3456 Y=$5678 P=$6f E=0 + Expected output: A=$9876 X=$3456 Y=$5678 P=$ed E=0 D=9876 +Test 03e4: tdc + Input: A=$0000 X=$3456 Y=$5678 P=$20 E=0 D=$9876 + Expected output: A=$9876 X=$3456 Y=$5678 P=$a0 E=0 +Test 03e5: tdc + Input: A=$1234 X=$3456 Y=$5678 P=$dd E=0 D=$0000 + Expected output: A=$0000 X=$0056 Y=$0078 P=$5f E=0 +Test 03e6: xba + Input: A=$9812 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1298 X=$3456 Y=$5678 P=$80 E=0 +Test 03e7: xba + Input: A=$00aa X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$02 E=0 +Test 03e8: xce + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 03e9: xce + Input: A=$1234 X=$3456 Y=$5678 P=$fe E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fe E=0 +Test 03ea: xce + Input: A=$1234 X=$1234 Y=$4567 P=$01 E=0 + Expected output: A=$1234 X=$0034 Y=$0067 P=$30 E=1 +Test 03eb: xce + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$31 E=0 +Test 03ec: xce + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 S=$03ff + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 S=01ff +Test 03ed: adc #$8765 + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 +Test 03ee: adc ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($7f1212)=$65 ($7f1213)=$87 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$0b E=0 ($7f1212)=$65 ($7f1213)=$87 +Test 03ef: adc ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$19 E=0 DBR=$7f D=$ff00 ($7f1212)=$65 ($7f1213)=$87 + Expected output: A=$0000 X=$0010 Y=$0078 P=$1b E=0 ($7f1212)=$65 ($7f1213)=$87 +Test 03f0: adc $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 ($000201)=$65 ($000202)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000201)=$65 ($000202)=$87 +Test 03f1: adc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000033)=$65 ($000034)=$87 +Test 03f2: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$65 ($7f1235)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$65 ($7f1235)=$87 +Test 03f3: adc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7e ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 03f4: adc $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 03f5: adc ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 03f6: adc ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 03f7: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$65 ($7f1235)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$65 ($7f1235)=$87 +Test 03f8: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 03f9: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 03fa: adc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000134)=$65 ($000135)=$87 + Expected output: A=$0000 X=$0133 Y=$5678 P=$0b E=0 ($000134)=$65 ($000135)=$87 +Test 03fb: adc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$19 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$0000 X=$0032 Y=$0078 P=$1b E=0 ($000033)=$65 ($000034)=$87 +Test 03fc: adc [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 03fd: adc [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 03fe: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$09 E=0 DBR=$7e ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$3456 Y=$0300 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 03ff: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$19 E=0 DBR=$7e ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0056 Y=$0030 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 0400: adc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$09 E=0 DBR=$7e ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 0401: adc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$19 E=0 DBR=$7e ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 0402: adc $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$09 E=0 ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 0403: adc $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$19 E=0 ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 0404: adc #$4470 + Input: A=$3550 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$8020 X=$3456 Y=$5678 P=$c8 E=0 +Test 0405: adc #$3999 + Input: A=$4000 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$7999 X=$3456 Y=$5678 P=$08 E=0 +Test 0406: adc #$87 + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 +Test 0407: adc ($10,x) + Input: A=$cc12 X=$ff91 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($7f1212)=$87 + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$2b E=0 ($7f1212)=$87 +Test 0408: adc ($90,x) + Input: A=$cc12 X=$1210 Y=$5678 P=$39 E=0 DBR=$7f D=$ff00 ($7f1212)=$87 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=0 ($7f1212)=$87 +Test 0409: adc $12,s + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 ($000201)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000201)=$87 +Test 040a: adc $34 + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000033)=$87 +Test 040b: adc [$34] + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$87 +Test 040c: adc $FFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7e ($7effff)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$87 +Test 040d: adc $7EFFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 ($7effff)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$87 +Test 040e: adc ($34),y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 040f: adc ($34),y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 0410: adc ($34) + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$87 +Test 0411: adc ($10,s),y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 0412: adc ($10,s),y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 0413: adc $02,x + Input: A=$cc12 X=$0133 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000134)=$87 + Expected output: A=$cc00 X=$0133 Y=$5678 P=$2b E=0 ($000134)=$87 +Test 0414: adc $02,x + Input: A=$cc12 X=$1232 Y=$5678 P=$39 E=0 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=0 ($000033)=$87 +Test 0415: adc [$34],y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 0416: adc [$34],y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 0417: adc $FFFF,y + Input: A=$cc12 X=$3456 Y=$0300 P=$29 E=0 DBR=$7e ($7f02ff)=$87 + Expected output: A=$cc00 X=$3456 Y=$0300 P=$2b E=0 ($7f02ff)=$87 +Test 0418: adc $FFFF,y + Input: A=$cc12 X=$3456 Y=$1230 P=$39 E=0 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=0 ($7f002f)=$87 +Test 0419: adc $FFFF,x + Input: A=$cc12 X=$0300 Y=$5678 P=$29 E=0 DBR=$7e ($7f02ff)=$87 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$87 +Test 041a: adc $FFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$39 E=0 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$87 +Test 041b: adc $7EFFFF,x + Input: A=$cc12 X=$0300 Y=$5678 P=$29 E=0 ($7f02ff)=$87 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$87 +Test 041c: adc $7EFFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$39 E=0 ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$87 +Test 041d: adc #$40 + Input: A=$cc40 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc80 X=$3456 Y=$5678 P=$e8 E=0 +Test 041e: adc #$39 + Input: A=$cc40 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc79 X=$3456 Y=$5678 P=$28 E=0 +Test 041f: sbc #$9089 + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 +Test 0420: sbc ($10,x) + Input: A=$9090 X=$ff91 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($7f1212)=$89 ($7f1213)=$90 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$0b E=0 ($7f1212)=$89 ($7f1213)=$90 +Test 0421: sbc ($90,x) + Input: A=$9090 X=$1210 Y=$5678 P=$18 E=0 DBR=$7f D=$ff00 ($7f1212)=$89 ($7f1213)=$90 + Expected output: A=$0000 X=$0010 Y=$0078 P=$1b E=0 ($7f1212)=$89 ($7f1213)=$90 +Test 0422: sbc $12,s + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 ($000201)=$89 ($000202)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000201)=$89 ($000202)=$90 +Test 0423: sbc $34 + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000033)=$89 ($000034)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000033)=$89 ($000034)=$90 +Test 0424: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$89 ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$89 ($7f1235)=$90 +Test 0425: sbc $FFFF + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7e ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0426: sbc $7EFFFF + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0427: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 0428: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 0429: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$89 ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$89 ($7f1235)=$90 +Test 042a: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 042b: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 042c: sbc $02,x + Input: A=$9090 X=$0133 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000134)=$89 ($000135)=$90 + Expected output: A=$0000 X=$0133 Y=$5678 P=$0b E=0 ($000134)=$89 ($000135)=$90 +Test 042d: sbc $02,x + Input: A=$9090 X=$1232 Y=$5678 P=$18 E=0 DBR=$7f D=$ffff ($000033)=$89 ($000034)=$90 + Expected output: A=$0000 X=$0032 Y=$0078 P=$1b E=0 ($000033)=$89 ($000034)=$90 +Test 042e: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 042f: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 0430: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$0300 P=$08 E=0 DBR=$7e ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$3456 Y=$0300 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0431: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$1230 P=$18 E=0 DBR=$7e ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0056 Y=$0030 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0432: sbc $FFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$08 E=0 DBR=$7e ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0433: sbc $FFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$18 E=0 DBR=$7e ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0434: sbc $7EFFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$08 E=0 ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0435: sbc $7EFFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$18 E=0 ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0436: sbc #$01 + Input: A=$0000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$9999 X=$3456 Y=$5678 P=$88 E=0 +Test 0437: sbc #$9000 + Input: A=$1000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$2000 X=$3456 Y=$5678 P=$48 E=0 +Test 0438: sbc #$9001 + Input: A=$1000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$1999 X=$3456 Y=$5678 P=$08 E=0 +Test 0439: sbc #$89 + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 +Test 043a: sbc ($10,x) + Input: A=$cc90 X=$ff91 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($7f1212)=$89 + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$2b E=0 ($7f1212)=$89 +Test 043b: sbc ($90,x) + Input: A=$cc90 X=$1210 Y=$5678 P=$38 E=0 DBR=$7f D=$ff00 ($7f1212)=$89 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=0 ($7f1212)=$89 +Test 043c: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 ($000201)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000201)=$89 +Test 043d: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000033)=$89 +Test 043e: sbc [$34] + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$89 +Test 043f: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7e ($7effff)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$89 +Test 0440: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 ($7effff)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$89 +Test 0441: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 0442: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 0443: sbc ($34) + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$89 +Test 0444: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 0445: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 0446: sbc $02,x + Input: A=$cc90 X=$0133 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000134)=$89 + Expected output: A=$cc00 X=$0133 Y=$5678 P=$2b E=0 ($000134)=$89 +Test 0447: sbc $02,x + Input: A=$cc90 X=$1232 Y=$5678 P=$38 E=0 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=0 ($000033)=$89 +Test 0448: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 0449: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 044a: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$0300 P=$28 E=0 DBR=$7e ($7f02ff)=$89 + Expected output: A=$cc00 X=$3456 Y=$0300 P=$2b E=0 ($7f02ff)=$89 +Test 044b: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$38 E=0 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=0 ($7f002f)=$89 +Test 044c: sbc $FFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$28 E=0 DBR=$7e ($7f02ff)=$89 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$89 +Test 044d: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$38 E=0 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$89 +Test 044e: sbc $7EFFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$28 E=0 ($7f02ff)=$89 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$89 +Test 044f: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$38 E=0 ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$89 +Test 0450: sbc #$01 + Input: A=$cc00 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc99 X=$3456 Y=$5678 P=$a8 E=0 +Test 0451: sbc #$90 + Input: A=$cc10 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc20 X=$3456 Y=$5678 P=$68 E=0 +Test 0452: sbc #$91 + Input: A=$cc10 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc19 X=$3456 Y=$5678 P=$28 E=0 diff --git a/roms/snes-tests/cputest/tests-full.inc b/roms/snes-tests/cputest/tests-full.inc new file mode 100644 index 00000000..bb61425a --- /dev/null +++ b/roms/snes-tests/cputest/tests-full.inc @@ -0,0 +1,68569 @@ +; Auto-generated by make_cpu_tests.py + +bank0_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + + start_tests: + +test0000: +.export test0000: far + ldx #$00 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$5C ; jmp long opcode + sta $7f0000 + lda #<@not_ok + sta $7f0001 + lda #>@not_ok + sta $7f0002 + lda #^@not_ok + sta $7f0003 + lda #$ea + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFFF +@not_ok: + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0001: +.export test0001: far + ldx #$01 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc #$edcb + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0002: +.export test0002: far + ldx #$02 + jsl init_test + lda #$cb + sta $7f1212 + lda #$ed + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$fe + sep #$01 + adc ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$cb + bne @to_fail + lda $7f1213 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0003: +.export test0003: far + ldx #$03 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$0123 + ldy #$5678 + rep #$fe + sep #$01 + adc ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0004: +.export test0004: far + ldx #$04 + jsl init_test + lda #$cb + sta $7f1212 + lda #$ed + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$cb + bne @to_fail + lda $7f1213 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0005: +.export test0005: far + ldx #$05 + jsl init_test + lda #$cb + sta $000201 + lda #$ed + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$cb + bne @to_fail + lda $000202 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0006: +.export test0006: far + ldx #$06 + jsl init_test + lda #$cb + sta $000033 + lda #$ed + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$cb + bne @to_fail + lda $000034 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0007: +.export test0007: far + ldx #$07 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cb + sta $7f1234 + lda #$ed + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$cb + bne @to_fail + lda $7f1235 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0008: +.export test0008: far + ldx #$08 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0009: +.export test0009: far + ldx #$09 + jsl init_test + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000a: +.export test000a: far + ldx #$0a + jsl init_test + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000b: +.export test000b: far + ldx #$0b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000c: +.export test000c: far + ldx #$0c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000d: +.export test000d: far + ldx #$0d + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fe + sep #$01 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000e: +.export test000e: far + ldx #$0e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cb + sta $7f1234 + lda #$ed + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$cb + bne @to_fail + lda $7f1235 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test000f: +.export test000f: far + ldx #$0f + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0010: +.export test0010: far + ldx #$10 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0011: +.export test0011: far + ldx #$11 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0012: +.export test0012: far + ldx #$12 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fe + sep #$01 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0013: +.export test0013: far + ldx #$13 + jsl init_test + lda #$cb + sta $000134 + lda #$ed + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$fe + sep #$01 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$cb + bne @to_fail + lda $000135 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0014: +.export test0014: far + ldx #$14 + jsl init_test + lda #$cb + sta $000033 + lda #$ed + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$cb + bne @to_fail + lda $000034 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0015: +.export test0015: far + ldx #$15 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cb + sta $7f0fdc + lda #$ed + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fe + sep #$01 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$cb + bne @to_fail + lda $7f0fdd + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0016: +.export test0016: far + ldx #$16 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cb + sta $7ffeec + lda #$ed + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ee + sep #$11 + .i8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$cb + bne @to_fail + lda $7ffeed + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0017: +.export test0017: far + ldx #$17 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$cb + sta $7effff + lda #$ed + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fe + sep #$01 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$cb + bne @to_fail + lda $7f0000 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0018: +.export test0018: far + ldx #$18 + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$fe + sep #$01 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0019: +.export test0019: far + ldx #$19 + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$ee + sep #$11 + .i8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001a: +.export test001a: far + ldx #$1a + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fe + sep #$01 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001b: +.export test001b: far + ldx #$1b + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001c: +.export test001c: far + ldx #$1c + jsl init_test + lda #$cb + sta $7f02ff + lda #$ed + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fe + sep #$01 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$cb + bne @to_fail + lda $7f0300 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001d: +.export test001d: far + ldx #$1d + jsl init_test + lda #$cb + sta $7f002f + lda #$ed + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$cb + bne @to_fail + lda $7f0030 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001e: +.export test001e: far + ldx #$1e + jsl init_test + rep #$20 + .a16 + lda #$6789 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + adc #$2000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c0 + bne @to_fail + ldx result_a + cpx #$8789 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test001f: +.export test001f: far + ldx #$1f + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$39 + sep #$c6 + adc #$8000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0047 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0020: +.export test0020: far + ldx #$20 + jsl init_test + rep #$20 + .a16 + lda #$9000 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + adc #$e000 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0041 + bne @to_fail + ldx result_a + cpx #$7001 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0021: +.export test0021: far + ldx #$21 + jsl init_test + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc #$ed + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0022: +.export test0022: far + ldx #$22 + jsl init_test + lda #$ed + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$ff91 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1212 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0023: +.export test0023: far + ldx #$23 + jsl init_test + lda #$ed + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1112 + ldx #$1210 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1212 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0024: +.export test0024: far + ldx #$24 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($EF,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0025: +.export test0025: far + ldx #$25 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($F0,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0026: +.export test0026: far + ldx #$26 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1112 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($F6,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0027: +.export test0027: far + ldx #$27 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1112 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($F7,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0028: +.export test0028: far + ldx #$28 + jsl init_test + lda #$ed + sta $000201 + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000201 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0029: +.export test0029: far + ldx #$29 + jsl init_test + lda #$ed + sta $000201 + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000201 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002a: +.export test002a: far + ldx #$2a + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002b: +.export test002b: far + ldx #$2b + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002c: +.export test002c: far + ldx #$2c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$ed + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002d: +.export test002d: far + ldx #$2d + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$ed + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc [$FF] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002e: +.export test002e: far + ldx #$2e + jsl init_test + lda #$ed + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test002f: +.export test002f: far + ldx #$2f + jsl init_test + lda #$ed + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0030: +.export test0030: far + ldx #$30 + jsl init_test + lda #$ed + sta $7effff + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0031: +.export test0031: far + ldx #$31 + jsl init_test + lda #$ed + sta $7effff + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7effff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0032: +.export test0032: far + ldx #$32 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$ed + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0033: +.export test0033: far + ldx #$33 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$ed + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0034: +.export test0034: far + ldx #$34 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$ed + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($FF),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1244 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0035: +.export test0035: far + ldx #$35 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$ed + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1112 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($FE),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1244 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0036: +.export test0036: far + ldx #$36 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0037: +.export test0037: far + ldx #$37 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($FF) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0038: +.export test0038: far + ldx #$38 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$ed + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1112 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($FE) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1234 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0039: +.export test0039: far + ldx #$39 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$ed + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003a: +.export test003a: far + ldx #$3a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$ed + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003b: +.export test003b: far + ldx #$3b + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$ed + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc ($12,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003c: +.export test003c: far + ldx #$3c + jsl init_test + lda #$ed + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$0133 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000134 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003d: +.export test003d: far + ldx #$3d + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$1232 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003e: +.export test003e: far + ldx #$3e + jsl init_test + lda #$ed + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000033 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test003f: +.export test003f: far + ldx #$3f + jsl init_test + lda #$ed + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $000133 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0040: +.export test0040: far + ldx #$40 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$ed + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1100 + rep #$de + sep #$21 + .a8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f0fdc + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0041: +.export test0041: far + ldx #$41 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$ed + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1112 + ldx #$3456 + ldy #$1110 + rep #$ce + sep #$31 + .a8 + .i8 + adc [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7ffeec + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0042: +.export test0042: far + ldx #$42 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$ed + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1112 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc [$FF],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f1244 + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0043: +.export test0043: far + ldx #$43 + jsl init_test + lda #$ed + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$0300 + rep #$de + sep #$21 + .a8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0044: +.export test0044: far + ldx #$44 + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1230 + rep #$ce + sep #$31 + .a8 + .i8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0045: +.export test0045: far + ldx #$45 + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0046: +.export test0046: far + ldx #$46 + jsl init_test + lda #$ed + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$0300 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0047: +.export test0047: far + ldx #$47 + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0048: +.export test0048: far + ldx #$48 + jsl init_test + lda #$ed + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0049: +.export test0049: far + ldx #$49 + jsl init_test + lda #$ed + sta $7f02ff + rep #$20 + .a16 + lda #$1112 + ldx #$0300 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f02ff + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004a: +.export test004a: far + ldx #$4a + jsl init_test + lda #$ed + sta $7f002f + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + rep #$ce + sep #$31 + .a8 + .i8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004b: +.export test004b: far + ldx #$4b + jsl init_test + lda #$ed + sta $7f002f + rep #$20 + .a16 + lda #$1112 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$de + sep #$21 + .a8 + .i8 + adc $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + lda $7f002f + cmp #$ed + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004c: +.export test004c: far + ldx #$4c + jsl init_test + rep #$20 + .a16 + lda #$1167 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + adc #$20 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e0 + bne @to_fail + ldx result_a + cpx #$1187 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004d: +.export test004d: far + ldx #$4d + jsl init_test + rep #$20 + .a16 + lda #$1180 + ldx #$3456 + ldy #$5678 + rep #$19 + sep #$e6 + .a8 + adc #$80 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0067 + bne @to_fail + ldx result_a + cpx #$1100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004e: +.export test004e: far + ldx #$4e + jsl init_test + rep #$20 + .a16 + lda #$1190 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + adc #$e0 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0061 + bne @to_fail + ldx result_a + cpx #$1171 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test004f: +.export test004f: far + ldx #$4f + jsl init_test + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and #$ef5c + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0050: +.export test0050: far + ldx #$50 + jsl init_test + lda #$5c + sta $7f1212 + lda #$ef + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + and ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1212 + cmp #$5c + bne @to_fail + lda $7f1213 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0051: +.export test0051: far + ldx #$51 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + and ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0052: +.export test0052: far + ldx #$52 + jsl init_test + lda #$5c + sta $7f1212 + lda #$ef + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1212 + cmp #$5c + bne @to_fail + lda $7f1213 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0053: +.export test0053: far + ldx #$53 + jsl init_test + lda #$5c + sta $000201 + lda #$ef + sta $000202 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000201 + cmp #$5c + bne @to_fail + lda $000202 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0054: +.export test0054: far + ldx #$54 + jsl init_test + lda #$5c + sta $000033 + lda #$ef + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000033 + cmp #$5c + bne @to_fail + lda $000034 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0055: +.export test0055: far + ldx #$55 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$5c + sta $7f1234 + lda #$ef + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1234 + cmp #$5c + bne @to_fail + lda $7f1235 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0056: +.export test0056: far + ldx #$56 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0057: +.export test0057: far + ldx #$57 + jsl init_test + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0058: +.export test0058: far + ldx #$58 + jsl init_test + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0059: +.export test0059: far + ldx #$59 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005a: +.export test005a: far + ldx #$5a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005b: +.export test005b: far + ldx #$5b + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005c: +.export test005c: far + ldx #$5c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$5c + sta $7f1234 + lda #$ef + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f1234 + cmp #$5c + bne @to_fail + lda $7f1235 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005d: +.export test005d: far + ldx #$5d + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005e: +.export test005e: far + ldx #$5e + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test005f: +.export test005f: far + ldx #$5f + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0060: +.export test0060: far + ldx #$60 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0061: +.export test0061: far + ldx #$61 + jsl init_test + lda #$5c + sta $000134 + lda #$ef + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000134 + cmp #$5c + bne @to_fail + lda $000135 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0062: +.export test0062: far + ldx #$62 + jsl init_test + lda #$5c + sta $000033 + lda #$ef + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $000033 + cmp #$5c + bne @to_fail + lda $000034 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0063: +.export test0063: far + ldx #$63 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$5c + sta $7f0fdc + lda #$ef + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f0fdc + cmp #$5c + bne @to_fail + lda $7f0fdd + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0064: +.export test0064: far + ldx #$64 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$5c + sta $7ffeec + lda #$ef + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7ffeec + cmp #$5c + bne @to_fail + lda $7ffeed + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0065: +.export test0065: far + ldx #$65 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$5c + sta $7effff + lda #$ef + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7effff + cmp #$5c + bne @to_fail + lda $7f0000 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0066: +.export test0066: far + ldx #$66 + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0067: +.export test0067: far + ldx #$67 + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0068: +.export test0068: far + ldx #$68 + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0069: +.export test0069: far + ldx #$69 + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006a: +.export test006a: far + ldx #$6a + jsl init_test + lda #$5c + sta $7f02ff + lda #$ef + sta $7f0300 + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f02ff + cmp #$5c + bne @to_fail + lda $7f0300 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006b: +.export test006b: far + ldx #$6b + jsl init_test + lda #$5c + sta $7f002f + lda #$ef + sta $7f0030 + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$ee5c + bne @to_fail + lda $7f002f + cmp #$5c + bne @to_fail + lda $7f0030 + cmp #$ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006c: +.export test006c: far + ldx #$6c + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + and #$aaaa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006d: +.export test006d: far + ldx #$6d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + and #$4300 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006e: +.export test006e: far + ldx #$6e + jsl init_test + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and #$df + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test006f: +.export test006f: far + ldx #$6f + jsl init_test + lda #$df + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and ($10,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1212 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0070: +.export test0070: far + ldx #$70 + jsl init_test + lda #$df + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$12fe + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and ($90,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1212 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0071: +.export test0071: far + ldx #$71 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($EF,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0072: +.export test0072: far + ldx #$72 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($F0,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0073: +.export test0073: far + ldx #$73 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$12fe + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($F6,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0074: +.export test0074: far + ldx #$74 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$12fe + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($F7,x) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0075: +.export test0075: far + ldx #$75 + jsl init_test + lda #$df + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000201 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0076: +.export test0076: far + ldx #$76 + jsl init_test + lda #$df + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $12,s + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000201 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0077: +.export test0077: far + ldx #$77 + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0078: +.export test0078: far + ldx #$78 + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0079: +.export test0079: far + ldx #$79 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$df + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and [$34] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007a: +.export test007a: far + ldx #$7a + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$df + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and [$FF] + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007b: +.export test007b: far + ldx #$7b + jsl init_test + lda #$df + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007c: +.export test007c: far + ldx #$7c + jsl init_test + lda #$df + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007d: +.export test007d: far + ldx #$7d + jsl init_test + lda #$df + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007e: +.export test007e: far + ldx #$7e + jsl init_test + lda #$df + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $7EFFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7effff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test007f: +.export test007f: far + ldx #$7f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$df + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0080: +.export test0080: far + ldx #$80 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$df + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and ($34),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0081: +.export test0081: far + ldx #$81 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$df + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($FF),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1244 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0082: +.export test0082: far + ldx #$82 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$df + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($FE),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1244 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0083: +.export test0083: far + ldx #$83 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and ($34) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0084: +.export test0084: far + ldx #$84 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($FF) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0085: +.export test0085: far + ldx #$85 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$df + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($FE) + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1234 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0086: +.export test0086: far + ldx #$86 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$df + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0087: +.export test0087: far + ldx #$87 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$df + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and ($10,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0088: +.export test0088: far + ldx #$88 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$df + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and ($12,s),y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0089: +.export test0089: far + ldx #$89 + jsl init_test + lda #$df + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000134 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008a: +.export test008a: far + ldx #$8a + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008b: +.export test008b: far + ldx #$8b + jsl init_test + lda #$df + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000033 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008c: +.export test008c: far + ldx #$8c + jsl init_test + lda #$df + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $000133 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008d: +.export test008d: far + ldx #$8d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$df + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f0fdc + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008e: +.export test008e: far + ldx #$8e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$df + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + and [$34],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7ffeec + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test008f: +.export test008f: far + ldx #$8f + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$df + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and [$FF],y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f1244 + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0090: +.export test0090: far + ldx #$90 + jsl init_test + lda #$df + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0091: +.export test0091: far + ldx #$91 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0092: +.export test0092: far + ldx #$92 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $FFFF,y + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0093: +.export test0093: far + ldx #$93 + jsl init_test + lda #$df + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0094: +.export test0094: far + ldx #$94 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0095: +.export test0095: far + ldx #$95 + jsl init_test + lda #$df + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0096: +.export test0096: far + ldx #$96 + jsl init_test + lda #$df + sta $7f02ff + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f02ff + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0097: +.export test0097: far + ldx #$97 + jsl init_test + lda #$df + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0098: +.export test0098: far + ldx #$98 + jsl init_test + lda #$df + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + and $7EFFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12de + bne @to_fail + lda $7f002f + cmp #$df + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0099: +.export test0099: far + ldx #$99 + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + and #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009a: +.export test009a: far + ldx #$9a + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009b: +.export test009b: far + ldx #$9b + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009c: +.export test009c: far + ldx #$9c + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009d: +.export test009d: far + ldx #$9d + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009e: +.export test009e: far + ldx #$9e + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test009f: +.export test009f: far + ldx #$9f + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a0: +.export test00a0: far + ldx #$a0 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a1: +.export test00a1: far + ldx #$a1 + jsl init_test + rep #$20 + .a16 + lda #$4111 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$8222 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a2: +.export test00a2: far + ldx #$a2 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$22 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a3: +.export test00a3: far + ldx #$a3 + jsl init_test + lda #$11 + sta $7effff + lda #$41 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a4: +.export test00a4: far + ldx #$a4 + jsl init_test + lda #$11 + sta $000134 + lda #$41 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$22 + bne @to_fail + lda $000135 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a5: +.export test00a5: far + ldx #$a5 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$22 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a6: +.export test00a6: far + ldx #$a6 + jsl init_test + lda #$11 + sta $7f02ff + lda #$41 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$22 + bne @to_fail + lda $7f0300 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a7: +.export test00a7: far + ldx #$a7 + jsl init_test + lda #$11 + sta $7f002f + lda #$41 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$22 + bne @to_fail + lda $7f0030 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a8: +.export test00a8: far + ldx #$a8 + jsl init_test + rep #$20 + .a16 + lda #$1280 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00a9: +.export test00a9: far + ldx #$a9 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00aa: +.export test00aa: far + ldx #$aa + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ab: +.export test00ab: far + ldx #$ab + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ac: +.export test00ac: far + ldx #$ac + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ad: +.export test00ad: far + ldx #$ad + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ae: +.export test00ae: far + ldx #$ae + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00af: +.export test00af: far + ldx #$af + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b0: +.export test00b0: far + ldx #$b0 + jsl init_test + lda #$80 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + asl $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b1: +.export test00b1: far + ldx #$b1 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b2: +.export test00b2: far + ldx #$b2 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b3: +.export test00b3: far + ldx #$b3 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b4: +.export test00b4: far + ldx #$b4 + jsl init_test + rep #$20 + .a16 + lda #$1241 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl a + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1282 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b5: +.export test00b5: far + ldx #$b5 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b6: +.export test00b6: far + ldx #$b6 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + asl $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b7: +.export test00b7: far + ldx #$b7 + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b8: +.export test00b8: far + ldx #$b8 + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + asl $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00b9: +.export test00b9: far + ldx #$b9 + jsl init_test + lda #$41 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ba: +.export test00ba: far + ldx #$ba + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bb: +.export test00bb: far + ldx #$bb + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + asl $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bc: +.export test00bc: far + ldx #$bc + jsl init_test + lda #$41 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + asl $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bd: +.export test00bd: far + ldx #$bd + jsl init_test + lda #$41 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00be: +.export test00be: far + ldx #$be + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00bf: +.export test00bf: far + ldx #$bf + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + asl $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c0: +.export test00c0: far + ldx #$c0 + jsl init_test + rep #$20 + .a16 + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit #$1234 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c1: +.export test00c1: far + ldx #$c1 + jsl init_test + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit #$aaaa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c2: +.export test00c2: far + ldx #$c2 + jsl init_test + rep #$20 + .a16 + lda #$0056 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$0056 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c3: +.export test00c3: far + ldx #$c3 + jsl init_test + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit #$aa + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c4: +.export test00c4: far + ldx #$c4 + jsl init_test + lda #$34 + sta $000033 + lda #$52 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c5: +.export test00c5: far + ldx #$c5 + jsl init_test + lda #$34 + sta $7effff + lda #$52 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7effff + cmp #$34 + bne @to_fail + lda $7f0000 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c6: +.export test00c6: far + ldx #$c6 + jsl init_test + lda #$34 + sta $000134 + lda #$52 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000134 + cmp #$34 + bne @to_fail + lda $000135 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c7: +.export test00c7: far + ldx #$c7 + jsl init_test + lda #$34 + sta $000033 + lda #$52 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9377 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c8: +.export test00c8: far + ldx #$c8 + jsl init_test + lda #$34 + sta $7f02ff + lda #$52 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7f02ff + cmp #$34 + bne @to_fail + lda $7f0300 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00c9: +.export test00c9: far + ldx #$c9 + jsl init_test + lda #$34 + sta $7f002f + lda #$52 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9377 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$9377 + bne @to_fail + lda $7f002f + cmp #$34 + bne @to_fail + lda $7f0030 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ca: +.export test00ca: far + ldx #$ca + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cb: +.export test00cb: far + ldx #$cb + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + lda $7f0000 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cc: +.export test00cc: far + ldx #$cc + jsl init_test + lda #$aa + sta $000134 + lda #$aa + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000134 + cmp #$aa + bne @to_fail + lda $000135 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cd: +.export test00cd: far + ldx #$cd + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0092 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ce: +.export test00ce: far + ldx #$ce + jsl init_test + lda #$aa + sta $7f02ff + lda #$aa + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0082 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7f02ff + cmp #$aa + bne @to_fail + lda $7f0300 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00cf: +.export test00cf: far + ldx #$cf + jsl init_test + lda #$aa + sta $7f002f + lda #$aa + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0092 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7f002f + cmp #$aa + bne @to_fail + lda $7f0030 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d0: +.export test00d0: far + ldx #$d0 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d1: +.export test00d1: far + ldx #$d1 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0170 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d2: +.export test00d2: far + ldx #$d2 + jsl init_test + lda #$52 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7effff + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d3: +.export test00d3: far + ldx #$d3 + jsl init_test + lda #$52 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0170 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7effff + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d4: +.export test00d4: far + ldx #$d4 + jsl init_test + lda #$52 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000134 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d5: +.export test00d5: far + ldx #$d5 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0070 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d6: +.export test00d6: far + ldx #$d6 + jsl init_test + lda #$52 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0093 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0170 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000033 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d7: +.export test00d7: far + ldx #$d7 + jsl init_test + lda #$52 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$0093 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0170 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $000133 + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d8: +.export test00d8: far + ldx #$d8 + jsl init_test + lda #$52 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0060 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7f02ff + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00d9: +.export test00d9: far + ldx #$d9 + jsl init_test + lda #$52 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0070 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7f002f + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00da: +.export test00da: far + ldx #$da + jsl init_test + lda #$52 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0093 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0170 + bne @to_fail + ldx result_a + cpx #$0093 + bne @to_fail + lda $7f002f + cmp #$52 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00db: +.export test00db: far + ldx #$db + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00dc: +.export test00dc: far + ldx #$dc + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $34 + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00dd: +.export test00dd: far + ldx #$dd + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00de: +.export test00de: far + ldx #$de + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FFFF + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00df: +.export test00df: far + ldx #$df + jsl init_test + lda #$aa + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000134 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e0: +.export test00e0: far + ldx #$e0 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e1: +.export test00e1: far + ldx #$e1 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $02,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e2: +.export test00e2: far + ldx #$e2 + jsl init_test + lda #$aa + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$0055 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000133 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e3: +.export test00e3: far + ldx #$e3 + jsl init_test + lda #$aa + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7f02ff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e4: +.export test00e4: far + ldx #$e4 + jsl init_test + lda #$aa + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7f002f + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e5: +.export test00e5: far + ldx #$e5 + jsl init_test + lda #$aa + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + bit $FFFF,x + jsr bank0_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b2 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7f002f + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test00e6 + +.segment "BANK1" + +bank1_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test00e6: +.export test00e6: far + ldx #$e6 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$80 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank0_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e7: +.export test00e7: far + ldx #$e7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$80 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e8: +.export test00e8: far + ldx #$e8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$90 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00e9: +.export test00e9: far + ldx #$e9 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$90 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ea: +.export test00ea: far + ldx #$ea + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + bcc @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0001 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00eb: +.export test00eb: far + ldx #$eb + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$b0 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ec: +.export test00ec: far + ldx #$ec + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$b0 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ed: +.export test00ed: far + ldx #$ed + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bcs @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ee: +.export test00ee: far + ldx #$ee + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$d0 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ef: +.export test00ef: far + ldx #$ef + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$d0 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f0: +.export test00f0: far + ldx #$f0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + bne @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f1: +.export test00f1: far + ldx #$f1 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$f0 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f2: +.export test00f2: far + ldx #$f2 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$f0 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f3: +.export test00f3: far + ldx #$f3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + beq @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f4: +.export test00f4: far + ldx #$f4 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$10 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f5: +.export test00f5: far + ldx #$f5 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$10 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f6: +.export test00f6: far + ldx #$f6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + bpl @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f7: +.export test00f7: far + ldx #$f7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$30 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f8: +.export test00f8: far + ldx #$f8 + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$30 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$7f + sep #$80 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00f9: +.export test00f9: far + ldx #$f9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bmi @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fa: +.export test00fa: far + ldx #$fa + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$50 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fb: +.export test00fb: far + ldx #$fb + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$50 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fc: +.export test00fc: far + ldx #$fc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + bvc @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fd: +.export test00fd: far + ldx #$fd + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0041 + lda #<@ok + sta $7e0042 + lda #>@ok + sta $7e0043 + lda #^@ok + sta $7e0044 + lda #$70 + sta $7effc0 + lda #$7f + sta $7effc1 + lda #$db + sta $7effc2 + lda #$db + sta $7f0041 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + jml $7EFFC0 + + jsr bank1_save_results + bra @to_fail +@ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00fe: +.export test00fe: far + ldx #$fe + jsl init_test + lda #$5C ; jmp long opcode + sta $7fffc2 + lda #<@ok + sta $7fffc3 + lda #>@ok + sta $7fffc4 + lda #^@ok + sta $7fffc5 + lda #$70 + sta $7f0040 + lda #$80 + sta $7f0041 + lda #$db + sta $7f0042 + lda #$db + sta $7effc2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$bf + sep #$40 + jml $7F0040 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0040 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test00ff: +.export test00ff: far + ldx #$ff + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + bvs @not_ok + bra @ok +@not_ok: + jsr bank1_save_results + bra @to_fail +@ok: + + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0100: +.export test0100: far + ldx #$100 + jsl init_test + lda #$5C ; jmp long opcode + sta $1000 + lda #<@ok + sta $1001 + lda #>@ok + sta $1002 + lda #^@ok + sta $1003 + lda #$00 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f4 + sep #$0b + jml $7e8000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0007 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01eb + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + lda $0001ed + cmp #$02 + bne @to_fail + lda $0001ee + cmp #$80 + bne @to_fail + lda $0001ec + cmp #$0b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $1000 + bra @next_test +@to_fail: + jml fail +@next_test: + +test0101: +.export test0101: far + ldx #$101 + jsl init_test + lda #$5C ; jmp long opcode + sta $1008 + lda #<@ok + sta $1009 + lda #>@ok + sta $100a + lda #^@ok + sta $100b + lda #$00 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$f4 + sep #$0b + .a8 + .i8 + jml $7e8000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0137 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fd + bne @to_fail + lda $0001ff + cmp #$02 + bne @to_fail + lda $000100 + cmp #$80 + bne @to_fail + lda $0001fe + cmp #$3b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $1008 + bra @next_test +@to_fail: + jml fail +@next_test: + +test0102: +.export test0102: far + ldx #$102 + jsl init_test + lda #$5C ; jmp long opcode + sta $1004 + lda #<@ok + sta $1005 + lda #>@ok + sta $1006 + lda #^@ok + sta $1007 + lda #$02 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f4 + sep #$0b + jml $7e8000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0007 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01eb + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + lda $0001ed + cmp #$02 + bne @to_fail + lda $0001ee + cmp #$80 + bne @to_fail + lda $0001ec + cmp #$0b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $1004 + bra @next_test +@to_fail: + jml fail +@next_test: + +test0103: +.export test0103: far + ldx #$103 + jsl init_test + lda #$5C ; jmp long opcode + sta $100c + lda #<@ok + sta $100d + lda #>@ok + sta $100e + lda #^@ok + sta $100f + lda #$02 + sta $7e8000 + lda #$db + sta $7e8001 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$f4 + sep #$0b + .a8 + .i8 + jml $7e8000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0137 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fd + bne @to_fail + lda $0001ff + cmp #$02 + bne @to_fail + lda $000100 + cmp #$80 + bne @to_fail + lda $0001fe + cmp #$3b + bne @to_fail + ldx #$1EF + txs + lda #$db + sta $100c + bra @next_test +@to_fail: + jml fail +@next_test: + +test0104: +.export test0104: far + ldx #$104 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7002 + lda #<@ok + sta $7e7003 + lda #>@ok + sta $7e7004 + lda #^@ok + sta $7e7005 + lda #$82 + sta $7ef000 + lda #$ff + sta $7ef001 + lda #$7f + sta $7ef002 + lda #$db + sta $7ef003 + lda #$db + sta $7f7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7EF000 + @ok: + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0105: +.export test0105: far + ldx #$105 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + clc + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fe + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0106: +.export test0106: far + ldx #$106 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + clc + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0107: +.export test0107: far + ldx #$107 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cld + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00f7 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0108: +.export test0108: far + ldx #$108 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cld + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0109: +.export test0109: far + ldx #$109 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cli + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fb + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010a: +.export test010a: far + ldx #$10a + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cli + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010b: +.export test010b: far + ldx #$10b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + clv + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00bf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010c: +.export test010c: far + ldx #$10c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + clv + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010d: +.export test010d: far + ldx #$10d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sec + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0001 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010e: +.export test010e: far + ldx #$10e + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sec + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test010f: +.export test010f: far + ldx #$10f + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sed + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0110: +.export test0110: far + ldx #$110 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sed + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0111: +.export test0111: far + ldx #$111 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sei + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0004 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0112: +.export test0112: far + ldx #$112 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sei + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0113: +.export test0113: far + ldx #$113 + jsl init_test + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0114: +.export test0114: far + ldx #$114 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0115: +.export test0115: far + ldx #$115 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcd + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0116: +.export test0116: far + ldx #$116 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcd + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0117: +.export test0117: far + ldx #$117 + jsl init_test + lda #$cd + sta $000201 + lda #$ab + sta $000202 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + lda $000202 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0118: +.export test0118: far + ldx #$118 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0119: +.export test0119: far + ldx #$119 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011a: +.export test011a: far + ldx #$11a + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011b: +.export test011b: far + ldx #$11b + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011c: +.export test011c: far + ldx #$11c + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011d: +.export test011d: far + ldx #$11d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011e: +.export test011e: far + ldx #$11e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test011f: +.export test011f: far + ldx #$11f + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0120: +.export test0120: far + ldx #$120 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0121: +.export test0121: far + ldx #$121 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0122: +.export test0122: far + ldx #$122 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0123: +.export test0123: far + ldx #$123 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0124: +.export test0124: far + ldx #$124 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0125: +.export test0125: far + ldx #$125 + jsl init_test + lda #$cd + sta $000134 + lda #$ab + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + lda $000135 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0126: +.export test0126: far + ldx #$126 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0127: +.export test0127: far + ldx #$127 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0128: +.export test0128: far + ldx #$128 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0129: +.export test0129: far + ldx #$129 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012a: +.export test012a: far + ldx #$12a + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012b: +.export test012b: far + ldx #$12b + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012c: +.export test012c: far + ldx #$12c + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012d: +.export test012d: far + ldx #$12d + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012e: +.export test012e: far + ldx #$12e + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test012f: +.export test012f: far + ldx #$12f + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0130: +.export test0130: far + ldx #$130 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0131: +.export test0131: far + ldx #$131 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0132: +.export test0132: far + ldx #$132 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ff + sep #$00 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0133: +.export test0133: far + ldx #$133 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0134: +.export test0134: far + ldx #$134 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0135: +.export test0135: far + ldx #$135 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ff + sep #$00 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0136: +.export test0136: far + ldx #$136 + jsl init_test + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0137: +.export test0137: far + ldx #$137 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0138: +.export test0138: far + ldx #$138 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcc + ldx #$0123 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0139: +.export test0139: far + ldx #$139 + jsl init_test + lda #$cd + sta $7f1212 + lda #$ab + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcc + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + lda $7f1213 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013a: +.export test013a: far + ldx #$13a + jsl init_test + lda #$cd + sta $000201 + lda #$ab + sta $000202 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + lda $000202 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013b: +.export test013b: far + ldx #$13b + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013c: +.export test013c: far + ldx #$13c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013d: +.export test013d: far + ldx #$13d + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013e: +.export test013e: far + ldx #$13e + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test013f: +.export test013f: far + ldx #$13f + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0140: +.export test0140: far + ldx #$140 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0141: +.export test0141: far + ldx #$141 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0142: +.export test0142: far + ldx #$142 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0143: +.export test0143: far + ldx #$143 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$ab + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + lda $7f1235 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0144: +.export test0144: far + ldx #$144 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0145: +.export test0145: far + ldx #$145 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0146: +.export test0146: far + ldx #$146 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0147: +.export test0147: far + ldx #$147 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0148: +.export test0148: far + ldx #$148 + jsl init_test + lda #$cd + sta $000134 + lda #$ab + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + lda $000135 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0149: +.export test0149: far + ldx #$149 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014a: +.export test014a: far + ldx #$14a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + lda #$ab + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + lda $7f0fdd + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014b: +.export test014b: far + ldx #$14b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + lda #$ab + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + lda $7ffeed + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014c: +.export test014c: far + ldx #$14c + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014d: +.export test014d: far + ldx #$14d + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014e: +.export test014e: far + ldx #$14e + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test014f: +.export test014f: far + ldx #$14f + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0150: +.export test0150: far + ldx #$150 + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0151: +.export test0151: far + ldx #$151 + jsl init_test + lda #$cd + sta $7f02ff + lda #$ab + sta $7f0300 + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + lda $7f0300 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0152: +.export test0152: far + ldx #$152 + jsl init_test + lda #$cd + sta $7f002f + lda #$ab + sta $7f0030 + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + lda $7f0030 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0153: +.export test0153: far + ldx #$153 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0154: +.export test0154: far + ldx #$154 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0155: +.export test0155: far + ldx #$155 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$30 + sep #$cf + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0156: +.export test0156: far + ldx #$156 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy #$abcd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0157: +.export test0157: far + ldx #$157 + jsl init_test + lda #$cd + sta $000033 + lda #$ab + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + lda $000034 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0158: +.export test0158: far + ldx #$158 + jsl init_test + lda #$cd + sta $7effff + lda #$ab + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$30 + sep #$cf + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcc + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + lda $7f0000 + cmp #$ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0159: +.export test0159: far + ldx #$159 + jsl init_test + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015a: +.export test015a: far + ldx #$15a + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015b: +.export test015b: far + ldx #$15b + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcd + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015c: +.export test015c: far + ldx #$15c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($EF,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015d: +.export test015d: far + ldx #$15d + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($F0,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test015e: +.export test015e: far + ldx #$15e + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$abcd + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($F6,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test015f: +.export test015f: far + ldx #$15f + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$abcd + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($F7,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0160: +.export test0160: far + ldx #$160 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0161: +.export test0161: far + ldx #$161 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0162: +.export test0162: far + ldx #$162 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0163: +.export test0163: far + ldx #$163 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0164: +.export test0164: far + ldx #$164 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0165: +.export test0165: far + ldx #$165 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp [$FF] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0166: +.export test0166: far + ldx #$166 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0167: +.export test0167: far + ldx #$167 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0168: +.export test0168: far + ldx #$168 + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0169: +.export test0169: far + ldx #$169 + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016a: +.export test016a: far + ldx #$16a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016b: +.export test016b: far + ldx #$16b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016c: +.export test016c: far + ldx #$16c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($FF),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016d: +.export test016d: far + ldx #$16d + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$cd + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$abcd + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($FE),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016e: +.export test016e: far + ldx #$16e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test016f: +.export test016f: far + ldx #$16f + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($FF) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0170: +.export test0170: far + ldx #$170 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$abcd + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($FE) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0171: +.export test0171: far + ldx #$171 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0172: +.export test0172: far + ldx #$172 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0173: +.export test0173: far + ldx #$173 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp ($12,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0174: +.export test0174: far + ldx #$174 + jsl init_test + lda #$cd + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0175: +.export test0175: far + ldx #$175 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0176: +.export test0176: far + ldx #$176 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0177: +.export test0177: far + ldx #$177 + jsl init_test + lda #$cd + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $FF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $000133 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0178: +.export test0178: far + ldx #$178 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0179: +.export test0179: far + ldx #$179 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcd + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017a: +.export test017a: far + ldx #$17a + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$cd + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcd + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp [$FF],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017b: +.export test017b: far + ldx #$17b + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017c: +.export test017c: far + ldx #$17c + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017d: +.export test017d: far + ldx #$17d + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017e: +.export test017e: far + ldx #$17e + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test017f: +.export test017f: far + ldx #$17f + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0180: +.export test0180: far + ldx #$180 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0181: +.export test0181: far + ldx #$181 + jsl init_test + lda #$cd + sta $7f02ff + rep #$20 + .a16 + lda #$abcd + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0182: +.export test0182: far + ldx #$182 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0183: +.export test0183: far + ldx #$183 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcd + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$abcd + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0184: +.export test0184: far + ldx #$184 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0185: +.export test0185: far + ldx #$185 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0186: +.export test0186: far + ldx #$186 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcd + ldy #$5678 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0187: +.export test0187: far + ldx #$187 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$ef + sep #$10 + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0188: +.export test0188: far + ldx #$188 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0189: +.export test0189: far + ldx #$189 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018a: +.export test018a: far + ldx #$18a + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018b: +.export test018b: far + ldx #$18b + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcd + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018c: +.export test018c: far + ldx #$18c + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$ef + sep #$10 + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018d: +.export test018d: far + ldx #$18d + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018e: +.export test018e: far + ldx #$18e + jsl init_test + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test018f: +.export test018f: far + ldx #$18f + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0190: +.export test0190: far + ldx #$190 + jsl init_test + lda #$cd + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$abcc + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1212 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0191: +.export test0191: far + ldx #$191 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($EF,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0192: +.export test0192: far + ldx #$192 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($F0,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0193: +.export test0193: far + ldx #$193 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$abcc + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($F6,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0194: +.export test0194: far + ldx #$194 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$abcc + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($F7,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0195: +.export test0195: far + ldx #$195 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0196: +.export test0196: far + ldx #$196 + jsl init_test + lda #$cd + sta $000201 + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000201 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0197: +.export test0197: far + ldx #$197 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0198: +.export test0198: far + ldx #$198 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0199: +.export test0199: far + ldx #$199 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019a: +.export test019a: far + ldx #$19a + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$cd + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp [$FF] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019b: +.export test019b: far + ldx #$19b + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019c: +.export test019c: far + ldx #$19c + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019d: +.export test019d: far + ldx #$19d + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019e: +.export test019e: far + ldx #$19e + jsl init_test + lda #$cd + sta $7effff + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test019f: +.export test019f: far + ldx #$19f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a0: +.export test01a0: far + ldx #$1a0 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a1: +.export test01a1: far + ldx #$1a1 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($FF),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a2: +.export test01a2: far + ldx #$1a2 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$cd + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$abcc + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($FE),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a3: +.export test01a3: far + ldx #$1a3 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a4: +.export test01a4: far + ldx #$1a4 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($FF) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a5: +.export test01a5: far + ldx #$1a5 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$cd + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$abcc + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($FE) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1234 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a6: +.export test01a6: far + ldx #$1a6 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a7: +.export test01a7: far + ldx #$1a7 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a8: +.export test01a8: far + ldx #$1a8 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$cd + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1110 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp ($12,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01a9: +.export test01a9: far + ldx #$1a9 + jsl init_test + lda #$cd + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000134 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01aa: +.export test01aa: far + ldx #$1aa + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ab: +.export test01ab: far + ldx #$1ab + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ac: +.export test01ac: far + ldx #$1ac + jsl init_test + lda #$cd + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $FF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $000133 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ad: +.export test01ad: far + ldx #$1ad + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$cd + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f0fdc + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ae: +.export test01ae: far + ldx #$1ae + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$cd + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$abcc + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + cmp [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7ffeec + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01af: +.export test01af: far + ldx #$1af + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$cd + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$abcc + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp [$FF],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f1244 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b0: +.export test01b0: far + ldx #$1b0 + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b1: +.export test01b1: far + ldx #$1b1 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b2: +.export test01b2: far + ldx #$1b2 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$3456 + ldy #$1230 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b3: +.export test01b3: far + ldx #$1b3 + jsl init_test + lda #$cd + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b4: +.export test01b4: far + ldx #$1b4 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b5: +.export test01b5: far + ldx #$1b5 + jsl init_test + lda #$cd + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b6: +.export test01b6: far + ldx #$1b6 + jsl init_test + lda #$cd + sta $7f02ff + rep #$20 + .a16 + lda #$abcc + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f02ff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b7: +.export test01b7: far + ldx #$1b7 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b8: +.export test01b8: far + ldx #$1b8 + jsl init_test + lda #$cd + sta $7f002f + rep #$20 + .a16 + lda #$abcc + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + cmp $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$abcc + bne @to_fail + lda $7f002f + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01b9: +.export test01b9: far + ldx #$1b9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ba: +.export test01ba: far + ldx #$1ba + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bb: +.export test01bb: far + ldx #$1bb + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$abcc + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + cpx $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bc: +.export test01bc: far + ldx #$1bc + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + rep #$20 + sep #$df + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bd: +.export test01bd: far + ldx #$1bd + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$abcc + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + cpx $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cc + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01be: +.export test01be: far + ldx #$1be + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy #$cd + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01bf: +.export test01bf: far + ldx #$1bf + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c0: +.export test01c0: far + ldx #$1c0 + jsl init_test + lda #$cd + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$abcc + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + cpy $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c1: +.export test01c1: far + ldx #$1c1 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + rep #$20 + sep #$df + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c2: +.export test01c2: far + ldx #$1c2 + jsl init_test + lda #$cd + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcc + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + cpy $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cc + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c3: +.export test01c3: far + ldx #$1c3 + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c4: +.export test01c4: far + ldx #$1c4 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c5: +.export test01c5: far + ldx #$1c5 + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c6: +.export test01c6: far + ldx #$1c6 + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c7: +.export test01c7: far + ldx #$1c7 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c8: +.export test01c8: far + ldx #$1c8 + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01c9: +.export test01c9: far + ldx #$1c9 + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ca: +.export test01ca: far + ldx #$1ca + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0001 + ldy #$5678 + rep #$ff + sep #$00 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cb: +.export test01cb: far + ldx #$1cb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0001 + rep #$ff + sep #$00 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cc: +.export test01cc: far + ldx #$1cc + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cd: +.export test01cd: far + ldx #$1cd + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ce: +.export test01ce: far + ldx #$1ce + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + lda $7f0000 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01cf: +.export test01cf: far + ldx #$1cf + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$ff + bne @to_fail + lda $000135 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d0: +.export test01d0: far + ldx #$1d0 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d1: +.export test01d1: far + ldx #$1d1 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$ff + bne @to_fail + lda $7f0300 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d2: +.export test01d2: far + ldx #$1d2 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$ff + bne @to_fail + lda $7f0030 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d3: +.export test01d3: far + ldx #$1d3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$30 + sep #$cf + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ffff + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d4: +.export test01d4: far + ldx #$1d4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$30 + sep #$cf + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$ffff + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d5: +.export test01d5: far + ldx #$1d5 + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d6: +.export test01d6: far + ldx #$1d6 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d7: +.export test01d7: far + ldx #$1d7 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d8: +.export test01d8: far + ldx #$1d8 + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01d9: +.export test01d9: far + ldx #$1d9 + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01da: +.export test01da: far + ldx #$1da + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01db: +.export test01db: far + ldx #$1db + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01dc: +.export test01dc: far + ldx #$1dc + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01dd: +.export test01dd: far + ldx #$1dd + jsl init_test + lda #$01 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + dec $FF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01de: +.export test01de: far + ldx #$1de + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01df: +.export test01df: far + ldx #$1df + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e0: +.export test01e0: far + ldx #$1e0 + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e1: +.export test01e1: far + ldx #$1e1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0001 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e2: +.export test01e2: far + ldx #$1e2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0001 + rep #$ef + sep #$10 + .i8 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e3: +.export test01e3: far + ldx #$1e3 + jsl init_test + rep #$20 + .a16 + lda #$1200 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$12ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e4: +.export test01e4: far + ldx #$1e4 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e5: +.export test01e5: far + ldx #$1e5 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + dec $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e6: +.export test01e6: far + ldx #$1e6 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e7: +.export test01e7: far + ldx #$1e7 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + dec $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e8: +.export test01e8: far + ldx #$1e8 + jsl init_test + lda #$00 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01e9: +.export test01e9: far + ldx #$1e9 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ea: +.export test01ea: far + ldx #$1ea + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + dec $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01eb: +.export test01eb: far + ldx #$1eb + jsl init_test + lda #$00 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + dec $FF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ec: +.export test01ec: far + ldx #$1ec + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ed: +.export test01ed: far + ldx #$1ed + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ee: +.export test01ee: far + ldx #$1ee + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + dec $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ef: +.export test01ef: far + ldx #$1ef + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + dex + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ff + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f0: +.export test01f0: far + ldx #$1f0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + dey + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ff + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f1: +.export test01f1: far + ldx #$1f1 + jsl init_test + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor #$6f8c + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f2: +.export test01f2: far + ldx #$1f2 + jsl init_test + lda #$8c + sta $7f1212 + lda #$6f + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + eor ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1212 + cmp #$8c + bne @to_fail + lda $7f1213 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f3: +.export test01f3: far + ldx #$1f3 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + eor ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f4: +.export test01f4: far + ldx #$1f4 + jsl init_test + lda #$8c + sta $7f1212 + lda #$6f + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$feff + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1212 + cmp #$8c + bne @to_fail + lda $7f1213 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f5: +.export test01f5: far + ldx #$1f5 + jsl init_test + lda #$8c + sta $000201 + lda #$6f + sta $000202 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000201 + cmp #$8c + bne @to_fail + lda $000202 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f6: +.export test01f6: far + ldx #$1f6 + jsl init_test + lda #$8c + sta $000033 + lda #$6f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000033 + cmp #$8c + bne @to_fail + lda $000034 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f7: +.export test01f7: far + ldx #$1f7 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8c + sta $7f1234 + lda #$6f + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1234 + cmp #$8c + bne @to_fail + lda $7f1235 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f8: +.export test01f8: far + ldx #$1f8 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01f9: +.export test01f9: far + ldx #$1f9 + jsl init_test + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fa: +.export test01fa: far + ldx #$1fa + jsl init_test + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fb: +.export test01fb: far + ldx #$1fb + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fc: +.export test01fc: far + ldx #$1fc + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fd: +.export test01fd: far + ldx #$1fd + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01fe: +.export test01fe: far + ldx #$1fe + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8c + sta $7f1234 + lda #$6f + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f1234 + cmp #$8c + bne @to_fail + lda $7f1235 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test01ff: +.export test01ff: far + ldx #$1ff + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0200: +.export test0200: far + ldx #$200 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0201: +.export test0201: far + ldx #$201 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0202: +.export test0202: far + ldx #$202 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0203: +.export test0203: far + ldx #$203 + jsl init_test + lda #$8c + sta $000134 + lda #$6f + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000134 + cmp #$8c + bne @to_fail + lda $000135 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0204: +.export test0204: far + ldx #$204 + jsl init_test + lda #$8c + sta $000033 + lda #$6f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $000033 + cmp #$8c + bne @to_fail + lda $000034 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0205: +.export test0205: far + ldx #$205 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8c + sta $7f0fdc + lda #$6f + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f0fdc + cmp #$8c + bne @to_fail + lda $7f0fdd + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0206: +.export test0206: far + ldx #$206 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8c + sta $7ffeec + lda #$6f + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7ffeec + cmp #$8c + bne @to_fail + lda $7ffeed + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0207: +.export test0207: far + ldx #$207 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$8c + sta $7effff + lda #$6f + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$feff + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7effff + cmp #$8c + bne @to_fail + lda $7f0000 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0208: +.export test0208: far + ldx #$208 + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0209: +.export test0209: far + ldx #$209 + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020a: +.export test020a: far + ldx #$20a + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020b: +.export test020b: far + ldx #$20b + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020c: +.export test020c: far + ldx #$20c + jsl init_test + lda #$8c + sta $7f02ff + lda #$6f + sta $7f0300 + rep #$20 + .a16 + lda #$feff + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f02ff + cmp #$8c + bne @to_fail + lda $7f0300 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020d: +.export test020d: far + ldx #$20d + jsl init_test + lda #$8c + sta $7f002f + lda #$6f + sta $7f0030 + rep #$20 + .a16 + lda #$feff + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$9173 + bne @to_fail + lda $7f002f + cmp #$8c + bne @to_fail + lda $7f0030 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020e: +.export test020e: far + ldx #$20e + jsl init_test + rep #$20 + .a16 + lda #$aaaa + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + eor #$aaaa + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test020f: +.export test020f: far + ldx #$20f + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + eor #$4334 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$5100 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0210: +.export test0210: far + ldx #$210 + jsl init_test + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor #$6f + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0211: +.export test0211: far + ldx #$211 + jsl init_test + lda #$6f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor ($10,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1212 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0212: +.export test0212: far + ldx #$212 + jsl init_test + lda #$6f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$12fe + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($90,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1212 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0213: +.export test0213: far + ldx #$213 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($EF,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0214: +.export test0214: far + ldx #$214 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($F0,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0215: +.export test0215: far + ldx #$215 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$12fe + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($F6,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0216: +.export test0216: far + ldx #$216 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$12fe + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($F7,x) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0217: +.export test0217: far + ldx #$217 + jsl init_test + lda #$6f + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000201 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0218: +.export test0218: far + ldx #$218 + jsl init_test + lda #$6f + sta $000201 + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $12,s + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000201 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0219: +.export test0219: far + ldx #$219 + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021a: +.export test021a: far + ldx #$21a + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021b: +.export test021b: far + ldx #$21b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$6f + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor [$34] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021c: +.export test021c: far + ldx #$21c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$6f + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor [$FF] + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021d: +.export test021d: far + ldx #$21d + jsl init_test + lda #$6f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021e: +.export test021e: far + ldx #$21e + jsl init_test + lda #$6f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test021f: +.export test021f: far + ldx #$21f + jsl init_test + lda #$6f + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0220: +.export test0220: far + ldx #$220 + jsl init_test + lda #$6f + sta $7effff + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $7EFFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7effff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0221: +.export test0221: far + ldx #$221 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$6f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0222: +.export test0222: far + ldx #$222 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$6f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($34),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0223: +.export test0223: far + ldx #$223 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$6f + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($FF),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1244 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0224: +.export test0224: far + ldx #$224 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$6f + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($FE),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1244 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0225: +.export test0225: far + ldx #$225 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor ($34) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0226: +.export test0226: far + ldx #$226 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($FF) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0227: +.export test0227: far + ldx #$227 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$6f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$12fe + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($FE) + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1234 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0228: +.export test0228: far + ldx #$228 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$6f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0229: +.export test0229: far + ldx #$229 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$6f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor ($10,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022a: +.export test022a: far + ldx #$22a + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$6f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor ($12,s),y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022b: +.export test022b: far + ldx #$22b + jsl init_test + lda #$6f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000134 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022c: +.export test022c: far + ldx #$22c + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022d: +.export test022d: far + ldx #$22d + jsl init_test + lda #$6f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000033 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022e: +.export test022e: far + ldx #$22e + jsl init_test + lda #$6f + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $FF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $000133 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test022f: +.export test022f: far + ldx #$22f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$6f + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f0fdc + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0230: +.export test0230: far + ldx #$230 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$6f + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$12fe + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + eor [$34],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7ffeec + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0231: +.export test0231: far + ldx #$231 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$6f + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$12fe + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor [$FF],y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f1244 + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0232: +.export test0232: far + ldx #$232 + jsl init_test + lda #$6f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0233: +.export test0233: far + ldx #$233 + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0234: +.export test0234: far + ldx #$234 + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $FFFF,y + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0235: +.export test0235: far + ldx #$235 + jsl init_test + lda #$6f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0236: +.export test0236: far + ldx #$236 + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0237: +.export test0237: far + ldx #$237 + jsl init_test + lda #$6f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0238: +.export test0238: far + ldx #$238 + jsl init_test + lda #$6f + sta $7f02ff + rep #$20 + .a16 + lda #$12fe + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f02ff + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0239: +.export test0239: far + ldx #$239 + jsl init_test + lda #$6f + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023a: +.export test023a: far + ldx #$23a + jsl init_test + lda #$6f + sta $7f002f + rep #$20 + .a16 + lda #$12fe + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + eor $7EFFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1291 + bne @to_fail + lda $7f002f + cmp #$6f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023b: +.export test023b: far + ldx #$23b + jsl init_test + rep #$20 + .a16 + lda #$aaaa + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + eor #$aa + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023c: +.export test023c: far + ldx #$23c + jsl init_test + rep #$20 + .a16 + lda #$ffff + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023d: +.export test023d: far + ldx #$23d + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023e: +.export test023e: far + ldx #$23e + jsl init_test + lda #$ff + sta $7effff + lda #$ff + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test023f: +.export test023f: far + ldx #$23f + jsl init_test + lda #$ff + sta $000134 + lda #$ff + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0240: +.export test0240: far + ldx #$240 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0241: +.export test0241: far + ldx #$241 + jsl init_test + lda #$ff + sta $7f02ff + lda #$ff + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0242: +.export test0242: far + ldx #$242 + jsl init_test + lda #$ff + sta $7f002f + lda #$ff + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0243: +.export test0243: far + ldx #$243 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$ffff + ldy #$5678 + rep #$ff + sep #$00 + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0244: +.export test0244: far + ldx #$244 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$ffff + rep #$ff + sep #$00 + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0245: +.export test0245: far + ldx #$245 + jsl init_test + rep #$20 + .a16 + lda #$7fff + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc a + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0246: +.export test0246: far + ldx #$246 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc $34 + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0247: +.export test0247: far + ldx #$247 + jsl init_test + lda #$ff + sta $7effff + lda #$7f + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + inc $FFFF + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0248: +.export test0248: far + ldx #$248 + jsl init_test + lda #$ff + sta $000134 + lda #$7f + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0249: +.export test0249: far + ldx #$249 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + inc $02,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024a: +.export test024a: far + ldx #$24a + jsl init_test + lda #$ff + sta $7f02ff + lda #$7f + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024b: +.export test024b: far + ldx #$24b + jsl init_test + lda #$ff + sta $7f002f + lda #$7f + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + inc $FFFF,x + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024c: +.export test024c: far + ldx #$24c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$7fff + ldy #$5678 + rep #$30 + sep #$cf + inx + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024d: +.export test024d: far + ldx #$24d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$7fff + rep #$30 + sep #$cf + iny + jsr bank1_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test024e + +.segment "BANK2" + +bank2_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test024e: +.export test024e: far + ldx #$24e + jsl init_test + rep #$20 + .a16 + lda #$12ff + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test024f: +.export test024f: far + ldx #$24f + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0250: +.export test0250: far + ldx #$250 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + inc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0251: +.export test0251: far + ldx #$251 + jsl init_test + lda #$ff + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0252: +.export test0252: far + ldx #$252 + jsl init_test + lda #$ff + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + inc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0253: +.export test0253: far + ldx #$253 + jsl init_test + lda #$ff + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0254: +.export test0254: far + ldx #$254 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0255: +.export test0255: far + ldx #$255 + jsl init_test + lda #$ff + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0256: +.export test0256: far + ldx #$256 + jsl init_test + lda #$ff + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + inc $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0257: +.export test0257: far + ldx #$257 + jsl init_test + lda #$ff + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0258: +.export test0258: far + ldx #$258 + jsl init_test + lda #$ff + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0032 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0259: +.export test0259: far + ldx #$259 + jsl init_test + lda #$ff + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025a: +.export test025a: far + ldx #$25a + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$00ff + ldy #$5678 + rep #$ef + sep #$10 + .i8 + inx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025b: +.export test025b: far + ldx #$25b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$00ff + rep #$ef + sep #$10 + .i8 + iny + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025c: +.export test025c: far + ldx #$25c + jsl init_test + rep #$20 + .a16 + lda #$127f + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025d: +.export test025d: far + ldx #$25d + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025e: +.export test025e: far + ldx #$25e + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + inc $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test025f: +.export test025f: far + ldx #$25f + jsl init_test + lda #$7f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0260: +.export test0260: far + ldx #$260 + jsl init_test + lda #$7f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + inc $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0261: +.export test0261: far + ldx #$261 + jsl init_test + lda #$7f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0262: +.export test0262: far + ldx #$262 + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0263: +.export test0263: far + ldx #$263 + jsl init_test + lda #$7f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + inc $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0264: +.export test0264: far + ldx #$264 + jsl init_test + lda #$7f + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + inc $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0265: +.export test0265: far + ldx #$265 + jsl init_test + lda #$7f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0266: +.export test0266: far + ldx #$266 + jsl init_test + lda #$7f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0267: +.export test0267: far + ldx #$267 + jsl init_test + lda #$7f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + inc $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0268: +.export test0268: far + ldx #$268 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$007f + ldy #$5678 + rep #$20 + sep #$df + .i8 + inx + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0269: +.export test0269: far + ldx #$269 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$007f + rep #$20 + sep #$df + .i8 + iny + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026a: +.export test026a: far + ldx #$26a + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$4c + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + lda #$db + sta $7e7003 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026b: +.export test026b: far + ldx #$26b + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7e8000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026c: +.export test026c: far + ldx #$26c + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$6c + sta $7e7000 + lda #$a2 + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026d: +.export test026d: far + ldx #$26d + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml [$FFA4] + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026e: +.export test026e: far + ldx #$26e + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7c + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$f0 + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e5000 + lda #$80 + sta $7e5001 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$6000 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$6000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test026f: +.export test026f: far + ldx #$26f + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7c + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0081 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + jml $7e7000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0270: +.export test0270: far + ldx #$270 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$7c + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0081 + ldy #$5678 + sec + xce + rep #$ff + sep #$00 + .a8 + .i8 + jml $7e7000 + + jsr bank2_save_results + bra @to_fail +@ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0271: +.export test0271: far + ldx #$271 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$20 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + lda #$db + sta $7e7003 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0272: +.export test0272: far + ldx #$272 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$20 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + lda #$db + sta $7e7003 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0001ff + cmp #$02 + bne @to_fail + lda $000100 + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0273: +.export test0273: far + ldx #$273 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$22 + sta $7f7000 + lda #$00 + sta $7f7001 + lda #$80 + sta $7f7002 + lda #$7e + sta $7f7003 + lda #$db + sta $7f7004 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7f7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ec + bne @to_fail + lda $0001ed + cmp #$03 + bne @to_fail + lda $0001ee + cmp #$70 + bne @to_fail + lda $0001ef + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0274: +.export test0274: far + ldx #$274 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$22 + sta $7f7000 + lda #$00 + sta $7f7001 + lda #$80 + sta $7f7002 + lda #$7e + sta $7f7003 + lda #$db + sta $7f7004 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7f7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fd + bne @to_fail + lda $0000fe + cmp #$03 + bne @to_fail + lda $0000ff + cmp #$70 + bne @to_fail + lda $000100 + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0275: +.export test0275: far + ldx #$275 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$fc + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$f0 + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e5000 + lda #$80 + sta $7e5001 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$6000 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$6000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0276: +.export test0276: far + ldx #$276 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$fc + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0081 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0277: +.export test0277: far + ldx #$277 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8000 + lda #<@ok + sta $7e8001 + lda #>@ok + sta $7e8002 + lda #^@ok + sta $7e8003 + lda #$fc + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$ff + sta $7e7002 + lda #$db + sta $7e7003 + lda #$00 + sta $7e0080 + lda #$80 + sta $7e0081 + lda #$7f + pha + plb + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$0081 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + jml $7e7000 + @ok: + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0081 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0000ff + cmp #$02 + bne @to_fail + lda $000100 + cmp #$70 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0278: +.export test0278: far + ldx #$278 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda #$8000 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0279: +.export test0279: far + ldx #$279 + jsl init_test + lda #$00 + sta $7f1212 + lda #$80 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$fd + sep #$02 + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027a: +.export test027a: far + ldx #$27a + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$0123 + ldy #$5678 + rep #$fd + sep #$02 + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027b: +.export test027b: far + ldx #$27b + jsl init_test + lda #$00 + sta $7f1212 + lda #$80 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027c: +.export test027c: far + ldx #$27c + jsl init_test + lda #$00 + sta $000201 + lda #$80 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027d: +.export test027d: far + ldx #$27d + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027e: +.export test027e: far + ldx #$27e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + lda #$80 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test027f: +.export test027f: far + ldx #$27f + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0280: +.export test0280: far + ldx #$280 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0281: +.export test0281: far + ldx #$281 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0282: +.export test0282: far + ldx #$282 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0283: +.export test0283: far + ldx #$283 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0284: +.export test0284: far + ldx #$284 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fd + sep #$02 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0285: +.export test0285: far + ldx #$285 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$80 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0286: +.export test0286: far + ldx #$286 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fd + sep #$02 + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0287: +.export test0287: far + ldx #$287 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0288: +.export test0288: far + ldx #$288 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0289: +.export test0289: far + ldx #$289 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fd + sep #$02 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028a: +.export test028a: far + ldx #$28a + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$fd + sep #$02 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028b: +.export test028b: far + ldx #$28b + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028c: +.export test028c: far + ldx #$28c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + lda #$80 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$fd + sep #$02 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028d: +.export test028d: far + ldx #$28d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + lda #$80 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$ed + sep #$12 + .i8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028e: +.export test028e: far + ldx #$28e + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$fd + sep #$02 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test028f: +.export test028f: far + ldx #$28f + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$fd + sep #$02 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0290: +.export test0290: far + ldx #$290 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$ed + sep #$12 + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0291: +.export test0291: far + ldx #$291 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fd + sep #$02 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0292: +.export test0292: far + ldx #$292 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0293: +.export test0293: far + ldx #$293 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$fd + sep #$02 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0294: +.export test0294: far + ldx #$294 + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0295: +.export test0295: far + ldx #$295 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx #$8000 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0296: +.export test0296: far + ldx #$296 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0297: +.export test0297: far + ldx #$297 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$fd + sep #$02 + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0298: +.export test0298: far + ldx #$298 + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0133 + rep #$fd + sep #$02 + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0299: +.export test0299: far + ldx #$299 + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$0300 + rep #$fd + sep #$02 + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029a: +.export test029a: far + ldx #$29a + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy #$8000 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029b: +.export test029b: far + ldx #$29b + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029c: +.export test029c: far + ldx #$29c + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$fd + sep #$02 + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029d: +.export test029d: far + ldx #$29d + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$1234 + rep #$fd + sep #$02 + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029e: +.export test029e: far + ldx #$29e + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$1234 + rep #$fd + sep #$02 + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test029f: +.export test029f: far + ldx #$29f + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a0: +.export test02a0: far + ldx #$2a0 + jsl init_test + lda #$00 + sta $7f1212 + lda #$00 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a1: +.export test02a1: far + ldx #$2a1 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$0123 + ldy #$5678 + rep #$30 + sep #$cf + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a2: +.export test02a2: far + ldx #$2a2 + jsl init_test + lda #$00 + sta $7f1212 + lda #$00 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a3: +.export test02a3: far + ldx #$2a3 + jsl init_test + lda #$00 + sta $000201 + lda #$00 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a4: +.export test02a4: far + ldx #$2a4 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a5: +.export test02a5: far + ldx #$2a5 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + lda #$00 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a6: +.export test02a6: far + ldx #$2a6 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a7: +.export test02a7: far + ldx #$2a7 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a8: +.export test02a8: far + ldx #$2a8 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02a9: +.export test02a9: far + ldx #$2a9 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02aa: +.export test02aa: far + ldx #$2aa + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ab: +.export test02ab: far + ldx #$2ab + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ac: +.export test02ac: far + ldx #$2ac + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$00 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ad: +.export test02ad: far + ldx #$2ad + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ae: +.export test02ae: far + ldx #$2ae + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02af: +.export test02af: far + ldx #$2af + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b0: +.export test02b0: far + ldx #$2b0 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b1: +.export test02b1: far + ldx #$2b1 + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b2: +.export test02b2: far + ldx #$2b2 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b3: +.export test02b3: far + ldx #$2b3 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + lda #$00 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b4: +.export test02b4: far + ldx #$2b4 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + lda #$00 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b5: +.export test02b5: far + ldx #$2b5 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b6: +.export test02b6: far + ldx #$2b6 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b7: +.export test02b7: far + ldx #$2b7 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b8: +.export test02b8: far + ldx #$2b8 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02b9: +.export test02b9: far + ldx #$2b9 + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ba: +.export test02ba: far + ldx #$2ba + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bb: +.export test02bb: far + ldx #$2bb + jsl init_test + lda #$00 + sta $7f002f + lda #$00 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bc: +.export test02bc: far + ldx #$2bc + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bd: +.export test02bd: far + ldx #$2bd + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02be: +.export test02be: far + ldx #$2be + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$30 + sep #$cf + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02bf: +.export test02bf: far + ldx #$2bf + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0133 + rep #$30 + sep #$cf + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c0: +.export test02c0: far + ldx #$2c0 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$0300 + rep #$30 + sep #$cf + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c1: +.export test02c1: far + ldx #$2c1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c2: +.export test02c2: far + ldx #$2c2 + jsl init_test + lda #$00 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c3: +.export test02c3: far + ldx #$2c3 + jsl init_test + lda #$00 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$30 + sep #$cf + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c4: +.export test02c4: far + ldx #$2c4 + jsl init_test + lda #$00 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$1234 + rep #$30 + sep #$cf + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c5: +.export test02c5: far + ldx #$2c5 + jsl init_test + lda #$00 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$1234 + rep #$30 + sep #$cf + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$004f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c6: +.export test02c6: far + ldx #$2c6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda #$80 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c7: +.export test02c7: far + ldx #$2c7 + jsl init_test + lda #$80 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1212 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c8: +.export test02c8: far + ldx #$2c8 + jsl init_test + lda #$80 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1212 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02c9: +.export test02c9: far + ldx #$2c9 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($EF,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ca: +.export test02ca: far + ldx #$2ca + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($F0,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cb: +.export test02cb: far + ldx #$2cb + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1234 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($F6,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test02cc: +.export test02cc: far + ldx #$2cc + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1234 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($F7,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cd: +.export test02cd: far + ldx #$2cd + jsl init_test + lda #$80 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000201 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ce: +.export test02ce: far + ldx #$2ce + jsl init_test + lda #$80 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000201 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02cf: +.export test02cf: far + ldx #$2cf + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d0: +.export test02d0: far + ldx #$2d0 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d1: +.export test02d1: far + ldx #$2d1 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$80 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d2: +.export test02d2: far + ldx #$2d2 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$80 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda [$FF] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d3: +.export test02d3: far + ldx #$2d3 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d4: +.export test02d4: far + ldx #$2d4 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d5: +.export test02d5: far + ldx #$2d5 + jsl init_test + lda #$80 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d6: +.export test02d6: far + ldx #$2d6 + jsl init_test + lda #$80 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d7: +.export test02d7: far + ldx #$2d7 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$80 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d8: +.export test02d8: far + ldx #$2d8 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$80 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02d9: +.export test02d9: far + ldx #$2d9 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$80 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($FF),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1244 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02da: +.export test02da: far + ldx #$2da + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$80 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($FE),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1244 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02db: +.export test02db: far + ldx #$2db + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02dc: +.export test02dc: far + ldx #$2dc + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($FF) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02dd: +.export test02dd: far + ldx #$2dd + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$80 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($FE) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1234 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02de: +.export test02de: far + ldx #$2de + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$80 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02df: +.export test02df: far + ldx #$2df + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$80 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e0: +.export test02e0: far + ldx #$2e0 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$80 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda ($12,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e1: +.export test02e1: far + ldx #$2e1 + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000134 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e2: +.export test02e2: far + ldx #$2e2 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e3: +.export test02e3: far + ldx #$2e3 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e4: +.export test02e4: far + ldx #$2e4 + jsl init_test + lda #$80 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $000133 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e5: +.export test02e5: far + ldx #$2e5 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$80 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$dd + sep #$22 + .a8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f0fdc + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e6: +.export test02e6: far + ldx #$2e6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$80 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$cd + sep #$32 + .a8 + .i8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7ffeec + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e7: +.export test02e7: far + ldx #$2e7 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$80 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda [$FF],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f1244 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e8: +.export test02e8: far + ldx #$2e8 + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$dd + sep #$22 + .a8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02e9: +.export test02e9: far + ldx #$2e9 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$cd + sep #$32 + .a8 + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ea: +.export test02ea: far + ldx #$2ea + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02eb: +.export test02eb: far + ldx #$2eb + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ec: +.export test02ec: far + ldx #$2ec + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ed: +.export test02ed: far + ldx #$2ed + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ee: +.export test02ee: far + ldx #$2ee + jsl init_test + lda #$80 + sta $7f02ff + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$dd + sep #$22 + .a8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f02ff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ef: +.export test02ef: far + ldx #$2ef + jsl init_test + lda #$80 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cd + sep #$32 + .a8 + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f0: +.export test02f0: far + ldx #$2f0 + jsl init_test + lda #$80 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$dd + sep #$22 + .a8 + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1280 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f1: +.export test02f1: far + ldx #$2f1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx #$80 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f2: +.export test02f2: far + ldx #$2f2 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f3: +.export test02f3: far + ldx #$2f3 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f4: +.export test02f4: far + ldx #$2f4 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$ed + sep #$12 + .i8 + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f5: +.export test02f5: far + ldx #$2f5 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f6: +.export test02f6: far + ldx #$2f6 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$1232 + rep #$ed + sep #$12 + .i8 + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f7: +.export test02f7: far + ldx #$2f7 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0032 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f8: +.export test02f8: far + ldx #$2f8 + jsl init_test + lda #$80 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$1234 + ldy #$0034 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldx $FF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0034 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02f9: +.export test02f9: far + ldx #$2f9 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + rep #$ed + sep #$12 + .i8 + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fa: +.export test02fa: far + ldx #$2fa + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0080 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fb: +.export test02fb: far + ldx #$2fb + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy #$80 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fc: +.export test02fc: far + ldx #$2fc + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fd: +.export test02fd: far + ldx #$2fd + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02fe: +.export test02fe: far + ldx #$2fe + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test02ff: +.export test02ff: far + ldx #$2ff + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0300: +.export test0300: far + ldx #$300 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0301: +.export test0301: far + ldx #$301 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$1234 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0302: +.export test0302: far + ldx #$302 + jsl init_test + lda #$80 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$1234 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldy $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0303: +.export test0303: far + ldx #$303 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + rep #$ed + sep #$12 + .i8 + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0304: +.export test0304: far + ldx #$304 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + sec + xce + rep #$ed + sep #$12 + .a8 + .i8 + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0080 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0305: +.export test0305: far + ldx #$305 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0306: +.export test0306: far + ldx #$306 + jsl init_test + lda #$00 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0307: +.export test0307: far + ldx #$307 + jsl init_test + lda #$00 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0308: +.export test0308: far + ldx #$308 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($EF,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0309: +.export test0309: far + ldx #$309 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($F0,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030a: +.export test030a: far + ldx #$30a + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1234 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($F6,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test030b: +.export test030b: far + ldx #$30b + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1234 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($F7,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030c: +.export test030c: far + ldx #$30c + jsl init_test + lda #$00 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030d: +.export test030d: far + ldx #$30d + jsl init_test + lda #$00 + sta $000201 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030e: +.export test030e: far + ldx #$30e + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test030f: +.export test030f: far + ldx #$30f + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0310: +.export test0310: far + ldx #$310 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0311: +.export test0311: far + ldx #$311 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$00 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda [$FF] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0312: +.export test0312: far + ldx #$312 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0313: +.export test0313: far + ldx #$313 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0314: +.export test0314: far + ldx #$314 + jsl init_test + lda #$00 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0315: +.export test0315: far + ldx #$315 + jsl init_test + lda #$00 + sta $7effff + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0316: +.export test0316: far + ldx #$316 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0317: +.export test0317: far + ldx #$317 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$00 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0318: +.export test0318: far + ldx #$318 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$00 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($FF),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0319: +.export test0319: far + ldx #$319 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$00 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($FE),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031a: +.export test031a: far + ldx #$31a + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031b: +.export test031b: far + ldx #$31b + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($FF) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031c: +.export test031c: far + ldx #$31c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$00 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($FE) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031d: +.export test031d: far + ldx #$31d + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031e: +.export test031e: far + ldx #$31e + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$00 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test031f: +.export test031f: far + ldx #$31f + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$00 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda ($12,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0320: +.export test0320: far + ldx #$320 + jsl init_test + lda #$00 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0321: +.export test0321: far + ldx #$321 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0322: +.export test0322: far + ldx #$322 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0323: +.export test0323: far + ldx #$323 + jsl init_test + lda #$00 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0324: +.export test0324: far + ldx #$324 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$00 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0325: +.export test0325: far + ldx #$325 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$00 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + lda [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0326: +.export test0326: far + ldx #$326 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$00 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda [$FF],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0327: +.export test0327: far + ldx #$327 + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0328: +.export test0328: far + ldx #$328 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0329: +.export test0329: far + ldx #$329 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032a: +.export test032a: far + ldx #$32a + jsl init_test + lda #$00 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032b: +.export test032b: far + ldx #$32b + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032c: +.export test032c: far + ldx #$32c + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032d: +.export test032d: far + ldx #$32d + jsl init_test + lda #$00 + sta $7f02ff + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032e: +.export test032e: far + ldx #$32e + jsl init_test + lda #$00 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test032f: +.export test032f: far + ldx #$32f + jsl init_test + lda #$00 + sta $7f002f + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lda $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0330: +.export test0330: far + ldx #$330 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0331: +.export test0331: far + ldx #$331 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0332: +.export test0332: far + ldx #$332 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldx $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0333: +.export test0333: far + ldx #$333 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0334: +.export test0334: far + ldx #$334 + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldx $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0335: +.export test0335: far + ldx #$335 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$1232 + rep #$20 + sep #$df + .i8 + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0336: +.export test0336: far + ldx #$336 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1234 + ldy #$0032 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldx $02,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0337: +.export test0337: far + ldx #$337 + jsl init_test + lda #$00 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$1234 + ldy #$0034 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldx $FF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0034 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0338: +.export test0338: far + ldx #$338 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + rep #$20 + sep #$df + .i8 + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0339: +.export test0339: far + ldx #$339 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$1230 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldx $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033a: +.export test033a: far + ldx #$33a + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033b: +.export test033b: far + ldx #$33b + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033c: +.export test033c: far + ldx #$33c + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1234 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldy $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033d: +.export test033d: far + ldx #$33d + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033e: +.export test033e: far + ldx #$33e + jsl init_test + lda #$00 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1234 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldy $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test033f: +.export test033f: far + ldx #$33f + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0340: +.export test0340: far + ldx #$340 + jsl init_test + lda #$00 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$1234 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldy $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0341: +.export test0341: far + ldx #$341 + jsl init_test + lda #$00 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$1234 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldy $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0342: +.export test0342: far + ldx #$342 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + rep #$20 + sep #$df + .i8 + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0343: +.export test0343: far + ldx #$343 + jsl init_test + lda #$00 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$1234 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + ldy $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$017f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0344: +.export test0344: far + ldx #$344 + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0345: +.export test0345: far + ldx #$345 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0346: +.export test0346: far + ldx #$346 + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0347: +.export test0347: far + ldx #$347 + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0348: +.export test0348: far + ldx #$348 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0349: +.export test0349: far + ldx #$349 + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034a: +.export test034a: far + ldx #$34a + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034b: +.export test034b: far + ldx #$34b + jsl init_test + rep #$20 + .a16 + lda #$4222 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$2111 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034c: +.export test034c: far + ldx #$34c + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034d: +.export test034d: far + ldx #$34d + jsl init_test + lda #$22 + sta $7effff + lda #$42 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$11 + bne @to_fail + lda $7f0000 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034e: +.export test034e: far + ldx #$34e + jsl init_test + lda #$22 + sta $000134 + lda #$42 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$11 + bne @to_fail + lda $000135 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test034f: +.export test034f: far + ldx #$34f + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0350: +.export test0350: far + ldx #$350 + jsl init_test + lda #$22 + sta $7f02ff + lda #$42 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$11 + bne @to_fail + lda $7f0300 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0351: +.export test0351: far + ldx #$351 + jsl init_test + lda #$22 + sta $7f002f + lda #$42 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$11 + bne @to_fail + lda $7f0030 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0352: +.export test0352: far + ldx #$352 + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0353: +.export test0353: far + ldx #$353 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0354: +.export test0354: far + ldx #$354 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0355: +.export test0355: far + ldx #$355 + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0356: +.export test0356: far + ldx #$356 + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0357: +.export test0357: far + ldx #$357 + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0358: +.export test0358: far + ldx #$358 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0359: +.export test0359: far + ldx #$359 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035a: +.export test035a: far + ldx #$35a + jsl init_test + lda #$01 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + lsr $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035b: +.export test035b: far + ldx #$35b + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035c: +.export test035c: far + ldx #$35c + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035d: +.export test035d: far + ldx #$35d + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035e: +.export test035e: far + ldx #$35e + jsl init_test + rep #$20 + .a16 + lda #$1242 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr a + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1221 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test035f: +.export test035f: far + ldx #$35f + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0360: +.export test0360: far + ldx #$360 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lsr $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0361: +.export test0361: far + ldx #$361 + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0362: +.export test0362: far + ldx #$362 + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lsr $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0363: +.export test0363: far + ldx #$363 + jsl init_test + lda #$42 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0364: +.export test0364: far + ldx #$364 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0365: +.export test0365: far + ldx #$365 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lsr $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0366: +.export test0366: far + ldx #$366 + jsl init_test + lda #$42 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lsr $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0367: +.export test0367: far + ldx #$367 + jsl init_test + lda #$42 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0368: +.export test0368: far + ldx #$368 + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0369: +.export test0369: far + ldx #$369 + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + lsr $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$017c + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$21 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036a: +.export test036a: far + ldx #$36a + jsl init_test + lda #$21 + sta $7effff + lda #$22 + sta $7e0000 + lda #$23 + sta $7e0001 + lda #$24 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$ffff + ldy #$fffe + rep #$ff + sep #$00 + mvn #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0003 + bne @to_fail + cpy #$0002 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7ffffe + cmp #$21 + bne @to_fail + lda $7fffff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$23 + bne @to_fail + lda $7f0001 + cmp #$24 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036b: +.export test036b: far + ldx #$36b + jsl init_test + lda #$31 + sta $7f0005 + lda #$32 + sta $7f0204 + lda #$99 + sta $7f0200 + rep #$20 + .a16 + lda #$01ff + ldx #$0005 + ldy #$0000 + rep #$10 + sep #$ef + .a8 + mvn #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0205 + bne @to_fail + cpy #$0200 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0000 + cmp #$31 + bne @to_fail + lda $7f01ff + cmp #$32 + bne @to_fail + lda $7f0200 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036c: +.export test036c: far + ldx #$36c + jsl init_test + lda #$41 + sta $7f0000 + lda #$42 + sta $7f0001 + rep #$20 + .a16 + lda #$01ff + ldx #$0000 + ldy #$0002 + rep #$ff + sep #$00 + mvn #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0200 + bne @to_fail + cpy #$0202 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0200 + cmp #$41 + bne @to_fail + lda $7f0201 + cmp #$42 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036d: +.export test036d: far + ldx #$36d + jsl init_test + lda #$51 + sta $7e00ff + lda #$52 + sta $7e0000 + lda #$53 + sta $7e0001 + lda #$54 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$05ff + ldy #$05fe + rep #$ef + sep #$10 + .i8 + mvn #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0003 + bne @to_fail + cpy #$0002 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f00fe + cmp #$51 + bne @to_fail + lda $7f00ff + cmp #$52 + bne @to_fail + lda $7f0000 + cmp #$53 + bne @to_fail + lda $7f0001 + cmp #$54 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036e: +.export test036e: far + ldx #$36e + jsl init_test + lda #$21 + sta $7effff + lda #$22 + sta $7e0000 + lda #$23 + sta $7e0001 + lda #$24 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7ffffd + rep #$20 + .a16 + lda #$0003 + ldx #$0002 + ldy #$0001 + rep #$ff + sep #$00 + mvp #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$fffe + bne @to_fail + cpy #$fffd + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7ffffe + cmp #$21 + bne @to_fail + lda $7fffff + cmp #$22 + bne @to_fail + lda $7f0000 + cmp #$23 + bne @to_fail + lda $7f0001 + cmp #$24 + bne @to_fail + lda $7ffffd + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test036f: +.export test036f: far + ldx #$36f + jsl init_test + lda #$31 + sta $7f0000 + lda #$32 + sta $7f01ff + lda #$99 + sta $7f0004 + rep #$20 + .a16 + lda #$01ff + ldx #$01ff + ldy #$0204 + rep #$10 + sep #$ef + .a8 + mvp #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ffff + bne @to_fail + cpy #$0004 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0005 + cmp #$31 + bne @to_fail + lda $7f0204 + cmp #$32 + bne @to_fail + lda $7f0004 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0370: +.export test0370: far + ldx #$370 + jsl init_test + lda #$41 + sta $7f0200 + lda #$42 + sta $7f0201 + rep #$20 + .a16 + lda #$01ff + ldx #$0201 + ldy #$01ff + rep #$ff + sep #$00 + mvp #$7f, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0001 + bne @to_fail + cpy #$ffff + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f0000 + cmp #$41 + bne @to_fail + lda $7f0001 + cmp #$42 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0371: +.export test0371: far + ldx #$371 + jsl init_test + lda #$51 + sta $7e00ff + lda #$52 + sta $7e0000 + lda #$53 + sta $7e0001 + lda #$54 + sta $7e0002 + lda #$00 + sta $7f0001 + lda #$99 + sta $7f0002 + rep #$20 + .a16 + lda #$0003 + ldx #$0502 + ldy #$0501 + rep #$ef + sep #$10 + .i8 + mvp #$7e, #$7f + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00fe + bne @to_fail + cpy #$00fd + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + lda result_dbr + cmp #$7f + bne @to_fail + lda $7f00fe + cmp #$51 + bne @to_fail + lda $7f00ff + cmp #$52 + bne @to_fail + lda $7f0000 + cmp #$53 + bne @to_fail + lda $7f0001 + cmp #$54 + bne @to_fail + lda $7f0002 + cmp #$99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0372: +.export test0372: far + ldx #$372 + jsl init_test + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora #$b939 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0373: +.export test0373: far + ldx #$373 + jsl init_test + lda #$39 + sta $7f1212 + lda #$b9 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + ora ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + lda $7f1213 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0374: +.export test0374: far + ldx #$374 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$2318 + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + ora ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0375: +.export test0375: far + ldx #$375 + jsl init_test + lda #$39 + sta $7f1212 + lda #$b9 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$2318 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + lda $7f1213 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0376: +.export test0376: far + ldx #$376 + jsl init_test + lda #$39 + sta $000201 + lda #$b9 + sta $000202 + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000201 + cmp #$39 + bne @to_fail + lda $000202 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0377: +.export test0377: far + ldx #$377 + jsl init_test + lda #$39 + sta $000033 + lda #$b9 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + lda $000034 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0378: +.export test0378: far + ldx #$378 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7f1234 + lda #$b9 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + lda $7f1235 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0379: +.export test0379: far + ldx #$379 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037a: +.export test037a: far + ldx #$37a + jsl init_test + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037b: +.export test037b: far + ldx #$37b + jsl init_test + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037c: +.export test037c: far + ldx #$37c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037d: +.export test037d: far + ldx #$37d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037e: +.export test037e: far + ldx #$37e + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test037f: +.export test037f: far + ldx #$37f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$39 + sta $7f1234 + lda #$b9 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + lda $7f1235 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0380: +.export test0380: far + ldx #$380 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0381: +.export test0381: far + ldx #$381 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0382: +.export test0382: far + ldx #$382 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0383: +.export test0383: far + ldx #$383 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0384: +.export test0384: far + ldx #$384 + jsl init_test + lda #$39 + sta $000134 + lda #$b9 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000134 + cmp #$39 + bne @to_fail + lda $000135 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0385: +.export test0385: far + ldx #$385 + jsl init_test + lda #$39 + sta $000033 + lda #$b9 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + lda $000034 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0386: +.export test0386: far + ldx #$386 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7f0fdc + lda #$b9 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + lda $7f0fdd + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0387: +.export test0387: far + ldx #$387 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7ffeec + lda #$b9 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + lda $7ffeed + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0388: +.export test0388: far + ldx #$388 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7effff + lda #$b9 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$2318 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + lda $7f0000 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0389: +.export test0389: far + ldx #$389 + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038a: +.export test038a: far + ldx #$38a + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038b: +.export test038b: far + ldx #$38b + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038c: +.export test038c: far + ldx #$38c + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$2318 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $FFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038d: +.export test038d: far + ldx #$38d + jsl init_test + lda #$39 + sta $7f02ff + lda #$b9 + sta $7f0300 + rep #$20 + .a16 + lda #$2318 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + lda $7f0300 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038e: +.export test038e: far + ldx #$38e + jsl init_test + lda #$39 + sta $7f002f + lda #$b9 + sta $7f0030 + rep #$20 + .a16 + lda #$2318 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ora $7EFFFF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$bb39 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + lda $7f0030 + cmp #$b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test038f: +.export test038f: far + ldx #$38f + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ora #$00 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0390: +.export test0390: far + ldx #$390 + jsl init_test + rep #$20 + .a16 + lda #$1200 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ora #$4300 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$004d + bne @to_fail + ldx result_a + cpx #$5300 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0391: +.export test0391: far + ldx #$391 + jsl init_test + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora #$39 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0392: +.export test0392: far + ldx #$392 + jsl init_test + lda #$39 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora ($10,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0393: +.export test0393: far + ldx #$393 + jsl init_test + lda #$39 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1298 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($90,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1212 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0394: +.export test0394: far + ldx #$394 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($EF,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0395: +.export test0395: far + ldx #$395 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($F0,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0396: +.export test0396: far + ldx #$396 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1298 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($F6,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0397: +.export test0397: far + ldx #$397 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$1298 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($F7,x) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0398: +.export test0398: far + ldx #$398 + jsl init_test + lda #$39 + sta $000201 + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000201 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0399: +.export test0399: far + ldx #$399 + jsl init_test + lda #$39 + sta $000201 + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $12,s + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000201 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039a: +.export test039a: far + ldx #$39a + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039b: +.export test039b: far + ldx #$39b + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $34 + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039c: +.export test039c: far + ldx #$39c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora [$34] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039d: +.export test039d: far + ldx #$39d + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$39 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora [$FF] + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039e: +.export test039e: far + ldx #$39e + jsl init_test + lda #$39 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test039f: +.export test039f: far + ldx #$39f + jsl init_test + lda #$39 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $FFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a0: +.export test03a0: far + ldx #$3a0 + jsl init_test + lda #$39 + sta $7effff + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a1: +.export test03a1: far + ldx #$3a1 + jsl init_test + lda #$39 + sta $7effff + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $7EFFFF + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7effff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a2: +.export test03a2: far + ldx #$3a2 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a3: +.export test03a3: far + ldx #$3a3 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$39 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($34),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a4: +.export test03a4: far + ldx #$3a4 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$39 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($FF),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1244 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a5: +.export test03a5: far + ldx #$3a5 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$39 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1298 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($FE),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1244 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a6: +.export test03a6: far + ldx #$3a6 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora ($34) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a7: +.export test03a7: far + ldx #$3a7 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($FF) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a8: +.export test03a8: far + ldx #$3a8 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$39 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$1298 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($FE) + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1234 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03a9: +.export test03a9: far + ldx #$3a9 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03aa: +.export test03aa: far + ldx #$3aa + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$39 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora ($10,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ab: +.export test03ab: far + ldx #$3ab + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$39 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora ($12,s),y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ac: +.export test03ac: far + ldx #$3ac + jsl init_test + lda #$39 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000134 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ad: +.export test03ad: far + ldx #$3ad + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ae: +.export test03ae: far + ldx #$3ae + jsl init_test + lda #$39 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $02,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000033 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03af: +.export test03af: far + ldx #$3af + jsl init_test + lda #$39 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $FF,x + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $000133 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b0: +.export test03b0: far + ldx #$3b0 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$39 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f0fdc + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b1: +.export test03b1: far + ldx #$3b1 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$39 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1298 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + ora [$34],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7ffeec + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b2: +.export test03b2: far + ldx #$3b2 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$39 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1298 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora [$FF],y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f1244 + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b3: +.export test03b3: far + ldx #$3b3 + jsl init_test + lda #$39 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b4: +.export test03b4: far + ldx #$3b4 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b5: +.export test03b5: far + ldx #$3b5 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $FFFF,y + jsr bank2_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test03b6 + +.segment "BANK3" + +bank3_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test03b6: +.export test03b6: far + ldx #$3b6 + jsl init_test + lda #$39 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b7: +.export test03b7: far + ldx #$3b7 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b8: +.export test03b8: far + ldx #$3b8 + jsl init_test + lda #$39 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03b9: +.export test03b9: far + ldx #$3b9 + jsl init_test + lda #$39 + sta $7f02ff + rep #$20 + .a16 + lda #$1298 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f02ff + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ba: +.export test03ba: far + ldx #$3ba + jsl init_test + lda #$39 + sta $7f002f + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ora $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bb: +.export test03bb: far + ldx #$3bb + jsl init_test + lda #$39 + sta $7f002f + rep #$20 + .a16 + lda #$1298 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ora $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12b9 + bne @to_fail + lda $7f002f + cmp #$39 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bc: +.export test03bc: far + ldx #$3bc + jsl init_test + rep #$20 + .a16 + lda #$aa00 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ora #$00 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bd: +.export test03bd: far + ldx #$3bd + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + nop + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03be: +.export test03be: far + ldx #$3be + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + nop + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03bf: +.export test03bf: far + ldx #$3bf + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + wdm $AB + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c0: +.export test03c0: far + ldx #$3c0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + wdm $AB + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c1: +.export test03c1: far + ldx #$3c1 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pea $ABCD + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$cd + bne @to_fail + lda $0001ef + cmp #$ab + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c2: +.export test03c2: far + ldx #$3c2 + jsl init_test + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + pea $9876 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0000ff + cmp #$76 + bne @to_fail + lda $000100 + cmp #$98 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c3: +.export test03c3: far + ldx #$3c3 + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pei ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$65 + bne @to_fail + lda $0001ef + cmp #$87 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c4: +.export test03c4: far + ldx #$3c4 + jsl init_test + lda #$54 + sta $0002ff + lda #$76 + sta $000300 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0200 + tcd + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + pei ($ff) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0000ff + cmp #$54 + bne @to_fail + lda $000100 + cmp #$76 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c5: +.export test03c5: far + ldx #$3c5 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7003 + lda #<@ok + sta $7e7004 + lda #>@ok + sta $7e7005 + lda #^@ok + sta $7e7006 + lda #$62 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$03 + bne @to_fail + lda $0001ef + cmp #$f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c6: +.export test03c6: far + ldx #$3c6 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7003 + lda #<@ok + sta $7e7004 + lda #>@ok + sta $7e7005 + lda #^@ok + sta $7e7006 + lda #$62 + sta $7e7000 + lda #$ff + sta $7e7001 + lda #$7f + sta $7e7002 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e7000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$02 + bne @to_fail + lda $0001ef + cmp #$f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c7: +.export test03c7: far + ldx #$3c7 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e7003 + lda #<@ok + sta $7e7004 + lda #>@ok + sta $7e7005 + lda #^@ok + sta $7e7006 + lda #$62 + sta $7e7000 + lda #$00 + sta $7e7001 + lda #$80 + sta $7e7002 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7e7000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0000ff + cmp #$03 + bne @to_fail + lda $000100 + cmp #$f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c8: +.export test03c8: far + ldx #$3c8 + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pla + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$fedc + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03c9: +.export test03c9: far + ldx #$3c9 + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$fedc + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ca: +.export test03ca: far + ldx #$3ca + jsl init_test + lda #$dc + sta $0001f0 + lda #$fe + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ply + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$fedc + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cb: +.export test03cb: far + ldx #$3cb + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pla + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cc: +.export test03cc: far + ldx #$3cc + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cd: +.export test03cd: far + ldx #$3cd + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ply + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ce: +.export test03ce: far + ldx #$3ce + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + pla + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$12ef + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03cf: +.export test03cf: far + ldx #$3cf + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + plx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ef + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d0: +.export test03d0: far + ldx #$3d0 + jsl init_test + lda #$ef + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ply + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ef + bne @to_fail + ldx result_p + cpx #$00dd + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d1: +.export test03d1: far + ldx #$3d1 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + pla + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d2: +.export test03d2: far + ldx #$3d2 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + plx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d3: +.export test03d3: far + ldx #$3d3 + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ply + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d4: +.export test03d4: far + ldx #$3d4 + jsl init_test + lda #$ce + sta $000100 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + pla + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$12ce + bne @to_fail + ldx result_s + cpx #$0100 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d5: +.export test03d5: far + ldx #$3d5 + jsl init_test + lda #$ce + sta $000100 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + plx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ce + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0100 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d6: +.export test03d6: far + ldx #$3d6 + jsl init_test + lda #$ce + sta $000100 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + ply + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ce + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0100 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d7: +.export test03d7: far + ldx #$3d7 + jsl init_test + lda #$fe + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plb + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + lda result_dbr + cmp #$fe + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03d8: +.export test03d8: far + ldx #$3d8 + jsl init_test + lda #$00 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$02 + sep #$fd + .a8 + .i8 + plb + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + lda result_dbr + cmp #$00 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test03d9: +.export test03d9: far + ldx #$3d9 + jsl init_test + lda #$3d + sta $000200 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + plb + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0100 + bne @to_fail + lda result_dbr + cmp #$3d + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03da: +.export test03da: far + ldx #$3da + jsl init_test + lda #$53 + sta $0001f0 + lda #$97 + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pld + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx result_d + cpx #$9753 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03db: +.export test03db: far + ldx #$3db + jsl init_test + lda #$00 + sta $0001f0 + lda #$00 + sta $0001f1 + rep #$20 + .a16 + lda #$9999 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$02 + sep #$fd + .a8 + .i8 + pld + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$007f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx result_d + cpx #$0000 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03dc: +.export test03dc: far + ldx #$3dc + jsl init_test + lda #$56 + sta $000200 + lda #$13 + sta $000201 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + pld + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0101 + bne @to_fail + ldx result_d + cpx #$1356 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03dd: +.export test03dd: far + ldx #$3dd + jsl init_test + lda #$00 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + plp + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03de: +.export test03de: far + ldx #$3de + jsl init_test + lda #$23 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + plp + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03df: +.export test03df: far + ldx #$3df + jsl init_test + lda #$10 + sta $0001f0 + rep #$20 + .a16 + lda #$1234 + ldx #$2345 + ldy #$3456 + rep #$ff + sep #$00 + plp + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0045 + bne @to_fail + cpy #$0056 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f0 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e0: +.export test03e0: far + ldx #$3e0 + jsl init_test + lda #$41 + sta $000100 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + plp + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0171 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0100 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e1: +.export test03e1: far + ldx #$3e1 + jsl init_test + rep #$20 + .a16 + lda #$9876 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + pha + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$76 + bne @to_fail + lda $0001ef + cmp #$98 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e2: +.export test03e2: far + ldx #$3e2 + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + pha + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$65 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e3: +.export test03e3: far + ldx #$3e3 + jsl init_test + rep #$20 + .a16 + ldx #$0100 + txs + lda #$5678 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + pha + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5678 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$78 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e4: +.export test03e4: far + ldx #$3e4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$9876 + ldy #$5678 + rep #$ff + sep #$00 + phx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$9876 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$76 + bne @to_fail + lda $0001ef + cmp #$98 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e5: +.export test03e5: far + ldx #$3e5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0023 + ldy #$5678 + rep #$20 + sep #$df + .i8 + phx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0023 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$23 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e6: +.export test03e6: far + ldx #$3e6 + jsl init_test + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + phx + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$34 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e7: +.export test03e7: far + ldx #$3e7 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1324 + rep #$ff + sep #$00 + phy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1324 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$24 + bne @to_fail + lda $0001ef + cmp #$13 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e8: +.export test03e8: far + ldx #$3e8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0035 + rep #$20 + sep #$df + .i8 + phy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0035 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$35 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03e9: +.export test03e9: far + ldx #$3e9 + jsl init_test + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$0046 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + phy + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0046 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$46 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ea: +.export test03ea: far + ldx #$3ea + jsl init_test + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + phb + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03eb: +.export test03eb: far + ldx #$3eb + jsl init_test + lda #$7f + pha + plb + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + phb + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$7f + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ec: +.export test03ec: far + ldx #$3ec + jsl init_test + rep #$20 + .a16 + lda #$6543 + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + phd + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ed + bne @to_fail + lda $0001ee + cmp #$43 + bne @to_fail + lda $0001ef + cmp #$65 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ed: +.export test03ed: far + ldx #$3ed + jsl init_test + rep #$20 + .a16 + lda #$1357 + tcd + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + phd + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01fe + bne @to_fail + lda $0000ff + cmp #$57 + bne @to_fail + lda $000100 + cmp #$13 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ee: +.export test03ee: far + ldx #$3ee + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8001 + lda #<@ok + sta $7e8002 + lda #>@ok + sta $7e8003 + lda #^@ok + sta $7e8004 + lda #$4b + sta $7e8000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e8000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$7e + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ef: +.export test03ef: far + ldx #$3ef + jsl init_test + lda #$5C ; jmp long opcode + sta $7e8001 + lda #<@ok + sta $7e8002 + lda #>@ok + sta $7e8003 + lda #^@ok + sta $7e8004 + lda #$4b + sta $7e8000 + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7e8000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$7e + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f0: +.export test03f0: far + ldx #$3f0 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f5 + sep #$0a + php + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000a + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ee + bne @to_fail + lda $0001ef + cmp #$0a + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f1: +.export test03f1: far + ldx #$3f1 + jsl init_test + rep #$20 + .a16 + ldx #$0100 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + php + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + lda $000100 + cmp #$ff + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f2: +.export test03f2: far + ldx #$3f2 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sep #$FF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f3: +.export test03f3: far + ldx #$3f3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ee + sep #$11 + .i8 + sep #$0F + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f4: +.export test03f4: far + ldx #$3f4 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rep #$F0 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$000f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f5: +.export test03f5: far + ldx #$3f5 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rep #$0F + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00f0 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f6: +.export test03f6: far + ldx #$3f6 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$c5 + sep #$3a + .a8 + .i8 + rep #$38 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f7: +.export test03f7: far + ldx #$3f7 + jsl init_test + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f8: +.export test03f8: far + ldx #$3f8 + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03f9: +.export test03f9: far + ldx #$3f9 + jsl init_test + lda #$00 + sta $7effff + lda #$80 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fa: +.export test03fa: far + ldx #$3fa + jsl init_test + lda #$00 + sta $000134 + lda #$80 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fb: +.export test03fb: far + ldx #$3fb + jsl init_test + lda #$00 + sta $000033 + lda #$80 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fc: +.export test03fc: far + ldx #$3fc + jsl init_test + lda #$00 + sta $7f02ff + lda #$80 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fd: +.export test03fd: far + ldx #$3fd + jsl init_test + lda #$00 + sta $7f002f + lda #$80 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03fe: +.export test03fe: far + ldx #$3fe + jsl init_test + rep #$20 + .a16 + lda #$4111 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$8223 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test03ff: +.export test03ff: far + ldx #$3ff + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$23 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0400: +.export test0400: far + ldx #$400 + jsl init_test + lda #$11 + sta $7effff + lda #$41 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$23 + bne @to_fail + lda $7f0000 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0401: +.export test0401: far + ldx #$401 + jsl init_test + lda #$11 + sta $000134 + lda #$41 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$23 + bne @to_fail + lda $000135 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0402: +.export test0402: far + ldx #$402 + jsl init_test + lda #$11 + sta $000033 + lda #$41 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$23 + bne @to_fail + lda $000034 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0403: +.export test0403: far + ldx #$403 + jsl init_test + lda #$11 + sta $7f02ff + lda #$41 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$23 + bne @to_fail + lda $7f0300 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0404: +.export test0404: far + ldx #$404 + jsl init_test + lda #$11 + sta $7f002f + lda #$41 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$23 + bne @to_fail + lda $7f0030 + cmp #$82 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0405: +.export test0405: far + ldx #$405 + jsl init_test + rep #$20 + .a16 + lda #$1280 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0406: +.export test0406: far + ldx #$406 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0407: +.export test0407: far + ldx #$407 + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0408: +.export test0408: far + ldx #$408 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0409: +.export test0409: far + ldx #$409 + jsl init_test + lda #$80 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040a: +.export test040a: far + ldx #$40a + jsl init_test + lda #$80 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040b: +.export test040b: far + ldx #$40b + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040c: +.export test040c: far + ldx #$40c + jsl init_test + lda #$80 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040d: +.export test040d: far + ldx #$40d + jsl init_test + lda #$80 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + rol $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040e: +.export test040e: far + ldx #$40e + jsl init_test + lda #$80 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test040f: +.export test040f: far + ldx #$40f + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0410: +.export test0410: far + ldx #$410 + jsl init_test + lda #$80 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0411: +.export test0411: far + ldx #$411 + jsl init_test + rep #$20 + .a16 + lda #$1241 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1283 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0412: +.export test0412: far + ldx #$412 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0413: +.export test0413: far + ldx #$413 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + rol $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0414: +.export test0414: far + ldx #$414 + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0415: +.export test0415: far + ldx #$415 + jsl init_test + lda #$41 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + rol $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0416: +.export test0416: far + ldx #$416 + jsl init_test + lda #$41 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0417: +.export test0417: far + ldx #$417 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0418: +.export test0418: far + ldx #$418 + jsl init_test + lda #$41 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + rol $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0419: +.export test0419: far + ldx #$419 + jsl init_test + lda #$41 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + rol $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041a: +.export test041a: far + ldx #$41a + jsl init_test + lda #$41 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041b: +.export test041b: far + ldx #$41b + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041c: +.export test041c: far + ldx #$41c + jsl init_test + lda #$41 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + rol $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$83 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041d: +.export test041d: far + ldx #$41d + jsl init_test + rep #$20 + .a16 + lda #$0001 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041e: +.export test041e: far + ldx #$41e + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test041f: +.export test041f: far + ldx #$41f + jsl init_test + lda #$01 + sta $7effff + lda #$00 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0420: +.export test0420: far + ldx #$420 + jsl init_test + lda #$01 + sta $000134 + lda #$00 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0421: +.export test0421: far + ldx #$421 + jsl init_test + lda #$01 + sta $000033 + lda #$00 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0422: +.export test0422: far + ldx #$422 + jsl init_test + lda #$01 + sta $7f02ff + lda #$00 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0423: +.export test0423: far + ldx #$423 + jsl init_test + lda #$01 + sta $7f002f + lda #$00 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0424: +.export test0424: far + ldx #$424 + jsl init_test + rep #$20 + .a16 + lda #$4222 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$a111 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0425: +.export test0425: far + ldx #$425 + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0426: +.export test0426: far + ldx #$426 + jsl init_test + lda #$22 + sta $7effff + lda #$42 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$11 + bne @to_fail + lda $7f0000 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0427: +.export test0427: far + ldx #$427 + jsl init_test + lda #$22 + sta $000134 + lda #$42 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$11 + bne @to_fail + lda $000135 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0428: +.export test0428: far + ldx #$428 + jsl init_test + lda #$22 + sta $000033 + lda #$42 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$11 + bne @to_fail + lda $000034 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0429: +.export test0429: far + ldx #$429 + jsl init_test + lda #$22 + sta $7f02ff + lda #$42 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$11 + bne @to_fail + lda $7f0300 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042a: +.export test042a: far + ldx #$42a + jsl init_test + lda #$22 + sta $7f002f + lda #$42 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00dc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$11 + bne @to_fail + lda $7f0030 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042b: +.export test042b: far + ldx #$42b + jsl init_test + rep #$20 + .a16 + lda #$1201 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042c: +.export test042c: far + ldx #$42c + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042d: +.export test042d: far + ldx #$42d + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042e: +.export test042e: far + ldx #$42e + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test042f: +.export test042f: far + ldx #$42f + jsl init_test + lda #$01 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0430: +.export test0430: far + ldx #$430 + jsl init_test + lda #$01 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0431: +.export test0431: far + ldx #$431 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0432: +.export test0432: far + ldx #$432 + jsl init_test + lda #$01 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0433: +.export test0433: far + ldx #$433 + jsl init_test + lda #$01 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ror $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0434: +.export test0434: far + ldx #$434 + jsl init_test + lda #$01 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0435: +.export test0435: far + ldx #$435 + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0436: +.export test0436: far + ldx #$436 + jsl init_test + lda #$01 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0437: +.export test0437: far + ldx #$437 + jsl init_test + rep #$20 + .a16 + lda #$1242 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror a + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$12a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0438: +.export test0438: far + ldx #$438 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0439: +.export test0439: far + ldx #$439 + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + ror $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043a: +.export test043a: far + ldx #$43a + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043b: +.export test043b: far + ldx #$43b + jsl init_test + lda #$42 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + ror $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043c: +.export test043c: far + ldx #$43c + jsl init_test + lda #$42 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043d: +.export test043d: far + ldx #$43d + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043e: +.export test043e: far + ldx #$43e + jsl init_test + lda #$42 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + ror $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test043f: +.export test043f: far + ldx #$43f + jsl init_test + lda #$42 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + ror $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0440: +.export test0440: far + ldx #$440 + jsl init_test + lda #$42 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ec + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0441: +.export test0441: far + ldx #$441 + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0442: +.export test0442: far + ldx #$442 + jsl init_test + lda #$42 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + ror $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fc + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$a1 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0443: +.export test0443: far + ldx #$443 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$60 + sta $7e8000 + lda #$ff + sta $0001f0 + lda #$ff + sta $0001f1 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + jml $7e8000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f1 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0444: +.export test0444: far + ldx #$444 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$60 + sta $7e8000 + lda #$ff + sta $000100 + lda #$ff + sta $000101 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + jml $7e8000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0101 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0445: +.export test0445: far + ldx #$445 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$ff + sta $0001f0 + lda #$ff + sta $0001f1 + lda #$7e + sta $0001f2 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + rtl + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f2 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0446: +.export test0446: far + ldx #$446 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$5C ; jmp long opcode + sta $7f1000 + lda #<@not_ok + sta $7f1001 + lda #>@not_ok + sta $7f1002 + lda #^@not_ok + sta $7f1003 + lda #$ff + sta $000200 + lda #$ff + sta $000201 + lda #$7e + sta $000202 + lda #$ff + sta $000100 + lda #$0f + sta $000101 + lda #$7f + sta $000102 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + rtl +@not_ok: + jsr bank3_save_results + bra @to_fail +@ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0102 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0447: +.export test0447: far + ldx #$447 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$88 + sta $0001f0 + lda #$00 + sta $0001f1 + lda #$00 + sta $0001f2 + lda #$7e + sta $0001f3 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fc + sep #$03 + rti + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0088 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01f3 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0448: +.export test0448: far + ldx #$448 + jsl init_test + lda #$5C ; jmp long opcode + sta $7e0000 + lda #<@ok + sta $7e0001 + lda #>@ok + sta $7e0002 + lda #^@ok + sta $7e0003 + lda #$40 + sta $7e8000 + lda #$88 + sta $000100 + lda #$00 + sta $000101 + lda #$00 + sta $000102 + rep #$20 + .a16 + ldx #$01ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$fc + sep #$03 + .a8 + .i8 + jml $7e8000 + @ok: + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b8 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0102 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0449: +.export test0449: far + ldx #$449 + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc #$908f + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044a: +.export test044a: far + ldx #$44a + jsl init_test + lda #$8f + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044b: +.export test044b: far + ldx #$44b + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044c: +.export test044c: far + ldx #$44c + jsl init_test + lda #$8f + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044d: +.export test044d: far + ldx #$44d + jsl init_test + lda #$8f + sta $000201 + lda #$90 + sta $000202 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$8f + bne @to_fail + lda $000202 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044e: +.export test044e: far + ldx #$44e + jsl init_test + lda #$8f + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test044f: +.export test044f: far + ldx #$44f + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7f1234 + lda #$90 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0450: +.export test0450: far + ldx #$450 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0451: +.export test0451: far + ldx #$451 + jsl init_test + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0452: +.export test0452: far + ldx #$452 + jsl init_test + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0453: +.export test0453: far + ldx #$453 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0454: +.export test0454: far + ldx #$454 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0455: +.export test0455: far + ldx #$455 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0456: +.export test0456: far + ldx #$456 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8f + sta $7f1234 + lda #$90 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0457: +.export test0457: far + ldx #$457 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0458: +.export test0458: far + ldx #$458 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0459: +.export test0459: far + ldx #$459 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045a: +.export test045a: far + ldx #$45a + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045b: +.export test045b: far + ldx #$45b + jsl init_test + lda #$8f + sta $000134 + lda #$90 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$8f + bne @to_fail + lda $000135 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045c: +.export test045c: far + ldx #$45c + jsl init_test + lda #$8f + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045d: +.export test045d: far + ldx #$45d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7f0fdc + lda #$90 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045e: +.export test045e: far + ldx #$45e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7ffeec + lda #$90 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test045f: +.export test045f: far + ldx #$45f + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0460: +.export test0460: far + ldx #$460 + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0461: +.export test0461: far + ldx #$461 + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0462: +.export test0462: far + ldx #$462 + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0463: +.export test0463: far + ldx #$463 + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0464: +.export test0464: far + ldx #$464 + jsl init_test + lda #$8f + sta $7f02ff + lda #$90 + sta $7f0300 + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0003 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0465: +.export test0465: far + ldx #$465 + jsl init_test + lda #$8f + sta $7f002f + lda #$90 + sta $7f0030 + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0013 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0466: +.export test0466: far + ldx #$466 + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + sbc #$2000 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0041 + bne @to_fail + ldx result_a + cpx #$7090 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0467: +.export test0467: far + ldx #$467 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$b8 + sep #$47 + sbc #$1235 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0084 + bne @to_fail + ldx result_a + cpx #$ffff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0468: +.export test0468: far + ldx #$468 + jsl init_test + rep #$20 + .a16 + lda #$7000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sbc #$a000 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c0 + bne @to_fail + ldx result_a + cpx #$cfff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0469: +.export test0469: far + ldx #$469 + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc #$8f + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test046a: +.export test046a: far + ldx #$46a + jsl init_test + lda #$8f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test046b: +.export test046b: far + ldx #$46b + jsl init_test + lda #$8f + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc90 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test046c: +.export test046c: far + ldx #$46c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($EF,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test046d: +.export test046d: far + ldx #$46d + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($F0,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test046e: +.export test046e: far + ldx #$46e + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc90 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($F6,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test046f: +.export test046f: far + ldx #$46f + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc90 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($F7,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0470: +.export test0470: far + ldx #$470 + jsl init_test + lda #$8f + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0471: +.export test0471: far + ldx #$471 + jsl init_test + lda #$8f + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0472: +.export test0472: far + ldx #$472 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0473: +.export test0473: far + ldx #$473 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0474: +.export test0474: far + ldx #$474 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0475: +.export test0475: far + ldx #$475 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$8f + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc [$FF] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0476: +.export test0476: far + ldx #$476 + jsl init_test + lda #$8f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0477: +.export test0477: far + ldx #$477 + jsl init_test + lda #$8f + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0478: +.export test0478: far + ldx #$478 + jsl init_test + lda #$8f + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0479: +.export test0479: far + ldx #$479 + jsl init_test + lda #$8f + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047a: +.export test047a: far + ldx #$47a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047b: +.export test047b: far + ldx #$47b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$8f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047c: +.export test047c: far + ldx #$47c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$8f + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($FF),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047d: +.export test047d: far + ldx #$47d + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$8f + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($FE),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047e: +.export test047e: far + ldx #$47e + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test047f: +.export test047f: far + ldx #$47f + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($FF) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0480: +.export test0480: far + ldx #$480 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$8f + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($FE) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0481: +.export test0481: far + ldx #$481 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0482: +.export test0482: far + ldx #$482 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$8f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0483: +.export test0483: far + ldx #$483 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$8f + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc ($12,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0484: +.export test0484: far + ldx #$484 + jsl init_test + lda #$8f + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0485: +.export test0485: far + ldx #$485 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0486: +.export test0486: far + ldx #$486 + jsl init_test + lda #$8f + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0487: +.export test0487: far + ldx #$487 + jsl init_test + lda #$8f + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000133 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0488: +.export test0488: far + ldx #$488 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$8f + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0489: +.export test0489: far + ldx #$489 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$8f + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sbc [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048a: +.export test048a: far + ldx #$48a + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$8f + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc [$FF],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048b: +.export test048b: far + ldx #$48b + jsl init_test + lda #$8f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048c: +.export test048c: far + ldx #$48c + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048d: +.export test048d: far + ldx #$48d + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048e: +.export test048e: far + ldx #$48e + jsl init_test + lda #$8f + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test048f: +.export test048f: far + ldx #$48f + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0490: +.export test0490: far + ldx #$490 + jsl init_test + lda #$8f + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0491: +.export test0491: far + ldx #$491 + jsl init_test + lda #$8f + sta $7f02ff + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0023 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0492: +.export test0492: far + ldx #$492 + jsl init_test + lda #$8f + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0033 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0493: +.export test0493: far + ldx #$493 + jsl init_test + lda #$8f + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0133 + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$8f + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0494: +.export test0494: far + ldx #$494 + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$de + sep #$21 + .a8 + sbc #$20 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0061 + bne @to_fail + ldx result_a + cpx #$cc70 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0495: +.export test0495: far + ldx #$495 + jsl init_test + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$98 + sep #$67 + .a8 + sbc #$13 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a4 + bne @to_fail + ldx result_a + cpx #$ccff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0496: +.export test0496: far + ldx #$496 + jsl init_test + rep #$20 + .a16 + lda #$cc70 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sbc #$a0 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e0 + bne @to_fail + ldx result_a + cpx #$cccf + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0497: +.export test0497: far + ldx #$497 + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$ff91 + ldy #$5678 + rep #$ff + sep #$00 + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0498: +.export test0498: far + ldx #$498 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$0123 + ldy #$5678 + rep #$ff + sep #$00 + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0499: +.export test0499: far + ldx #$499 + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$1210 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049a: +.export test049a: far + ldx #$49a + jsl init_test + lda #$34 + sta $000201 + lda #$12 + sta $000202 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049b: +.export test049b: far + ldx #$49b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049c: +.export test049c: far + ldx #$49c + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049d: +.export test049d: far + ldx #$49d + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049e: +.export test049e: far + ldx #$49e + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test049f: +.export test049f: far + ldx #$49f + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a0: +.export test04a0: far + ldx #$4a0 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a1: +.export test04a1: far + ldx #$4a1 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a2: +.export test04a2: far + ldx #$4a2 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a3: +.export test04a3: far + ldx #$4a3 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a4: +.export test04a4: far + ldx #$4a4 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + sta ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a5: +.export test04a5: far + ldx #$4a5 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a6: +.export test04a6: far + ldx #$4a6 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a7: +.export test04a7: far + ldx #$4a7 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a8: +.export test04a8: far + ldx #$4a8 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04a9: +.export test04a9: far + ldx #$4a9 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04aa: +.export test04aa: far + ldx #$4aa + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$ff + sep #$00 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ab: +.export test04ab: far + ldx #$4ab + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$ef + sep #$10 + .i8 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ac: +.export test04ac: far + ldx #$4ac + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$ff + sep #$00 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ad: +.export test04ad: far + ldx #$4ad + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$0300 + rep #$ff + sep #$00 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ae: +.export test04ae: far + ldx #$4ae + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1230 + rep #$ef + sep #$10 + .i8 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04af: +.export test04af: far + ldx #$4af + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b0: +.export test04b0: far + ldx #$4b0 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b1: +.export test04b1: far + ldx #$4b1 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b2: +.export test04b2: far + ldx #$4b2 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b3: +.export test04b3: far + ldx #$4b3 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$ff + sep #$00 + stx $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b4: +.export test04b4: far + ldx #$4b4 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$ff + sep #$00 + stx $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b5: +.export test04b5: far + ldx #$4b5 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$0133 + rep #$ff + sep #$00 + stx $02,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b6: +.export test04b6: far + ldx #$4b6 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$ff + sep #$00 + sty $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b7: +.export test04b7: far + ldx #$4b7 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$ff + sep #$00 + sty $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b8: +.export test04b8: far + ldx #$4b8 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$8000 + rep #$ff + sep #$00 + sty $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04b9: +.export test04b9: far + ldx #$4b9 + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$ff91 + ldy #$5678 + rep #$30 + sep #$cf + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ba: +.export test04ba: far + ldx #$4ba + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$0123 + ldy #$5678 + rep #$30 + sep #$cf + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04bb: +.export test04bb: far + ldx #$4bb + jsl init_test + lda #$34 + sta $7f1212 + lda #$12 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$8000 + ldx #$1210 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + lda $7f1213 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04bc: +.export test04bc: far + ldx #$4bc + jsl init_test + lda #$34 + sta $000201 + lda #$12 + sta $000202 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + lda $000202 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04bd: +.export test04bd: far + ldx #$4bd + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04be: +.export test04be: far + ldx #$4be + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04bf: +.export test04bf: far + ldx #$4bf + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c0: +.export test04c0: far + ldx #$4c0 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c1: +.export test04c1: far + ldx #$4c1 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c2: +.export test04c2: far + ldx #$4c2 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c3: +.export test04c3: far + ldx #$4c3 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c4: +.export test04c4: far + ldx #$4c4 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c5: +.export test04c5: far + ldx #$4c5 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$34 + sta $7f1234 + lda #$12 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + lda $7f1235 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c6: +.export test04c6: far + ldx #$4c6 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + sta ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c7: +.export test04c7: far + ldx #$4c7 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c8: +.export test04c8: far + ldx #$4c8 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04c9: +.export test04c9: far + ldx #$4c9 + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ca: +.export test04ca: far + ldx #$4ca + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04cb: +.export test04cb: far + ldx #$4cb + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04cc: +.export test04cc: far + ldx #$4cc + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7f0fdc + lda #$12 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1100 + rep #$30 + sep #$cf + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + lda $7f0fdd + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04cd: +.export test04cd: far + ldx #$4cd + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$34 + sta $7ffeec + lda #$12 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1110 + rep #$20 + sep #$df + .i8 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + lda $7ffeed + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ce: +.export test04ce: far + ldx #$4ce + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$8000 + ldx #$3456 + ldy #$1111 + rep #$30 + sep #$cf + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04cf: +.export test04cf: far + ldx #$4cf + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$0300 + rep #$30 + sep #$cf + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d0: +.export test04d0: far + ldx #$4d0 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$3456 + ldy #$1230 + rep #$20 + sep #$df + .i8 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d1: +.export test04d1: far + ldx #$4d1 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d2: +.export test04d2: far + ldx #$4d2 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d3: +.export test04d3: far + ldx #$4d3 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + rep #$20 + .a16 + lda #$8000 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d4: +.export test04d4: far + ldx #$4d4 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + rep #$20 + .a16 + lda #$8000 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d5: +.export test04d5: far + ldx #$4d5 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$30 + sep #$cf + stx $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d6: +.export test04d6: far + ldx #$4d6 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$8000 + ldy #$5678 + rep #$30 + sep #$cf + stx $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d7: +.export test04d7: far + ldx #$4d7 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$8000 + ldy #$0133 + rep #$30 + sep #$cf + stx $02,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8000 + bne @to_fail + cpy #$0133 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d8: +.export test04d8: far + ldx #$4d8 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$30 + sep #$cf + sty $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04d9: +.export test04d9: far + ldx #$4d9 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$8000 + rep #$30 + sep #$cf + sty $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04da: +.export test04da: far + ldx #$4da + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$8000 + rep #$30 + sep #$cf + sty $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$8000 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04db: +.export test04db: far + ldx #$4db + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$ff91 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04dc: +.export test04dc: far + ldx #$4dc + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$5500 + ldx #$1210 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04dd: +.export test04dd: far + ldx #$4dd + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($EF,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04de: +.export test04de: far + ldx #$4de + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($F0,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04df: +.export test04df: far + ldx #$4df + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$5500 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($F6,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test04e0: +.export test04e0: far + ldx #$4e0 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$5500 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($F7,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e1: +.export test04e1: far + ldx #$4e1 + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e2: +.export test04e2: far + ldx #$4e2 + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e3: +.export test04e3: far + ldx #$4e3 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e4: +.export test04e4: far + ldx #$4e4 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e5: +.export test04e5: far + ldx #$4e5 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e6: +.export test04e6: far + ldx #$4e6 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta [$FF] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e7: +.export test04e7: far + ldx #$4e7 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e8: +.export test04e8: far + ldx #$4e8 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04e9: +.export test04e9: far + ldx #$4e9 + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ea: +.export test04ea: far + ldx #$4ea + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $7EFFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04eb: +.export test04eb: far + ldx #$4eb + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ec: +.export test04ec: far + ldx #$4ec + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($34),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ed: +.export test04ed: far + ldx #$4ed + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($FF),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ee: +.export test04ee: far + ldx #$4ee + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$12 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($FE),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ef: +.export test04ef: far + ldx #$4ef + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta ($34) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f0: +.export test04f0: far + ldx #$4f0 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($FF) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f1: +.export test04f1: far + ldx #$4f1 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($FE) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f2: +.export test04f2: far + ldx #$4f2 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f3: +.export test04f3: far + ldx #$4f3 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta ($10,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f4: +.export test04f4: far + ldx #$4f4 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta ($12,s),y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f5: +.export test04f5: far + ldx #$4f5 + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f6: +.export test04f6: far + ldx #$4f6 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f7: +.export test04f7: far + ldx #$4f7 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f8: +.export test04f8: far + ldx #$4f8 + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04f9: +.export test04f9: far + ldx #$4f9 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$12 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$df + sep #$20 + .a8 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04fa: +.export test04fa: far + ldx #$4fa + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$cf + sep #$30 + .a8 + .i8 + sta [$34],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04fb: +.export test04fb: far + ldx #$4fb + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$12 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta [$FF],y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04fc: +.export test04fc: far + ldx #$4fc + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$0300 + rep #$df + sep #$20 + .a8 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04fd: +.export test04fd: far + ldx #$4fd + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + rep #$cf + sep #$30 + .a8 + .i8 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04fe: +.export test04fe: far + ldx #$4fe + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $FFFF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test04ff: +.export test04ff: far + ldx #$4ff + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0500: +.export test0500: far + ldx #$500 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0501: +.export test0501: far + ldx #$501 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $FFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0502: +.export test0502: far + ldx #$502 + jsl init_test + lda #$12 + sta $7f02ff + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0503: +.export test0503: far + ldx #$503 + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0504: +.export test0504: far + ldx #$504 + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + sta $7EFFFF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0505: +.export test0505: far + ldx #$505 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stx $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0506: +.export test0506: far + ldx #$506 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + stx $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0507: +.export test0507: far + ldx #$507 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stx $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0508: +.export test0508: far + ldx #$508 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + stx $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0509: +.export test0509: far + ldx #$509 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$1232 + rep #$ef + sep #$10 + .i8 + stx $02,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050a: +.export test050a: far + ldx #$50a + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$0032 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + stx $02,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050b: +.export test050b: far + ldx #$50b + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0000 + ldy #$0034 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + stx $FF,y + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0034 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050c: +.export test050c: far + ldx #$50c + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050d: +.export test050d: far + ldx #$50d + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + sty $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050e: +.export test050e: far + ldx #$50e + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test050f: +.export test050f: far + ldx #$50f + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + sty $FFFF + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0510: +.export test0510: far + ldx #$510 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + sty $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0511: +.export test0511: far + ldx #$511 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$0000 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + sty $02,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0512: +.export test0512: far + ldx #$512 + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$0000 + sec + xce + rep #$ef + sep #$10 + .a8 + .i8 + sty $FF,x + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0513: +.export test0513: far + ldx #$513 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$ff91 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta ($10,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0514: +.export test0514: far + ldx #$514 + jsl init_test + lda #$12 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$5500 + ldx #$1210 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($90,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1212 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0515: +.export test0515: far + ldx #$515 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($EF,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0516: +.export test0516: far + ldx #$516 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($F0,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0517: +.export test0517: far + ldx #$517 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$5500 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($F6,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0518: +.export test0518: far + ldx #$518 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$5500 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($F7,x) + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0519: +.export test0519: far + ldx #$519 + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test051a: +.export test051a: far + ldx #$51a + jsl init_test + lda #$12 + sta $000201 + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $12,s + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000201 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test051b: +.export test051b: far + ldx #$51b + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test051c: +.export test051c: far + ldx #$51c + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $34 + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test051d: +.export test051d: far + ldx #$51d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta [$34] + jsr bank3_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml test051e + +.segment "BANK4" + +bank4_save_results: + ; At this point we don't know the values of DBR or D, so should use only long addressing + php + sep #$20 + .a8 + sta f:result_a + pla + sta f:result_p + pla ; low byte of return addr + sta f:retaddr + pla ; high byte of return addr + sta f:retaddr+1 + clc + xce ; E mode = 0, so that stack doesn't wrap (which causes issues for some emulators with jsl) + php + pla + and #$01 + sta f:result_p+1 + lda f:result_a + jsl save_results + ldx retaddr + phx + ldx result_x + rts + +test051e: +.export test051e: far + ldx #$51e + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$12 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta [$FF] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test051f: +.export test051f: far + ldx #$51f + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0520: +.export test0520: far + ldx #$520 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0521: +.export test0521: far + ldx #$521 + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0522: +.export test0522: far + ldx #$522 + jsl init_test + lda #$12 + sta $7effff + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0523: +.export test0523: far + ldx #$523 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0524: +.export test0524: far + ldx #$524 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0525: +.export test0525: far + ldx #$525 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($FF),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0526: +.export test0526: far + ldx #$526 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$12 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($FE),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0527: +.export test0527: far + ldx #$527 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0528: +.export test0528: far + ldx #$528 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($FF) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0529: +.export test0529: far + ldx #$529 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$12 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$5500 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($FE) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1234 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052a: +.export test052a: far + ldx #$52a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052b: +.export test052b: far + ldx #$52b + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052c: +.export test052c: far + ldx #$52c + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$12 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta ($12,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052d: +.export test052d: far + ldx #$52d + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0133 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052e: +.export test052e: far + ldx #$52e + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$1232 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test052f: +.export test052f: far + ldx #$52f + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0530: +.export test0530: far + ldx #$530 + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $FF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0531: +.export test0531: far + ldx #$531 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$12 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1100 + rep #$10 + sep #$ef + .a8 + sta [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f0fdc + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0532: +.export test0532: far + ldx #$532 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$12 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5500 + ldx #$3456 + ldy #$1110 + rep #$00 + sep #$ff + .a8 + .i8 + sta [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7ffeec + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0533: +.export test0533: far + ldx #$533 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$12 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$5500 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta [$FF],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f1244 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0534: +.export test0534: far + ldx #$534 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$0300 + rep #$10 + sep #$ef + .a8 + sta $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0535: +.export test0535: far + ldx #$535 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + rep #$00 + sep #$ff + .a8 + .i8 + sta $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0536: +.export test0536: far + ldx #$536 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0537: +.export test0537: far + ldx #$537 + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0538: +.export test0538: far + ldx #$538 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0539: +.export test0539: far + ldx #$539 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053a: +.export test053a: far + ldx #$53a + jsl init_test + lda #$12 + sta $7f02ff + rep #$20 + .a16 + lda #$5500 + ldx #$0300 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + sta $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053b: +.export test053b: far + ldx #$53b + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + rep #$00 + sep #$ff + .a8 + .i8 + sta $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053c: +.export test053c: far + ldx #$53c + jsl init_test + lda #$12 + sta $7f002f + rep #$20 + .a16 + lda #$5500 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + sta $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$5500 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053d: +.export test053d: far + ldx #$53d + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stx $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053e: +.export test053e: far + ldx #$53e + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + stx $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test053f: +.export test053f: far + ldx #$53f + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stx $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0540: +.export test0540: far + ldx #$540 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + stx $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0541: +.export test0541: far + ldx #$541 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$1232 + rep #$20 + sep #$df + .i8 + stx $02,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0542: +.export test0542: far + ldx #$542 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0000 + ldy #$0032 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + stx $02,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0032 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0543: +.export test0543: far + ldx #$543 + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0000 + ldy #$0034 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + stx $FF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0034 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0544: +.export test0544: far + ldx #$544 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0545: +.export test0545: far + ldx #$545 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$0000 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + sty $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0546: +.export test0546: far + ldx #$546 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0547: +.export test0547: far + ldx #$547 + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + sty $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0548: +.export test0548: far + ldx #$548 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$0000 + rep #$20 + sep #$df + .i8 + sty $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0549: +.export test0549: far + ldx #$549 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$0000 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + sty $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054a: +.export test054a: far + ldx #$54a + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$0000 + sec + xce + rep #$20 + sep #$df + .a8 + .i8 + sty $FF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$01ff + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054b: +.export test054b: far + ldx #$54b + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + stz $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054c: +.export test054c: far + ldx #$54c + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$ff + sep #$00 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054d: +.export test054d: far + ldx #$54d + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054e: +.export test054e: far + ldx #$54e + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + stz $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test054f: +.export test054f: far + ldx #$54f + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$ff + sep #$00 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0550: +.export test0550: far + ldx #$550 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0010 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0551: +.export test0551: far + ldx #$551 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + stz $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0552: +.export test0552: far + ldx #$552 + jsl init_test + lda #$34 + sta $000134 + lda #$12 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$30 + sep #$cf + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + lda $000135 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0553: +.export test0553: far + ldx #$553 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + lda $000034 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0554: +.export test0554: far + ldx #$554 + jsl init_test + lda #$34 + sta $7effff + lda #$12 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + stz $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + lda $7f0000 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0555: +.export test0555: far + ldx #$555 + jsl init_test + lda #$34 + sta $7f02ff + lda #$12 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$30 + sep #$cf + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cf + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + lda $7f0300 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0556: +.export test0556: far + ldx #$556 + jsl init_test + lda #$34 + sta $7f002f + lda #$12 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$20 + sep #$df + .i8 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00df + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + lda $7f0030 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0557: +.export test0557: far + ldx #$557 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0558: +.export test0558: far + ldx #$558 + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + stz $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0559: +.export test0559: far + ldx #$559 + jsl init_test + lda #$12 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000134 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055a: +.export test055a: far + ldx #$55a + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055b: +.export test055b: far + ldx #$55b + jsl init_test + lda #$12 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + stz $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000033 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055c: +.export test055c: far + ldx #$55c + jsl init_test + lda #$12 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$1234 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + stz $FF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $000133 + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055d: +.export test055d: far + ldx #$55d + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055e: +.export test055e: far + ldx #$55e + jsl init_test + lda #$12 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + stz $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7effff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test055f: +.export test055f: far + ldx #$55f + jsl init_test + lda #$12 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$df + sep #$20 + .a8 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f02ff + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0560: +.export test0560: far + ldx #$560 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$cf + sep #$30 + .a8 + .i8 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0030 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0561: +.export test0561: far + ldx #$561 + jsl init_test + lda #$12 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + stz $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + lda $7f002f + cmp #$00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0562: +.export test0562: far + ldx #$562 + jsl init_test + lda #$34 + sta $000033 + lda #$92 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $000033 + cmp #$04 + bne @to_fail + lda $000034 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0563: +.export test0563: far + ldx #$563 + jsl init_test + lda #$34 + sta $7effff + lda #$92 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $7effff + cmp #$04 + bne @to_fail + lda $7f0000 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0564: +.export test0564: far + ldx #$564 + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + lda $000034 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0565: +.export test0565: far + ldx #$565 + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + lda $7f0000 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0566: +.export test0566: far + ldx #$566 + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0567: +.export test0567: far + ldx #$567 + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0568: +.export test0568: far + ldx #$568 + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0569: +.export test0569: far + ldx #$569 + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056a: +.export test056a: far + ldx #$56a + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056b: +.export test056b: far + ldx #$56b + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + trb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056c: +.export test056c: far + ldx #$56c + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056d: +.export test056d: far + ldx #$56d + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + trb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$aa + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056e: +.export test056e: far + ldx #$56e + jsl init_test + lda #$34 + sta $000033 + lda #$92 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $000033 + cmp #$34 + bne @to_fail + lda $000034 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test056f: +.export test056f: far + ldx #$56f + jsl init_test + lda #$34 + sta $7effff + lda #$92 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1630 + ldx #$3456 + ldy #$5678 + rep #$30 + sep #$cf + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00cd + bne @to_fail + ldx result_a + cpx #$1630 + bne @to_fail + lda $7effff + cmp #$34 + bne @to_fail + lda $7f0000 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0570: +.export test0570: far + ldx #$570 + jsl init_test + lda #$aa + sta $000033 + lda #$aa + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + lda $000034 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0571: +.export test0571: far + ldx #$571 + jsl init_test + lda #$aa + sta $7effff + lda #$aa + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$5555 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$5555 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + lda $7f0000 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0572: +.export test0572: far + ldx #$572 + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0573: +.export test0573: far + ldx #$573 + jsl init_test + lda #$92 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0016 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $000033 + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0574: +.export test0574: far + ldx #$574 + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0575: +.export test0575: far + ldx #$575 + jsl init_test + lda #$92 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0016 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$10 + sep #$ef + .a8 + .i8 + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$0016 + bne @to_fail + lda $7effff + cmp #$96 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0576: +.export test0576: far + ldx #$576 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0577: +.export test0577: far + ldx #$577 + jsl init_test + lda #$aa + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + tsb $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $000033 + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0578: +.export test0578: far + ldx #$578 + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0579: +.export test0579: far + ldx #$579 + jsl init_test + lda #$aa + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$0055 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$df + sep #$20 + .a8 + .i8 + tsb $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0132 + bne @to_fail + ldx result_a + cpx #$0055 + bne @to_fail + lda $7effff + cmp #$ff + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057a: +.export test057a: far + ldx #$57a + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$5678 + ldy #$5678 + rep #$ff + sep #$00 + tax + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057b: +.export test057b: far + ldx #$57b + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$5678 + ldy #$5678 + rep #$ff + sep #$00 + tax + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057c: +.export test057c: far + ldx #$57c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tax + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$1234 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057d: +.export test057d: far + ldx #$57d + jsl init_test + rep #$20 + .a16 + lda #$87ab + ldx #$5678 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tax + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ab + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$87ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057e: +.export test057e: far + ldx #$57e + jsl init_test + rep #$20 + .a16 + lda #$8765 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tay + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$8765 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test057f: +.export test057f: far + ldx #$57f + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tay + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0580: +.export test0580: far + ldx #$580 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tay + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1234 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0581: +.export test0581: far + ldx #$581 + jsl init_test + rep #$20 + .a16 + lda #$87ab + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tay + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00ab + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$87ab + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0582: +.export test0582: far + ldx #$582 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$9876 + ldy #$5678 + rep #$ff + sep #$00 + txa + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$9876 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0583: +.export test0583: far + ldx #$583 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$ff + sep #$00 + txa + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0584: +.export test0584: far + ldx #$584 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$00cd + ldy #$5678 + rep #$20 + sep #$df + .i8 + txa + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00cd + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$00cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0585: +.export test0585: far + ldx #$585 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$abcd + ldy #$5678 + rep #$df + sep #$20 + .a8 + txa + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$abcd + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0586: +.export test0586: far + ldx #$586 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$ab00 + ldy #$5678 + rep #$df + sep #$20 + .a8 + txa + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ab00 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0587: +.export test0587: far + ldx #$587 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$9876 + rep #$ff + sep #$00 + tya + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$9876 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0588: +.export test0588: far + ldx #$588 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tya + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0589: +.export test0589: far + ldx #$589 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$00cd + rep #$20 + sep #$df + .i8 + tya + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$00cd + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$00cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058a: +.export test058a: far + ldx #$58a + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$abcd + rep #$df + sep #$20 + .a8 + tya + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$abcd + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$12cd + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058b: +.export test058b: far + ldx #$58b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$ab00 + rep #$df + sep #$20 + .a8 + tya + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$ab00 + bne @to_fail + ldx result_p + cpx #$0022 + bne @to_fail + ldx result_a + cpx #$1200 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058c: +.export test058c: far + ldx #$58c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$8765 + ldy #$5678 + rep #$ff + sep #$00 + txy + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058d: +.export test058d: far + ldx #$58d + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$5678 + rep #$12 + sep #$ed + .a8 + txy + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058e: +.export test058e: far + ldx #$58e + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0098 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + txy + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0098 + bne @to_fail + cpy #$0098 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test058f: +.export test058f: far + ldx #$58f + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$0098 + rep #$ef + sep #$10 + .i8 + txy + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0590: +.export test0590: far + ldx #$590 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$8765 + rep #$ff + sep #$00 + tyx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$8765 + bne @to_fail + cpy #$8765 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0591: +.export test0591: far + ldx #$591 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$5678 + ldy #$0000 + rep #$12 + sep #$ed + .a8 + tyx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$006f + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0592: +.export test0592: far + ldx #$592 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0000 + ldy #$0098 + rep #$ef + sep #$10 + .i8 + tyx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0098 + bne @to_fail + cpy #$0098 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0593: +.export test0593: far + ldx #$593 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0098 + ldy #$0000 + rep #$ef + sep #$10 + .i8 + tyx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0000 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0594: +.export test0594: far + ldx #$594 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tsx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$006d + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0595: +.export test0595: far + ldx #$595 + jsl init_test + rep #$20 + .a16 + ldx #$0200 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tsx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0000 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0012 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0596: +.export test0596: far + ldx #$596 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ef + sep #$10 + .i8 + tsx + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ef + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0090 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0597: +.export test0597: far + ldx #$597 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$20 + sep #$df + .i8 + tsc + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005d + bne @to_fail + ldx result_a + cpx #$01ef + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0598: +.export test0598: far + ldx #$598 + jsl init_test + rep #$20 + .a16 + ldx #$0200 + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tsc + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0020 + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test0599: +.export test0599: far + ldx #$599 + jsl init_test + rep #$20 + .a16 + ldx #$0000 + txs + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tsc + bne @not_ok + iny +@not_ok: + ldx #$1ef + txs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$0001 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test059a: +.export test059a: far + ldx #$59a + jsl init_test + rep #$20 + .a16 + ldx #$8000 + txs + lda #$1234 + ldx #$3456 + ldy #$0000 + rep #$ff + sep #$00 + tsc + bpl @not_ok + iny +@not_ok: + ldx #$1ef + txs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$01ef + bne @to_fail + cpy #$0001 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$8000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test059b: +.export test059b: far + ldx #$59b + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$0200 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + txs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0200 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test059c: +.export test059c: far + ldx #$59c + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$00ff + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + txs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ff + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test059d: +.export test059d: far + ldx #$59d + jsl init_test + rep #$20 + .a16 + lda #$0200 + ldx #$3456 + ldy #$5678 + rep #$10 + sep #$ef + .a8 + tcs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ef + bne @to_fail + ldx result_a + cpx #$0200 + bne @to_fail + ldx result_s + cpx #$0200 + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test059e: +.export test059e: far + ldx #$59e + jsl init_test + rep #$20 + .a16 + lda #$77ff + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + tcs + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$77ff + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test059f: +.export test059f: far + ldx #$59f + jsl init_test + rep #$20 + .a16 + lda #$1234 + tcd + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + tcd + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + ldx result_d + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a0: +.export test05a0: far + ldx #$5a0 + jsl init_test + rep #$20 + .a16 + lda #$9876 + ldx #$3456 + ldy #$5678 + rep #$90 + sep #$6f + .a8 + tcd + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00ed + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + ldx result_d + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a1: +.export test05a1: far + ldx #$5a1 + jsl init_test + rep #$20 + .a16 + lda #$9876 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + tcd + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01b0 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + ldx result_d + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a2: +.export test05a2: far + ldx #$5a2 + jsl init_test + rep #$20 + .a16 + lda #$9876 + tcd + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$df + sep #$20 + .a8 + tdc + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a0 + bne @to_fail + ldx result_a + cpx #$9876 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a3: +.export test05a3: far + ldx #$5a3 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$22 + sep #$dd + .i8 + tdc + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$005f + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a4: +.export test05a4: far + ldx #$5a4 + jsl init_test + rep #$20 + .a16 + lda #$9812 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xba + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0080 + bne @to_fail + ldx result_a + cpx #$1298 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a5: +.export test05a5: far + ldx #$5a5 + jsl init_test + rep #$20 + .a16 + lda #$00aa + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xba + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0002 + bne @to_fail + ldx result_a + cpx #$aa00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a6: +.export test05a6: far + ldx #$5a6 + jsl init_test + rep #$20 + .a16 + lda #$9812 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$00 + sep #$ff + .a8 + .i8 + xba + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$01fd + bne @to_fail + ldx result_a + cpx #$1298 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a7: +.export test05a7: far + ldx #$5a7 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$ff + sep #$00 + xce + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0000 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a8: +.export test05a8: far + ldx #$5a8 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$01 + sep #$fe + .a8 + .i8 + xce + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$00fe + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05a9: +.export test05a9: far + ldx #$5a9 + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$1234 + ldy #$4567 + rep #$fe + sep #$01 + xce + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0067 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05aa: +.export test05aa: far + ldx #$5aa + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$cf + sep #$30 + .a8 + .i8 + xce + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0031 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ab: +.export test05ab: far + ldx #$5ab + jsl init_test + rep #$20 + .a16 + ldx #$03ff + txs + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$fe + sep #$01 + xce + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$0130 + bne @to_fail + ldx result_a + cpx #$1234 + bne @to_fail + ldx result_s + cpx #$01ff + bne @to_fail + ldx #$1EF + txs + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ac: +.export test05ac: far + ldx #$5ac + jsl init_test + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc #$8765 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ad: +.export test05ad: far + ldx #$5ad + jsl init_test + lda #$65 + sta $7f1212 + lda #$87 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$ff91 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$65 + bne @to_fail + lda $7f1213 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ae: +.export test05ae: far + ldx #$5ae + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$0123 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05af: +.export test05af: far + ldx #$5af + jsl init_test + lda #$65 + sta $7f1212 + lda #$87 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$1234 + ldx #$1210 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc ($90,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$65 + bne @to_fail + lda $7f1213 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b0: +.export test05b0: far + ldx #$5b0 + jsl init_test + lda #$65 + sta $000201 + lda #$87 + sta $000202 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$65 + bne @to_fail + lda $000202 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b1: +.export test05b1: far + ldx #$5b1 + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$65 + bne @to_fail + lda $000034 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b2: +.export test05b2: far + ldx #$5b2 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$65 + sta $7f1234 + lda #$87 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$65 + bne @to_fail + lda $7f1235 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b3: +.export test05b3: far + ldx #$5b3 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b4: +.export test05b4: far + ldx #$5b4 + jsl init_test + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b5: +.export test05b5: far + ldx #$5b5 + jsl init_test + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b6: +.export test05b6: far + ldx #$5b6 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b7: +.export test05b7: far + ldx #$5b7 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b8: +.export test05b8: far + ldx #$5b8 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$f6 + sep #$09 + adc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05b9: +.export test05b9: far + ldx #$5b9 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$65 + sta $7f1234 + lda #$87 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$65 + bne @to_fail + lda $7f1235 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ba: +.export test05ba: far + ldx #$5ba + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + adc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05bb: +.export test05bb: far + ldx #$5bb + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05bc: +.export test05bc: far + ldx #$5bc + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05bd: +.export test05bd: far + ldx #$5bd + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$f6 + sep #$09 + adc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05be: +.export test05be: far + ldx #$5be + jsl init_test + lda #$65 + sta $000134 + lda #$87 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$0133 + ldy #$5678 + rep #$f6 + sep #$09 + adc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$65 + bne @to_fail + lda $000135 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05bf: +.export test05bf: far + ldx #$5bf + jsl init_test + lda #$65 + sta $000033 + lda #$87 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$1232 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$65 + bne @to_fail + lda $000034 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c0: +.export test05c0: far + ldx #$5c0 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$65 + sta $7f0fdc + lda #$87 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1100 + rep #$f6 + sep #$09 + adc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$65 + bne @to_fail + lda $7f0fdd + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c1: +.export test05c1: far + ldx #$5c1 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$65 + sta $7ffeec + lda #$87 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1110 + rep #$e6 + sep #$19 + .i8 + adc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$65 + bne @to_fail + lda $7ffeed + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c2: +.export test05c2: far + ldx #$5c2 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$65 + sta $7effff + lda #$87 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$1234 + ldx #$3456 + ldy #$1111 + rep #$f6 + sep #$09 + adc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$65 + bne @to_fail + lda $7f0000 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c3: +.export test05c3: far + ldx #$5c3 + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$0300 + rep #$f6 + sep #$09 + adc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c4: +.export test05c4: far + ldx #$5c4 + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$3456 + ldy #$1230 + rep #$e6 + sep #$19 + .i8 + adc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c5: +.export test05c5: far + ldx #$5c5 + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$f6 + sep #$09 + adc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c6: +.export test05c6: far + ldx #$5c6 + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c7: +.export test05c7: far + ldx #$5c7 + jsl init_test + lda #$65 + sta $7f02ff + lda #$87 + sta $7f0300 + rep #$20 + .a16 + lda #$1234 + ldx #$0300 + ldy #$5678 + rep #$f6 + sep #$09 + adc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$65 + bne @to_fail + lda $7f0300 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c8: +.export test05c8: far + ldx #$5c8 + jsl init_test + lda #$65 + sta $7f002f + lda #$87 + sta $7f0030 + rep #$20 + .a16 + lda #$1234 + ldx #$1230 + ldy #$5678 + rep #$e6 + sep #$19 + .i8 + adc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$65 + bne @to_fail + lda $7f0030 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05c9: +.export test05c9: far + ldx #$5c9 + jsl init_test + rep #$20 + .a16 + lda #$3550 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + adc #$4470 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00c8 + bne @to_fail + ldx result_a + cpx #$8020 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ca: +.export test05ca: far + ldx #$5ca + jsl init_test + rep #$20 + .a16 + lda #$4000 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + adc #$3999 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$7999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05cb: +.export test05cb: far + ldx #$5cb + jsl init_test + rep #$20 + .a16 + lda #$dcba + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + adc #$dbca + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0009 + bne @to_fail + ldx result_a + cpx #$1eea + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05cc: +.export test05cc: far + ldx #$5cc + jsl init_test + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc #$87 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05cd: +.export test05cd: far + ldx #$5cd + jsl init_test + lda #$87 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$ff91 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ce: +.export test05ce: far + ldx #$5ce + jsl init_test + lda #$87 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc12 + ldx #$1210 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($90,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05cf: +.export test05cf: far + ldx #$5cf + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($EF,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d0: +.export test05d0: far + ldx #$5d0 + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($F0,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d1: +.export test05d1: far + ldx #$5d1 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc12 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($F6,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test05d2: +.export test05d2: far + ldx #$5d2 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc12 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($F7,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d3: +.export test05d3: far + ldx #$5d3 + jsl init_test + lda #$87 + sta $000201 + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d4: +.export test05d4: far + ldx #$5d4 + jsl init_test + lda #$87 + sta $000201 + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d5: +.export test05d5: far + ldx #$5d5 + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d6: +.export test05d6: far + ldx #$5d6 + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d7: +.export test05d7: far + ldx #$5d7 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$87 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d8: +.export test05d8: far + ldx #$5d8 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$87 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc [$FF] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05d9: +.export test05d9: far + ldx #$5d9 + jsl init_test + lda #$87 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05da: +.export test05da: far + ldx #$5da + jsl init_test + lda #$87 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05db: +.export test05db: far + ldx #$5db + jsl init_test + lda #$87 + sta $7effff + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05dc: +.export test05dc: far + ldx #$5dc + jsl init_test + lda #$87 + sta $7effff + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05dd: +.export test05dd: far + ldx #$5dd + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$87 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05de: +.export test05de: far + ldx #$5de + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$87 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05df: +.export test05df: far + ldx #$5df + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$87 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($FF),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e0: +.export test05e0: far + ldx #$5e0 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$87 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc12 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($FE),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e1: +.export test05e1: far + ldx #$5e1 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e2: +.export test05e2: far + ldx #$5e2 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($FF) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e3: +.export test05e3: far + ldx #$5e3 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$87 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc12 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($FE) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e4: +.export test05e4: far + ldx #$5e4 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$87 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e5: +.export test05e5: far + ldx #$5e5 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$87 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e6: +.export test05e6: far + ldx #$5e6 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$87 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc ($12,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e7: +.export test05e7: far + ldx #$5e7 + jsl init_test + lda #$87 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$0133 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e8: +.export test05e8: far + ldx #$5e8 + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$1232 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05e9: +.export test05e9: far + ldx #$5e9 + jsl init_test + lda #$87 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ea: +.export test05ea: far + ldx #$5ea + jsl init_test + lda #$87 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $FF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000133 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05eb: +.export test05eb: far + ldx #$5eb + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$87 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1100 + rep #$d6 + sep #$29 + .a8 + adc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ec: +.export test05ec: far + ldx #$5ec + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$87 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc12 + ldx #$3456 + ldy #$1110 + rep #$c6 + sep #$39 + .a8 + .i8 + adc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ed: +.export test05ed: far + ldx #$5ed + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$87 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc12 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc [$FF],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ee: +.export test05ee: far + ldx #$5ee + jsl init_test + lda #$87 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$0300 + rep #$d6 + sep #$29 + .a8 + adc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ef: +.export test05ef: far + ldx #$5ef + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1230 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f0: +.export test05f0: far + ldx #$5f0 + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f1: +.export test05f1: far + ldx #$5f1 + jsl init_test + lda #$87 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$0300 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f2: +.export test05f2: far + ldx #$5f2 + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f3: +.export test05f3: far + ldx #$5f3 + jsl init_test + lda #$87 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f4: +.export test05f4: far + ldx #$5f4 + jsl init_test + lda #$87 + sta $7f02ff + rep #$20 + .a16 + lda #$cc12 + ldx #$0300 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + adc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f5: +.export test05f5: far + ldx #$5f5 + jsl init_test + lda #$87 + sta $7f002f + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + rep #$c6 + sep #$39 + .a8 + .i8 + adc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f6: +.export test05f6: far + ldx #$5f6 + jsl init_test + lda #$87 + sta $7f002f + rep #$20 + .a16 + lda #$cc12 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$d6 + sep #$29 + .a8 + .i8 + adc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$87 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f7: +.export test05f7: far + ldx #$5f7 + jsl init_test + rep #$20 + .a16 + lda #$cc40 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + adc #$40 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00e8 + bne @to_fail + ldx result_a + cpx #$cc80 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f8: +.export test05f8: far + ldx #$5f8 + jsl init_test + rep #$20 + .a16 + lda #$cc40 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + adc #$39 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0028 + bne @to_fail + ldx result_a + cpx #$cc79 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05f9: +.export test05f9: far + ldx #$5f9 + jsl init_test + rep #$20 + .a16 + lda #$ccdc + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + adc #$db + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0029 + bne @to_fail + ldx result_a + cpx #$cc1d + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05fa: +.export test05fa: far + ldx #$5fa + jsl init_test + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc #$9089 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05fb: +.export test05fb: far + ldx #$5fb + jsl init_test + lda #$89 + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$ff91 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05fc: +.export test05fc: far + ldx #$5fc + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$0123 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0123 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05fd: +.export test05fd: far + ldx #$5fd + jsl init_test + lda #$89 + sta $7f1212 + lda #$90 + sta $7f1213 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$9090 + ldx #$1210 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc ($90,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + lda $7f1213 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05fe: +.export test05fe: far + ldx #$5fe + jsl init_test + lda #$89 + sta $000201 + lda #$90 + sta $000202 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000201 + cmp #$89 + bne @to_fail + lda $000202 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test05ff: +.export test05ff: far + ldx #$5ff + jsl init_test + lda #$89 + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0600: +.export test0600: far + ldx #$600 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7f1234 + lda #$90 + sta $7f1235 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0601: +.export test0601: far + ldx #$601 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0602: +.export test0602: far + ldx #$602 + jsl init_test + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0603: +.export test0603: far + ldx #$603 + jsl init_test + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0604: +.export test0604: far + ldx #$604 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0605: +.export test0605: far + ldx #$605 + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0606: +.export test0606: far + ldx #$606 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$f7 + sep #$08 + sbc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0607: +.export test0607: far + ldx #$607 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$89 + sta $7f1234 + lda #$90 + sta $7f1235 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + lda $7f1235 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0608: +.export test0608: far + ldx #$608 + jsl init_test + lda #$ff + sta $000033 + lda #$ff + sta $000034 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$5678 + rep #$f7 + sep #$08 + sbc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0609: +.export test0609: far + ldx #$609 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060a: +.export test060a: far + ldx #$60a + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060b: +.export test060b: far + ldx #$60b + jsl init_test + lda #$ee + sta $0001ff + lda #$ee + sta $000200 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$f7 + sep #$08 + sbc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060c: +.export test060c: far + ldx #$60c + jsl init_test + lda #$89 + sta $000134 + lda #$90 + sta $000135 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$0133 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000134 + cmp #$89 + bne @to_fail + lda $000135 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060d: +.export test060d: far + ldx #$60d + jsl init_test + lda #$89 + sta $000033 + lda #$90 + sta $000034 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$1232 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + lda $000034 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060e: +.export test060e: far + ldx #$60e + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7f0fdc + lda #$90 + sta $7f0fdd + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1100 + rep #$f7 + sep #$08 + sbc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + lda $7f0fdd + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test060f: +.export test060f: far + ldx #$60f + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7ffeec + lda #$90 + sta $7ffeed + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1110 + rep #$e7 + sep #$18 + .i8 + sbc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + lda $7ffeed + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0610: +.export test0610: far + ldx #$610 + jsl init_test + lda #$ee + sta $000033 + lda #$ee + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7effff + lda #$90 + sta $7f0000 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$9090 + ldx #$3456 + ldy #$1111 + rep #$f7 + sep #$08 + sbc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1111 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + lda $7f0000 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0611: +.export test0611: far + ldx #$611 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$0300 + rep #$f7 + sep #$08 + sbc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0612: +.export test0612: far + ldx #$612 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$3456 + ldy #$1230 + rep #$e7 + sep #$18 + .i8 + sbc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0613: +.export test0613: far + ldx #$613 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0614: +.export test0614: far + ldx #$614 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0615: +.export test0615: far + ldx #$615 + jsl init_test + lda #$89 + sta $7f02ff + lda #$90 + sta $7f0300 + rep #$20 + .a16 + lda #$9090 + ldx #$0300 + ldy #$5678 + rep #$f7 + sep #$08 + sbc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$000b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + lda $7f0300 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0616: +.export test0616: far + ldx #$616 + jsl init_test + lda #$89 + sta $7f002f + lda #$90 + sta $7f0030 + rep #$20 + .a16 + lda #$9090 + ldx #$1230 + ldy #$5678 + rep #$e7 + sep #$18 + .i8 + sbc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$001b + bne @to_fail + ldx result_a + cpx #$0000 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + lda $7f0030 + cmp #$90 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0617: +.export test0617: far + ldx #$617 + jsl init_test + rep #$20 + .a16 + lda #$0000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$01 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0088 + bne @to_fail + ldx result_a + cpx #$9999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0618: +.export test0618: far + ldx #$618 + jsl init_test + rep #$20 + .a16 + lda #$1000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$9000 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0048 + bne @to_fail + ldx result_a + cpx #$2000 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0619: +.export test0619: far + ldx #$619 + jsl init_test + rep #$20 + .a16 + lda #$1000 + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$9001 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$1999 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061a: +.export test061a: far + ldx #$61a + jsl init_test + rep #$20 + .a16 + lda #$ab1d + ldx #$3456 + ldy #$5678 + rep #$f6 + sep #$09 + sbc #$f1e2 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0008 + bne @to_fail + ldx result_a + cpx #$59db + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061b: +.export test061b: far + ldx #$61b + jsl init_test + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc #$89 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061c: +.export test061c: far + ldx #$61c + jsl init_test + lda #$89 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$ff91 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc ($10,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$ff91 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061d: +.export test061d: far + ldx #$61d + jsl init_test + lda #$89 + sta $7f1212 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ff00 + tcd + lda #$cc90 + ldx #$1210 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($90,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1212 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061e: +.export test061e: far + ldx #$61e + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($EF,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test061f: +.export test061f: far + ldx #$61f + jsl init_test + lda #$34 + sta $000100 + lda #$12 + sta $000101 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0010 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($F0,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0010 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0620: +.export test0620: far + ldx #$620 + jsl init_test + lda #$34 + sta $0002fe + lda #$12 + sta $0002ff + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc90 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($F6,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +; This tests undocumented behavior - see the cputest README file for details +test0621: +.export test0621: far + ldx #$621 + jsl init_test + lda #$34 + sta $0002ff + lda #$12 + sta $000200 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$011a + tcd + lda #$cc90 + ldx #$00ee + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($F7,x) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$00ee + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0622: +.export test0622: far + ldx #$622 + jsl init_test + lda #$89 + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0623: +.export test0623: far + ldx #$623 + jsl init_test + lda #$89 + sta $000201 + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $12,s + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000201 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0624: +.export test0624: far + ldx #$624 + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0625: +.export test0625: far + ldx #$625 + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $34 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0626: +.export test0626: far + ldx #$626 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7f1234 + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc [$34] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0627: +.export test0627: far + ldx #$627 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$89 + sta $7f1234 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc [$FF] + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0628: +.export test0628: far + ldx #$628 + jsl init_test + lda #$89 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0629: +.export test0629: far + ldx #$629 + jsl init_test + lda #$89 + sta $7effff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $FFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062a: +.export test062a: far + ldx #$62a + jsl init_test + lda #$89 + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062b: +.export test062b: far + ldx #$62b + jsl init_test + lda #$89 + sta $7effff + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $7EFFFF + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7effff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062c: +.export test062c: far + ldx #$62c + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062d: +.export test062d: far + ldx #$62d + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$89 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($34),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062e: +.export test062e: far + ldx #$62e + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$89 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($FF),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test062f: +.export test062f: far + ldx #$62f + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$89 + sta $7f1244 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($FE),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0630: +.export test0630: far + ldx #$630 + jsl init_test + lda #$34 + sta $000033 + lda #$12 + sta $000034 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc ($34) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0631: +.export test0631: far + ldx #$631 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000100 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($FF) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0632: +.export test0632: far + ldx #$632 + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$00 + sta $000100 + lda #$89 + sta $7f1234 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0101 + tcd + lda #$cc90 + ldx #$3456 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($FE) + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1234 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0633: +.export test0633: far + ldx #$633 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7f0fdc + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0634: +.export test0634: far + ldx #$634 + jsl init_test + lda #$dc + sta $0001ff + lda #$fe + sta $000200 + lda #$89 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc ($10,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0635: +.export test0635: far + ldx #$635 + jsl init_test + lda #$dc + sta $000201 + lda #$fe + sta $000202 + lda #$89 + sta $7ffeec + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1110 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc ($12,s),y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0636: +.export test0636: far + ldx #$636 + jsl init_test + lda #$89 + sta $000134 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0133 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0133 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000134 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0637: +.export test0637: far + ldx #$637 + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$1232 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0638: +.export test0638: far + ldx #$638 + jsl init_test + lda #$89 + sta $000033 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$0032 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $02,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0032 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000033 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0639: +.export test0639: far + ldx #$639 + jsl init_test + lda #$89 + sta $000133 + lda #$7f + pha + plb + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$0034 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $FF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0034 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $000133 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063a: +.export test063a: far + ldx #$63a + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7e + sta $000035 + lda #$89 + sta $7f0fdc + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1100 + rep #$d7 + sep #$28 + .a8 + sbc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$1100 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f0fdc + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063b: +.export test063b: far + ldx #$63b + jsl init_test + lda #$dc + sta $000033 + lda #$fe + sta $000034 + lda #$7f + sta $000035 + lda #$89 + sta $7ffeec + rep #$20 + .a16 + lda #$ffff + tcd + lda #$cc90 + ldx #$3456 + ldy #$1110 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc [$34],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7ffeec + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063c: +.export test063c: far + ldx #$63c + jsl init_test + lda #$34 + sta $0001ff + lda #$12 + sta $000200 + lda #$7f + sta $000201 + lda #$89 + sta $7f1244 + rep #$20 + .a16 + lda #$0100 + tcd + lda #$cc90 + ldx #$3456 + ldy #$0010 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc [$FF],y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0010 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f1244 + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063d: +.export test063d: far + ldx #$63d + jsl init_test + lda #$89 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$0300 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$0300 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063e: +.export test063e: far + ldx #$63e + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test063f: +.export test063f: far + ldx #$63f + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$3456 + ldy #$1230 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $FFFF,y + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0056 + bne @to_fail + cpy #$0030 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0640: +.export test0640: far + ldx #$640 + jsl init_test + lda #$89 + sta $7f02ff + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0641: +.export test0641: far + ldx #$641 + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0642: +.export test0642: far + ldx #$642 + jsl init_test + lda #$89 + sta $7f002f + lda #$7e + pha + plb + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $FFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0643: +.export test0643: far + ldx #$643 + jsl init_test + lda #$89 + sta $7f02ff + rep #$20 + .a16 + lda #$cc90 + ldx #$0300 + ldy #$5678 + rep #$d7 + sep #$28 + .a8 + sbc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0300 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$002b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f02ff + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0644: +.export test0644: far + ldx #$644 + jsl init_test + lda #$89 + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + rep #$c7 + sep #$38 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$003b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0645: +.export test0645: far + ldx #$645 + jsl init_test + lda #$89 + sta $7f002f + rep #$20 + .a16 + lda #$cc90 + ldx #$1230 + ldy #$5678 + sec + xce + rep #$d7 + sep #$28 + .a8 + .i8 + sbc $7EFFFF,x + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$0030 + bne @to_fail + cpy #$0078 + bne @to_fail + ldx result_p + cpx #$013b + bne @to_fail + ldx result_a + cpx #$cc00 + bne @to_fail + lda $7f002f + cmp #$89 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0646: +.export test0646: far + ldx #$646 + jsl init_test + rep #$20 + .a16 + lda #$cc00 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$01 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$00a8 + bne @to_fail + ldx result_a + cpx #$cc99 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0647: +.export test0647: far + ldx #$647 + jsl init_test + rep #$20 + .a16 + lda #$cc10 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$90 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0068 + bne @to_fail + ldx result_a + cpx #$cc20 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0648: +.export test0648: far + ldx #$648 + jsl init_test + rep #$20 + .a16 + lda #$cc10 + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$91 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0028 + bne @to_fail + ldx result_a + cpx #$cc19 + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + +test0649: +.export test0649: far + ldx #$649 + jsl init_test + rep #$20 + .a16 + lda #$ccab + ldx #$3456 + ldy #$5678 + rep #$d6 + sep #$29 + .a8 + sbc #$f1 + jsr bank4_save_results ; now X=0, E=0, M=1 + .a8 + .i16 + cpx #$3456 + bne @to_fail + cpy #$5678 + bne @to_fail + ldx result_p + cpx #$0028 + bne @to_fail + ldx result_a + cpx #$cc5a + bne @to_fail + bra @next_test +@to_fail: + jml fail +@next_test: + + jml success diff --git a/roms/snes-tests/cputest/tests-full.map b/roms/snes-tests/cputest/tests-full.map new file mode 100644 index 00000000..5f5ff3c3 --- /dev/null +++ b/roms/snes-tests/cputest/tests-full.map @@ -0,0 +1,3272 @@ +Modules list: +------------- +cputest-full.o: + CODE Offs=000000 Size=004CC2 Align=00001 Fill=0000 + RODATA Offs=000000 Size=001B56 Align=00001 Fill=0000 + BSS Offs=000000 Size=000000 Align=00001 Fill=0000 + DATA Offs=000000 Size=000000 Align=00001 Fill=0000 + ZEROPAGE Offs=000000 Size=000022 Align=00001 Fill=0000 + NULL Offs=000000 Size=000000 Align=00001 Fill=0000 + HEADER Offs=000000 Size=000015 Align=00001 Fill=0000 + ROMINFO Offs=000000 Size=00000B Align=00001 Fill=0000 + VECTORS Offs=000000 Size=000020 Align=00001 Fill=0000 + BANK1 Offs=000000 Size=0074FB Align=00001 Fill=0000 + BANK2 Offs=000000 Size=0077FF Align=00001 Fill=0000 + BANK3 Offs=000000 Size=0075DC Align=00001 Fill=0000 + BANK4 Offs=000000 Size=005C62 Align=00001 Fill=0000 + TEST_DATA Offs=000000 Size=000007 Align=00001 Fill=0000 + + +Segment list: +------------- +Name Start End Size Align +---------------------------------------------------- +DATA 000000 000000 000000 00001 +NULL 000000 000000 000000 00001 +ZEROPAGE 000000 000021 000022 00001 +BSS 000200 000200 000000 00001 +CODE 008000 00CCC1 004CC2 00001 +RODATA 00CCC2 00E817 001B56 00001 +TEST_DATA 00FFA0 00FFA6 000007 00001 +HEADER 00FFC0 00FFD4 000015 00001 +ROMINFO 00FFD5 00FFDF 00000B 00001 +VECTORS 00FFE0 00FFFF 000020 00001 +BANK1 018000 01F4FA 0074FB 00001 +BANK2 028000 02F7FE 0077FF 00001 +BANK3 038000 03F5DB 0075DC 00001 +BANK4 048000 04DC61 005C62 00001 + + +Exports list by name: +--------------------- +test0000 008294 LF test0001 00830A LF +test0002 008344 LF test0003 0083A1 LF +test0004 008406 LF test0005 008463 LF +test0006 0084B4 LF test0007 008509 LF +test0008 00856E LF test0009 0085D3 LF +test000a 00862D LF test000b 008684 LF +test000c 0086E9 LF test000d 00874E LF +test000e 0087B3 LF test000f 008818 LF +test0010 00887D LF test0011 0088E0 LF +test0012 008943 LF test0013 0089A6 LF +test0014 0089FF LF test0015 008A54 LF +test0016 008AB9 LF test0017 008B1E LF +test0018 008B83 LF test0019 008BDD LF +test001a 008C37 LF test001b 008C91 LF +test001c 008CEB LF test001d 008D42 LF +test001e 008D99 LF test001f 008DD3 LF +test0020 008E0D LF test0021 008E47 LF +test0022 008E80 LF test0023 008ECF LF +test0024 008F1E LF test0025 008F79 LF +test0026 008FD4 LF test0027 00902F LF +test0028 00908A LF test0029 0090CF LF +test002a 009116 LF test002b 009161 LF +test002c 0091AE LF test002d 009205 LF +test002e 009261 LF test002f 0092AD LF +test0030 0092FB LF test0031 009344 LF +test0032 00938F LF test0033 0093E6 LF +test0034 00943D LF test0035 009498 LF +test0036 0094F8 LF test0037 00954F LF +test0038 0095AA LF test0039 00960A LF +test003a 00965F LF test003b 0096B4 LF +test003c 00970B LF test003d 009758 LF +test003e 0097A3 LF test003f 0097F0 LF +test0040 00983F LF test0041 009896 LF +test0042 0098ED LF test0043 009949 LF +test0044 009995 LF test0045 0099E1 LF +test0046 009A2F LF test0047 009A7B LF +test0048 009AC7 LF test0049 009B15 LF +test004a 009B5E LF test004b 009BA7 LF +test004c 009BF2 LF test004d 009C2B LF +test004e 009C64 LF test004f 009C9D LF +test0050 009CD7 LF test0051 009D34 LF +test0052 009D99 LF test0053 009DF6 LF +test0054 009E47 LF test0055 009E9C LF +test0056 009F01 LF test0057 009F66 LF +test0058 009FC0 LF test0059 00A017 LF +test005a 00A07C LF test005b 00A0E1 LF +test005c 00A146 LF test005d 00A1AB LF +test005e 00A210 LF test005f 00A273 LF +test0060 00A2D6 LF test0061 00A339 LF +test0062 00A392 LF test0063 00A3E7 LF +test0064 00A44C LF test0065 00A4B1 LF +test0066 00A516 LF test0067 00A570 LF +test0068 00A5CA LF test0069 00A624 LF +test006a 00A67E LF test006b 00A6D5 LF +test006c 00A72C LF test006d 00A766 LF +test006e 00A7A0 LF test006f 00A7D9 LF +test0070 00A828 LF test0071 00A877 LF +test0072 00A8D2 LF test0073 00A92D LF +test0074 00A988 LF test0075 00A9E3 LF +test0076 00AA28 LF test0077 00AA6F LF +test0078 00AABA LF test0079 00AB07 LF +test007a 00AB5E LF test007b 00ABBA LF +test007c 00AC06 LF test007d 00AC54 LF +test007e 00AC9D LF test007f 00ACE8 LF +test0080 00AD3F LF test0081 00AD96 LF +test0082 00ADF1 LF test0083 00AE51 LF +test0084 00AEA8 LF test0085 00AF03 LF +test0086 00AF63 LF test0087 00AFB8 LF +test0088 00B00D LF test0089 00B064 LF +test008a 00B0B1 LF test008b 00B0FC LF +test008c 00B149 LF test008d 00B198 LF +test008e 00B1EF LF test008f 00B246 LF +test0090 00B2A2 LF test0091 00B2EE LF +test0092 00B33A LF test0093 00B388 LF +test0094 00B3D4 LF test0095 00B420 LF +test0096 00B46E LF test0097 00B4B7 LF +test0098 00B500 LF test0099 00B54B LF +test009a 00B584 LF test009b 00B5BC LF +test009c 00B611 LF test009d 00B66B LF +test009e 00B6C4 LF test009f 00B719 LF +test00a0 00B773 LF test00a1 00B7CD LF +test00a2 00B805 LF test00a3 00B85A LF +test00a4 00B8B4 LF test00a5 00B90D LF +test00a6 00B962 LF test00a7 00B9BC LF +test00a8 00BA16 LF test00a9 00BA4E LF +test00aa 00BA99 LF test00ab 00BAE6 LF +test00ac 00BB32 LF test00ad 00BB80 LF +test00ae 00BBCD LF test00af 00BC18 LF +test00b0 00BC65 LF test00b1 00BCB4 LF +test00b2 00BD00 LF test00b3 00BD4C LF +test00b4 00BD9A LF test00b5 00BDD2 LF +test00b6 00BE1D LF test00b7 00BE6A LF +test00b8 00BEB6 LF test00b9 00BF04 LF +test00ba 00BF51 LF test00bb 00BF9C LF +test00bc 00BFE9 LF test00bd 00C038 LF +test00be 00C084 LF test00bf 00C0D0 LF +test00c0 00C11E LF test00c1 00C158 LF +test00c2 00C192 LF test00c3 00C1CB LF +test00c4 00C204 LF test00c5 00C259 LF +test00c6 00C2B3 LF test00c7 00C30C LF +test00c8 00C361 LF test00c9 00C3BB LF +test00ca 00C415 LF test00cb 00C46A LF +test00cc 00C4C4 LF test00cd 00C51D LF +test00ce 00C572 LF test00cf 00C5CC LF +test00d0 00C626 LF test00d1 00C671 LF +test00d2 00C6BE LF test00d3 00C70A LF +test00d4 00C758 LF test00d5 00C7A5 LF +test00d6 00C7F0 LF test00d7 00C83D LF +test00d8 00C88C LF test00d9 00C8D8 LF +test00da 00C924 LF test00db 00C972 LF +test00dc 00C9BD LF test00dd 00CA0A LF +test00de 00CA56 LF test00df 00CAA4 LF +test00e0 00CAF1 LF test00e1 00CB3C LF +test00e2 00CB89 LF test00e3 00CBD8 LF +test00e4 00CC24 LF test00e5 00CC70 LF +test00e6 01802E LF test00e7 01809E LF +test00e8 018109 LF test00e9 018179 LF +test00ea 0181E4 LF test00eb 018224 LF +test00ec 018296 LF test00ed 018303 LF +test00ee 018343 LF test00ef 0183B3 LF +test00f0 01841E LF test00f1 01845E LF +test00f2 0184CE LF test00f3 018539 LF +test00f4 018579 LF test00f5 0185E9 LF +test00f6 018654 LF test00f7 018694 LF +test00f8 018704 LF test00f9 01876F LF +test00fa 0187AF LF test00fb 01881F LF +test00fc 01888A LF test00fd 0188CA LF +test00fe 01893A LF test00ff 0189A5 LF +test0100 0189E5 LF test0101 018A6C LF +test0102 018AF2 LF test0103 018B79 LF +test0104 018BFF LF test0105 018C70 LF +test0106 018CA8 LF test0107 018CE0 LF +test0108 018D18 LF test0109 018D50 LF +test010a 018D88 LF test010b 018DC0 LF +test010c 018DF8 LF test010d 018E30 LF +test010e 018E68 LF test010f 018EA0 LF +test0110 018ED8 LF test0111 018F10 LF +test0112 018F48 LF test0113 018F80 LF +test0114 018FBA LF test0115 019017 LF +test0116 01907C LF test0117 0190D9 LF +test0118 01912A LF test0119 01917F LF +test011a 0191E4 LF test011b 019249 LF +test011c 0192A3 LF test011d 0192FA LF +test011e 01935F LF test011f 0193C4 LF +test0120 019429 LF test0121 01948E LF +test0122 0194F3 LF test0123 019556 LF +test0124 0195B9 LF test0125 01961C LF +test0126 019675 LF test0127 0196CA LF +test0128 01972F LF test0129 019794 LF +test012a 0197F9 LF test012b 019853 LF +test012c 0198AD LF test012d 019907 LF +test012e 019961 LF test012f 0199B8 LF +test0130 019A0F LF test0131 019A49 LF +test0132 019A9E LF test0133 019AF8 LF +test0134 019B32 LF test0135 019B87 LF +test0136 019BE1 LF test0137 019C1B LF +test0138 019C78 LF test0139 019CDD LF +test013a 019D3A LF test013b 019D8B LF +test013c 019DE0 LF test013d 019E45 LF +test013e 019EAA LF test013f 019F04 LF +test0140 019F5B LF test0141 019FC0 LF +test0142 01A025 LF test0143 01A08A LF +test0144 01A0EF LF test0145 01A154 LF +test0146 01A1B7 LF test0147 01A21A LF +test0148 01A27D LF test0149 01A2D6 LF +test014a 01A32B LF test014b 01A390 LF +test014c 01A3F5 LF test014d 01A45A LF +test014e 01A4B4 LF test014f 01A50E LF +test0150 01A568 LF test0151 01A5C2 LF +test0152 01A619 LF test0153 01A670 LF +test0154 01A6AA LF test0155 01A6FF LF +test0156 01A759 LF test0157 01A793 LF +test0158 01A7E8 LF test0159 01A842 LF +test015a 01A87B LF test015b 01A8CA LF +test015c 01A919 LF test015d 01A974 LF +test015e 01A9CF LF test015f 01AA2A LF +test0160 01AA85 LF test0161 01AACA LF +test0162 01AB11 LF test0163 01AB5C LF +test0164 01ABA9 LF test0165 01AC00 LF +test0166 01AC5C LF test0167 01ACA8 LF +test0168 01ACF6 LF test0169 01AD3F LF +test016a 01AD8A LF test016b 01ADE1 LF +test016c 01AE38 LF test016d 01AE93 LF +test016e 01AEF3 LF test016f 01AF4A LF +test0170 01AFA5 LF test0171 01B005 LF +test0172 01B05A LF test0173 01B0AF LF +test0174 01B106 LF test0175 01B153 LF +test0176 01B19E LF test0177 01B1EB LF +test0178 01B23A LF test0179 01B291 LF +test017a 01B2E8 LF test017b 01B344 LF +test017c 01B390 LF test017d 01B3DC LF +test017e 01B42A LF test017f 01B476 LF +test0180 01B4C2 LF test0181 01B510 LF +test0182 01B559 LF test0183 01B5A2 LF +test0184 01B5ED LF test0185 01B626 LF +test0186 01B671 LF test0187 01B6BE LF +test0188 01B70A LF test0189 01B758 LF +test018a 01B791 LF test018b 01B7DC LF +test018c 01B829 LF test018d 01B875 LF +test018e 01B8C3 LF test018f 01B8FC LF +test0190 01B94B LF test0191 01B99A LF +test0192 01B9F5 LF test0193 01BA50 LF +test0194 01BAAB LF test0195 01BB06 LF +test0196 01BB4B LF test0197 01BB92 LF +test0198 01BBDD LF test0199 01BC2A LF +test019a 01BC81 LF test019b 01BCDD LF +test019c 01BD29 LF test019d 01BD77 LF +test019e 01BDC0 LF test019f 01BE0B LF +test01a0 01BE62 LF test01a1 01BEB9 LF +test01a2 01BF14 LF test01a3 01BF74 LF +test01a4 01BFCB LF test01a5 01C026 LF +test01a6 01C086 LF test01a7 01C0DB LF +test01a8 01C130 LF test01a9 01C187 LF +test01aa 01C1D4 LF test01ab 01C21F LF +test01ac 01C26C LF test01ad 01C2BB LF +test01ae 01C312 LF test01af 01C369 LF +test01b0 01C3C5 LF test01b1 01C411 LF +test01b2 01C45D LF test01b3 01C4AB LF +test01b4 01C4F7 LF test01b5 01C543 LF +test01b6 01C591 LF test01b7 01C5DA LF +test01b8 01C623 LF test01b9 01C66E LF +test01ba 01C6A7 LF test01bb 01C6F2 LF +test01bc 01C73F LF test01bd 01C78B LF +test01be 01C7D9 LF test01bf 01C812 LF +test01c0 01C85D LF test01c1 01C8AA LF +test01c2 01C8F6 LF test01c3 01C944 LF +test01c4 01C97C LF test01c5 01C9D1 LF +test01c6 01CA2B LF test01c7 01CA84 LF +test01c8 01CAD9 LF test01c9 01CB33 LF +test01ca 01CB8D LF test01cb 01CBC5 LF +test01cc 01CBFD LF test01cd 01CC35 LF +test01ce 01CC8A LF test01cf 01CCE4 LF +test01d0 01CD3D LF test01d1 01CD92 LF +test01d2 01CDEC LF test01d3 01CE46 LF +test01d4 01CE7E LF test01d5 01CEB6 LF +test01d6 01CEEE LF test01d7 01CF39 LF +test01d8 01CF86 LF test01d9 01CFD2 LF +test01da 01D020 LF test01db 01D06D LF +test01dc 01D0B8 LF test01dd 01D105 LF +test01de 01D154 LF test01df 01D1A0 LF +test01e0 01D1EC LF test01e1 01D23A LF +test01e2 01D272 LF test01e3 01D2AA LF +test01e4 01D2E2 LF test01e5 01D32D LF +test01e6 01D37A LF test01e7 01D3C6 LF +test01e8 01D414 LF test01e9 01D461 LF +test01ea 01D4AC LF test01eb 01D4F9 LF +test01ec 01D548 LF test01ed 01D594 LF +test01ee 01D5E0 LF test01ef 01D62E LF +test01f0 01D666 LF test01f1 01D69E LF +test01f2 01D6D8 LF test01f3 01D735 LF +test01f4 01D79A LF test01f5 01D7F7 LF +test01f6 01D848 LF test01f7 01D89D LF +test01f8 01D902 LF test01f9 01D967 LF +test01fa 01D9C1 LF test01fb 01DA18 LF +test01fc 01DA7D LF test01fd 01DAE2 LF +test01fe 01DB47 LF test01ff 01DBAC LF +test0200 01DC11 LF test0201 01DC74 LF +test0202 01DCD7 LF test0203 01DD3A LF +test0204 01DD93 LF test0205 01DDE8 LF +test0206 01DE4D LF test0207 01DEB2 LF +test0208 01DF17 LF test0209 01DF71 LF +test020a 01DFCB LF test020b 01E025 LF +test020c 01E07F LF test020d 01E0D6 LF +test020e 01E12D LF test020f 01E167 LF +test0210 01E1A1 LF test0211 01E1DA LF +test0212 01E229 LF test0213 01E278 LF +test0214 01E2D3 LF test0215 01E32E LF +test0216 01E389 LF test0217 01E3E4 LF +test0218 01E429 LF test0219 01E470 LF +test021a 01E4BB LF test021b 01E508 LF +test021c 01E55F LF test021d 01E5BB LF +test021e 01E607 LF test021f 01E655 LF +test0220 01E69E LF test0221 01E6E9 LF +test0222 01E740 LF test0223 01E797 LF +test0224 01E7F2 LF test0225 01E852 LF +test0226 01E8A9 LF test0227 01E904 LF +test0228 01E964 LF test0229 01E9B9 LF +test022a 01EA0E LF test022b 01EA65 LF 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+test060f (cputest-full.o): +test0610 (cputest-full.o): +test0611 (cputest-full.o): +test0612 (cputest-full.o): +test0613 (cputest-full.o): +test0614 (cputest-full.o): +test0615 (cputest-full.o): +test0616 (cputest-full.o): +test0617 (cputest-full.o): +test0618 (cputest-full.o): +test0619 (cputest-full.o): +test061a (cputest-full.o): +test061b (cputest-full.o): +test061c (cputest-full.o): +test061d (cputest-full.o): +test061e (cputest-full.o): +test061f (cputest-full.o): +test0620 (cputest-full.o): +test0621 (cputest-full.o): +test0622 (cputest-full.o): +test0623 (cputest-full.o): +test0624 (cputest-full.o): +test0625 (cputest-full.o): +test0626 (cputest-full.o): +test0627 (cputest-full.o): +test0628 (cputest-full.o): +test0629 (cputest-full.o): +test062a (cputest-full.o): +test062b (cputest-full.o): +test062c (cputest-full.o): +test062d (cputest-full.o): +test062e (cputest-full.o): +test062f (cputest-full.o): +test0630 (cputest-full.o): +test0631 (cputest-full.o): +test0632 (cputest-full.o): +test0633 (cputest-full.o): +test0634 (cputest-full.o): +test0635 (cputest-full.o): +test0636 (cputest-full.o): +test0637 (cputest-full.o): +test0638 (cputest-full.o): +test0639 (cputest-full.o): +test063a (cputest-full.o): +test063b (cputest-full.o): +test063c (cputest-full.o): +test063d (cputest-full.o): +test063e (cputest-full.o): +test063f (cputest-full.o): +test0640 (cputest-full.o): +test0641 (cputest-full.o): +test0642 (cputest-full.o): +test0643 (cputest-full.o): +test0644 (cputest-full.o): +test0645 (cputest-full.o): +test0646 (cputest-full.o): +test0647 (cputest-full.o): +test0648 (cputest-full.o): +test0649 (cputest-full.o): + diff --git a/roms/snes-tests/cputest/tests-full.txt b/roms/snes-tests/cputest/tests-full.txt new file mode 100644 index 00000000..f0bc0726 --- /dev/null +++ b/roms/snes-tests/cputest/tests-full.txt @@ -0,0 +1,4905 @@ +Auto-generated by make_cpu_tests.py + +Test 0000: nop ; test PC wrapping from $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$ea + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 0001: adc #$edcb + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 0002: adc ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($7f1212)=$cb ($7f1213)=$ed + Expected output: A=$0000 X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$cb ($7f1213)=$ed +Test 0003: adc ($10,x) + Input: A=$1234 X=$0123 Y=$5678 P=$01 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$0123 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0004: adc ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$11 E=0 DBR=$7f D=$ff00 ($7f1212)=$cb ($7f1213)=$ed + Expected output: A=$0000 X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$cb ($7f1213)=$ed +Test 0005: adc $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 ($000201)=$cb ($000202)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000201)=$cb ($000202)=$ed +Test 0006: adc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000033)=$cb ($000034)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$cb ($000034)=$ed +Test 0007: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cb ($7f1235)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cb ($7f1235)=$ed +Test 0008: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0009: adc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7e ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 000a: adc $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 000b: adc ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 000c: adc ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 000d: adc ($34),y + Input: A=$1234 X=$3456 Y=$1111 P=$01 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 000e: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cb ($7f1235)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cb ($7f1235)=$ed +Test 000f: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0010: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 0011: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 0012: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1111 P=$01 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0013: adc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$01 E=0 DBR=$7f D=$ffff ($000134)=$cb ($000135)=$ed + Expected output: A=$0000 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$cb ($000135)=$ed +Test 0014: adc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$11 E=0 DBR=$7f D=$ffff ($000033)=$cb ($000034)=$ed + Expected output: A=$0000 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$cb ($000034)=$ed +Test 0015: adc [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$01 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cb ($7f0fdd)=$ed + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cb ($7f0fdd)=$ed +Test 0016: adc [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$11 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cb ($7ffeed)=$ed + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cb ($7ffeed)=$ed +Test 0017: adc [$34],y + Input: A=$1234 X=$3456 Y=$1111 P=$01 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$cb ($7f0000)=$ed + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cb ($7f0000)=$ed +Test 0018: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$01 E=0 DBR=$7e ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 0019: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$11 E=0 DBR=$7e ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 001a: adc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$01 E=0 DBR=$7e ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 001b: adc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$11 E=0 DBR=$7e ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 001c: adc $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$01 E=0 ($7f02ff)=$cb ($7f0300)=$ed + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cb ($7f0300)=$ed +Test 001d: adc $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$11 E=0 ($7f002f)=$cb ($7f0030)=$ed + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cb ($7f0030)=$ed +Test 001e: adc #$2000 + Input: A=$6789 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$8789 X=$3456 Y=$5678 P=$c0 E=0 +Test 001f: adc #$8000 + Input: A=$8000 X=$3456 Y=$5678 P=$c6 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$47 E=0 +Test 0020: adc #$e000 + Input: A=$9000 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$7001 X=$3456 Y=$5678 P=$41 E=0 +Test 0021: adc #$ed + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 +Test 0022: adc ($10,x) + Input: A=$1112 X=$ff91 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($7f1212)=$ed + Expected output: A=$1100 X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$ed +Test 0023: adc ($90,x) + Input: A=$1112 X=$1210 Y=$5678 P=$31 E=0 DBR=$7f D=$ff00 ($7f1212)=$ed + Expected output: A=$1100 X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$ed +Test 0024: adc ($EF,x) + Input: A=$1112 X=$0010 Y=$5678 P=$21 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 0025: adc ($F0,x) + Input: A=$1112 X=$0010 Y=$5678 P=$21 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 0026: adc ($F6,x) + Input: A=$1112 X=$00ee Y=$5678 P=$21 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 0027: adc ($F7,x) + Input: A=$1112 X=$00ee Y=$5678 P=$21 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$ed + Note: This tests undocumented behavior - see the cputest README file for details +Test 0028: adc $12,s + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 ($000201)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($000201)=$ed +Test 0029: adc $12,s + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 ($000201)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($000201)=$ed +Test 002a: adc $34 + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$ed +Test 002b: adc $34 + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$ed +Test 002c: adc [$34] + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$ed +Test 002d: adc [$FF] + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 002e: adc $FFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7e ($7effff)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$ed +Test 002f: adc $FFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 DBR=$7e ($7effff)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$ed +Test 0030: adc $7EFFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 ($7effff)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$ed +Test 0031: adc $7EFFFF + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 ($7effff)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$ed +Test 0032: adc ($34),y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 0033: adc ($34),y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 0034: adc ($FF),y + Input: A=$1112 X=$3456 Y=$0010 P=$21 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$ed +Test 0035: adc ($FE),y + Input: A=$1112 X=$3456 Y=$0010 P=$21 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$ed +Test 0036: adc ($34) + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$ed +Test 0037: adc ($FF) + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 0038: adc ($FE) + Input: A=$1112 X=$3456 Y=$5678 P=$21 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$ed + Expected output: A=$1100 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$ed +Test 0039: adc ($10,s),y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 003a: adc ($10,s),y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 003b: adc ($12,s),y + Input: A=$1112 X=$3456 Y=$1110 P=$21 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=1 ($7ffeec)=$ed +Test 003c: adc $02,x + Input: A=$1112 X=$0133 Y=$5678 P=$21 E=0 DBR=$7f D=$ffff ($000134)=$ed + Expected output: A=$1100 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$ed +Test 003d: adc $02,x + Input: A=$1112 X=$1232 Y=$5678 P=$31 E=0 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$ed +Test 003e: adc $02,x + Input: A=$1112 X=$0032 Y=$5678 P=$21 E=1 DBR=$7f D=$ffff ($000033)=$ed + Expected output: A=$1100 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$ed +Test 003f: adc $FF,x + Input: A=$1112 X=$0034 Y=$5678 P=$21 E=1 DBR=$7f D=$0100 ($000133)=$ed + Expected output: A=$1100 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$ed +Test 0040: adc [$34],y + Input: A=$1112 X=$3456 Y=$1100 P=$21 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$ed + Expected output: A=$1100 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$ed +Test 0041: adc [$34],y + Input: A=$1112 X=$3456 Y=$1110 P=$31 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$ed +Test 0042: adc [$FF],y + Input: A=$1112 X=$3456 Y=$0010 P=$21 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$ed + Expected output: A=$1100 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$ed +Test 0043: adc $FFFF,y + Input: A=$1112 X=$3456 Y=$0300 P=$21 E=0 DBR=$7e ($7f02ff)=$ed + Expected output: A=$1100 X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$ed +Test 0044: adc $FFFF,y + Input: A=$1112 X=$3456 Y=$1230 P=$31 E=0 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$ed +Test 0045: adc $FFFF,y + Input: A=$1112 X=$3456 Y=$1230 P=$21 E=1 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0056 Y=$0030 P=$33 E=1 ($7f002f)=$ed +Test 0046: adc $FFFF,x + Input: A=$1112 X=$0300 Y=$5678 P=$21 E=0 DBR=$7e ($7f02ff)=$ed + Expected output: A=$1100 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$ed +Test 0047: adc $FFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$31 E=0 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$ed +Test 0048: adc $FFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$21 E=1 DBR=$7e ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$ed +Test 0049: adc $7EFFFF,x + Input: A=$1112 X=$0300 Y=$5678 P=$21 E=0 ($7f02ff)=$ed + Expected output: A=$1100 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$ed +Test 004a: adc $7EFFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$31 E=0 ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$ed +Test 004b: adc $7EFFFF,x + Input: A=$1112 X=$1230 Y=$5678 P=$21 E=1 ($7f002f)=$ed + Expected output: A=$1100 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$ed +Test 004c: adc #$20 + Input: A=$1167 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1187 X=$3456 Y=$5678 P=$e0 E=0 +Test 004d: adc #$80 + Input: A=$1180 X=$3456 Y=$5678 P=$e6 E=0 + Expected output: A=$1100 X=$3456 Y=$5678 P=$67 E=0 +Test 004e: adc #$e0 + Input: A=$1190 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$1171 X=$3456 Y=$5678 P=$61 E=0 +Test 004f: and #$ef5c + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 +Test 0050: and ($10,x) + Input: A=$feff X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$5c ($7f1213)=$ef + Expected output: A=$ee5c X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$5c ($7f1213)=$ef +Test 0051: and ($10,x) + Input: A=$feff X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$0123 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0052: and ($90,x) + Input: A=$feff X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$5c ($7f1213)=$ef + Expected output: A=$ee5c X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$5c ($7f1213)=$ef +Test 0053: and $12,s + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($000201)=$5c ($000202)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($000201)=$5c ($000202)=$ef +Test 0054: and $34 + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$5c ($000034)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($000033)=$5c ($000034)=$ef +Test 0055: and [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$5c ($7f1235)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$5c ($7f1235)=$ef +Test 0056: and [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0057: and $FFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0058: and $7EFFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0059: and ($34),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 005a: and ($34),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 005b: and ($34),y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 005c: and ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$5c ($7f1235)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$5c ($7f1235)=$ef +Test 005d: and ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 005e: and ($10,s),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 005f: and ($10,s),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 0060: and ($10,s),y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0061: and $02,x + Input: A=$feff X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$5c ($000135)=$ef + Expected output: A=$ee5c X=$0133 Y=$5678 P=$80 E=0 ($000134)=$5c ($000135)=$ef +Test 0062: and $02,x + Input: A=$feff X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$5c ($000034)=$ef + Expected output: A=$ee5c X=$0032 Y=$0078 P=$90 E=0 ($000033)=$5c ($000034)=$ef +Test 0063: and [$34],y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$5c ($7f0fdd)=$ef + Expected output: A=$ee5c X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$5c ($7f0fdd)=$ef +Test 0064: and [$34],y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$5c ($7ffeed)=$ef + Expected output: A=$ee5c X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$5c ($7ffeed)=$ef +Test 0065: and [$34],y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$5c ($7f0000)=$ef + Expected output: A=$ee5c X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$5c ($7f0000)=$ef +Test 0066: and $FFFF,y + Input: A=$feff X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 0067: and $FFFF,y + Input: A=$feff X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 0068: and $FFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 0069: and $FFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 006a: and $7EFFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$5c ($7f0300)=$ef + Expected output: A=$ee5c X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$5c ($7f0300)=$ef +Test 006b: and $7EFFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$5c ($7f0030)=$ef + Expected output: A=$ee5c X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$5c ($7f0030)=$ef +Test 006c: and #$aaaa + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 006d: and #$4300 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$0200 X=$3456 Y=$5678 P=$4d E=0 +Test 006e: and #$df + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 +Test 006f: and ($10,x) + Input: A=$12fe X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$df + Expected output: A=$12de X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$df +Test 0070: and ($90,x) + Input: A=$12fe X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$df + Expected output: A=$12de X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$df +Test 0071: and ($EF,x) + Input: A=$12fe X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$df + Expected output: A=$12de X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 0072: and ($F0,x) + Input: A=$12fe X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$df + Expected output: A=$12de X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 0073: and ($F6,x) + Input: A=$12fe X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$df + Expected output: A=$12de X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 0074: and ($F7,x) + Input: A=$12fe X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$df + Expected output: A=$12de X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$df + Note: This tests undocumented behavior - see the cputest README file for details +Test 0075: and $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($000201)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$df +Test 0076: and $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 ($000201)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($000201)=$df +Test 0077: and $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$df +Test 0078: and $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($000033)=$df +Test 0079: and [$34] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$df +Test 007a: and [$FF] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 007b: and $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$df +Test 007c: and $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$df +Test 007d: and $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$df +Test 007e: and $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$df +Test 007f: and ($34),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 0080: and ($34),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 0081: and ($FF),y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$df +Test 0082: and ($FE),y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$df +Test 0083: and ($34) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$df + Expected output: A=$12de X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$df +Test 0084: and ($FF) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 0085: and ($FE) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$df + Expected output: A=$12de X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$df +Test 0086: and ($10,s),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 0087: and ($10,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 0088: and ($12,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=1 ($7ffeec)=$df +Test 0089: and $02,x + Input: A=$12fe X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$df + Expected output: A=$12de X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$df +Test 008a: and $02,x + Input: A=$12fe X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$df +Test 008b: and $02,x + Input: A=$12fe X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$df + Expected output: A=$12de X=$0032 Y=$0078 P=$b0 E=1 ($000033)=$df +Test 008c: and $FF,x + Input: A=$12fe X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$df + Expected output: A=$12de X=$0034 Y=$0078 P=$b0 E=1 ($000133)=$df +Test 008d: and [$34],y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$df + Expected output: A=$12de X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$df +Test 008e: and [$34],y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$df +Test 008f: and [$FF],y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$df + Expected output: A=$12de X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$df +Test 0090: and $FFFF,y + Input: A=$12fe X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$df + Expected output: A=$12de X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$df +Test 0091: and $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$df +Test 0092: and $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0056 Y=$0030 P=$b0 E=1 ($7f002f)=$df +Test 0093: and $FFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$df + Expected output: A=$12de X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$df +Test 0094: and $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$df +Test 0095: and $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$df +Test 0096: and $7EFFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$df + Expected output: A=$12de X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$df +Test 0097: and $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$df +Test 0098: and $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$df + Expected output: A=$12de X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$df +Test 0099: and #$aa + Input: A=$5555 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$5500 X=$3456 Y=$5678 P=$22 E=0 +Test 009a: asl a + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 009b: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 009c: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 009d: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 009e: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 009f: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 00a0: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 00a1: asl a + Input: A=$4111 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8222 X=$3456 Y=$5678 P=$cc E=0 +Test 00a2: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$22 ($000034)=$82 +Test 00a3: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$11 ($7f0000)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$22 ($7f0000)=$82 +Test 00a4: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$11 ($000135)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$22 ($000135)=$82 +Test 00a5: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$22 ($000034)=$82 +Test 00a6: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$11 ($7f0300)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$22 ($7f0300)=$82 +Test 00a7: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$11 ($7f0030)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$22 ($7f0030)=$82 +Test 00a8: asl a + Input: A=$1280 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 00a9: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 00aa: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 00ab: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 00ac: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$00 +Test 00ad: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 00ae: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 00af: asl $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 00b0: asl $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$80 + Expected output: A=$1234 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$00 +Test 00b1: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 00b2: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 00b3: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$00 +Test 00b4: asl a + Input: A=$1241 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1282 X=$3456 Y=$5678 P=$ec E=0 +Test 00b5: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$82 +Test 00b6: asl $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($000033)=$82 +Test 00b7: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$82 +Test 00b8: asl $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($7effff)=$82 +Test 00b9: asl $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$82 +Test 00ba: asl $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$82 +Test 00bb: asl $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=1 ($000033)=$82 +Test 00bc: asl $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$41 + Expected output: A=$1234 X=$0034 Y=$0078 P=$fc E=1 ($000133)=$82 +Test 00bd: asl $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$82 +Test 00be: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$82 +Test 00bf: asl $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=1 ($7f002f)=$82 +Test 00c0: bit #$1234 + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$9377 X=$3456 Y=$5678 P=$cd E=0 +Test 00c1: bit #$aaaa + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 +Test 00c2: bit #$aa + Input: A=$0056 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$0056 X=$3456 Y=$5678 P=$20 E=0 +Test 00c3: bit #$aa + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 +Test 00c4: bit $34 + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$52 + Expected output: A=$9377 X=$3456 Y=$5678 P=$4d E=0 ($000033)=$34 ($000034)=$52 +Test 00c5: bit $FFFF + Input: A=$9377 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$52 + Expected output: A=$9377 X=$3456 Y=$5678 P=$4d E=0 ($7effff)=$34 ($7f0000)=$52 +Test 00c6: bit $02,x + Input: A=$9377 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$52 + Expected output: A=$9377 X=$0133 Y=$5678 P=$4d E=0 ($000134)=$34 ($000135)=$52 +Test 00c7: bit $02,x + Input: A=$9377 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$52 + Expected output: A=$9377 X=$0032 Y=$0078 P=$5d E=0 ($000033)=$34 ($000034)=$52 +Test 00c8: bit $FFFF,x + Input: A=$9377 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$52 + Expected output: A=$9377 X=$0300 Y=$5678 P=$4d E=0 ($7f02ff)=$34 ($7f0300)=$52 +Test 00c9: bit $FFFF,x + Input: A=$9377 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$52 + Expected output: A=$9377 X=$0030 Y=$0078 P=$5d E=0 ($7f002f)=$34 ($7f0030)=$52 +Test 00ca: bit $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$82 E=0 ($000033)=$aa ($000034)=$aa +Test 00cb: bit $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$82 E=0 ($7effff)=$aa ($7f0000)=$aa +Test 00cc: bit $02,x + Input: A=$5555 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$aa ($000135)=$aa + Expected output: A=$5555 X=$0133 Y=$5678 P=$82 E=0 ($000134)=$aa ($000135)=$aa +Test 00cd: bit $02,x + Input: A=$5555 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$0032 Y=$0078 P=$92 E=0 ($000033)=$aa ($000034)=$aa +Test 00ce: bit $FFFF,x + Input: A=$5555 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$aa ($7f0300)=$aa + Expected output: A=$5555 X=$0300 Y=$5678 P=$82 E=0 ($7f02ff)=$aa ($7f0300)=$aa +Test 00cf: bit $FFFF,x + Input: A=$5555 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$aa ($7f0030)=$aa + Expected output: A=$5555 X=$0030 Y=$0078 P=$92 E=0 ($7f002f)=$aa ($7f0030)=$aa +Test 00d0: bit $34 + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$3456 Y=$5678 P=$60 E=0 ($000033)=$52 +Test 00d1: bit $34 + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$0056 Y=$0078 P=$70 E=1 ($000033)=$52 +Test 00d2: bit $FFFF + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$52 + Expected output: A=$0093 X=$3456 Y=$5678 P=$60 E=0 ($7effff)=$52 +Test 00d3: bit $FFFF + Input: A=$0093 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$52 + Expected output: A=$0093 X=$0056 Y=$0078 P=$70 E=1 ($7effff)=$52 +Test 00d4: bit $02,x + Input: A=$0093 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$52 + Expected output: A=$0093 X=$0133 Y=$5678 P=$60 E=0 ($000134)=$52 +Test 00d5: bit $02,x + Input: A=$0093 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$0032 Y=$0078 P=$70 E=0 ($000033)=$52 +Test 00d6: bit $02,x + Input: A=$0093 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$52 + Expected output: A=$0093 X=$0032 Y=$0078 P=$70 E=1 ($000033)=$52 +Test 00d7: bit $FF,x + Input: A=$0093 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$52 + Expected output: A=$0093 X=$0034 Y=$0078 P=$70 E=1 ($000133)=$52 +Test 00d8: bit $FFFF,x + Input: A=$0093 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$52 + Expected output: A=$0093 X=$0300 Y=$5678 P=$60 E=0 ($7f02ff)=$52 +Test 00d9: bit $FFFF,x + Input: A=$0093 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$52 + Expected output: A=$0093 X=$0030 Y=$0078 P=$70 E=0 ($7f002f)=$52 +Test 00da: bit $FFFF,x + Input: A=$0093 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$52 + Expected output: A=$0093 X=$0030 Y=$0078 P=$70 E=1 ($7f002f)=$52 +Test 00db: bit $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$a2 E=0 ($000033)=$aa +Test 00dc: bit $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$b2 E=1 ($000033)=$aa +Test 00dd: bit $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$a2 E=0 ($7effff)=$aa +Test 00de: bit $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$b2 E=1 ($7effff)=$aa +Test 00df: bit $02,x + Input: A=$0055 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$aa + Expected output: A=$0055 X=$0133 Y=$5678 P=$a2 E=0 ($000134)=$aa +Test 00e0: bit $02,x + Input: A=$0055 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0032 Y=$0078 P=$b2 E=0 ($000033)=$aa +Test 00e1: bit $02,x + Input: A=$0055 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0032 Y=$0078 P=$b2 E=1 ($000033)=$aa +Test 00e2: bit $FF,x + Input: A=$0055 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$aa + Expected output: A=$0055 X=$0034 Y=$0078 P=$b2 E=1 ($000133)=$aa +Test 00e3: bit $FFFF,x + Input: A=$0055 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$aa + Expected output: A=$0055 X=$0300 Y=$5678 P=$a2 E=0 ($7f02ff)=$aa +Test 00e4: bit $FFFF,x + Input: A=$0055 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$aa + Expected output: A=$0055 X=$0030 Y=$0078 P=$b2 E=0 ($7f002f)=$aa +Test 00e5: bit $FFFF,x + Input: A=$0055 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$aa + Expected output: A=$0055 X=$0030 Y=$0078 P=$b2 E=1 ($7f002f)=$aa +Test 00e6: bra +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$80 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00e7: bra -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$80 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00e8: bcc +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$90 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00e9: bcc -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$90 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00ea: bcc @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$01 E=0 + Additional initialization or checks are performed - see assembly +Test 00eb: bcs +127 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 ($7effc0)=$b0 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 + Additional initialization or checks are performed - see assembly +Test 00ec: bcs -128 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 ($7f0040)=$b0 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 + Additional initialization or checks are performed - see assembly +Test 00ed: bcs @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00ee: bne +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$d0 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00ef: bne -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$d0 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00f0: bne @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00f1: beq +127 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effc0)=$f0 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00f2: beq -128 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7f0040)=$f0 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Additional initialization or checks are performed - see assembly +Test 00f3: beq @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00f4: bpl +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$10 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00f5: bpl -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$10 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00f6: bpl @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00f7: bmi +127 + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 ($7effc0)=$30 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00f8: bmi -128 + Input: A=$1234 X=$3456 Y=$5678 P=$80 E=0 ($7f0040)=$30 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 + Additional initialization or checks are performed - see assembly +Test 00f9: bmi @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00fa: bvc +127 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effc0)=$50 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00fb: bvc -128 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f0040)=$50 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 00fc: bvc @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00fd: bvs +127 + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 ($7effc0)=$70 ($7effc1)=$7f ($7effc2)=$db ($7f0041)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00fe: bvs -128 + Input: A=$1234 X=$3456 Y=$5678 P=$40 E=0 ($7f0040)=$70 ($7f0041)=$80 ($7f0042)=$db ($7effc2)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$40 E=0 + Additional initialization or checks are performed - see assembly +Test 00ff: bvs @not_ok + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 0100: brk + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=0 ($7e8000)=$00 ($7e8001)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$07 E=0 S=01eb ($0001ef)=$7e ($0001ed)=$02 ($0001ee)=$80 ($0001ec)=$0b + Additional initialization or checks are performed - see assembly +Test 0101: brk + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=1 S=$0100 ($7e8000)=$00 ($7e8001)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$37 E=1 S=01fd ($0001ff)=$02 ($000100)=$80 ($0001fe)=$3b + Additional initialization or checks are performed - see assembly +Test 0102: cop #$DB + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=0 ($7e8000)=$02 ($7e8001)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$07 E=0 S=01eb ($0001ef)=$7e ($0001ed)=$02 ($0001ee)=$80 ($0001ec)=$0b + Additional initialization or checks are performed - see assembly +Test 0103: cop #$DB + Input: A=$1234 X=$3456 Y=$5678 P=$0b E=1 S=$0100 ($7e8000)=$02 ($7e8001)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$37 E=1 S=01fd ($0001ff)=$02 ($000100)=$80 ($0001fe)=$3b + Additional initialization or checks are performed - see assembly +Test 0104: BRL +$7FFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7ef000)=$82 ($7ef001)=$ff ($7ef002)=$7f ($7ef003)=$db ($7f7002)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 0105: clc + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fe E=0 +Test 0106: clc + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 0107: cld + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$f7 E=0 +Test 0108: cld + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 0109: cli + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fb E=0 +Test 010a: cli + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 010b: clv + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$bf E=0 +Test 010c: clv + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 010d: sec + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$01 E=0 +Test 010e: sec + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 010f: sed + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$08 E=0 +Test 0110: sed + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 0111: sei + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$04 E=0 +Test 0112: sei + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 0113: cmp #$abcd + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 +Test 0114: cmp ($10,x) + Input: A=$abcd X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcd X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 0115: cmp ($10,x) + Input: A=$abcd X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$0123 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0116: cmp ($90,x) + Input: A=$abcd X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcd X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 0117: cmp $12,s + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 ($000201)=$cd ($000202)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($000201)=$cd ($000202)=$ab +Test 0118: cmp $34 + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 0119: cmp [$34] + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 011a: cmp [$34] + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 011b: cmp $FFFF + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 011c: cmp $7EFFFF + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 011d: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 011e: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 011f: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0120: cmp ($34) + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 0121: cmp ($34) + Input: A=$abcd X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0122: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 0123: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 0124: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0125: cmp $02,x + Input: A=$abcd X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$cd ($000135)=$ab + Expected output: A=$abcd X=$0133 Y=$5678 P=$03 E=0 ($000134)=$cd ($000135)=$ab +Test 0126: cmp $02,x + Input: A=$abcd X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcd X=$0032 Y=$0078 P=$13 E=0 ($000033)=$cd ($000034)=$ab +Test 0127: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcd X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 0128: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcd X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 0129: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcd X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 012a: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 012b: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 012c: cmp $FFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 012d: cmp $FFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 012e: cmp $7EFFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcd X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 012f: cmp $7EFFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcd X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 0130: cpx #$abcd + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 +Test 0131: cpx $34 + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 0132: cpx $FFFF + Input: A=$1234 X=$abcd Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$abcd Y=$5678 P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0133: cpy #$abcd + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 +Test 0134: cpy $34 + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 ($000033)=$cd ($000034)=$ab +Test 0135: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcd P=$00 E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$3456 Y=$abcd P=$03 E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0136: cmp #$abcd + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 +Test 0137: cmp ($10,x) + Input: A=$abcc X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcc X=$ff91 Y=$5678 P=$cc E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 0138: cmp ($10,x) + Input: A=$abcc X=$0123 Y=$5678 P=$cf E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$0123 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0139: cmp ($90,x) + Input: A=$abcc X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$cd ($7f1213)=$ab + Expected output: A=$abcc X=$0010 Y=$0078 P=$dc E=0 ($7f1212)=$cd ($7f1213)=$ab +Test 013a: cmp $12,s + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 ($000201)=$cd ($000202)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($000201)=$cd ($000202)=$ab +Test 013b: cmp $34 + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 013c: cmp [$34] + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 013d: cmp [$34] + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 013e: cmp $FFFF + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 013f: cmp $7EFFFF + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0140: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 0141: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 0142: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1111 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$1111 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0143: cmp ($34) + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd ($7f1235)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7f1234)=$cd ($7f1235)=$ab +Test 0144: cmp ($34) + Input: A=$abcc X=$3456 Y=$5678 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0145: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 0146: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 0147: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1111 P=$cf E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$1111 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0148: cmp $02,x + Input: A=$abcc X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$cd ($000135)=$ab + Expected output: A=$abcc X=$0133 Y=$5678 P=$cc E=0 ($000134)=$cd ($000135)=$ab +Test 0149: cmp $02,x + Input: A=$abcc X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$abcc X=$0032 Y=$0078 P=$dc E=0 ($000033)=$cd ($000034)=$ab +Test 014a: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd ($7f0fdd)=$ab + Expected output: A=$abcc X=$3456 Y=$1100 P=$cc E=0 ($7f0fdc)=$cd ($7f0fdd)=$ab +Test 014b: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd ($7ffeed)=$ab + Expected output: A=$abcc X=$0056 Y=$0010 P=$dc E=0 ($7ffeec)=$cd ($7ffeed)=$ab +Test 014c: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1111 P=$cf E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$abcc X=$3456 Y=$1111 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 014d: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$3456 Y=$0300 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 014e: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0056 Y=$0030 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 014f: cmp $FFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 0150: cmp $FFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 0151: cmp $7EFFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$cd ($7f0300)=$ab + Expected output: A=$abcc X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$cd ($7f0300)=$ab +Test 0152: cmp $7EFFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$cd ($7f0030)=$ab + Expected output: A=$abcc X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$cd ($7f0030)=$ab +Test 0153: cpx #$abcd + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 +Test 0154: cpx $34 + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 0155: cpx $FFFF + Input: A=$1234 X=$abcc Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$abcc Y=$5678 P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0156: cpy #$abcd + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 +Test 0157: cpy $34 + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 DBR=$7f D=$ffff ($000033)=$cd ($000034)=$ab + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 ($000033)=$cd ($000034)=$ab +Test 0158: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcc P=$cf E=0 DBR=$7e ($7effff)=$cd ($7f0000)=$ab + Expected output: A=$1234 X=$3456 Y=$abcc P=$cc E=0 ($7effff)=$cd ($7f0000)=$ab +Test 0159: cmp #$cd + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 +Test 015a: cmp ($10,x) + Input: A=$abcd X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$cd + Expected output: A=$abcd X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$cd +Test 015b: cmp ($90,x) + Input: A=$abcd X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$cd + Expected output: A=$abcd X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$cd +Test 015c: cmp ($EF,x) + Input: A=$abcd X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 015d: cmp ($F0,x) + Input: A=$abcd X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 015e: cmp ($F6,x) + Input: A=$abcd X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 015f: cmp ($F7,x) + Input: A=$abcd X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$cd + Note: This tests undocumented behavior - see the cputest README file for details +Test 0160: cmp $12,s + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 ($000201)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($000201)=$cd +Test 0161: cmp $12,s + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 ($000201)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($000201)=$cd +Test 0162: cmp $34 + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($000033)=$cd +Test 0163: cmp $34 + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($000033)=$cd +Test 0164: cmp [$34] + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$cd +Test 0165: cmp [$FF] + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 0166: cmp $FFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$cd +Test 0167: cmp $FFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$cd +Test 0168: cmp $7EFFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$cd +Test 0169: cmp $7EFFFF + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$cd +Test 016a: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 016b: cmp ($34),y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 016c: cmp ($FF),y + Input: A=$abcd X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$cd +Test 016d: cmp ($FE),y + Input: A=$abcd X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$cd +Test 016e: cmp ($34) + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$cd +Test 016f: cmp ($FF) + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 0170: cmp ($FE) + Input: A=$abcd X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$cd + Expected output: A=$abcd X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$cd +Test 0171: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 0172: cmp ($10,s),y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 0173: cmp ($12,s),y + Input: A=$abcd X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=1 ($7ffeec)=$cd +Test 0174: cmp $02,x + Input: A=$abcd X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$cd + Expected output: A=$abcd X=$0133 Y=$5678 P=$23 E=0 ($000134)=$cd +Test 0175: cmp $02,x + Input: A=$abcd X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$0032 Y=$0078 P=$33 E=0 ($000033)=$cd +Test 0176: cmp $02,x + Input: A=$abcd X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcd X=$0032 Y=$0078 P=$33 E=1 ($000033)=$cd +Test 0177: cmp $FF,x + Input: A=$abcd X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$cd + Expected output: A=$abcd X=$0034 Y=$0078 P=$33 E=1 ($000133)=$cd +Test 0178: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd + Expected output: A=$abcd X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$cd +Test 0179: cmp [$34],y + Input: A=$abcd X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$cd +Test 017a: cmp [$FF],y + Input: A=$abcd X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$cd + Expected output: A=$abcd X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$cd +Test 017b: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcd X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$cd +Test 017c: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$cd +Test 017d: cmp $FFFF,y + Input: A=$abcd X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0056 Y=$0030 P=$33 E=1 ($7f002f)=$cd +Test 017e: cmp $FFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcd X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$cd +Test 017f: cmp $FFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$cd +Test 0180: cmp $FFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$cd +Test 0181: cmp $7EFFFF,x + Input: A=$abcd X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$cd + Expected output: A=$abcd X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$cd +Test 0182: cmp $7EFFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$cd +Test 0183: cmp $7EFFFF,x + Input: A=$abcd X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$cd + Expected output: A=$abcd X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$cd +Test 0184: cpx #$cd + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 +Test 0185: cpx $34 + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 ($000033)=$cd +Test 0186: cpx $34 + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$33 E=1 ($000033)=$cd +Test 0187: cpx $FFFF + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$13 E=0 ($7effff)=$cd +Test 0188: cpx $FFFF + Input: A=$1234 X=$abcd Y=$5678 P=$10 E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cd Y=$0078 P=$33 E=1 ($7effff)=$cd +Test 0189: cpy #$cd + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 +Test 018a: cpy $34 + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 ($000033)=$cd +Test 018b: cpy $34 + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$33 E=1 ($000033)=$cd +Test 018c: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$13 E=0 ($7effff)=$cd +Test 018d: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcd P=$10 E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cd P=$33 E=1 ($7effff)=$cd +Test 018e: cmp #$cd + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 +Test 018f: cmp ($10,x) + Input: A=$abcc X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$cd + Expected output: A=$abcc X=$ff91 Y=$5678 P=$ec E=0 ($7f1212)=$cd +Test 0190: cmp ($90,x) + Input: A=$abcc X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$cd + Expected output: A=$abcc X=$0010 Y=$0078 P=$fc E=0 ($7f1212)=$cd +Test 0191: cmp ($EF,x) + Input: A=$abcc X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$0010 Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 0192: cmp ($F0,x) + Input: A=$abcc X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$0010 Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 0193: cmp ($F6,x) + Input: A=$abcc X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$00ee Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 0194: cmp ($F7,x) + Input: A=$abcc X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$00ee Y=$0078 P=$fc E=1 ($7f1234)=$cd + Note: This tests undocumented behavior - see the cputest README file for details +Test 0195: cmp $12,s + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 ($000201)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($000201)=$cd +Test 0196: cmp $12,s + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 ($000201)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($000201)=$cd +Test 0197: cmp $34 + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($000033)=$cd +Test 0198: cmp $34 + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($000033)=$cd +Test 0199: cmp [$34] + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7f1234)=$cd +Test 019a: cmp [$FF] + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 019b: cmp $FFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$cd +Test 019c: cmp $FFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($7effff)=$cd +Test 019d: cmp $7EFFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$cd +Test 019e: cmp $7EFFFF + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 ($7effff)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($7effff)=$cd +Test 019f: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 01a0: cmp ($34),y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 01a1: cmp ($FF),y + Input: A=$abcc X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=1 ($7f1244)=$cd +Test 01a2: cmp ($FE),y + Input: A=$abcc X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=1 ($7f1244)=$cd +Test 01a3: cmp ($34) + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$3456 Y=$5678 P=$ec E=0 ($7f1234)=$cd +Test 01a4: cmp ($FF) + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 01a5: cmp ($FE) + Input: A=$abcc X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$cd + Expected output: A=$abcc X=$0056 Y=$0078 P=$fc E=1 ($7f1234)=$cd +Test 01a6: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 01a7: cmp ($10,s),y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 01a8: cmp ($12,s),y + Input: A=$abcc X=$3456 Y=$1110 P=$ef E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=1 ($7ffeec)=$cd +Test 01a9: cmp $02,x + Input: A=$abcc X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$cd + Expected output: A=$abcc X=$0133 Y=$5678 P=$ec E=0 ($000134)=$cd +Test 01aa: cmp $02,x + Input: A=$abcc X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$0032 Y=$0078 P=$fc E=0 ($000033)=$cd +Test 01ab: cmp $02,x + Input: A=$abcc X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$abcc X=$0032 Y=$0078 P=$fc E=1 ($000033)=$cd +Test 01ac: cmp $FF,x + Input: A=$abcc X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$cd + Expected output: A=$abcc X=$0034 Y=$0078 P=$fc E=1 ($000133)=$cd +Test 01ad: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$cd + Expected output: A=$abcc X=$3456 Y=$1100 P=$ec E=0 ($7f0fdc)=$cd +Test 01ae: cmp [$34],y + Input: A=$abcc X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=0 ($7ffeec)=$cd +Test 01af: cmp [$FF],y + Input: A=$abcc X=$3456 Y=$0010 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$cd + Expected output: A=$abcc X=$0056 Y=$0010 P=$fc E=1 ($7f1244)=$cd +Test 01b0: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcc X=$3456 Y=$0300 P=$ec E=0 ($7f02ff)=$cd +Test 01b1: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0056 Y=$0030 P=$fc E=0 ($7f002f)=$cd +Test 01b2: cmp $FFFF,y + Input: A=$abcc X=$3456 Y=$1230 P=$ef E=1 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0056 Y=$0030 P=$fc E=1 ($7f002f)=$cd +Test 01b3: cmp $FFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$cd + Expected output: A=$abcc X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$cd +Test 01b4: cmp $FFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$cd +Test 01b5: cmp $FFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=1 ($7f002f)=$cd +Test 01b6: cmp $7EFFFF,x + Input: A=$abcc X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$cd + Expected output: A=$abcc X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$cd +Test 01b7: cmp $7EFFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$cd +Test 01b8: cmp $7EFFFF,x + Input: A=$abcc X=$1230 Y=$5678 P=$ef E=1 ($7f002f)=$cd + Expected output: A=$abcc X=$0030 Y=$0078 P=$fc E=1 ($7f002f)=$cd +Test 01b9: cpx #$cd + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 +Test 01ba: cpx $34 + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 ($000033)=$cd +Test 01bb: cpx $34 + Input: A=$1234 X=$abcc Y=$5678 P=$df E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$fc E=1 ($000033)=$cd +Test 01bc: cpx $FFFF + Input: A=$1234 X=$abcc Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$dc E=0 ($7effff)=$cd +Test 01bd: cpx $FFFF + Input: A=$1234 X=$abcc Y=$5678 P=$df E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$00cc Y=$0078 P=$fc E=1 ($7effff)=$cd +Test 01be: cpy #$cd + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 +Test 01bf: cpy $34 + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 ($000033)=$cd +Test 01c0: cpy $34 + Input: A=$1234 X=$3456 Y=$abcc P=$df E=1 DBR=$7f D=$ffff ($000033)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$fc E=1 ($000033)=$cd +Test 01c1: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcc P=$df E=0 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$dc E=0 ($7effff)=$cd +Test 01c2: cpy $FFFF + Input: A=$1234 X=$3456 Y=$abcc P=$df E=1 DBR=$7e ($7effff)=$cd + Expected output: A=$1234 X=$0056 Y=$00cc P=$fc E=1 ($7effff)=$cd +Test 01c3: dec a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 01c4: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$00 ($000034)=$00 +Test 01c5: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 01c6: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$02 E=0 ($000134)=$00 ($000135)=$00 +Test 01c7: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$12 E=0 ($000033)=$00 ($000034)=$00 +Test 01c8: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 01c9: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 01ca: dex + Input: A=$1234 X=$0001 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 +Test 01cb: dey + Input: A=$1234 X=$3456 Y=$0001 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 +Test 01cc: dec a + Input: A=$0000 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$ffff X=$3456 Y=$5678 P=$cd E=0 +Test 01cd: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$ff ($000034)=$ff +Test 01ce: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$ff ($7f0000)=$ff +Test 01cf: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cd E=0 ($000134)=$ff ($000135)=$ff +Test 01d0: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dd E=0 ($000033)=$ff ($000034)=$ff +Test 01d1: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cd E=0 ($7f02ff)=$ff ($7f0300)=$ff +Test 01d2: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dd E=0 ($7f002f)=$ff ($7f0030)=$ff +Test 01d3: dex + Input: A=$1234 X=$0000 Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$ffff Y=$5678 P=$cd E=0 +Test 01d4: dey + Input: A=$1234 X=$3456 Y=$0000 P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$ffff P=$cd E=0 +Test 01d5: dec a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 +Test 01d6: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$00 +Test 01d7: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 ($000033)=$00 +Test 01d8: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$00 +Test 01d9: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 ($7effff)=$00 +Test 01da: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$22 E=0 ($000134)=$00 +Test 01db: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=0 ($000033)=$00 +Test 01dc: dec $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=1 ($000033)=$00 +Test 01dd: dec $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$01 + Expected output: A=$1234 X=$0034 Y=$0078 P=$32 E=1 ($000133)=$00 +Test 01de: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$00 +Test 01df: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=0 ($7f002f)=$00 +Test 01e0: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=1 ($7f002f)=$00 +Test 01e1: dex + Input: A=$1234 X=$0001 Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 +Test 01e2: dey + Input: A=$1234 X=$3456 Y=$0001 P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 +Test 01e3: dec a + Input: A=$1200 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$12ff X=$3456 Y=$5678 P=$ed E=0 +Test 01e4: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$ff +Test 01e5: dec $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fd E=1 ($000033)=$ff +Test 01e6: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$ff +Test 01e7: dec $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fd E=1 ($7effff)=$ff +Test 01e8: dec $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ed E=0 ($000134)=$ff +Test 01e9: dec $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=0 ($000033)=$ff +Test 01ea: dec $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=1 ($000033)=$ff +Test 01eb: dec $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$00 + Expected output: A=$1234 X=$0034 Y=$0078 P=$fd E=1 ($000133)=$ff +Test 01ec: dec $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ed E=0 ($7f02ff)=$ff +Test 01ed: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=0 ($7f002f)=$ff +Test 01ee: dec $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=1 ($7f002f)=$ff +Test 01ef: dex + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$00ff Y=$0078 P=$dd E=0 +Test 01f0: dey + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$00ff P=$dd E=0 +Test 01f1: eor #$6f8c + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 +Test 01f2: eor ($10,x) + Input: A=$feff X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$8c ($7f1213)=$6f + Expected output: A=$9173 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$8c ($7f1213)=$6f +Test 01f3: eor ($10,x) + Input: A=$feff X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$0123 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 01f4: eor ($90,x) + Input: A=$feff X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$8c ($7f1213)=$6f + Expected output: A=$9173 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$8c ($7f1213)=$6f +Test 01f5: eor $12,s + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($000201)=$8c ($000202)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$8c ($000202)=$6f +Test 01f6: eor $34 + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$8c ($000034)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$8c ($000034)=$6f +Test 01f7: eor [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8c ($7f1235)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$8c ($7f1235)=$6f +Test 01f8: eor [$34] + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 01f9: eor $FFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 01fa: eor $7EFFFF + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 01fb: eor ($34),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 01fc: eor ($34),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 01fd: eor ($34),y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 01fe: eor ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8c ($7f1235)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$8c ($7f1235)=$6f +Test 01ff: eor ($34) + Input: A=$feff X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 0200: eor ($10,s),y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 0201: eor ($10,s),y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 0202: eor ($10,s),y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 0203: eor $02,x + Input: A=$feff X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$8c ($000135)=$6f + Expected output: A=$9173 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$8c ($000135)=$6f +Test 0204: eor $02,x + Input: A=$feff X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$8c ($000034)=$6f + Expected output: A=$9173 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$8c ($000034)=$6f +Test 0205: eor [$34],y + Input: A=$feff X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8c ($7f0fdd)=$6f + Expected output: A=$9173 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$8c ($7f0fdd)=$6f +Test 0206: eor [$34],y + Input: A=$feff X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8c ($7ffeed)=$6f + Expected output: A=$9173 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$8c ($7ffeed)=$6f +Test 0207: eor [$34],y + Input: A=$feff X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$8c ($7f0000)=$6f + Expected output: A=$9173 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$8c ($7f0000)=$6f +Test 0208: eor $FFFF,y + Input: A=$feff X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 0209: eor $FFFF,y + Input: A=$feff X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 020a: eor $FFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 020b: eor $FFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 020c: eor $7EFFFF,x + Input: A=$feff X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$8c ($7f0300)=$6f + Expected output: A=$9173 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$8c ($7f0300)=$6f +Test 020d: eor $7EFFFF,x + Input: A=$feff X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$8c ($7f0030)=$6f + Expected output: A=$9173 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$8c ($7f0030)=$6f +Test 020e: eor #$aaaa + Input: A=$aaaa X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 020f: eor #$4334 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$5100 X=$3456 Y=$5678 P=$4d E=0 +Test 0210: eor #$6f + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 +Test 0211: eor ($10,x) + Input: A=$12fe X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$6f + Expected output: A=$1291 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$6f +Test 0212: eor ($90,x) + Input: A=$12fe X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$6f + Expected output: A=$1291 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$6f +Test 0213: eor ($EF,x) + Input: A=$12fe X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 0214: eor ($F0,x) + Input: A=$12fe X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 0215: eor ($F6,x) + Input: A=$12fe X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 0216: eor ($F7,x) + Input: A=$12fe X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$6f + Note: This tests undocumented behavior - see the cputest README file for details +Test 0217: eor $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($000201)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$6f +Test 0218: eor $12,s + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 ($000201)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($000201)=$6f +Test 0219: eor $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$6f +Test 021a: eor $34 + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($000033)=$6f +Test 021b: eor [$34] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$6f +Test 021c: eor [$FF] + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 021d: eor $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$6f +Test 021e: eor $FFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$6f +Test 021f: eor $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$6f +Test 0220: eor $7EFFFF + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$6f +Test 0221: eor ($34),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0222: eor ($34),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 0223: eor ($FF),y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$6f +Test 0224: eor ($FE),y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$6f +Test 0225: eor ($34) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$6f +Test 0226: eor ($FF) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 0227: eor ($FE) + Input: A=$12fe X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$6f + Expected output: A=$1291 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$6f +Test 0228: eor ($10,s),y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0229: eor ($10,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 022a: eor ($12,s),y + Input: A=$12fe X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=1 ($7ffeec)=$6f +Test 022b: eor $02,x + Input: A=$12fe X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$6f + Expected output: A=$1291 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$6f +Test 022c: eor $02,x + Input: A=$12fe X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$6f +Test 022d: eor $02,x + Input: A=$12fe X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$6f + Expected output: A=$1291 X=$0032 Y=$0078 P=$b0 E=1 ($000033)=$6f +Test 022e: eor $FF,x + Input: A=$12fe X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$6f + Expected output: A=$1291 X=$0034 Y=$0078 P=$b0 E=1 ($000133)=$6f +Test 022f: eor [$34],y + Input: A=$12fe X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$6f + Expected output: A=$1291 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$6f +Test 0230: eor [$34],y + Input: A=$12fe X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$6f +Test 0231: eor [$FF],y + Input: A=$12fe X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$6f + Expected output: A=$1291 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$6f +Test 0232: eor $FFFF,y + Input: A=$12fe X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$6f + Expected output: A=$1291 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$6f +Test 0233: eor $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$6f +Test 0234: eor $FFFF,y + Input: A=$12fe X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0056 Y=$0030 P=$b0 E=1 ($7f002f)=$6f +Test 0235: eor $FFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$6f + Expected output: A=$1291 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$6f +Test 0236: eor $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$6f +Test 0237: eor $FFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$6f +Test 0238: eor $7EFFFF,x + Input: A=$12fe X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$6f + Expected output: A=$1291 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$6f +Test 0239: eor $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$6f +Test 023a: eor $7EFFFF,x + Input: A=$12fe X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$6f + Expected output: A=$1291 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$6f +Test 023b: eor #$aa + Input: A=$aaaa X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$22 E=0 +Test 023c: inc a + Input: A=$ffff X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 023d: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$00 ($000034)=$00 +Test 023e: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$ff ($7f0000)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 023f: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$ff ($000135)=$ff + Expected output: A=$1234 X=$0133 Y=$5678 P=$02 E=0 ($000134)=$00 ($000135)=$00 +Test 0240: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$ff + Expected output: A=$1234 X=$0032 Y=$0078 P=$12 E=0 ($000033)=$00 ($000034)=$00 +Test 0241: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$ff ($7f0300)=$ff + Expected output: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0242: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$ff ($7f0030)=$ff + Expected output: A=$1234 X=$0030 Y=$0078 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0243: inx + Input: A=$1234 X=$ffff Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 +Test 0244: iny + Input: A=$1234 X=$3456 Y=$ffff P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 +Test 0245: inc a + Input: A=$7fff X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cd E=0 +Test 0246: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$00 ($000034)=$80 +Test 0247: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$ff ($7f0000)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0248: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$ff ($000135)=$7f + Expected output: A=$1234 X=$0133 Y=$5678 P=$cd E=0 ($000134)=$00 ($000135)=$80 +Test 0249: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$ff ($000034)=$7f + Expected output: A=$1234 X=$0032 Y=$0078 P=$dd E=0 ($000033)=$00 ($000034)=$80 +Test 024a: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$ff ($7f0300)=$7f + Expected output: A=$1234 X=$0300 Y=$5678 P=$cd E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 024b: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$ff ($7f0030)=$7f + Expected output: A=$1234 X=$0030 Y=$0078 P=$dd E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 024c: inx + Input: A=$1234 X=$7fff Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cd E=0 +Test 024d: iny + Input: A=$1234 X=$3456 Y=$7fff P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cd E=0 +Test 024e: inc a + Input: A=$12ff X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 +Test 024f: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$00 +Test 0250: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 ($000033)=$00 +Test 0251: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$00 +Test 0252: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$ff + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 ($7effff)=$00 +Test 0253: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$ff + Expected output: A=$1234 X=$0133 Y=$5678 P=$22 E=0 ($000134)=$00 +Test 0254: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=0 ($000033)=$00 +Test 0255: inc $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$ff + Expected output: A=$1234 X=$0032 Y=$0078 P=$32 E=1 ($000033)=$00 +Test 0256: inc $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$ff + Expected output: A=$1234 X=$0034 Y=$0078 P=$32 E=1 ($000133)=$00 +Test 0257: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$ff + Expected output: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$00 +Test 0258: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$ff + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=0 ($7f002f)=$00 +Test 0259: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$ff + Expected output: A=$1234 X=$0030 Y=$0078 P=$32 E=1 ($7f002f)=$00 +Test 025a: inx + Input: A=$1234 X=$00ff Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 +Test 025b: iny + Input: A=$1234 X=$3456 Y=$00ff P=$10 E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 +Test 025c: inc a + Input: A=$127f X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1280 X=$3456 Y=$5678 P=$ed E=0 +Test 025d: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$80 +Test 025e: inc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$0056 Y=$0078 P=$fd E=1 ($000033)=$80 +Test 025f: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$80 +Test 0260: inc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$7f + Expected output: A=$1234 X=$0056 Y=$0078 P=$fd E=1 ($7effff)=$80 +Test 0261: inc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$7f + Expected output: A=$1234 X=$0133 Y=$5678 P=$ed E=0 ($000134)=$80 +Test 0262: inc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=0 ($000033)=$80 +Test 0263: inc $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$7f + Expected output: A=$1234 X=$0032 Y=$0078 P=$fd E=1 ($000033)=$80 +Test 0264: inc $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$7f + Expected output: A=$1234 X=$0034 Y=$0078 P=$fd E=1 ($000133)=$80 +Test 0265: inc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$7f + Expected output: A=$1234 X=$0300 Y=$5678 P=$ed E=0 ($7f02ff)=$80 +Test 0266: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$7f + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=0 ($7f002f)=$80 +Test 0267: inc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$7f + Expected output: A=$1234 X=$0030 Y=$0078 P=$fd E=1 ($7f002f)=$80 +Test 0268: inx + Input: A=$1234 X=$007f Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0080 Y=$0078 P=$dd E=0 +Test 0269: iny + Input: A=$1234 X=$3456 Y=$007f P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0080 P=$dd E=0 +Test 026a: jmp $8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$4c ($7e7001)=$00 ($7e7002)=$80 ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 026b: jml $7e8000 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 + Additional initialization or checks are performed - see assembly +Test 026c: jmp ($FFA2) + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$6c ($7e7001)=$a2 ($7e7002)=$ff ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 026d: jml [$FFA4] + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 026e: jmp ($F000,x) + Input: A=$1234 X=$6000 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$7c ($7e7001)=$00 ($7e7002)=$f0 ($7e7003)=$db ($7e5000)=$00 ($7e5001)=$80 + Expected output: A=$1234 X=$6000 Y=$5678 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 026f: jmp ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$10 E=0 DBR=$7f ($7e7000)=$7c ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$10 E=0 + Additional initialization or checks are performed - see assembly +Test 0270: jmp ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$00 E=1 DBR=$7f ($7e7000)=$7c ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$30 E=1 + Additional initialization or checks are performed - see assembly +Test 0271: jsr $8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$20 ($7e7001)=$00 ($7e7002)=$80 ($7e7003)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 0272: jsr $8000 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 ($7e7000)=$20 ($7e7001)=$00 ($7e7002)=$80 ($7e7003)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fe ($0001ff)=$02 ($000100)=$70 + Additional initialization or checks are performed - see assembly +Test 0273: jsl $FE8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7f7000)=$22 ($7f7001)=$00 ($7f7002)=$80 ($7f7003)=$7e ($7f7004)=$db + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ec ($0001ed)=$03 ($0001ee)=$70 ($0001ef)=$7f + Additional initialization or checks are performed - see assembly +Test 0274: jsl $FE8000 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 ($7f7000)=$22 ($7f7001)=$00 ($7f7002)=$80 ($7f7003)=$7e ($7f7004)=$db + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fd ($0000fe)=$03 ($0000ff)=$70 ($000100)=$7f + Additional initialization or checks are performed - see assembly +Test 0275: jsr ($F000,x) + Input: A=$1234 X=$6000 Y=$5678 P=$00 E=0 DBR=$7f ($7e7000)=$fc ($7e7001)=$00 ($7e7002)=$f0 ($7e7003)=$db ($7e5000)=$00 ($7e5001)=$80 + Expected output: A=$1234 X=$6000 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 0276: jsr ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$10 E=0 DBR=$7f ($7e7000)=$fc ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$10 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$70 + Additional initialization or checks are performed - see assembly +Test 0277: jsr ($FFFF,x) + Input: A=$1234 X=$0081 Y=$5678 P=$30 E=1 S=$0100 DBR=$7f ($7e7000)=$fc ($7e7001)=$ff ($7e7002)=$ff ($7e7003)=$db ($7e0080)=$00 ($7e0081)=$80 + Expected output: A=$1234 X=$0081 Y=$0078 P=$30 E=1 S=01fe ($0000ff)=$02 ($000100)=$70 + Additional initialization or checks are performed - see assembly +Test 0278: lda #$8000 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 +Test 0279: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($7f1212)=$00 ($7f1213)=$80 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 027a: lda ($10,x) + Input: A=$1234 X=$0123 Y=$5678 P=$02 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$0123 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 027b: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$12 E=0 DBR=$7f D=$ff00 ($7f1212)=$00 ($7f1213)=$80 + Expected output: A=$8000 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 027c: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($000201)=$00 ($000202)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$00 ($000202)=$80 +Test 027d: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 027e: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 ($7f1235)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 027f: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0280: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0281: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0282: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0283: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0284: lda ($34),y + Input: A=$1234 X=$3456 Y=$1111 P=$02 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0285: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 ($7f1235)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 0286: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$02 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0287: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 0288: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 0289: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1111 P=$02 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 028a: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$8000 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 028b: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$8000 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$00 ($000034)=$80 +Test 028c: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$02 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 ($7f0fdd)=$80 + Expected output: A=$8000 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 028d: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$12 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 ($7ffeed)=$80 + Expected output: A=$8000 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 028e: lda [$34],y + Input: A=$1234 X=$3456 Y=$1111 P=$02 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$8000 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 028f: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 0290: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$12 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 0291: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 0292: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$12 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 0293: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$02 E=0 ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$8000 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 0294: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$12 E=0 ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$8000 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 0295: ldx #$8000 + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 +Test 0296: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 0297: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$8000 Y=$5678 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0298: ldx $02,y + Input: A=$1234 X=$1234 Y=$0133 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$8000 Y=$0133 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 0299: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$0300 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$8000 Y=$0300 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 029a: ldy #$8000 + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 +Test 029b: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 ($000033)=$00 ($000034)=$80 +Test 029c: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$02 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$8000 P=$80 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 029d: ldy $02,x + Input: A=$1234 X=$0133 Y=$1234 P=$02 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$8000 P=$80 E=0 ($000134)=$00 ($000135)=$80 +Test 029e: ldy $FFFF,x + Input: A=$1234 X=$0300 Y=$1234 P=$02 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$8000 P=$80 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 029f: lda #$00 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 +Test 02a0: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$00 ($7f1213)=$00 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$4f E=0 ($7f1212)=$00 ($7f1213)=$00 +Test 02a1: lda ($10,x) + Input: A=$1234 X=$0123 Y=$5678 P=$cf E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$0123 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02a2: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$00 ($7f1213)=$00 + Expected output: A=$0000 X=$0010 Y=$0078 P=$5f E=0 ($7f1212)=$00 ($7f1213)=$00 +Test 02a3: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$00 ($000202)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($000201)=$00 ($000202)=$00 +Test 02a4: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 02a5: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 ($7f1235)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7f1234)=$00 ($7f1235)=$00 +Test 02a6: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02a7: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02a8: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02a9: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 02aa: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 02ab: lda ($34),y + Input: A=$1234 X=$3456 Y=$1111 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$1111 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02ac: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 ($7f1235)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7f1234)=$00 ($7f1235)=$00 +Test 02ad: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02ae: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 02af: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 02b0: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1111 P=$cf E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$1111 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02b1: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$0000 X=$0133 Y=$5678 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 02b2: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$0000 X=$0032 Y=$0078 P=$5f E=0 ($000033)=$00 ($000034)=$00 +Test 02b3: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 ($7f0fdd)=$00 + Expected output: A=$0000 X=$3456 Y=$1100 P=$4f E=0 ($7f0fdc)=$00 ($7f0fdd)=$00 +Test 02b4: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 ($7ffeed)=$00 + Expected output: A=$0000 X=$0056 Y=$0010 P=$5f E=0 ($7ffeec)=$00 ($7ffeed)=$00 +Test 02b5: lda [$34],y + Input: A=$1234 X=$3456 Y=$1111 P=$cf E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$0000 X=$3456 Y=$1111 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02b6: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$3456 Y=$0300 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02b7: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0056 Y=$0030 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 02b8: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$0300 Y=$5678 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02b9: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0030 Y=$0078 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 02ba: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$0000 X=$0300 Y=$5678 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02bb: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$00 ($7f0030)=$00 + Expected output: A=$0000 X=$0030 Y=$0078 P=$5f E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 02bc: ldx #$00 + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 +Test 02bd: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 02be: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02bf: ldx $02,y + Input: A=$1234 X=$1234 Y=$0133 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0000 Y=$0133 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 02c0: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0000 Y=$0300 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02c1: ldy #$00 + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 +Test 02c2: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 ($000033)=$00 ($000034)=$00 +Test 02c3: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$cf E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$4f E=0 ($7effff)=$00 ($7f0000)=$00 +Test 02c4: ldy $02,x + Input: A=$1234 X=$0133 Y=$1234 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$0000 P=$4f E=0 ($000134)=$00 ($000135)=$00 +Test 02c5: ldy $FFFF,x + Input: A=$1234 X=$0300 Y=$1234 P=$cf E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$0000 P=$4f E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 02c6: lda #$80 + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 +Test 02c7: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($7f1212)=$80 + Expected output: A=$1280 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$80 +Test 02c8: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$32 E=0 DBR=$7f D=$ff00 ($7f1212)=$80 + Expected output: A=$1280 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$80 +Test 02c9: lda ($EF,x) + Input: A=$1234 X=$0010 Y=$5678 P=$22 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02ca: lda ($F0,x) + Input: A=$1234 X=$0010 Y=$5678 P=$22 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02cb: lda ($F6,x) + Input: A=$1234 X=$00ee Y=$5678 P=$22 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02cc: lda ($F7,x) + Input: A=$1234 X=$00ee Y=$5678 P=$22 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$80 + Note: This tests undocumented behavior - see the cputest README file for details +Test 02cd: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($000201)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$80 +Test 02ce: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 ($000201)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($000201)=$80 +Test 02cf: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$80 +Test 02d0: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($000033)=$80 +Test 02d1: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$80 +Test 02d2: lda [$FF] + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02d3: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$80 +Test 02d4: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 DBR=$7e ($7effff)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$80 +Test 02d5: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$80 +Test 02d6: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 ($7effff)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$80 +Test 02d7: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 02d8: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 02d9: lda ($FF),y + Input: A=$1234 X=$3456 Y=$0010 P=$22 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$80 +Test 02da: lda ($FE),y + Input: A=$1234 X=$3456 Y=$0010 P=$22 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$80 +Test 02db: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$80 +Test 02dc: lda ($FF) + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02dd: lda ($FE) + Input: A=$1234 X=$3456 Y=$5678 P=$22 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$80 + Expected output: A=$1280 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$80 +Test 02de: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 02df: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 02e0: lda ($12,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$22 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=1 ($7ffeec)=$80 +Test 02e1: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$22 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1280 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$80 +Test 02e2: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$32 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$80 +Test 02e3: lda $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$22 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1280 X=$0032 Y=$0078 P=$b0 E=1 ($000033)=$80 +Test 02e4: lda $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$22 E=1 DBR=$7f D=$0100 ($000133)=$80 + Expected output: A=$1280 X=$0034 Y=$0078 P=$b0 E=1 ($000133)=$80 +Test 02e5: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$22 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$80 + Expected output: A=$1280 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$80 +Test 02e6: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$32 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$80 +Test 02e7: lda [$FF],y + Input: A=$1234 X=$3456 Y=$0010 P=$22 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$80 + Expected output: A=$1280 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$80 +Test 02e8: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$22 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1280 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$80 +Test 02e9: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$32 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$80 +Test 02ea: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$22 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0056 Y=$0030 P=$b0 E=1 ($7f002f)=$80 +Test 02eb: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$22 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1280 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$80 +Test 02ec: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$32 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$80 +Test 02ed: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$22 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$80 +Test 02ee: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$22 E=0 ($7f02ff)=$80 + Expected output: A=$1280 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$80 +Test 02ef: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$32 E=0 ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$80 +Test 02f0: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$22 E=1 ($7f002f)=$80 + Expected output: A=$1280 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$80 +Test 02f1: ldx #$80 + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 +Test 02f2: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 ($000033)=$80 +Test 02f3: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$b0 E=1 ($000033)=$80 +Test 02f4: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$90 E=0 ($7effff)=$80 +Test 02f5: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$12 E=1 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0080 Y=$0078 P=$b0 E=1 ($7effff)=$80 +Test 02f6: ldx $02,y + Input: A=$1234 X=$1234 Y=$1232 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0032 P=$90 E=0 ($000033)=$80 +Test 02f7: ldx $02,y + Input: A=$1234 X=$1234 Y=$0032 P=$12 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0080 Y=$0032 P=$b0 E=1 ($000033)=$80 +Test 02f8: ldx $FF,y + Input: A=$1234 X=$1234 Y=$0034 P=$12 E=1 DBR=$7f D=$0100 ($000133)=$80 + Expected output: A=$1234 X=$0080 Y=$0034 P=$b0 E=1 ($000133)=$80 +Test 02f9: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$12 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0080 Y=$0030 P=$90 E=0 ($7f002f)=$80 +Test 02fa: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$12 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0080 Y=$0030 P=$b0 E=1 ($7f002f)=$80 +Test 02fb: ldy #$80 + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 +Test 02fc: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 ($000033)=$80 +Test 02fd: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$b0 E=1 ($000033)=$80 +Test 02fe: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$90 E=0 ($7effff)=$80 +Test 02ff: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$12 E=1 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0056 Y=$0080 P=$b0 E=1 ($7effff)=$80 +Test 0300: ldy $02,x + Input: A=$1234 X=$1232 Y=$1234 P=$12 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0080 P=$90 E=0 ($000033)=$80 +Test 0301: ldy $02,x + Input: A=$1234 X=$0032 Y=$1234 P=$12 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0080 P=$b0 E=1 ($000033)=$80 +Test 0302: ldy $FF,x + Input: A=$1234 X=$0034 Y=$1234 P=$12 E=1 DBR=$7f D=$0100 ($000133)=$80 + Expected output: A=$1234 X=$0034 Y=$0080 P=$b0 E=1 ($000133)=$80 +Test 0303: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$12 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0080 P=$90 E=0 ($7f002f)=$80 +Test 0304: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$12 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0080 P=$b0 E=1 ($7f002f)=$80 +Test 0305: lda #$00 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 +Test 0306: lda ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$00 + Expected output: A=$1200 X=$ff91 Y=$5678 P=$6f E=0 ($7f1212)=$00 +Test 0307: lda ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$00 + Expected output: A=$1200 X=$0010 Y=$0078 P=$7f E=0 ($7f1212)=$00 +Test 0308: lda ($EF,x) + Input: A=$1234 X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$0010 Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 0309: lda ($F0,x) + Input: A=$1234 X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$0010 Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 030a: lda ($F6,x) + Input: A=$1234 X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$00ee Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 030b: lda ($F7,x) + Input: A=$1234 X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$00ee Y=$0078 P=$7f E=1 ($7f1234)=$00 + Note: This tests undocumented behavior - see the cputest README file for details +Test 030c: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($000201)=$00 +Test 030d: lda $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 ($000201)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($000201)=$00 +Test 030e: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($000033)=$00 +Test 030f: lda $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($000033)=$00 +Test 0310: lda [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7f1234)=$00 +Test 0311: lda [$FF] + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 0312: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7effff)=$00 +Test 0313: lda $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($7effff)=$00 +Test 0314: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7effff)=$00 +Test 0315: lda $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 ($7effff)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($7effff)=$00 +Test 0316: lda ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 0317: lda ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 0318: lda ($FF),y + Input: A=$1234 X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=1 ($7f1244)=$00 +Test 0319: lda ($FE),y + Input: A=$1234 X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=1 ($7f1244)=$00 +Test 031a: lda ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$6f E=0 ($7f1234)=$00 +Test 031b: lda ($FF) + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 031c: lda ($FE) + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$00 + Expected output: A=$1200 X=$0056 Y=$0078 P=$7f E=1 ($7f1234)=$00 +Test 031d: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 031e: lda ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 031f: lda ($12,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$ef E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=1 ($7ffeec)=$00 +Test 0320: lda $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$00 + Expected output: A=$1200 X=$0133 Y=$5678 P=$6f E=0 ($000134)=$00 +Test 0321: lda $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$0032 Y=$0078 P=$7f E=0 ($000033)=$00 +Test 0322: lda $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1200 X=$0032 Y=$0078 P=$7f E=1 ($000033)=$00 +Test 0323: lda $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$00 + Expected output: A=$1200 X=$0034 Y=$0078 P=$7f E=1 ($000133)=$00 +Test 0324: lda [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$00 + Expected output: A=$1200 X=$3456 Y=$1100 P=$6f E=0 ($7f0fdc)=$00 +Test 0325: lda [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=0 ($7ffeec)=$00 +Test 0326: lda [$FF],y + Input: A=$1234 X=$3456 Y=$0010 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$00 + Expected output: A=$1200 X=$0056 Y=$0010 P=$7f E=1 ($7f1244)=$00 +Test 0327: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1200 X=$3456 Y=$0300 P=$6f E=0 ($7f02ff)=$00 +Test 0328: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0056 Y=$0030 P=$7f E=0 ($7f002f)=$00 +Test 0329: lda $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$ef E=1 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0056 Y=$0030 P=$7f E=1 ($7f002f)=$00 +Test 032a: lda $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$00 + Expected output: A=$1200 X=$0300 Y=$5678 P=$6f E=0 ($7f02ff)=$00 +Test 032b: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=0 ($7f002f)=$00 +Test 032c: lda $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=1 ($7f002f)=$00 +Test 032d: lda $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 + Expected output: A=$1200 X=$0300 Y=$5678 P=$6f E=0 ($7f02ff)=$00 +Test 032e: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=0 ($7f002f)=$00 +Test 032f: lda $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 ($7f002f)=$00 + Expected output: A=$1200 X=$0030 Y=$0078 P=$7f E=1 ($7f002f)=$00 +Test 0330: ldx #$00 + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 +Test 0331: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 ($000033)=$00 +Test 0332: ldx $34 + Input: A=$1234 X=$1234 Y=$5678 P=$df E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$7f E=1 ($000033)=$00 +Test 0333: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$5f E=0 ($7effff)=$00 +Test 0334: ldx $FFFF + Input: A=$1234 X=$1234 Y=$5678 P=$df E=1 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$7f E=1 ($7effff)=$00 +Test 0335: ldx $02,y + Input: A=$1234 X=$1234 Y=$1232 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0032 P=$5f E=0 ($000033)=$00 +Test 0336: ldx $02,y + Input: A=$1234 X=$1234 Y=$0032 P=$df E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0000 Y=$0032 P=$7f E=1 ($000033)=$00 +Test 0337: ldx $FF,y + Input: A=$1234 X=$1234 Y=$0034 P=$df E=1 DBR=$7f D=$0100 ($000133)=$00 + Expected output: A=$1234 X=$0000 Y=$0034 P=$7f E=1 ($000133)=$00 +Test 0338: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0000 Y=$0030 P=$5f E=0 ($7f002f)=$00 +Test 0339: ldx $FFFF,y + Input: A=$1234 X=$1234 Y=$1230 P=$df E=1 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0000 Y=$0030 P=$7f E=1 ($7f002f)=$00 +Test 033a: ldy #$00 + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 +Test 033b: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 ($000033)=$00 +Test 033c: ldy $34 + Input: A=$1234 X=$3456 Y=$1234 P=$df E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$7f E=1 ($000033)=$00 +Test 033d: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$df E=0 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$5f E=0 ($7effff)=$00 +Test 033e: ldy $FFFF + Input: A=$1234 X=$3456 Y=$1234 P=$df E=1 DBR=$7e ($7effff)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$7f E=1 ($7effff)=$00 +Test 033f: ldy $02,x + Input: A=$1234 X=$1232 Y=$1234 P=$df E=0 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0000 P=$5f E=0 ($000033)=$00 +Test 0340: ldy $02,x + Input: A=$1234 X=$0032 Y=$1234 P=$df E=1 DBR=$7f D=$ffff ($000033)=$00 + Expected output: A=$1234 X=$0032 Y=$0000 P=$7f E=1 ($000033)=$00 +Test 0341: ldy $FF,x + Input: A=$1234 X=$0034 Y=$1234 P=$df E=1 DBR=$7f D=$0100 ($000133)=$00 + Expected output: A=$1234 X=$0034 Y=$0000 P=$7f E=1 ($000133)=$00 +Test 0342: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$df E=0 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0000 P=$5f E=0 ($7f002f)=$00 +Test 0343: ldy $FFFF,x + Input: A=$1234 X=$1230 Y=$1234 P=$df E=1 DBR=$7e ($7f002f)=$00 + Expected output: A=$1234 X=$0030 Y=$0000 P=$7f E=1 ($7f002f)=$00 +Test 0344: lsr a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 0345: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 0346: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0347: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 0348: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 0349: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 034a: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 034b: lsr a + Input: A=$4222 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$2111 X=$3456 Y=$5678 P=$4c E=0 +Test 034c: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$4c E=0 ($000033)=$11 ($000034)=$21 +Test 034d: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$22 ($7f0000)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$4c E=0 ($7effff)=$11 ($7f0000)=$21 +Test 034e: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$22 ($000135)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$4c E=0 ($000134)=$11 ($000135)=$21 +Test 034f: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$5c E=0 ($000033)=$11 ($000034)=$21 +Test 0350: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$22 ($7f0300)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$4c E=0 ($7f02ff)=$11 ($7f0300)=$21 +Test 0351: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$22 ($7f0030)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$5c E=0 ($7f002f)=$11 ($7f0030)=$21 +Test 0352: lsr a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 0353: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 0354: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 0355: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 0356: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$00 +Test 0357: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 0358: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 0359: lsr $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 035a: lsr $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$01 + Expected output: A=$1234 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$00 +Test 035b: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 035c: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 035d: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$00 +Test 035e: lsr a + Input: A=$1242 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1221 X=$3456 Y=$5678 P=$6c E=0 +Test 035f: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$6c E=0 ($000033)=$21 +Test 0360: lsr $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7c E=1 ($000033)=$21 +Test 0361: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$6c E=0 ($7effff)=$21 +Test 0362: lsr $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7c E=1 ($7effff)=$21 +Test 0363: lsr $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$6c E=0 ($000134)=$21 +Test 0364: lsr $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$7c E=0 ($000033)=$21 +Test 0365: lsr $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$7c E=1 ($000033)=$21 +Test 0366: lsr $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$42 + Expected output: A=$1234 X=$0034 Y=$0078 P=$7c E=1 ($000133)=$21 +Test 0367: lsr $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$6c E=0 ($7f02ff)=$21 +Test 0368: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$7c E=0 ($7f002f)=$21 +Test 0369: lsr $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$7c E=1 ($7f002f)=$21 +Test 036a: mvn #$7e, #$7f + Input: A=$0003 X=$ffff Y=$fffe P=$00 E=0 ($7effff)=$21 ($7e0000)=$22 ($7e0001)=$23 ($7e0002)=$24 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$0003 Y=$0002 P=$00 E=0 DBR=7f ($7ffffe)=$21 ($7fffff)=$22 ($7f0000)=$23 ($7f0001)=$24 ($7f0002)=$99 +Test 036b: mvn #$7f, #$7f + Input: A=$01ff X=$0005 Y=$0000 P=$ef E=0 ($7f0005)=$31 ($7f0204)=$32 ($7f0200)=$99 + Expected output: A=$ffff X=$0205 Y=$0200 P=$ef E=0 DBR=7f ($7f0000)=$31 ($7f01ff)=$32 ($7f0200)=$99 +Test 036c: mvn #$7f, #$7f + Input: A=$01ff X=$0000 Y=$0002 P=$00 E=0 ($7f0000)=$41 ($7f0001)=$42 + Expected output: A=$ffff X=$0200 Y=$0202 P=$00 E=0 DBR=7f ($7f0200)=$41 ($7f0201)=$42 +Test 036d: mvn #$7e, #$7f + Input: A=$0003 X=$05ff Y=$05fe P=$10 E=0 ($7e00ff)=$51 ($7e0000)=$52 ($7e0001)=$53 ($7e0002)=$54 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$0003 Y=$0002 P=$10 E=0 DBR=7f ($7f00fe)=$51 ($7f00ff)=$52 ($7f0000)=$53 ($7f0001)=$54 ($7f0002)=$99 +Test 036e: mvp #$7e, #$7f + Input: A=$0003 X=$0002 Y=$0001 P=$00 E=0 ($7effff)=$21 ($7e0000)=$22 ($7e0001)=$23 ($7e0002)=$24 ($7f0001)=$00 ($7ffffd)=$99 + Expected output: A=$ffff X=$fffe Y=$fffd P=$00 E=0 DBR=7f ($7ffffe)=$21 ($7fffff)=$22 ($7f0000)=$23 ($7f0001)=$24 ($7ffffd)=$99 +Test 036f: mvp #$7f, #$7f + Input: A=$01ff X=$01ff Y=$0204 P=$ef E=0 ($7f0000)=$31 ($7f01ff)=$32 ($7f0004)=$99 + Expected output: A=$ffff X=$ffff Y=$0004 P=$ef E=0 DBR=7f ($7f0005)=$31 ($7f0204)=$32 ($7f0004)=$99 +Test 0370: mvp #$7f, #$7f + Input: A=$01ff X=$0201 Y=$01ff P=$00 E=0 ($7f0200)=$41 ($7f0201)=$42 + Expected output: A=$ffff X=$0001 Y=$ffff P=$00 E=0 DBR=7f ($7f0000)=$41 ($7f0001)=$42 +Test 0371: mvp #$7e, #$7f + Input: A=$0003 X=$0502 Y=$0501 P=$10 E=0 ($7e00ff)=$51 ($7e0000)=$52 ($7e0001)=$53 ($7e0002)=$54 ($7f0001)=$00 ($7f0002)=$99 + Expected output: A=$ffff X=$00fe Y=$00fd P=$10 E=0 DBR=7f ($7f00fe)=$51 ($7f00ff)=$52 ($7f0000)=$53 ($7f0001)=$54 ($7f0002)=$99 +Test 0372: ora #$b939 + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 +Test 0373: ora ($10,x) + Input: A=$2318 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$39 ($7f1213)=$b9 + Expected output: A=$bb39 X=$ff91 Y=$5678 P=$80 E=0 ($7f1212)=$39 ($7f1213)=$b9 +Test 0374: ora ($10,x) + Input: A=$2318 X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$0123 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 0375: ora ($90,x) + Input: A=$2318 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$39 ($7f1213)=$b9 + Expected output: A=$bb39 X=$0010 Y=$0078 P=$90 E=0 ($7f1212)=$39 ($7f1213)=$b9 +Test 0376: ora $12,s + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$39 ($000202)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($000201)=$39 ($000202)=$b9 +Test 0377: ora $34 + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$39 ($000034)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($000033)=$39 ($000034)=$b9 +Test 0378: ora [$34] + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$39 ($7f1235)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$39 ($7f1235)=$b9 +Test 0379: ora [$34] + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 037a: ora $FFFF + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 037b: ora $7EFFFF + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 037c: ora ($34),y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 037d: ora ($34),y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 037e: ora ($34),y + Input: A=$2318 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 037f: ora ($34) + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$39 ($7f1235)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7f1234)=$39 ($7f1235)=$b9 +Test 0380: ora ($34) + Input: A=$2318 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$5678 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 0381: ora ($10,s),y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 0382: ora ($10,s),y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 0383: ora ($10,s),y + Input: A=$2318 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 0384: ora $02,x + Input: A=$2318 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$39 ($000135)=$b9 + Expected output: A=$bb39 X=$0133 Y=$5678 P=$80 E=0 ($000134)=$39 ($000135)=$b9 +Test 0385: ora $02,x + Input: A=$2318 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$39 ($000034)=$b9 + Expected output: A=$bb39 X=$0032 Y=$0078 P=$90 E=0 ($000033)=$39 ($000034)=$b9 +Test 0386: ora [$34],y + Input: A=$2318 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$39 ($7f0fdd)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1100 P=$80 E=0 ($7f0fdc)=$39 ($7f0fdd)=$b9 +Test 0387: ora [$34],y + Input: A=$2318 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$39 ($7ffeed)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0010 P=$90 E=0 ($7ffeec)=$39 ($7ffeed)=$b9 +Test 0388: ora [$34],y + Input: A=$2318 X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$39 ($7f0000)=$b9 + Expected output: A=$bb39 X=$3456 Y=$1111 P=$80 E=0 ($7effff)=$39 ($7f0000)=$b9 +Test 0389: ora $FFFF,y + Input: A=$2318 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$3456 Y=$0300 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 038a: ora $FFFF,y + Input: A=$2318 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0056 Y=$0030 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 038b: ora $FFFF,x + Input: A=$2318 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 038c: ora $FFFF,x + Input: A=$2318 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 038d: ora $7EFFFF,x + Input: A=$2318 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$39 ($7f0300)=$b9 + Expected output: A=$bb39 X=$0300 Y=$5678 P=$80 E=0 ($7f02ff)=$39 ($7f0300)=$b9 +Test 038e: ora $7EFFFF,x + Input: A=$2318 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$39 ($7f0030)=$b9 + Expected output: A=$bb39 X=$0030 Y=$0078 P=$90 E=0 ($7f002f)=$39 ($7f0030)=$b9 +Test 038f: ora #$00 + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 +Test 0390: ora #$4300 + Input: A=$1200 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$5300 X=$3456 Y=$5678 P=$4d E=0 +Test 0391: ora #$39 + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 +Test 0392: ora ($10,x) + Input: A=$1298 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$39 + Expected output: A=$12b9 X=$ff91 Y=$5678 P=$a0 E=0 ($7f1212)=$39 +Test 0393: ora ($90,x) + Input: A=$1298 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$39 + Expected output: A=$12b9 X=$0010 Y=$0078 P=$b0 E=0 ($7f1212)=$39 +Test 0394: ora ($EF,x) + Input: A=$1298 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 0395: ora ($F0,x) + Input: A=$1298 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$0010 Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 0396: ora ($F6,x) + Input: A=$1298 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 0397: ora ($F7,x) + Input: A=$1298 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$00ee Y=$0078 P=$b0 E=1 ($7f1234)=$39 + Note: This tests undocumented behavior - see the cputest README file for details +Test 0398: ora $12,s + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($000201)=$39 +Test 0399: ora $12,s + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 ($000201)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($000201)=$39 +Test 039a: ora $34 + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($000033)=$39 +Test 039b: ora $34 + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($000033)=$39 +Test 039c: ora [$34] + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$39 +Test 039d: ora [$FF] + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 039e: ora $FFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$39 +Test 039f: ora $FFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$39 +Test 03a0: ora $7EFFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7effff)=$39 +Test 03a1: ora $7EFFFF + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($7effff)=$39 +Test 03a2: ora ($34),y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 03a3: ora ($34),y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 03a4: ora ($FF),y + Input: A=$1298 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$39 +Test 03a5: ora ($FE),y + Input: A=$1298 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$39 +Test 03a6: ora ($34) + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$3456 Y=$5678 P=$a0 E=0 ($7f1234)=$39 +Test 03a7: ora ($FF) + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 03a8: ora ($FE) + Input: A=$1298 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$39 + Expected output: A=$12b9 X=$0056 Y=$0078 P=$b0 E=1 ($7f1234)=$39 +Test 03a9: ora ($10,s),y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 03aa: ora ($10,s),y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 03ab: ora ($12,s),y + Input: A=$1298 X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=1 ($7ffeec)=$39 +Test 03ac: ora $02,x + Input: A=$1298 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$39 + Expected output: A=$12b9 X=$0133 Y=$5678 P=$a0 E=0 ($000134)=$39 +Test 03ad: ora $02,x + Input: A=$1298 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$0032 Y=$0078 P=$b0 E=0 ($000033)=$39 +Test 03ae: ora $02,x + Input: A=$1298 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$39 + Expected output: A=$12b9 X=$0032 Y=$0078 P=$b0 E=1 ($000033)=$39 +Test 03af: ora $FF,x + Input: A=$1298 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$39 + Expected output: A=$12b9 X=$0034 Y=$0078 P=$b0 E=1 ($000133)=$39 +Test 03b0: ora [$34],y + Input: A=$1298 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$39 + Expected output: A=$12b9 X=$3456 Y=$1100 P=$a0 E=0 ($7f0fdc)=$39 +Test 03b1: ora [$34],y + Input: A=$1298 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=0 ($7ffeec)=$39 +Test 03b2: ora [$FF],y + Input: A=$1298 X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$39 + Expected output: A=$12b9 X=$0056 Y=$0010 P=$b0 E=1 ($7f1244)=$39 +Test 03b3: ora $FFFF,y + Input: A=$1298 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$39 + Expected output: A=$12b9 X=$3456 Y=$0300 P=$a0 E=0 ($7f02ff)=$39 +Test 03b4: ora $FFFF,y + Input: A=$1298 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0056 Y=$0030 P=$b0 E=0 ($7f002f)=$39 +Test 03b5: ora $FFFF,y + Input: A=$1298 X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0056 Y=$0030 P=$b0 E=1 ($7f002f)=$39 +Test 03b6: ora $FFFF,x + Input: A=$1298 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$39 + Expected output: A=$12b9 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$39 +Test 03b7: ora $FFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$39 +Test 03b8: ora $FFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$39 +Test 03b9: ora $7EFFFF,x + Input: A=$1298 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$39 + Expected output: A=$12b9 X=$0300 Y=$5678 P=$a0 E=0 ($7f02ff)=$39 +Test 03ba: ora $7EFFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=0 ($7f002f)=$39 +Test 03bb: ora $7EFFFF,x + Input: A=$1298 X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$39 + Expected output: A=$12b9 X=$0030 Y=$0078 P=$b0 E=1 ($7f002f)=$39 +Test 03bc: ora #$00 + Input: A=$aa00 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$22 E=0 +Test 03bd: nop + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 03be: nop + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 +Test 03bf: wdm $AB + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 03c0: wdm $AB + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 +Test 03c1: pea $ABCD + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$cd ($0001ef)=$ab +Test 03c2: pea $9876 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fe ($0000ff)=$76 ($000100)=$98 +Test 03c3: pei ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$65 ($0001ef)=$87 +Test 03c4: pei ($ff) + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 DBR=$7f D=$0200 ($0002ff)=$54 ($000300)=$76 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fe ($0000ff)=$54 ($000100)=$76 +Test 03c5: per -$8000 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$62 ($7e7001)=$00 ($7e7002)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$03 ($0001ef)=$f0 + Additional initialization or checks are performed - see assembly +Test 03c6: per +$7FFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e7000)=$62 ($7e7001)=$ff ($7e7002)=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$02 ($0001ef)=$f0 + Additional initialization or checks are performed - see assembly +Test 03c7: per -$8000 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 ($7e7000)=$62 ($7e7001)=$00 ($7e7002)=$80 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fe ($0000ff)=$03 ($000100)=$f0 + Additional initialization or checks are performed - see assembly +Test 03c8: pla + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$fedc X=$3456 Y=$5678 P=$80 E=0 S=01f1 +Test 03c9: plx + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$1234 X=$fedc Y=$5678 P=$80 E=0 S=01f1 +Test 03ca: ply + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$dc ($0001f1)=$fe + Expected output: A=$1234 X=$3456 Y=$fedc P=$80 E=0 S=01f1 +Test 03cb: pla + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 S=01f1 +Test 03cc: plx + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0000 Y=$5678 P=$02 E=0 S=01f1 +Test 03cd: ply + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$3456 Y=$0000 P=$02 E=0 S=01f1 +Test 03ce: pla + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$12ef X=$3456 Y=$5678 P=$ed E=0 S=01f0 +Test 03cf: plx + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$1234 X=$00ef Y=$0078 P=$dd E=0 S=01f0 +Test 03d0: ply + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 ($0001f0)=$ef ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$00ef P=$dd E=0 S=01f0 +Test 03d1: pla + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1200 X=$3456 Y=$5678 P=$22 E=0 S=01f0 +Test 03d2: plx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 S=01f0 +Test 03d3: ply + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$0000 P=$12 E=0 S=01f0 +Test 03d4: pla + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000100)=$ce + Expected output: A=$12ce X=$0056 Y=$0078 P=$b0 E=1 S=0100 +Test 03d5: plx + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000100)=$ce + Expected output: A=$1234 X=$00ce Y=$0078 P=$b0 E=1 S=0100 +Test 03d6: ply + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000100)=$ce + Expected output: A=$1234 X=$0056 Y=$00ce P=$b0 E=1 S=0100 +Test 03d7: plb + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$fe + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 S=01f0 DBR=fe +Test 03d8: plb + Input: A=$1234 X=$3456 Y=$5678 P=$fd E=0 ($0001f0)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7f E=0 S=01f0 DBR=00 +Test 03d9: plb + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000200)=$3d + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 S=0100 DBR=3d + Note: This tests undocumented behavior - see the cputest README file for details +Test 03da: pld + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$53 ($0001f1)=$97 + Expected output: A=$1234 X=$3456 Y=$5678 P=$80 E=0 S=01f1 D=9753 +Test 03db: pld + Input: A=$1234 X=$3456 Y=$5678 P=$fd E=0 D=$9999 ($0001f0)=$00 ($0001f1)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$7f E=0 S=01f1 D=0000 +Test 03dc: pld + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000200)=$56 ($000201)=$13 + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 S=0101 D=1356 +Test 03dd: plp + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 ($0001f0)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$00 E=0 S=01f0 +Test 03de: plp + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$23 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 S=01f0 +Test 03df: plp + Input: A=$1234 X=$2345 Y=$3456 P=$00 E=0 ($0001f0)=$10 + Expected output: A=$1234 X=$0045 Y=$0056 P=$10 E=0 S=01f0 +Test 03e0: plp + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 S=$01ff ($000100)=$41 + Expected output: A=$1234 X=$0056 Y=$0078 P=$71 E=1 S=0100 +Test 03e1: pha + Input: A=$9876 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$9876 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$76 ($0001ef)=$98 +Test 03e2: pha + Input: A=$8765 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$8765 X=$3456 Y=$5678 P=$ef E=0 S=01ee ($0001ef)=$65 +Test 03e3: pha + Input: A=$5678 X=$3456 Y=$5678 P=$30 E=1 S=$0100 + Expected output: A=$5678 X=$0056 Y=$0078 P=$30 E=1 S=01ff ($000100)=$78 +Test 03e4: phx + Input: A=$1234 X=$9876 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$9876 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$76 ($0001ef)=$98 +Test 03e5: phx + Input: A=$1234 X=$0023 Y=$5678 P=$df E=0 + Expected output: A=$1234 X=$0023 Y=$0078 P=$df E=0 S=01ee ($0001ef)=$23 +Test 03e6: phx + Input: A=$1234 X=$0034 Y=$5678 P=$30 E=1 S=$0100 + Expected output: A=$1234 X=$0034 Y=$0078 P=$30 E=1 S=01ff ($000100)=$34 +Test 03e7: phy + Input: A=$1234 X=$3456 Y=$1324 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$1324 P=$00 E=0 S=01ed ($0001ee)=$24 ($0001ef)=$13 +Test 03e8: phy + Input: A=$1234 X=$3456 Y=$0035 P=$df E=0 + Expected output: A=$1234 X=$0056 Y=$0035 P=$df E=0 S=01ee ($0001ef)=$35 +Test 03e9: phy + Input: A=$1234 X=$3456 Y=$0046 P=$30 E=1 S=$0100 + Expected output: A=$1234 X=$0056 Y=$0046 P=$30 E=1 S=01ff ($000100)=$46 +Test 03ea: phb + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ee ($0001ef)=$7f +Test 03eb: phb + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 DBR=$7f + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01ff ($000100)=$7f +Test 03ec: phd + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 D=$6543 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ed ($0001ee)=$43 ($0001ef)=$65 +Test 03ed: phd + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 D=$1357 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01fe ($0000ff)=$57 ($000100)=$13 +Test 03ee: phk + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e8000)=$4b + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01ee ($0001ef)=$7e + Additional initialization or checks are performed - see assembly +Test 03ef: phk + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 ($7e8000)=$4b + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01ff ($000100)=$7e + Additional initialization or checks are performed - see assembly +Test 03f0: php + Input: A=$1234 X=$3456 Y=$5678 P=$0a E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$0a E=0 S=01ee ($0001ef)=$0a +Test 03f1: php + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$0100 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=01ff ($000100)=$ff +Test 03f2: sep #$FF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=0 +Test 03f3: sep #$0F + Input: A=$1234 X=$3456 Y=$5678 P=$11 E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$1f E=0 +Test 03f4: rep #$F0 + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$0f E=0 +Test 03f5: rep #$0F + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$f0 E=0 +Test 03f6: rep #$38 + Input: A=$1234 X=$3456 Y=$5678 P=$3a E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$32 E=1 +Test 03f7: rol a + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 03f8: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 03f9: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$00 ($7f0000)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 03fa: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$00 ($000135)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 03fb: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$00 ($000034)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 03fc: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$00 ($7f0300)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 03fd: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$00 ($7f0030)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 03fe: rol a + Input: A=$4111 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$8223 X=$3456 Y=$5678 P=$cc E=0 +Test 03ff: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$23 ($000034)=$82 +Test 0400: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$11 ($7f0000)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$23 ($7f0000)=$82 +Test 0401: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$11 ($000135)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$23 ($000135)=$82 +Test 0402: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$11 ($000034)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$23 ($000034)=$82 +Test 0403: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$11 ($7f0300)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$23 ($7f0300)=$82 +Test 0404: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$11 ($7f0030)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$23 ($7f0030)=$82 +Test 0405: rol a + Input: A=$1280 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 0406: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 0407: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 0408: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 0409: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$80 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$00 +Test 040a: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$80 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 040b: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 040c: rol $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$80 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 040d: rol $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$80 + Expected output: A=$1234 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$00 +Test 040e: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$80 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 040f: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 0410: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$80 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$00 +Test 0411: rol a + Input: A=$1241 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1283 X=$3456 Y=$5678 P=$ec E=0 +Test 0412: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$83 +Test 0413: rol $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($000033)=$83 +Test 0414: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$83 +Test 0415: rol $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$41 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($7effff)=$83 +Test 0416: rol $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$41 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$83 +Test 0417: rol $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$83 +Test 0418: rol $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$41 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=1 ($000033)=$83 +Test 0419: rol $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$41 + Expected output: A=$1234 X=$0034 Y=$0078 P=$fc E=1 ($000133)=$83 +Test 041a: rol $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$41 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$83 +Test 041b: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$83 +Test 041c: rol $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$41 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=1 ($7f002f)=$83 +Test 041d: ror a + Input: A=$0001 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 041e: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$00 ($000034)=$00 +Test 041f: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$01 ($7f0000)=$00 + Expected output: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0420: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$01 ($000135)=$00 + Expected output: A=$1234 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$00 ($000135)=$00 +Test 0421: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$01 ($000034)=$00 + Expected output: A=$1234 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$00 ($000034)=$00 +Test 0422: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$01 ($7f0300)=$00 + Expected output: A=$1234 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0423: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$01 ($7f0030)=$00 + Expected output: A=$1234 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0424: ror a + Input: A=$4222 X=$3456 Y=$5678 P=$cf E=0 + Expected output: A=$a111 X=$3456 Y=$5678 P=$cc E=0 +Test 0425: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($000033)=$11 ($000034)=$a1 +Test 0426: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$22 ($7f0000)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cc E=0 ($7effff)=$11 ($7f0000)=$a1 +Test 0427: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$22 ($000135)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cc E=0 ($000134)=$11 ($000135)=$a1 +Test 0428: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$22 ($000034)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$dc E=0 ($000033)=$11 ($000034)=$a1 +Test 0429: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$22 ($7f0300)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cc E=0 ($7f02ff)=$11 ($7f0300)=$a1 +Test 042a: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$22 ($7f0030)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$dc E=0 ($7f002f)=$11 ($7f0030)=$a1 +Test 042b: ror a + Input: A=$1201 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$5678 P=$23 E=0 +Test 042c: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$00 +Test 042d: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 042e: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$00 +Test 042f: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$01 + Expected output: A=$1234 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$00 +Test 0430: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$01 + Expected output: A=$1234 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$00 +Test 0431: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$00 +Test 0432: ror $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$01 + Expected output: A=$1234 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$00 +Test 0433: ror $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$01 + Expected output: A=$1234 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$00 +Test 0434: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$01 + Expected output: A=$1234 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$00 +Test 0435: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$00 +Test 0436: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$01 + Expected output: A=$1234 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$00 +Test 0437: ror a + Input: A=$1242 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$12a1 X=$3456 Y=$5678 P=$ec E=0 +Test 0438: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($000033)=$a1 +Test 0439: ror $34 + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($000033)=$a1 +Test 043a: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$3456 Y=$5678 P=$ec E=0 ($7effff)=$a1 +Test 043b: ror $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$42 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fc E=1 ($7effff)=$a1 +Test 043c: ror $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$42 + Expected output: A=$1234 X=$0133 Y=$5678 P=$ec E=0 ($000134)=$a1 +Test 043d: ror $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=0 ($000033)=$a1 +Test 043e: ror $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$42 + Expected output: A=$1234 X=$0032 Y=$0078 P=$fc E=1 ($000033)=$a1 +Test 043f: ror $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$42 + Expected output: A=$1234 X=$0034 Y=$0078 P=$fc E=1 ($000133)=$a1 +Test 0440: ror $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$42 + Expected output: A=$1234 X=$0300 Y=$5678 P=$ec E=0 ($7f02ff)=$a1 +Test 0441: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=0 ($7f002f)=$a1 +Test 0442: ror $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$42 + Expected output: A=$1234 X=$0030 Y=$0078 P=$fc E=1 ($7f002f)=$a1 +Test 0443: rts + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7e8000)=$60 ($0001f0)=$ff ($0001f1)=$ff + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01f1 + Additional initialization or checks are performed - see assembly +Test 0444: rts + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$01ff ($7e8000)=$60 ($000100)=$ff ($000101)=$ff + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=0101 + Additional initialization or checks are performed - see assembly +Test 0445: rtl + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($0001f0)=$ff ($0001f1)=$ff ($0001f2)=$7e + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 S=01f2 + Additional initialization or checks are performed - see assembly +Test 0446: rtl + Input: A=$1234 X=$3456 Y=$5678 P=$ff E=1 S=$01ff ($000200)=$ff ($000201)=$ff ($000202)=$7e ($000100)=$ff ($000101)=$0f ($000102)=$7f + Expected output: A=$1234 X=$0056 Y=$0078 P=$ff E=1 S=0102 + Additional initialization or checks are performed - see assembly +Test 0447: rti + Input: A=$1234 X=$3456 Y=$5678 P=$03 E=0 ($0001f0)=$88 ($0001f1)=$00 ($0001f2)=$00 ($0001f3)=$7e + Expected output: A=$1234 X=$3456 Y=$5678 P=$88 E=0 S=01f3 + Additional initialization or checks are performed - see assembly +Test 0448: rts + Input: A=$1234 X=$3456 Y=$5678 P=$03 E=1 S=$01ff ($7e8000)=$40 ($000100)=$88 ($000101)=$00 ($000102)=$00 + Expected output: A=$1234 X=$0056 Y=$0078 P=$b8 E=1 S=0102 + Additional initialization or checks are performed - see assembly +Test 0449: sbc #$908f + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 +Test 044a: sbc ($10,x) + Input: A=$9090 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$8f ($7f1213)=$90 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$03 E=0 ($7f1212)=$8f ($7f1213)=$90 +Test 044b: sbc ($10,x) + Input: A=$9090 X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$0123 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 044c: sbc ($90,x) + Input: A=$9090 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$8f ($7f1213)=$90 + Expected output: A=$0000 X=$0010 Y=$0078 P=$13 E=0 ($7f1212)=$8f ($7f1213)=$90 +Test 044d: sbc $12,s + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$8f ($000202)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000201)=$8f ($000202)=$90 +Test 044e: sbc $34 + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$8f ($000034)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($000033)=$8f ($000034)=$90 +Test 044f: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8f ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$8f ($7f1235)=$90 +Test 0450: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0451: sbc $FFFF + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0452: sbc $7EFFFF + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0453: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 0454: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 0455: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0456: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8f ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7f1234)=$8f ($7f1235)=$90 +Test 0457: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0458: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 0459: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 045a: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 045b: sbc $02,x + Input: A=$9090 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$8f ($000135)=$90 + Expected output: A=$0000 X=$0133 Y=$5678 P=$03 E=0 ($000134)=$8f ($000135)=$90 +Test 045c: sbc $02,x + Input: A=$9090 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$8f ($000034)=$90 + Expected output: A=$0000 X=$0032 Y=$0078 P=$13 E=0 ($000033)=$8f ($000034)=$90 +Test 045d: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8f ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$03 E=0 ($7f0fdc)=$8f ($7f0fdd)=$90 +Test 045e: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8f ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$13 E=0 ($7ffeec)=$8f ($7ffeed)=$90 +Test 045f: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$8f ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$03 E=0 ($7effff)=$8f ($7f0000)=$90 +Test 0460: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$3456 Y=$0300 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 0461: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0056 Y=$0030 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 0462: sbc $FFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 0463: sbc $FFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 0464: sbc $7EFFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$8f ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$03 E=0 ($7f02ff)=$8f ($7f0300)=$90 +Test 0465: sbc $7EFFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$8f ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$13 E=0 ($7f002f)=$8f ($7f0030)=$90 +Test 0466: sbc #$2000 + Input: A=$9090 X=$3456 Y=$5678 P=$01 E=0 + Expected output: A=$7090 X=$3456 Y=$5678 P=$41 E=0 +Test 0467: sbc #$1235 + Input: A=$1234 X=$3456 Y=$5678 P=$47 E=0 + Expected output: A=$ffff X=$3456 Y=$5678 P=$84 E=0 +Test 0468: sbc #$a000 + Input: A=$7000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$cfff X=$3456 Y=$5678 P=$c0 E=0 +Test 0469: sbc #$8f + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 +Test 046a: sbc ($10,x) + Input: A=$cc90 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$8f + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$23 E=0 ($7f1212)=$8f +Test 046b: sbc ($90,x) + Input: A=$cc90 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$8f + Expected output: A=$cc00 X=$0010 Y=$0078 P=$33 E=0 ($7f1212)=$8f +Test 046c: sbc ($EF,x) + Input: A=$cc90 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 046d: sbc ($F0,x) + Input: A=$cc90 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$0010 Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 046e: sbc ($F6,x) + Input: A=$cc90 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 046f: sbc ($F7,x) + Input: A=$cc90 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$00ee Y=$0078 P=$33 E=1 ($7f1234)=$8f + Note: This tests undocumented behavior - see the cputest README file for details +Test 0470: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($000201)=$8f +Test 0471: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 ($000201)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($000201)=$8f +Test 0472: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($000033)=$8f +Test 0473: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($000033)=$8f +Test 0474: sbc [$34] + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$8f +Test 0475: sbc [$FF] + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 0476: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$8f +Test 0477: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$8f +Test 0478: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7effff)=$8f +Test 0479: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($7effff)=$8f +Test 047a: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 047b: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 047c: sbc ($FF),y + Input: A=$cc90 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$8f +Test 047d: sbc ($FE),y + Input: A=$cc90 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$8f +Test 047e: sbc ($34) + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$3456 Y=$5678 P=$23 E=0 ($7f1234)=$8f +Test 047f: sbc ($FF) + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 0480: sbc ($FE) + Input: A=$cc90 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$8f + Expected output: A=$cc00 X=$0056 Y=$0078 P=$33 E=1 ($7f1234)=$8f +Test 0481: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 0482: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 0483: sbc ($12,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=1 ($7ffeec)=$8f +Test 0484: sbc $02,x + Input: A=$cc90 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$8f + Expected output: A=$cc00 X=$0133 Y=$5678 P=$23 E=0 ($000134)=$8f +Test 0485: sbc $02,x + Input: A=$cc90 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$0032 Y=$0078 P=$33 E=0 ($000033)=$8f +Test 0486: sbc $02,x + Input: A=$cc90 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$8f + Expected output: A=$cc00 X=$0032 Y=$0078 P=$33 E=1 ($000033)=$8f +Test 0487: sbc $FF,x + Input: A=$cc90 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$8f + Expected output: A=$cc00 X=$0034 Y=$0078 P=$33 E=1 ($000133)=$8f +Test 0488: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$8f + Expected output: A=$cc00 X=$3456 Y=$1100 P=$23 E=0 ($7f0fdc)=$8f +Test 0489: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=0 ($7ffeec)=$8f +Test 048a: sbc [$FF],y + Input: A=$cc90 X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$8f + Expected output: A=$cc00 X=$0056 Y=$0010 P=$33 E=1 ($7f1244)=$8f +Test 048b: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$8f + Expected output: A=$cc00 X=$3456 Y=$0300 P=$23 E=0 ($7f02ff)=$8f +Test 048c: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0056 Y=$0030 P=$33 E=0 ($7f002f)=$8f +Test 048d: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0056 Y=$0030 P=$33 E=1 ($7f002f)=$8f +Test 048e: sbc $FFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$8f + Expected output: A=$cc00 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$8f +Test 048f: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$8f +Test 0490: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$8f +Test 0491: sbc $7EFFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$8f + Expected output: A=$cc00 X=$0300 Y=$5678 P=$23 E=0 ($7f02ff)=$8f +Test 0492: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=0 ($7f002f)=$8f +Test 0493: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$8f + Expected output: A=$cc00 X=$0030 Y=$0078 P=$33 E=1 ($7f002f)=$8f +Test 0494: sbc #$20 + Input: A=$cc90 X=$3456 Y=$5678 P=$21 E=0 + Expected output: A=$cc70 X=$3456 Y=$5678 P=$61 E=0 +Test 0495: sbc #$13 + Input: A=$cc12 X=$3456 Y=$5678 P=$67 E=0 + Expected output: A=$ccff X=$3456 Y=$5678 P=$a4 E=0 +Test 0496: sbc #$a0 + Input: A=$cc70 X=$3456 Y=$5678 P=$20 E=0 + Expected output: A=$cccf X=$3456 Y=$5678 P=$e0 E=0 +Test 0497: sta ($10,x) + Input: A=$8000 X=$ff91 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$00 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 0498: sta ($10,x) + Input: A=$8000 X=$0123 Y=$5678 P=$00 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$0123 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 0499: sta ($90,x) + Input: A=$8000 X=$1210 Y=$5678 P=$10 E=0 DBR=$7f D=$ff00 ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$0010 Y=$0078 P=$10 E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 049a: sta $12,s + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$34 ($000202)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000201)=$00 ($000202)=$80 +Test 049b: sta $34 + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 049c: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 049d: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 049e: sta $FFFF + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 049f: sta $7EFFFF + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04a0: sta ($34),y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04a1: sta ($34),y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04a2: sta ($34),y + Input: A=$8000 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04a3: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 04a4: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04a5: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04a6: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04a7: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1111 P=$00 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04a8: sta $02,x + Input: A=$8000 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$8000 X=$0133 Y=$5678 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 04a9: sta $02,x + Input: A=$8000 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$0032 Y=$0078 P=$10 E=0 ($000033)=$00 ($000034)=$80 +Test 04aa: sta [$34],y + Input: A=$8000 X=$3456 Y=$1100 P=$00 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$00 E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04ab: sta [$34],y + Input: A=$8000 X=$3456 Y=$1110 P=$10 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$10 E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04ac: sta [$34],y + Input: A=$8000 X=$3456 Y=$1111 P=$00 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04ad: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$0300 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$3456 Y=$0300 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04ae: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$1230 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0056 Y=$0030 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04af: sta $FFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04b0: sta $FFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04b1: sta $7EFFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04b2: sta $7EFFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$10 E=0 ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04b3: stx $34 + Input: A=$1234 X=$8000 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 04b4: stx $FFFF + Input: A=$1234 X=$8000 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04b5: stx $02,y + Input: A=$1234 X=$8000 Y=$0133 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$8000 Y=$0133 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 04b6: sty $34 + Input: A=$1234 X=$3456 Y=$8000 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$00 E=0 ($000033)=$00 ($000034)=$80 +Test 04b7: sty $FFFF + Input: A=$1234 X=$3456 Y=$8000 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$00 E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04b8: sty $02,x + Input: A=$1234 X=$0133 Y=$8000 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$8000 P=$00 E=0 ($000134)=$00 ($000135)=$80 +Test 04b9: sta ($10,x) + Input: A=$8000 X=$ff91 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$ff91 Y=$5678 P=$cf E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 04ba: sta ($10,x) + Input: A=$8000 X=$0123 Y=$5678 P=$cf E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$0123 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04bb: sta ($90,x) + Input: A=$8000 X=$1210 Y=$5678 P=$df E=0 DBR=$7f D=$ff00 ($7f1212)=$34 ($7f1213)=$12 + Expected output: A=$8000 X=$0010 Y=$0078 P=$df E=0 ($7f1212)=$00 ($7f1213)=$80 +Test 04bc: sta $12,s + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$34 ($000202)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000201)=$00 ($000202)=$80 +Test 04bd: sta $34 + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 04be: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 04bf: sta [$34] + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04c0: sta $FFFF + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04c1: sta $7EFFFF + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04c2: sta ($34),y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04c3: sta ($34),y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04c4: sta ($34),y + Input: A=$8000 X=$3456 Y=$1111 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04c5: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$34 ($7f1235)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7f1234)=$00 ($7f1235)=$80 +Test 04c6: sta ($34) + Input: A=$8000 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04c7: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04c8: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04c9: sta ($10,s),y + Input: A=$8000 X=$3456 Y=$1111 P=$cf E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04ca: sta $02,x + Input: A=$8000 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$8000 X=$0133 Y=$5678 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 04cb: sta $02,x + Input: A=$8000 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$8000 X=$0032 Y=$0078 P=$df E=0 ($000033)=$00 ($000034)=$80 +Test 04cc: sta [$34],y + Input: A=$8000 X=$3456 Y=$1100 P=$cf E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$34 ($7f0fdd)=$12 + Expected output: A=$8000 X=$3456 Y=$1100 P=$cf E=0 ($7f0fdc)=$00 ($7f0fdd)=$80 +Test 04cd: sta [$34],y + Input: A=$8000 X=$3456 Y=$1110 P=$df E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$34 ($7ffeed)=$12 + Expected output: A=$8000 X=$0056 Y=$0010 P=$df E=0 ($7ffeec)=$00 ($7ffeed)=$80 +Test 04ce: sta [$34],y + Input: A=$8000 X=$3456 Y=$1111 P=$cf E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$8000 X=$3456 Y=$1111 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04cf: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$0300 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$3456 Y=$0300 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04d0: sta $FFFF,y + Input: A=$8000 X=$3456 Y=$1230 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0056 Y=$0030 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04d1: sta $FFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04d2: sta $FFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04d3: sta $7EFFFF,x + Input: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$8000 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$80 +Test 04d4: sta $7EFFFF,x + Input: A=$8000 X=$1230 Y=$5678 P=$df E=0 ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$8000 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$80 +Test 04d5: stx $34 + Input: A=$1234 X=$8000 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 04d6: stx $FFFF + Input: A=$1234 X=$8000 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$8000 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04d7: stx $02,y + Input: A=$1234 X=$8000 Y=$0133 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$8000 Y=$0133 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 04d8: sty $34 + Input: A=$1234 X=$3456 Y=$8000 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cf E=0 ($000033)=$00 ($000034)=$80 +Test 04d9: sty $FFFF + Input: A=$1234 X=$3456 Y=$8000 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$8000 P=$cf E=0 ($7effff)=$00 ($7f0000)=$80 +Test 04da: sty $02,x + Input: A=$1234 X=$0133 Y=$8000 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$8000 P=$cf E=0 ($000134)=$00 ($000135)=$80 +Test 04db: sta ($10,x) + Input: A=$5500 X=$ff91 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($7f1212)=$12 + Expected output: A=$5500 X=$ff91 Y=$5678 P=$20 E=0 ($7f1212)=$00 +Test 04dc: sta ($90,x) + Input: A=$5500 X=$1210 Y=$5678 P=$30 E=0 DBR=$7f D=$ff00 ($7f1212)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$30 E=0 ($7f1212)=$00 +Test 04dd: sta ($EF,x) + Input: A=$5500 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04de: sta ($F0,x) + Input: A=$5500 X=$0010 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04df: sta ($F6,x) + Input: A=$5500 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$00ee Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04e0: sta ($F7,x) + Input: A=$5500 X=$00ee Y=$5678 P=$20 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$00ee Y=$0078 P=$30 E=1 ($7f1234)=$00 + Note: This tests undocumented behavior - see the cputest README file for details +Test 04e1: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000201)=$00 +Test 04e2: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 ($000201)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($000201)=$00 +Test 04e3: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($000033)=$00 +Test 04e4: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($000033)=$00 +Test 04e5: sta [$34] + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7f1234)=$00 +Test 04e6: sta [$FF] + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04e7: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 04e8: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($7effff)=$00 +Test 04e9: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 04ea: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 ($7effff)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($7effff)=$00 +Test 04eb: sta ($34),y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 04ec: sta ($34),y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 04ed: sta ($FF),y + Input: A=$5500 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=1 ($7f1244)=$00 +Test 04ee: sta ($FE),y + Input: A=$5500 X=$3456 Y=$0010 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=1 ($7f1244)=$00 +Test 04ef: sta ($34) + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$20 E=0 ($7f1234)=$00 +Test 04f0: sta ($FF) + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04f1: sta ($FE) + Input: A=$5500 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$30 E=1 ($7f1234)=$00 +Test 04f2: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 04f3: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 04f4: sta ($12,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$20 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=1 ($7ffeec)=$00 +Test 04f5: sta $02,x + Input: A=$5500 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$5500 X=$0133 Y=$5678 P=$20 E=0 ($000134)=$00 +Test 04f6: sta $02,x + Input: A=$5500 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$30 E=0 ($000033)=$00 +Test 04f7: sta $02,x + Input: A=$5500 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$30 E=1 ($000033)=$00 +Test 04f8: sta $FF,x + Input: A=$5500 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$5500 X=$0034 Y=$0078 P=$30 E=1 ($000133)=$00 +Test 04f9: sta [$34],y + Input: A=$5500 X=$3456 Y=$1100 P=$20 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$20 E=0 ($7f0fdc)=$00 +Test 04fa: sta [$34],y + Input: A=$5500 X=$3456 Y=$1110 P=$30 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=0 ($7ffeec)=$00 +Test 04fb: sta [$FF],y + Input: A=$5500 X=$3456 Y=$0010 P=$20 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$30 E=1 ($7f1244)=$00 +Test 04fc: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$0300 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$3456 Y=$0300 P=$20 E=0 ($7f02ff)=$00 +Test 04fd: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$30 E=0 ($7f002f)=$00 +Test 04fe: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$20 E=1 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$30 E=1 ($7f002f)=$00 +Test 04ff: sta $FFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 0500: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 0501: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=1 ($7f002f)=$00 +Test 0502: sta $7EFFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 0503: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$30 E=0 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 0504: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$20 E=1 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$30 E=1 ($7f002f)=$00 +Test 0505: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$10 E=0 ($000033)=$00 +Test 0506: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$30 E=1 ($000033)=$00 +Test 0507: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$10 E=0 ($7effff)=$00 +Test 0508: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$10 E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$30 E=1 ($7effff)=$00 +Test 0509: stx $02,y + Input: A=$1234 X=$0000 Y=$1232 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$10 E=0 ($000033)=$00 +Test 050a: stx $02,y + Input: A=$1234 X=$0000 Y=$0032 P=$10 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$30 E=1 ($000033)=$00 +Test 050b: stx $FF,y + Input: A=$1234 X=$0000 Y=$0034 P=$10 E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$1234 X=$0000 Y=$0034 P=$30 E=1 ($000133)=$00 +Test 050c: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$10 E=0 ($000033)=$00 +Test 050d: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$30 E=1 ($000033)=$00 +Test 050e: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$10 E=0 ($7effff)=$00 +Test 050f: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$10 E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$30 E=1 ($7effff)=$00 +Test 0510: sty $02,x + Input: A=$1234 X=$1232 Y=$0000 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$10 E=0 ($000033)=$00 +Test 0511: sty $02,x + Input: A=$1234 X=$0032 Y=$0000 P=$10 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$30 E=1 ($000033)=$00 +Test 0512: sty $FF,x + Input: A=$1234 X=$0034 Y=$0000 P=$10 E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$1234 X=$0034 Y=$0000 P=$30 E=1 ($000133)=$00 +Test 0513: sta ($10,x) + Input: A=$5500 X=$ff91 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($7f1212)=$12 + Expected output: A=$5500 X=$ff91 Y=$5678 P=$ef E=0 ($7f1212)=$00 +Test 0514: sta ($90,x) + Input: A=$5500 X=$1210 Y=$5678 P=$ff E=0 DBR=$7f D=$ff00 ($7f1212)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$ff E=0 ($7f1212)=$00 +Test 0515: sta ($EF,x) + Input: A=$5500 X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 0516: sta ($F0,x) + Input: A=$5500 X=$0010 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0010 Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 0517: sta ($F6,x) + Input: A=$5500 X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$00ee Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 0518: sta ($F7,x) + Input: A=$5500 X=$00ee Y=$5678 P=$ef E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$00ee Y=$0078 P=$ff E=1 ($7f1234)=$00 + Note: This tests undocumented behavior - see the cputest README file for details +Test 0519: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000201)=$00 +Test 051a: sta $12,s + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 ($000201)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($000201)=$00 +Test 051b: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($000033)=$00 +Test 051c: sta $34 + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($000033)=$00 +Test 051d: sta [$34] + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7f1234)=$00 +Test 051e: sta [$FF] + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 051f: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 +Test 0520: sta $FFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($7effff)=$00 +Test 0521: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7effff)=$00 +Test 0522: sta $7EFFFF + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 ($7effff)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($7effff)=$00 +Test 0523: sta ($34),y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 0524: sta ($34),y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 0525: sta ($FF),y + Input: A=$5500 X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=1 ($7f1244)=$00 +Test 0526: sta ($FE),y + Input: A=$5500 X=$3456 Y=$0010 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=1 ($7f1244)=$00 +Test 0527: sta ($34) + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$3456 Y=$5678 P=$ef E=0 ($7f1234)=$00 +Test 0528: sta ($FF) + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 0529: sta ($FE) + Input: A=$5500 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$12 + Expected output: A=$5500 X=$0056 Y=$0078 P=$ff E=1 ($7f1234)=$00 +Test 052a: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 052b: sta ($10,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 052c: sta ($12,s),y + Input: A=$5500 X=$3456 Y=$1110 P=$ef E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=1 ($7ffeec)=$00 +Test 052d: sta $02,x + Input: A=$5500 X=$0133 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$5500 X=$0133 Y=$5678 P=$ef E=0 ($000134)=$00 +Test 052e: sta $02,x + Input: A=$5500 X=$1232 Y=$5678 P=$ff E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$ff E=0 ($000033)=$00 +Test 052f: sta $02,x + Input: A=$5500 X=$0032 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$5500 X=$0032 Y=$0078 P=$ff E=1 ($000033)=$00 +Test 0530: sta $FF,x + Input: A=$5500 X=$0034 Y=$5678 P=$ef E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$5500 X=$0034 Y=$0078 P=$ff E=1 ($000133)=$00 +Test 0531: sta [$34],y + Input: A=$5500 X=$3456 Y=$1100 P=$ef E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$12 + Expected output: A=$5500 X=$3456 Y=$1100 P=$ef E=0 ($7f0fdc)=$00 +Test 0532: sta [$34],y + Input: A=$5500 X=$3456 Y=$1110 P=$ff E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=0 ($7ffeec)=$00 +Test 0533: sta [$FF],y + Input: A=$5500 X=$3456 Y=$0010 P=$ef E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$12 + Expected output: A=$5500 X=$0056 Y=$0010 P=$ff E=1 ($7f1244)=$00 +Test 0534: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$0300 P=$ef E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$3456 Y=$0300 P=$ef E=0 ($7f02ff)=$00 +Test 0535: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$ff E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$ff E=0 ($7f002f)=$00 +Test 0536: sta $FFFF,y + Input: A=$5500 X=$3456 Y=$1230 P=$ef E=1 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0056 Y=$0030 P=$ff E=1 ($7f002f)=$00 +Test 0537: sta $FFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$ef E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 +Test 0538: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ff E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=0 ($7f002f)=$00 +Test 0539: sta $FFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ef E=1 DBR=$7e ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=1 ($7f002f)=$00 +Test 053a: sta $7EFFFF,x + Input: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$12 + Expected output: A=$5500 X=$0300 Y=$5678 P=$ef E=0 ($7f02ff)=$00 +Test 053b: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ff E=0 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=0 ($7f002f)=$00 +Test 053c: sta $7EFFFF,x + Input: A=$5500 X=$1230 Y=$5678 P=$ef E=1 ($7f002f)=$12 + Expected output: A=$5500 X=$0030 Y=$0078 P=$ff E=1 ($7f002f)=$00 +Test 053d: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$df E=0 ($000033)=$00 +Test 053e: stx $34 + Input: A=$1234 X=$0000 Y=$5678 P=$df E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$ff E=1 ($000033)=$00 +Test 053f: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$df E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$df E=0 ($7effff)=$00 +Test 0540: stx $FFFF + Input: A=$1234 X=$0000 Y=$5678 P=$df E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0000 Y=$0078 P=$ff E=1 ($7effff)=$00 +Test 0541: stx $02,y + Input: A=$1234 X=$0000 Y=$1232 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$df E=0 ($000033)=$00 +Test 0542: stx $02,y + Input: A=$1234 X=$0000 Y=$0032 P=$df E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0000 Y=$0032 P=$ff E=1 ($000033)=$00 +Test 0543: stx $FF,y + Input: A=$1234 X=$0000 Y=$0034 P=$df E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$1234 X=$0000 Y=$0034 P=$ff E=1 ($000133)=$00 +Test 0544: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$df E=0 ($000033)=$00 +Test 0545: sty $34 + Input: A=$1234 X=$3456 Y=$0000 P=$df E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$ff E=1 ($000033)=$00 +Test 0546: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$df E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$df E=0 ($7effff)=$00 +Test 0547: sty $FFFF + Input: A=$1234 X=$3456 Y=$0000 P=$df E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0000 P=$ff E=1 ($7effff)=$00 +Test 0548: sty $02,x + Input: A=$1234 X=$1232 Y=$0000 P=$df E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$df E=0 ($000033)=$00 +Test 0549: sty $02,x + Input: A=$1234 X=$0032 Y=$0000 P=$df E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0000 P=$ff E=1 ($000033)=$00 +Test 054a: sty $FF,x + Input: A=$1234 X=$0034 Y=$0000 P=$df E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$1234 X=$0034 Y=$0000 P=$ff E=1 ($000133)=$00 +Test 054b: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($000033)=$00 ($000034)=$00 +Test 054c: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$00 E=0 ($000134)=$00 ($000135)=$00 +Test 054d: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$10 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$10 E=0 ($000033)=$00 ($000034)=$00 +Test 054e: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 ($7effff)=$00 ($7f0000)=$00 +Test 054f: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$00 E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$00 E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0550: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$10 E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$10 E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0551: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($000033)=$00 ($000034)=$00 +Test 0552: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000134)=$34 ($000135)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$cf E=0 ($000134)=$00 ($000135)=$00 +Test 0553: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$df E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$df E=0 ($000033)=$00 ($000034)=$00 +Test 0554: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$cf E=0 ($7effff)=$00 ($7f0000)=$00 +Test 0555: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$cf E=0 DBR=$7e ($7f02ff)=$34 ($7f0300)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$cf E=0 ($7f02ff)=$00 ($7f0300)=$00 +Test 0556: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$df E=0 DBR=$7e ($7f002f)=$34 ($7f0030)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$df E=0 ($7f002f)=$00 ($7f0030)=$00 +Test 0557: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($000033)=$00 +Test 0558: stz $34 + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 ($000033)=$00 +Test 0559: stz $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000134)=$12 + Expected output: A=$1234 X=$0133 Y=$5678 P=$20 E=0 ($000134)=$00 +Test 055a: stz $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$30 E=0 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$30 E=0 ($000033)=$00 +Test 055b: stz $02,x + Input: A=$1234 X=$0032 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$12 + Expected output: A=$1234 X=$0032 Y=$0078 P=$30 E=1 ($000033)=$00 +Test 055c: stz $FF,x + Input: A=$1234 X=$0034 Y=$5678 P=$20 E=1 DBR=$7f D=$0100 ($000133)=$12 + Expected output: A=$1234 X=$0034 Y=$0078 P=$30 E=1 ($000133)=$00 +Test 055d: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$3456 Y=$5678 P=$20 E=0 ($7effff)=$00 +Test 055e: stz $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$12 + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 ($7effff)=$00 +Test 055f: stz $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$20 E=0 DBR=$7e ($7f02ff)=$12 + Expected output: A=$1234 X=$0300 Y=$5678 P=$20 E=0 ($7f02ff)=$00 +Test 0560: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$30 E=0 DBR=$7e ($7f002f)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$30 E=0 ($7f002f)=$00 +Test 0561: stz $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$20 E=1 DBR=$7e ($7f002f)=$12 + Expected output: A=$1234 X=$0030 Y=$0078 P=$30 E=1 ($7f002f)=$00 +Test 0562: trb $34 + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$04 ($000034)=$80 +Test 0563: trb $FFFF + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$04 ($7f0000)=$80 +Test 0564: trb $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$aa ($000034)=$aa +Test 0565: trb $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$aa ($7f0000)=$aa +Test 0566: trb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$80 +Test 0567: trb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$0056 Y=$0078 P=$fd E=1 ($000033)=$80 +Test 0568: trb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$80 +Test 0569: trb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$0056 Y=$0078 P=$fd E=1 ($7effff)=$80 +Test 056a: trb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$aa +Test 056b: trb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$32 E=1 ($000033)=$aa +Test 056c: trb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$aa +Test 056d: trb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$32 E=1 ($7effff)=$aa +Test 056e: tsb $34 + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($000033)=$34 ($000034)=$96 +Test 056f: tsb $FFFF + Input: A=$1630 X=$3456 Y=$5678 P=$cf E=0 DBR=$7e ($7effff)=$34 ($7f0000)=$92 + Expected output: A=$1630 X=$3456 Y=$5678 P=$cd E=0 ($7effff)=$34 ($7f0000)=$96 +Test 0570: tsb $34 + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7f D=$ffff ($000033)=$aa ($000034)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($000033)=$ff ($000034)=$ff +Test 0571: tsb $FFFF + Input: A=$5555 X=$3456 Y=$5678 P=$00 E=0 DBR=$7e ($7effff)=$aa ($7f0000)=$aa + Expected output: A=$5555 X=$3456 Y=$5678 P=$02 E=0 ($7effff)=$ff ($7f0000)=$ff +Test 0572: tsb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($000033)=$96 +Test 0573: tsb $34 + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=1 DBR=$7f D=$ffff ($000033)=$92 + Expected output: A=$0016 X=$0056 Y=$0078 P=$fd E=1 ($000033)=$96 +Test 0574: tsb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=0 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$3456 Y=$5678 P=$ed E=0 ($7effff)=$96 +Test 0575: tsb $FFFF + Input: A=$0016 X=$3456 Y=$5678 P=$ef E=1 DBR=$7e ($7effff)=$92 + Expected output: A=$0016 X=$0056 Y=$0078 P=$fd E=1 ($7effff)=$96 +Test 0576: tsb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($000033)=$ff +Test 0577: tsb $34 + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7f D=$ffff ($000033)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$32 E=1 ($000033)=$ff +Test 0578: tsb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=0 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$3456 Y=$5678 P=$22 E=0 ($7effff)=$ff +Test 0579: tsb $FFFF + Input: A=$0055 X=$3456 Y=$5678 P=$20 E=1 DBR=$7e ($7effff)=$aa + Expected output: A=$0055 X=$0056 Y=$0078 P=$32 E=1 ($7effff)=$ff +Test 057a: tax + Input: A=$8765 X=$5678 Y=$5678 P=$00 E=0 + Expected output: A=$8765 X=$8765 Y=$5678 P=$80 E=0 +Test 057b: tax + Input: A=$0000 X=$5678 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$0000 Y=$5678 P=$02 E=0 +Test 057c: tax + Input: A=$1234 X=$5678 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$1234 Y=$5678 P=$6d E=0 +Test 057d: tax + Input: A=$87ab X=$5678 Y=$5678 P=$10 E=0 + Expected output: A=$87ab X=$00ab Y=$0078 P=$90 E=0 +Test 057e: tay + Input: A=$8765 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$8765 X=$3456 Y=$8765 P=$80 E=0 +Test 057f: tay + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$0000 P=$02 E=0 +Test 0580: tay + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$3456 Y=$1234 P=$6d E=0 +Test 0581: tay + Input: A=$87ab X=$3456 Y=$5678 P=$10 E=0 + Expected output: A=$87ab X=$0056 Y=$00ab P=$90 E=0 +Test 0582: txa + Input: A=$1234 X=$9876 Y=$5678 P=$00 E=0 + Expected output: A=$9876 X=$9876 Y=$5678 P=$80 E=0 +Test 0583: txa + Input: A=$1234 X=$0000 Y=$5678 P=$00 E=0 + Expected output: A=$0000 X=$0000 Y=$5678 P=$02 E=0 +Test 0584: txa + Input: A=$1234 X=$00cd Y=$5678 P=$df E=0 + Expected output: A=$00cd X=$00cd Y=$0078 P=$5d E=0 +Test 0585: txa + Input: A=$1234 X=$abcd Y=$5678 P=$20 E=0 + Expected output: A=$12cd X=$abcd Y=$5678 P=$a0 E=0 +Test 0586: txa + Input: A=$1234 X=$ab00 Y=$5678 P=$20 E=0 + Expected output: A=$1200 X=$ab00 Y=$5678 P=$22 E=0 +Test 0587: tya + Input: A=$1234 X=$3456 Y=$9876 P=$00 E=0 + Expected output: A=$9876 X=$3456 Y=$9876 P=$80 E=0 +Test 0588: tya + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 + Expected output: A=$0000 X=$3456 Y=$0000 P=$02 E=0 +Test 0589: tya + Input: A=$1234 X=$3456 Y=$00cd P=$df E=0 + Expected output: A=$00cd X=$0056 Y=$00cd P=$5d E=0 +Test 058a: tya + Input: A=$1234 X=$3456 Y=$abcd P=$20 E=0 + Expected output: A=$12cd X=$3456 Y=$abcd P=$a0 E=0 +Test 058b: tya + Input: A=$1234 X=$3456 Y=$ab00 P=$20 E=0 + Expected output: A=$1200 X=$3456 Y=$ab00 P=$22 E=0 +Test 058c: txy + Input: A=$1234 X=$8765 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$8765 Y=$8765 P=$80 E=0 +Test 058d: txy + Input: A=$1234 X=$0000 Y=$5678 P=$ed E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$6f E=0 +Test 058e: txy + Input: A=$1234 X=$0098 Y=$0000 P=$10 E=0 + Expected output: A=$1234 X=$0098 Y=$0098 P=$90 E=0 +Test 058f: txy + Input: A=$1234 X=$0000 Y=$0098 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$12 E=0 +Test 0590: tyx + Input: A=$1234 X=$5678 Y=$8765 P=$00 E=0 + Expected output: A=$1234 X=$8765 Y=$8765 P=$80 E=0 +Test 0591: tyx + Input: A=$1234 X=$5678 Y=$0000 P=$ed E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$6f E=0 +Test 0592: tyx + Input: A=$1234 X=$0000 Y=$0098 P=$10 E=0 + Expected output: A=$1234 X=$0098 Y=$0098 P=$90 E=0 +Test 0593: tyx + Input: A=$1234 X=$0098 Y=$0000 P=$10 E=0 + Expected output: A=$1234 X=$0000 Y=$0000 P=$12 E=0 +Test 0594: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$01ef Y=$5678 P=$6d E=0 +Test 0595: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 S=$0200 + Expected output: A=$1234 X=$0000 Y=$0078 P=$12 E=0 S=0200 +Test 0596: tsx + Input: A=$1234 X=$3456 Y=$5678 P=$10 E=0 + Expected output: A=$1234 X=$00ef Y=$0078 P=$90 E=0 +Test 0597: tsc + Input: A=$1234 X=$3456 Y=$5678 P=$df E=0 + Expected output: A=$01ef X=$0056 Y=$0078 P=$5d E=0 +Test 0598: tsc + Input: A=$1234 X=$3456 Y=$5678 P=$20 E=0 S=$0200 + Expected output: A=$0200 X=$3456 Y=$5678 P=$20 E=0 S=0200 +Test 0599: tsc + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 S=$0000 + Expected output: A=$0000 X=$01ef Y=$0001 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 059a: tsc + Input: A=$1234 X=$3456 Y=$0000 P=$00 E=0 S=$8000 + Expected output: A=$8000 X=$01ef Y=$0001 P=$00 E=0 + Additional initialization or checks are performed - see assembly +Test 059b: txs + Input: A=$1234 X=$0200 Y=$5678 P=$ef E=0 + Expected output: A=$1234 X=$0200 Y=$5678 P=$ef E=0 S=0200 +Test 059c: txs + Input: A=$1234 X=$00ff Y=$5678 P=$30 E=1 + Expected output: A=$1234 X=$00ff Y=$0078 P=$30 E=1 S=01ff +Test 059d: tcs + Input: A=$0200 X=$3456 Y=$5678 P=$ef E=0 + Expected output: A=$0200 X=$3456 Y=$5678 P=$ef E=0 S=0200 +Test 059e: tcs + Input: A=$77ff X=$3456 Y=$5678 P=$30 E=1 + Expected output: A=$77ff X=$0056 Y=$0078 P=$30 E=1 S=01ff +Test 059f: tcd + Input: A=$0000 X=$3456 Y=$5678 P=$00 E=0 D=$1234 + Expected output: A=$0000 X=$3456 Y=$5678 P=$02 E=0 D=0000 +Test 05a0: tcd + Input: A=$9876 X=$3456 Y=$5678 P=$6f E=0 + Expected output: A=$9876 X=$3456 Y=$5678 P=$ed E=0 D=9876 +Test 05a1: tcd + Input: A=$9876 X=$3456 Y=$5678 P=$30 E=1 + Expected output: A=$9876 X=$0056 Y=$0078 P=$b0 E=1 D=9876 +Test 05a2: tdc + Input: A=$0000 X=$3456 Y=$5678 P=$20 E=0 D=$9876 + Expected output: A=$9876 X=$3456 Y=$5678 P=$a0 E=0 +Test 05a3: tdc + Input: A=$1234 X=$3456 Y=$5678 P=$dd E=0 D=$0000 + Expected output: A=$0000 X=$0056 Y=$0078 P=$5f E=0 +Test 05a4: xba + Input: A=$9812 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1298 X=$3456 Y=$5678 P=$80 E=0 +Test 05a5: xba + Input: A=$00aa X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$aa00 X=$3456 Y=$5678 P=$02 E=0 +Test 05a6: xba + Input: A=$9812 X=$3456 Y=$5678 P=$ff E=1 + Expected output: A=$1298 X=$0056 Y=$0078 P=$fd E=1 +Test 05a7: xce + Input: A=$1234 X=$3456 Y=$5678 P=$00 E=0 + Expected output: A=$1234 X=$3456 Y=$5678 P=$00 E=0 +Test 05a8: xce + Input: A=$1234 X=$3456 Y=$5678 P=$fe E=0 + Expected output: A=$1234 X=$0056 Y=$0078 P=$fe E=0 +Test 05a9: xce + Input: A=$1234 X=$1234 Y=$4567 P=$01 E=0 + Expected output: A=$1234 X=$0034 Y=$0067 P=$30 E=1 +Test 05aa: xce + Input: A=$1234 X=$3456 Y=$5678 P=$30 E=1 + Expected output: A=$1234 X=$0056 Y=$0078 P=$31 E=0 +Test 05ab: xce + Input: A=$1234 X=$3456 Y=$5678 P=$01 E=0 S=$03ff + Expected output: A=$1234 X=$0056 Y=$0078 P=$30 E=1 S=01ff +Test 05ac: adc #$8765 + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 +Test 05ad: adc ($10,x) + Input: A=$1234 X=$ff91 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($7f1212)=$65 ($7f1213)=$87 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$0b E=0 ($7f1212)=$65 ($7f1213)=$87 +Test 05ae: adc ($10,x) + Input: A=$1234 X=$0123 Y=$5678 P=$09 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$0123 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05af: adc ($90,x) + Input: A=$1234 X=$1210 Y=$5678 P=$19 E=0 DBR=$7f D=$ff00 ($7f1212)=$65 ($7f1213)=$87 + Expected output: A=$0000 X=$0010 Y=$0078 P=$1b E=0 ($7f1212)=$65 ($7f1213)=$87 +Test 05b0: adc $12,s + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 ($000201)=$65 ($000202)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000201)=$65 ($000202)=$87 +Test 05b1: adc $34 + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000033)=$65 ($000034)=$87 +Test 05b2: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$65 ($7f1235)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$65 ($7f1235)=$87 +Test 05b3: adc [$34] + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05b4: adc $FFFF + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7e ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05b5: adc $7EFFFF + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05b6: adc ($34),y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 05b7: adc ($34),y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 05b8: adc ($34),y + Input: A=$1234 X=$3456 Y=$1111 P=$09 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05b9: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$65 ($7f1235)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$65 ($7f1235)=$87 +Test 05ba: adc ($34) + Input: A=$1234 X=$3456 Y=$5678 P=$09 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05bb: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 05bc: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 05bd: adc ($10,s),y + Input: A=$1234 X=$3456 Y=$1111 P=$09 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05be: adc $02,x + Input: A=$1234 X=$0133 Y=$5678 P=$09 E=0 DBR=$7f D=$ffff ($000134)=$65 ($000135)=$87 + Expected output: A=$0000 X=$0133 Y=$5678 P=$0b E=0 ($000134)=$65 ($000135)=$87 +Test 05bf: adc $02,x + Input: A=$1234 X=$1232 Y=$5678 P=$19 E=0 DBR=$7f D=$ffff ($000033)=$65 ($000034)=$87 + Expected output: A=$0000 X=$0032 Y=$0078 P=$1b E=0 ($000033)=$65 ($000034)=$87 +Test 05c0: adc [$34],y + Input: A=$1234 X=$3456 Y=$1100 P=$09 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$65 ($7f0fdd)=$87 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$65 ($7f0fdd)=$87 +Test 05c1: adc [$34],y + Input: A=$1234 X=$3456 Y=$1110 P=$19 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$65 ($7ffeed)=$87 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$65 ($7ffeed)=$87 +Test 05c2: adc [$34],y + Input: A=$1234 X=$3456 Y=$1111 P=$09 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$65 ($7f0000)=$87 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$65 ($7f0000)=$87 +Test 05c3: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$0300 P=$09 E=0 DBR=$7e ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$3456 Y=$0300 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 05c4: adc $FFFF,y + Input: A=$1234 X=$3456 Y=$1230 P=$19 E=0 DBR=$7e ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0056 Y=$0030 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 05c5: adc $FFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$09 E=0 DBR=$7e ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 05c6: adc $FFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$19 E=0 DBR=$7e ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 05c7: adc $7EFFFF,x + Input: A=$1234 X=$0300 Y=$5678 P=$09 E=0 ($7f02ff)=$65 ($7f0300)=$87 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$65 ($7f0300)=$87 +Test 05c8: adc $7EFFFF,x + Input: A=$1234 X=$1230 Y=$5678 P=$19 E=0 ($7f002f)=$65 ($7f0030)=$87 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$65 ($7f0030)=$87 +Test 05c9: adc #$4470 + Input: A=$3550 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$8020 X=$3456 Y=$5678 P=$c8 E=0 +Test 05ca: adc #$3999 + Input: A=$4000 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$7999 X=$3456 Y=$5678 P=$08 E=0 +Test 05cb: adc #$dbca + Input: A=$dcba X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$1eea X=$3456 Y=$5678 P=$09 E=0 +Test 05cc: adc #$87 + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 +Test 05cd: adc ($10,x) + Input: A=$cc12 X=$ff91 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($7f1212)=$87 + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$2b E=0 ($7f1212)=$87 +Test 05ce: adc ($90,x) + Input: A=$cc12 X=$1210 Y=$5678 P=$39 E=0 DBR=$7f D=$ff00 ($7f1212)=$87 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=0 ($7f1212)=$87 +Test 05cf: adc ($EF,x) + Input: A=$cc12 X=$0010 Y=$5678 P=$29 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05d0: adc ($F0,x) + Input: A=$cc12 X=$0010 Y=$5678 P=$29 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05d1: adc ($F6,x) + Input: A=$cc12 X=$00ee Y=$5678 P=$29 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$00ee Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05d2: adc ($F7,x) + Input: A=$cc12 X=$00ee Y=$5678 P=$29 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$00ee Y=$0078 P=$3b E=1 ($7f1234)=$87 + Note: This tests undocumented behavior - see the cputest README file for details +Test 05d3: adc $12,s + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 ($000201)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000201)=$87 +Test 05d4: adc $12,s + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 ($000201)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($000201)=$87 +Test 05d5: adc $34 + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000033)=$87 +Test 05d6: adc $34 + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($000033)=$87 +Test 05d7: adc [$34] + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$87 +Test 05d8: adc [$FF] + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05d9: adc $FFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7e ($7effff)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$87 +Test 05da: adc $FFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 DBR=$7e ($7effff)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7effff)=$87 +Test 05db: adc $7EFFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 ($7effff)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$87 +Test 05dc: adc $7EFFFF + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 ($7effff)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7effff)=$87 +Test 05dd: adc ($34),y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 05de: adc ($34),y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 05df: adc ($FF),y + Input: A=$cc12 X=$3456 Y=$0010 P=$29 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$87 +Test 05e0: adc ($FE),y + Input: A=$cc12 X=$3456 Y=$0010 P=$29 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$87 +Test 05e1: adc ($34) + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$87 +Test 05e2: adc ($FF) + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05e3: adc ($FE) + Input: A=$cc12 X=$3456 Y=$5678 P=$29 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$87 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$87 +Test 05e4: adc ($10,s),y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 05e5: adc ($10,s),y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 05e6: adc ($12,s),y + Input: A=$cc12 X=$3456 Y=$1110 P=$29 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7ffeec)=$87 +Test 05e7: adc $02,x + Input: A=$cc12 X=$0133 Y=$5678 P=$29 E=0 DBR=$7f D=$ffff ($000134)=$87 + Expected output: A=$cc00 X=$0133 Y=$5678 P=$2b E=0 ($000134)=$87 +Test 05e8: adc $02,x + Input: A=$cc12 X=$1232 Y=$5678 P=$39 E=0 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=0 ($000033)=$87 +Test 05e9: adc $02,x + Input: A=$cc12 X=$0032 Y=$5678 P=$29 E=1 DBR=$7f D=$ffff ($000033)=$87 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=1 ($000033)=$87 +Test 05ea: adc $FF,x + Input: A=$cc12 X=$0034 Y=$5678 P=$29 E=1 DBR=$7f D=$0100 ($000133)=$87 + Expected output: A=$cc00 X=$0034 Y=$0078 P=$3b E=1 ($000133)=$87 +Test 05eb: adc [$34],y + Input: A=$cc12 X=$3456 Y=$1100 P=$29 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$87 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$87 +Test 05ec: adc [$34],y + Input: A=$cc12 X=$3456 Y=$1110 P=$39 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$87 +Test 05ed: adc [$FF],y + Input: A=$cc12 X=$3456 Y=$0010 P=$29 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$87 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$87 +Test 05ee: adc $FFFF,y + Input: A=$cc12 X=$3456 Y=$0300 P=$29 E=0 DBR=$7e ($7f02ff)=$87 + Expected output: A=$cc00 X=$3456 Y=$0300 P=$2b E=0 ($7f02ff)=$87 +Test 05ef: adc $FFFF,y + Input: A=$cc12 X=$3456 Y=$1230 P=$39 E=0 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=0 ($7f002f)=$87 +Test 05f0: adc $FFFF,y + Input: A=$cc12 X=$3456 Y=$1230 P=$29 E=1 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=1 ($7f002f)=$87 +Test 05f1: adc $FFFF,x + Input: A=$cc12 X=$0300 Y=$5678 P=$29 E=0 DBR=$7e ($7f02ff)=$87 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$87 +Test 05f2: adc $FFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$39 E=0 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$87 +Test 05f3: adc $FFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$29 E=1 DBR=$7e ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=1 ($7f002f)=$87 +Test 05f4: adc $7EFFFF,x + Input: A=$cc12 X=$0300 Y=$5678 P=$29 E=0 ($7f02ff)=$87 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$87 +Test 05f5: adc $7EFFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$39 E=0 ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$87 +Test 05f6: adc $7EFFFF,x + Input: A=$cc12 X=$1230 Y=$5678 P=$29 E=1 ($7f002f)=$87 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=1 ($7f002f)=$87 +Test 05f7: adc #$40 + Input: A=$cc40 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc80 X=$3456 Y=$5678 P=$e8 E=0 +Test 05f8: adc #$39 + Input: A=$cc40 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc79 X=$3456 Y=$5678 P=$28 E=0 +Test 05f9: adc #$db + Input: A=$ccdc X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc1d X=$3456 Y=$5678 P=$29 E=0 +Test 05fa: sbc #$9089 + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 +Test 05fb: sbc ($10,x) + Input: A=$9090 X=$ff91 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($7f1212)=$89 ($7f1213)=$90 + Expected output: A=$0000 X=$ff91 Y=$5678 P=$0b E=0 ($7f1212)=$89 ($7f1213)=$90 +Test 05fc: sbc ($10,x) + Input: A=$9090 X=$0123 Y=$5678 P=$08 E=0 DBR=$7e D=$ff00 ($000033)=$ff ($000034)=$ff ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$0123 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 05fd: sbc ($90,x) + Input: A=$9090 X=$1210 Y=$5678 P=$18 E=0 DBR=$7f D=$ff00 ($7f1212)=$89 ($7f1213)=$90 + Expected output: A=$0000 X=$0010 Y=$0078 P=$1b E=0 ($7f1212)=$89 ($7f1213)=$90 +Test 05fe: sbc $12,s + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 ($000201)=$89 ($000202)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000201)=$89 ($000202)=$90 +Test 05ff: sbc $34 + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000033)=$89 ($000034)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($000033)=$89 ($000034)=$90 +Test 0600: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$89 ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$89 ($7f1235)=$90 +Test 0601: sbc [$34] + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 D=$ffff ($000033)=$ff ($000034)=$ff ($000035)=$7e ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0602: sbc $FFFF + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7e ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0603: sbc $7EFFFF + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0604: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 0605: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 0606: sbc ($34),y + Input: A=$9090 X=$3456 Y=$1111 P=$08 E=0 DBR=$7e D=$ffff ($000033)=$ee ($000034)=$ee ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0607: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$89 ($7f1235)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7f1234)=$89 ($7f1235)=$90 +Test 0608: sbc ($34) + Input: A=$9090 X=$3456 Y=$5678 P=$08 E=0 DBR=$7e D=$ffff ($000033)=$ff ($000034)=$ff ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$5678 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0609: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 060a: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 060b: sbc ($10,s),y + Input: A=$9090 X=$3456 Y=$1111 P=$08 E=0 DBR=$7e ($0001ff)=$ee ($000200)=$ee ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 060c: sbc $02,x + Input: A=$9090 X=$0133 Y=$5678 P=$08 E=0 DBR=$7f D=$ffff ($000134)=$89 ($000135)=$90 + Expected output: A=$0000 X=$0133 Y=$5678 P=$0b E=0 ($000134)=$89 ($000135)=$90 +Test 060d: sbc $02,x + Input: A=$9090 X=$1232 Y=$5678 P=$18 E=0 DBR=$7f D=$ffff ($000033)=$89 ($000034)=$90 + Expected output: A=$0000 X=$0032 Y=$0078 P=$1b E=0 ($000033)=$89 ($000034)=$90 +Test 060e: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1100 P=$08 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$89 ($7f0fdd)=$90 + Expected output: A=$0000 X=$3456 Y=$1100 P=$0b E=0 ($7f0fdc)=$89 ($7f0fdd)=$90 +Test 060f: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1110 P=$18 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$89 ($7ffeed)=$90 + Expected output: A=$0000 X=$0056 Y=$0010 P=$1b E=0 ($7ffeec)=$89 ($7ffeed)=$90 +Test 0610: sbc [$34],y + Input: A=$9090 X=$3456 Y=$1111 P=$08 E=0 D=$ffff ($000033)=$ee ($000034)=$ee ($000035)=$7e ($7effff)=$89 ($7f0000)=$90 + Expected output: A=$0000 X=$3456 Y=$1111 P=$0b E=0 ($7effff)=$89 ($7f0000)=$90 +Test 0611: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$0300 P=$08 E=0 DBR=$7e ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$3456 Y=$0300 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0612: sbc $FFFF,y + Input: A=$9090 X=$3456 Y=$1230 P=$18 E=0 DBR=$7e ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0056 Y=$0030 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0613: sbc $FFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$08 E=0 DBR=$7e ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0614: sbc $FFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$18 E=0 DBR=$7e ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0615: sbc $7EFFFF,x + Input: A=$9090 X=$0300 Y=$5678 P=$08 E=0 ($7f02ff)=$89 ($7f0300)=$90 + Expected output: A=$0000 X=$0300 Y=$5678 P=$0b E=0 ($7f02ff)=$89 ($7f0300)=$90 +Test 0616: sbc $7EFFFF,x + Input: A=$9090 X=$1230 Y=$5678 P=$18 E=0 ($7f002f)=$89 ($7f0030)=$90 + Expected output: A=$0000 X=$0030 Y=$0078 P=$1b E=0 ($7f002f)=$89 ($7f0030)=$90 +Test 0617: sbc #$01 + Input: A=$0000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$9999 X=$3456 Y=$5678 P=$88 E=0 +Test 0618: sbc #$9000 + Input: A=$1000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$2000 X=$3456 Y=$5678 P=$48 E=0 +Test 0619: sbc #$9001 + Input: A=$1000 X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$1999 X=$3456 Y=$5678 P=$08 E=0 +Test 061a: sbc #$f1e2 + Input: A=$ab1d X=$3456 Y=$5678 P=$09 E=0 + Expected output: A=$59db X=$3456 Y=$5678 P=$08 E=0 +Test 061b: sbc #$89 + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 +Test 061c: sbc ($10,x) + Input: A=$cc90 X=$ff91 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($7f1212)=$89 + Expected output: A=$cc00 X=$ff91 Y=$5678 P=$2b E=0 ($7f1212)=$89 +Test 061d: sbc ($90,x) + Input: A=$cc90 X=$1210 Y=$5678 P=$38 E=0 DBR=$7f D=$ff00 ($7f1212)=$89 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=0 ($7f1212)=$89 +Test 061e: sbc ($EF,x) + Input: A=$cc90 X=$0010 Y=$5678 P=$28 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 061f: sbc ($F0,x) + Input: A=$cc90 X=$0010 Y=$5678 P=$28 E=1 DBR=$7f D=$0100 ($000100)=$34 ($000101)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$0010 Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 0620: sbc ($F6,x) + Input: A=$cc90 X=$00ee Y=$5678 P=$28 E=1 DBR=$7f D=$011a ($0002fe)=$34 ($0002ff)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$00ee Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 0621: sbc ($F7,x) + Input: A=$cc90 X=$00ee Y=$5678 P=$28 E=1 DBR=$7f D=$011a ($0002ff)=$34 ($000200)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$00ee Y=$0078 P=$3b E=1 ($7f1234)=$89 + Note: This tests undocumented behavior - see the cputest README file for details +Test 0622: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 ($000201)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000201)=$89 +Test 0623: sbc $12,s + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 ($000201)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($000201)=$89 +Test 0624: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($000033)=$89 +Test 0625: sbc $34 + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($000033)=$89 +Test 0626: sbc [$34] + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 D=$ffff ($000033)=$34 ($000034)=$12 ($000035)=$7f ($7f1234)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$89 +Test 0627: sbc [$FF] + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1234)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 0628: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7e ($7effff)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$89 +Test 0629: sbc $FFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 DBR=$7e ($7effff)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7effff)=$89 +Test 062a: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 ($7effff)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7effff)=$89 +Test 062b: sbc $7EFFFF + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 ($7effff)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7effff)=$89 +Test 062c: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 DBR=$7e D=$ffff ($000033)=$dc ($000034)=$fe ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 062d: sbc ($34),y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 DBR=$7f D=$ffff ($000033)=$dc ($000034)=$fe ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 062e: sbc ($FF),y + Input: A=$cc90 X=$3456 Y=$0010 P=$28 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1244)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$89 +Test 062f: sbc ($FE),y + Input: A=$cc90 X=$3456 Y=$0010 P=$28 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1244)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$89 +Test 0630: sbc ($34) + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000033)=$34 ($000034)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$3456 Y=$5678 P=$2b E=0 ($7f1234)=$89 +Test 0631: sbc ($FF) + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 DBR=$7f D=$0100 ($0001ff)=$34 ($000100)=$12 ($7f1234)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 0632: sbc ($FE) + Input: A=$cc90 X=$3456 Y=$5678 P=$28 E=1 DBR=$7f D=$0101 ($0001ff)=$34 ($000200)=$12 ($000100)=$00 ($7f1234)=$89 + Expected output: A=$cc00 X=$0056 Y=$0078 P=$3b E=1 ($7f1234)=$89 +Test 0633: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 DBR=$7e ($0001ff)=$dc ($000200)=$fe ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 0634: sbc ($10,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 DBR=$7f ($0001ff)=$dc ($000200)=$fe ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 0635: sbc ($12,s),y + Input: A=$cc90 X=$3456 Y=$1110 P=$28 E=1 DBR=$7f ($000201)=$dc ($000202)=$fe ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7ffeec)=$89 +Test 0636: sbc $02,x + Input: A=$cc90 X=$0133 Y=$5678 P=$28 E=0 DBR=$7f D=$ffff ($000134)=$89 + Expected output: A=$cc00 X=$0133 Y=$5678 P=$2b E=0 ($000134)=$89 +Test 0637: sbc $02,x + Input: A=$cc90 X=$1232 Y=$5678 P=$38 E=0 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=0 ($000033)=$89 +Test 0638: sbc $02,x + Input: A=$cc90 X=$0032 Y=$5678 P=$28 E=1 DBR=$7f D=$ffff ($000033)=$89 + Expected output: A=$cc00 X=$0032 Y=$0078 P=$3b E=1 ($000033)=$89 +Test 0639: sbc $FF,x + Input: A=$cc90 X=$0034 Y=$5678 P=$28 E=1 DBR=$7f D=$0100 ($000133)=$89 + Expected output: A=$cc00 X=$0034 Y=$0078 P=$3b E=1 ($000133)=$89 +Test 063a: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1100 P=$28 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7e ($7f0fdc)=$89 + Expected output: A=$cc00 X=$3456 Y=$1100 P=$2b E=0 ($7f0fdc)=$89 +Test 063b: sbc [$34],y + Input: A=$cc90 X=$3456 Y=$1110 P=$38 E=0 D=$ffff ($000033)=$dc ($000034)=$fe ($000035)=$7f ($7ffeec)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=0 ($7ffeec)=$89 +Test 063c: sbc [$FF],y + Input: A=$cc90 X=$3456 Y=$0010 P=$28 E=1 D=$0100 ($0001ff)=$34 ($000200)=$12 ($000201)=$7f ($7f1244)=$89 + Expected output: A=$cc00 X=$0056 Y=$0010 P=$3b E=1 ($7f1244)=$89 +Test 063d: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$0300 P=$28 E=0 DBR=$7e ($7f02ff)=$89 + Expected output: A=$cc00 X=$3456 Y=$0300 P=$2b E=0 ($7f02ff)=$89 +Test 063e: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$38 E=0 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=0 ($7f002f)=$89 +Test 063f: sbc $FFFF,y + Input: A=$cc90 X=$3456 Y=$1230 P=$28 E=1 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0056 Y=$0030 P=$3b E=1 ($7f002f)=$89 +Test 0640: sbc $FFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$28 E=0 DBR=$7e ($7f02ff)=$89 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$89 +Test 0641: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$38 E=0 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$89 +Test 0642: sbc $FFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$28 E=1 DBR=$7e ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=1 ($7f002f)=$89 +Test 0643: sbc $7EFFFF,x + Input: A=$cc90 X=$0300 Y=$5678 P=$28 E=0 ($7f02ff)=$89 + Expected output: A=$cc00 X=$0300 Y=$5678 P=$2b E=0 ($7f02ff)=$89 +Test 0644: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$38 E=0 ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=0 ($7f002f)=$89 +Test 0645: sbc $7EFFFF,x + Input: A=$cc90 X=$1230 Y=$5678 P=$28 E=1 ($7f002f)=$89 + Expected output: A=$cc00 X=$0030 Y=$0078 P=$3b E=1 ($7f002f)=$89 +Test 0646: sbc #$01 + Input: A=$cc00 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc99 X=$3456 Y=$5678 P=$a8 E=0 +Test 0647: sbc #$90 + Input: A=$cc10 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc20 X=$3456 Y=$5678 P=$68 E=0 +Test 0648: sbc #$91 + Input: A=$cc10 X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc19 X=$3456 Y=$5678 P=$28 E=0 +Test 0649: sbc #$f1 + Input: A=$ccab X=$3456 Y=$5678 P=$29 E=0 + Expected output: A=$cc5a X=$3456 Y=$5678 P=$28 E=0 diff --git a/roms/snes-tests/cputest/tests_table.inc b/roms/snes-tests/cputest/tests_table.inc new file mode 100644 index 00000000..6ef9953b --- /dev/null +++ b/roms/snes-tests/cputest/tests_table.inc @@ -0,0 +1,1107 @@ +.faraddr test0000 +.faraddr test0001 +.faraddr test0002 +.faraddr test0003 +.faraddr test0004 +.faraddr test0005 +.faraddr test0006 +.faraddr test0007 +.faraddr test0008 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file mode 100644 index 00000000..69720db2 --- /dev/null +++ b/roms/snes-tests/spctest/.gitignore @@ -0,0 +1,3 @@ +spc_tests*.asm +*.spc +tests.txt diff --git a/roms/snes-tests/spctest/Makefile b/roms/snes-tests/spctest/Makefile new file mode 100644 index 00000000..4f9a6dc7 --- /dev/null +++ b/roms/snes-tests/spctest/Makefile @@ -0,0 +1,19 @@ +TEST_ASMS = spc_tests0.asm spc_tests1.asm spc_tests2.asm +TEST_SPCS = $(patsubst %.asm,%.spc,$(TEST_ASMS)) + +all: spctest.sfc + +%.spc: %.asm spc_common.inc + spcasm -f plain $< $@ + +spctest.o: spctest.asm $(TEST_SPCS) font.bin + ca65 spctest.asm -o spctest.o + +$(TEST_ASMS) tests.txt: make_tests.py + python3 make_tests.py + +spctest.sfc: spctest.o lorom128.cfg + ld65 -C lorom128.cfg -o spctest.sfc spctest.o + +clean: + rm -f spctest.o spctest.spc $(TEST_ASMS) diff --git a/roms/snes-tests/spctest/README.md b/roms/snes-tests/spctest/README.md new file mode 100644 index 00000000..187f5d0a --- /dev/null +++ b/roms/snes-tests/spctest/README.md @@ -0,0 +1,32 @@ +# SPC-700 test ROM + +This is an SNES ROM that performs comprehensive testing of the SPC-700 instruction set. + +If a test fails, see the autogenerated tests.txt or spc_tests*.asm files for details about the test. + +### The ROM tests the following + +- All SPC-700 opcodes except SLEEP and STOP +- Each instruction is tested in all supported addressing modes +- Multiple tests per instruction, designed to test edge cases and correct flag result +- Behavior with and without P=1 flag + +### The ROM does *not* test + +- Cycle count taken by instructions, or other timing-related behavior +- Dummy reads +- S-SMP memory-mapped registers (e.g. timers) +- DSP + +## Building + +Required tools are ca65/ld65, [spcasm](https://github.com/kleinesfilmroellchen/spcasm), and Python 3. + +Either use the Makefile by running `make`, or run: + + python3 make_tests.py + spcasm -f plain spc_tests0.asm spc_tests0.spc + spcasm -f plain spc_tests1.asm spc_tests1.spc + spcasm -f plain spc_tests2.asm spc_tests2.spc + ca65 spctest.asm -o spctest.o + ld65 -C lorom128.cfg -o spctest.sfc spctest.o diff --git a/roms/snes-tests/spctest/font.bin b/roms/snes-tests/spctest/font.bin new file mode 100644 index 00000000..05af94b8 Binary files /dev/null and b/roms/snes-tests/spctest/font.bin differ diff --git a/roms/snes-tests/spctest/lorom128.cfg b/roms/snes-tests/spctest/lorom128.cfg new file mode 100644 index 00000000..35aa71c4 --- /dev/null +++ b/roms/snes-tests/spctest/lorom128.cfg @@ -0,0 +1,30 @@ +# ca65 linker config for 128K SMC + +# Physical areas of memory +# Names need not match, but it makes it easier to remember if they do. +MEMORY { + ZEROPAGE: start = 0, size = $100; + BSS: start = $200, size = $1800; + ROM: start = $8000, size = $8000, fill = yes; + BANK1: start = $18000, size = $8000, fill = yes; + BANK2: start = $28000, size = $8000, fill = yes; + BANK3: start = $38000, size = $8000, fill = yes; +} + +# Logical areas code/data can be put into. +SEGMENTS { + ZEROPAGE: load = ZEROPAGE, type = zp; + BSS: load = BSS, type = bss, align = $100; + + CODE: load = ROM, align = $8000; + RODATA: load = ROM; + HEADER: load = ROM, start = $FFC0; + ROMINFO: load = ROM, start = $FFD5, optional = yes; + VECTORS: load = ROM, start = $FFE0; + + # The extra three banks + BANK1: load = BANK1, align = $8000, optional = yes; + BANK2: load = BANK2, align = $8000, optional = yes; + BANK3: load = BANK3, align = $8000, optional = yes; +} + diff --git a/roms/snes-tests/spctest/make_tests.py b/roms/snes-tests/spctest/make_tests.py new file mode 100755 index 00000000..83b29bc2 --- /dev/null +++ b/roms/snes-tests/spctest/make_tests.py @@ -0,0 +1,1338 @@ +#!/usr/bin/env python3 + +TESTS_PER_FILE = 500 + +test_num = 0 +file_num = 0 +tests_txt = [] +spc_code = [] + +FLAGS_MAP = {"C": 1, "Z": 2, "I": 4, "H": 8, "B": 0x10, "P": 0x20, "V": 0x40, "N": 0x80} + +# addressing modes: +A_IMPLIED = 0 +A_DP = 1 # $12 +A_DP_X = 2 # $12+x +A_DP_Y = 3 # $12+y +A_IND_X = 4 # (x) +A_DP_DP = 5 # $12, $34 +A_IND_X_IND_Y = 6 # (x), (y) +A_DP_IMM = 7 # $12, #$34 +A_ABS = (8,) # $1234 +A_ABS_X = (9,) # $1234+x +A_ABS_Y = (10,) # $1234+y +A_DP_X_IND = (11,) # [dp+x] +A_IND_DP_Y = (12,) # [dp]+y +A_IMM = (13,) # #$12 +A_IND_X_PLUS = (14,) # (x)+ + +# Other modes are handled with specific instructions' tests + + +def flags(p, default=None, add=None): + """Return flags byte, converting from string and adding `add` if needed""" + if p is None: + return flags(default or 0, add=add) + if isinstance(p, int): + ret = p + else: + ret = sum(FLAGS_MAP[c] for c in set(p)) + if add is not None: + ret |= flags(add) + return ret + + +def test( + ins, + a=0x12, + x=0x34, + y=0x56, + p=None, + ea=None, + ex=None, + ey=None, + ep=None, + esp=None, + before_regs=None, + before_ins=None, + after_ins=None, + after_checks=None, + **kwargs, +): + """Test the given instruction, setting registers/memory before and checking them after. + + - a, x, y, p are the input register values + - e* are the expected output values. If None then they should be the same as input. + - mem_abcd means this is the input value in memory location $ABCD (or any other). + - emem_abcd is the output value. + - before_regs, before_ins, after_ins, after_checks are used to add additional assembly code + at specific points. + """ + global test_num + if test_num % TESTS_PER_FILE == 0 and test_num != 0: + close_spc_file() + start_spc_file() + + p = flags(p) + ep = flags(ep, p) + if ea is None: + ea = a + if ex is None: + ex = x + if ey is None: + ey = y + + mem_input = [] + mem_output = {} + for k, v in kwargs.items(): + if k.startswith("mem_"): + mem_input.append((int(k[4:], 16), v)) + elif k.startswith("emem_"): + mem_output[int(k[5:], 16)] = v + else: + assert False, "Invalid keyword: " + k + + spc_code.append(f"""test{test_num:04x}: + mov a, #${(test_num & 0xFF):02x} + mov y, #${(test_num >> 8):02x} + call init_test""") + + if before_regs: + spc_code.append(before_regs) + for loc, val in mem_input: + if loc not in mem_output: + mem_output[loc] = val + if loc < 0x100: + spc_code.append(f" mov ${loc:02x}, #${val:02x}") + else: + spc_code.append(f" mov a, #${val:02x}") + spc_code.append(f" mov ${loc:04x}, a") + + spc_code.append(f"""\ + mov a, #${p:02x} + push a + mov a, #${a:02x} + mov x, #${x:02x} + mov y, #${y:02x} + pop psw""") + if before_ins: + spc_code.append(before_ins) + spc_code.append(f" {ins}") + if after_ins: + spc_code.append(after_ins) + spc_code.append(f"""\ + call save_results ; now a = result psw + cmp a, #${ep:02x} + bne .to_fail + cmp result_a, #${ea:02x} + bne .to_fail + cmp x, #${ex:02x} + bne .to_fail + cmp y, #${ey:02x} + bne .to_fail""") + if esp is not None: + spc_code.append(f"""\ + mov x, sp + cmp x, #${esp:02x} + bne .to_fail""") + + for loc, val in mem_output.items(): + if val is not None: + if loc < 0x100: + spc_code.append(f" cmp ${loc:02x}, #${val:02x}") + else: + spc_code.append(f" mov a, ${loc:04x}") + spc_code.append(f" cmp a, #${val:02x}") + spc_code.append(" bne .to_fail") + + if after_checks: + spc_code.append(after_checks) + + spc_code.append("""\ + bra .next_test + .to_fail: + jmp fail + .next_test: + """) + + tests_txt.append(f"Test {test_num:04x}: {ins}") + inputs = f"A=${a:02x} X=${x:02x} Y=${y:02x} P=${p:02x}" + if mem_input: + inputs += " " + " ".join(f"(${loc:02x})=${val:02x}" for loc, val in mem_input) + outputs = f"A=${ea:02x} X=${ex:02x} Y=${ey:02x} P=${ep:02x}" + if esp is not None: + outputs += f" SP={esp:02x}" + if mem_output: + outputs += " " + " ".join( + f"(${loc:02x})=${val:02x}" + for loc, val in mem_output.items() + if val is not None + ) + + tests_txt.append(f" Input: {inputs}") + tests_txt.append(f" Expected output: {outputs}") + if before_regs or before_ins or after_ins or after_checks: + tests_txt.append( + " Additional initialization or checks are performed - see assembly" + ) + + test_num += 1 + + +def add_operand(base_ins, operand): + if "%" in base_ins: + return base_ins.replace("%", operand) + else: + return f"{base_ins} {operand}" + + +def test_one_param_ins(base_ins, modes, val, result=None, p="", ep=None, **kwargs): + """Test an instruction with one operand such as ASL. + If base_ins contains a % sign then the operand replaces it, otherwise it's placed at the end. + """ + if result is None: + result = val + + def do_test(operand, add_p_flag=False, **kwargs2): + add_flags = flags("P") if add_p_flag else 0 + new_p = flags(p) | add_flags + new_ep = flags(ep, new_p) | add_flags + kwargs3 = kwargs.copy() + kwargs3.update(kwargs2) + test(add_operand(base_ins, operand), p=new_p, ep=new_ep, **kwargs3) + + for mode in modes: + if mode == A_IMPLIED: + do_test("a", a=val, ea=result) + elif mode == A_DP: + do_test("$01", mem_01=val, emem_01=result) + do_test("$02", add_p_flag=True, mem_102=val, emem_102=result) + elif mode == A_DP_X: + do_test("$ff+x", x=2, mem_01=val, emem_01=result) + do_test("$ff+x", add_p_flag=True, x=3, mem_102=val, emem_102=result) + elif mode == A_DP_Y: + do_test("$ff+y", y=2, mem_01=val, emem_01=result) + do_test("$ff+y", add_p_flag=True, y=3, mem_102=val, emem_102=result) + elif mode == A_ABS: + do_test("$103", mem_103=val, emem_103=result) + elif mode == A_IND_X: + do_test("(x)", x=1, mem_01=val, emem_01=result) + elif mode == A_IND_X_PLUS: + do_test( + "(x+)", x=1, ex=2, mem_01=val, emem_01=result + ) # spcasm doesn't support (x)+ syntax for some reason + elif mode == A_ABS_X: + do_test("$ffff+x", x=5, mem_04=val, emem_04=result) + elif mode == A_ABS_Y: + do_test("$103+y", y=1, mem_104=val, emem_104=result) + elif mode == A_DP_X_IND: + do_test( + "[$ff+x]", x=2, mem_01=0x02, mem_02=0x01, mem_102=val, emem_102=result + ) + elif mode == A_IND_DP_Y: + do_test( + "[$01]+y", y=5, mem_01=0xFE, mem_02=0xFF, mem_03=val, emem_03=result + ) + elif mode == A_IMM: + assert val == result # Can't change imm... + do_test(f"#${val:02x}") + else: + assert False, "Invalid mode for " + base_ins + + +def test_two_param_ins(base_ins, modes, val1, val2, result=None, p="", ep=None): + """Test an instruction with two operands such as AND""" + if result is None: + result = val1 + for mode in modes: + if mode == A_DP_DP: + test( + f"{base_ins} $01, $02", + mem_01=val1, + mem_02=val2, + emem_01=result, + p=p, + ep=ep, + ) + test( + f"{base_ins} $02, $03", + mem_102=val1, + mem_103=val2, + emem_102=result, + p=flags(p, add="P"), + ep=flags(ep, p, add="P"), + ) + elif mode == A_IND_X_IND_Y: + test( + f"{base_ins} (x), (y)", + x=1, + y=2, + mem_01=val1, + mem_02=val2, + emem_01=result, + p=p, + ep=ep, + ) + elif mode == A_DP_IMM: + test_one_param_ins( + f"{base_ins} %, #${val2:02x}", [A_DP], val1, result, p=p, ep=ep + ) + else: + # It's a single operand, so add a fixed A operand and treated the second one as the only operand + test_one_param_ins( + f"{base_ins} a, %", [mode], val2, a=val1, ea=result, p=p, ep=ep + ) + + +def test_16bit_ins( + base_ins, val, result=None, ya=None, p="", eya=None, ep=None, **kwargs +): + """Test a 16 bit instruction. These only use direct page addressing""" + if result is None: + result = val + if ya is not None: + kwargs["a"] = ya & 0xFF + kwargs["y"] = ya >> 8 + if eya is not None: + kwargs["ea"] = eya & 0xFF + kwargs["ey"] = eya >> 8 + test( + add_operand(base_ins, "$01"), + mem_01=val & 0xFF, + mem_02=val >> 8, + emem_01=result & 0xFF, + emem_02=result >> 8, + p=p, + ep=ep, + **kwargs, + ) + # now with direct page 1 + wrapping + test( + add_operand(base_ins, "$FF"), + mem_1ff=val & 0xFF, + mem_100=val >> 8, + emem_1ff=result & 0xFF, + emem_100=result >> 8, + p=flags(p, add="P"), + ep=flags(ep, p, add="P"), + **kwargs, + ) + + +def test_branch_taken(base_ins, **kwargs): + # branch backwards: + before = """\ + bra .branch + .ok: + bra .ok2 + .branch:""" + after = """\ + call save_results + bra .to_fail + .ok2:""" + test(f"{base_ins} .ok", before_ins=before, after_ins=after, **kwargs) + + # branch forward: + after = """\ + call save_results + bra .to_fail + .ok:""" + test(f"{base_ins} .ok", after_ins=after, **kwargs) + + +def test_branch_not_taken(base_ins, **kwargs): + after = """\ + bra .ok + .not_ok: + call save_results + bra .to_fail + .ok:""" + test(f"{base_ins} .not_ok", after_ins=after, **kwargs) + + +def adc_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + test_two_param_ins("adc", modes, 0x12, 0x34, p="", result=0x46, ep="") + test_two_param_ins("adc", modes, 0x12, 0x34, p="CZIHBVN", result=0x47, ep="IB") + test_two_param_ins("adc", modes, 0xCB, 0x34, p="C", result=0x00, ep="ZCH") + test_two_param_ins("adc", modes, 0x00, 0x00, p="", result=0x00, ep="Z") + test_two_param_ins("adc", modes, 0x90, 0x90, p="", result=0x20, ep="CV") + test_two_param_ins("adc", modes, 0x50, 0x50, p="", result=0xA0, ep="VN") + test_two_param_ins("adc", modes, 0x00, 0x7F, p="C", result=0x80, ep="VNH") + test_two_param_ins("adc", modes, 0x00, 0xFF, p="C", result=0x00, ep="ZCH") + + +def addw_tests(): + def test_addw(val1, val2, p, ep): + res = (val1 + val2) & 0xFFFF + test_16bit_ins("addw ya, %", val2, ya=val1, p=p, eya=res, ep=ep) + + test_addw(0x3412, 0x00FF, p="", ep="") + test_addw(0x3412, 0x00FF, p="CZIHBVN", ep="IB") + test_addw(0x0000, 0x0001, p="", ep="") + test_addw(0x0000, 0x0100, p="", ep="") + test_addw(0x34FF, 0x00FF, p="H", ep="") + test_addw(0x3412, 0x0C00, p="", ep="H") + test_addw(0x7FFF, 0x0001, p="", ep="HNV") + test_addw(0xFFFF, 0x0001, p="", ep="HZC") + test_addw(0x8000, 0xFFFF, p="", ep="CV") + + +def and_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + test_two_param_ins("and", modes, 0xFF, 0xFF, result=0xFF, ep="N") + test_two_param_ins("and", modes, 0xFF, 0x00, result=0x00, ep="Z") + test_two_param_ins("and", modes, 0x00, 0xFF, result=0x00, p="CZIHBVN", ep="CZIHBV") + test_two_param_ins("and", modes, 0xC5, 0x93, result=0x81, p="CZIHBVN", ep="CIHBVN") + + +def and1_tests(): + test("and1 C, $102.2", p="C", mem_102=0x04, ep="C") + test("and1 C, $102.2", p="", mem_102=0x04, ep="") + test("and1 C, $102.2", p="CZIHBPVN", mem_102=0xFB, ep="ZIHBPVN") + test("and1 C, /$102.2", p="C", mem_102=0x04, ep="") + test("and1 C, /$102.2", p="C", mem_102=0xFB, ep="C") + test("and1 C, /$102.2", p="C", mem_102=0x00, ep="C") + + +def asl_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + test_one_param_ins("asl", modes, 0xFF, 0xFE, p="", ep="NC") + test_one_param_ins("asl", modes, 0x80, 0x00, p="", ep="ZC") + test_one_param_ins("asl", modes, 0x03, 0x06, p="CZIHBVN", ep="IHBV") + + +def bbc_tests(): + for bit in range(8): + test_branch_not_taken(f"bbc $01.{bit},", mem_01=1 << bit) + test_branch_not_taken(f"bbc $01.{bit},", mem_01=0xFF, p="CZIHBVN") + test_branch_taken(f"bbc $01.{bit},", mem_01=0xFF - (1 << bit)) + test_branch_taken(f"bbc $01.{bit},", mem_01=0x00, p="CZIHBVN") + test_branch_not_taken(f"bbc $02.{bit},", mem_102=1 << bit, p="P") + test_branch_taken(f"bbc $02.{bit},", mem_102=0xFF - (1 << bit), p="P") + + +def bbs_tests(): + for bit in range(8): + test_branch_taken(f"bbs $01.{bit},", mem_01=1 << bit) + test_branch_taken(f"bbs $01.{bit},", mem_01=0xFF, p="CZIHBVN") + test_branch_not_taken(f"bbs $01.{bit},", mem_01=0xFF - (1 << bit)) + test_branch_not_taken(f"bbs $01.{bit},", mem_01=0x00, p="CZIHBVN") + test_branch_taken(f"bbs $02.{bit},", mem_102=1 << bit, p="P") + test_branch_not_taken(f"bbs $02.{bit},", mem_102=0xFF - (1 << bit), p="P") + + +def branch_tests(): + """Tests the simple branch instructions which don't access memory""" + test_branch_taken("bra") + test_branch_taken("bra", p="CZIHBPVN") + + def flag_test(ins_on, ins_off, flag): + flag = flags(flag) + test_branch_taken(ins_on, p=flag) + test_branch_not_taken(ins_off, p=flag) + test_branch_not_taken(ins_on, p="") + test_branch_taken(ins_off, p="") + test_branch_taken(ins_on, p="CZIHBPVN") + test_branch_not_taken(ins_off, p="CZIHBPVN") + test_branch_not_taken(ins_on, p=flags("CZIHBPVN") - flag) + test_branch_taken(ins_off, p=flags("CZIHBPVN") - flag) + + flag_test("bcs", "bcc", "C") + flag_test("beq", "bne", "Z") + flag_test("bmi", "bpl", "N") + flag_test("bvs", "bvc", "V") + + +def brk_tests(): + before_regs = """\ + mov a, #(.brk_target & $FF) + mov $ffde, a + mov a, #(.brk_target >> 8) + mov $ffdf, a""" + + after_ins = """\ + .after_brk: + bra .to_fail + .brk_target:""" + + after_checks = """\ + mov a, $1ee + cmp a, #(.after_brk & $FF) + bne .to_fail + mov a, $1ef + cmp a, #(.after_brk >> 8) + bne .to_fail + pop a + pop a + pop a""" + + test( + "brk", + p="", + ep="B", + esp=0xEC, + emem_1ed=0x00, + before_regs=before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + test( + "brk", + p="CZIHBPVN", + ep="CZHBPVN", + esp=0xEC, + emem_1ed=flags("CZIHBPVN"), + before_regs=before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + + +def call_tests(): + after_ins = """\ + .after_call: + bra .to_fail + .call_target:""" + + after_checks = """\ + mov a, $1ee + cmp a, #(.after_call & $FF) + bne .to_fail + mov a, $1ef + cmp a, #(.after_call >> 8) + bne .to_fail + pop a + pop a""" + + test("call .call_target", after_ins=after_ins, after_checks=after_checks) + test( + "call .call_target", + p="CZIHBPVN", + after_ins=after_ins, + after_checks=after_checks, + ) + + # put 'jmp .call_target' at $FFFF (wrapping) + pcall_before_regs = """\ + mov a, #$5F + mov $FFFF, a + mov $00, #(.call_target & $FF) + mov $01, #(.call_target >> 8)""" + + test( + "pcall $FF", + before_regs=pcall_before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + test( + "pcall $FF", + p="CZIHBPVN", + before_regs=pcall_before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + + for n in range(16): + addr = 0xFFDE - 2 * n + # erase previous pointer to make sure we don't use it, and add a new one. + tcall_before_regs = f"""\ + mov a, #$00 + mov ${addr - 1:04x}, a + mov a, #(.call_target & $FF) + mov ${addr:04x}, a + mov a, #(.call_target >> 8) + mov ${addr + 1:04x}, a""" + test( + f"tcall {n}", + before_regs=tcall_before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + test( + f"tcall {n}", + p="CZIHBPVN", + before_regs=tcall_before_regs, + after_ins=after_ins, + after_checks=after_checks, + ) + + +def cbne_tests(): + for p in ["", "CZIHBVN"]: + test_branch_taken("cbne $01,", p=p, ep=p, a=0x12, mem_01=0x13) + test_branch_not_taken("cbne $01,", p=p, ep=p, a=0x80, mem_01=0x80) + test_branch_taken("cbne $ff+x,", p=p, ep=p, x=2, a=0xFF, mem_01=0x00) + test_branch_not_taken("cbne $ff+x,", p=p, ep=p, x=2, a=0xFF, mem_01=0xFF) + + test_branch_taken("cbne $02,", p=p + "P", ep=p + "P", a=0x12, mem_102=0x13) + test_branch_not_taken("cbne $02,", p=p + "P", ep=p + "P", a=0x80, mem_102=0x80) + test_branch_taken( + "cbne $ff+x,", p=p + "P", ep=p + "P", x=4, a=0xFF, mem_103=0x00 + ) + test_branch_not_taken( + "cbne $ff+x,", p=p + "P", ep=p + "P", x=4, a=0xFF, mem_103=0xFF + ) + + +def clr1_tests(): + for bit in range(8): + test_one_param_ins(f"clr1 %.{bit}", [A_DP], 0xFF, 0xFF - (1 << bit)) + test_one_param_ins(f"clr1 %.{bit}", [A_DP], 0x00, 0x00) + test_one_param_ins( + f"clr1 %.{bit}", [A_DP], 0xFF, 0xFF - (1 << bit), p="CZIHBVN", ep="CZIHBVN" + ) + test_one_param_ins( + f"clr1 %.{bit}", [A_DP], 0x00, 0x00, p="CZIHBVN", ep="CZIHBVN" + ) + + +def flag_manip_tests(): + test("clrc", p="CZIHBPVN", ep="ZIHBPVN") + test("clrc", p="", ep="") + test("clrp", p="CZIHBPVN", ep="CZIHBVN") + test("clrp", p="", ep="") + test("clrv", p="CZIHBPVN", ep="CZIBPN") + test("clrv", p="", ep="") + test("setc", p="CZIHBPVN", ep="CZIHBPVN") + test("setc", p="", ep="C") + test("setp", p="CZIHBPVN", ep="CZIHBPVN") + test("setp", p="", ep="P") + test("di", p="CZIHBPVN", ep="CZHBPVN") + test("di", p="", ep="") + test("ei", p="CZIHBPVN", ep="CZIHBPVN") + test("ei", p="", ep="I") + test("notc", p="CZIHBPVN", ep="ZIHBPVN") + test("notc", p="", ep="C") + + +def cmp_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + modes_xy = [ + A_IMM, + A_DP, + A_ABS, + ] # addressing modes for comparing with x or y registers + + def do_test(val1, val2, p, ep): + test_two_param_ins("cmp", modes, val1, val2, p=p, ep=ep) + test_one_param_ins("cmp x, %", modes_xy, val2, x=val1, p=p, ep=ep) + test_one_param_ins("cmp y, %", modes_xy, val2, y=val1, p=p, ep=ep) + + do_test(0x12, 0x12, p="", ep="ZC") + do_test(0x13, 0x12, p="CZIHBVN", ep="CIHBV") + do_test(0x12, 0x13, p="CZIHBVN", ep="IHBVN") + do_test(0xFE, 0xFF, p="", ep="N") + do_test(0xFE, 0x01, p="", ep="CN") + + +def cmpw_tests(): + test_16bit_ins("cmpw ya, %", ya=0x2345, val=0x1245, p="", ep="C") + test_16bit_ins("cmpw ya, %", ya=0xFFFF, val=0xFFFF, p="CZIHBVN", ep="CZIHBV") + test_16bit_ins("cmpw ya, %", ya=0xFFFF, val=1, p="CZIHBVN", ep="CIHBVN") + test_16bit_ins("cmpw ya, %", ya=0x7FFF, val=0x8000, p="", ep="N") + + +def daa_tests(): + test("daa a", a=0x10, p="", ea=0x10, ep="") + test("daa a", a=0x1A, p="", ea=0x20, ep="") + test("daa a", a=0x10, p="C", ea=0x70, ep="C") + test("daa a", a=0x10, p="CH", ea=0x76, ep="CH") + test("daa a", a=0xFF, p="ZIBPVN", ea=0x65, ep="CIBPV") + test("daa a", a=0x9A, p="", ea=0x00, ep="ZC") + + # The following can only happen after addition of numbers with non-BCD digits + test("daa a", a=0x91, p="C", ea=0xF1, ep="CN") + test("daa a", a=0x9A, p="H", ea=0x00, ep="ZHC") + test("daa a", a=0x99, p="H", ea=0x9F, ep="HN") + + +def das_tests(): + test("das a", a=0x10, p="CH", ea=0x10, ep="CH") + test("das a", a=0x1A, p="CH", ea=0x14, ep="CH") + test("das a", a=0xA1, p="CZIHBPVN", ea=0x41, ep="IHBPV") + test("das a", a=0xFF, p="CH", ea=0x99, ep="HN") + test("das a", a=0x99, p="", ea=0x33, ep="") + test("das a", a=0x66, p="", ea=0x00, ep="Z") + + # The following can only happen after subtraction of numbers with non-BCD digits + test("das a", a=0x11, p="", ea=0xAB, ep="N") + + +def dbnz_tests(): + test_branch_taken("dbnz y,", y=0, ey=0xFF, p="") + test_branch_taken("dbnz y,", y=0x81, ey=0x80, p="CZIHBPVN", ep="CZIHBPVN") + test_branch_not_taken("dbnz y,", y=1, ey=0, p="") + + test_branch_taken("dbnz $01,", mem_01=0, emem_01=0xFF, p="") + test_branch_taken("dbnz $01,", mem_01=0x81, emem_01=0x80, p="CZIHBVN", ep="CZIHBVN") + test_branch_not_taken("dbnz $01,", mem_01=1, emem_01=0, p="") + + test_branch_taken("dbnz $02,", mem_102=0, emem_102=0xFF, p="P") + test_branch_taken( + "dbnz $02,", mem_102=0x81, emem_102=0x80, p="CZIHBPVN", ep="CZIHBPVN" + ) + test_branch_not_taken("dbnz $02,", mem_102=1, emem_102=0, p="P") + + +def dec_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + + def do_test(val, res, p, ep): + test_one_param_ins("dec", modes, val, res, p=p, ep=ep) + test("dec x", x=val, ex=res, p=p, ep=ep) + test("dec y", y=val, ey=res, p=p, ep=ep) + + do_test(0x00, 0xFF, p="", ep="N") + do_test(0x01, 0x00, p="", ep="Z") + do_test(0x80, 0x7F, p="CZIHBVN", ep="CIHBV") + + +def decw_tests(): + test_16bit_ins("decw", 0x0001, 0x0000, p="", ep="Z") + test_16bit_ins("decw", 0x0000, 0xFFFF, p="", ep="N") + test_16bit_ins("decw", 0x0101, 0x0100, p="CZIHBVN", ep="CIHBV") + test_16bit_ins("decw", 0x0080, 0x007F, p="", ep="") + + +def div_tests(): + test("div ya, x", y=0x00, a=0x00, x=0x00, p="", ey=0, ea=0xFF, ep="HVN") + test("div ya, x", y=0x01, a=0x23, x=0x10, p="", ey=3, ea=0x12, ep="H") + test("div ya, x", y=0x01, a=0x10, x=0x88, p="CZIHBPVN", ey=0, ea=0x2, ep="CIBP") + test("div ya, x", y=0x01, a=0x0F, x=0x88, p="CZIHBPVN", ey=0x87, ea=0x1, ep="CIBP") + test("div ya, x", y=0x01, a=0x23, x=0x01, p="", ey=0, ea=0x23, ep="HV") + test("div ya, x", y=0xFF, a=0xFF, x=0x00, p="", ey=0xFF, ea=0x00, ep="ZVH") + test("div ya, x", y=0xAB, a=0xCD, x=0x03, p="", ey=0xC5, ea=0x58, ep="VH") + + +def eor_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + test_two_param_ins("eor", modes, 0xFF, 0xFF, result=0x00, ep="Z") + test_two_param_ins("eor", modes, 0xFF, 0x00, result=0xFF, ep="N") + test_two_param_ins("eor", modes, 0x55, 0xFF, result=0xAA, p="CZIHBVN", ep="CIHBVN") + test_two_param_ins("eor", modes, 0x35, 0x89, result=0xBC, p="CZIHBVN", ep="CIHBVN") + + +def eor1_tests(): + test("eor1 C, $102.2", p="C", mem_102=0x04, ep="") + test("eor1 C, $102.2", p="", mem_102=0x04, ep="C") + test("eor1 C, $102.2", p="CZIHBPVN", mem_102=0xFB, ep="CZIHBPVN") + test("eor1 C, $102.2", p="ZIHBPVN", mem_102=0xFB, ep="ZIHBPVN") + + +def inc_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + + def do_test(val, res, p, ep): + test_one_param_ins("inc", modes, val, res, p=p, ep=ep) + test("inc x", x=val, ex=res, p=p, ep=ep) + test("inc y", y=val, ey=res, p=p, ep=ep) + + do_test(0x00, 0x01, p="", ep="") + do_test(0xFF, 0x00, p="", ep="Z") + do_test(0x80, 0x81, p="CZIHBVN", ep="CIHBVN") + + +def incw_tests(): + test_16bit_ins("incw", 0xFFFF, 0x0000, p="", ep="Z") + test_16bit_ins("incw", 0x0000, 0x0001, p="", ep="") + test_16bit_ins("incw", 0x00FF, 0x0100, p="CZIHBVN", ep="CIHBV") + test_16bit_ins("incw", 0x7FFF, 0x8000, p="", ep="N") + + +def jmp_tests(): + after = """\ + call save_results + bra .to_fail + .ok:""" + + test("jmp .ok", after_ins=after) + + before = """\ + mov a, #(.ok & $FF) + mov $FFFF, a + mov $00, #(.ok >> 8)""" + test("jmp [$FF00+x]", x=0xFF, before_regs=before, after_ins=after) + + +def lsr_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + test_one_param_ins("lsr", modes, 0xFF, 0x7F, p="", ep="C") + test_one_param_ins("lsr", modes, 0x01, 0x00, p="", ep="ZC") + test_one_param_ins("lsr", modes, 0x06, 0x03, p="CZIHBVN", ep="IHBV") + + +def mov_tests(): + # mov a, mem/imm + modes = [ + A_IMM, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_IND_X_PLUS, + ] + test_one_param_ins( + "mov a, %", modes, 0x12, a=0x00, ea=0x12, p="CZIHBVN", ep="CIHBV" + ) + test_one_param_ins("mov a, %", modes, 0x80, ea=0x80, p="", ep="N") + test_one_param_ins("mov a, %", modes, 0x00, ea=0x00, p="", ep="Z") + + # mov mem, a + modes = [ + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_IND_X_PLUS, + ] + test_one_param_ins( + "mov %, a", modes, 0x00, a=0x12, result=0x12, p="CZIHBVN", ep="CZIHBVN" + ) + test_one_param_ins("mov %, a", modes, 0xFF, a=0x00, result=0x00, p="", ep="") + + # mov x, mem/imm + modes = [A_IMM, A_DP, A_DP_Y, A_ABS] + test_one_param_ins( + "mov x, %", modes, 0x12, x=0x00, ex=0x12, p="CZIHBVN", ep="CIHBV" + ) + test_one_param_ins("mov x, %", modes, 0x80, ex=0x80, p="", ep="N") + test_one_param_ins("mov x, %", modes, 0x00, ex=0x00, p="", ep="Z") + + # mov y, mem/imm + modes = [A_IMM, A_DP, A_DP_X, A_ABS] + test_one_param_ins( + "mov y, %", modes, 0x12, y=0x00, ey=0x12, p="CZIHBVN", ep="CIHBV" + ) + test_one_param_ins("mov y, %", modes, 0x80, ey=0x80, p="", ep="N") + test_one_param_ins("mov y, %", modes, 0x00, ey=0x00, p="", ep="Z") + + # mov mem, x + modes = [A_DP, A_DP_Y, A_ABS] + test_one_param_ins( + "mov %, x", modes, 0x00, x=0x12, result=0x12, p="CZIHBVN", ep="CZIHBVN" + ) + test_one_param_ins("mov %, x", modes, 0xFF, x=0x00, result=0x00, p="", ep="") + + # mov mem, y + modes = [A_DP, A_DP_X, A_ABS] + test_one_param_ins( + "mov %, y", modes, 0x00, y=0x12, result=0x12, p="CZIHBVN", ep="CZIHBVN" + ) + test_one_param_ins("mov %, y", modes, 0xFF, y=0x00, result=0x00, p="", ep="") + + # mov mem, mem/imm + modes = [A_DP_DP, A_DP_IMM] + test_two_param_ins("mov", modes, 0x00, 0x12, 0x12, p="CZIHBVN", ep="CZIHBVN") + test_two_param_ins("mov", modes, 0xFF, 0x00, 0x00, p="", ep="") + + # mov reg, reg + test("mov a, x", a=0x00, x=0x12, ea=0x12, p="CZIHBVN", ep="CIHBV") + test("mov a, x", a=0x12, x=0x00, ea=0x00, p="", ep="Z") + test("mov a, x", a=0x12, x=0x80, ea=0x80, p="", ep="N") + test("mov a, y", a=0x00, y=0x12, ea=0x12, p="CZIHBVN", ep="CIHBV") + test("mov a, y", a=0x12, y=0x00, ea=0x00, p="", ep="Z") + test("mov a, y", a=0x12, y=0x80, ea=0x80, p="", ep="N") + test("mov x, a", x=0x00, a=0x12, ex=0x12, p="CZIHBVN", ep="CIHBV") + test("mov x, a", x=0x12, a=0x00, ex=0x00, p="", ep="Z") + test("mov x, a", x=0x12, a=0x80, ex=0x80, p="", ep="N") + test("mov y, a", y=0x00, a=0x12, ey=0x12, p="CZIHBVN", ep="CIHBV") + test("mov y, a", y=0x12, a=0x00, ey=0x00, p="", ep="Z") + test("mov y, a", y=0x12, a=0x80, ey=0x80, p="", ep="N") + test("mov x, sp", ex=0xEF, p="CZIHBPV", ep="CIHBPVN") + + # mov sp, x + after = """\ + mov x, #$EF + mov sp, x""" + test("mov sp, x", x=0x00, esp=0x00, p="", ep="", after_checks=after) + test("mov sp, x", x=0x80, esp=0x80, p="CZIHBPVN", ep="CZIHBPVN", after_checks=after) + + +def mov1_tests(): + test("mov1 C, $102.2", p="", mem_102=0x04, ep="C") + test("mov1 C, $102.2", p="C", mem_102=0x04, ep="C") + test("mov1 C, $102.2", p="CZIHBPVN", mem_102=0xFB, ep="ZIHBPVN") + test("mov1 C, $102.2", p="ZIHBPVN", mem_102=0xFB, ep="ZIHBPVN") + + test("mov1 $102.3, C", mem_102=0x80, emem_102=0x88, p="C") + test("mov1 $102.3, C", mem_102=0x88, emem_102=0x88, p="CZIHBPVN") + test("mov1 $102.3, C", mem_102=0x88, emem_102=0x80, p="") + test("mov1 $102.3, C", mem_102=0x80, emem_102=0x80, p="ZIHBPVN") + + +def movw_tests(): + test_16bit_ins("movw ya, %", 0x12AB, eya=0x12AB, p="CZIHBVN", ep="CIHBV") + test_16bit_ins("movw ya, %", 0x8000, eya=0x8000, p="", ep="N") + test_16bit_ins("movw ya, %", 0x0000, eya=0x0000, p="", ep="Z") + + test_16bit_ins( + "movw %, ya", 0x0000, ya=0x1234, result=0x1234, p="CZIHBVN", ep="CZIHBVN" + ) + test_16bit_ins("movw %, ya", 0xABCD, ya=0x0000, result=0x0000, p="", ep="") + + +def mul_tests(): + test("mul ya", a=0xAB, y=0xCD, ey=0x88, ea=0xEF, p="CZIHBPVN", ep="CIHBPVN") + test("mul ya", a=0x05, y=0x02, ey=0x00, ea=0x0A, p="", ep="Z") + test("mul ya", a=0xFF, y=0xFF, ey=0xFE, ea=0x01, p="", ep="N") + test("mul ya", a=0x80, y=0x02, ey=0x01, ea=0x00, p="", ep="") + + +def nop_tests(): + test("nop", p="", ep="") + test("nop", p="CZIHBPVN", ep="CZIHBPVN") + + +def not1_tests(): + test("not1 $102.2", mem_102=0x04, emem_102=0x00, p="", ep="") + test("not1 $102.2", mem_102=0xFF, emem_102=0xFB, p="CZIHBPVN", ep="CZIHBPVN") + test("not1 $102.2", mem_102=0xC0, emem_102=0xC4, p="", ep="") + + +def or_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + test_two_param_ins("or", modes, 0x88, 0x19, result=0x99, p="", ep="N") + test_two_param_ins("or", modes, 0xFF, 0x00, result=0xFF, p="CZIHBVN", ep="CIHBVN") + test_two_param_ins("or", modes, 0x00, 0x00, result=0x00, p="", ep="Z") + + +def or1_tests(): + test("or1 C, $102.2", p="C", mem_102=0x04, ep="C") + test("or1 C, $102.2", p="", mem_102=0x04, ep="C") + test("or1 C, $102.2", p="CZIHBPVN", mem_102=0xFB, ep="CZIHBPVN") + test("or1 C, $102.2", p="ZIHBPVN", mem_102=0xFB, ep="ZIHBPVN") + test("or1 C, /$102.2", p="C", mem_102=0x04, ep="C") + test("or1 C, /$102.2", p="", mem_102=0x04, ep="") + test("or1 C, /$102.2", p="CZIHBPVN", mem_102=0xFB, ep="CZIHBPVN") + test("or1 C, /$102.2", p="ZIHBPVN", mem_102=0xFB, ep="CZIHBPVN") + + +def pop_tests(): + after = " push a" + # The emem_01f0=None will disable the check that memory hasn't changed, because we overwrite it by calling a function + test( + "pop a", + mem_01f0=0x98, + ea=0x98, + esp=0xF0, + p="", + ep="", + emem_01f0=None, + after_checks=after, + ) + test( + "pop a", + mem_01f0=0x00, + ea=0x00, + esp=0xF0, + p="CZIHBPVN", + ep="CZIHBPVN", + emem_01f0=None, + after_checks=after, + ) + test( + "pop x", + mem_01f0=0x98, + ex=0x98, + esp=0xF0, + p="", + ep="", + emem_01f0=None, + after_checks=after, + ) + test( + "pop x", + mem_01f0=0x00, + ex=0x00, + esp=0xF0, + p="CZIHBPVN", + ep="CZIHBPVN", + emem_01f0=None, + after_checks=after, + ) + test( + "pop y", + mem_01f0=0x98, + ey=0x98, + esp=0xF0, + p="", + ep="", + emem_01f0=None, + after_checks=after, + ) + test( + "pop y", + mem_01f0=0x00, + ey=0x00, + esp=0xF0, + p="CZIHBPVN", + ep="CZIHBPVN", + emem_01f0=None, + after_checks=after, + ) + test( + "pop psw", + mem_01f0=flags(""), + p="CZIHBPVN", + ep="", + emem_01f0=None, + after_checks=after, + ) + test( + "pop psw", + mem_01f0=flags("CZIHBPVN"), + p="", + ep="CZIHBPVN", + emem_01f0=None, + after_checks=after, + ) + + +def push_tests(): + after = " pop a" + test("push a", a=0x12, emem_01ef=0x12, esp=0xEE, p="", ep="", after_checks=after) + test( + "push a", + a=0x00, + emem_01ef=0x00, + esp=0xEE, + p="CZIHBPVN", + ep="CZIHBPVN", + after_checks=after, + ) + test("push x", x=0x12, emem_01ef=0x12, esp=0xEE, p="", ep="", after_checks=after) + test( + "push x", + x=0x00, + emem_01ef=0x00, + esp=0xEE, + p="CZIHBPVN", + ep="CZIHBPVN", + after_checks=after, + ) + test("push y", y=0x12, emem_01ef=0x12, esp=0xEE, p="", ep="", after_checks=after) + test( + "push y", + y=0x00, + emem_01ef=0x00, + esp=0xEE, + p="CZIHBPVN", + ep="CZIHBPVN", + after_checks=after, + ) + test( + "push psw", + p="CZIHBPVN", + emem_01ef=flags("CZIHBPVN"), + esp=0xEE, + ep="CZIHBPVN", + after_checks=after, + ) + test("push psw", p="", emem_01ef=flags(""), esp=0xEE, ep="", after_checks=after) + + +def ret_tests(): + before = """\ + mov a, #(.ok >> 8) + push a + mov a, #(.ok & $FF) + push a""" + after = """\ + call save_results + bra .to_fail + .ok:""" + test("ret", esp=0xEF, p="", ep="", before_regs=before, after_ins=after) + test( + "ret", + esp=0xEF, + p="CZIHBPVN", + ep="CZIHBPVN", + before_regs=before, + after_ins=after, + ) + + +def ret1_tests(): + before = """\ + mov a, #(.ok >> 8) + push a + mov a, #(.ok & $FF) + push a + push a""" # last push will be overwritten + after = """\ + call save_results + bra .to_fail + .ok:""" + test( + "ret1", + esp=0xEF, + mem_1ed=flags(""), + p="CZIHBPVN", + ep="", + emem_1ed=None, + before_regs=before, + after_ins=after, + ) + test( + "ret1", + esp=0xEF, + mem_1ed=flags("CZIHBPVN"), + p="", + ep="CZIHBPVN", + emem_1ed=None, + before_regs=before, + after_ins=after, + ) + + +def rol_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + test_one_param_ins("rol", modes, 0xFF, 0xFE, p="", ep="NC") + test_one_param_ins("rol", modes, 0xFF, 0xFF, p="C", ep="NC") + test_one_param_ins("rol", modes, 0x80, 0x00, p="", ep="ZC") + test_one_param_ins("rol", modes, 0x03, 0x07, p="CZIHBVN", ep="IHBV") + + +def ror_tests(): + modes = [A_IMPLIED, A_DP, A_DP_X, A_ABS] + test_one_param_ins("ror", modes, 0xFF, 0x7F, p="", ep="C") + test_one_param_ins("ror", modes, 0xFF, 0xFF, p="C", ep="NC") + test_one_param_ins("ror", modes, 0x01, 0x00, p="", ep="ZC") + test_one_param_ins("ror", modes, 0x06, 0x83, p="CZIHBVN", ep="IHBVN") + + +def sbc_tests(): + modes = [ + A_IMM, + A_IND_X_IND_Y, + A_IND_X, + A_IND_DP_Y, + A_DP_X_IND, + A_DP, + A_DP_X, + A_ABS, + A_ABS_X, + A_ABS_Y, + A_DP_DP, + A_DP_IMM, + ] + test_two_param_ins("sbc", modes, 0x46, 0x12, p="C", result=0x34, ep="CH") + test_two_param_ins("sbc", modes, 0x47, 0x12, p="ZIHBVN", result=0x34, ep="CHIB") + test_two_param_ins("sbc", modes, 0xCB, 0xCA, p="", result=0x00, ep="ZCH") + test_two_param_ins("sbc", modes, 0x90, 0x21, p="C", result=0x6F, ep="CV") + test_two_param_ins("sbc", modes, 0x70, 0xE0, p="H", result=0x8F, ep="VN") + test_two_param_ins("sbc", modes, 0x00, 0x00, p="", result=0xFF, ep="N") + + +def set1_tests(): + for bit in range(8): + test_one_param_ins(f"set1 %.{bit}", [A_DP], 0xFF, 0xFF, p="", ep="") + test_one_param_ins(f"set1 %.{bit}", [A_DP], 0x00, 1 << bit, p="", ep="") + test_one_param_ins( + f"set1 %.{bit}", [A_DP], 0xFF, 0xFF, p="CZIHBVN", ep="CZIHBVN" + ) + test_one_param_ins( + f"set1 %.{bit}", [A_DP], 0x12, 0x12 | (1 << bit), p="CZIHBVN", ep="CZIHBVN" + ) + + +def subw_tests(): + def test_subw(val1, val2, p, ep): + res = (val1 - val2) & 0xFFFF + test_16bit_ins("subw ya, %", val2, ya=val1, p=p, eya=res, ep=ep) + + test_subw(0x3412, 0x00FF, p="", ep="CH") + test_subw(0x3412, 0x00FF, p="CZIHBVN", ep="IBCH") + test_subw(0x0000, 0x0001, p="", ep="N") + test_subw(0xABCD, 0xABCD, p="", ep="CHZ") + test_subw(0x1234, 0x0300, p="H", ep="C") + test_subw(0x1234, 0x0034, p="", ep="CH") + test_subw(0x1234, 0x1200, p="", ep="CH") + test_subw(0x8000, 0x0001, p="", ep="CV") + test_subw(0x7123, 0xEFED, p="", ep="VN") + + +def tclr1_tests(): + test_one_param_ins("tclr1", [A_ABS], 0xFF, a=0x09, result=0xF6, p="", ep="") + test_one_param_ins( + "tclr1", [A_ABS], 0x05, a=0x15, result=0x00, p="CZIHBPVN", ep="CIHBPV" + ) + test_one_param_ins("tclr1", [A_ABS], 0x12, a=0x12, result=0x00, p="", ep="Z") + test_one_param_ins("tclr1", [A_ABS], 0x12, a=0x02, result=0x10, p="", ep="N") + + +def tset1_tests(): + test_one_param_ins( + "tset1", [A_ABS], 0x11, a=0x09, result=0x19, p="CZIHBPVN", ep="CIHBPVN" + ) + test_one_param_ins( + "tset1", [A_ABS], 0x09, a=0x11, result=0x19, p="CZIHBPVN", ep="CIHBPV" + ) + test_one_param_ins( + "tset1", [A_ABS], 0x05, a=0x05, result=0x05, p="CZIHBPVN", ep="CZIHBPV" + ) + test_one_param_ins("tset1", [A_ABS], 0xFF, a=0xFE, result=0xFF, p="", ep="N") + + +def xcn_tests(): + test("xcn a", a=0x12, ea=0x21, p="CZIHBPVN", ep="CIHBPV") + test("xcn a", a=0x18, ea=0x81, p="", ep="N") + test("xcn a", a=0x00, ea=0x00, p="", ep="Z") + test("xcn a", a=0xF0, ea=0x0F, p="", ep="") + + +def add_all_tests(): + adc_tests() + addw_tests() + and_tests() + and1_tests() + asl_tests() + bbc_tests() + bbs_tests() + branch_tests() + brk_tests() + call_tests() # also PCALL and TCALL + cbne_tests() + clr1_tests() + flag_manip_tests() + cmp_tests() + cmpw_tests() + dbnz_tests() + dec_tests() + decw_tests() + eor_tests() + eor1_tests() + inc_tests() + incw_tests() + jmp_tests() + lsr_tests() + mov_tests() + mov1_tests() + movw_tests() + mul_tests() + nop_tests() + not1_tests() + or_tests() + or1_tests() + pop_tests() + push_tests() + ret_tests() + ret1_tests() + rol_tests() + ror_tests() + sbc_tests() + set1_tests() + subw_tests() + tclr1_tests() + tset1_tests() + xcn_tests() + + # Leave daa/das/div to the end because some of their behavior is not officially documented + daa_tests() + das_tests() + div_tests() + + +def start_spc_file(): + spc_code.clear() + spc_code.append("; Auto-generated by make_tests.py\n") + spc_code.append('include "spc_common.inc"') + spc_code.append("start_tests:\n") + + +def close_spc_file(): + global file_num + + spc_code.append(""" jmp success""") + with open(f"spc_tests{file_num}.asm", "w") as f: + f.write("\n".join(spc_code) + "\n") + file_num += 1 + + +def main(): + tests_txt.append("Auto-generated by make_tests.py\n") + + start_spc_file() + add_all_tests() + + with open("tests.txt", "w") as f: + f.write("\n".join(tests_txt) + "\n") + close_spc_file() + + +main() diff --git a/roms/snes-tests/spctest/spc_common.inc b/roms/snes-tests/spctest/spc_common.inc new file mode 100644 index 00000000..6656e27f --- /dev/null +++ b/roms/snes-tests/spctest/spc_common.inc @@ -0,0 +1,79 @@ +; All memory up to $300 is uninitialized +org $0 + ; First 16 bytes are reserved for testing instructions. +org $10 +test_num: + dw 0 +result_a: db 0 +result_x: db 0 +result_y: db 0 +result_p: db 0 + +; Load RAM from here +org $300 +main: + mov $f4, #$00 + mov $f1, #$00 ; disable IPL ROM +.wait1: ; wait for CPU to set port1 = 1 + cmp $f5, #$01 + bne .wait1 + + ; CPU put last test num in ports 2/3 + mov a, $F6 + mov test_num, a + mov a, $F7 + mov test_num+1, a + + jmp start_tests + + +; input: YA = test number +init_test: + incw test_num + cmpw ya, test_num + beq .ok + jmp fail ; We are at the wrong test - possibly due to an errant jump +.ok: + movw $f6, ya ; let main CPU know what test is running + ret + + +; saves registers to memory and returns psw in a. Also clears P flag +save_results: + push psw + clrp + mov result_a, a + mov result_x, x + mov result_y, y + pop a + mov result_p, a + ret + + +success: + mov $f4, #$01 +.wait1: ; Wait for CPU set set port1 = 0 + cmp $f5, #$00 + bne .wait1 + + mov $f1, #$80 ; enable IPL ROM + jmp $ffc0 ; jump to IPL ROM + + +fail: + ; $f6,$f7 contain last test number + mov a, result_p + mov $f5, a + mov $f4, #$02 +.wait1: ; wait for CPU to set port1 = 2 + cmp $f5, #$02 + bne .wait1 + + mov a, result_a + mov $f5, a + mov a, result_x + mov $f6, a + mov a, result_y + mov $f7, a + mov $f4, #$03 +.end: bra .end diff --git a/roms/snes-tests/spctest/spctest.asm b/roms/snes-tests/spctest/spctest.asm new file mode 100644 index 00000000..3db11e20 --- /dev/null +++ b/roms/snes-tests/spctest/spctest.asm @@ -0,0 +1,392 @@ +.p816 +.i16 +.a8 + +; CPU <--> SPC communication: +; - Normal IPL ROM load+execute program +; - SPC sets port0 = 0, CPU waits for it. +; - CPU sets port2/3 = last test num (or -1 at start), port1 = 1, SPC waits for it +; - SPC continuously writes 16-bit test numbers to port2/port3, without waiting for response +; - When all tests done successfully: +; - SPC sets port2/3 = last test num, port0 = 1 +; - CPU sets port1 = 0, SPC waits for it. +; - SPC jumps to IPL ROM. CPU repeats from start if needed, otherwise stops. +; - When a test fails: +; - SPC sets port2/3 = test num, port1 = PSW, port0 = 2 +; - CPU sets port1 = 2, SPC waits for it. +; - SPC sets port1 = A, port2 = X, port3 = Y, port0 = 3 +; - SPC and CPU stop + + +.segment "HEADER" + .byte "SPC-700 TEST " +.segment "ROMINFO" ; $FFD5 + .byte $30 ; LoROM + .byte 0 ; no battery/chips + .byte $07 ; 128K + .byte 0, 0, 0, 0 + .word $0000, $FFFF ;checksum+complement + +.segment "VECTORS" + .word 0, 0, 0, 0, 0, 0, 0, 0 + .word 0, 0, 0, 0, 0, 0, main, 0 + +.segment "ZEROPAGE" +spc_addr: .word 0 +spc_size: .word 0 +last_test_num: .word 0 + +.segment "CODE" + +.macro load_and_run_spc addr, end_addr + lda #^addr + ldx #.loword(addr) + ldy #end_addr-addr + jsr load_spc + jsr wait_result +.endmacro + + +main: + clc + xce + sei + rep #$18 ; 16 bit X/Y + sep #$20 ; 8 bit A + ldx #$1FFF + txs + jsr init_regs + jsr init_video_mem + + ldx #txt_running + ldy #$21 + jsr write_text + + ldx #txt_testnum + ldy #$61 + jsr write_text + + lda #$0F ; screen on + sta $2100 + + ldx #$ffff + stx last_test_num + load_and_run_spc spc0, spc0end + load_and_run_spc spc1, spc1end + load_and_run_spc spc2, spc2end + + ldx #txt_success + ldy #$32 + jsr write_text +@end: jmp @end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init_regs: + lda #$8F ; screen off + sta $2100 + + stz $2105 ; BG mode 0, 8x8 tiles + stz $2106 ; No mosaic + stz $2107 ; BG1: 32x32 tilemap at address 0 + lda #$04 + sta $210B ; BG1 tiles at byte $8000 / word $4000 + stz $210D ; BG1HOFS = 0 + stz $210D + lda #$FF + sta $210E ; BG1VOFS = -1 + sta $210E + lda #$80 + sta $2115 ; VMAIN: inc address by 1 after high byte + stz $2121 ; Palette addr = 0 + stz $2122 + stz $2122 ; palette 0 = black + lda #$FF + sta $2122 + sta $2122 ; palette 1 = white + lda #$01 + sta $212C ; enable BG1 + stz $212D ; disable subscreen + stz $212E ; no window masking + stz $2130 ; no window force black + lda #$30 + sta $2131 ; no color math + stz $2133 ; no hires/interlace/overscan + stz $4200 ; no NMI, IRQ, joypad autoread + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +init_video_mem: + ; clear vmem + stz $2116 + stz $2117 ; VADDR = 0 + + lda #$09 + sta $4300 ; DMA0: to ppu, write to 2 registers, no increment + lda #$18 + sta $4301 ; DMA0: Write to PPU 2118/2119 (VMDATA) + lda #zero + sta $4303 + lda #^zero + sta $4304 + stz $4305 + stz $4306 ; 65536 bytes + lda #$01 + sta $420B ; run DMA0 + + ; copy font to vmem + stz $2116 + lda #$40 + sta $2117 ; VADDR = $4000 (word address) + lda #$01 + sta $4300 ; DMA0: to ppu, 2 bytes->2 registers, inc by 1 + lda #font + sta $4303 + lda #^font + sta $4304 + stz $4305 + lda #$08 + sta $4306 ; 2048 bytes + lda #$01 + sta $420B ; run DMA0 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; 0:x = text (null-terminated). y = vmem word address +write_text: + sty $2116 +@loop: + lda $00,x + beq @end + sta $2118 + stz $2119 + inx + bra @loop +@end: + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +; a = val. y = vmem word address +write_hex8: + sty $2116 + pha + lsr a + lsr a + lsr a + lsr a + clc + jsr @write_digit + pla + and #$0F +@write_digit: ; write hex digit in A + cmp #$0A + bcc @num + clc + adc #'A'-$0A-'0' +@num: + clc + adc #'0' + sta $2118 + stz $2119 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +; 0:x = address. y = vmem word address +write_hex16: + lda $01,x + jsr write_hex8 + lda $00,x + iny + iny + jsr write_hex8 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +; Input: a = bank, x = addr, y = size +load_spc: + stx spc_addr + sty spc_size + pha + plb ; DBR = bank + + ldx #$BBAA +@wait1: + cpx $2140 + bne @wait1 + + ldx #$300 ; dest address + stx $2142 + lda #$CC + sta $2141 ; any nonzero value + sta $2140 +@wait2: + cmp $2140 + bne @wait2 + + ldy #$0000 +load_spc_loop: + lda (spc_addr),y + sta $2141 + tya + sta $2140 + +@wait3: + cmp $2140 + bne @wait3 + + iny + cpy spc_size + bne load_spc_loop + + ldx #$300 ; execution address + stx $2142 + stz $2141 + ina + ina + sta $2140 + +@wait4: ; wait for acknowledgement + cmp $2140 + bne @wait4 + + ; IPL protocol ends here + + ; wait until port0 == 0 +@wait5: + lda $2140 + bne @wait5 + + ldx last_test_num + stx $2142 ; port 2/3 = 1 less than next test num (will be checked by SPC) + + lda #$01 + sta $2141 ; set port1 = 1 + + lda #$00 ; reset DBR to 0 + pha + plb + + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +update_test_num: + ldx $2142 + stx last_test_num + ldx #$2142 + ldy #$6E + jmp write_hex16 + rts + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + +wait_result: +@wait1: + jsr update_test_num ; This may not have effect while rendering, but we repeat it later anyway + lda $2140 + beq @wait1 + + jsr wait_for_vblank + jsr update_test_num + lda $2140 + cmp #$01 + bne @failed + + ; Tests succeeded + stz $2141 ; port1 = 0 (tell SPC to continue into IPL ROM) + rts + +@failed: + ldx #txt_fail + ldy #$32 + jsr write_text + ldx #txt_a + ldy #$A1 + jsr write_text + ldx #txt_x + ldy #$C1 + jsr write_text + ldx #txt_y + ldy #$E1 + jsr write_text + ldx #txt_p + ldy #$101 + jsr write_text + + lda $2141 ; PSW + ldy #$105 + jsr write_hex8 + + lda #$02 + sta $2141 + + lda #$03 +@wait3: + cmp $2140 + bne @wait3 + + lda $2141 ; a + ldy #$A5 + jsr write_hex8 + + lda $2142 ; x + ldy #$C5 + jsr write_hex8 + + lda $2143 ; y + ldy #$E5 + jsr write_hex8 + +@end: bra @end + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; + + +wait_for_vblank: +@wait1: + bit $4210 + bmi @wait1 +@wait2: + bit $4210 + bpl @wait2 + rts + + +.segment "RODATA" +txt_running: .byte "Running tests...", 0 +txt_success: .byte "Success", 0 +txt_fail: .byte "Failed", 0 +txt_testnum: .byte "Test number:", 0 +txt_a: .byte "A = ", 0 +txt_x: .byte "X = ", 0 +txt_y: .byte "Y = ", 0 +txt_p: .byte "P = ", 0 +zero: + .byte 0, 0 +font: + .incbin "font.bin" + +spc0: + .incbin "spc_tests0.spc", $300 +spc0end: + +.segment "BANK1" +spc1: + .incbin "spc_tests1.spc", $300 +spc1end: + +.segment "BANK2" +spc2: + .incbin "spc_tests2.spc", $300 +spc2end: diff --git a/roms/snes-tests/spctest/spctest.sfc b/roms/snes-tests/spctest/spctest.sfc new file mode 100644 index 00000000..e2f368ad Binary files /dev/null and b/roms/snes-tests/spctest/spctest.sfc differ diff --git a/roms/snes/UPSTREAM.md b/roms/snes/UPSTREAM.md new file mode 100644 index 00000000..2fdd7897 --- /dev/null +++ b/roms/snes/UPSTREAM.md @@ -0,0 +1,4 @@ +# Upstreams + +- peter-lemon-snes +https://github.com/PeterLemon/SNES diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.asm b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.asm new file mode 100644 index 00000000..0c691ba0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.asm @@ -0,0 +1,76 @@ +// SNES Bank HiROM/FastROM demo by krom (Peter Lemon): +// 1. Jump To Bank Code +// 2. DMA Loads Palette Data To CGRAM +// 3. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 4. DMA Clears VRAM Map To A Space " " Character +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "BANKHiROMFastROM.sfc", create + +macro seek(variable offset) { + origin offset & $3FFFFF + base offset | $C00000 // HiROM/FastROM +} + +seek($0000); fill $20000 // Fill Upto $1FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(FASTROM) // Run SNES Initialisation Routine + jml Bank1 // Jump To Bank 1 + +// BANK 1 +seek($10000); Bank1: + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Title Text + LoadLOVRAM(Title, $F882, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + LoadLOVRAM(PageBreak, $F8C2, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Text + LoadLOVRAM(BANKTEXT, $F942, 30, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +Title: + db "Bank Test HiROM/FastROM ($C0):" + +PageBreak: + db "------------------------------" + +BANKTEXT: + db "Jump To Bank 1 ($C1) PASSED" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.png b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.png new file mode 100644 index 00000000..e5df657b Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.png differ diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.sfc b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.sfc new file mode 100644 index 00000000..fdae1c65 Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.sfc differ diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/Font8x8.asm b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES.INC b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..29fc4afb --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "BANK HIROM FASTROM " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $21 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/make.bat b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/make.bat new file mode 100644 index 00000000..a5e22648 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMFastROM/make.bat @@ -0,0 +1 @@ +bass BANKHiROMFastROM.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.asm b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.asm new file mode 100644 index 00000000..8ea93075 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.asm @@ -0,0 +1,76 @@ +// SNES Bank HiROM/SlowROM demo by krom (Peter Lemon): +// 1. Jump To Bank Code +// 2. DMA Loads Palette Data To CGRAM +// 3. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 4. DMA Clears VRAM Map To A Space " " Character +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "BANKHiROMSlowROM.sfc", create + +macro seek(variable offset) { + origin offset & $3FFFFF + base offset | $400000 // HiROM/SlowROM +} + +seek($0000); fill $20000 // Fill Upto $1FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + jml Bank1 // Jump To Bank 1 + +// BANK 1 +seek($10000); Bank1: + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Title Text + LoadLOVRAM(Title, $F882, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + LoadLOVRAM(PageBreak, $F8C2, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Text + LoadLOVRAM(BANKTEXT, $F942, 30, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +Title: + db "Bank Test HiROM/SlowROM ($40):" + +PageBreak: + db "------------------------------" + +BANKTEXT: + db "Jump To Bank 1 ($41) PASSED" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.png b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.png new file mode 100644 index 00000000..f11d17e0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.png differ diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.sfc b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.sfc new file mode 100644 index 00000000..d38b02af Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.sfc differ diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/Font8x8.asm b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES.INC b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..3c6c6c60 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "BANK HIROM SLOWROM " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $21 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/make.bat b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/make.bat new file mode 100644 index 00000000..1da82d6a --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/HiROMSlowROM/make.bat @@ -0,0 +1 @@ +bass BANKHiROMSlowROM.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.asm b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.asm new file mode 100644 index 00000000..9f7d925b --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.asm @@ -0,0 +1,76 @@ +// SNES Bank LoROM/FastROM demo by krom (Peter Lemon): +// 1. Jump To Bank Code +// 2. DMA Loads Palette Data To CGRAM +// 3. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 4. DMA Clears VRAM Map To A Space " " Character +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "BANKLoROMFastROM.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset | $800000 // LoROM/FastROM +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(FASTROM) // Run SNES Initialisation Routine + jml Bank1 // Jump To Bank 1 + +// BANK 1 +seek($18000); Bank1: + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Title Text + LoadLOVRAM(Title, $F882, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + LoadLOVRAM(PageBreak, $F8C2, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Text + LoadLOVRAM(BANKTEXT, $F942, 30, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +Title: + db "Bank Test LoROM/FastROM ($80):" + +PageBreak: + db "------------------------------" + +BANKTEXT: + db "Jump To Bank 1 ($81) PASSED" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.png b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.png new file mode 100644 index 00000000..b73a6ad7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.png differ diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.sfc b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.sfc new file mode 100644 index 00000000..ff3db935 Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.sfc differ diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/Font8x8.asm b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES.INC b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..18020047 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "BANK LOROM FASTROM " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/make.bat b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/make.bat new file mode 100644 index 00000000..43974fb5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMFastROM/make.bat @@ -0,0 +1 @@ +bass BANKLoROMFastROM.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.asm b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.asm new file mode 100644 index 00000000..faf71af0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.asm @@ -0,0 +1,76 @@ +// SNES Bank LoROM/SlowROM demo by krom (Peter Lemon): +// 1. Jump To Bank Code +// 2. DMA Loads Palette Data To CGRAM +// 3. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 4. DMA Clears VRAM Map To A Space " " Character +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "BANKLoROMSlowROM.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset // LoROM/SlowROM +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + jml Bank1 // Jump To Bank 1 + +// BANK 1 +seek($18000); Bank1: + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Title Text + LoadLOVRAM(Title, $F882, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + LoadLOVRAM(PageBreak, $F8C2, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Text + LoadLOVRAM(BANKTEXT, $F942, 30, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +Title: + db "Bank Test LoROM/SlowROM ($00):" + +PageBreak: + db "------------------------------" + +BANKTEXT: + db "Jump To Bank 1 ($01) PASSED" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.png b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.png new file mode 100644 index 00000000..c8ed4cca Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.png differ diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.sfc b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.sfc new file mode 100644 index 00000000..39ff689d Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.sfc differ diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/Font8x8.asm b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES.INC b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c9c43594 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "BANK LOROM SLOWROM " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/make.bat b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/make.bat new file mode 100644 index 00000000..83840b56 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/LoROMSlowROM/make.bat @@ -0,0 +1 @@ +bass BANKLoROMSlowROM.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.asm b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.asm new file mode 100644 index 00000000..b8357e7c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.asm @@ -0,0 +1,91 @@ +// SNES Bank WRAM demo by krom (Peter Lemon): +// 1. Jump To Bank Code +// 2. DMA Loads Palette Data To CGRAM +// 3. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 4. DMA Clears VRAM Map To A Space " " Character +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "BANKWRAM.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset // LoROM/SlowROM +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Setup WRAM Code + rep #$20 // Set 16-Bit Accumulator + lda.w #WRAMEnd-WRAMStart // A = Length + ldx.w #WRAMStart // X = Source + ldy.w #$0000 // Y = Destination + mvn $7F=$00 // Block Move + sep #$20 // Set 8-Bit Accumulator + + // Reset Data Bank + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7F0000 // Jump To Bank 1 + +WRAMStart: + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Title Text + LoadLOVRAM(Title, $F882, 21, 0) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + LoadLOVRAM(PageBreak, $F8C2, 30, 0) // Load Text To VRAM Lo Bytes + + // Print Text + LoadLOVRAM(BANKTEXT, $F942, 30, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + bra Loop + +WRAMEnd: + +Title: + db "Bank Test WRAM ($7E):" + +PageBreak: + db "------------------------------" + +BANKTEXT: + db "Jump To Bank 1 ($7F) PASSED" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.png b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.png new file mode 100644 index 00000000..b1641c3a Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.png differ diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.sfc b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.sfc new file mode 100644 index 00000000..6fbca1db Binary files /dev/null and b/roms/snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.sfc differ diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/Font8x8.asm b/roms/snes/peter-lemon-snes/BANK/WRAM/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES.INC b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..1e51ad2d --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "BANK WRAM " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/BANK/WRAM/make.bat b/roms/snes/peter-lemon-snes/BANK/WRAM/make.bat new file mode 100644 index 00000000..e76afccc --- /dev/null +++ b/roms/snes/peter-lemon-snes/BANK/WRAM/make.bat @@ -0,0 +1 @@ +bass BANKWRAM.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.asm new file mode 100644 index 00000000..0202fcf3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x128 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x128FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x128FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.png new file mode 100644 index 00000000..4cb7eb55 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.sfc new file mode 100644 index 00000000..139a18a8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly_gsu.asm new file mode 100644 index 00000000..3b82e6b0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly_gsu.asm @@ -0,0 +1,323 @@ +// SNES GSU 2BPP 256x128 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*128)/4 // R3 = SRAM Destination + iwt r12, #(128*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*128)/4)+64 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*128)/4)+256+64 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #32 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e132b230 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/make.bat new file mode 100644 index 00000000..e68d0240 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x128FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.asm new file mode 100644 index 00000000..69605a3a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x160 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x160FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x160FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.png new file mode 100644 index 00000000..5879f43b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.sfc new file mode 100644 index 00000000..81c29525 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly_gsu.asm new file mode 100644 index 00000000..a7f86eca --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly_gsu.asm @@ -0,0 +1,387 @@ +// SNES GSU 2BPP 256x160 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*160)/4 // R3 = SRAM Destination + iwt r12, #(160*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*160)/4)+96 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*160)/4)+320+96 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #48 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e132b230 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/make.bat new file mode 100644 index 00000000..a4f30a3f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x160FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.asm new file mode 100644 index 00000000..91e90253 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.asm @@ -0,0 +1,150 @@ +// SNES GSU 2BPP 256x192 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x192FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA Source + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x192FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.png new file mode 100644 index 00000000..7f81b320 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.sfc new file mode 100644 index 00000000..e3a1cdd4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly_gsu.asm new file mode 100644 index 00000000..b4c1eb5e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly_gsu.asm @@ -0,0 +1,451 @@ +// SNES GSU 2BPP 256x192 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*192)/4 // R3 = SRAM Destination + iwt r12, #(192*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*192)/4)+128 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*192)/4)+384+128 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #64 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e132b230 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/make.bat new file mode 100644 index 00000000..7a3e0a07 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x192FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.asm new file mode 100644 index 00000000..fb75975f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x128 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x128PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x128PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.png new file mode 100644 index 00000000..e3fc5e73 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.sfc new file mode 100644 index 00000000..b8c22597 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine_gsu.asm new file mode 100644 index 00000000..f13099a6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 2BPP 256x128 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #127 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..dc7dc6af --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/make.bat new file mode 100644 index 00000000..ed60ed2b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x128PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.asm new file mode 100644 index 00000000..cfe64230 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x160 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x160PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x160PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.png new file mode 100644 index 00000000..4cdd55ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.sfc new file mode 100644 index 00000000..4faec30e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine_gsu.asm new file mode 100644 index 00000000..68839575 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 2BPP 256x160 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #159 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..dc7dc6af --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/make.bat new file mode 100644 index 00000000..5bccd215 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x160PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.asm new file mode 100644 index 00000000..b9f422e3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.asm @@ -0,0 +1,150 @@ +// SNES GSU 2BPP 256x192 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x192PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA Source + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x192PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.png new file mode 100644 index 00000000..ca810e68 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.sfc new file mode 100644 index 00000000..4cf3809c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine_gsu.asm new file mode 100644 index 00000000..ab6e9f95 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 2BPP 256x192 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #191 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..dc7dc6af --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/make.bat new file mode 100644 index 00000000..4cc0d5ef --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x192PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.asm new file mode 100644 index 00000000..4a64fa43 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x128 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x128PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x128PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.png new file mode 100644 index 00000000..52131e4e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.sfc new file mode 100644 index 00000000..a6b785e7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel_gsu.asm new file mode 100644 index 00000000..43b73c16 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 2BPP 256x128 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #63 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d93fe926 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/make.bat new file mode 100644 index 00000000..93fb3cc5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x128PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.asm new file mode 100644 index 00000000..4801a32a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.asm @@ -0,0 +1,142 @@ +// SNES GSU 2BPP 256x160 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x160PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x160PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.png new file mode 100644 index 00000000..46066221 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.sfc new file mode 100644 index 00000000..774f28fb Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel_gsu.asm new file mode 100644 index 00000000..c2b67773 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 2BPP 256x160 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #79 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d93fe926 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/make.bat new file mode 100644 index 00000000..1eb31de4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x160PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.asm new file mode 100644 index 00000000..e58a6634 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.asm @@ -0,0 +1,150 @@ +// SNES GSU 2BPP 256x192 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU2BPP256x192PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA Source + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU2BPP256x192PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.png new file mode 100644 index 00000000..38530ac1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.sfc new file mode 100644 index 00000000..38261127 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel_gsu.asm new file mode 100644 index 00000000..4753a48b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 2BPP 256x192 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/8 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #95 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d93fe926 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 2BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/make.bat new file mode 100644 index 00000000..af9d64c2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/make.bat @@ -0,0 +1 @@ +bass GSU2BPP256x192PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.asm new file mode 100644 index 00000000..b63a6e08 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.asm @@ -0,0 +1,149 @@ +// SNES GSU 4BPP 256x128 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x128FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x128FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.png new file mode 100644 index 00000000..73bd2bb8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.sfc new file mode 100644 index 00000000..db7aca4c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly_gsu.asm new file mode 100644 index 00000000..f54731be --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly_gsu.asm @@ -0,0 +1,323 @@ +// SNES GSU 4BPP 256x128 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*128)/2 // R3 = SRAM Destination + iwt r12, #(128*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*128)/2)+64 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*128)/2)+256+64 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #32 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..167005b5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/make.bat new file mode 100644 index 00000000..12449807 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x128FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.asm new file mode 100644 index 00000000..66cd5bfd --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.asm @@ -0,0 +1,146 @@ +// SNES GSU 4BPP 256x160 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x160FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x160FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.png new file mode 100644 index 00000000..8cfaa1f6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.sfc new file mode 100644 index 00000000..bdffa5d1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly_gsu.asm new file mode 100644 index 00000000..2e67b444 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly_gsu.asm @@ -0,0 +1,387 @@ +// SNES GSU 4BPP 256x160 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*160)/2 // R3 = SRAM Destination + iwt r12, #(160*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*160)/2)+96 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*160)/2)+320+96 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #48 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..167005b5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/make.bat new file mode 100644 index 00000000..c50d5dcf --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x160FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.asm new file mode 100644 index 00000000..0bbac538 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.asm @@ -0,0 +1,154 @@ +// SNES GSU 4BPP 256x192 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x192FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x192FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.png new file mode 100644 index 00000000..d5c4ce7e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.sfc new file mode 100644 index 00000000..f2f700f4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly_gsu.asm new file mode 100644 index 00000000..ff87f035 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly_gsu.asm @@ -0,0 +1,451 @@ +// SNES GSU 4BPP 256x192 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #(256*192)/2 // R3 = SRAM Destination + iwt r12, #(192*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #((256*192)/2)+128 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #((256*192)/2)+384+128 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #64 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..167005b5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/make.bat new file mode 100644 index 00000000..1734c9d3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x192FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.asm new file mode 100644 index 00000000..ca3e7e99 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.asm @@ -0,0 +1,149 @@ +// SNES GSU 4BPP 256x128 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x128PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x128PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.png new file mode 100644 index 00000000..a95f0ca1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.sfc new file mode 100644 index 00000000..50921d96 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine_gsu.asm new file mode 100644 index 00000000..896da3ef --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 4BPP 256x128 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #127 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c19951bc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/make.bat new file mode 100644 index 00000000..b7fbdd46 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x128PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.asm new file mode 100644 index 00000000..6472808c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.asm @@ -0,0 +1,146 @@ +// SNES GSU 4BPP 256x160 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x160PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x160PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.png new file mode 100644 index 00000000..157288f8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.sfc new file mode 100644 index 00000000..75b8729f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine_gsu.asm new file mode 100644 index 00000000..2080f1d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 4BPP 256x160 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #159 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c19951bc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/make.bat new file mode 100644 index 00000000..7dc4ef8c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x160PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.asm new file mode 100644 index 00000000..8c3d3dbb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.asm @@ -0,0 +1,154 @@ +// SNES GSU 4BPP 256x192 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x192PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x192PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.png new file mode 100644 index 00000000..304879c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.sfc new file mode 100644 index 00000000..f49c1656 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine_gsu.asm new file mode 100644 index 00000000..e0579b41 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 4BPP 256x192 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #191 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c19951bc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/make.bat new file mode 100644 index 00000000..b1d9eeee --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x192PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.asm new file mode 100644 index 00000000..bd530a8c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.asm @@ -0,0 +1,149 @@ +// SNES GSU 4BPP 256x128 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x128PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + sta.w REG_MDMAEN // $420B: DMA Enable + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x128PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.png new file mode 100644 index 00000000..6d3f5759 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.sfc new file mode 100644 index 00000000..2de8980d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel_gsu.asm new file mode 100644 index 00000000..05bee629 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 4BPP 256x128 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #63 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..adca4da3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/make.bat new file mode 100644 index 00000000..536d7bd0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x128PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.asm new file mode 100644 index 00000000..ce5b8fb2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.asm @@ -0,0 +1,146 @@ +// SNES GSU 4BPP 256x160 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x160PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$2800 // Set Size In Bytes To DMA Transfer + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + WaitNMI() + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x160PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.png new file mode 100644 index 00000000..057715a1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.sfc new file mode 100644 index 00000000..c4b432cf Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel_gsu.asm new file mode 100644 index 00000000..95617df0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 4BPP 256x160 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #79 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..adca4da3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/make.bat new file mode 100644 index 00000000..056b668a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x160PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.asm new file mode 100644 index 00000000..694757a8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.asm @@ -0,0 +1,154 @@ +// SNES GSU 4BPP 256x192 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU4BPP256x192PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_4BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU4BPP256x192PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.png new file mode 100644 index 00000000..845c9fbd Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.sfc new file mode 100644 index 00000000..75bb113e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel_gsu.asm new file mode 100644 index 00000000..a58c5347 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 4BPP 256x192 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/4 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #95 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..adca4da3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 4BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/make.bat new file mode 100644 index 00000000..bb5511af --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/make.bat @@ -0,0 +1 @@ +bass GSU4BPP256x192PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.asm new file mode 100644 index 00000000..63cac0ba --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x128 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x128FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x128FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.png new file mode 100644 index 00000000..706110ff Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.sfc new file mode 100644 index 00000000..7f3e60eb Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly_gsu.asm new file mode 100644 index 00000000..e90494c5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly_gsu.asm @@ -0,0 +1,323 @@ +// SNES GSU 8BPP 256x128 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #256*128 // R3 = SRAM Destination + iwt r12, #(128*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #(256*128)+64 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #(256*128)+256+64 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #32 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..343da98e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/make.bat new file mode 100644 index 00000000..550a2a5a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x128FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.asm new file mode 100644 index 00000000..55940302 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x160 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x160FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3556 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #3 // Y = 3 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #193 // Compare Scanline Y To 193 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x160FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.png new file mode 100644 index 00000000..4af0d4f7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.sfc new file mode 100644 index 00000000..bd207de8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly_gsu.asm new file mode 100644 index 00000000..2db075cd --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly_gsu.asm @@ -0,0 +1,387 @@ +// SNES GSU 8BPP 256x160 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #256*160 // R3 = SRAM Destination + iwt r12, #(160*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #(256*160)+96 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #(256*160)+320+96 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #48 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..343da98e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/make.bat new file mode 100644 index 00000000..f8595012 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x160FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.asm new file mode 100644 index 00000000..c468b46a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.asm @@ -0,0 +1,154 @@ +// SNES GSU 8BPP 256x192 Fill Poly Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x192FillPoly.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #4 // Y = 4 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x192FillPoly_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.png new file mode 100644 index 00000000..5b18d8e6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.sfc new file mode 100644 index 00000000..132c99d2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly_gsu.asm new file mode 100644 index 00000000..a268726e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly_gsu.asm @@ -0,0 +1,451 @@ +// SNES GSU 8BPP 256x192 Fill Poly Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Copy Scan Left/Right Data To RAM + iwt r14, #ScanLeft // R14 = ROM Address + iwt r3, #256*192 // R3 = SRAM Destination + iwt r12, #(192*2)*2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + getbl // R0 = ROM Byte Lo + inc r14 // R14++ + getbh // R0 = ROM Byte Lo/Hi (ROM Word) + inc r14 // R14++ + stw (r3) // Store R0 To RAM + inc r3 // R3++ + loop // IF (Loop Count != 0) Loop + inc r3 // R3++ (Delay Slot) + + // Fill Poly + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + iwt r3, #(256*192)+128 // R3 = Scan Left RAM Address + Poly Top Scanline + iwt r4, #(256*192)+384+128 // R4 = Scan Right RAM Address + Poly Top Scanline + ibt r2, #64 // R2 = Plot Y Position + ibt r5, #63 // R5 = Fill Y Count (Poly Bottom Scanline - Poly Top Scanline) + + LoopFill: + to r1 ; ldw (r3) // R1 = Scan Left Plot X Position + ldw (r4) // R0 = Scan Right Plot X Position + to r12 ; sub r1 // R12 = Fill Length (Scan Right Plot X - Scan Left Plot X) + inc r12 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + loop // IF (Loop Count != 0) Loop + plot // Plot Color, R1++ (Delay Slot) + + inc r3 // Scan Left RAM Address++ + inc r3 // Scan Left RAM Address++ + inc r4 // Scan Right RAM Address++ + inc r4 // Scan Right RAM Address++ + dec r5 // Fill Y Count-- + bne LoopFill // IF (Fill Y Count != 0) Loop Fill + inc r2 // Plot Y Position++ (Delay Slot) + + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot + +ScanLeft: // Left Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 126 + dw 125 + dw 124 + dw 123 + dw 122 + dw 121 + dw 120 + dw 119 + dw 118 + dw 117 + dw 116 + dw 115 + dw 114 + dw 113 + dw 112 + dw 111 + dw 110 + dw 109 + dw 108 + dw 107 + dw 106 + dw 105 + dw 104 + dw 103 + dw 102 + dw 101 + dw 100 + dw 99 + dw 98 + dw 97 + dw 96 + dw 97 + dw 98 + dw 99 + dw 100 + dw 101 + dw 102 + dw 103 + dw 104 + dw 105 + dw 106 + dw 107 + dw 108 + dw 109 + dw 110 + dw 111 + dw 112 + dw 113 + dw 114 + dw 115 + dw 116 + dw 117 + dw 118 + dw 119 + dw 120 + dw 121 + dw 122 + dw 123 + dw 124 + dw 125 + dw 126 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + +ScanRight: // Right Hand Scanline X Buffer (Size Of Screen Y) + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 127 + dw 128 + dw 129 + dw 130 + dw 131 + dw 132 + dw 133 + dw 134 + dw 135 + dw 136 + dw 137 + dw 138 + dw 139 + dw 140 + dw 141 + dw 142 + dw 143 + dw 144 + dw 145 + dw 146 + dw 147 + dw 148 + dw 149 + dw 150 + dw 151 + dw 152 + dw 153 + dw 154 + dw 155 + dw 156 + dw 157 + dw 158 + dw 157 + dw 156 + dw 155 + dw 154 + dw 153 + dw 152 + dw 151 + dw 150 + dw 149 + dw 148 + dw 147 + dw 146 + dw 145 + dw 144 + dw 143 + dw 142 + dw 141 + dw 140 + dw 139 + dw 138 + dw 137 + dw 136 + dw 135 + dw 134 + dw 133 + dw 132 + dw 131 + dw 130 + dw 129 + dw 128 + dw 127 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 + dw 0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..343da98e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP FILL POLY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/make.bat new file mode 100644 index 00000000..cc5d3956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x192FillPoly.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.asm new file mode 100644 index 00000000..c37cfc01 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x128 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x128PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x128PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.png new file mode 100644 index 00000000..b69f1e26 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.sfc new file mode 100644 index 00000000..84224730 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine_gsu.asm new file mode 100644 index 00000000..504b79f2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 8BPP 256x128 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #127 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d29035d6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/make.bat new file mode 100644 index 00000000..7c7aa27e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x128PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.asm new file mode 100644 index 00000000..854af6a8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x160 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x160PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3556 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #3 // Y = 3 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #193 // Compare Scanline Y To 193 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x160PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.png new file mode 100644 index 00000000..49ca3ab4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.sfc new file mode 100644 index 00000000..f795b400 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine_gsu.asm new file mode 100644 index 00000000..ed66bff2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 8BPP 256x160 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #159 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d29035d6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/make.bat new file mode 100644 index 00000000..7d4161bf --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x160PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.asm new file mode 100644 index 00000000..babff94f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.asm @@ -0,0 +1,154 @@ +// SNES GSU 8BPP 256x192 Plot Line Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x192PlotLine.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #4 // Y = 4 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x192PlotLine_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.png new file mode 100644 index 00000000..47590d36 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.sfc new file mode 100644 index 00000000..2f043292 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine_gsu.asm new file mode 100644 index 00000000..646e2bf3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine_gsu.asm @@ -0,0 +1,86 @@ +// SNES GSU 8BPP 256x192 Plot Line Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Line Color From X0/Y0 To X1/Y1 Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + + iwt r1, #0 // R1 = X0 + iwt r2, #0 // R2 = Y0 + iwt r3, #255 // R3 = X1 + iwt r4, #191 // R4 = Y1 + + with r5 ; sub r5 // R5 = 0 + with r3 ; sub r1 // R3 = DX (X1 - X0) + bpl SXPos + inc r5 // IF (X1 > X0), R5 (SX) = 1 (Delay Slot) + dec r5 // IF (X1 < X0), R5 (SX) = -1 + dec r5 // R5 = -1 + with r3 ; not // R3 ~= R3 + inc r3 // R3 = ABS(DX) + SXPos: + + with r6 ; sub r6 // R6 = 0 + with r4 ; sub r2 // R4 = DY (Y1 - Y0) + bpl SYPos + inc r6 // IF (Y1 > Y0), R6 (SY) = 1 (Delay Slot) + dec r6 // IF (Y1 < Y0), R6 (SY) = -1 + dec r6 // R6 = -1 + with r4 ; not // R4 ~= R4 + inc r4 // R4 = ABS(DY) + SYPos: + + from r3 ; cmp r4 // Compare DX To DY + blt YMajor // IF (DX < DY) Y Major, Else X Major + plot // Plot Color (R1++) (Delay Slot) + + from r3 ; lsr // IF (DX >= DY), R0 (X Error) = R3 (DX) / 2 (X Error = DX / 2) + move r12, r3 // R12 = Loop Count (DX) + move r13, r15 // R13 = Loop Address + // LoopX: + sub r4 // Subtract R4 (DY) From R0 (X Error) & Compare R4 (X Error) To Zero (X Error -= DY) + bge XEnd + dec r1 // R1-- (Delay Slot) + with r2 ; add r6 // IF (X Error < 0), Add R6 (SY) To R2 (Y0) (Y0 += SY) + add r3 // IF (X Error < 0), Add R3 (DX) To R0 (X Error) (X Error += DX) + XEnd: + with r1 ; add r5 // Add R5 (SX) To R1 (X0) (X0 += SX) + loop // LoopX, IF (X0 == X1), Line End + plot // Plot Color (R1++) (Delay Slot) + bra LineEnd + + YMajor: + from r4 ; lsr // IF (DX < DY), R0 (Y Error) = R4 (DY) / 2 (Y Error = DY / 2) + move r12, r4 // R12 = Loop Count (DY) + move r13, r15 // R13 = Loop Address + // LoopY: + sub r3 // Subtract R3 (DX) From R0 (Y Error) & Compare R1 (Y Error) To Zero + bge YEnd + dec r1 // R1-- (Delay Slot) + with r1 ; add r5 // IF (Y Error < 0), Add R5 (SX) To R1 (X0) (X0 += SX) + add r4 // IF (Y Error < 0), Add R4 (DY) To R0 (Y Error) (Y Error += DY) + YEnd: + with r2 ; add r6 // Add R6 (SY) To R2 (Y0) (Y0 += SY) + loop // LoopY, IF (Y0 == Y1), Line End + plot // Plot Color (R1++) (Delay Slot) + + LineEnd: + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d29035d6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT LINE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/make.bat new file mode 100644 index 00000000..aa420f9c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x192PlotLine.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU256x128Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU256x128Map.asm new file mode 100644 index 00000000..3e799956 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU256x128Map.asm @@ -0,0 +1,32 @@ +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0000,$0010,$0020,$0030,$0040,$0050,$0060,$0070,$0080,$0090,$00A0,$00B0,$00C0,$00D0,$00E0,$00F0,$0100,$0110,$0120,$0130,$0140,$0150,$0160,$0170,$0180,$0190,$01A0,$01B0,$01C0,$01D0,$01E0,$01F0 +dw $0001,$0011,$0021,$0031,$0041,$0051,$0061,$0071,$0081,$0091,$00A1,$00B1,$00C1,$00D1,$00E1,$00F1,$0101,$0111,$0121,$0131,$0141,$0151,$0161,$0171,$0181,$0191,$01A1,$01B1,$01C1,$01D1,$01E1,$01F1 +dw $0002,$0012,$0022,$0032,$0042,$0052,$0062,$0072,$0082,$0092,$00A2,$00B2,$00C2,$00D2,$00E2,$00F2,$0102,$0112,$0122,$0132,$0142,$0152,$0162,$0172,$0182,$0192,$01A2,$01B2,$01C2,$01D2,$01E2,$01F2 +dw $0003,$0013,$0023,$0033,$0043,$0053,$0063,$0073,$0083,$0093,$00A3,$00B3,$00C3,$00D3,$00E3,$00F3,$0103,$0113,$0123,$0133,$0143,$0153,$0163,$0173,$0183,$0193,$01A3,$01B3,$01C3,$01D3,$01E3,$01F3 +dw $0004,$0014,$0024,$0034,$0044,$0054,$0064,$0074,$0084,$0094,$00A4,$00B4,$00C4,$00D4,$00E4,$00F4,$0104,$0114,$0124,$0134,$0144,$0154,$0164,$0174,$0184,$0194,$01A4,$01B4,$01C4,$01D4,$01E4,$01F4 +dw $0005,$0015,$0025,$0035,$0045,$0055,$0065,$0075,$0085,$0095,$00A5,$00B5,$00C5,$00D5,$00E5,$00F5,$0105,$0115,$0125,$0135,$0145,$0155,$0165,$0175,$0185,$0195,$01A5,$01B5,$01C5,$01D5,$01E5,$01F5 +dw $0006,$0016,$0026,$0036,$0046,$0056,$0066,$0076,$0086,$0096,$00A6,$00B6,$00C6,$00D6,$00E6,$00F6,$0106,$0116,$0126,$0136,$0146,$0156,$0166,$0176,$0186,$0196,$01A6,$01B6,$01C6,$01D6,$01E6,$01F6 +dw $0007,$0017,$0027,$0037,$0047,$0057,$0067,$0077,$0087,$0097,$00A7,$00B7,$00C7,$00D7,$00E7,$00F7,$0107,$0117,$0127,$0137,$0147,$0157,$0167,$0177,$0187,$0197,$01A7,$01B7,$01C7,$01D7,$01E7,$01F7 +dw $0008,$0018,$0028,$0038,$0048,$0058,$0068,$0078,$0088,$0098,$00A8,$00B8,$00C8,$00D8,$00E8,$00F8,$0108,$0118,$0128,$0138,$0148,$0158,$0168,$0178,$0188,$0198,$01A8,$01B8,$01C8,$01D8,$01E8,$01F8 +dw $0009,$0019,$0029,$0039,$0049,$0059,$0069,$0079,$0089,$0099,$00A9,$00B9,$00C9,$00D9,$00E9,$00F9,$0109,$0119,$0129,$0139,$0149,$0159,$0169,$0179,$0189,$0199,$01A9,$01B9,$01C9,$01D9,$01E9,$01F9 +dw $000A,$001A,$002A,$003A,$004A,$005A,$006A,$007A,$008A,$009A,$00AA,$00BA,$00CA,$00DA,$00EA,$00FA,$010A,$011A,$012A,$013A,$014A,$015A,$016A,$017A,$018A,$019A,$01AA,$01BA,$01CA,$01DA,$01EA,$01FA +dw $000B,$001B,$002B,$003B,$004B,$005B,$006B,$007B,$008B,$009B,$00AB,$00BB,$00CB,$00DB,$00EB,$00FB,$010B,$011B,$012B,$013B,$014B,$015B,$016B,$017B,$018B,$019B,$01AB,$01BB,$01CB,$01DB,$01EB,$01FB +dw $000C,$001C,$002C,$003C,$004C,$005C,$006C,$007C,$008C,$009C,$00AC,$00BC,$00CC,$00DC,$00EC,$00FC,$010C,$011C,$012C,$013C,$014C,$015C,$016C,$017C,$018C,$019C,$01AC,$01BC,$01CC,$01DC,$01EC,$01FC +dw $000D,$001D,$002D,$003D,$004D,$005D,$006D,$007D,$008D,$009D,$00AD,$00BD,$00CD,$00DD,$00ED,$00FD,$010D,$011D,$012D,$013D,$014D,$015D,$016D,$017D,$018D,$019D,$01AD,$01BD,$01CD,$01DD,$01ED,$01FD +dw $000E,$001E,$002E,$003E,$004E,$005E,$006E,$007E,$008E,$009E,$00AE,$00BE,$00CE,$00DE,$00EE,$00FE,$010E,$011E,$012E,$013E,$014E,$015E,$016E,$017E,$018E,$019E,$01AE,$01BE,$01CE,$01DE,$01EE,$01FE +dw $000F,$001F,$002F,$003F,$004F,$005F,$006F,$007F,$008F,$009F,$00AF,$00BF,$00CF,$00DF,$00EF,$00FF,$010F,$011F,$012F,$013F,$014F,$015F,$016F,$017F,$018F,$019F,$01AF,$01BF,$01CF,$01DF,$01EF,$01FF +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 +dw $0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200,$0200 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.asm new file mode 100644 index 00000000..f18baa6b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x128 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x128PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H128) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #2 // Y = 2 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #177 // Compare Scanline Y To 177 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x128PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x128Map.asm" // Include GSU 256x128 BG Map (2048 Bytes) +HDMATable: + db 32, %10000000 // Repeat 32 Scanlines, Turn Off Screen, Zero Brightness + db 15, %10000000 // Repeat 15 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.png new file mode 100644 index 00000000..1274a07b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.sfc new file mode 100644 index 00000000..745bd4ae Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel_gsu.asm new file mode 100644 index 00000000..6e24f299 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 8BPP 256x128 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*128)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #63 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..8fec9607 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/make.bat new file mode 100644 index 00000000..95184f07 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x128PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU256x160Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU256x160Map.asm new file mode 100644 index 00000000..910a8243 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU256x160Map.asm @@ -0,0 +1,32 @@ +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0000,$0014,$0028,$003C,$0050,$0064,$0078,$008C,$00A0,$00B4,$00C8,$00DC,$00F0,$0104,$0118,$012C,$0140,$0154,$0168,$017C,$0190,$01A4,$01B8,$01CC,$01E0,$01F4,$0208,$021C,$0230,$0244,$0258,$026C +dw $0001,$0015,$0029,$003D,$0051,$0065,$0079,$008D,$00A1,$00B5,$00C9,$00DD,$00F1,$0105,$0119,$012D,$0141,$0155,$0169,$017D,$0191,$01A5,$01B9,$01CD,$01E1,$01F5,$0209,$021D,$0231,$0245,$0259,$026D +dw $0002,$0016,$002A,$003E,$0052,$0066,$007A,$008E,$00A2,$00B6,$00CA,$00DE,$00F2,$0106,$011A,$012E,$0142,$0156,$016A,$017E,$0192,$01A6,$01BA,$01CE,$01E2,$01F6,$020A,$021E,$0232,$0246,$025A,$026E +dw $0003,$0017,$002B,$003F,$0053,$0067,$007B,$008F,$00A3,$00B7,$00CB,$00DF,$00F3,$0107,$011B,$012F,$0143,$0157,$016B,$017F,$0193,$01A7,$01BB,$01CF,$01E3,$01F7,$020B,$021F,$0233,$0247,$025B,$026F +dw $0004,$0018,$002C,$0040,$0054,$0068,$007C,$0090,$00A4,$00B8,$00CC,$00E0,$00F4,$0108,$011C,$0130,$0144,$0158,$016C,$0180,$0194,$01A8,$01BC,$01D0,$01E4,$01F8,$020C,$0220,$0234,$0248,$025C,$0270 +dw $0005,$0019,$002D,$0041,$0055,$0069,$007D,$0091,$00A5,$00B9,$00CD,$00E1,$00F5,$0109,$011D,$0131,$0145,$0159,$016D,$0181,$0195,$01A9,$01BD,$01D1,$01E5,$01F9,$020D,$0221,$0235,$0249,$025D,$0271 +dw $0006,$001A,$002E,$0042,$0056,$006A,$007E,$0092,$00A6,$00BA,$00CE,$00E2,$00F6,$010A,$011E,$0132,$0146,$015A,$016E,$0182,$0196,$01AA,$01BE,$01D2,$01E6,$01FA,$020E,$0222,$0236,$024A,$025E,$0272 +dw $0007,$001B,$002F,$0043,$0057,$006B,$007F,$0093,$00A7,$00BB,$00CF,$00E3,$00F7,$010B,$011F,$0133,$0147,$015B,$016F,$0183,$0197,$01AB,$01BF,$01D3,$01E7,$01FB,$020F,$0223,$0237,$024B,$025F,$0273 +dw $0008,$001C,$0030,$0044,$0058,$006C,$0080,$0094,$00A8,$00BC,$00D0,$00E4,$00F8,$010C,$0120,$0134,$0148,$015C,$0170,$0184,$0198,$01AC,$01C0,$01D4,$01E8,$01FC,$0210,$0224,$0238,$024C,$0260,$0274 +dw $0009,$001D,$0031,$0045,$0059,$006D,$0081,$0095,$00A9,$00BD,$00D1,$00E5,$00F9,$010D,$0121,$0135,$0149,$015D,$0171,$0185,$0199,$01AD,$01C1,$01D5,$01E9,$01FD,$0211,$0225,$0239,$024D,$0261,$0275 +dw $000A,$001E,$0032,$0046,$005A,$006E,$0082,$0096,$00AA,$00BE,$00D2,$00E6,$00FA,$010E,$0122,$0136,$014A,$015E,$0172,$0186,$019A,$01AE,$01C2,$01D6,$01EA,$01FE,$0212,$0226,$023A,$024E,$0262,$0276 +dw $000B,$001F,$0033,$0047,$005B,$006F,$0083,$0097,$00AB,$00BF,$00D3,$00E7,$00FB,$010F,$0123,$0137,$014B,$015F,$0173,$0187,$019B,$01AF,$01C3,$01D7,$01EB,$01FF,$0213,$0227,$023B,$024F,$0263,$0277 +dw $000C,$0020,$0034,$0048,$005C,$0070,$0084,$0098,$00AC,$00C0,$00D4,$00E8,$00FC,$0110,$0124,$0138,$014C,$0160,$0174,$0188,$019C,$01B0,$01C4,$01D8,$01EC,$0200,$0214,$0228,$023C,$0250,$0264,$0278 +dw $000D,$0021,$0035,$0049,$005D,$0071,$0085,$0099,$00AD,$00C1,$00D5,$00E9,$00FD,$0111,$0125,$0139,$014D,$0161,$0175,$0189,$019D,$01B1,$01C5,$01D9,$01ED,$0201,$0215,$0229,$023D,$0251,$0265,$0279 +dw $000E,$0022,$0036,$004A,$005E,$0072,$0086,$009A,$00AE,$00C2,$00D6,$00EA,$00FE,$0112,$0126,$013A,$014E,$0162,$0176,$018A,$019E,$01B2,$01C6,$01DA,$01EE,$0202,$0216,$022A,$023E,$0252,$0266,$027A +dw $000F,$0023,$0037,$004B,$005F,$0073,$0087,$009B,$00AF,$00C3,$00D7,$00EB,$00FF,$0113,$0127,$013B,$014F,$0163,$0177,$018B,$019F,$01B3,$01C7,$01DB,$01EF,$0203,$0217,$022B,$023F,$0253,$0267,$027B +dw $0010,$0024,$0038,$004C,$0060,$0074,$0088,$009C,$00B0,$00C4,$00D8,$00EC,$0100,$0114,$0128,$013C,$0150,$0164,$0178,$018C,$01A0,$01B4,$01C8,$01DC,$01F0,$0204,$0218,$022C,$0240,$0254,$0268,$027C +dw $0011,$0025,$0039,$004D,$0061,$0075,$0089,$009D,$00B1,$00C5,$00D9,$00ED,$0101,$0115,$0129,$013D,$0151,$0165,$0179,$018D,$01A1,$01B5,$01C9,$01DD,$01F1,$0205,$0219,$022D,$0241,$0255,$0269,$027D +dw $0012,$0026,$003A,$004E,$0062,$0076,$008A,$009E,$00B2,$00C6,$00DA,$00EE,$0102,$0116,$012A,$013E,$0152,$0166,$017A,$018E,$01A2,$01B6,$01CA,$01DE,$01F2,$0206,$021A,$022E,$0242,$0256,$026A,$027E +dw $0013,$0027,$003B,$004F,$0063,$0077,$008B,$009F,$00B3,$00C7,$00DB,$00EF,$0103,$0117,$012B,$013F,$0153,$0167,$017B,$018F,$01A3,$01B7,$01CB,$01DF,$01F3,$0207,$021B,$022F,$0243,$0257,$026B,$027F +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 +dw $0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280,$0280 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.asm new file mode 100644 index 00000000..f73c688a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.asm @@ -0,0 +1,153 @@ +// SNES GSU 8BPP 256x160 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x160PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H160) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3556 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #3 // Y = 3 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #193 // Compare Scanline Y To 193 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x160PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x160Map.asm" // Include GSU 256x160 BG Map (2048 Bytes) +HDMATable: + db 31, %10000000 // Repeat 31 Scanlines, Turn Off Screen, Zero Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.png new file mode 100644 index 00000000..7bda3a86 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.sfc new file mode 100644 index 00000000..2c5749f3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel_gsu.asm new file mode 100644 index 00000000..6233c51d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 8BPP 256x160 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*160)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #79 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..8fec9607 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/make.bat new file mode 100644 index 00000000..484567fd --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x160PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU256x192Map.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU256x192Map.asm new file mode 100644 index 00000000..11b9d055 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU256x192Map.asm @@ -0,0 +1,32 @@ +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0000,$0018,$0030,$0048,$0060,$0078,$0090,$00A8,$00C0,$00D8,$00F0,$0108,$0120,$0138,$0150,$0168,$0180,$0198,$01B0,$01C8,$01E0,$01F8,$0210,$0228,$0240,$0258,$0270,$0288,$02A0,$02B8,$02D0,$02E8 +dw $0001,$0019,$0031,$0049,$0061,$0079,$0091,$00A9,$00C1,$00D9,$00F1,$0109,$0121,$0139,$0151,$0169,$0181,$0199,$01B1,$01C9,$01E1,$01F9,$0211,$0229,$0241,$0259,$0271,$0289,$02A1,$02B9,$02D1,$02E9 +dw $0002,$001A,$0032,$004A,$0062,$007A,$0092,$00AA,$00C2,$00DA,$00F2,$010A,$0122,$013A,$0152,$016A,$0182,$019A,$01B2,$01CA,$01E2,$01FA,$0212,$022A,$0242,$025A,$0272,$028A,$02A2,$02BA,$02D2,$02EA +dw $0003,$001B,$0033,$004B,$0063,$007B,$0093,$00AB,$00C3,$00DB,$00F3,$010B,$0123,$013B,$0153,$016B,$0183,$019B,$01B3,$01CB,$01E3,$01FB,$0213,$022B,$0243,$025B,$0273,$028B,$02A3,$02BB,$02D3,$02EB +dw $0004,$001C,$0034,$004C,$0064,$007C,$0094,$00AC,$00C4,$00DC,$00F4,$010C,$0124,$013C,$0154,$016C,$0184,$019C,$01B4,$01CC,$01E4,$01FC,$0214,$022C,$0244,$025C,$0274,$028C,$02A4,$02BC,$02D4,$02EC +dw $0005,$001D,$0035,$004D,$0065,$007D,$0095,$00AD,$00C5,$00DD,$00F5,$010D,$0125,$013D,$0155,$016D,$0185,$019D,$01B5,$01CD,$01E5,$01FD,$0215,$022D,$0245,$025D,$0275,$028D,$02A5,$02BD,$02D5,$02ED +dw $0006,$001E,$0036,$004E,$0066,$007E,$0096,$00AE,$00C6,$00DE,$00F6,$010E,$0126,$013E,$0156,$016E,$0186,$019E,$01B6,$01CE,$01E6,$01FE,$0216,$022E,$0246,$025E,$0276,$028E,$02A6,$02BE,$02D6,$02EE +dw $0007,$001F,$0037,$004F,$0067,$007F,$0097,$00AF,$00C7,$00DF,$00F7,$010F,$0127,$013F,$0157,$016F,$0187,$019F,$01B7,$01CF,$01E7,$01FF,$0217,$022F,$0247,$025F,$0277,$028F,$02A7,$02BF,$02D7,$02EF +dw $0008,$0020,$0038,$0050,$0068,$0080,$0098,$00B0,$00C8,$00E0,$00F8,$0110,$0128,$0140,$0158,$0170,$0188,$01A0,$01B8,$01D0,$01E8,$0200,$0218,$0230,$0248,$0260,$0278,$0290,$02A8,$02C0,$02D8,$02F0 +dw $0009,$0021,$0039,$0051,$0069,$0081,$0099,$00B1,$00C9,$00E1,$00F9,$0111,$0129,$0141,$0159,$0171,$0189,$01A1,$01B9,$01D1,$01E9,$0201,$0219,$0231,$0249,$0261,$0279,$0291,$02A9,$02C1,$02D9,$02F1 +dw $000A,$0022,$003A,$0052,$006A,$0082,$009A,$00B2,$00CA,$00E2,$00FA,$0112,$012A,$0142,$015A,$0172,$018A,$01A2,$01BA,$01D2,$01EA,$0202,$021A,$0232,$024A,$0262,$027A,$0292,$02AA,$02C2,$02DA,$02F2 +dw $000B,$0023,$003B,$0053,$006B,$0083,$009B,$00B3,$00CB,$00E3,$00FB,$0113,$012B,$0143,$015B,$0173,$018B,$01A3,$01BB,$01D3,$01EB,$0203,$021B,$0233,$024B,$0263,$027B,$0293,$02AB,$02C3,$02DB,$02F3 +dw $000C,$0024,$003C,$0054,$006C,$0084,$009C,$00B4,$00CC,$00E4,$00FC,$0114,$012C,$0144,$015C,$0174,$018C,$01A4,$01BC,$01D4,$01EC,$0204,$021C,$0234,$024C,$0264,$027C,$0294,$02AC,$02C4,$02DC,$02F4 +dw $000D,$0025,$003D,$0055,$006D,$0085,$009D,$00B5,$00CD,$00E5,$00FD,$0115,$012D,$0145,$015D,$0175,$018D,$01A5,$01BD,$01D5,$01ED,$0205,$021D,$0235,$024D,$0265,$027D,$0295,$02AD,$02C5,$02DD,$02F5 +dw $000E,$0026,$003E,$0056,$006E,$0086,$009E,$00B6,$00CE,$00E6,$00FE,$0116,$012E,$0146,$015E,$0176,$018E,$01A6,$01BE,$01D6,$01EE,$0206,$021E,$0236,$024E,$0266,$027E,$0296,$02AE,$02C6,$02DE,$02F6 +dw $000F,$0027,$003F,$0057,$006F,$0087,$009F,$00B7,$00CF,$00E7,$00FF,$0117,$012F,$0147,$015F,$0177,$018F,$01A7,$01BF,$01D7,$01EF,$0207,$021F,$0237,$024F,$0267,$027F,$0297,$02AF,$02C7,$02DF,$02F7 +dw $0010,$0028,$0040,$0058,$0070,$0088,$00A0,$00B8,$00D0,$00E8,$0100,$0118,$0130,$0148,$0160,$0178,$0190,$01A8,$01C0,$01D8,$01F0,$0208,$0220,$0238,$0250,$0268,$0280,$0298,$02B0,$02C8,$02E0,$02F8 +dw $0011,$0029,$0041,$0059,$0071,$0089,$00A1,$00B9,$00D1,$00E9,$0101,$0119,$0131,$0149,$0161,$0179,$0191,$01A9,$01C1,$01D9,$01F1,$0209,$0221,$0239,$0251,$0269,$0281,$0299,$02B1,$02C9,$02E1,$02F9 +dw $0012,$002A,$0042,$005A,$0072,$008A,$00A2,$00BA,$00D2,$00EA,$0102,$011A,$0132,$014A,$0162,$017A,$0192,$01AA,$01C2,$01DA,$01F2,$020A,$0222,$023A,$0252,$026A,$0282,$029A,$02B2,$02CA,$02E2,$02FA +dw $0013,$002B,$0043,$005B,$0073,$008B,$00A3,$00BB,$00D3,$00EB,$0103,$011B,$0133,$014B,$0163,$017B,$0193,$01AB,$01C3,$01DB,$01F3,$020B,$0223,$023B,$0253,$026B,$0283,$029B,$02B3,$02CB,$02E3,$02FB +dw $0014,$002C,$0044,$005C,$0074,$008C,$00A4,$00BC,$00D4,$00EC,$0104,$011C,$0134,$014C,$0164,$017C,$0194,$01AC,$01C4,$01DC,$01F4,$020C,$0224,$023C,$0254,$026C,$0284,$029C,$02B4,$02CC,$02E4,$02FC +dw $0015,$002D,$0045,$005D,$0075,$008D,$00A5,$00BD,$00D5,$00ED,$0105,$011D,$0135,$014D,$0165,$017D,$0195,$01AD,$01C5,$01DD,$01F5,$020D,$0225,$023D,$0255,$026D,$0285,$029D,$02B5,$02CD,$02E5,$02FD +dw $0016,$002E,$0046,$005E,$0076,$008E,$00A6,$00BE,$00D6,$00EE,$0106,$011E,$0136,$014E,$0166,$017E,$0196,$01AE,$01C6,$01DE,$01F6,$020E,$0226,$023E,$0256,$026E,$0286,$029E,$02B6,$02CE,$02E6,$02FE +dw $0017,$002F,$0047,$005F,$0077,$008F,$00A7,$00BF,$00D7,$00EF,$0107,$011F,$0137,$014F,$0167,$017F,$0197,$01AF,$01C7,$01DF,$01F7,$020F,$0227,$023F,$0257,$026F,$0287,$029F,$02B7,$02CF,$02E7,$02FF +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 +dw $0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300,$0300 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.asm new file mode 100644 index 00000000..a4a04445 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.asm @@ -0,0 +1,154 @@ +// SNES GSU 8BPP 256x192 Plot Pixel Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "GSU8BPP256x192PlotPixel.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + // Load Blue Palette Color (GSU Clear Color) + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Blue Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111100 // Load Blue Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Load White Palette Color (Plot Pixel Color) + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + LoadVRAM(BGMap, $F800, $800, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_8BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + + LoopGSU: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne LoopGSU + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + // Setup DMA On Channel 0 + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP0 // $4300: DMA0 Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA0 Destination + lda.b #$70 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + ldx.w #$3000 // Set Size In Bytes To DMA Transfer + +Refresh: + ldy.w #$0000 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + sty.w REG_A1T0L // $4302: DMA0 Source + ldy.w #4 // Y = 4 + LoopGSUSRAM: + stx.w REG_DAS0L // $4305: DMA0 Transfer Size/HDMA + + WaitScanline: + // Start Vertical Counter Latch + lda.w REG_SLHV // A = PPU1 Latch H/V-Counter By Software ($2137) + lda.w REG_OPVCT // A = Vertical Counter Latch (Scanline Y) ($213D) + cmp.b #205 // Compare Scanline Y To 205 + bne WaitScanline + + lda.b #%00000011 // Initiate DMA Transfer (Channel 0 & 1) + sta.w REG_MDMAEN // $420B: DMA Enable + dey // Y-- + bne LoopGSUSRAM + bra Refresh +CPURAMEnd: + +// GSU Code +// BANK 0 +GSUROM: + include "GSU8BPP256x192PlotPixel_gsu.asm" // Include GSU ROM Data +BGMap: + include "GSU256x192Map.asm" // Include GSU 256x192 BG Map (2048 Bytes) +HDMATable: + db 19, %10000000 // Repeat 19 Scanlines, Turn Off Screen, Zero Brightness + db 29, %00001111 // Repeat 29 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 28, %00001111 // Repeat 28 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.png b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.png new file mode 100644 index 00000000..0885352b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.sfc new file mode 100644 index 00000000..18a0f72b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel_gsu.asm new file mode 100644 index 00000000..70da7768 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel_gsu.asm @@ -0,0 +1,28 @@ +// SNES GSU 8BPP 256x192 Plot Pixel Demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + sub r0 // R0 = 0 + cmode // Set Color Mode + + // Fill Screen With Clear Color + sub r0 // R0 = 0 (Fill Value) + iwt r3, #$0000 // R3 = Screen Base (SRAM Destination) + iwt r12, #(256*192)/2 // R12 = Loop Count + move r13, r15 // R13 = Loop Address + // Loop: + stw (r3) // Store Fill Value Word To Screen Base + inc r3 // Screen Base++ + loop // IF (Loop Count != 0) Loop + inc r3 // Screen Base++ (Delay Slot) + + // Plot Pixel Color At X/Y Location + ibt r0, #1 // R0 = Color #1 + color // Set Value In COLOR + ibt r1, #127 // R1 = Plot X Position + ibt r2, #95 // R2 = Plot Y Position + plot // Plot Color + rpix // Flush Pixel Cache + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..8fec9607 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU 8BPP PLOT PIXEL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/make.bat new file mode 100644 index 00000000..e6697d98 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/make.bat @@ -0,0 +1 @@ +bass GSU8BPP256x192PlotPixel.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.asm new file mode 100644 index 00000000..f65a50cb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.asm @@ -0,0 +1,2319 @@ +// SNES GSU Test ADC (Add With Carry) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUADC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ADCRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADC15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test ADC (Add With Carry):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ADCR0: + db "R0/$50 " +ADCR1: + db "R1/$51 " +ADCR2: + db "R2/$52 " +ADCR3: + db "R3/$53 " +ADCR4: + db "R4/$54 " +ADCR5: + db "R5/$55 " +ADCR6: + db "R6/$56 " +ADCR7: + db "R7/$57 " +ADCR8: + db "R8/$58 " +ADCR9: + db "R9/$59 " +ADCR10: + db "R10/$5A" +ADCR11: + db "R11/$5B" +ADCR12: + db "R12/$5C" +ADCR13: + db "R13/$5D" +ADCR14: + db "R14/$5E" +ADCR15: + db "R15/$5F" + +HASH: + db "#" +ADC0: + db "#0/$50 " +ADC1: + db "#1/$51 " +ADC2: + db "#2/$52 " +ADC3: + db "#3/$53 " +ADC4: + db "#4/$54 " +ADC5: + db "#5/$55 " +ADC6: + db "#6/$56 " +ADC7: + db "#7/$57 " +ADC8: + db "#8/$58 " +ADC9: + db "#9/$59 " +ADC10: + db "#10/$5A" +ADC11: + db "#11/$5B" +ADC12: + db "#12/$5C" +ADC13: + db "#13/$5D" +ADC14: + db "#14/$5E" +ADC15: + db "#15/$5F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ADCRegister: + db "ADC register (Opcode: $3D5n)" +ADCConst: + db "ADC #const (Opcode: $3F5n)" + +ADCResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +ADCResultCheckB: + dw $FFFF +SFRResultCheckB: + db $18 +SFRResultCheckC: + db $08 + +SFRResultCheckD: + db $02 + +ADCResultCheckC: + dw $8000 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUADC_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.png new file mode 100644 index 00000000..1e24b1be Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.sfc new file mode 100644 index 00000000..f1d9cd12 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC_gsu.asm new file mode 100644 index 00000000..441a616e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test ADC (Add With Carry) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // ADC register + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8001 // R0 = $8001 + with r1 ; adc r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFF // R0 = $7FFF + with r1 ; adc r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$8001 // R1 = $8001 + adc r1 // R0 += R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$7FFF // R1 = $7FFF + adc r1 // R0 += R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$8001 // R2 = $8001 + adc r2 // R0 += R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$7FFF // R2 = $7FFF + adc r2 // R0 += R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$8001 // R3 = $8001 + adc r3 // R0 += R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$7FFF // R3 = $7FFF + adc r3 // R0 += R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$8001 // R4 = $8001 + adc r4 // R0 += R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$7FFF // R4 = $7FFF + adc r4 // R0 += R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$8001 // R5 = $8001 + adc r5 // R0 += R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$7FFF // R5 = $7FFF + adc r5 // R0 += R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$8001 // R6 = $8001 + adc r6 // R0 += R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$7FFF // R6 = $7FFF + adc r6 // R0 += R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$8001 // R7 = $8001 + adc r7 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$7FFF // R7 = $7FFF + adc r7 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$8001 // R8 = $8001 + adc r8 // R0 += R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$7FFF // R8 = $7FFF + adc r8 // R0 += R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$8001 // R9 = $8001 + adc r9 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$7FFF // R9 = $7FFF + adc r9 // R0 += R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$8001 // R10 = $8001 + adc r10 // R0 += R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$7FFF // R10 = $7FFF + adc r10 // R0 += R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$8001 // R11 = $8001 + adc r11 // R0 += R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$7FFF // R11 = $7FFF + adc r11 // R0 += R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$8001 // R12 = $8001 + adc r12 // R0 += R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$7FFF // R12 = $7FFF + adc r12 // R0 += R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$8001 // R13 = $8001 + adc r13 // R0 += R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$7FFF // R13 = $7FFF + adc r13 // R0 += R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$8001 // R14 = $8001 + adc r14 // R0 += R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$7FFF // R14 = $7FFF + adc r14 // R0 += R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$420E // R0 = $420E + adc r15 // R0 += R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$4205 // R0 = $4205 + adc r15 // R0 += R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // ADC #const + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + adc #0 // R0 += 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8000 // R0 = $8000 + adc #0 // R0 += 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + adc #1 // R0 += 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFE // R0 = $7FFE + adc #1 // R0 += 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + adc #2 // R0 += 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFD // R0 = $7FFD + adc #2 // R0 += 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFD // R0 = $FFFD + adc #3 // R0 += 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFC // R0 = $7FFC + adc #3 // R0 += 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFC // R0 = $FFFC + adc #4 // R0 += 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFB // R0 = $7FFB + adc #4 // R0 += 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFB // R0 = $FFFB + adc #5 // R0 += 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFA // R0 = $7FFA + adc #5 // R0 += 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFA // R0 = $FFFA + adc #6 // R0 += 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF9 // R0 = $7FF9 + adc #6 // R0 += 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF9 // R0 = $FFF9 + adc #7 // R0 += 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF8 // R0 = $7FF8 + adc #7 // R0 += 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF8 // R0 = $FFF8 + adc #8 // R0 += 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF7 // R0 = $7FF7 + adc #8 // R0 += 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF7 // R0 = $FFF7 + adc #9 // R0 += 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF6 // R0 = $7FF6 + adc #9 // R0 += 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF6 // R0 = $FFF6 + adc #10 // R0 += 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF5 // R0 = $7FF5 + adc #10 // R0 += 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF5 // R0 = $FFF5 + adc #11 // R0 += 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF4 // R0 = $7FF4 + adc #11 // R0 += 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF4 // R0 = $FFF4 + adc #12 // R0 += 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF3 // R0 = $7FF3 + adc #12 // R0 += 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF3 // R0 = $FFF3 + adc #13 // R0 += 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF2 // R0 = $7FF2 + adc #13 // R0 += 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF2 // R0 = $FFF2 + adc #14 // R0 += 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF1 // R0 = $7FF1 + adc #14 // R0 += 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF1 // R0 = $FFF1 + adc #15 // R0 += 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF0 // R0 = $7FF0 + adc #15 // R0 += 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..34a8ba7b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST ADC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/make.bat new file mode 100644 index 00000000..5949e3e7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/make.bat @@ -0,0 +1 @@ +bass GSUADC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.asm new file mode 100644 index 00000000..c12c64d7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.asm @@ -0,0 +1,2319 @@ +// SNES GSU Test ADD (Addition) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUADD.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 24) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ADDRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADDR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckB + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADDConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADD15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADDResultCheckC + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test ADD (Addition):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ADDR0: + db "R0/$50 " +ADDR1: + db "R1/$51 " +ADDR2: + db "R2/$52 " +ADDR3: + db "R3/$53 " +ADDR4: + db "R4/$54 " +ADDR5: + db "R5/$55 " +ADDR6: + db "R6/$56 " +ADDR7: + db "R7/$57 " +ADDR8: + db "R8/$58 " +ADDR9: + db "R9/$59 " +ADDR10: + db "R10/$5A" +ADDR11: + db "R11/$5B" +ADDR12: + db "R12/$5C" +ADDR13: + db "R13/$5D" +ADDR14: + db "R14/$5E" +ADDR15: + db "R15/$5F" + +HASH: + db "#" +ADD0: + db "#0/$50 " +ADD1: + db "#1/$51 " +ADD2: + db "#2/$52 " +ADD3: + db "#3/$53 " +ADD4: + db "#4/$54 " +ADD5: + db "#5/$55 " +ADD6: + db "#6/$56 " +ADD7: + db "#7/$57 " +ADD8: + db "#8/$58 " +ADD9: + db "#9/$59 " +ADD10: + db "#10/$5A" +ADD11: + db "#11/$5B" +ADD12: + db "#12/$5C" +ADD13: + db "#13/$5D" +ADD14: + db "#14/$5E" +ADD15: + db "#15/$5F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ADDRegister: + db "ADD register (Opcode: $5n) " +ADDConst: + db "ADD #const (Opcode: $3E5n)" + +ADDResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +ADDResultCheckB: + dw $FFFE +SFRResultCheckB: + db $18 +SFRResultCheckC: + db $08 + +SFRResultCheckD: + db $02 + +ADDResultCheckC: + dw $8000 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUADD_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.png new file mode 100644 index 00000000..827c2342 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.sfc new file mode 100644 index 00000000..6661d057 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD_gsu.asm new file mode 100644 index 00000000..3204a02a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test ADD (Addition) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // ADD register + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8001 // R0 = $8001 + with r1 ; add r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFF // R0 = $7FFF + with r1 ; add r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$8001 // R1 = $8001 + add r1 // R0 += R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$7FFF // R1 = $7FFF + add r1 // R0 += R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$8001 // R2 = $8001 + add r2 // R0 += R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$7FFF // R2 = $7FFF + add r2 // R0 += R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$8001 // R3 = $8001 + add r3 // R0 += R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$7FFF // R3 = $7FFF + add r3 // R0 += R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$8001 // R4 = $8001 + add r4 // R0 += R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$7FFF // R4 = $7FFF + add r4 // R0 += R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$8001 // R5 = $8001 + add r5 // R0 += R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$7FFF // R5 = $7FFF + add r5 // R0 += R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$8001 // R6 = $8001 + add r6 // R0 += R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$7FFF // R6 = $7FFF + add r6 // R0 += R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$8001 // R7 = $8001 + add r7 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$7FFF // R7 = $7FFF + add r7 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$8001 // R8 = $8001 + add r8 // R0 += R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$7FFF // R8 = $7FFF + add r8 // R0 += R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$8001 // R9 = $8001 + add r9 // R0 += R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$7FFF // R9 = $7FFF + add r9 // R0 += R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$8001 // R10 = $8001 + add r10 // R0 += R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$7FFF // R10 = $7FFF + add r10 // R0 += R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$8001 // R11 = $8001 + add r11 // R0 += R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$7FFF // R11 = $7FFF + add r11 // R0 += R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$8001 // R12 = $8001 + add r12 // R0 += R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$7FFF // R12 = $7FFF + add r12 // R0 += R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$8001 // R13 = $8001 + add r13 // R0 += R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$7FFF // R13 = $7FFF + add r13 // R0 += R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$8001 // R14 = $8001 + add r14 // R0 += R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$7FFF // R14 = $7FFF + add r14 // R0 += R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$4233 // R0 = $4233 + add r15 // R0 += R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$422B // R0 = $422B + add r15 // R0 += R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // ADD #const + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + add #0 // R0 += 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8000 // R0 = $8000 + add #0 // R0 += 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + add #1 // R0 += 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + add #1 // R0 += 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + add #2 // R0 += 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFE // R0 = $7FFE + add #2 // R0 += 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFD // R0 = $FFFD + add #3 // R0 += 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFD // R0 = $7FFD + add #3 // R0 += 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFC // R0 = $FFFC + add #4 // R0 += 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFC // R0 = $7FFC + add #4 // R0 += 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFB // R0 = $FFFB + add #5 // R0 += 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFB // R0 = $7FFB + add #5 // R0 += 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFA // R0 = $FFFA + add #6 // R0 += 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFA // R0 = $7FFA + add #6 // R0 += 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF9 // R0 = $FFF9 + add #7 // R0 += 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF9 // R0 = $7FF9 + add #7 // R0 += 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF8 // R0 = $FFF8 + add #8 // R0 += 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF8 // R0 = $7FF8 + add #8 // R0 += 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF7 // R0 = $FFF7 + add #9 // R0 += 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF7 // R0 = $7FF7 + add #9 // R0 += 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF6 // R0 = $FFF6 + add #10 // R0 += 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF6 // R0 = $7FF6 + add #10 // R0 += 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF5 // R0 = $FFF5 + add #11 // R0 += 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF5 // R0 = $7FF5 + add #11 // R0 += 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF4 // R0 = $FFF4 + add #12 // R0 += 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF4 // R0 = $7FF4 + add #12 // R0 += 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF3 // R0 = $FFF3 + add #13 // R0 += 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF3 // R0 = $7FF3 + add #13 // R0 += 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF2 // R0 = $FFF2 + add #14 // R0 += 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF2 // R0 = $7FF2 + add #14 // R0 += 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF1 // R0 = $FFF1 + add #15 // R0 += 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FF1 // R0 = $7FF1 + add #15 // R0 += 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4214d4d9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST ADD " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/make.bat new file mode 100644 index 00000000..ac7df394 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/make.bat @@ -0,0 +1 @@ +bass GSUADD.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.asm new file mode 100644 index 00000000..a54ac157 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.asm @@ -0,0 +1,2322 @@ +// SNES GSU Test AND (Logical AND) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUAND.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ANDRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + stz.w GSU_SFR // GSU SFR (Status/Flag) = 0 + + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ANDR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + stz.w GSU_SFR // GSU SFR (Status/Flag) = 0 + + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0001 + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0002 + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0003 + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0004 + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0005 + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0006 + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0007 + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0008 + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0009 + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000A + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000B + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000C + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000D + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000E + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(AND15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000F + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test AND (Logical AND):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ANDR0: + db "R0/$70 " +ANDR1: + db "R1/$71 " +ANDR2: + db "R2/$72 " +ANDR3: + db "R3/$73 " +ANDR4: + db "R4/$74 " +ANDR5: + db "R5/$75 " +ANDR6: + db "R6/$76 " +ANDR7: + db "R7/$77 " +ANDR8: + db "R8/$78 " +ANDR9: + db "R9/$79 " +ANDR10: + db "R10/$7A" +ANDR11: + db "R11/$7B" +ANDR12: + db "R12/$7C" +ANDR13: + db "R13/$7D" +ANDR14: + db "R14/$7E" +ANDR15: + db "R15/$7F" + +HASH: + db "#" +AND0: + db "#0/$70 " +AND1: + db "#1/$71 " +AND2: + db "#2/$72 " +AND3: + db "#3/$73 " +AND4: + db "#4/$74 " +AND5: + db "#5/$75 " +AND6: + db "#6/$76 " +AND7: + db "#7/$77 " +AND8: + db "#8/$78 " +AND9: + db "#9/$79 " +AND10: + db "#10/$7A" +AND11: + db "#11/$7B" +AND12: + db "#12/$7C" +AND13: + db "#13/$7D" +AND14: + db "#14/$7E" +AND15: + db "#15/$7F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ANDRegister: + db "AND register (Opcode: $7n) " +ANDConst: + db "AND #const (Opcode: $3E7n)" + +ANDResultCheckA: + dw $0000 +SFRResultCheckA: + db $00 +SFRResultCheckB: + db $02 + +ANDResultCheckB: + dw $FFFF +SFRResultCheckC: + db $1E +SFRResultCheckD: + db $08 + +ANDResultCheckC: + dw $BDDC + +// GSU Code +// BANK 0 +GSUROM: + include "GSUAND_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.png new file mode 100644 index 00000000..371f0023 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.sfc new file mode 100644 index 00000000..fc2cdc82 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND_gsu.asm new file mode 100644 index 00000000..62688d98 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND_gsu.asm @@ -0,0 +1,427 @@ +// SNES GSU Test AND (Logical AND) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // AND register + //////////////////////////// + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r1 ; and r0 // R1 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + iwt r8, #$FF00 // R8 = $FF00 + with r1 ; and r0 // R1 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$0000 // R1 = $0000 + and r1 // R0 &= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$FFFF // R1 = $FFFF + and r1 // R0 &= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$0000 // R2 = $0000 + and r2 // R0 &= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$FFFF // R2 = $FFFF + and r2 // R0 &= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$0000 // R3 = $0000 + and r3 // R0 &= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$FFFF // R3 = $FFFF + and r3 // R0 &= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$0000 // R4 = $0000 + and r4 // R0 &= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$FFFF // R4 = $FFFF + and r4 // R0 &= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$0000 // R5 = $0000 + and r5 // R0 &= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$FFFF // R5 = $FFFF + and r5 // R0 &= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + and r6 // R0 &= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$FFFF // R6 = $FFFF + and r6 // R0 &= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$0000 // R7 = $0000 + and r7 // R0 &= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$FFFF // R7 = $FFFF + and r7 // R0 &= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$0000 // R8 = $0000 + and r8 // R0 &= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$FFFF // R8 = $FFFF + and r8 // R0 &= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$0000 // R9 = $0000 + and r9 // R0 &= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$FFFF // R9 = $FFFF + and r9 // R0 &= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$0000 // R10 = $0000 + and r10 // R0 &= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$FFFF // R10 = $FFFF + and r10 // R0 &= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$0000 // R11 = $0000 + and r11 // R0 &= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$FFFF // R11 = $FFFF + and r11 // R0 &= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$0000 // R12 = $0000 + and r12 // R0 &= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$FFFF // R12 = $FFFF + and r12 // R0 &= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$0000 // R13 = $0000 + and r13 // R0 &= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$FFFF // R13 = $FFFF + and r13 // R0 &= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$0000 // R14 = $0000 + and r14 // R0 &= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$FFFF // R14 = $FFFF + and r14 // R0 &= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and r15 // R0 &= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and r15 // R0 &= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // AND #const + //////////////////////////// + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + and #0 // R0 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + iwt r8, #$FF00 // R8 = $FF00 + and #0 // R0 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #1 // R0 &= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #1 // R0 &= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #2 // R0 &= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #2 // R0 &= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #3 // R0 &= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #3 // R0 &= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #4 // R0 &= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #4 // R0 &= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #5 // R0 &= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #5 // R0 &= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #6 // R0 &= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #6 // R0 &= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #7 // R0 &= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #7 // R0 &= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #8 // R0 &= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #8 // R0 &= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #9 // R0 &= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #9 // R0 &= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #10 // R0 &= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #10 // R0 &= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #11 // R0 &= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #11 // R0 &= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #12 // R0 &= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #12 // R0 &= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #13 // R0 &= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #13 // R0 &= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #14 // R0 &= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #14 // R0 &= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + and #15 // R0 &= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + and #15 // R0 &= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b0884bfc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST AND " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/make.bat new file mode 100644 index 00000000..b271bb17 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/make.bat @@ -0,0 +1 @@ +bass GSUAND.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.asm new file mode 100644 index 00000000..458a72c1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.asm @@ -0,0 +1,1239 @@ +// SNES GSU Test ASR (Arithmetic Shift Right) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUASR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ASRRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ASRR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASRResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test ASR (Shift Right):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ASRR0: + db "R0/$96 " +ASRR1: + db "R1/$96 " +ASRR2: + db "R2/$96 " +ASRR3: + db "R3/$96 " +ASRR4: + db "R4/$96 " +ASRR5: + db "R5/$96 " +ASRR6: + db "R6/$96 " +ASRR7: + db "R7/$96 " +ASRR8: + db "R8/$96 " +ASRR9: + db "R9/$96 " +ASRR10: + db "R10/$96" +ASRR11: + db "R11/$96" +ASRR12: + db "R12/$96" +ASRR13: + db "R13/$96" +ASRR14: + db "R14/$96" +ASRR15: + db "R15/$96" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ASRRegister: + db "ASR register (Opcode: $96) " + +ASRResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +ASRResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +ASRResultCheckC: + dw $CFD7 +SFRResultCheckC: + db $0C + +// GSU Code +// BANK 0 +GSUROM: + include "GSUASR_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.png new file mode 100644 index 00000000..d9589db0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.sfc new file mode 100644 index 00000000..9e28aff7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR_gsu.asm new file mode 100644 index 00000000..4c2fe42e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test ASR (Arithmetic Shift Right) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // ASR register + //////////////////////////// + + iwt r0, #$0001 // R0 = $0001 + asr // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + asr // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0001 // R1 = $0001 + with r1 ; asr // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFE // R1 = $FFFE + with r1 ; asr // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0001 // R2 = $0001 + with r2 ; asr // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFE // R2 = $FFFE + with r2 ; asr // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0001 // R3 = $0001 + with r3 ; asr // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFE // R3 = $FFFE + with r3 ; asr // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0001 // R4 = $0001 + with r4 ; asr // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFE // R4 = $FFFE + with r4 ; asr // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0001 // R5 = $0001 + with r5 ; asr // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFE // R5 = $FFFE + with r5 ; asr // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0001 // R6 = $0001 + with r6 ; asr // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFE // R6 = $FFFE + with r6 ; asr // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0001 // R7 = $0001 + with r7 ; asr // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFE // R7 = $FFFE + with r7 ; asr // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0001 // R8 = $0001 + with r8 ; asr // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFE // R8 = $FFFE + with r8 ; asr // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0001 // R9 = $0001 + with r9 ; asr // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFE // R9 = $FFFE + with r9 ; asr // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0001 // R10 = $0001 + with r10 ; asr // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFE // R10 = $FFFE + with r10 ; asr // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0001 // R11 = $0001 + with r11 ; asr // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFE // R11 = $FFFE + with r11 ; asr // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0001 // R12 = $0001 + with r12 ; asr // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFE // R12 = $FFFE + with r12 ; asr // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0001 // R13 = $0001 + with r13 ; asr // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFE // R13 = $FFFE + with r13 ; asr // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0001 // R14 = $0001 + with r14 ; asr // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFE // R14 = $FFFE + with r14 ; asr // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; asr // R0 = R15 >> 1 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c7e3faa8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST ASR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/make.bat new file mode 100644 index 00000000..81f81320 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/make.bat @@ -0,0 +1 @@ +bass GSUASR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.asm new file mode 100644 index 00000000..d7ba2de3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.asm @@ -0,0 +1,2322 @@ +// SNES GSU Test BIC (BIT Clear) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUBIC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(BICRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + stz.w GSU_SFR // GSU SFR (Status/Flag) = 0 + + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BICR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(BICConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + stz.w GSU_SFR // GSU SFR (Status/Flag) = 0 + + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFE + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFD + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFB + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFA + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF9 + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF8 + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF7 + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF6 + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF5 + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF4 + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF3 + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF2 + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF1 + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BICResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(BIC15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF0 + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test BIC (BIT Clear):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +BICR0: + db "R0/$70 " +BICR1: + db "R1/$71 " +BICR2: + db "R2/$72 " +BICR3: + db "R3/$73 " +BICR4: + db "R4/$74 " +BICR5: + db "R5/$75 " +BICR6: + db "R6/$76 " +BICR7: + db "R7/$77 " +BICR8: + db "R8/$78 " +BICR9: + db "R9/$79 " +BICR10: + db "R10/$7A" +BICR11: + db "R11/$7B" +BICR12: + db "R12/$7C" +BICR13: + db "R13/$7D" +BICR14: + db "R14/$7E" +BICR15: + db "R15/$7F" + +HASH: + db "#" +BIC0: + db "#0/$70 " +BIC1: + db "#1/$71 " +BIC2: + db "#2/$72 " +BIC3: + db "#3/$73 " +BIC4: + db "#4/$74 " +BIC5: + db "#5/$75 " +BIC6: + db "#6/$76 " +BIC7: + db "#7/$77 " +BIC8: + db "#8/$78 " +BIC9: + db "#9/$79 " +BIC10: + db "#10/$7A" +BIC11: + db "#11/$7B" +BIC12: + db "#12/$7C" +BIC13: + db "#13/$7D" +BIC14: + db "#14/$7E" +BIC15: + db "#15/$7F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +BICRegister: + db "BIC register (Opcode: $3D7n)" +BICConst: + db "BIC #const (Opcode: $3F7n)" + +BICResultCheckA: + dw $0000 +SFRResultCheckA: + db $00 +SFRResultCheckB: + db $02 + +BICResultCheckB: + dw $FFFF +SFRResultCheckC: + db $1E +SFRResultCheckD: + db $08 + +BICResultCheckC: + dw $4205 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUBIC_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.png new file mode 100644 index 00000000..282692b8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.sfc new file mode 100644 index 00000000..93ad99b6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC_gsu.asm new file mode 100644 index 00000000..0cfaaa3c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC_gsu.asm @@ -0,0 +1,427 @@ +// SNES GSU Test BIC (BIT Clear) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // BIC register + //////////////////////////// + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r1 ; bic r0 // R1 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + iwt r8, #$FF00 // R8 = $FF00 + with r1 ; bic r0 // R1 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$FFFF // R1 = $FFFF + bic r1 // R0 &= !R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$0000 // R1 = $0000 + bic r1 // R0 &= !R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$FFFF // R2 = $FFFF + bic r2 // R0 &= !R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$0000 // R2 = $0000 + bic r2 // R0 &= !R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$FFFF // R3 = $FFFF + bic r3 // R0 &= !R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$0000 // R3 = $0000 + bic r3 // R0 &= !R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$FFFF // R4 = $FFFF + bic r4 // R0 &= !R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$0000 // R4 = $0000 + bic r4 // R0 &= !R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$FFFF // R5 = $FFFF + bic r5 // R0 &= !R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$0000 // R5 = $0000 + bic r5 // R0 &= !R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$FFFF // R6 = $FFFF + bic r6 // R0 &= !R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + bic r6 // R0 &= !R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$FFFF // R7 = $FFFF + bic r7 // R0 &= !R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$0000 // R7 = $0000 + bic r7 // R0 &= !R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$FFFF // R8 = $FFFF + bic r8 // R0 &= !R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$0000 // R8 = $0000 + bic r8 // R0 &= !R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$FFFF // R9 = $FFFF + bic r9 // R0 &= !R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$0000 // R9 = $0000 + bic r9 // R0 &= !R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$FFFF // R10 = $FFFF + bic r10 // R0 &= !R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$0000 // R10 = $0000 + bic r10 // R0 &= !R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$FFFF // R11 = $FFFF + bic r11 // R0 &= !R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$0000 // R11 = $0000 + bic r11 // R0 &= !R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$FFFF // R12 = $FFFF + bic r12 // R0 &= !R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$0000 // R12 = $0000 + bic r12 // R0 &= !R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$FFFF // R13 = $FFFF + bic r13 // R0 &= !R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$0000 // R13 = $0000 + bic r13 // R0 &= !R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$FFFF // R14 = $FFFF + bic r14 // R0 &= !R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$0000 // R14 = $0000 + bic r14 // R0 &= !R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$BDF0 // R0 = $BDF0 + bic r15 // R0 &= !R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic r15 // R0 &= !R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // BIC #const + //////////////////////////// + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + bic #0 // R0 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + iwt r8, #$FF00 // R8 = $FF00 + bic #0 // R0 = (R7 & $FF00) + (R8 / $100) (MERGE) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0001 // R0 = $0001 + bic #1 // R0 &= !1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #1 // R0 &= !1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0002 // R0 = $0002 + bic #2 // R0 &= !2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #2 // R0 &= !2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0003 // R0 = $0003 + bic #3 // R0 &= !3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #3 // R0 &= !3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0004 // R0 = $0004 + bic #4 // R0 &= !4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #4 // R0 &= !4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0005 // R0 = $0005 + bic #5 // R0 &= !5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #5 // R0 &= !5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0006 // R0 = $0006 + bic #6 // R0 &= !6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #6 // R0 &= !6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0007 // R0 = $0007 + bic #7 // R0 &= !7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #7 // R0 &= !7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0008 // R0 = $0008 + bic #8 // R0 &= !8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #8 // R0 &= !8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0009 // R0 = $0009 + bic #9 // R0 &= !9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #9 // R0 &= !9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000A // R0 = $000A + bic #10 // R0 &= !10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #10 // R0 &= !10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000B // R0 = $000B + bic #11 // R0 &= !11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #11 // R0 &= !11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000C // R0 = $000C + bic #12 // R0 &= !12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #12 // R0 &= !12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000D // R0 = $000D + bic #13 // R0 &= !13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #13 // R0 &= !13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000E // R0 = $000E + bic #14 // R0 &= !14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #14 // R0 &= !14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000F // R0 = $000F + bic #15 // R0 &= !15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + bic #15 // R0 &= !15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..0aecd934 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST BIC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/make.bat new file mode 100644 index 00000000..5fa087ec --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/make.bat @@ -0,0 +1 @@ +bass GSUBIC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.asm new file mode 100644 index 00000000..c14ada1a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.asm @@ -0,0 +1,291 @@ +// SNES GSU Test Cache Injection demo by krom (Peter Lemon): +// 1. GSU Cart Has No SRAM Or Extended Header +// 2. GSU Cache Code Uploaded From SNES Side (Writes Minimum Cache Line Data) +// 3. GSU RON & RAN Not Set +// 4. GSU Resumes Using PC After STOP +arch snes.cpu +output "GSUCACHEINJECT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy GSU Code To Cache + rep #$20 // Set 16-Bit Accumulator + stz.w GSU_SFR // GSU GO=0 (SFR=$0000) + lda.w #(GSUROMEnd-GSUROM)-1 // A = Length + ldx.w #GSUROM // X = Source + ldy.w #$3100 // Y = Destination + mvn $00=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ADCRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + ///////////////////////////////////////////////////////////////// + ldx.w #$0000 // Program Cache Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ADCR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop + +Title: + db "GSU Test Cache Injection Demo:" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ADCR0: + db "R0/$50 " + +HASH: + db "#" +ADC0: + db "#0/$50 " + +Fail: + db "FAIL" +Pass: + db "PASS" + +ADCRegister: + db "ADC register (Opcode: $3D5n)" + +ADCResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 +ADCResultCheckB: + dw $FFFF +SFRResultCheckB: + db $18 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUCACHEINJECT_gsu.asm" // Include GSU ROM Data +GSUROMEnd: + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.png new file mode 100644 index 00000000..fa40929b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.sfc new file mode 100644 index 00000000..47f8c373 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT_gsu.asm new file mode 100644 index 00000000..b2a5d17f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT_gsu.asm @@ -0,0 +1,23 @@ +// SNES GSU Test Cache Injection demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // Cache Injection Code + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8001 // R0 = $8001 + with r1 ; adc r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFF // R0 = $7FFF + with r1 ; adc r0 // R1 += R0 + + stop // Stop GSU + nop // Delay Slot + + fill 10 // PAD Cache Line (16 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9cb0e71e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST CACHE INJECT" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $13 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/make.bat new file mode 100644 index 00000000..63f3aad1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/make.bat @@ -0,0 +1 @@ +bass GSUCACHEINJECT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.asm new file mode 100644 index 00000000..1ee24ca8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.asm @@ -0,0 +1,1269 @@ +// SNES GSU Test CMP (Compare) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUCMP.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 23) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(CMPRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckA + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckB + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(CMPR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test CMP (Compare):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +CMPR0: + db "R0/$60 " +CMPR1: + db "R1/$61 " +CMPR2: + db "R2/$62 " +CMPR3: + db "R3/$63 " +CMPR4: + db "R4/$64 " +CMPR5: + db "R5/$65 " +CMPR6: + db "R6/$66 " +CMPR7: + db "R7/$67 " +CMPR8: + db "R8/$68 " +CMPR9: + db "R9/$69 " +CMPR10: + db "R10/$6A" +CMPR11: + db "R11/$6B" +CMPR12: + db "R12/$6C" +CMPR13: + db "R13/$6D" +CMPR14: + db "R14/$6E" +CMPR15: + db "R15/$6F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +CMPRegister: + db "CMP register (Opcode: $3F6n)" + +CMPResultCheckA: + dw $7FFF +SFRResultCheckA: + db $06 +SFRResultCheckB: + db $18 + +CMPResultCheckB: + dw $A0E8 +CMPResultCheckC: + dw $A0ED +SFRResultCheckC: + db $08 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUCMP_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.png new file mode 100644 index 00000000..f96d07db Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.sfc new file mode 100644 index 00000000..53870d27 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP_gsu.asm new file mode 100644 index 00000000..01da68ee --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP_gsu.asm @@ -0,0 +1,229 @@ +// SNES GSU Test CMP (Compare) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // CMP register + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFF // R0 = $7FFF + with r1 ; cmp r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8000 // R0 = $8000 + with r1 ; cmp r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$7FFF // R1 = $7FFF + cmp r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$8000 // R1 = $8000 + cmp r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$7FFF // R2 = $7FFF + cmp r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$8000 // R2 = $8000 + cmp r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$7FFF // R3 = $7FFF + cmp r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$8000 // R3 = $8000 + cmp r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$7FFF // R4 = $7FFF + cmp r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$8000 // R4 = $8000 + cmp r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$7FFF // R5 = $7FFF + cmp r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$8000 // R5 = $8000 + cmp r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$7FFF // R6 = $7FFF + cmp r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$8000 // R6 = $8000 + cmp r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$7FFF // R7 = $7FFF + cmp r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$8000 // R7 = $8000 + cmp r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$7FFF // R8 = $7FFF + cmp r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$8000 // R8 = $8000 + cmp r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$7FFF // R9 = $7FFF + cmp r9 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$8000 // R9 = $8000 + cmp r9 // R0 -= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$7FFF // R10 = $7FFF + cmp r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$8000 // R10 = $8000 + cmp r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$7FFF // R11 = $7FFF + cmp r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$8000 // R11 = $8000 + cmp r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$7FFF // R12 = $7FFF + cmp r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$8000 // R12 = $8000 + cmp r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$7FFF // R13 = $7FFF + cmp r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$8000 // R13 = $8000 + cmp r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$7FFF // R14 = $7FFF + cmp r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$8000 // R14 = $8000 + cmp r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$A0E8 // R0 = $A0E8 + cmp r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$A0ED // R0 = $A0ED + cmp r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..02306f68 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST CMP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/make.bat new file mode 100644 index 00000000..b5ed0bee --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/make.bat @@ -0,0 +1 @@ +bass GSUCMP.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.asm new file mode 100644 index 00000000..93bc12d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.asm @@ -0,0 +1,1201 @@ +// SNES GSU Test DEC (Decrement) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUDEC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(DECRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DECR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test DEC (Decrement):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +DECR0: + db "R0/$E0 " +DECR1: + db "R1/$E1 " +DECR2: + db "R2/$E2 " +DECR3: + db "R3/$E3 " +DECR4: + db "R4/$E4 " +DECR5: + db "R5/$E5 " +DECR6: + db "R6/$E6 " +DECR7: + db "R7/$E7 " +DECR8: + db "R8/$E8 " +DECR9: + db "R9/$E9 " +DECR10: + db "R10/$EA" +DECR11: + db "R11/$EB" +DECR12: + db "R12/$EC" +DECR13: + db "R13/$ED" +DECR14: + db "R14/$EE" + +Fail: + db "FAIL" +Pass: + db "PASS" + +DECRegister: + db "DEC register (Opcode: $En) " + +DECResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +DECResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUDEC_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.png new file mode 100644 index 00000000..0b7e5f43 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.sfc new file mode 100644 index 00000000..6d8d5269 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC_gsu.asm new file mode 100644 index 00000000..e22b5594 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC_gsu.asm @@ -0,0 +1,187 @@ +// SNES GSU Test DEC (Decrement) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // DEC register + //////////////////////////// + + iwt r0, #$0001 // R0 = $0001 + dec r0 // R0-- + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + dec r0 // R0-- + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0001 // R1 = $0001 + dec r1 // R1-- + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0000 // R1 = $0000 + dec r1 // R1-- + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0001 // R2 = $0001 + dec r2 // R2-- + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + dec r2 // R2-- + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0001 // R3 = $0001 + dec r3 // R3-- + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + dec r3 // R3-- + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0001 // R4 = $0001 + dec r4 // R4-- + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + dec r4 // R4-- + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0001 // R5 = $0001 + dec r5 // R5-- + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + dec r5 // R5-- + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0001 // R6 = $0001 + dec r6 // R6-- + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + dec r6 // R6-- + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0001 // R7 = $0001 + dec r7 // R7-- + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + dec r7 // R7-- + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0001 // R8 = $0001 + dec r8 // R8-- + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + dec r8 // R8-- + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0001 // R9 = $0001 + dec r9 // R9-- + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + dec r9 // R9-- + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0001 // R10 = $0001 + dec r10 // R10-- + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + dec r10 // R10-- + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0001 // R11 = $0001 + dec r11 // R11-- + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + dec r11 // R11-- + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0001 // R12 = $0001 + dec r12 // R12-- + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + dec r12 // R12-- + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0001 // R13 = $0001 + dec r13 // R13-- + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + dec r13 // R13-- + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0001 // R14 = $0001 + dec r14 // R14-- + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + dec r14 // R14-- + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..1a467815 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST DEC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/make.bat new file mode 100644 index 00000000..095a03b3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/make.bat @@ -0,0 +1 @@ +bass GSUDEC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.asm new file mode 100644 index 00000000..100e1fdb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.asm @@ -0,0 +1,1239 @@ +// SNES GSU Test DIV2 (Divide by 2) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUDIV2.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(DIV2Register, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(DIV2R15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DIV2ResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test DIV2 (Divide by 2):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +DIV2R0: + db "R0/$96 " +DIV2R1: + db "R1/$96 " +DIV2R2: + db "R2/$96 " +DIV2R3: + db "R3/$96 " +DIV2R4: + db "R4/$96 " +DIV2R5: + db "R5/$96 " +DIV2R6: + db "R6/$96 " +DIV2R7: + db "R7/$96 " +DIV2R8: + db "R8/$96 " +DIV2R9: + db "R9/$96 " +DIV2R10: + db "R10/$96" +DIV2R11: + db "R11/$96" +DIV2R12: + db "R12/$96" +DIV2R13: + db "R13/$96" +DIV2R14: + db "R14/$96" +DIV2R15: + db "R15/$96" + +Fail: + db "FAIL" +Pass: + db "PASS" + +DIV2Register: + db "DIV2 register (Opcode: $3D96)" + +DIV2ResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +DIV2ResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +DIV2ResultCheckC: + dw $CFE7 +SFRResultCheckC: + db $0C + +// GSU Code +// BANK 0 +GSUROM: + include "GSUDIV2_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.png new file mode 100644 index 00000000..cb156a10 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.sfc new file mode 100644 index 00000000..78fc4bd3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2_gsu.asm new file mode 100644 index 00000000..528e6460 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test DIV2 (Divide by 2) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // DIV2 register + //////////////////////////// + + iwt r0, #$FFFF // R0 = $FFFF + div2 // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + div2 // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + with r1 ; div2 // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFE // R1 = $FFFE + with r1 ; div2 // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + with r2 ; div2 // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFE // R2 = $FFFE + with r2 ; div2 // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + with r3 ; div2 // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFE // R3 = $FFFE + with r3 ; div2 // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + with r4 ; div2 // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFE // R4 = $FFFE + with r4 ; div2 // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + with r5 ; div2 // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFE // R5 = $FFFE + with r5 ; div2 // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + with r6 ; div2 // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFE // R6 = $FFFE + with r6 ; div2 // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + with r7 ; div2 // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFE // R7 = $FFFE + with r7 ; div2 // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + with r8 ; div2 // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFE // R8 = $FFFE + with r8 ; div2 // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + with r9 ; div2 // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFE // R9 = $FFFE + with r9 ; div2 // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + with r10 ; div2 // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFE // R10 = $FFFE + with r10 ; div2 // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + with r11 ; div2 // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFE // R11 = $FFFE + with r11 ; div2 // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + with r12 ; div2 // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFE // R12 = $FFFE + with r12 ; div2 // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + with r13 ; div2 // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFE // R13 = $FFFE + with r13 ; div2 // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + with r14 ; div2 // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFE // R14 = $FFFE + with r14 ; div2 // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; div2 // R0 = R15 >> 1 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..163d428f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST DIV2 " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/make.bat new file mode 100644 index 00000000..945310a4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/make.bat @@ -0,0 +1 @@ +bass GSUDIV2.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.asm new file mode 100644 index 00000000..a7188e6d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.asm @@ -0,0 +1,1268 @@ +// SNES GSU Test FMULT (Multiply Fraction Word) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUFMULT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(FMULTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(FMULTR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w FMULTResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test FMULT (Multiply Word)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +FMULTR0: + db "R0/$9F " +FMULTR1: + db "R1/$9F " +FMULTR2: + db "R2/$9F " +FMULTR3: + db "R3/$9F " +FMULTR4: + db "R4/$9F " +FMULTR5: + db "R5/$9F " +FMULTR6: + db "R6/$9F " +FMULTR7: + db "R7/$9F " +FMULTR8: + db "R8/$9F " +FMULTR9: + db "R9/$9F " +FMULTR10: + db "R10/$9F" +FMULTR11: + db "R11/$9F" +FMULTR12: + db "R12/$9F" +FMULTR13: + db "R13/$9F" +FMULTR14: + db "R14/$9F" +FMULTR15: + db "R15/$9F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +FMULTRegister: + db "FMULT register (Opcode: $9F) " + +FMULTResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +FMULTResultCheckB: + dw $FFFF +SFRResultCheckB: + db $0C + +FMULTResultCheckC: + dw $FD07 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUFMULT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.png new file mode 100644 index 00000000..8276b4e4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.sfc new file mode 100644 index 00000000..edc78902 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT_gsu.asm new file mode 100644 index 00000000..05c366c8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT_gsu.asm @@ -0,0 +1,229 @@ +// SNES GSU Test FMULT (Multiply Fraction Word) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // FMULT register + //////////////////////////// + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + fmult // R0 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R1 = $FFFF + iwt r6, #$0800 // R6 = $FFFF + fmult // R0 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r1 ; fmult // R1 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r1 ; fmult // R1 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r2 ; fmult // R2 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r2 ; fmult // R2 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r3 ; fmult // R3 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r3 ; fmult // R3 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r4 ; fmult // R4 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r4 ; fmult // R4 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r5 ; fmult // R5 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r5 ; fmult // R5 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + to r6 ; from r0 ; fmult // R6 = R0 * (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0800 // R6 = $0800 + to r6 ; from r0 ; fmult // R6 = R0 * (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r7 ; fmult // R7 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r7 ; fmult // R7 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r8 ; fmult // R8 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r8 ; fmult // R8 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r9 ; fmult // R9 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r9 ; fmult // R9 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r10 ; fmult // R10 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r10 ; fmult // R10 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r11 ; fmult // R11 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r11 ; fmult // R11 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r12 ; fmult // R12 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r12 ; fmult // R12 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r13 ; fmult // R13 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r13 ; fmult // R13 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r14 ; fmult // R14 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r14 ; fmult // R14 *= (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + to r0 ; from r15 ; fmult // R0 = r15 * (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0800 // R6 = $0800 + to r0 ; from r15 ; fmult // R0 = r15 * (R6 / $10000) + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..87b70761 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST FMULT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/make.bat new file mode 100644 index 00000000..216d13f5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/make.bat @@ -0,0 +1 @@ +bass GSUFMULT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.asm new file mode 100644 index 00000000..9dd5bd51 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.asm @@ -0,0 +1,1237 @@ +// SNES GSU Test HIB (Hi Byte) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUHIB.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 23) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(HIBRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(HIBR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w HIBResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test HIB (Hi Byte):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +HIBR0: + db "R0/$C0 " +HIBR1: + db "R1/$C0 " +HIBR2: + db "R2/$C0 " +HIBR3: + db "R3/$C0 " +HIBR4: + db "R4/$C0 " +HIBR5: + db "R5/$C0 " +HIBR6: + db "R6/$C0 " +HIBR7: + db "R7/$C0 " +HIBR8: + db "R8/$C0 " +HIBR9: + db "R9/$C0 " +HIBR10: + db "R10/$C0" +HIBR11: + db "R11/$C0" +HIBR12: + db "R12/$C0" +HIBR13: + db "R13/$C0" +HIBR14: + db "R14/$C0" +HIBR15: + db "R15/$C0" + +Fail: + db "FAIL" +Pass: + db "PASS" + +HIBRegister: + db "HIB register (Opcode: $C0) " + +HIBResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +HIBResultCheckB: + dw $00FF +SFRResultCheckB: + db $08 + +HIBResultCheckC: + dw $009F + +// GSU Code +// BANK 0 +GSUROM: + include "GSUHIB_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.png new file mode 100644 index 00000000..0d34fbf4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.sfc new file mode 100644 index 00000000..239eddc8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB_gsu.asm new file mode 100644 index 00000000..835c213b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test HIB (Hi Byte) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // HIB register + //////////////////////////// + + iwt r0, #$00FF // R0 = $00FF + hib // R0 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FF00 // R0 = $FF00 + hib // R0 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$00FF // R1 = $00FF + with r1 ; hib // R1 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FF00 // R1 = $FF00 + with r1 ; hib // R1 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$00FF // R2 = $00FF + with r2 ; hib // R2 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FF00 // R2 = $FF00 + with r2 ; hib // R2 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$00FF // R3 = $00FF + with r3 ; hib // R3 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FF00 // R3 = $FF00 + with r3 ; hib // R3 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$00FF // R4 = $00FF + with r4 ; hib // R4 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FF00 // R4 = $FF00 + with r4 ; hib // R4 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$00FF // R5 = $00FF + with r5 ; hib // R5 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FF00 // R5 = $FF00 + with r5 ; hib // R5 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$00FF // R6 = $00FF + with r6 ; hib // R6 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FF00 // R6 = $FF00 + with r6 ; hib // R6 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + with r7 ; hib // R7 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + with r7 ; hib // R7 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$00FF // R8 = $00FF + with r8 ; hib // R8 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FF00 // R8 = $FF00 + with r8 ; hib // R8 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$00FF // R9 = $00FF + with r9 ; hib // R9 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FF00 // R9 = $FF00 + with r9 ; hib // R9 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$00FF // R10 = $00FF + with r10 ; hib // R10 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FF00 // R10 = $FF00 + with r10 ; hib // R10 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$00FF // R11 = $00FF + with r11 ; hib // R11 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FF00 // R11 = $FF00 + with r11 ; hib // R11 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$00FF // R12 = $00FF + with r12 ; hib // R12 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FF00 // R12 = $FF00 + with r12 ; hib // R12 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$00FF // R13 = $00FF + with r13 ; hib // R13 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FF00 // R13 = $FF00 + with r13 ; hib // R13 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$00FF // R14 = $00FF + with r14 ; hib // R14 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FF00 // R14 = $FF00 + with r14 ; hib // R14 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; hib // R0 = R15 >> 8 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..41a4ec76 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST HIB " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/make.bat new file mode 100644 index 00000000..dfe0d7e8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/make.bat @@ -0,0 +1 @@ +bass GSUHIB.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.asm new file mode 100644 index 00000000..138ebe88 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.asm @@ -0,0 +1,1199 @@ +// SNES GSU Test IBT (Immediate Byte Transfer) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUIBT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(IBTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IBTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IBTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test IBT (Immediate Byte):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +IBTR0: + db "R0/$A0 " +IBTR1: + db "R1/$A1 " +IBTR2: + db "R2/$A2 " +IBTR3: + db "R3/$A3 " +IBTR4: + db "R4/$A4 " +IBTR5: + db "R5/$A5 " +IBTR6: + db "R6/$A6 " +IBTR7: + db "R7/$A7 " +IBTR8: + db "R8/$A8 " +IBTR9: + db "R9/$A9 " +IBTR10: + db "R10/$AA" +IBTR11: + db "R11/$AB" +IBTR12: + db "R12/$AC" +IBTR13: + db "R13/$AD" +IBTR14: + db "R14/$AE" + +Fail: + db "FAIL" +Pass: + db "PASS" + +IBTRegister: + db "IBT reg, #$nn (Opcode: $Arnn)" + +IBTResultCheckA: + dw $007F +SFRResultCheckA: + db $00 + +IBTResultCheckB: + dw $FFFF + +// GSU Code +// BANK 0 +GSUROM: + include "GSUIBT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.png new file mode 100644 index 00000000..7fe7c925 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.sfc new file mode 100644 index 00000000..ade1ff9c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT_gsu.asm new file mode 100644 index 00000000..e822c3a1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT_gsu.asm @@ -0,0 +1,217 @@ +// SNES GSU Test IBT (Immediate Byte Transfer) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // IBT register, #nn + //////////////////////////// + + ibt r0, #$7F // R0 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r0, #$FF // R0 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r1, #$7F // R1 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r1, #$FF // R1 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r2, #$7F // R2 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r2, #$FF // R2 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r3, #$7F // R3 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r3, #$FF // R3 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r4, #$7F // R4 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r4, #$FF // R4 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r5, #$7F // R5 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r5, #$FF // R5 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r6, #$7F // R6 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r6, #$FF // R6 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r7, #$7F // R7 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r7, #$FF // R7 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r8, #$7F // R8 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r8, #$FF // R8 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r9, #$7F // R9 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r9, #$FF // R9 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r10, #$7F // R10 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r10, #$FF // R10 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r11, #$7F // R11 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r11, #$FF // R11 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r12, #$7F // R12 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r12, #$FF // R12 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r13, #$7F // R13 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r13, #$FF // R13 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r14, #$7F // R14 = $007F + nop + nop + + stop // Stop GSU + nop // Delay Slot + + ibt r14, #$FF // R14 = $FFFF + nop + nop + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..7865ef9e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST IBT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/make.bat new file mode 100644 index 00000000..06f32d99 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/make.bat @@ -0,0 +1 @@ +bass GSUIBT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.asm new file mode 100644 index 00000000..434e6201 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.asm @@ -0,0 +1,1201 @@ +// SNES GSU Test INC (Increment) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUINC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(INCRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(INCR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test INC (Increment):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +INCR0: + db "R0/$D0 " +INCR1: + db "R1/$D1 " +INCR2: + db "R2/$D2 " +INCR3: + db "R3/$D3 " +INCR4: + db "R4/$D4 " +INCR5: + db "R5/$D5 " +INCR6: + db "R6/$D6 " +INCR7: + db "R7/$D7 " +INCR8: + db "R8/$D8 " +INCR9: + db "R9/$D9 " +INCR10: + db "R10/$DA" +INCR11: + db "R11/$DB" +INCR12: + db "R12/$DC" +INCR13: + db "R13/$DD" +INCR14: + db "R14/$DE" + +Fail: + db "FAIL" +Pass: + db "PASS" + +INCRegister: + db "INC register (Opcode: $Dn) " + +INCResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +INCResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUINC_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.png new file mode 100644 index 00000000..4f2ef8ea Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.sfc new file mode 100644 index 00000000..dc61f960 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC_gsu.asm new file mode 100644 index 00000000..f611fc7a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC_gsu.asm @@ -0,0 +1,187 @@ +// SNES GSU Test INC (Increment) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // INC register + //////////////////////////// + + iwt r0, #$FFFF // R0 = $FFFF + inc r0 // R0++ + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + inc r0 // R0++ + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + inc r1 // R1++ + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFE // R1 = $FFFE + inc r1 // R1++ + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + inc r2 // R2++ + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFE // R2 = $FFFE + inc r2 // R2++ + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + inc r3 // R3++ + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFE // R3 = $FFFE + inc r3 // R3++ + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + inc r4 // R4++ + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFE // R4 = $FFFE + inc r4 // R4++ + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + inc r5 // R5++ + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFE // R5 = $FFFE + inc r5 // R5++ + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + inc r6 // R6++ + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFE // R6 = $FFFE + inc r6 // R6++ + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + inc r7 // R7++ + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFE // R7 = $FFFE + inc r7 // R7++ + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + inc r8 // R8++ + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFE // R8 = $FFFE + inc r8 // R8++ + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + inc r9 // R9++ + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFE // R9 = $FFFE + inc r9 // R9++ + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + inc r10 // R10++ + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFE // R10 = $FFFE + inc r10 // R10++ + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + inc r11 // R11++ + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFE // R11 = $FFFE + inc r11 // R11++ + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + inc r12 // R12++ + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFE // R12 = $FFFE + inc r12 // R12++ + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + inc r13 // R13++ + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFE // R13 = $FFFE + inc r13 // R13++ + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + inc r14 // R14++ + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFE // R14 = $FFFE + inc r14 // R14++ + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a9ba3943 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST INC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/make.bat new file mode 100644 index 00000000..d947cff2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/make.bat @@ -0,0 +1 @@ +bass GSUINC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.asm new file mode 100644 index 00000000..38ab95fb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.asm @@ -0,0 +1,1199 @@ +// SNES GSU Test IWT (Immediate Word Transfer) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUIWT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(IWTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(IWTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w IWTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test IWT (Immediate Word):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +IWTR0: + db "R0/$F0 " +IWTR1: + db "R1/$F1 " +IWTR2: + db "R2/$F2 " +IWTR3: + db "R3/$F3 " +IWTR4: + db "R4/$F4 " +IWTR5: + db "R5/$F5 " +IWTR6: + db "R6/$F6 " +IWTR7: + db "R7/$F7 " +IWTR8: + db "R8/$F8 " +IWTR9: + db "R9/$F9 " +IWTR10: + db "R10/$FA" +IWTR11: + db "R11/$FB" +IWTR12: + db "R12/$FC" +IWTR13: + db "R13/$FD" +IWTR14: + db "R14/$FE" + +Fail: + db "FAIL" +Pass: + db "PASS" + +IWTRegister: + db "IWT reg,#$nnnn (Opcode: $Frnn)" + +IWTResultCheckA: + dw $0000 +SFRResultCheckA: + db $00 + +IWTResultCheckB: + dw $FFFF + +// GSU Code +// BANK 0 +GSUROM: + include "GSUIWT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.png new file mode 100644 index 00000000..49ed7146 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.sfc new file mode 100644 index 00000000..0b89d818 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT_gsu.asm new file mode 100644 index 00000000..e3df531c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT_gsu.asm @@ -0,0 +1,187 @@ +// SNES GSU Test IWT (Immediate Word Transfer) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // IWT register, #nnnn + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0000 // R1 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + nop // Delay Slot + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..bf66ac33 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST IWT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/make.bat new file mode 100644 index 00000000..8eca84d9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/make.bat @@ -0,0 +1 @@ +bass GSUIWT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.asm new file mode 100644 index 00000000..cf0aae93 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.asm @@ -0,0 +1,1268 @@ +// SNES GSU Test LMULT (Multiply Long Word) demo by krom (Peter Lemon): +arch snes.cpu +output "GSULMULT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(LMULTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LMULTR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LMULTResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test LMULT (Multiply Word)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +LMULTR0: + db "R0/$9F " +LMULTR1: + db "R1/$9F " +LMULTR2: + db "R2/$9F " +LMULTR3: + db "R3/$9F " +LMULTR4: + db "R4/$9F " +LMULTR5: + db "R5/$9F " +LMULTR6: + db "R6/$9F " +LMULTR7: + db "R7/$9F " +LMULTR8: + db "R8/$9F " +LMULTR9: + db "R9/$9F " +LMULTR10: + db "R10/$9F" +LMULTR11: + db "R11/$9F" +LMULTR12: + db "R12/$9F" +LMULTR13: + db "R13/$9F" +LMULTR14: + db "R14/$9F" +LMULTR15: + db "R15/$9F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +LMULTRegister: + db "LMULT register (Opcode: $3D9F)" + +LMULTResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +LMULTResultCheckB: + dw $FFFF +SFRResultCheckB: + db $0C + +LMULTResultCheckC: + dw $FD08 + +// GSU Code +// BANK 0 +GSUROM: + include "GSULMULT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.png new file mode 100644 index 00000000..8c4b8f6a Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.sfc new file mode 100644 index 00000000..c8a4d092 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT_gsu.asm new file mode 100644 index 00000000..8528d97d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT_gsu.asm @@ -0,0 +1,229 @@ +// SNES GSU Test LMULT (Multiply Long Word) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // LMULT register + //////////////////////////// + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + lmult // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R1 = $FFFF + iwt r6, #$0800 // R6 = $FFFF + lmult // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r1 ; lmult // R1 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r1 ; lmult // R1 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r2 ; lmult // R2 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r2 ; lmult // R2 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r3 ; lmult // R3 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r3 ; lmult // R3 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r4 ; lmult // R4 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r4 ; lmult // R4 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r5 ; lmult // R5 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r5 ; lmult // R5 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + to r6 ; from r0 ; lmult // R6 = R0 * R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0800 // R6 = $0800 + to r6 ; from r0 ; lmult // R6 = R0 * R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r7 ; lmult // R7 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r7 ; lmult // R7 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r8 ; lmult // R8 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r8 ; lmult // R8 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r9 ; lmult // R9 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r9 ; lmult // R9 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r10 ; lmult // R10 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r10 ; lmult // R10 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r11 ; lmult // R11 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r11 ; lmult // R11 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r12 ; lmult // R12 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r12 ; lmult // R12 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r13 ; lmult // R13 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r13 ; lmult // R13 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + iwt r6, #$0000 // R6 = $0000 + with r14 ; lmult // R14 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + iwt r6, #$0800 // R6 = $0800 + with r14 ; lmult // R14 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + to r0 ; from r15 ; lmult // R0 = r15 * R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0800 // R6 = $0800 + to r0 ; from r15 ; lmult // R0 = r15 * R6 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..652b295f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST LMULT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/make.bat new file mode 100644 index 00000000..b171d873 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/make.bat @@ -0,0 +1 @@ +bass GSULMULT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.asm new file mode 100644 index 00000000..ecd0d70f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.asm @@ -0,0 +1,1237 @@ +// SNES GSU Test LOB (Lo Byte) demo by krom (Peter Lemon): +arch snes.cpu +output "GSULOB.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 23) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(LOBRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LOBR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LOBResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test LOB (Lo Byte):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +LOBR0: + db "R0/$9E " +LOBR1: + db "R1/$9E " +LOBR2: + db "R2/$9E " +LOBR3: + db "R3/$9E " +LOBR4: + db "R4/$9E " +LOBR5: + db "R5/$9E " +LOBR6: + db "R6/$9E " +LOBR7: + db "R7/$9E " +LOBR8: + db "R8/$9E " +LOBR9: + db "R9/$9E " +LOBR10: + db "R10/$9E" +LOBR11: + db "R11/$9E" +LOBR12: + db "R12/$9E" +LOBR13: + db "R13/$9E" +LOBR14: + db "R14/$9E" +LOBR15: + db "R15/$9E" + +Fail: + db "FAIL" +Pass: + db "PASS" + +LOBRegister: + db "LOB register (Opcode: $9E) " + +LOBResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +LOBResultCheckB: + dw $00FF +SFRResultCheckB: + db $08 + +LOBResultCheckC: + dw $00AA + +// GSU Code +// BANK 0 +GSUROM: + include "GSULOB_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.png new file mode 100644 index 00000000..ef0d04b8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.sfc new file mode 100644 index 00000000..606c4b03 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB_gsu.asm new file mode 100644 index 00000000..6cc7d883 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test LOB (Lo Byte) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // LOB register + //////////////////////////// + + iwt r0, #$FF00 // R0 = $FF00 + lob // R0 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + lob // R0 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FF00 // R1 = $FF00 + with r1 ; lob // R1 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + with r1 ; lob // R1 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FF00 // R2 = $FF00 + with r2 ; lob // R2 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + with r2 ; lob // R2 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FF00 // R3 = $FF00 + with r3 ; lob // R3 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + with r3 ; lob // R3 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FF00 // R4 = $FF00 + with r4 ; lob // R4 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + with r4 ; lob // R4 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FF00 // R5 = $FF00 + with r5 ; lob // R5 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + with r5 ; lob // R5 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FF00 // R6 = $FF00 + with r6 ; lob // R6 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + with r6 ; lob // R6 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FF00 // R7 = $FF00 + with r7 ; lob // R7 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + with r7 ; lob // R7 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FF00 // R8 = $FF00 + with r8 ; lob // R8 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + with r8 ; lob // R8 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FF00 // R9 = $FF00 + with r9 ; lob // R9 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + with r9 ; lob // R9 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FF00 // R10 = $FF00 + with r10 ; lob // R10 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + with r10 ; lob // R10 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FF00 // R11 = $FF00 + with r11 ; lob // R11 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + with r11 ; lob // R11 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FF00 // R12 = $FF00 + with r12 ; lob // R12 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + with r12 ; lob // R12 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FF00 // R13 = $FF00 + with r13 ; lob // R13 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + with r13 ; lob // R13 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FF00 // R14 = $FF00 + with r14 ; lob // R14 &= $FF + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + with r14 ; lob // R14 &= $FF + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; lob // R0 = R15 & $FF + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b209e11d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST LOB " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/make.bat new file mode 100644 index 00000000..69197724 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/make.bat @@ -0,0 +1 @@ +bass GSULOB.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.asm new file mode 100644 index 00000000..0747f549 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.asm @@ -0,0 +1,1237 @@ +// SNES GSU Test LSR (Logical Shift Right) demo by krom (Peter Lemon): +arch snes.cpu +output "GSULSR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(LSRRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(LSRR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test LSR (Shift Right):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +LSRR0: + db "R0/$03 " +LSRR1: + db "R1/$03 " +LSRR2: + db "R2/$03 " +LSRR3: + db "R3/$03 " +LSRR4: + db "R4/$03 " +LSRR5: + db "R5/$03 " +LSRR6: + db "R6/$03 " +LSRR7: + db "R7/$03 " +LSRR8: + db "R8/$03 " +LSRR9: + db "R9/$03 " +LSRR10: + db "R10/$03" +LSRR11: + db "R11/$03" +LSRR12: + db "R12/$03" +LSRR13: + db "R13/$03" +LSRR14: + db "R14/$03" +LSRR15: + db "R15/$03" + +Fail: + db "FAIL" +Pass: + db "PASS" + +LSRRegister: + db "LSR register (Opcode: $03) " + +LSRResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +LSRResultCheckB: + dw $7FFF +SFRResultCheckB: + db $00 + +LSRResultCheckC: + dw $4FD7 + +// GSU Code +// BANK 0 +GSUROM: + include "GSULSR_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.png new file mode 100644 index 00000000..335663df Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.sfc new file mode 100644 index 00000000..426b5ffc Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR_gsu.asm new file mode 100644 index 00000000..06f5a071 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test LSR (Logical Shift Right) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // LSR register + //////////////////////////// + + iwt r0, #$0001 // R0 = $0001 + lsr // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + lsr // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0001 // R1 = $0001 + with r1 ; lsr // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFE // R1 = $FFFE + with r1 ; lsr // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0001 // R2 = $0001 + with r2 ; lsr // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFE // R2 = $FFFE + with r2 ; lsr // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0001 // R3 = $0001 + with r3 ; lsr // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFE // R3 = $FFFE + with r3 ; lsr // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0001 // R4 = $0001 + with r4 ; lsr // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFE // R4 = $FFFE + with r4 ; lsr // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0001 // R5 = $0001 + with r5 ; lsr // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFE // R5 = $FFFE + with r5 ; lsr // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0001 // R6 = $0001 + with r6 ; lsr // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFE // R6 = $FFFE + with r6 ; lsr // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0001 // R7 = $0001 + with r7 ; lsr // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFE // R7 = $FFFE + with r7 ; lsr // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0001 // R8 = $0001 + with r8 ; lsr // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFE // R8 = $FFFE + with r8 ; lsr // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0001 // R9 = $0001 + with r9 ; lsr // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFE // R9 = $FFFE + with r9 ; lsr // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0001 // R10 = $0001 + with r10 ; lsr // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFE // R10 = $FFFE + with r10 ; lsr // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0001 // R11 = $0001 + with r11 ; lsr // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFE // R11 = $FFFE + with r11 ; lsr // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0001 // R12 = $0001 + with r12 ; lsr // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFE // R12 = $FFFE + with r12 ; lsr // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0001 // R13 = $0001 + with r13 ; lsr // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFE // R13 = $FFFE + with r13 ; lsr // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0001 // R14 = $0001 + with r14 ; lsr // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFE // R14 = $FFFE + with r14 ; lsr // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; lsr // R0 = R15 >> 1 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e8baa949 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST LSR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/make.bat new file mode 100644 index 00000000..2301cfe8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/make.bat @@ -0,0 +1 @@ +bass GSULSR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.asm new file mode 100644 index 00000000..b2bdf96c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.asm @@ -0,0 +1,1201 @@ +// SNES GSU Test MERGE (Hi R7 + Hi R8) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUMERGE.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(MERGERegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MERGER14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MERGEResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test MERGE (Hi R7 + Hi R8)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +MERGER0: + db "R0/$70 " +MERGER1: + db "R1/$70 " +MERGER2: + db "R2/$70 " +MERGER3: + db "R3/$70 " +MERGER4: + db "R4/$70 " +MERGER5: + db "R5/$70 " +MERGER6: + db "R6/$70 " +MERGER7: + db "R7/$70 " +MERGER8: + db "R8/$70 " +MERGER9: + db "R9/$70 " +MERGER10: + db "R10/$70" +MERGER11: + db "R11/$70" +MERGER12: + db "R12/$70" +MERGER13: + db "R13/$70" +MERGER14: + db "R14/$70" + +Fail: + db "FAIL" +Pass: + db "PASS" + +MERGERegister: + db "MERGE register (Opcode: $70) " + +MERGEResultCheckA: + dw $0000 +SFRResultCheckA: + db $00 + +MERGEResultCheckB: + dw $C030 +SFRResultCheckB: + db $1E + +// GSU Code +// BANK 0 +GSUROM: + include "GSUMERGE_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.png new file mode 100644 index 00000000..c30fc825 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.sfc new file mode 100644 index 00000000..ac6d2fe4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE_gsu.asm new file mode 100644 index 00000000..4a08f294 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE_gsu.asm @@ -0,0 +1,217 @@ +// SNES GSU Test MERGE (Hi R7 + Hi R8) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // MERGE register + //////////////////////////// + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + merge // R0 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + merge // R0 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r1 ; merge // R1 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r1 ; merge // R1 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r2 ; merge // R2 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r2 ; merge // R2 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r3 ; merge // R3 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r3 ; merge // R3 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r4 ; merge // R4 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r4 ; merge // R4 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r5 ; merge // R5 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r5 ; merge // R5 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r6 ; merge // R6 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r6 ; merge // R6 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r7 ; merge // R7 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r7 ; merge // R7 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r8 ; merge // R8 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r8 ; merge // R8 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r9 ; merge // R9 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r9 ; merge // R9 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r10 ; merge // R10 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r10 ; merge // R10 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r11 ; merge // R11 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r11 ; merge // R11 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r12 ; merge // R12 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r12 ; merge // R12 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r13 ; merge // R13 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r13 ; merge // R13 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + iwt r8, #$00FF // R8 = $00FF + with r14 ; merge // R14 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$C0FF // R7 = $C0FF + iwt r8, #$30FF // R8 = $30FF + with r14 ; merge // R14 = (R7 & $FF00) + (R8 / $100) + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..1668cece --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST MERGE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/make.bat new file mode 100644 index 00000000..243fbc19 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/make.bat @@ -0,0 +1 @@ +bass GSUMERGE.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.asm new file mode 100644 index 00000000..38909d17 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.asm @@ -0,0 +1,1205 @@ +// SNES GSU Test MOVE (Move Register) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUMOVE.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(MOVERegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckC + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVER14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVEResultCheckD + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test MOVE (Move Register):" + +PageBreak: + db "------------------------------" + +Key: + db "Rd/Rs | Result | VSCZ | Test |" + +MOVER0: + db "R0/R1 " +MOVER1: + db "R1/R2 " +MOVER2: + db "R2/R3 " +MOVER3: + db "R3/R4 " +MOVER4: + db "R4/R5 " +MOVER5: + db "R5/R6 " +MOVER6: + db "R6/R7 " +MOVER7: + db "R7/R8 " +MOVER8: + db "R8/R9 " +MOVER9: + db "R9/R10 " +MOVER10: + db "R10/R11" +MOVER11: + db "R11/R12" +MOVER12: + db "R12/R13" +MOVER13: + db "R13/R14" +MOVER14: + db "R14/R15" + +Fail: + db "FAIL" +Pass: + db "PASS" + +MOVERegister: + db "MOVE dest,src (Opcode: $2s1d)" + +MOVEResultCheckA: + dw $0000 +SFRResultCheckA: + db $00 + +MOVEResultCheckB: + dw $FFFF + +MOVEResultCheckC: + dw $9EC1 + +MOVEResultCheckD: + dw $9EC5 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUMOVE_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.png new file mode 100644 index 00000000..27938134 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.sfc new file mode 100644 index 00000000..385fc9c7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE_gsu.asm new file mode 100644 index 00000000..66bf3b91 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE_gsu.asm @@ -0,0 +1,185 @@ +// SNES GSU Test MOVE (Move Register) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // MOVE destination, source + //////////////////////////// + + iwt r1, #$0000 // R1 = $0000 + move r0, r1 // R0 = R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + move r0, r1 // R0 = R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + move r1, r2 // R1 = R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R1 = $FFFF + move r1, r2 // R1 = R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + move r2, r3 // R2 = R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + move r2, r3 // R2 = R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + move r3, r4 // R3 = R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + move r3, r4 // R3 = R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + move r4, r5 // R4 = R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + move r4, r5 // R4 = R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + move r5, r6 // R5 = R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + move r5, r6 // R5 = R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + move r6, r7 // R6 = R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + move r6, r7 // R6 = R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + move r7, r8 // R7 = R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + move r7, r8 // R7 = R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + move r8, r9 // R8 = R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + move r8, r9 // R8 = R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + move r9, r10 // R9 = R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + move r9, r10 // R9 = R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + move r10, r11 // R10 = R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + move r10, r11 // R10 = R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + move r11, r12 // R11 = R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + move r11, r12 // R11 = R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + move r12, r13 // R12 = R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + move r12, r13 // R12 = R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + move r13, r14 // R13 = R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + move r13, r14 // R13 = R14 + + stop // Stop GSU + nop // Delay Slot + + move r14, r15 // R14 = R15 + + stop // Stop GSU + nop // Delay Slot + + move r14, r15 // R14 = R15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9e54fd4e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST MOVE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/make.bat new file mode 100644 index 00000000..62793a97 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/make.bat @@ -0,0 +1 @@ +bass GSUMOVE.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.asm new file mode 100644 index 00000000..ea4b656e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.asm @@ -0,0 +1,1207 @@ +// SNES GSU Test MOVES (Move Register + Flags) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUMOVES.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(MOVESRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckC + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MOVESR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MOVESResultCheckD + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test MOVES (Move Register)" + +PageBreak: + db "------------------------------" + +Key: + db "Rd/Rs | Result | VSCZ | Test |" + +MOVESR0: + db "R0/R1 " +MOVESR1: + db "R1/R2 " +MOVESR2: + db "R2/R3 " +MOVESR3: + db "R3/R4 " +MOVESR4: + db "R4/R5 " +MOVESR5: + db "R5/R6 " +MOVESR6: + db "R6/R7 " +MOVESR7: + db "R7/R8 " +MOVESR8: + db "R8/R9 " +MOVESR9: + db "R9/R10 " +MOVESR10: + db "R10/R11" +MOVESR11: + db "R11/R12" +MOVESR12: + db "R12/R13" +MOVESR13: + db "R13/R14" +MOVESR14: + db "R14/R15" + +Fail: + db "FAIL" +Pass: + db "PASS" + +MOVESRegister: + db "MOVES dest,src (Opcode: $2dBs)" + +MOVESResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +MOVESResultCheckB: + dw $FFFF +SFRResultCheckB: + db $18 + +MOVESResultCheckC: + dw $9EC2 + +MOVESResultCheckD: + dw $9EC6 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUMOVES_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.png new file mode 100644 index 00000000..ec3e4e2c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.sfc new file mode 100644 index 00000000..ac3f966f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES_gsu.asm new file mode 100644 index 00000000..f5e517bc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES_gsu.asm @@ -0,0 +1,185 @@ +// SNES GSU Test MOVES (Move Register + Flags) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // MOVES destination, source + //////////////////////////// + + iwt r1, #$0000 // R1 = $0000 + moves r0, r1 // R0 = R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + moves r0, r1 // R0 = R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + moves r1, r2 // R1 = R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R1 = $FFFF + moves r1, r2 // R1 = R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + moves r2, r3 // R2 = R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + moves r2, r3 // R2 = R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + moves r3, r4 // R3 = R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + moves r3, r4 // R3 = R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + moves r4, r5 // R4 = R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + moves r4, r5 // R4 = R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + moves r5, r6 // R5 = R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + moves r5, r6 // R5 = R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + moves r6, r7 // R6 = R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + moves r6, r7 // R6 = R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + moves r7, r8 // R7 = R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + moves r7, r8 // R7 = R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + moves r8, r9 // R8 = R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + moves r8, r9 // R8 = R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + moves r9, r10 // R9 = R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + moves r9, r10 // R9 = R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + moves r10, r11 // R10 = R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + moves r10, r11 // R10 = R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + moves r11, r12 // R11 = R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + moves r11, r12 // R11 = R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + moves r12, r13 // R12 = R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + moves r12, r13 // R12 = R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + moves r13, r14 // R13 = R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + moves r13, r14 // R13 = R14 + + stop // Stop GSU + nop // Delay Slot + + moves r14, r15 // R14 = R15 + + stop // Stop GSU + nop // Delay Slot + + moves r14, r15 // R14 = R15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..29699512 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST MOVES " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/make.bat new file mode 100644 index 00000000..8ee2ca6c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/make.bat @@ -0,0 +1 @@ +bass GSUMOVES.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.asm new file mode 100644 index 00000000..20f509a0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.asm @@ -0,0 +1,2314 @@ +// SNES GSU Test MULT (Signed Multiply Byte) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUMULT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(MULTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULTR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(MULTConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFF + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFE + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFD + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFB + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFFA + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF9 + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF8 + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF7 + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF6 + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF5 + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF4 + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF3 + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF2 + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w MULTResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(MULT15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$FFF1 + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test MULT (Multiply Byte):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +MULTR0: + db "R0/$80 " +MULTR1: + db "R1/$81 " +MULTR2: + db "R2/$82 " +MULTR3: + db "R3/$83 " +MULTR4: + db "R4/$84 " +MULTR5: + db "R5/$85 " +MULTR6: + db "R6/$86 " +MULTR7: + db "R7/$87 " +MULTR8: + db "R8/$88 " +MULTR9: + db "R9/$89 " +MULTR10: + db "R10/$8A" +MULTR11: + db "R11/$8B" +MULTR12: + db "R12/$8C" +MULTR13: + db "R13/$8D" +MULTR14: + db "R14/$8E" +MULTR15: + db "R15/$8F" + +HASH: + db "#" +MULT0: + db "#0/$80 " +MULT1: + db "#1/$81 " +MULT2: + db "#2/$82 " +MULT3: + db "#3/$83 " +MULT4: + db "#4/$84 " +MULT5: + db "#5/$85 " +MULT6: + db "#6/$86 " +MULT7: + db "#7/$87 " +MULT8: + db "#8/$88 " +MULT9: + db "#9/$89 " +MULT10: + db "#10/$8A" +MULT11: + db "#11/$8B" +MULT12: + db "#12/$8C" +MULT13: + db "#13/$8D" +MULT14: + db "#14/$8E" +MULT15: + db "#15/$8F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +MULTRegister: + db "MULT register (Opcode: $8n) " +MULTConst: + db "MULT #const (Opcode: $3E8n)" + +MULTResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +MULTResultCheckB: + dw $FF81 +SFRResultCheckB: + db $08 + +MULTResultCheckC: + dw $EBA9 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUMULT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.png new file mode 100644 index 00000000..3f01412d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.sfc new file mode 100644 index 00000000..c9ee3f1d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT_gsu.asm new file mode 100644 index 00000000..be56424a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test MULT (Signed Multiply Byte) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // MULT register + //////////////////////////// + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$0000 // R0 = $0000 + with r1 ; mult r0 // R1 *= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$007F // R0 = $007F + with r1 ; mult r0 // R1 *= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r1, #$0000 // R1 = $0000 + mult r1 // R0 *= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r1, #$007F // R1 = $007F + mult r1 // R0 *= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r2, #$0000 // R2 = $0000 + mult r2 // R0 *= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r2, #$007F // R2 = $007F + mult r2 // R0 *= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r3, #$0000 // R3 = $0000 + mult r3 // R0 *= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r3, #$007F // R3 = $007F + mult r3 // R0 *= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r4, #$0000 // R4 = $0000 + mult r4 // R0 *= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r4, #$007F // R4 = $007F + mult r4 // R0 *= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r5, #$0000 // R5 = $0000 + mult r5 // R0 *= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r5, #$007F // R5 = $007F + mult r5 // R0 *= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r6, #$0000 // R6 = $0000 + mult r6 // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r6, #$007F // R6 = $007F + mult r6 // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r7, #$0000 // R7 = $0000 + mult r7 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r7, #$007F // R7 = $007F + mult r7 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r8, #$0000 // R8 = $0000 + mult r8 // R0 *= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r8, #$007F // R8 = $007F + mult r8 // R0 *= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r9, #$0000 // R9 = $0000 + mult r9 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r9, #$007F // R9 = $007F + mult r9 // R0 *= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r10, #$0000 // R10 = $0000 + mult r10 // R0 *= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r10, #$007F // R10 = $007F + mult r10 // R0 *= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r11, #$0000 // R11 = $0000 + mult r11 // R0 *= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r11, #$007F // R11 = $007F + mult r11 // R0 *= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r12, #$0000 // R12 = $0000 + mult r12 // R0 *= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r12, #$007F // R12 = $007F + mult r12 // R0 *= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r13, #$0000 // R13 = $0000 + mult r13 // R0 *= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r13, #$007F // R13 = $007F + mult r13 // R0 *= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r14, #$0000 // R14 = $0000 + mult r14 // R0 *= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r14, #$007F // R14 = $007F + mult r14 // R0 *= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult r15 // R0 *= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$007F // R0 = $007F + mult r15 // R0 *= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // MULT #const + //////////////////////////// + + iwt r0, #$00FF // R0 = $00FF + mult #0 // R0 *= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$007F // R0 = $007F + mult #0 // R0 *= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #1 // R0 *= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #1 // R0 *= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #2 // R0 *= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #2 // R0 *= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #3 // R0 *= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #3 // R0 *= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #4 // R0 *= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #4 // R0 *= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #5 // R0 *= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #5 // R0 *= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #6 // R0 *= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #6 // R0 *= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #7 // R0 *= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #7 // R0 *= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #8 // R0 *= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #8 // R0 *= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #9 // R0 *= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #9 // R0 *= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #10 // R0 *= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #10 // R0 *= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #11 // R0 *= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #11 // R0 *= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #12 // R0 *= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #12 // R0 *= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #13 // R0 *= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #13 // R0 *= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #14 // R0 *= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #14 // R0 *= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + mult #15 // R0 *= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + mult #15 // R0 *= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..655dbc60 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST MULT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/make.bat new file mode 100644 index 00000000..c27ad31f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/make.bat @@ -0,0 +1 @@ +bass GSUMULT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.asm new file mode 100644 index 00000000..4369cbdb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.asm @@ -0,0 +1,1239 @@ +// SNES GSU Test NOT (Compliment Bits) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUNOT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(NOTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(NOTR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w NOTResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test NOT (Compliment Bits)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +NOTR0: + db "R0/$4F " +NOTR1: + db "R1/$4F " +NOTR2: + db "R2/$4F " +NOTR3: + db "R3/$4F " +NOTR4: + db "R4/$4F " +NOTR5: + db "R5/$4F " +NOTR6: + db "R6/$4F " +NOTR7: + db "R7/$4F " +NOTR8: + db "R8/$4F " +NOTR9: + db "R9/$4F " +NOTR10: + db "R10/$4F" +NOTR11: + db "R11/$4F" +NOTR12: + db "R12/$4F" +NOTR13: + db "R13/$4F" +NOTR14: + db "R14/$4F" +NOTR15: + db "R15/$4F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +NOTRegister: + db "NOT register (Opcode: $4F) " + +NOTResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +NOTResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +NOTResultCheckC: + dw $604D +SFRResultCheckC: + db $00 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUNOT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.png new file mode 100644 index 00000000..8362b8cd Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.sfc new file mode 100644 index 00000000..3673b39f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT_gsu.asm new file mode 100644 index 00000000..565d85d5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test NOT (Compliment Bits) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // NOT register + //////////////////////////// + + iwt r0, #$FFFF // R0 = $FFFF + not // R0 ~= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + not // R0 ~= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFF // R1 = $FFFF + with r1 ; not // R1 ~= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0000 // R1 = $0000 + with r1 ; not // R1 ~= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFF // R2 = $FFFF + with r2 ; not // R2 ~= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + with r2 ; not // R2 ~= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFF // R3 = $FFFF + with r3 ; not // R3 ~= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + with r3 ; not // R3 ~= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFF // R4 = $FFFF + with r4 ; not // R4 ~= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + with r4 ; not // R4 ~= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFF // R5 = $FFFF + with r5 ; not // R5 ~= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + with r5 ; not // R5 ~= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFF // R6 = $FFFF + with r6 ; not // R6 ~= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + with r6 ; not // R6 ~= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFF // R7 = $FFFF + with r7 ; not // R7 ~= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + with r7 ; not // R7 ~= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFF // R8 = $FFFF + with r8 ; not // R8 ~= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + with r8 ; not // R8 ~= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFF // R9 = $FFFF + with r9 ; not // R9 ~= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + with r9 ; not // R9 ~= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFF // R10 = $FFFF + with r10 ; not // R10 ~= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + with r10 ; not // R10 ~= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFF // R11 = $FFFF + with r11 ; not // R11 ~= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + with r11 ; not // R11 ~= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFF // R12 = $FFFF + with r12 ; not // R12 ~= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + with r12 ; not // R12 ~= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFF // R13 = $FFFF + with r13 ; not // R13 ~= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + with r13 ; not // R13 ~= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFF // R14 = $FFFF + with r14 ; not // R14 ~= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + with r14 ; not // R14 ~= R14 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; not // R0 = ~R15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b5aa0d3a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST NOT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/make.bat new file mode 100644 index 00000000..01a6c637 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/make.bat @@ -0,0 +1 @@ +bass GSUNOT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.asm new file mode 100644 index 00000000..edea53e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.asm @@ -0,0 +1,2320 @@ +// SNES GSU Test OR (Logical OR) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUOR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ORRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckD + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ORR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0001 + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0002 + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0003 + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0004 + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0005 + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0006 + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0007 + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0008 + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0009 + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000A + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000B + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000C + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000D + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000E + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$000F + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(OR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORResultCheckC + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test OR (Logical OR):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ORR0: + db "R0/$C0 " +ORR1: + db "R1/$C1 " +ORR2: + db "R2/$C2 " +ORR3: + db "R3/$C3 " +ORR4: + db "R4/$C4 " +ORR5: + db "R5/$C5 " +ORR6: + db "R6/$C6 " +ORR7: + db "R7/$C7 " +ORR8: + db "R8/$C8 " +ORR9: + db "R9/$C9 " +ORR10: + db "R10/$CA" +ORR11: + db "R11/$CB" +ORR12: + db "R12/$CC" +ORR13: + db "R13/$CD" +ORR14: + db "R14/$CE" +ORR15: + db "R15/$CF" + +HASH: + db "#" +OR0: + db "#0/$C0 " +OR1: + db "#1/$C1 " +OR2: + db "#2/$C2 " +OR3: + db "#3/$C3 " +OR4: + db "#4/$C4 " +OR5: + db "#5/$C5 " +OR6: + db "#6/$C6 " +OR7: + db "#7/$C7 " +OR8: + db "#8/$C8 " +OR9: + db "#9/$C9 " +OR10: + db "#10/$CA" +OR11: + db "#11/$CB" +OR12: + db "#12/$CC" +OR13: + db "#13/$CD" +OR14: + db "#14/$CE" +OR15: + db "#15/$CF" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ORRegister: + db "OR register (Opcode: $Cn) " +ORConst: + db "OR #const (Opcode: $3ECn)" + +ORResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +ORResultCheckB: + dw $00FF +SFRResultCheckB: + db $08 + +ORResultCheckC: + dw $FFFF + +ORResultCheckD: + dw $BDCF + +SFRResultCheckC: + db $00 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUOR_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.png new file mode 100644 index 00000000..a4d62154 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.sfc new file mode 100644 index 00000000..3e6275bc Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR_gsu.asm new file mode 100644 index 00000000..1ce36805 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test OR (Logical OR) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // OR register + //////////////////////////// + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$00FF // R0 = $00FF + with r1 ; or r0 // R1 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FF00 // R1 = $FF00 + iwt r0, #$FF00 // R0 = $FF00 + with r1 ; or r0 // R1 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r1, #$0000 // R1 = $0000 + or r1 // R0 |= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r1, #$FF00 // R1 = $FF00 + or r1 // R0 |= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r2, #$0000 // R2 = $0000 + or r2 // R0 |= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r2, #$FF00 // R2 = $FF00 + or r2 // R0 |= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r3, #$0000 // R3 = $0000 + or r3 // R0 |= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r3, #$FF00 // R3 = $FF00 + or r3 // R0 |= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r4, #$0000 // R4 = $0000 + or r4 // R0 |= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r4, #$FF00 // R4 = $FF00 + or r4 // R0 |= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r5, #$0000 // R5 = $0000 + or r5 // R0 |= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r5, #$FF00 // R5 = $FF00 + or r5 // R0 |= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r6, #$0000 // R6 = $0000 + or r6 // R0 |= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r6, #$FF00 // R6 = $FF00 + or r6 // R0 |= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r7, #$0000 // R7 = $0000 + or r7 // R0 |= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r7, #$FF00 // R7 = $FF00 + or r7 // R0 |= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r8, #$0000 // R8 = $0000 + or r8 // R0 |= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r8, #$FF00 // R8 = $FF00 + or r8 // R0 |= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r9, #$0000 // R9 = $0000 + or r9 // R0 |= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r9, #$FF00 // R9 = $FF00 + or r9 // R0 |= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r10, #$0000 // R10 = $0000 + or r10 // R0 |= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r10, #$FF00 // R10 = $FF00 + or r10 // R0 |= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r11, #$0000 // R11 = $0000 + or r11 // R0 |= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r11, #$FF00 // R11 = $FF00 + or r11 // R0 |= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r12, #$0000 // R12 = $0000 + or r12 // R0 |= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r12, #$FF00 // R12 = $FF00 + or r12 // R0 |= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r13, #$0000 // R13 = $0000 + or r13 // R0 |= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r13, #$FF00 // R13 = $FF00 + or r13 // R0 |= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + iwt r14, #$0000 // R14 = $0000 + or r14 // R0 |= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r14, #$FF00 // R14 = $FF00 + or r14 // R0 |= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or r15 // R0 |= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + or r15 // R0 |= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // OR #const + //////////////////////////// + + iwt r0, #$00FF // R0 = $00FF + or #0 // R0 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FF00 // R0 = $FF00 + or #0 // R0 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #1 // R0 |= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + or #1 // R0 |= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #2 // R0 |= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFD // R0 = $FFFD + or #2 // R0 |= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #3 // R0 |= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFC // R0 = $FFFC + or #3 // R0 |= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #4 // R0 |= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFB // R0 = $FFFB + or #4 // R0 |= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #5 // R0 |= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFA // R0 = $FFFA + or #5 // R0 |= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #6 // R0 |= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF9 // R0 = $FFF9 + or #6 // R0 |= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #7 // R0 |= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF8 // R0 = $FFF8 + or #7 // R0 |= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #8 // R0 |= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF7 // R0 = $FFF7 + or #8 // R0 |= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #9 // R0 |= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF6 // R0 = $FFF6 + or #9 // R0 |= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #10 // R0 |= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF5 // R0 = $FFF5 + or #10 // R0 |= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #11 // R0 |= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF4 // R0 = $FFF4 + or #11 // R0 |= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #12 // R0 |= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF3 // R0 = $FFF3 + or #12 // R0 |= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #13 // R0 |= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF2 // R0 = $FFF2 + or #13 // R0 |= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #14 // R0 |= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF1 // R0 = $FFF1 + or #14 // R0 |= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + or #15 // R0 |= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF0 // R0 = $FFF0 + or #15 // R0 |= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..98dfb7fa --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST OR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/make.bat new file mode 100644 index 00000000..eb17c686 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/make.bat @@ -0,0 +1 @@ +bass GSUOR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.asm new file mode 100644 index 00000000..1acf1449 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.asm @@ -0,0 +1,1239 @@ +// SNES GSU Test ROL (Rotate Left) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUROL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ROLRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(ROLR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test ROL (Rotate Left):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +ROLR0: + db "R0/$04 " +ROLR1: + db "R1/$04 " +ROLR2: + db "R2/$04 " +ROLR3: + db "R3/$04 " +ROLR4: + db "R4/$04 " +ROLR5: + db "R5/$04 " +ROLR6: + db "R6/$04 " +ROLR7: + db "R7/$04 " +ROLR8: + db "R8/$04 " +ROLR9: + db "R9/$04 " +ROLR10: + db "R10/$04" +ROLR11: + db "R11/$04" +ROLR12: + db "R12/$04" +ROLR13: + db "R13/$04" +ROLR14: + db "R14/$04" +ROLR15: + db "R15/$04" + +Fail: + db "FAIL" +Pass: + db "PASS" + +ROLRegister: + db "ROL register (Opcode: $04) " + +ROLResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +ROLResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +ROLResultCheckC: + dw $3F5E +SFRResultCheckC: + db $04 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUROL_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.png new file mode 100644 index 00000000..6b81dcab Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.sfc new file mode 100644 index 00000000..699d8bc7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL_gsu.asm new file mode 100644 index 00000000..1573c8ba --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test ROL (Rotate Left) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // ROL register + //////////////////////////// + + iwt r0, #$8000 // R0 = $8000 + rol // R0 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + rol // R0 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$8000 // R1 = $8000 + with r1 ; rol // R1 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + with r1 ; rol // R1 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$8000 // R2 = $8000 + with r2 ; rol // R2 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$7FFF // R2 = $7FFF + with r2 ; rol // R2 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$8000 // R3 = $8000 + with r3 ; rol // R3 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$7FFF // R3 = $7FFF + with r3 ; rol // R3 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$8000 // R4 = $8000 + with r4 ; rol // R4 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$7FFF // R4 = $7FFF + with r4 ; rol // R4 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$8000 // R5 = $8000 + with r5 ; rol // R5 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$7FFF // R5 = $7FFF + with r5 ; rol // R5 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$8000 // R6 = $8000 + with r6 ; rol // R6 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$7FFF // R6 = $7FFF + with r6 ; rol // R6 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$8000 // R7 = $8000 + with r7 ; rol // R7 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$7FFF // R7 = $7FFF + with r7 ; rol // R7 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$8000 // R8 = $8000 + with r8 ; rol // R8 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$7FFF // R8 = $7FFF + with r8 ; rol // R8 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$8000 // R9 = $8000 + with r9 ; rol // R9 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$7FFF // R9 = $7FFF + with r9 ; rol // R9 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$8000 // R10 = $8000 + with r10 ; rol // R10 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$7FFF // R10 = $7FFF + with r10 ; rol // R10 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$8000 // R11 = $8000 + with r11 ; rol // R11 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$7FFF // R11 = $7FFF + with r11 ; rol // R11 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$8000 // R12 = $8000 + with r12 ; rol // R12 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$7FFF // R12 = $7FFF + with r12 ; rol // R12 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$8000 // R13 = $8000 + with r13 ; rol // R13 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$7FFF // R13 = $7FFF + with r13 ; rol // R13 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$8000 // R14 = $8000 + with r14 ; rol // R14 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$7FFF // R14 = $7FFF + with r14 ; rol // R14 <<= 1 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; rol // R0 = R15 << 1 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..276a4fc2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST ROL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/make.bat new file mode 100644 index 00000000..eb528109 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/make.bat @@ -0,0 +1 @@ +bass GSUROL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.asm new file mode 100644 index 00000000..6da55153 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.asm @@ -0,0 +1,1239 @@ +// SNES GSU Test ROR (Rotate Right) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUROR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(RORRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(RORR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test ROR (Rotate Right):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +RORR0: + db "R0/$97 " +RORR1: + db "R1/$97 " +RORR2: + db "R2/$97 " +RORR3: + db "R3/$97 " +RORR4: + db "R4/$97 " +RORR5: + db "R5/$97 " +RORR6: + db "R6/$97 " +RORR7: + db "R7/$97 " +RORR8: + db "R8/$97 " +RORR9: + db "R9/$97 " +RORR10: + db "R10/$97" +RORR11: + db "R11/$97" +RORR12: + db "R12/$97" +RORR13: + db "R13/$97" +RORR14: + db "R14/$97" +RORR15: + db "R15/$97" + +Fail: + db "FAIL" +Pass: + db "PASS" + +RORRegister: + db "ROR register (Opcode: $97) " + +RORResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +RORResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +RORResultCheckC: + dw $4FD8 +SFRResultCheckC: + db $00 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUROR_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.png new file mode 100644 index 00000000..e26a2bc7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.sfc new file mode 100644 index 00000000..b879b9a3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR_gsu.asm new file mode 100644 index 00000000..3487dbc2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test ROR (Rotate Right) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // ROR register + //////////////////////////// + + iwt r0, #$0001 // R0 = $0001 + ror // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + ror // R0 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0001 // R1 = $0001 + with r1 ; ror // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FFFE // R1 = $FFFE + with r1 ; ror // R1 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0001 // R2 = $0001 + with r2 ; ror // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$FFFE // R2 = $FFFE + with r2 ; ror // R2 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0001 // R3 = $0001 + with r3 ; ror // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$FFFE // R3 = $FFFE + with r3 ; ror // R3 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0001 // R4 = $0001 + with r4 ; ror // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$FFFE // R4 = $FFFE + with r4 ; ror // R4 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0001 // R5 = $0001 + with r5 ; ror // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$FFFE // R5 = $FFFE + with r5 ; ror // R5 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0001 // R6 = $0001 + with r6 ; ror // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$FFFE // R6 = $FFFE + with r6 ; ror // R6 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0001 // R7 = $0001 + with r7 ; ror // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$FFFE // R7 = $FFFE + with r7 ; ror // R7 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0001 // R8 = $0001 + with r8 ; ror // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$FFFE // R8 = $FFFE + with r8 ; ror // R8 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0001 // R9 = $0001 + with r9 ; ror // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$FFFE // R9 = $FFFE + with r9 ; ror // R9 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0001 // R10 = $0001 + with r10 ; ror // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$FFFE // R10 = $FFFE + with r10 ; ror // R10 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0001 // R11 = $0001 + with r11 ; ror // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$FFFE // R11 = $FFFE + with r11 ; ror // R11 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0001 // R12 = $0001 + with r12 ; ror // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$FFFE // R12 = $FFFE + with r12 ; ror // R12 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0001 // R13 = $0001 + with r13 ; ror // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$FFFE // R13 = $FFFE + with r13 ; ror // R13 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0001 // R14 = $0001 + with r14 ; ror // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$FFFE // R14 = $FFFE + with r14 ; ror // R14 >>= 1 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; ror // R0 = R15 >> 1 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..ef5fd4c8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST ROR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/make.bat new file mode 100644 index 00000000..5185cc50 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/make.bat @@ -0,0 +1 @@ +bass GSUROR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.asm new file mode 100644 index 00000000..c6fd0c55 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.asm @@ -0,0 +1,1267 @@ +// SNES GSU Test SBC (Subtract With Borrow) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUSBC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SBCRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SBCR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckB + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test SBC (Sub With Borrow)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +SBCR0: + db "R0/$60 " +SBCR1: + db "R1/$61 " +SBCR2: + db "R2/$62 " +SBCR3: + db "R3/$63 " +SBCR4: + db "R4/$64 " +SBCR5: + db "R5/$65 " +SBCR6: + db "R6/$66 " +SBCR7: + db "R7/$67 " +SBCR8: + db "R8/$68 " +SBCR9: + db "R9/$69 " +SBCR10: + db "R10/$6A" +SBCR11: + db "R11/$6B" +SBCR12: + db "R12/$6C" +SBCR13: + db "R13/$6D" +SBCR14: + db "R14/$6E" +SBCR15: + db "R15/$6F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +SBCRegister: + db "SBC register (Opcode: $3D6n)" + +SBCResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +SBCResultCheckB: + dw $FFFF +SFRResultCheckB: + db $18 +SFRResultCheckC: + db $08 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUSBC_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.png new file mode 100644 index 00000000..b6299771 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.sfc new file mode 100644 index 00000000..be56a67d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC_gsu.asm new file mode 100644 index 00000000..67121d0b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC_gsu.asm @@ -0,0 +1,229 @@ +// SNES GSU Test SBC (Subtract With Borrow) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // SBC register + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFE // R0 = $7FFE + with r1 ; sbc r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8000 // R0 = $8000 + with r1 ; sbc r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$7FFE // R1 = $7FFE + sbc r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$8000 // R1 = $8000 + sbc r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$7FFE // R2 = $7FFE + sbc r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$8000 // R2 = $8000 + sbc r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$7FFE // R3 = $7FFE + sbc r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$8000 // R3 = $8000 + sbc r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$7FFE // R4 = $7FFE + sbc r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$8000 // R4 = $8000 + sbc r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$7FFE // R5 = $7FFE + sbc r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$8000 // R5 = $8000 + sbc r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$7FFE // R6 = $7FFE + sbc r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$8000 // R6 = $8000 + sbc r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$7FFE // R7 = $7FFE + sbc r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$8000 // R7 = $8000 + sbc r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$7FFE // R8 = $7FFE + sbc r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$8000 // R8 = $8000 + sbc r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$7FFE // R9 = $7FFE + sbc r9 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$8000 // R9 = $8000 + sbc r9 // R0 -= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$7FFE // R10 = $7FFE + sbc r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$8000 // R10 = $8000 + sbc r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$7FFE // R11 = $7FFE + sbc r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$8000 // R11 = $8000 + sbc r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$7FFE // R12 = $7FFE + sbc r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$8000 // R12 = $8000 + sbc r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$7FFE // R13 = $7FFE + sbc r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$8000 // R13 = $8000 + sbc r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$7FFE // R14 = $7FFE + sbc r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$8000 // R14 = $8000 + sbc r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$A0EE // R0 = $A0EE + sbc r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$A0F3 // R0 = $A0F3 + sbc r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e2e416d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST SBC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/make.bat new file mode 100644 index 00000000..52d4e668 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/make.bat @@ -0,0 +1 @@ +bass GSUSBC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.asm new file mode 100644 index 00000000..a6795eae --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.asm @@ -0,0 +1,1237 @@ +// SNES GSU Test SEX (Sign Extend) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUSEX.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SEXRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SEXR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SEXResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test SEX (Sign Extend):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +SEXR0: + db "R0/$95 " +SEXR1: + db "R1/$95 " +SEXR2: + db "R2/$95 " +SEXR3: + db "R3/$95 " +SEXR4: + db "R4/$95 " +SEXR5: + db "R5/$95 " +SEXR6: + db "R6/$95 " +SEXR7: + db "R7/$95 " +SEXR8: + db "R8/$95 " +SEXR9: + db "R9/$95 " +SEXR10: + db "R10/$95" +SEXR11: + db "R11/$95" +SEXR12: + db "R12/$95" +SEXR13: + db "R13/$95" +SEXR14: + db "R14/$95" +SEXR15: + db "R15/$95" + +Fail: + db "FAIL" +Pass: + db "PASS" + +SEXRegister: + db "SEX register (Opcode: $95) " + +SEXResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +SEXResultCheckB: + dw $FFFF +SFRResultCheckB: + db $08 + +SEXResultCheckC: + dw $FFAE + +// GSU Code +// BANK 0 +GSUROM: + include "GSUSEX_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.png new file mode 100644 index 00000000..bdeace51 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.sfc new file mode 100644 index 00000000..564c815f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX_gsu.asm new file mode 100644 index 00000000..6e2a0e9a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test SEX (Sign Extend) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // SEX register + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + sex // R0 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + sex // R0 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0000 // R1 = $0000 + with r1 ; sex // R1 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$00FF // R1 = $00FF + with r1 ; sex // R1 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + with r2 ; sex // R2 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$00FF // R2 = $00FF + with r2 ; sex // R2 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + with r3 ; sex // R3 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$00FF // R3 = $00FF + with r3 ; sex // R3 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + with r4 ; sex // R4 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$00FF // R4 = $00FF + with r4 ; sex // R4 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + with r5 ; sex // R5 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$00FF // R5 = $00FF + with r5 ; sex // R5 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + with r6 ; sex // R6 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$00FF // R6 = $00FF + with r6 ; sex // R6 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + with r7 ; sex // R7 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$00FF // R7 = $00FF + with r7 ; sex // R7 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + with r8 ; sex // R8 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$00FF // R8 = $00FF + with r8 ; sex // R8 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + with r9 ; sex // R9 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$00FF // R9 = $00FF + with r9 ; sex // R9 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + with r10 ; sex // R10 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$00FF // R10 = $00FF + with r10 ; sex // R10 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + with r11 ; sex // R11 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$00FF // R11 = $00FF + with r11 ; sex // R11 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + with r12 ; sex // R12 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$00FF // R12 = $00FF + with r12 ; sex // R12 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + with r13 ; sex // R13 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$00FF // R13 = $00FF + with r13 ; sex // R13 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + with r14 ; sex // R14 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$00FF // R14 = $00FF + with r14 ; sex // R14 = Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; sex // R0 = R15 Signed (16-Bit) + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..760133f9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST SEX " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/make.bat new file mode 100644 index 00000000..982a489a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/make.bat @@ -0,0 +1 @@ +bass GSUSEX.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.asm new file mode 100644 index 00000000..d6964c5a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.asm @@ -0,0 +1,2319 @@ +// SNES GSU Test SUB (Subtraction) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUSUB.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SUBRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUBR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckB + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SUBConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SUB15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SUBResultCheckC + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckD + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test SUB (Subtraction):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +SUBR0: + db "R0/$60 " +SUBR1: + db "R1/$61 " +SUBR2: + db "R2/$62 " +SUBR3: + db "R3/$63 " +SUBR4: + db "R4/$64 " +SUBR5: + db "R5/$65 " +SUBR6: + db "R6/$66 " +SUBR7: + db "R7/$67 " +SUBR8: + db "R8/$68 " +SUBR9: + db "R9/$69 " +SUBR10: + db "R10/$6A" +SUBR11: + db "R11/$6B" +SUBR12: + db "R12/$6C" +SUBR13: + db "R13/$6D" +SUBR14: + db "R14/$6E" +SUBR15: + db "R15/$6F" + +HASH: + db "#" +SUB0: + db "#0/$60 " +SUB1: + db "#1/$61 " +SUB2: + db "#2/$62 " +SUB3: + db "#3/$63 " +SUB4: + db "#4/$64 " +SUB5: + db "#5/$65 " +SUB6: + db "#6/$66 " +SUB7: + db "#7/$67 " +SUB8: + db "#8/$68 " +SUB9: + db "#9/$69 " +SUB10: + db "#10/$6A" +SUB11: + db "#11/$6B" +SUB12: + db "#12/$6C" +SUB13: + db "#13/$6D" +SUB14: + db "#14/$6E" +SUB15: + db "#15/$6F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +SUBRegister: + db "SUB register (Opcode: $6n) " +SUBConst: + db "SUB #const (Opcode: $3E6n)" + +SUBResultCheckA: + dw $0000 +SFRResultCheckA: + db $06 + +SUBResultCheckB: + dw $FFFF +SFRResultCheckB: + db $18 +SFRResultCheckC: + db $08 + +SFRResultCheckD: + db $0C + +SUBResultCheckC: + dw $8000 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUSUB_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.png new file mode 100644 index 00000000..0fe8e63e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.sfc new file mode 100644 index 00000000..6ae37273 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB_gsu.asm new file mode 100644 index 00000000..b74ac59a --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test SUB (Subtraction) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // SUB register + //////////////////////////// + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$7FFF // R0 = $7FFF + with r1 ; sub r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$7FFF // R1 = $7FFF + iwt r0, #$8000 // R0 = $8000 + with r1 ; sub r0 // R1 -= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$7FFF // R1 = $7FFF + sub r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r1, #$8000 // R1 = $8000 + sub r1 // R0 -= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$7FFF // R2 = $7FFF + sub r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r2, #$8000 // R2 = $8000 + sub r2 // R0 -= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$7FFF // R3 = $7FFF + sub r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r3, #$8000 // R3 = $8000 + sub r3 // R0 -= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$7FFF // R4 = $7FFF + sub r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r4, #$8000 // R4 = $8000 + sub r4 // R0 -= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$7FFF // R5 = $7FFF + sub r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r5, #$8000 // R5 = $8000 + sub r5 // R0 -= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$7FFF // R6 = $7FFF + sub r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r6, #$8000 // R6 = $8000 + sub r6 // R0 -= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$7FFF // R7 = $7FFF + sub r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r7, #$8000 // R7 = $8000 + sub r7 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$7FFF // R8 = $7FFF + sub r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r8, #$8000 // R8 = $8000 + sub r8 // R0 -= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$7FFF // R9 = $7FFF + sub r9 // R0 -= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r9, #$8000 // R9 = $8000 + sub r9 // R0 -= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$7FFF // R10 = $7FFF + sub r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r10, #$8000 // R10 = $8000 + sub r10 // R0 -= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$7FFF // R11 = $7FFF + sub r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r11, #$8000 // R11 = $8000 + sub r11 // R0 -= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$7FFF // R12 = $7FFF + sub r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r12, #$8000 // R12 = $8000 + sub r12 // R0 -= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$7FFF // R13 = $7FFF + sub r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r13, #$8000 // R13 = $8000 + sub r13 // R0 -= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$7FFF // R14 = $7FFF + sub r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$7FFF // R0 = $7FFF + iwt r14, #$8000 // R14 = $8000 + sub r14 // R0 -= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$BDD0 // R0 = $BDD0 + sub r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$BDD5 // R0 = $BDD5 + sub r15 // R0 -= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // SUB #const + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + sub #0 // R0 -= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8000 // R0 = $8000 + sub #0 // R0 -= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0001 // R0 = $0001 + sub #1 // R0 -= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8001 // R0 = $8001 + sub #1 // R0 -= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0002 // R0 = $0002 + sub #2 // R0 -= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8002 // R0 = $8002 + sub #2 // R0 -= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0003 // R0 = $0003 + sub #3 // R0 -= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8003 // R0 = $8003 + sub #3 // R0 -= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0004 // R0 = $0004 + sub #4 // R0 -= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8004 // R0 = $8004 + sub #4 // R0 -= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0005 // R0 = $0005 + sub #5 // R0 -= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8005 // R0 = $8005 + sub #5 // R0 -= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0006 // R0 = $0006 + sub #6 // R0 -= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8006 // R0 = $8006 + sub #6 // R0 -= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0007 // R0 = $0007 + sub #7 // R0 -= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8007 // R0 = $8007 + sub #7 // R0 -= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0008 // R0 = $0008 + sub #8 // R0 -= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8008 // R0 = $8008 + sub #8 // R0 -= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0009 // R0 = $0009 + sub #9 // R0 -= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$8009 // R0 = $8009 + sub #9 // R0 -= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000A // R0 = $000A + sub #10 // R0 -= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800A // R0 = $800A + sub #10 // R0 -= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000B // R0 = $000B + sub #11 // R0 -= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800B // R0 = $800B + sub #11 // R0 -= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000C // R0 = $000C + sub #12 // R0 -= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800C // R0 = $800C + sub #12 // R0 -= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000D // R0 = $000D + sub #13 // R0 -= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800D // R0 = $800D + sub #13 // R0 -= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000E // R0 = $000E + sub #14 // R0 -= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800E // R0 = $800E + sub #14 // R0 -= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000F // R0 = $000F + sub #15 // R0 -= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$800F // R0 = $800F + sub #15 // R0 -= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..32b4a777 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST SUB " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/make.bat new file mode 100644 index 00000000..cf91ca9c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/make.bat @@ -0,0 +1 @@ +bass GSUSUB.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.asm new file mode 100644 index 00000000..5959639d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.asm @@ -0,0 +1,1237 @@ +// SNES GSU Test SWAP (Hi/Lo Bytes) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUSWAP.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SWAPRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R2 // X = GSU R2 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R3 // X = GSU R3 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R4 // X = GSU R4 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R5 // X = GSU R5 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R6 // X = GSU R6 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R7 // X = GSU R7 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R8 // X = GSU R8 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R9 // X = GSU R9 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R10 // X = GSU R10 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R11 // X = GSU R11 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R12 // X = GSU R12 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R13 // X = GSU R13 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R14 // X = GSU R14 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(SWAPR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SWAPResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test SWAP (Hi/Lo Bytes):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +SWAPR0: + db "R0/$4D " +SWAPR1: + db "R1/$4D " +SWAPR2: + db "R2/$4D " +SWAPR3: + db "R3/$4D " +SWAPR4: + db "R4/$4D " +SWAPR5: + db "R5/$4D " +SWAPR6: + db "R6/$4D " +SWAPR7: + db "R7/$4D " +SWAPR8: + db "R8/$4D " +SWAPR9: + db "R9/$4D " +SWAPR10: + db "R10/$4D" +SWAPR11: + db "R11/$4D" +SWAPR12: + db "R12/$4D" +SWAPR13: + db "R13/$4D" +SWAPR14: + db "R14/$4D" +SWAPR15: + db "R15/$4D" + +Fail: + db "FAIL" +Pass: + db "PASS" + +SWAPRegister: + db "SWAP register (Opcode: $4D) " + +SWAPResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +SWAPResultCheckB: + dw $FEDC +SFRResultCheckB: + db $08 + +SWAPResultCheckC: + dw $AF9F + +// GSU Code +// BANK 0 +GSUROM: + include "GSUSWAP_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.png new file mode 100644 index 00000000..617b7ea3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.sfc new file mode 100644 index 00000000..50fc8337 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP_gsu.asm new file mode 100644 index 00000000..2ae09ae9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP_gsu.asm @@ -0,0 +1,192 @@ +// SNES GSU Test SWAP (Hi/Lo Bytes) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // SWAP register + //////////////////////////// + + iwt r0, #$0000 // R0 = $0000 + swap // R0 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$DCFE // R0 = $DCFE + swap // R0 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$0000 // R1 = $0000 + with r1 ; swap // R1 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$DCFE // R1 = $DCFE + with r1 ; swap // R1 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$0000 // R2 = $0000 + with r2 ; swap // R2 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r2, #$DCFE // R2 = $DCFE + with r2 ; swap // R2 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$0000 // R3 = $0000 + with r3 ; swap // R3 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r3, #$DCFE // R3 = $DCFE + with r3 ; swap // R3 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$0000 // R4 = $0000 + with r4 ; swap // R4 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r4, #$DCFE // R4 = $DCFE + with r4 ; swap // R4 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$0000 // R5 = $0000 + with r5 ; swap // R5 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r5, #$DCFE // R5 = $DCFE + with r5 ; swap // R5 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$0000 // R6 = $0000 + with r6 ; swap // R6 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r6, #$DCFE // R6 = $DCFE + with r6 ; swap // R6 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$0000 // R7 = $0000 + with r7 ; swap // R7 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r7, #$DCFE // R7 = $DCFE + with r7 ; swap // R7 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$0000 // R8 = $0000 + with r8 ; swap // R8 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r8, #$DCFE // R8 = $DCFE + with r8 ; swap // R8 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$0000 // R9 = $0000 + with r9 ; swap // R9 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r9, #$DCFE // R9 = $DCFE + with r9 ; swap // R9 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$0000 // R10 = $0000 + with r10 ; swap // R10 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r10, #$DCFE // R10 = $DCFE + with r10 ; swap // R10 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$0000 // R11 = $0000 + with r11 ; swap // R11 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r11, #$DCFE // R11 = $DCFE + with r11 ; swap // R11 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$0000 // R12 = $0000 + with r12 ; swap // R12 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r12, #$DCFE // R12 = $DCFE + with r12 ; swap // R12 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$0000 // R13 = $0000 + with r13 ; swap // R13 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r13, #$DCFE // R13 = $DCFE + with r13 ; swap // R13 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$0000 // R14 = $0000 + with r14 ; swap // R14 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r14, #$DCFE // R14 = $DCFE + with r14 ; swap // R14 >>= 8 + + stop // Stop GSU + nop // Delay Slot + + to r0 ; from r15 ; swap // R0 = R15 >> 8 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9b106f24 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST SWAP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/make.bat new file mode 100644 index 00000000..d64aa8e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/make.bat @@ -0,0 +1 @@ +bass GSUSWAP.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.asm new file mode 100644 index 00000000..0d809e0c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.asm @@ -0,0 +1,2317 @@ +// SNES GSU Test UMULT (Unsigned Multiply Byte) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUUMULT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(UMULTRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULTR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(UMULTConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$00FF + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$01FE + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$02FD + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$03FC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$04FB + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$05FA + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$06F9 + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$07F8 + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$08F7 + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$09F6 + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0AF5 + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0BF4 + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0CF3 + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0DF2 + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w UMULTResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(UMULT15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w #$0EF1 + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckC + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test UMULT (Multiply Byte)" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +UMULTR0: + db "R0/$80 " +UMULTR1: + db "R1/$81 " +UMULTR2: + db "R2/$82 " +UMULTR3: + db "R3/$83 " +UMULTR4: + db "R4/$84 " +UMULTR5: + db "R5/$85 " +UMULTR6: + db "R6/$86 " +UMULTR7: + db "R7/$87 " +UMULTR8: + db "R8/$88 " +UMULTR9: + db "R9/$89 " +UMULTR10: + db "R10/$8A" +UMULTR11: + db "R11/$8B" +UMULTR12: + db "R12/$8C" +UMULTR13: + db "R13/$8D" +UMULTR14: + db "R14/$8E" +UMULTR15: + db "R15/$8F" + +HASH: + db "#" +UMULT0: + db "#0/$80 " +UMULT1: + db "#1/$81 " +UMULT2: + db "#2/$82 " +UMULT3: + db "#3/$83 " +UMULT4: + db "#4/$84 " +UMULT5: + db "#5/$85 " +UMULT6: + db "#6/$86 " +UMULT7: + db "#7/$87 " +UMULT8: + db "#8/$88 " +UMULT9: + db "#9/$89 " +UMULT10: + db "#10/$8A" +UMULT11: + db "#11/$8B" +UMULT12: + db "#12/$8C" +UMULT13: + db "#13/$8D" +UMULT14: + db "#14/$8E" +UMULT15: + db "#15/$8F" + +Fail: + db "FAIL" +Pass: + db "PASS" + +UMULTRegister: + db "UMULT register (Opcode: $3D8n)" +UMULTConst: + db "UMULT #const (Opcode: $3F8n)" + +UMULTResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +UMULTResultCheckB: + dw $FE01 +SFRResultCheckB: + db $08 + +UMULTResultCheckC: + dw $F708 + +SFRResultCheckC: + db $00 + +// GSU Code +// BANK 0 +GSUROM: + include "GSUUMULT_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.png new file mode 100644 index 00000000..96f5885e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.sfc new file mode 100644 index 00000000..365a6835 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT_gsu.asm new file mode 100644 index 00000000..7cf3e44b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test UMULT (Unsigned Multiply Byte) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // UMULT register + //////////////////////////// + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$0000 // R0 = $0000 + with r1 ; umult r0 // R1 *= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$00FF // R0 = $00FF + with r1 ; umult r0 // R1 *= R0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r1, #$0000 // R1 = $0000 + umult r1 // R0 *= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r1, #$00FF // R1 = $00FF + umult r1 // R0 *= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r2, #$0000 // R2 = $0000 + umult r2 // R0 *= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r2, #$00FF // R2 = $00FF + umult r2 // R0 *= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r3, #$0000 // R3 = $0000 + umult r3 // R0 *= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r3, #$00FF // R3 = $00FF + umult r3 // R0 *= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r4, #$0000 // R4 = $0000 + umult r4 // R0 *= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r4, #$00FF // R4 = $00FF + umult r4 // R0 *= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r5, #$0000 // R5 = $0000 + umult r5 // R0 *= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r5, #$00FF // R5 = $00FF + umult r5 // R0 *= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r6, #$0000 // R6 = $0000 + umult r6 // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r6, #$00FF // R6 = $00FF + umult r6 // R0 *= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r7, #$0000 // R7 = $0000 + umult r7 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r7, #$00FF // R7 = $00FF + umult r7 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r8, #$0000 // R8 = $0000 + umult r8 // R0 *= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r8, #$00FF // R8 = $00FF + umult r8 // R0 *= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r9, #$0000 // R9 = $0000 + umult r9 // R0 *= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r9, #$00FF // R9 = $00FF + umult r9 // R0 *= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r10, #$0000 // R10 = $0000 + umult r10 // R0 *= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r10, #$00FF // R10 = $00FF + umult r10 // R0 *= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r11, #$0000 // R11 = $0000 + umult r11 // R0 *= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r11, #$00FF // R11 = $00FF + umult r11 // R0 *= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r12, #$0000 // R12 = $0000 + umult r12 // R0 *= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r12, #$00FF // R12 = $00FF + umult r12 // R0 *= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r13, #$0000 // R13 = $0000 + umult r13 // R0 *= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r13, #$00FF // R13 = $00FF + umult r13 // R0 *= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r14, #$0000 // R14 = $0000 + umult r14 // R0 *= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + iwt r14, #$00FF // R14 = $00FF + umult r14 // R0 *= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult r15 // R0 *= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult r15 // R0 *= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // UMULT #const + //////////////////////////// + + iwt r0, #$00FF // R0 = $00FF + umult #0 // R0 *= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$007F // R0 = $007F + umult #0 // R0 *= 0 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #1 // R0 *= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #1 // R0 *= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #2 // R0 *= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #2 // R0 *= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #3 // R0 *= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #3 // R0 *= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #4 // R0 *= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #4 // R0 *= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #5 // R0 *= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #5 // R0 *= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #6 // R0 *= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #6 // R0 *= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #7 // R0 *= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #7 // R0 *= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #8 // R0 *= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #8 // R0 *= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #9 // R0 *= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #9 // R0 *= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #10 // R0 *= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #10 // R0 *= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #11 // R0 *= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #11 // R0 *= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #12 // R0 *= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #12 // R0 *= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #13 // R0 *= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #13 // R0 *= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #14 // R0 *= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #14 // R0 *= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0000 // R0 = $0000 + umult #15 // R0 *= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$00FF // R0 = $00FF + umult #15 // R0 *= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d0a18712 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST UMULT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/make.bat new file mode 100644 index 00000000..7ef2c9d6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/make.bat @@ -0,0 +1 @@ +bass GSUUMULT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/Font8x8.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.asm new file mode 100644 index 00000000..77a9d530 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.asm @@ -0,0 +1,2314 @@ +// SNES GSU Test XOR (Exclusive-OR) demo by krom (Peter Lemon): +arch snes.cpu +output "GSUXOR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintSFR(SRC, DEST) { // Print GSU Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%00010000 // A = Overflow Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00001000 // A = Sign Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000100 // A = Carry Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}SFRFlagTest // Test SFR Flag Data + + bra {#}SFREnd + + {#}SFRFlagTest: + bit.b {SRC} // Test GSU Status Flag Data Bit + bne {#}SFRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}SFRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}SFREnd: +} + +macro GSUWait() { // Wait For GSU To Finish +{#}GSUBusy: + lda.w GSU_SFR // X = GSU Status/Flag Register + bit.b #GSU_SFR_GSU // Check GSU Is Running + bne {#}GSUBusy +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_GSU.INC" // Include GSU Definitions + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // GSU Result Data Word +SFRFlagData: + dw 0 // GSU Status/Flag Register Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%01111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $1F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + // Copy CPU Code To WRAM + rep #$20 // Set 16-Bit Accumulator + lda.w #(CPURAMEnd-CPURAM)-1 // A = Length + ldx.w #CPURAM // X = Source + ldy.w #CPURAM // Y = Destination + mvn $7E=$00 // Block Move Bytes To WRAM + CPURAM + sep #$20 // Set 8-Bit Accumulator + + lda.b #$00 // A = $00 + pha // Push A To Stack + plb // Data Bank = $00 + + jml $7E0000+CPURAM // Run CPU Code From WRAM + +CPURAM: // CPU Program Code To Be Run From RAM + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(XORRegister, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + // Setup GSU SNES Side + lda.b #GSU_CLSR_21MHz // Clock Data + sta.w GSU_CLSR // Set Operating Clock Frequency ($3039) + + lda.b #GSU_CFGR_IRQ_MASK // Config Data + sta.w GSU_CFGR // Set Config Register ($3037) + + stz.w GSU_SCBR // Set Screen Base ($3038) + stz.w GSU_PBR // Set Program Code Bank ($3034) + stz.w GSU_ROMBR // Set Game PAK ROM Bank ($3036) + stz.w GSU_RAMBR // Set Game PAK RAM Bank ($303C) + + lda.b #(GSU_RON|GSU_RAN|GSU_SCMR_2BPP|GSU_SCMR_H192) // Screen Size Mode + sta.w GSU_SCMR // Sets RON, RAN Flag, Screen Size & Color Number ($303A) + + ///////////////////////////////////////////////////////////////// + ldx.w #GSUROM // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R1 // X = GSU R1 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail9 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass10 + Fail10: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail10 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail11 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass12 + Fail12: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail12 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail13 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass14 + Fail14: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail14 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail15 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass16 + Fail16: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail16 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail25 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass26 + Fail26: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail26 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail27 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass28 + Fail28: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail28 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail29 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass30 + Fail30: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail30 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass31 + Fail31: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail31 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XORR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass32 + Fail32: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail32 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(XORConst, $F902, 30) // Load Text To VRAM Lo Bytes + + PrintText(HASH, $F982, 1) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR0, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR0, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR1, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR1, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR2, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR2, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR3, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR3, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR4, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail41 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR4, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass42 + Fail42: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail42 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR5, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass43 + Fail43: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail43 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR5, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass44 + Fail44: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail44 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR6, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail45 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR6, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass46 + Fail46: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail46 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR7, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass47 + Fail47: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail47 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR7, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass48 + Fail48: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail48 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $200, 0) // Clear VRAM Map To Fixed Tile Word + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR8, $FA02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR8, $FA42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FA64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR9, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR9, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FAE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR10, $FB02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR10, $FB42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FB64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR11, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR11, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FBE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR12, $FC02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail57 + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR12, $FC42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FC64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass58 + Fail58: + PrintText(Fail, $FC72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail58 + PrintText(Pass, $FC72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR13, $FC82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FC92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass59 + Fail59: + PrintText(Fail, $FCB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail59 + PrintText(Pass, $FCB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR13, $FCC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FCD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FCE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass60 + Fail60: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail60 + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR14, $FD02, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD12, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD24) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FD32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail61 + PrintText(Pass, $FD32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR14, $FD42, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD52, 2) // Print Result Data + PrintSFR(SFRFlagData, $FD64) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass62 + Fail62: + PrintText(Fail, $FD72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail62 + PrintText(Pass, $FD72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR15, $FD82, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FD92, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDA4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckA + beq Pass63 + Fail63: + PrintText(Fail, $FDB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckA + bne Fail63 + PrintText(Pass, $FDB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + ldx.w GSU_R15 // Program Address + stx.w GSU_R15 // Sets Program Counter ($301E) + GSUWait() // Wait For GSU To Finish + + // Store Result & GSU Status Flag Data + ldx.w GSU_R0 // X = GSU R0 (Result) + stx.b ResultData // Store Result To Memory + ldx.w GSU_SFR // X = GSU SFR (Status/Flag) + stx.b SFRFlagData // Store GSU Status Flag Data To Memory + + WaitNMI() // Wait For VSync + PrintText(XOR15, $FDC2, 7) // Load Text To VRAM Lo Bytes + + // Print Result & GSU Status Flag Data + PrintValue(ResultData, $FDD2, 2) // Print Result Data + PrintSFR(SFRFlagData, $FDE4) // Print GSU Status Flag Data + + // Check Result & GSU Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w XORResultCheckC + beq Pass64 + Fail64: + PrintText(Fail, $FDF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b SFRFlagData // A = GSU Status Flag Data + cmp.w SFRResultCheckB + bne Fail64 + PrintText(Pass, $FDF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + bra Loop +CPURAMEnd: + +Title: + db "GSU Test XOR (Exclusive-OR):" + +PageBreak: + db "------------------------------" + +Key: + db "Rn/Op | Result | VSCZ | Test |" + +XORR0: + db "R0/$C0 " +XORR1: + db "R1/$C1 " +XORR2: + db "R2/$C2 " +XORR3: + db "R3/$C3 " +XORR4: + db "R4/$C4 " +XORR5: + db "R5/$C5 " +XORR6: + db "R6/$C6 " +XORR7: + db "R7/$C7 " +XORR8: + db "R8/$C8 " +XORR9: + db "R9/$C9 " +XORR10: + db "R10/$CA" +XORR11: + db "R11/$CB" +XORR12: + db "R12/$CC" +XORR13: + db "R13/$CD" +XORR14: + db "R14/$CE" +XORR15: + db "R15/$CF" + +HASH: + db "#" +XOR0: + db "#0/$C0 " +XOR1: + db "#1/$C1 " +XOR2: + db "#2/$C2 " +XOR3: + db "#3/$C3 " +XOR4: + db "#4/$C4 " +XOR5: + db "#5/$C5 " +XOR6: + db "#6/$C6 " +XOR7: + db "#7/$C7 " +XOR8: + db "#8/$C8 " +XOR9: + db "#9/$C9 " +XOR10: + db "#10/$CA" +XOR11: + db "#11/$CB" +XOR12: + db "#12/$CC" +XOR13: + db "#13/$CD" +XOR14: + db "#14/$CE" +XOR15: + db "#15/$CF" + +Fail: + db "FAIL" +Pass: + db "PASS" + +XORRegister: + db "XOR register (Opcode: $3DCn)" +XORConst: + db "XOR #const (Opcode: $3FCn)" + +XORResultCheckA: + dw $0000 +SFRResultCheckA: + db $02 + +XORResultCheckB: + dw $00FF +SFRResultCheckB: + db $08 + +XORResultCheckC: + dw $FFFF + +// GSU Code +// BANK 0 +GSUROM: + include "GSUXOR_gsu.asm" // Include GSU ROM Data + +// BG Data +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.png b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.png new file mode 100644 index 00000000..b01a2b48 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.png differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.sfc b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.sfc new file mode 100644 index 00000000..9160c6a2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR_gsu.asm b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR_gsu.asm new file mode 100644 index 00000000..f46fa2b1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR_gsu.asm @@ -0,0 +1,425 @@ +// SNES GSU Test XOR (Exclusive-OR) demo (GSU Code) by krom (Peter Lemon): +arch snes.gsu + +GSUStart: + //////////////////////////// + // XOR register + //////////////////////////// + + iwt r1, #$00FF // R1 = $00FF + iwt r0, #$00FF // R0 = $00FF + with r1 ; xor r0 // R1 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r1, #$FF00 // R1 = $FF00 + iwt r0, #$FF00 // R0 = $FF00 + with r1 ; xor r0 // R1 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$FFFF // R1 = $FFFF + xor r1 // R0 ^= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r1, #$0000 // R1 = $0000 + xor r1 // R0 ^= R1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$FFFF // R2 = $FFFF + xor r2 // R0 ^= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r2, #$0000 // R2 = $0000 + xor r2 // R0 ^= R2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$FFFF // R3 = $FFFF + xor r3 // R0 ^= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r3, #$0000 // R3 = $0000 + xor r3 // R0 ^= R3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$FFFF // R4 = $FFFF + xor r4 // R0 ^= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r4, #$0000 // R4 = $0000 + xor r4 // R0 ^= R4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$FFFF // R5 = $FFFF + xor r5 // R0 ^= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r5, #$0000 // R5 = $0000 + xor r5 // R0 ^= R5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$FFFF // R6 = $FFFF + xor r6 // R0 ^= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r6, #$0000 // R6 = $0000 + xor r6 // R0 ^= R6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$FFFF // R7 = $FFFF + xor r7 // R0 ^= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r7, #$0000 // R7 = $0000 + xor r7 // R0 ^= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$FFFF // R8 = $FFFF + xor r8 // R0 ^= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r8, #$0000 // R8 = $0000 + xor r8 // R0 ^= R8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$FFFF // R9 = $FFFF + xor r9 // R0 ^= R7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r9, #$0000 // R9 = $0000 + xor r9 // R0 ^= R9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$FFFF // R10 = $FFFF + xor r10 // R0 ^= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r10, #$0000 // R10 = $0000 + xor r10 // R0 ^= R10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$FFFF // R11 = $FFFF + xor r11 // R0 ^= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r11, #$0000 // R11 = $0000 + xor r11 // R0 ^= R11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$FFFF // R12 = $FFFF + xor r12 // R0 ^= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r12, #$0000 // R12 = $0000 + xor r12 // R0 ^= R12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$FFFF // R13 = $FFFF + xor r13 // R0 ^= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r13, #$0000 // R13 = $0000 + xor r13 // R0 ^= R13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$FFFF // R14 = $FFFF + xor r14 // R0 ^= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFF // R0 = $FFFF + iwt r14, #$0000 // R14 = $0000 + xor r14 // R0 ^= R14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$BDEE // R0 = $BDEE + xor r15 // R0 ^= R15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$420A // R0 = $420A + xor r15 // R0 ^= R15 + + stop // Stop GSU + nop // Delay Slot + + //////////////////////////// + // XOR #const + //////////////////////////// + + iwt r0, #$00FF // R0 = $00FF + xor #0 // R0 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FF00 // R0 = $FF00 + xor #0 // R0 >>= 8 (HIB) + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0001 // R0 = $0001 + xor #1 // R0 ^= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFE // R0 = $FFFE + xor #1 // R0 ^= 1 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0002 // R0 = $0002 + xor #2 // R0 ^= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFD // R0 = $FFFD + xor #2 // R0 ^= 2 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0003 // R0 = $0003 + xor #3 // R0 ^= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFC // R0 = $FFFC + xor #3 // R0 ^= 3 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0004 // R0 = $0004 + xor #4 // R0 ^= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFB // R0 = $FFFB + xor #4 // R0 ^= 4 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0005 // R0 = $0005 + xor #5 // R0 ^= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFFA // R0 = $FFFA + xor #5 // R0 ^= 5 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0006 // R0 = $0006 + xor #6 // R0 ^= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF9 // R0 = $FFF9 + xor #6 // R0 ^= 6 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0007 // R0 = $0007 + xor #7 // R0 ^= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF8 // R0 = $FFF8 + xor #7 // R0 ^= 7 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0008 // R0 = $0008 + xor #8 // R0 ^= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF7 // R0 = $FFF7 + xor #8 // R0 ^= 8 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$0009 // R0 = $0009 + xor #9 // R0 ^= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF6 // R0 = $FFF6 + xor #9 // R0 ^= 9 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000A // R0 = $000A + xor #10 // R0 ^= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF5 // R0 = $FFF5 + xor #10 // R0 ^= 10 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000B // R0 = $000B + xor #11 // R0 ^= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF4 // R0 = $FFF4 + xor #11 // R0 ^= 11 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000C // R0 = $000C + xor #12 // R0 ^= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF3 // R0 = $FFF3 + xor #12 // R0 ^= 12 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000D // R0 = $000D + xor #13 // R0 ^= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF2 // R0 = $FFF2 + xor #13 // R0 ^= 13 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000E // R0 = $000E + xor #14 // R0 ^= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF1 // R0 = $FFF1 + xor #14 // R0 ^= 14 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$000F // R0 = $000F + xor #15 // R0 ^= 15 + + stop // Stop GSU + nop // Delay Slot + + iwt r0, #$FFF0 // R0 = $FFF0 + xor #15 // R0 ^= 15 + + stop // Stop GSU + nop // Delay Slot \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..6cd63f50 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/LIB/SNES_HEADER.ASM @@ -0,0 +1,103 @@ +//============= +// SNES Header +//============= +// Extended Header +seek($FFB0) +db 0,0 // Maker Code +db "KROM" // Game Code +fill 7 // Fill 7 Bytes +db 6 // Ext Cart RAM SIZE (GSU) +db 0 // Special Version +db 0 // Cartridge Sub-Number + +// Normal Header +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GSU TEST XOR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $14 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $33 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/make.bat b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/make.bat new file mode 100644 index 00000000..198a1796 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/make.bat @@ -0,0 +1 @@ +bass GSUXOR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.asm new file mode 100644 index 00000000..34faffb8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.asm @@ -0,0 +1,5231 @@ +// SNES 65816 CPU Test ADC (Add With Carry) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUADC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ADCConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + adc.b #$81 // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + adc.b #$7F // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + adc.w #$8001 // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + adc.w #$7FFF // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$49 // A = $49 + adc.b #$51 // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + adc.b #$49 // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + adc.w #$5001 // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + adc.w #$4999 // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.w AbsoluteData // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.w AbsoluteData // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.w AbsoluteData // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.w AbsoluteData // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.w AbsoluteData // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass13 + Fail13: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail13 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.w AbsoluteData // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass14 + Fail14: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail14 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.w AbsoluteData // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass15 + Fail15: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail15 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.w AbsoluteData // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass16 + Fail16: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail16 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.l AbsoluteData // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.l AbsoluteData // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.l AbsoluteData // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.l AbsoluteData // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.l AbsoluteData // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.l AbsoluteData // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.l AbsoluteData // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.l AbsoluteData // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.b AbsoluteData // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + adc.b AbsoluteData // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.b AbsoluteData // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + adc.b AbsoluteData // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.b AbsoluteData // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass29 + Fail29: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail29 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + adc.b AbsoluteData // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass30 + Fail30: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail30 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.b AbsoluteData // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass31 + Fail31: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail31 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + adc.b AbsoluteData // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass32 + Fail32: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail32 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + adc (IndirectData) // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + adc (IndirectData) // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + adc (IndirectData) // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + adc (IndirectData) // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + adc (IndirectData) // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + adc (IndirectData) // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + adc (IndirectData) // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + adc (IndirectData) // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + adc [IndirectData] // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + adc [IndirectData] // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + adc [IndirectData] // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + adc [IndirectData] // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + adc [IndirectData] // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass45 + Fail45: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail45 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + adc [IndirectData] // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass46 + Fail46: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail46 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + adc [IndirectData] // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass47 + Fail47: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail47 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + adc [IndirectData] // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass48 + Fail48: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail48 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.w AbsoluteData,x // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.w AbsoluteData,x // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.w AbsoluteData,x // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.w AbsoluteData,x // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.w AbsoluteData,x // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.w AbsoluteData,x // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.w AbsoluteData,x // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.w AbsoluteData,x // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCLongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.l AbsoluteData,x // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.l AbsoluteData,x // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.l AbsoluteData,x // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.l AbsoluteData,x // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.l AbsoluteData,x // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass61 + Fail61: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail61 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.l AbsoluteData,x // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass62 + Fail62: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail62 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.l AbsoluteData,x // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass63 + Fail63: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail63 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.l AbsoluteData,x // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass64 + Fail64: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail64 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc AbsoluteData,y // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass65 + Fail65: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail65 + Pass65: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail65 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc AbsoluteData,y // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass66 + Fail66: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail66 + Pass66: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail66 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc AbsoluteData,y // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass67 + Fail67: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail67 + Pass67: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail67 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc AbsoluteData,y // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass68 + Fail68: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail68 + Pass68: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail68 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc AbsoluteData,y // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass69 + Fail69: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail69 + Pass69: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail69 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc AbsoluteData,y // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass70 + Fail70: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail70 + Pass70: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail70 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc AbsoluteData,y // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass71 + Fail71: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail71 + Pass71: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail71 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc AbsoluteData,y // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass72 + Fail72: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail72 + Pass72: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail72 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.b AbsoluteData,x // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass73 + Fail73: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail73 + Pass73: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail73 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc.b AbsoluteData,x // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass74 + Fail74: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail74 + Pass74: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail74 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.b AbsoluteData,x // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass75 + Fail75: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail75 + Pass75: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail75 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc.b AbsoluteData,x // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass76 + Fail76: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail76 + Pass76: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail76 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.b AbsoluteData,x // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass77 + Fail77: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail77 + Pass77: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail77 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc.b AbsoluteData,x // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass78 + Fail78: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail78 + Pass78: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail78 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.b AbsoluteData,x // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass79 + Fail79: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail79 + Pass79: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail79 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc.b AbsoluteData,x // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass80 + Fail80: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail80 + Pass80: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail80 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc (IndirectData,x) // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass81 + Fail81: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail81 + Pass81: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail81 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + adc (IndirectData,x) // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass82 + Fail82: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail82 + Pass82: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail82 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc (IndirectData,x) // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass83 + Fail83: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail83 + Pass83: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail83 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + adc (IndirectData,x) // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass84 + Fail84: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail84 + Pass84: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail84 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc (IndirectData,x) // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass85 + Fail85: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail85 + Pass85: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail85 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + adc (IndirectData,x) // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass86 + Fail86: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail86 + Pass86: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail86 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc (IndirectData,x) // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass87 + Fail87: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail87 + Pass87: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail87 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + adc (IndirectData,x) // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass88 + Fail88: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail88 + Pass88: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail88 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc (IndirectData),y // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass89 + Fail89: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail89 + Pass89: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail89 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc (IndirectData),y // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass90 + Fail90: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail90 + Pass90: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail90 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc (IndirectData),y // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass91 + Fail91: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail91 + Pass91: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail91 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc (IndirectData),y // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass92 + Fail92: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail92 + Pass92: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail92 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc (IndirectData),y // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass93 + Fail93: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail93 + Pass93: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail93 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc (IndirectData),y // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass94 + Fail94: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail94 + Pass94: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail94 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc (IndirectData),y // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass95 + Fail95: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail95 + Pass95: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail95 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc (IndirectData),y // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass96 + Fail96: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail96 + Pass96: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail96 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc [IndirectData],y // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass97 + Fail97: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail97 + Pass97: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail97 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc [IndirectData],y // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass98 + Fail98: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail98 + Pass98: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail98 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc [IndirectData],y // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass99 + Fail99: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail99 + Pass99: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail99 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc [IndirectData],y // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass100 + Fail100: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail100 + Pass100: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail100 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc [IndirectData],y // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass101 + Fail101: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail101 + Pass101: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail101 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc [IndirectData],y // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass102 + Fail102: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail102 + Pass102: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail102 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc [IndirectData],y // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass103 + Fail103: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail103 + Pass103: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail103 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc [IndirectData],y // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass104 + Fail104: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail104 + Pass104: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail104 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCSRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + pha // Push A To Stack + lda.b #$7F // A = $7F + adc $01,s // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass105 + Fail105: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail105 + Pass105: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail105 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + pha // Push A To Stack + lda.b #$7F // A = $7F + adc $01,s // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass106 + Fail106: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail106 + Pass106: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail106 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + pha // Push A To Stack + lda.w #$7FFF // A = $7FFF + adc $01,s // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass107 + Fail107: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail107 + Pass107: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail107 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + pha // Push A To Stack + lda.w #$7FFF // A = $7FFF + adc $01,s // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass108 + Fail108: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail108 + Pass108: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail108 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + pha // Push A To Stack + lda.b #$49 // A = $49 + adc $01,s // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass109 + Fail109: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail109 + Pass109: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail109 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + pha // Push A To Stack + lda.b #$49 // A = $49 + adc $01,s // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass110 + Fail110: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail110 + Pass110: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail110 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + pha // Push A To Stack + lda.w #$4999 // A = $4999 + adc $01,s // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass111 + Fail111: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail111 + Pass111: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail111 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + pha // Push A To Stack + lda.w #$4999 // A = $4999 + adc $01,s // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass112 + Fail112: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail112 + Pass112: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail112 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCSRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc ($01,s),y // A += $81 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckA + beq Pass113 + Fail113: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail113 + Pass113: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail113 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + adc ($01,s),y // A += $7F + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckB + beq Pass114 + Fail114: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail114 + Pass114: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail114 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc ($01,s),y // A += $8001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckC + beq Pass115 + Fail115: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail115 + Pass115: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail115 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + adc ($01,s),y // A += $7FFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckD + beq Pass116 + Fail116: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail116 + Pass116: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail116 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$51 // A = $51 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc ($01,s),y // A += $51 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckE + beq Pass117 + Fail117: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail117 + Pass117: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail117 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + adc ($01,s),y // A += $49 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ADCResultCheckF + beq Pass118 + Fail118: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail118 + Pass118: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail118 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$5001 // A = $5001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc ($01,s),y // A += $5001 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckG + beq Pass119 + Fail119: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail119 + Pass119: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail119 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + adc ($01,s),y // A += $4999 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ADCResultCheckH + beq Pass120 + Fail120: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail120 + Pass120: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail120 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test ADC (Add With Carry):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Decimal8Bit: + db "BCD,8" +Decimal16Bit: + db "BCD,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +ADCConst: + db "ADC #const (Opcode: $69)" +ADCAddr: + db "ADC addr (Opcode: $6D)" +ADCLong: + db "ADC long (Opcode: $6F)" +ADCDP: + db "ADC dp (Opcode: $65)" +ADCDPIndirect: + db "ADC (dp) (Opcode: $72)" +ADCDPIndirectLong: + db "ADC [dp] (Opcode: $67)" +ADCAddrX: + db "ADC addr,X (Opcode: $7D)" +ADCLongX: + db "ADC long,X (Opcode: $7F)" +ADCAddrY: + db "ADC addr,Y (Opcode: $79)" +ADCDPX: + db "ADC dp,X (Opcode: $75)" +ADCDPIndirectX: + db "ADC (dp,X) (Opcode: $61)" +ADCDPIndirectY: + db "ADC (dp),Y (Opcode: $71)" +ADCDPIndirectLongY: + db "ADC [dp],Y (Opcode: $77)" +ADCSRS: + db "ADC sr,S (Opcode: $63)" +ADCSRSY: + db "ADC (sr,S),Y (Opcode: $73)" + +ADCResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +ADCResultCheckB: + db $FF +PSRResultCheckB: + db $E4 + +ADCResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +ADCResultCheckD: + dw $FFFF +PSRResultCheckD: + db $C4 + +ADCResultCheckE: + db $00 +PSRResultCheckE: + db $6F + +ADCResultCheckF: + db $99 +PSRResultCheckF: + db $EC + +ADCResultCheckG: + dw $0000 +PSRResultCheckG: + db $4F + +ADCResultCheckH: + dw $9999 +PSRResultCheckH: + db $CC + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.png new file mode 100644 index 00000000..cda0fa10 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.sfc new file mode 100644 index 00000000..0e1ce851 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..35f8892b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST ADC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/make.bat new file mode 100644 index 00000000..6b1943a4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ADC/make.bat @@ -0,0 +1 @@ +bass CPUADC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.asm new file mode 100644 index 00000000..5b59fd90 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.asm @@ -0,0 +1,2772 @@ +// SNES 65816 CPU Test AND (AND With Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUAND.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ANDConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + and.b #$00 // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + and.b #$FF // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + and.w #$0000 // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + and.w #$FFFF // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.w AbsoluteData // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.w AbsoluteData // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.w AbsoluteData // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.w AbsoluteData // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.l AbsoluteData // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.l AbsoluteData // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.l AbsoluteData // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.l AbsoluteData // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.b AbsoluteData // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + and.b AbsoluteData // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.b AbsoluteData // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + and.b AbsoluteData // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + and (IndirectData) // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + and (IndirectData) // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + and (IndirectData) // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + and (IndirectData) // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + and [IndirectData] // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + and [IndirectData] // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + and [IndirectData] // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + and [IndirectData] // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.w AbsoluteData,x // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.w AbsoluteData,x // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.w AbsoluteData,x // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.w AbsoluteData,x // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDLongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.l AbsoluteData,x // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.l AbsoluteData,x // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.l AbsoluteData,x // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.l AbsoluteData,x // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and AbsoluteData,y // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and AbsoluteData,y // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and AbsoluteData,y // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and AbsoluteData,y // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.b AbsoluteData,x // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and.b AbsoluteData,x // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.b AbsoluteData,x // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and.b AbsoluteData,x // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and (IndirectData,x) // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + and (IndirectData,x) // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and (IndirectData,x) // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + and (IndirectData,x) // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and (IndirectData),y // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and (IndirectData),y // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and (IndirectData),y // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and (IndirectData),y // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and [IndirectData],y // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and [IndirectData],y // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and [IndirectData],y // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and [IndirectData],y // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDSRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + pha // Push A To Stack + lda.b #$FF // A = $FF + and $01,s // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + pha // Push A To Stack + lda.b #$FF // A = $FF + and $01,s // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + and $01,s // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + and $01,s // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDSRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and ($01,s),y // A &= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + and ($01,s),y // A &= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ANDResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and ($01,s),y // A &= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + and ($01,s),y // A &= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ANDResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test AND (AND With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +ANDConst: + db "AND #const (Opcode: $29)" +ANDAddr: + db "AND addr (Opcode: $2D)" +ANDLong: + db "AND long (Opcode: $2F)" +ANDDP: + db "AND dp (Opcode: $25)" +ANDDPIndirect: + db "AND (dp) (Opcode: $32)" +ANDDPIndirectLong: + db "AND [dp] (Opcode: $27)" +ANDAddrX: + db "AND addr,X (Opcode: $3D)" +ANDLongX: + db "AND long,X (Opcode: $3F)" +ANDAddrY: + db "AND addr,Y (Opcode: $39)" +ANDDPX: + db "AND dp,X (Opcode: $35)" +ANDDPIndirectX: + db "AND (dp,X) (Opcode: $21)" +ANDDPIndirectY: + db "AND (dp),Y (Opcode: $31)" +ANDDPIndirectLongY: + db "AND [dp],Y (Opcode: $37)" +ANDSRS: + db "AND sr,S (Opcode: $23)" +ANDSRSY: + db "AND (sr,S),Y (Opcode: $33)" + +ANDResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +ANDResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +ANDResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +ANDResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.png new file mode 100644 index 00000000..30b48fb2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.sfc new file mode 100644 index 00000000..eb5adcce Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..3180514b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST AND " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/make.bat new file mode 100644 index 00000000..3b8874ee --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/AND/make.bat @@ -0,0 +1 @@ +bass CPUAND.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.asm new file mode 100644 index 00000000..f43150fa --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.asm @@ -0,0 +1,996 @@ +// SNES 65816 CPU Test ASL (Arithmetic Shift Left) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUASL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 26) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ASLA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + asl // A <<= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ASLResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + asl // A <<= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ASLResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + asl // A <<= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASLResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + asl // A <<= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ASLResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ASLAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + asl.w AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + asl.w AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + asl.w AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + asl.w AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ASLDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + asl.b AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + asl.b AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + asl.b AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + asl.b AbsoluteData // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ASLAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.w AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.w AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.w AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.w AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ASLDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.b AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.b AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ASLResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.b AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + asl.b AbsoluteData,x // Memory <<= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ASLResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test ASL (Shift Left):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +ASLA: + db "ASL A (Opcode: $0A)" +ASLAddr: + db "ASL addr (Opcode: $0E)" +ASLDP: + db "ASL dp (Opcode: $06)" +ASLAddrX: + db "ASL addr,X (Opcode: $1E)" +ASLDPX: + db "ASL dp,X (Opcode: $16)" + +ASLResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +ASLResultCheckB: + db $FE +PSRResultCheckB: + db $A4 + +ASLResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +ASLResultCheckD: + dw $FFFE +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.png new file mode 100644 index 00000000..cee785c9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.sfc new file mode 100644 index 00000000..2671db8b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..0d76e9f2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST ASL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/make.bat new file mode 100644 index 00000000..791b576e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ASL/make.bat @@ -0,0 +1 @@ +bass CPUASL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.asm new file mode 100644 index 00000000..0b0be90f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.asm @@ -0,0 +1,1728 @@ +// SNES 65816 CPU Test BIT (Test Memory Bits) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUBIT.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(BITConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + bit.b #$00 // A & $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w BITConstResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRConstResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + bit.b #$FF // A & $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w BITConstResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRConstResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + bit.w #$0000 // A & $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BITConstResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRConstResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + bit.w #$FFFF // A & $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w BITConstResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRConstResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(BITAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + bit.w AbsoluteData // A & $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + bit.w AbsoluteData // A & $FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + bit.w AbsoluteData // A & $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + bit.w AbsoluteData // A & $FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(BITDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + bit.b AbsoluteData // A & $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + bit.b AbsoluteData // A & $FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + bit.b AbsoluteData // A & $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + bit.b AbsoluteData // A & $FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(BITAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + bit.w AbsoluteData,x // A & $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + bit.w AbsoluteData,x // A & $FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + bit.w AbsoluteData,x // A & $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + bit.w AbsoluteData,x // A & $FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(BITDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + bit.b AbsoluteData,x // A & $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + bit.b AbsoluteData,x // A & $FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + bit.b AbsoluteData,x // A & $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + bit.b AbsoluteData,x // A & $FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRBAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + rep #$80 // Reset Negative Flag + trb.w AbsoluteData // A & ~$FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckE + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + trb.w AbsoluteData // A & ~$FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckF + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + rep #$80 // Reset Negative Flag + trb.w AbsoluteData // A & ~$FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckG + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + trb.w AbsoluteData // A & ~$FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckH + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRBDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + rep #$80 // Reset Negative Flag + trb.b AbsoluteData // A & ~$FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckE + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + trb.b AbsoluteData // A & ~$FF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckF + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + rep #$80 // Reset Negative Flag + trb.b AbsoluteData // A & ~$FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckG + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + trb.b AbsoluteData // A & ~$FFFF + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckH + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TSBAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + tsb.w AbsoluteData // A | $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckI + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckI + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + tsb.w AbsoluteData // A | $F0 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckJ + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckJ + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + tsb.w AbsoluteData // A | $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckK + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckK + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$F000 // A = $F000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + tsb.w AbsoluteData // A | $F000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckL + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckL + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TSBDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + tsb.b AbsoluteData // A | $00 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckI + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckI + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + tsb.b AbsoluteData // A | $F0 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w BITResultCheckJ + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckJ + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + tsb.b AbsoluteData // A | $0000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckK + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckK + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$F000 // A = $F000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + tsb.b AbsoluteData // A | $F000 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w BITResultCheckL + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckL + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test BIT (Test Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +BITConst: + db "BIT #const (Opcode: $89)" +BITAddr: + db "BIT addr (Opcode: $2C)" +BITDP: + db "BIT dp (Opcode: $24)" +BITAddrX: + db "BIT addr,X (Opcode: $3C)" +BITDPX: + db "BIT dp,X (Opcode: $34)" +TRBAddr: + db "TRB addr (Opcode: $1C)" +TRBDP: + db "TRB dp (Opcode: $14)" +TSBAddr: + db "TSB addr (Opcode: $0C)" +TSBDP: + db "TSB dp (Opcode: $04)" + +BITConstResultCheckA: + db $00 +PSRConstResultCheckA: + db $26 + +BITConstResultCheckB: + db $7F +PSRConstResultCheckB: + db $24 + +BITConstResultCheckC: + dw $0000 +PSRConstResultCheckC: + db $06 + +BITConstResultCheckD: + dw $7FFF +PSRConstResultCheckD: + db $04 + +BITResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +BITResultCheckB: + db $FF +PSRResultCheckB: + db $E4 + +BITResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +BITResultCheckD: + dw $FFFF +PSRResultCheckD: + db $C4 + +BITResultCheckE: + db $00 +PSRResultCheckE: + db $24 + +BITResultCheckF: + db $FF +PSRResultCheckF: + db $26 + +BITResultCheckG: + dw $0000 +PSRResultCheckG: + db $04 + +BITResultCheckH: + dw $FFFF +PSRResultCheckH: + db $06 + +BITResultCheckI: + db $00 +PSRResultCheckI: + db $26 + +BITResultCheckJ: + db $FF +PSRResultCheckJ: + db $24 + +BITResultCheckK: + dw $0000 +PSRResultCheckK: + db $06 + +BITResultCheckL: + dw $FFFF +PSRResultCheckL: + db $04 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.png new file mode 100644 index 00000000..d3c97e86 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.sfc new file mode 100644 index 00000000..91c3e4ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..667afba1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST BIT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/make.bat new file mode 100644 index 00000000..d77d0d72 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BIT/make.bat @@ -0,0 +1 @@ +bass CPUBIT.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.asm new file mode 100644 index 00000000..ab5bd5d7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.asm @@ -0,0 +1,397 @@ +// SNES 65816 CPU Test BRA (Branch) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUBRA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 22) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BCCBranch, $F9C2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$C3 // Set NVZC Flags + clc // Clear Carry Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $F9E4) // Print Processor Status Flag Data + + // Run Test + clc // Clear Carry Flag + bcc Pass1 + Fail1: + PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BCSBranch, $FA02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sec // Set Carry Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Run Test + sec // Set Carry Flag + bcs Pass2 + Fail2: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BNEBranch, $FA42, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$C3 // Set NVZC Flags + rep #$02 // Reset Zero Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Run Test + rep #$02 // Reset Zero Flag + bne Pass3 + Fail3: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BEQBranch, $FA82, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$02 // Set Zero Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Run Test + sep #$02 // Set Zero Flag + beq Pass4 + Fail4: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BVCBranch, $FAC2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$C3 // Set NVZC Flags + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Run Test + clv // Clear Overflow Flag + bvc Pass5 + Fail5: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BVSBranch, $FB02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$40 // Set Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Run Test + sep #$40 // Set Overflow Flag + bvs Pass6 + Fail6: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BPLBranch, $FB42, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$C3 // Set NVZC Flags + rep #$80 // Reset Negative Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Run Test + rep #$80 // Reset Negative Flag + bpl Pass7 + Fail7: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BMIBranch, $FB82, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$80 // Set Negative Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Run Test + sep #$80 // Set Negative Flag + bmi Pass8 + Fail8: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BRABranch, $FBC2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Run Test + bra Pass9 + Fail9: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BRLBranch, $FC02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FC24) // Print Processor Status Flag Data + + // Run Test + brl Pass10 + Fail10: + PrintText(Fail, $FC32, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + PrintText(Pass, $FC32, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test BRA (Branch):" + +PageBreak: + db "------------------------------" + +Key: + db "Type | Opcode | NVZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +BCCBranch: + db "BCC $90" +BCSBranch: + db "BCS $B0" +BNEBranch: + db "BNE $D0" +BEQBranch: + db "BEQ $F0" +BVCBranch: + db "BVC $50" +BVSBranch: + db "BVS $70" +BPLBranch: + db "BPL $10" +BMIBranch: + db "BMI $30" +BRABranch: + db "BRA $80" +BRLBranch: + db "BRL $82" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.png new file mode 100644 index 00000000..acbe7f73 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.sfc new file mode 100644 index 00000000..655eeaa4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a32c84e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST BRA " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/make.bat new file mode 100644 index 00000000..2ec84939 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/BRA/make.bat @@ -0,0 +1 @@ +bass CPUBRA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.asm new file mode 100644 index 00000000..a51e0921 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.asm @@ -0,0 +1,3694 @@ +// SNES 65816 CPU Test CMP (Compare With Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUCMP.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(CMPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + cmp.b #$FF // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$FF // A = $FF + cmp.b #$00 // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + cmp.w #$FFFF // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + cmp.w #$0000 // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.w AbsoluteData // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.w AbsoluteData // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.w AbsoluteData // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.w AbsoluteData // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.l AbsoluteData // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.l AbsoluteData // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.l AbsoluteData // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.l AbsoluteData // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.b AbsoluteData // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + cmp.b AbsoluteData // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.b AbsoluteData // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + cmp.b AbsoluteData // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + cmp (IndirectData) // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + cmp (IndirectData) // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + cmp (IndirectData) // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + cmp (IndirectData) // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + cmp [IndirectData] // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + cmp [IndirectData] // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + cmp [IndirectData] // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + cmp [IndirectData] // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.w AbsoluteData,x // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.w AbsoluteData,x // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.w AbsoluteData,x // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.w AbsoluteData,x // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPLongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.l AbsoluteData,x // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.l AbsoluteData,x // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.l AbsoluteData,x // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.l AbsoluteData,x // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp AbsoluteData,y // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp AbsoluteData,y // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp AbsoluteData,y // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp AbsoluteData,y // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.b AbsoluteData,x // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp.b AbsoluteData,x // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.b AbsoluteData,x // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp.b AbsoluteData,x // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp (IndirectData,x) // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + cmp (IndirectData,x) // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp (IndirectData,x) // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + cmp (IndirectData,x) // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp (IndirectData),y // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp (IndirectData),y // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp (IndirectData),y // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp (IndirectData),y // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPDPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp [IndirectData],y // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp [IndirectData],y // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp [IndirectData],y // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp [IndirectData],y // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPSRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + pha // Push A To Stack + lda.b #$FF // A = $FF + cmp $01,s // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + pha // Push A To Stack + lda.b #$FF // A = $FF + cmp $01,s // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + cmp $01,s // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + cmp $01,s // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CMPSRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp ($01,s),y // A -= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + cmp ($01,s),y // A -= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp ($01,s),y // A -= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + cmp ($01,s),y // A -= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPXConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + cpx.b #$FF // X -= $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass61 + Fail61: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail61 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldx.b #$FF // X = $FF + cpx.b #$00 // X -= $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass62 + Fail62: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail62 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$FFFF // X = $FFFF + cpx.w #$FFFF // X -= $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass63 + Fail63: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail63 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$FFFF // X = $FFFF + cpx.w #$0000 // X -= $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass64 + Fail64: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail64 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPXAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldx.b #$FF // X = $FF + cpx.w AbsoluteData // X -= $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass65 + Fail65: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail65 + Pass65: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail65 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldx.b #$FF // X = $FF + cpx.w AbsoluteData // X -= $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass66 + Fail66: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail66 + Pass66: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail66 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldx.w #$FFFF // X = $FFFF + cpx.w AbsoluteData // X -= $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass67 + Fail67: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail67 + Pass67: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail67 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldx.w #$FFFF // X = $FFFF + cpx.w AbsoluteData // X -= $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass68 + Fail68: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail68 + Pass68: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail68 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPXDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldx.b #$FF // X = $FF + cpx.b AbsoluteData // X -= $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass69 + Fail69: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail69 + Pass69: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail69 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldx.b #$FF // X = $FF + cpx.b AbsoluteData // X -= $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass70 + Fail70: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail70 + Pass70: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail70 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldx.w #$FFFF // X = $FFFF + cpx.b AbsoluteData // X -= $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass71 + Fail71: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail71 + Pass71: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail71 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldx.w #$FFFF // X = $FFFF + cpx.b AbsoluteData // X -= $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass72 + Fail72: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail72 + Pass72: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail72 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPYConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + cpy.b #$FF // Y -= $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass73 + Fail73: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail73 + Pass73: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail73 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldy.b #$FF // Y = $FF + cpy.b #$00 // Y -= $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass74 + Fail74: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail74 + Pass74: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail74 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$FFFF // Y = $FFFF + cpy.w #$FFFF // Y -= $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass75 + Fail75: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail75 + Pass75: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail75 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$FFFF // Y = $FFFF + cpy.w #$0000 // Y -= $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass76 + Fail76: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail76 + Pass76: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail76 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPYAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldy.b #$FF // Y = $FF + cpy.w AbsoluteData // Y -= $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass77 + Fail77: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail77 + Pass77: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail77 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldy.b #$FF // Y = $FF + cpy.w AbsoluteData // Y -= $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass78 + Fail78: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail78 + Pass78: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail78 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldy.w #$FFFF // Y = $FFFF + cpy.w AbsoluteData // Y -= $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass79 + Fail79: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail79 + Pass79: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail79 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldy.w #$FFFF // Y = $FFFF + cpy.w AbsoluteData // Y -= $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass80 + Fail80: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail80 + Pass80: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail80 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(CPYDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldy.b #$FF // Y = $FF + cpy.b AbsoluteData // Y -= $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckE + beq Pass81 + Fail81: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail81 + Pass81: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail81 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldy.b #$FF // Y = $FF + cpy.b AbsoluteData // Y -= $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w CMPResultCheckF + beq Pass82 + Fail82: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail82 + Pass82: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail82 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldy.w #$FFFF // Y = $FFFF + cpy.b AbsoluteData // Y -= $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckG + beq Pass83 + Fail83: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail83 + Pass83: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail83 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldy.w #$FFFF // Y = $FFFF + cpy.b AbsoluteData // Y -= $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w CMPResultCheckH + beq Pass84 + Fail84: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail84 + Pass84: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail84 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test CMP (CMP With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +CMPConst: + db "CMP #const (Opcode: $C9)" +CMPAddr: + db "CMP addr (Opcode: $CD)" +CMPLong: + db "CMP long (Opcode: $CF)" +CMPDP: + db "CMP dp (Opcode: $C5)" +CMPDPIndirect: + db "CMP (dp) (Opcode: $D2)" +CMPDPIndirectLong: + db "CMP [dp] (Opcode: $C7)" +CMPAddrX: + db "CMP addr,X (Opcode: $DD)" +CMPLongX: + db "CMP long,X (Opcode: $DF)" +CMPAddrY: + db "CMP addr,Y (Opcode: $D9)" +CMPDPX: + db "CMP dp,X (Opcode: $D5)" +CMPDPIndirectX: + db "CMP (dp,X) (Opcode: $C1)" +CMPDPIndirectY: + db "CMP (dp),Y (Opcode: $D1)" +CMPDPIndirectLongY: + db "CMP [dp],Y (Opcode: $D7)" +CMPSRS: + db "CMP sr,S (Opcode: $C3)" +CMPSRSY: + db "CMP (sr,S),Y (Opcode: $D3)" +CPXConst: + db "CPX #const (Opcode: $E0)" +CPXAddr: + db "CPX addr (Opcode: $EC)" +CPXDP: + db "CPX dp (Opcode: $E4)" +CPYConst: + db "CPY #const (Opcode: $C0)" +CPYAddr: + db "CPY addr (Opcode: $CC)" +CPYDP: + db "CPY dp (Opcode: $C4)" + +CMPResultCheckA: + db $FF +PSRResultCheckA: + db $27 + +CMPResultCheckB: + db $FF +PSRResultCheckB: + db $A5 + +CMPResultCheckC: + dw $FFFF +PSRResultCheckC: + db $07 + +CMPResultCheckD: + dw $FFFF +PSRResultCheckD: + db $85 + +CMPResultCheckE: + db $FF +PSRResultCheckE: + db $37 + +CMPResultCheckF: + db $FF +PSRResultCheckF: + db $B5 + +CMPResultCheckG: + dw $FFFF +PSRResultCheckG: + db $27 + +CMPResultCheckH: + dw $FFFF +PSRResultCheckH: + db $A5 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.png new file mode 100644 index 00000000..8f93ae44 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.sfc new file mode 100644 index 00000000..78236f4d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4dcbeb89 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST CMP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/make.bat new file mode 100644 index 00000000..87acf974 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/CMP/make.bat @@ -0,0 +1 @@ +bass CPUCMP.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.asm new file mode 100644 index 00000000..733d4573 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.asm @@ -0,0 +1,1334 @@ +// SNES 65816 CPU Test DEC (Decrement) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUDEC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(DECA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + dec // A-- + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + dec // A-- + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + dec // A-- + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + dec // A-- + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + dec.w AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + dec.w AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + dec.w AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + dec.w AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + dec.b AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + dec.b AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + dec.b AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + dec.b AbsoluteData // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.w AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.w AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.w AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.w AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.b AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$81 // A = $81 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.b AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w DECResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.b AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8001 // A = $8001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + dec.b AbsoluteData,x // Memory-- + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w DECResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$01 // X = $01 + dex // X-- + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckE + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$81 // X = $81 + dex // X-- + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckF + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0001 // X = $0001 + dex // X-- + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckG + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$8001 // X = $8001 + dex // X-- + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckH + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$01 // Y = $01 + dey // Y-- + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckE + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$81 // Y = $81 + dey // Y-- + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w DECResultCheckF + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0001 // Y = $0001 + dey // Y-- + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckG + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$8001 // Y = $8001 + dey // Y-- + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w DECResultCheckH + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test DEC (Decrement):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +DECA: + db "DEC A (Opcode: $3A)" +DECAddr: + db "DEC addr (Opcode: $CE)" +DECDP: + db "DEC dp (Opcode: $C6)" +DECAddrX: + db "DEC addr,X (Opcode: $DE)" +DECDPX: + db "DEC dp,X (Opcode: $D6)" +DECX: + db "DEX (Opcode: $CA)" +DECY: + db "DEY (Opcode: $88)" + +DECResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +DECResultCheckB: + db $80 +PSRResultCheckB: + db $A4 + +DECResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +DECResultCheckD: + dw $8000 +PSRResultCheckD: + db $84 + +DECResultCheckE: + db $00 +PSRResultCheckE: + db $36 + +DECResultCheckF: + db $80 +PSRResultCheckF: + db $B4 + +DECResultCheckG: + dw $0000 +PSRResultCheckG: + db $26 + +DECResultCheckH: + dw $8000 +PSRResultCheckH: + db $A4 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.png new file mode 100644 index 00000000..b1cc1451 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.sfc new file mode 100644 index 00000000..ebbc4e5c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..95b52e2f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST DEC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/make.bat new file mode 100644 index 00000000..2286bfb3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/DEC/make.bat @@ -0,0 +1 @@ +bass CPUDEC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.asm new file mode 100644 index 00000000..a25da9bb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.asm @@ -0,0 +1,2772 @@ +// SNES 65816 CPU Test EOR (Exclusive-OR With Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUEOR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(EORConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + eor.b #$FF // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + eor.b #$00 // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + eor.w #$FFFF // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + eor.w #$0000 // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.w AbsoluteData // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.w AbsoluteData // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.w AbsoluteData // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.w AbsoluteData // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.l AbsoluteData // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.l AbsoluteData // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.l AbsoluteData // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.l AbsoluteData // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.b AbsoluteData // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$FF // A = $FF + eor.b AbsoluteData // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.b AbsoluteData // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$FFFF // A = $FFFF + eor.b AbsoluteData // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + eor (IndirectData) // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + eor (IndirectData) // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + eor (IndirectData) // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + eor (IndirectData) // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + eor [IndirectData] // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$FF // A = $FF + eor [IndirectData] // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + eor [IndirectData] // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$FFFF // A = $FFFF + eor [IndirectData] // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.w AbsoluteData,x // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.w AbsoluteData,x // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.w AbsoluteData,x // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.w AbsoluteData,x // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORLongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.l AbsoluteData,x // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.l AbsoluteData,x // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.l AbsoluteData,x // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.l AbsoluteData,x // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor AbsoluteData,y // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor AbsoluteData,y // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor AbsoluteData,y // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor AbsoluteData,y // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.b AbsoluteData,x // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor.b AbsoluteData,x // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.b AbsoluteData,x // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor.b AbsoluteData,x // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor (IndirectData,x) // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$FF // A = $FF + eor (IndirectData,x) // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor (IndirectData,x) // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$FFFF // A = $FFFF + eor (IndirectData,x) // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor (IndirectData),y // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor (IndirectData),y // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor (IndirectData),y // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor (IndirectData),y // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor [IndirectData],y // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor [IndirectData],y // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor [IndirectData],y // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor [IndirectData],y // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORSRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + pha // Push A To Stack + lda.b #$FF // A = $FF + eor $01,s // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + pha // Push A To Stack + lda.b #$FF // A = $FF + eor $01,s // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + eor $01,s // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + eor $01,s // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORSRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor ($01,s),y // A ^= $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$FF // A = $FF + eor ($01,s),y // A ^= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w EORResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor ($01,s),y // A ^= $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$FFFF // A = $FFFF + eor ($01,s),y // A ^= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w EORResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test EOR (XOR With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +EORConst: + db "EOR #const (Opcode: $49)" +EORAddr: + db "EOR addr (Opcode: $4D)" +EORLong: + db "EOR long (Opcode: $4F)" +EORDP: + db "EOR dp (Opcode: $45)" +EORDPIndirect: + db "EOR (dp) (Opcode: $52)" +EORDPIndirectLong: + db "EOR [dp] (Opcode: $47)" +EORAddrX: + db "EOR addr,X (Opcode: $5D)" +EORLongX: + db "EOR long,X (Opcode: $5F)" +EORAddrY: + db "EOR addr,Y (Opcode: $59)" +EORDPX: + db "EOR dp,X (Opcode: $55)" +EORDPIndirectX: + db "EOR (dp,X) (Opcode: $41)" +EORDPIndirectY: + db "EOR (dp),Y (Opcode: $51)" +EORDPIndirectLongY: + db "EOR [dp],Y (Opcode: $57)" +EORSRS: + db "EOR sr,S (Opcode: $43)" +EORSRSY: + db "EOR (sr,S),Y (Opcode: $53)" + +EORResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +EORResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +EORResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +EORResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.png new file mode 100644 index 00000000..08b30d4f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.sfc new file mode 100644 index 00000000..1df5d81c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..ad11c9e0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST EOR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/make.bat new file mode 100644 index 00000000..7232f5f0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/EOR/make.bat @@ -0,0 +1 @@ +bass CPUEOR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.asm new file mode 100644 index 00000000..f8785e0c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.asm @@ -0,0 +1,1334 @@ +// SNES 65816 CPU Test INC (Increment) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUINC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(INCA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + inc // A++ + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + inc // A++ + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + inc // A++ + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + inc // A++ + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + inc.w AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + inc.w AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + inc.w AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + inc.w AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + inc.b AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + inc.b AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + inc.b AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + inc.b AbsoluteData // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.w AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.w AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.w AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.w AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.b AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.b AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w INCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.b AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + inc.b AbsoluteData,x // Memory++ + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w INCResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + inx // X++ + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckE + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$7F // X = $7F + inx // X++ + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckF + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + inx // X++ + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckG + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$7FFF // X = $7FFF + inx // X++ + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckH + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + iny // Y++ + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckE + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$7F // Y = $7F + iny // Y++ + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w INCResultCheckF + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + iny // Y++ + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckG + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$7FFF // Y = $7FFF + iny // Y++ + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w INCResultCheckH + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test INC (Increment):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +INCA: + db "INC A (Opcode: $1A)" +INCAddr: + db "INC addr (Opcode: $EE)" +INCDP: + db "INC dp (Opcode: $E6)" +INCAddrX: + db "INC addr,X (Opcode: $FE)" +INCDPX: + db "INC dp,X (Opcode: $F6)" +INCX: + db "INX (Opcode: $E8)" +INCY: + db "INY (Opcode: $C8)" + +INCResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +INCResultCheckB: + db $80 +PSRResultCheckB: + db $A4 + +INCResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +INCResultCheckD: + dw $8000 +PSRResultCheckD: + db $84 + +INCResultCheckE: + db $00 +PSRResultCheckE: + db $36 + +INCResultCheckF: + db $80 +PSRResultCheckF: + db $B4 + +INCResultCheckG: + dw $0000 +PSRResultCheckG: + db $26 + +INCResultCheckH: + dw $8000 +PSRResultCheckH: + db $A4 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.png new file mode 100644 index 00000000..e613d4b5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.sfc new file mode 100644 index 00000000..29bfc61c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b40e6f89 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST INC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/make.bat new file mode 100644 index 00000000..f7ed6459 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/INC/make.bat @@ -0,0 +1 @@ +bass CPUINC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.asm new file mode 100644 index 00000000..97d5ce22 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.asm @@ -0,0 +1,232 @@ +// SNES 65816 CPU Test JMP (Jump) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUJMP.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 20) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JMPAddr, $F9C2, 18) // Load Text To VRAM Lo Bytes + + // Run Test + jmp Pass1 // PC = Address + Fail1: + PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JMPIndirect, $FA02, 18) // Load Text To VRAM Lo Bytes + + // Run Test + ldx.w #Pass2 // X = Pass2 + stx.b AbsoluteData // Store Absolute Data + jmp (AbsoluteData) // PC = Address + Fail2: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JMPIndirectX, $FA42, 18) // Load Text To VRAM Lo Bytes + + // Run Test + ldx.w #Pass3 // X = Pass3 + stx.b AbsoluteData // Store Absolute Data + ldx.w #$0000 // X = $0000 + jmp (AbsoluteData,x) // PC = Address + Fail3: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JMPLong, $FA82, 18) // Load Text To VRAM Lo Bytes + + // Run Test + jml Pass4 // PC = Address + Fail4: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JMPIndirectLong, $FAC2, 18) // Load Text To VRAM Lo Bytes + + // Run Test + ldx.w #Pass5 // X = Pass5 + stx.b IndirectData // Store Indirect Data + jmp [IndirectData] // PC = Address + Fail5: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JSRAddr, $FB02, 18) // Load Text To VRAM Lo Bytes + + // Run Test + jsr JSRA // Stack = PC, PC = Address + bra Pass6 // Branch After Return From Subroutine + Fail6: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JSRIndirectX, $FB42, 18) // Load Text To VRAM Lo Bytes + + // Run Test + ldx.w #JSRB // X = JSRB + stx.b AbsoluteData // Store Absolute Data + ldx.w #$0000 // X = $0000 + jsr (AbsoluteData,x) // Stack = PC, PC = Address + bra Pass7 // Branch After Return From Subroutine + Fail7: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(JSRLong, $FB82, 18) // Load Text To VRAM Lo Bytes + + // Run Test + jsl JSRC // Stack = PC, PC = Address + bra Pass8 // Branch After Return From Subroutine + Fail8: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +JSRA: + rts // Return From Subroutine +JSRB: + rts // Return From Subroutine +JSRC: + rtl // Return From Subroutine + +Title: + db "CPU Test JMP (Jump):" + +PageBreak: + db "------------------------------" + +Key: + db "Syntax | Opcode | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +JMPAddr: + db "JMP addr $4C" +JMPIndirect: + db "JMP (addr) $6C" +JMPIndirectX: + db "JMP (addr,X) $7C" +JMPLong: + db "JMP/JML long $5C" +JMPIndirectLong: + db "JMP/JML [addr] $DC" +JSRAddr: + db "JSR addr $20" +JSRIndirectX: + db "JSR (addr,X) $FC" +JSRLong: + db "JSR/JSL long $22" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.png new file mode 100644 index 00000000..bdb95f34 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.sfc new file mode 100644 index 00000000..98bf2620 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..47057ab9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST JMP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/make.bat new file mode 100644 index 00000000..a4d0a294 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/JMP/make.bat @@ -0,0 +1 @@ +bass CPUJMP.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.asm new file mode 100644 index 00000000..25c73f21 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.asm @@ -0,0 +1,4362 @@ +// SNES 65816 CPU Test LDR (Load Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPULDR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(LDAConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDAAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.w AbsoluteData // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.w AbsoluteData // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w AbsoluteData // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.w AbsoluteData // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDALong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.l AbsoluteData // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.l AbsoluteData // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.l AbsoluteData // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.l AbsoluteData // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b AbsoluteData // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + lda.b AbsoluteData // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.b AbsoluteData // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + lda.b AbsoluteData // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda (IndirectData) // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda (IndirectData) // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda (IndirectData) // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda (IndirectData) // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda [IndirectData] // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda [IndirectData] // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda [IndirectData] // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda [IndirectData] // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDAAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w AbsoluteData,x // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w AbsoluteData,x // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w AbsoluteData,x // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w AbsoluteData,x // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDALongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.l AbsoluteData,x // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.l AbsoluteData,x // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.l AbsoluteData,x // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.l AbsoluteData,x // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDAAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda AbsoluteData,y // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda AbsoluteData,y // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda AbsoluteData,y // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda AbsoluteData,y // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b AbsoluteData,x // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b AbsoluteData,x // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b AbsoluteData,x // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b AbsoluteData,x // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda (IndirectData,x) // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda (IndirectData,x) // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda (IndirectData,x) // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda (IndirectData,x) // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda (IndirectData),y // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda (IndirectData),y // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda (IndirectData),y // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda (IndirectData),y // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDADPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda [IndirectData],y // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda [IndirectData],y // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda [IndirectData],y // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda [IndirectData],y // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDASRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + pha // Push A To Stack + lda $01,s // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + pha // Push A To Stack + lda $01,s // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + pha // Push A To Stack + lda $01,s // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + pha // Push A To Stack + lda $01,s // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDASRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda ($01,s),y // A = $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda ($01,s),y // A = $FF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda ($01,s),y // A = $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda ($01,s),y // A = $FFFF + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDXConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass61 + Fail61: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail61 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass62 + Fail62: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail62 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass63 + Fail63: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail63 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass64 + Fail64: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail64 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDXAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldx.w AbsoluteData // X = $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass65 + Fail65: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail65 + Pass65: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail65 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldx.w AbsoluteData // X = $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass66 + Fail66: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail66 + Pass66: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail66 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldx.w AbsoluteData // X = $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass67 + Fail67: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail67 + Pass67: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail67 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldx.w AbsoluteData // X = $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass68 + Fail68: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail68 + Pass68: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail68 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDXDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldx.b AbsoluteData // X = $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass69 + Fail69: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail69 + Pass69: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail69 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldx.b AbsoluteData // X = $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass70 + Fail70: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail70 + Pass70: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail70 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldx.b AbsoluteData // X = $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass71 + Fail71: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail71 + Pass71: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail71 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldx.b AbsoluteData // X = $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass72 + Fail72: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail72 + Pass72: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail72 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDXAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldy.b #0 // Y = 0 + ldx AbsoluteData,y // X = $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass73 + Fail73: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail73 + Pass73: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail73 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldy.b #0 // Y = 0 + ldx AbsoluteData,y // X = $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass74 + Fail74: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail74 + Pass74: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail74 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + ldx AbsoluteData,y // X = $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass75 + Fail75: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail75 + Pass75: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail75 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + ldx AbsoluteData,y // X = $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass76 + Fail76: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail76 + Pass76: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail76 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDXDPY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + stx.b AbsoluteData // Store Absolute Data + ldy.b #0 // Y = 0 + ldx.b AbsoluteData,y // X = $00 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass77 + Fail77: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail77 + Pass77: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail77 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + stx.b AbsoluteData // Store Absolute Data + ldy.b #0 // Y = 0 + ldx.b AbsoluteData,y // X = $FF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass78 + Fail78: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail78 + Pass78: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail78 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + stx.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + ldx.b AbsoluteData,y // X = $0000 + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass79 + Fail79: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail79 + Pass79: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail79 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + stx.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + ldx.b AbsoluteData,y // X = $FFFF + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass80 + Fail80: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail80 + Pass80: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail80 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDYConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass81 + Fail81: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail81 + Pass81: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail81 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass82 + Fail82: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail82 + Pass82: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail82 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass83 + Fail83: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail83 + Pass83: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail83 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass84 + Fail84: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail84 + Pass84: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail84 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDYAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldy.w AbsoluteData // Y = $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass85 + Fail85: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail85 + Pass85: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail85 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldy.w AbsoluteData // Y = $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass86 + Fail86: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail86 + Pass86: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail86 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldy.w AbsoluteData // Y = $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass87 + Fail87: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail87 + Pass87: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail87 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldy.w AbsoluteData // Y = $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass88 + Fail88: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail88 + Pass88: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail88 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDYDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldy.b AbsoluteData // Y = $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass89 + Fail89: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail89 + Pass89: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail89 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldy.b AbsoluteData // Y = $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass90 + Fail90: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail90 + Pass90: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail90 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldy.b AbsoluteData // Y = $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass91 + Fail91: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail91 + Pass91: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail91 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldy.b AbsoluteData // Y = $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass92 + Fail92: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail92 + Pass92: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail92 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDYAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldx.b #0 // X = 0 + ldy AbsoluteData,x // Y = $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass93 + Fail93: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail93 + Pass93: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail93 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldx.b #0 // X = 0 + ldy AbsoluteData,x // Y = $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass94 + Fail94: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail94 + Pass94: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail94 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ldy AbsoluteData,x // Y = $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass95 + Fail95: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail95 + Pass95: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail95 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ldy AbsoluteData,x // Y = $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass96 + Fail96: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail96 + Pass96: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail96 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LDYDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + sty.b AbsoluteData // Store Absolute Data + ldx.b #0 // X = 0 + ldy.b AbsoluteData,x // Y = $00 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckE + beq Pass97 + Fail97: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail97 + Pass97: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail97 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + sty.b AbsoluteData // Store Absolute Data + ldx.b #0 // X = 0 + ldy.b AbsoluteData,x // Y = $FF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LDRResultCheckF + beq Pass98 + Fail98: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail98 + Pass98: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail98 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + sty.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ldy.b AbsoluteData,x // Y = $0000 + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckG + beq Pass99 + Fail99: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail99 + Pass99: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail99 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sty.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ldy.b AbsoluteData,x // Y = $FFFF + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LDRResultCheckH + beq Pass100 + Fail100: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail100 + Pass100: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail100 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test LDR (Load Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +LDAConst: + db "LDA #const (Opcode: $A9)" +LDAAddr: + db "LDA addr (Opcode: $AD)" +LDALong: + db "LDA long (Opcode: $AF)" +LDADP: + db "LDA dp (Opcode: $A5)" +LDADPIndirect: + db "LDA (dp) (Opcode: $B2)" +LDADPIndirectLong: + db "LDA [dp] (Opcode: $A7)" +LDAAddrX: + db "LDA addr,X (Opcode: $BD)" +LDALongX: + db "LDA long,X (Opcode: $BF)" +LDAAddrY: + db "LDA addr,Y (Opcode: $B9)" +LDADPX: + db "LDA dp,X (Opcode: $B5)" +LDADPIndirectX: + db "LDA (dp,X) (Opcode: $A1)" +LDADPIndirectY: + db "LDA (dp),Y (Opcode: $B1)" +LDADPIndirectLongY: + db "LDA [dp],Y (Opcode: $B7)" +LDASRS: + db "LDA sr,S (Opcode: $A3)" +LDASRSY: + db "LDA (sr,S),Y (Opcode: $B3)" +LDXConst: + db "LDX #const (Opcode: $A2)" +LDXAddr: + db "LDX addr (Opcode: $AE)" +LDXDP: + db "LDX dp (Opcode: $A6)" +LDXAddrY: + db "LDX addr,Y (Opcode: $BE)" +LDXDPY: + db "LDX dp,Y (Opcode: $B6)" +LDYConst: + db "LDY #const (Opcode: $A0)" +LDYAddr: + db "LDY addr (Opcode: $AC)" +LDYDP: + db "LDY dp (Opcode: $A4)" +LDYAddrX: + db "LDY addr,X (Opcode: $BC)" +LDYDPX: + db "LDY dp,X (Opcode: $B4)" + +LDRResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +LDRResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +LDRResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +LDRResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +LDRResultCheckE: + db $00 +PSRResultCheckE: + db $36 + +LDRResultCheckF: + db $FF +PSRResultCheckF: + db $B4 + +LDRResultCheckG: + dw $0000 +PSRResultCheckG: + db $26 + +LDRResultCheckH: + dw $FFFF +PSRResultCheckH: + db $A4 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.png new file mode 100644 index 00000000..095ea853 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.sfc new file mode 100644 index 00000000..2e661a0c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a738d5c0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST LDR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/make.bat new file mode 100644 index 00000000..fd69255f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LDR/make.bat @@ -0,0 +1 @@ +bass CPULDR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.asm new file mode 100644 index 00000000..7dd6f44e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.asm @@ -0,0 +1,996 @@ +// SNES 65816 CPU Test LSR (Logical Shift Right) demo by krom (Peter Lemon): +arch snes.cpu +output "CPULSR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(LSRA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + lsr // A >>= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LSRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FE // A = $FE + lsr // A >>= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w LSRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + lsr // A >>= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + lsr // A >>= 1 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w LSRResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LSRAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + lsr.w AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + lsr.w AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + lsr.w AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + lsr.w AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LSRDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + lsr.b AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + lsr.b AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + lsr.b AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + lsr.b AbsoluteData // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LSRAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.w AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.w AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.w AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.w AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(LSRDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.b AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.b AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w LSRResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.b AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lsr.b AbsoluteData,x // Memory >>= 1 + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w LSRResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test LSR (Shift Right):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +LSRA: + db "LSR A (Opcode: $4A)" +LSRAddr: + db "LSR addr (Opcode: $4E)" +LSRDP: + db "LSR dp (Opcode: $46)" +LSRAddrX: + db "LSR addr,X (Opcode: $5E)" +LSRDPX: + db "LSR dp,X (Opcode: $56)" + +LSRResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +LSRResultCheckB: + db $7F +PSRResultCheckB: + db $24 + +LSRResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +LSRResultCheckD: + dw $7FFF +PSRResultCheckD: + db $04 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.png new file mode 100644 index 00000000..ebd60cfd Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.sfc new file mode 100644 index 00000000..4ab535e7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4a6ea379 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST LSR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/make.bat new file mode 100644 index 00000000..57e55a5f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/LSR/make.bat @@ -0,0 +1 @@ +bass CPULSR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.asm new file mode 100644 index 00000000..77148fac --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.asm @@ -0,0 +1,399 @@ +// SNES 65816 CPU Test MOV (Block Move) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUMOV.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintData(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #$0000 // X = Number Of Hex Characters To Print + + {#}LoopHEX: + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + inx // X++ + cpx.w #{SIZE} // Compare X To SIZE + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultDataA: + dw 0 // Result Data Word +ResultDataX: + dw 0 // Result Data Word +ResultDataY: + dw 0 // Result Data Word +ResultDataMVN: + fill 64 // Result Data (64 Byte Block) +ResultDataMVP: + fill 64 // Result Data (64 Byte Block) + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 26) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(MOVMVN, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + lda.w #$003F // A = Length (64 Bytes) + ldx.w #MOVSRCData // X = Source + ldy.w #ResultDataMVN // Y = Destination + mvn $00=$00 // Block Move 64 Bytes + + // Store Result Data + sta.b ResultDataA // Store Result To Memory + stx.b ResultDataX // Store Result To Memory + sty.b ResultDataY // Store Result To Memory + sep #$20 // Set 8-Bit Accumulator + + // Print Result + PrintValue(ResultDataA, $FA24, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataA // X = Result Data + cpx.w MOVResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + // Print Result + PrintValue(ResultDataX, $FA64, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataX // X = Result Data + cpx.w MOVResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + // Print Result + PrintValue(ResultDataY, $FAA4, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataY // X = Result Data + cpx.w MOVResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + WaitNMI() // Wait For VSync + + // Print Result + PrintData(ResultDataMVN, $FB02, 8) // Print Result Data + PrintData(ResultDataMVN+8, $FB42, 8) // Print Result Data + PrintData(ResultDataMVN+16, $FB82, 8) // Print Result Data + PrintData(ResultDataMVN+24, $FBC2, 8) // Print Result Data + PrintData(ResultDataMVN+32, $FC02, 8) // Print Result Data + PrintData(ResultDataMVN+40, $FC42, 8) // Print Result Data + PrintData(ResultDataMVN+48, $FC82, 8) // Print Result Data + PrintData(ResultDataMVN+56, $FCC2, 8) // Print Result Data + + // Check Result Data + ldx.w #$0000 // X = Result Data Index + LoopResult4: + lda.b ResultDataMVN,x // A = Result Data + cmp.w MOVSRCData,x + bne Fail4 + inx // X++ + cpx.w #$0040 // Compare Result Data Index to 64 + bne LoopResult4 // IF (Result Data Index != 64) Loop Result + beq Pass4 + Fail4: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $180, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(MOVMVP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + lda.w #$003F // A = Length (64 Bytes) + ldx.w #MOVSRCData+$3F // X = Source + ldy.w #ResultDataMVP+$3F // Y = Destination + mvp $00=$00 // Block Move 64 Bytes + + // Store Result Data + sta.b ResultDataA // Store Result To Memory + stx.b ResultDataX // Store Result To Memory + sty.b ResultDataY // Store Result To Memory + sep #$20 // Set 8-Bit Accumulator + + // Print Result + PrintValue(ResultDataA, $FA24, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataA // X = Result Data + cpx.w MOVResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + // Print Result + PrintValue(ResultDataX, $FA64, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataX // X = Result Data + cpx.w MOVResultCheckE + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + // Print Result + PrintValue(ResultDataY, $FAA4, 2) // Print Result Data + + // Check Result Data + ldx.b ResultDataY // X = Result Data + cpx.w MOVResultCheckF + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + WaitNMI() // Wait For VSync + + // Print Result + PrintData(ResultDataMVP, $FB02, 8) // Print Result Data + PrintData(ResultDataMVP+8, $FB42, 8) // Print Result Data + PrintData(ResultDataMVP+16, $FB82, 8) // Print Result Data + PrintData(ResultDataMVP+24, $FBC2, 8) // Print Result Data + PrintData(ResultDataMVP+32, $FC02, 8) // Print Result Data + PrintData(ResultDataMVP+40, $FC42, 8) // Print Result Data + PrintData(ResultDataMVP+48, $FC82, 8) // Print Result Data + PrintData(ResultDataMVP+56, $FCC2, 8) // Print Result Data + + // Check Result Data + ldx.w #$0000 // X = Result Data Index + LoopResult8: + lda.b ResultDataMVP,x // A = Result Data + cmp.w MOVSRCData,x + bne Fail8 + inx // X++ + cpx.w #$0040 // Compare Result Data Index to 64 + bne LoopResult8 // IF (Result Data Index != 64) Loop Result + beq Pass8 + Fail8: + PrintText(Fail, $FCF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + PrintText(Pass, $FCF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test MOV (Block Move):" + +PageBreak: + db "------------------------------" + +Key: + db "Result Block | AXY | Test |" + +Fail: + db "FAIL" +Pass: + db "PASS" + +MOVMVN: + db "MVN src,dest (Opcode: $54)" +MOVMVP: + db "MVP src,dest (Opcode: $44)" + +MOVResultCheckA: + dw $FFFF +MOVResultCheckB: + dw $8B04 +MOVResultCheckC: + dw $0046 +MOVResultCheckD: + dw $0086 +MOVResultCheckE: + dw $8AC3 +MOVResultCheckF: + dw $0045 + +MOVSRCData: + db $01,$02,$03,$04,$05,$06,$07,$08 + db $09,$10,$11,$12,$13,$14,$15,$16 + db $17,$18,$19,$20,$21,$22,$23,$24 + db $25,$26,$27,$28,$29,$30,$31,$32 + db $33,$34,$35,$36,$37,$38,$39,$40 + db $41,$42,$43,$44,$45,$46,$47,$48 + db $49,$50,$51,$52,$53,$54,$55,$56 + db $57,$58,$59,$60,$61,$62,$63,$64 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.png new file mode 100644 index 00000000..a8375c19 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.sfc new file mode 100644 index 00000000..7e1c6451 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e926d095 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST MOV " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/make.bat new file mode 100644 index 00000000..51281aa8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MOV/make.bat @@ -0,0 +1 @@ +bass CPUMOV.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.asm new file mode 100644 index 00000000..e2056730 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.asm @@ -0,0 +1,346 @@ +// SNES 65816 CPU Test MSC (Miscellaneous) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUMSC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte + +seek($8000); Start: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.b #$24 // Compare A To $24 + bne Init // IF (A != $24) Init + jmp STPCheck // IF (A = $24) STP Check + +Init: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 29) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Reset Info Text + PrintText(ResetInfo, $F902, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(NOPMSC, $F9C2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $F9E4) // Print Processor Status Flag Data + + // Run Test + nop // No Operation + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass1 + PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + Pass1: + PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(WDMMSC, $FA02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Run Test + wdm #$00 // No Operation + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass2 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + Pass2: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(BRKMSC, $FA42, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Run Test + brk #$00 // Software Interrupt + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass3 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + Pass3: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(COPMSC, $FA82, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Run Test + cop #$00 // Software Interrupt + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass4 + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + Pass4: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(WAIMSC, $FAC2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Run Test + lda.b #$80 // Set VBlank Interrupt + sta.w REG_NMITIMEN // Store Interrupt Enable + wai // Wait for Interrupt + stz.w REG_NMITIMEN // Reset VBlank Interrupt + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass5 + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + Pass5: + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(STPMSC, $FB02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Run Test + stp // Stop the Processor (Reset) + + STPCheck: + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + sep #$20 // Set 8-Bit A + rep #$10 // Set 16-Bit X/Y + + // Setup Video + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass6 + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + Pass6: + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +RTIBreak: + rti // Return From Interrupt + +Title: + db "CPU Test MSC (Miscellaneous):" + +PageBreak: + db "------------------------------" + +ResetInfo: + db "** Please Reset To PASS STP **" + +Key: + db "Type | Opcode | NVZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +NOPMSC: + db "NOP $EA" +WDMMSC: + db "WDM $42" +BRKMSC: + db "BRK $00" +COPMSC: + db "COP $02" +WAIMSC: + db "WAI $CB" +STPMSC: + db "STP $DB" + +PSRResultCheck: + db $24 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.png new file mode 100644 index 00000000..2d0b612c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.sfc new file mode 100644 index 00000000..450d157b Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..14cd5a58 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST MSC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw RTIBreak // COP VECTOR (COP Opcode) +dw RTIBreak // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw RTIBreak // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/make.bat new file mode 100644 index 00000000..e3a50086 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/MSC/make.bat @@ -0,0 +1 @@ +bass CPUMSC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.asm new file mode 100644 index 00000000..756a88b1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.asm @@ -0,0 +1,2772 @@ +// SNES 65816 CPU Test ORA (OR With Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUORA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ORAConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + ora.b #$00 // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$0F // A = $0F + ora.b #$F0 // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + ora.w #$0000 // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$00FF // A = $00FF + ora.w #$FF00 // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + ora.w AbsoluteData // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + lda.b #$0F // A = $0F + ora.w AbsoluteData // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + ora.w AbsoluteData // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + lda.w #$00FF // A = $00FF + ora.w AbsoluteData // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORALong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + ora.l AbsoluteData // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + lda.b #$0F // A = $0F + ora.l AbsoluteData // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + ora.l AbsoluteData // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + lda.w #$00FF // A = $00FF + ora.l AbsoluteData // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + lda.b #$00 // A = $00 + ora.b AbsoluteData // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + lda.b #$0F // A = $0F + ora.b AbsoluteData // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$0000 // A = $0000 + ora.b AbsoluteData // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + lda.w #$00FF // A = $00FF + ora.b AbsoluteData // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$00 // A = $00 + ora (IndirectData) // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$0F // A = $0F + ora (IndirectData) // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$0000 // A = $0000 + ora (IndirectData) // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$00FF // A = $00FF + ora (IndirectData) // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$00 // A = $00 + ora [IndirectData] // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$0F // A = $0F + ora [IndirectData] // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$0000 // A = $0000 + ora [IndirectData] // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$00FF // A = $00FF + ora [IndirectData] // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + ora.w AbsoluteData,x // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$0F // A = $0F + ora.w AbsoluteData,x // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + ora.w AbsoluteData,x // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$00FF // A = $00FF + ora.w AbsoluteData,x // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORALongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + ora.l AbsoluteData,x // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$0F // A = $0F + ora.l AbsoluteData,x // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + ora.l AbsoluteData,x // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$00FF // A = $00FF + ora.l AbsoluteData,x // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$00 // A = $00 + ora AbsoluteData,y // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$0F // A = $0F + ora AbsoluteData,y // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$0000 // A = $0000 + ora AbsoluteData,y // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$00FF // A = $00FF + ora AbsoluteData,y // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + ora.b AbsoluteData,x // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$0F // A = $0F + ora.b AbsoluteData,x // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + ora.b AbsoluteData,x // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$00FF // A = $00FF + ora.b AbsoluteData,x // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$00 // A = $00 + ora (IndirectData,x) // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$0F // A = $0F + ora (IndirectData,x) // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$0000 // A = $0000 + ora (IndirectData,x) // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$00FF // A = $00FF + ora (IndirectData,x) // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$00 // A = $00 + ora (IndirectData),y // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$0F // A = $0F + ora (IndirectData),y // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$0000 // A = $0000 + ora (IndirectData),y // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$00FF // A = $00FF + ora (IndirectData),y // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$00 // A = $00 + ora [IndirectData],y // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$0F // A = $0F + ora [IndirectData],y // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$0000 // A = $0000 + ora [IndirectData],y // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$00FF // A = $00FF + ora [IndirectData],y // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORASRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + pha // Push A To Stack + lda.b #$00 // A = $00 + ora $01,s // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + pha // Push A To Stack + lda.b #$0F // A = $0F + ora $01,s // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + pha // Push A To Stack + lda.w #$0000 // A = $0000 + ora $01,s // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + pha // Push A To Stack + lda.w #$00FF // A = $00FF + ora $01,s // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORASRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$00 // A = $00 + ora ($01,s),y // A |= $00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$F0 // A = $F0 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$0F // A = $0F + ora ($01,s),y // A |= $F0 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ORAResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$0000 // A = $0000 + ora ($01,s),y // A |= $0000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$00FF // A = $00FF + ora ($01,s),y // A |= $FF00 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ORAResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test ORA (OR With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +ORAConst: + db "ORA #const (Opcode: $09)" +ORAAddr: + db "ORA addr (Opcode: $0D)" +ORALong: + db "ORA long (Opcode: $0F)" +ORADP: + db "ORA dp (Opcode: $05)" +ORADPIndirect: + db "ORA (dp) (Opcode: $12)" +ORADPIndirectLong: + db "ORA [dp] (Opcode: $07)" +ORAAddrX: + db "ORA addr,X (Opcode: $1D)" +ORALongX: + db "ORA long,X (Opcode: $1F)" +ORAAddrY: + db "ORA addr,Y (Opcode: $19)" +ORADPX: + db "ORA dp,X (Opcode: $15)" +ORADPIndirectX: + db "ORA (dp,X) (Opcode: $01)" +ORADPIndirectY: + db "ORA (dp),Y (Opcode: $11)" +ORADPIndirectLongY: + db "ORA [dp],Y (Opcode: $17)" +ORASRS: + db "ORA sr,S (Opcode: $03)" +ORASRSY: + db "ORA (sr,S),Y (Opcode: $13)" + +ORAResultCheckA: + db $00 +PSRResultCheckA: + db $26 + +ORAResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +ORAResultCheckC: + dw $0000 +PSRResultCheckC: + db $06 + +ORAResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.png new file mode 100644 index 00000000..0ce199ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.sfc new file mode 100644 index 00000000..213402b4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..425648ab --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST ORA " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/make.bat new file mode 100644 index 00000000..2bacf2eb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ORA/make.bat @@ -0,0 +1 @@ +bass CPUORA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.asm new file mode 100644 index 00000000..c124f3f1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.asm @@ -0,0 +1,2014 @@ +// SNES 65816 CPU Test PHL (Push Pull) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUPHL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(PEAPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + pea $DEAD // Stack = $DEAD + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + pea $BEEF // Stack = $BEEF + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PEIPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Load Test Data + ldx.w #$DEAD // X = $DEAD + stx.b AbsoluteData // Store Absolute Data + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + pei (AbsoluteData) // Stack = $DEAD + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckC + bne Fail3 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Load Test Data + ldx.w #$BEEF // X = $BEEF + stx.b AbsoluteData // Store Absolute Data + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + pei (AbsoluteData) // Stack = $BEEF + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckD + bne Fail4 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PERPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + per AbsoluteData // Stack = PC Relative Indirect Address + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckE + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckE + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + per AbsoluteData // Stack = PC Relative Indirect Address + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckF + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckF + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHAPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + + // Run Test + lda.b #$7F // A = $7F + pha // Stack = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckG + beq Pass7 + Fail7: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckG + bne Fail7 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + + // Run Test + lda.w #$7FFF // A = $7FFF + pha // Stack = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckH + beq Pass8 + Fail8: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckH + bne Fail8 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHBPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + phb // Stack = Bank Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckI + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckI + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + phb // Stack = Bank Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckJ + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckJ + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHDPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + phd // Stack = Direct Page Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckK + beq Pass11 + Fail11: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckK + bne Fail11 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + phd // Stack = Direct Page Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckL + beq Pass12 + Fail12: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckL + bne Fail12 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHKPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + phk // Stack = Program Bank Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckM + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckM + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + phk // Stack = Program Bank Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckN + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckN + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHPPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + php // Stack = Push Processor Status Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckO + beq Pass15 + Fail15: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckO + bne Fail15 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + php // Stack = Push Processor Status Register + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckP + beq Pass16 + Fail16: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckP + bne Fail16 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHXPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldx.b #$7F // X = $7F + phx // Stack = X + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckQ + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckQ + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldx.w #$7FFF // X = $7FFF + phx // Stack = X + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckR + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckR + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PHYPSH, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + ldy.b #$7F // Y = $7F + phy // Stack = Y + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + pla // Pull A Register From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PSHResultCheckS + beq Pass19 + Fail19: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckS + bne Fail19 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + ldy.w #$7FFF // Y = $7FFF + phy // Stack = Y + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + plx // Pull X Register From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PSHResultCheckT + beq Pass20 + Fail20: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSHPSRResultCheckT + bne Fail20 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLAPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$00 // A = $00 + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + + // Run Test + pla // A = Stack + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$FF // A = $FF + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + + // Run Test + pla // A = Stack + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$0000 // X = $0000 + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + + // Run Test + pla // A = Stack + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckC + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckC + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$FFFF // X = $FFFF + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + + // Run Test + pla // A = Stack + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckD + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckD + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLBPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + phb // Push Data Bank Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + plb // Data Bank Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phb // Push Data Bank Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull A From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckE + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckE + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Store Data + phb // Push Data Bank Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + plb // Data Bank Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phb // Push Data Bank Register To Stack + pla // Pull A From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckF + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckF + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLDPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + phd // Push Direct Page Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + pld // Direct Page Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phd // Push Data Bank Register To Stack + rep #$10 // Set 16-Bit X/Y + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckG + beq Pass27 + Fail27: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckG + bne Fail27 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Store Data + phd // Push Direct Page Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + pld // Direct Page Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phd // Push Data Bank Register To Stack + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckH + beq Pass28 + Fail28: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckH + bne Fail28 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLPPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + php // Push Processor Status Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + + // Run Test + plp // Processor Status Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull A From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckI + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckI + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Store Data + php // Push Processor Status Register To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + + // Run Test + plp // Processor Status Register = Stack + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + php // Push Processor Status Register To Stack + pla // Pull A From Stack + sta.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckJ + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckJ + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLXPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$00 // A = $00 + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + plx // X = Stack + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckK + beq Pass31 + Fail31: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckK + bne Fail31 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$FF // A = $FF + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + plx // X = Stack + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckL + beq Pass32 + Fail32: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckL + bne Fail32 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$0000 // X = $0000 + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + plx // X = Stack + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckM + beq Pass33 + Fail33: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckM + bne Fail33 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$FFFF // X = $FFFF + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + plx // X = Stack + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckN + beq Pass34 + Fail34: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckN + bne Fail34 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(PLYPUL, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$00 // A = $00 + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + ply // Y = Stack + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckO + beq Pass35 + Fail35: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckO + bne Fail35 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Store Data + lda.b #$FF // A = $FF + pha // Push A To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + sep #$10 // Set 8-Bit X/Y + + // Run Test + ply // Y = Stack + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w PULResultCheckP + beq Pass36 + Fail36: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckP + bne Fail36 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$0000 // X = $0000 + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + ply // Y = Stack + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckQ + beq Pass37 + Fail37: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckQ + bne Fail37 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Store Data + ldx.w #$FFFF // X = $FFFF + phx // Push X To Stack + + // Setup Flags + rep #$C3 // Reset NVZC Flags + rep #$10 // Set 16-Bit X/Y + + // Run Test + ply // Y = Stack + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w PULResultCheckR + beq Pass38 + Fail38: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PULPSRResultCheckR + bne Fail38 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test PHL (Push Pull):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +PEAPSH: + db "PEA addr (Opcode: $F4)" +PEIPSH: + db "PEI (dp) (Opcode: $D4)" +PERPSH: + db "PER label (Opcode: $62)" +PHAPSH: + db "PHA (Opcode: $48)" +PHBPSH: + db "PHB (Opcode: $8B)" +PHDPSH: + db "PHD (Opcode: $0B)" +PHKPSH: + db "PHK (Opcode: $4B)" +PHPPSH: + db "PHP (Opcode: $08)" +PHXPSH: + db "PHX (Opcode: $DA)" +PHYPSH: + db "PHY (Opcode: $5A)" +PLAPUL: + db "PLA (Opcode: $68)" +PLBPUL: + db "PLB (Opcode: $AB)" +PLDPUL: + db "PLD (Opcode: $2B)" +PLPPUL: + db "PLP (Opcode: $28)" +PLXPUL: + db "PLX (Opcode: $FA)" +PLYPUL: + db "PLY (Opcode: $7A)" + +PSHResultCheckA: + dw $DEAD +PSHPSRResultCheckA: + db $34 + +PSHResultCheckB: + dw $BEEF +PSHPSRResultCheckB: + db $04 + +PSHResultCheckC: + dw $DEAD +PSHPSRResultCheckC: + db $34 + +PSHResultCheckD: + dw $BEEF +PSHPSRResultCheckD: + db $04 + +PSHResultCheckE: + dw $86EF +PSHPSRResultCheckE: + db $34 + +PSHResultCheckF: + dw $87C2 +PSHPSRResultCheckF: + db $04 + +PSHResultCheckG: + db $7F +PSHPSRResultCheckG: + db $24 + +PSHResultCheckH: + dw $7FFF +PSHPSRResultCheckH: + db $04 + +PSHResultCheckI: + db $00 +PSHPSRResultCheckI: + db $34 + +PSHResultCheckJ: + db $00 +PSHPSRResultCheckJ: + db $04 + +PSHResultCheckK: + dw $0000 +PSHPSRResultCheckK: + db $34 + +PSHResultCheckL: + dw $0000 +PSHPSRResultCheckL: + db $04 + +PSHResultCheckM: + db $00 +PSHPSRResultCheckM: + db $34 + +PSHResultCheckN: + db $00 +PSHPSRResultCheckN: + db $04 + +PSHResultCheckO: + db $34 +PSHPSRResultCheckO: + db $34 + +PSHResultCheckP: + db $04 +PSHPSRResultCheckP: + db $04 + +PSHResultCheckQ: + db $7F +PSHPSRResultCheckQ: + db $34 + +PSHResultCheckR: + dw $7FFF +PSHPSRResultCheckR: + db $24 + +PSHResultCheckS: + db $7F +PSHPSRResultCheckS: + db $34 + +PSHResultCheckT: + dw $7FFF +PSHPSRResultCheckT: + db $24 + +PULResultCheckA: + db $00 +PULPSRResultCheckA: + db $26 + +PULResultCheckB: + db $FF +PULPSRResultCheckB: + db $A4 + +PULResultCheckC: + dw $0000 +PULPSRResultCheckC: + db $06 + +PULResultCheckD: + dw $FFFF +PULPSRResultCheckD: + db $84 + +PULResultCheckE: + db $00 +PULPSRResultCheckE: + db $36 + +PULResultCheckF: + db $00 +PULPSRResultCheckF: + db $06 + +PULResultCheckG: + dw $0000 +PULPSRResultCheckG: + db $36 + +PULResultCheckH: + dw $0000 +PULPSRResultCheckH: + db $06 + +PULResultCheckI: + db $65 +PULPSRResultCheckI: + db $67 + +PULResultCheckJ: + db $65 +PULPSRResultCheckJ: + db $67 + +PULResultCheckK: + db $00 +PULPSRResultCheckK: + db $36 + +PULResultCheckL: + db $FF +PULPSRResultCheckL: + db $B4 + +PULResultCheckM: + dw $0000 +PULPSRResultCheckM: + db $26 + +PULResultCheckN: + dw $FFFF +PULPSRResultCheckN: + db $A4 + +PULResultCheckO: + db $00 +PULPSRResultCheckO: + db $36 + +PULResultCheckP: + db $FF +PULPSRResultCheckP: + db $B4 + +PULResultCheckQ: + dw $0000 +PULPSRResultCheckQ: + db $26 + +PULResultCheckR: + dw $FFFF +PULPSRResultCheckR: + db $A4 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.png new file mode 100644 index 00000000..2afc56c1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.sfc new file mode 100644 index 00000000..58d6c11a Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..6917346e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST PHL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/make.bat new file mode 100644 index 00000000..b16eb790 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PHL/make.bat @@ -0,0 +1 @@ +bass CPUPHL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.asm new file mode 100644 index 00000000..9428604e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.asm @@ -0,0 +1,431 @@ +// SNES 65816 CPU Test PSR (PSR Flags) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUPSR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00001000 // A = Decimal Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000100 // A = Interrupt Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(CLCPSR, $F9C2, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$CF // Set NVDIZC Flags + + // Run Test + clc // Clear Carry Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + cld // Clear Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $F9E0) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(CLDPSR, $FA02, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$CF // Set NVDIZC Flags + + // Run Test + cld // Clear Decimal Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA20) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(CLIPSR, $FA42, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$CF // Set NVDIZC Flags + + // Run Test + cli // Clear Interrupt Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + cld // Clear Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA60) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(CLVPSR, $FA82, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$CF // Set NVDIZC Flags + + // Run Test + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + cld // Clear Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAA0) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(REPPSR, $FAC2, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$CF // Set NVDIZC Flags + + // Run Test + rep #$CF // Reset NVDIZC Flags + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FAE0) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + beq Pass5 + Fail5: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(SECPSR, $FB02, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$CF // Reset NVDIZC Flags + + // Run Test + sec // Set Carry Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FB20) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + beq Pass6 + Fail6: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(SEDPSR, $FB42, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$CF // Reset NVDIZC Flags + + // Run Test + sed // Set Decimal Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + cld // Clear Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FB60) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + beq Pass7 + Fail7: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(SEIPSR, $FB82, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$CF // Reset NVDIZC Flags + + // Run Test + sei // Set Interrupt Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FBA0) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + beq Pass8 + Fail8: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(SEPPSR, $FBC2, 9) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$CF // Reset NVDIZC Flags + + // Run Test + sep #$CF // Set NVDIZC Flags + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + cld // Clear Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FBE0) // Print Processor Status Flag Data + + // Check Processor Status Flag Data + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckI + beq Pass9 + Fail9: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test PSR (PSR Flags):" + +PageBreak: + db "------------------------------" + +Key: + db "Type| Opcode | NVDIZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +CLCPSR: + db "CLC $18" +CLDPSR: + db "CLD $D8" +CLIPSR: + db "CLI $58" +CLVPSR: + db "CLV $B8" +REPPSR: + db "REP $C2" +SECPSR: + db "SEC $38" +SEDPSR: + db "SED $F8" +SEIPSR: + db "SEI $78" +SEPPSR: + db "SEP $E2" + +PSRResultCheckA: + db $EE +PSRResultCheckB: + db $E7 +PSRResultCheckC: + db $EB +PSRResultCheckD: + db $AF +PSRResultCheckE: + db $20 +PSRResultCheckF: + db $21 +PSRResultCheckG: + db $28 +PSRResultCheckH: + db $24 +PSRResultCheckI: + db $EF + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.png new file mode 100644 index 00000000..87418e1e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.sfc new file mode 100644 index 00000000..7cab0545 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4367bc9d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST PSR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/make.bat new file mode 100644 index 00000000..488e65e5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/PSR/make.bat @@ -0,0 +1 @@ +bass CPUPSR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.asm new file mode 100644 index 00000000..c8df3036 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.asm @@ -0,0 +1,231 @@ +// SNES 65816 CPU Test RET (Return) demo by krom (Peter Lemon): +arch snes.cpu +output "CPURET.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 22) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F942, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F982, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(RTIReturn, $F9C2, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $F9E4) // Print Processor Status Flag Data + + // Run Test + brk #$00 // Software Interrupt + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass1 + PrintText(Fail, $F9F2, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + Pass1: + PrintText(Pass, $F9F2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(RTLReturn, $FA02, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Run Test + jsl RETA // Jump To Subroutine Long + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass2 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + Pass2: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Type/Opcode Text + PrintText(RTSReturn, $FA42, 11) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Processor Status Flag Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Run Test + jsr RETB // Jump To Subroutine + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheck + beq Pass3 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + Pass3: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +RTIBreak: + rti // Return From Interrupt +RETA: + rtl // Return From Subroutine Long +RETB: + rts // Return From Subroutine + +Title: + db "CPU Test RET (Return):" + +PageBreak: + db "------------------------------" + +Key: + db "Type | Opcode | NVZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +RTIReturn: + db "RTI $40" +RTLReturn: + db "RTL $6B" +RTSReturn: + db "RTS $60" + +PSRResultCheck: + db $24 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.png new file mode 100644 index 00000000..fac1f0dc Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.sfc new file mode 100644 index 00000000..e4d0b8a0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..32517117 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST RET " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw RTIBreak // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/make.bat new file mode 100644 index 00000000..619d1b6e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/RET/make.bat @@ -0,0 +1 @@ +bass CPURET.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.asm new file mode 100644 index 00000000..3c451b50 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.asm @@ -0,0 +1,996 @@ +// SNES 65816 CPU Test ROL (Rotate Left) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUROL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 27) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ROLA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + rol // Rotate Left A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ROLResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + rol // Rotate Left A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w ROLResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + rol // Rotate Left A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + rol // Rotate Left A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w ROLResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ROLAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + rol.w AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + rol.w AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + rol.w AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + rol.w AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ROLDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + rol.b AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + rol.b AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + rol.b AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + rol.b AbsoluteData // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ROLAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.w AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.w AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.w AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.w AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ROLDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.b AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.b AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w ROLResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.b AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + rol.b AbsoluteData,x // Rotate Left Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w ROLResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test ROL (Rotate Left):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +ROLA: + db "ROL A (Opcode: $2A)" +ROLAddr: + db "ROL addr (Opcode: $2E)" +ROLDP: + db "ROL dp (Opcode: $26)" +ROLAddrX: + db "ROL addr,X (Opcode: $3E)" +ROLDPX: + db "ROL dp,X (Opcode: $36)" + +ROLResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +ROLResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +ROLResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +ROLResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.png new file mode 100644 index 00000000..00ff0800 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.sfc new file mode 100644 index 00000000..09df46b5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..6dd15569 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST ROL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/make.bat new file mode 100644 index 00000000..5e2eb68d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROL/make.bat @@ -0,0 +1 @@ +bass CPUROL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.asm new file mode 100644 index 00000000..637afefa --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.asm @@ -0,0 +1,996 @@ +// SNES 65816 CPU Test ROR (Rotate Right) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUROR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(RORA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + ror // Rotate Right A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w RORResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$FE // A = $FE + ror // Rotate Right A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w RORResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + ror // Rotate Right A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // set Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + ror // Rotate Right A + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w RORResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(RORAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ror.w AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ror.w AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ror.w AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckC + beq Pass7 + Fail7: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail7 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ror.w AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckD + beq Pass8 + Fail8: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail8 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(RORDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ror.b AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ror.b AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ror.b AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ror.b AbsoluteData // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(RORAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.w AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.w AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.w AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckC + beq Pass15 + Fail15: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail15 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.w AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckD + beq Pass16 + Fail16: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail16 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(RORDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$01 // A = $01 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.b AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$FE // A = $FE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.b AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b AbsoluteData // A = Result Data + cmp.w RORResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$0001 // A = $0001 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.b AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$FFFE // A = $FFFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + ror.b AbsoluteData,x // Rotate Right Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(AbsoluteData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b AbsoluteData // X = Result Data + cpx.w RORResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test ROR (Rotate Right):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +RORA: + db "ROR A (Opcode: $6A)" +RORAddr: + db "ROR addr (Opcode: $6E)" +RORDP: + db "ROR dp (Opcode: $66)" +RORAddrX: + db "ROR addr,X (Opcode: $7E)" +RORDPX: + db "ROR dp,X (Opcode: $76)" + +RORResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +RORResultCheckB: + db $FF +PSRResultCheckB: + db $A4 + +RORResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +RORResultCheckD: + dw $FFFF +PSRResultCheckD: + db $84 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.png new file mode 100644 index 00000000..890d91b4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.sfc new file mode 100644 index 00000000..62c9c89d Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..57645fa9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST ROR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/make.bat new file mode 100644 index 00000000..ba844b12 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/ROR/make.bat @@ -0,0 +1 @@ +bass CPUROR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.asm new file mode 100644 index 00000000..8c907ff0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.asm @@ -0,0 +1,5231 @@ +// SNES 65816 CPU Test SBC (Subtract With Borrow) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUSBC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +AbsoluteData: + dw 0 // Absolute Data Word +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SBCConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sbc.b #$7E // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$7F // A = $7F + sbc.b #$80 // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sbc.w #$7FFE // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$7FFF // A = $7FFF + sbc.w #$8000 // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sbc.b #$48 // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$49 // A = $49 + sbc.b #$50 // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sbc.w #$4998 // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$4999 // A = $4999 + sbc.w #$5000 // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.w AbsoluteData // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.w AbsoluteData // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.w AbsoluteData // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.w AbsoluteData // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.w AbsoluteData // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass13 + Fail13: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail13 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.w AbsoluteData // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass14 + Fail14: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail14 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.w AbsoluteData // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass15 + Fail15: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail15 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.w AbsoluteData // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass16 + Fail16: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail16 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.l AbsoluteData // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.l AbsoluteData // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.l AbsoluteData // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.l AbsoluteData // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.l AbsoluteData // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass21 + Fail21: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail21 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.l AbsoluteData // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass22 + Fail22: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail22 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.l AbsoluteData // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass23 + Fail23: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail23 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.l AbsoluteData // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass24 + Fail24: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail24 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.b AbsoluteData // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + lda.b #$7F // A = $7F + sbc.b AbsoluteData // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.b AbsoluteData // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$7FFF // A = $7FFF + sbc.b AbsoluteData // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.b AbsoluteData // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass29 + Fail29: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail29 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + lda.b #$49 // A = $49 + sbc.b AbsoluteData // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass30 + Fail30: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail30 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.b AbsoluteData // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass31 + Fail31: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail31 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + lda.w #$4999 // A = $4999 + sbc.b AbsoluteData // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass32 + Fail32: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail32 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + sbc (IndirectData) // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + sbc (IndirectData) // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + sbc (IndirectData) // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + sbc (IndirectData) // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + sbc (IndirectData) // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass37 + Fail37: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail37 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + sbc (IndirectData) // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass38 + Fail38: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail38 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + sbc (IndirectData) // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass39 + Fail39: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail39 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + sbc (IndirectData) // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass40 + Fail40: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail40 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + sbc [IndirectData] // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$7F // A = $7F + sbc [IndirectData] // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + sbc [IndirectData] // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass43 + Fail43: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail43 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$7FFF // A = $7FFF + sbc [IndirectData] // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass44 + Fail44: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail44 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + sbc [IndirectData] // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass45 + Fail45: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail45 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.b #$49 // A = $49 + sbc [IndirectData] // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass46 + Fail46: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail46 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + sbc [IndirectData] // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass47 + Fail47: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail47 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + lda.w #$4999 // A = $4999 + sbc [IndirectData] // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass48 + Fail48: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail48 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.w AbsoluteData,x // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.w AbsoluteData,x // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.w AbsoluteData,x // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.w AbsoluteData,x // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.w AbsoluteData,x // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass53 + Fail53: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail53 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.w AbsoluteData,x // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass54 + Fail54: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail54 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.w AbsoluteData,x // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass55 + Fail55: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail55 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.w AbsoluteData,x // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass56 + Fail56: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail56 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCLongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.l AbsoluteData,x // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass57 + Fail57: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail57 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.l AbsoluteData,x // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass58 + Fail58: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail58 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.l AbsoluteData,x // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass59 + Fail59: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail59 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.l AbsoluteData,x // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass60 + Fail60: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail60 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.l AbsoluteData,x // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass61 + Fail61: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail61 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.l AbsoluteData,x // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass62 + Fail62: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail62 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.l AbsoluteData,x // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass63 + Fail63: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail63 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.l AbsoluteData,x // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass64 + Fail64: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail64 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc AbsoluteData,y // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass65 + Fail65: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail65 + Pass65: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail65 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc AbsoluteData,y // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass66 + Fail66: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail66 + Pass66: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail66 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc AbsoluteData,y // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass67 + Fail67: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail67 + Pass67: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail67 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc AbsoluteData,y // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass68 + Fail68: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail68 + Pass68: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail68 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc AbsoluteData,y // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass69 + Fail69: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail69 + Pass69: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail69 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc AbsoluteData,y // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass70 + Fail70: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail70 + Pass70: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail70 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc AbsoluteData,y // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass71 + Fail71: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail71 + Pass71: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail71 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc AbsoluteData,y // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass72 + Fail72: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail72 + Pass72: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail72 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.b AbsoluteData,x // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass73 + Fail73: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail73 + Pass73: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail73 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc.b AbsoluteData,x // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass74 + Fail74: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail74 + Pass74: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail74 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.b AbsoluteData,x // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass75 + Fail75: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail75 + Pass75: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail75 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc.b AbsoluteData,x // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass76 + Fail76: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail76 + Pass76: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail76 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.b AbsoluteData,x // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass77 + Fail77: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail77 + Pass77: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail77 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc.b AbsoluteData,x // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass78 + Fail78: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail78 + Pass78: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail78 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.b AbsoluteData,x // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass79 + Fail79: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail79 + Pass79: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail79 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc.b AbsoluteData,x // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass80 + Fail80: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail80 + Pass80: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail80 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc (IndirectData,x) // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass81 + Fail81: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail81 + Pass81: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail81 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$7F // A = $7F + sbc (IndirectData,x) // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass82 + Fail82: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail82 + Pass82: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail82 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc (IndirectData,x) // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass83 + Fail83: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail83 + Pass83: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail83 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$7FFF // A = $7FFF + sbc (IndirectData,x) // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass84 + Fail84: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail84 + Pass84: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail84 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc (IndirectData,x) // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass85 + Fail85: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail85 + Pass85: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail85 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.b #$49 // A = $49 + sbc (IndirectData,x) // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass86 + Fail86: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail86 + Pass86: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail86 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc (IndirectData,x) // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass87 + Fail87: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail87 + Pass87: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail87 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + lda.w #$4999 // A = $4999 + sbc (IndirectData,x) // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass88 + Fail88: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail88 + Pass88: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail88 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc (IndirectData),y // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass89 + Fail89: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail89 + Pass89: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail89 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc (IndirectData),y // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass90 + Fail90: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail90 + Pass90: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail90 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc (IndirectData),y // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass91 + Fail91: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail91 + Pass91: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail91 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc (IndirectData),y // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass92 + Fail92: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail92 + Pass92: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail92 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc (IndirectData),y // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass93 + Fail93: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail93 + Pass93: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail93 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc (IndirectData),y // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass94 + Fail94: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail94 + Pass94: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail94 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc (IndirectData),y // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass95 + Fail95: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail95 + Pass95: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail95 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc (IndirectData),y // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass96 + Fail96: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail96 + Pass96: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail96 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc [IndirectData],y // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass97 + Fail97: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail97 + Pass97: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail97 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc [IndirectData],y // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass98 + Fail98: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail98 + Pass98: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail98 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc [IndirectData],y // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass99 + Fail99: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail99 + Pass99: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail99 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc [IndirectData],y // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass100 + Fail100: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail100 + Pass100: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail100 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc [IndirectData],y // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass101 + Fail101: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail101 + Pass101: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail101 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc [IndirectData],y // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass102 + Fail102: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail102 + Pass102: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail102 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc [IndirectData],y // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass103 + Fail103: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail103 + Pass103: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail103 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc [IndirectData],y // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass104 + Fail104: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail104 + Pass104: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail104 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCSRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + pha // Push A To Stack + lda.b #$7F // A = $7F + sbc $01,s // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass105 + Fail105: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail105 + Pass105: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail105 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + pha // Push A To Stack + lda.b #$7F // A = $7F + sbc $01,s // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass106 + Fail106: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail106 + Pass106: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail106 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + pha // Push A To Stack + lda.w #$7FFF // A = $7FFF + sbc $01,s // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass107 + Fail107: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail107 + Pass107: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail107 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + pha // Push A To Stack + lda.w #$7FFF // A = $7FFF + sbc $01,s // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass108 + Fail108: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail108 + Pass108: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail108 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + pha // Push A To Stack + lda.b #$49 // A = $49 + sbc $01,s // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass109 + Fail109: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail109 + Pass109: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail109 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + pha // Push A To Stack + lda.b #$49 // A = $49 + sbc $01,s // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass110 + Fail110: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail110 + Pass110: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail110 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + pha // Push A To Stack + lda.w #$4999 // A = $4999 + sbc $01,s // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass111 + Fail111: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail111 + Pass111: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail111 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + pha // Push A To Stack + lda.w #$4999 // A = $4999 + sbc $01,s // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass112 + Fail112: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail112 + Pass112: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail112 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCSRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$7E // A = $7E + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc ($01,s),y // A -= $7E + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckA + beq Pass113 + Fail113: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail113 + Pass113: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail113 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$80 // A = $80 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$7F // A = $7F + sbc ($01,s),y // A -= $80 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckB + beq Pass114 + Fail114: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail114 + Pass114: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail114 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$7FFE // A = $7FFE + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc ($01,s),y // A -= $7FFE + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckC + beq Pass115 + Fail115: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail115 + Pass115: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail115 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$8000 // A = $8000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$7FFF // A = $7FFF + sbc ($01,s),y // A -= $8000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckD + beq Pass116 + Fail116: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail116 + Pass116: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail116 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.b #$48 // A = $48 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc ($01,s),y // A -= $48 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckE + beq Pass117 + Fail117: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail117 + Pass117: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail117 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal8Bit, $FB42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.b #$50 // A = $50 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.b #$49 // A = $49 + sbc ($01,s),y // A -= $50 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w SBCResultCheckF + beq Pass118 + Fail118: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail118 + Pass118: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail118 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FB82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$4998 // A = $4998 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc ($01,s),y // A -= $4998 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckG + beq Pass119 + Fail119: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail119 + Pass119: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail119 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Decimal16Bit, $FBC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + sep #$08 // Set Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sec // Set Carry Flag + + // Run Test + lda.w #$5000 // A = $5000 + sta.b AbsoluteData // Store Absolute Data + ldx.w #AbsoluteData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + lda.w #$4999 // A = $4999 + sbc ($01,s),y // A -= $5000 + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w SBCResultCheckH + beq Pass120 + Fail120: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail120 + Pass120: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail120 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test SBC (Sub With Borrow):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Decimal8Bit: + db "BCD,8" +Decimal16Bit: + db "BCD,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +SBCConst: + db "SBC #const (Opcode: $E9)" +SBCAddr: + db "SBC addr (Opcode: $ED)" +SBCLong: + db "SBC long (Opcode: $EF)" +SBCDP: + db "SBC dp (Opcode: $E5)" +SBCDPIndirect: + db "SBC (dp) (Opcode: $F2)" +SBCDPIndirectLong: + db "SBC [dp] (Opcode: $E7)" +SBCAddrX: + db "SBC addr,X (Opcode: $FD)" +SBCLongX: + db "SBC long,X (Opcode: $FF)" +SBCAddrY: + db "SBC addr,Y (Opcode: $F9)" +SBCDPX: + db "SBC dp,X (Opcode: $F5)" +SBCDPIndirectX: + db "SBC (dp,X) (Opcode: $E1)" +SBCDPIndirectY: + db "SBC (dp),Y (Opcode: $F1)" +SBCDPIndirectLongY: + db "SBC [dp],Y (Opcode: $F7)" +SBCSRS: + db "SBC sr,S (Opcode: $E3)" +SBCSRSY: + db "SBC (sr,S),Y (Opcode: $F3)" + +SBCResultCheckA: + db $00 +PSRResultCheckA: + db $27 + +SBCResultCheckB: + db $FF +PSRResultCheckB: + db $E4 + +SBCResultCheckC: + dw $0000 +PSRResultCheckC: + db $07 + +SBCResultCheckD: + dw $FFFF +PSRResultCheckD: + db $C4 + +SBCResultCheckE: + db $00 +PSRResultCheckE: + db $2F + +SBCResultCheckF: + db $99 +PSRResultCheckF: + db $AC + +SBCResultCheckG: + dw $0000 +PSRResultCheckG: + db $0F + +SBCResultCheckH: + dw $9999 +PSRResultCheckH: + db $8C + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.png new file mode 100644 index 00000000..beb3e4d7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.sfc new file mode 100644 index 00000000..5d74af8a Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4211d595 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST SBC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/make.bat new file mode 100644 index 00000000..ade100dc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/SBC/make.bat @@ -0,0 +1 @@ +bass CPUSBC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.asm new file mode 100644 index 00000000..38e2258e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.asm @@ -0,0 +1,2313 @@ +// SNES 65816 CPU Test STR (Store Memory) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUSTR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte +IndirectData: + dl 0 // Indirect Data Long + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 28) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(STAAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + rep #$80 // Reset Negative Flag + sta.w ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + rep #$80 // Reset Negative Flag + sta.w ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STALong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + rep #$80 // Reset Negative Flag + sta.l ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass3 + Fail3: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail3 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + rep #$80 // Reset Negative Flag + sta.l ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass4 + Fail4: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail4 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + rep #$80 // Reset Negative Flag + sta.b ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass5 + Fail5: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail5 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + rep #$80 // Reset Negative Flag + sta.b ResultData // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass6 + Fail6: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail6 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPIndirect, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Address Word + rep #$02 // Reset Zero Flag + stx.b IndirectData // Store Indirect Data + sta (IndirectData) // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass7 + Fail7: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail7 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Address Word + rep #$02 // Reset Zero Flag + stx.b IndirectData // Store Indirect Data + sta (IndirectData) // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass8 + Fail8: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail8 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPIndirectLong, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Address Word + rep #$02 // Reset Zero Flag + stx.b IndirectData // Store Indirect Data + sta [IndirectData] // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Address Word + rep #$02 // Reset Zero Flag + stx.b IndirectData // Store Indirect Data + sta [IndirectData] // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STAAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.w ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass11 + Fail11: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail11 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.w ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass12 + Fail12: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail12 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STALongX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.l ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass13 + Fail13: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail13 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.l ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass14 + Fail14: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail14 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STAAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta ResultData,y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass15 + Fail15: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail15 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta ResultData,y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass16 + Fail16: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail16 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.b ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta.b ResultData,x // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta (IndirectData,x) // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass19 + Fail19: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail19 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sta (IndirectData,x) // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass20 + Fail20: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail20 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta (IndirectData),y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta (IndirectData),y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STADPIndirectLongY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta [IndirectData],y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass23 + Fail23: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail23 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Address Word + stx.b IndirectData // Store Indirect Data + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta [IndirectData],y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass24 + Fail24: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail24 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STASRS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + pha // Push A To Stack + lda.b #$FF // A = $FF + sta $01,s // Store A + pla // Pull A From Stack + rep #$80 // Reset Negative Flag + sta.b ResultData // Store Result To Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + pha // Push A To Stack + lda.w #$FFFF // A = $FFFF + sta $01,s // Store A + pla // Pull A From Stack + rep #$80 // Reset Negative Flag + sta.b ResultData // Store Result To Memory + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STASRSY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$FF // A = $FF + ldx.w #ResultData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta ($01,s),y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckA + beq Pass27 + Fail27: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail27 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + ldx.w #ResultData // X = Absolute Data Indirect Address + phx // Push X To Stack + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + sta ($01,s),y // Store A + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckB + beq Pass28 + Fail28: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail28 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STXAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + rep #$80 // Reset Negative Flag + stx.w ResultData // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + rep #$80 // Reset Negative Flag + stx.w ResultData // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STXDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + rep #$80 // Reset Negative Flag + stx.b ResultData // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass31 + Fail31: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail31 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + rep #$80 // Reset Negative Flag + stx.b ResultData // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass32 + Fail32: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail32 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STXDPY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$FF // X = $FF + ldy.b #0 // Y = 0 + rep #$02 // Reset Zero Flag + stx ResultData,y // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + ldy.w #0 // Y = 0 + rep #$02 // Reset Zero Flag + stx ResultData,y // Store X + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STYAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + rep #$80 // Reset Negative Flag + sty.w ResultData // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass35 + Fail35: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail35 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + rep #$80 // Reset Negative Flag + sty.w ResultData // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass36 + Fail36: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail36 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STYDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + rep #$80 // Reset Negative Flag + sty.b ResultData // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + rep #$80 // Reset Negative Flag + sty.b ResultData // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STYDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$FF // Y = $FF + ldx.b #0 // X = 0 + rep #$02 // Reset Zero Flag + sty ResultData,x // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckC + beq Pass39 + Fail39: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail39 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + sty ResultData,x // Store Y + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckD + beq Pass40 + Fail40: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail40 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STZAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + stz.w ResultData // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckE + beq Pass41 + Fail41: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail41 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + stz.w ResultData // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckF + beq Pass42 + Fail42: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail42 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STZDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + stz.b ResultData // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckE + beq Pass43 + Fail43: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail43 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$02 // Reset Zero Flag + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + stz.b ResultData // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckF + beq Pass44 + Fail44: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail44 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STZAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + stz.w ResultData,x // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckE + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + stz.w ResultData,x // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckF + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $40, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(STZDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + stz.b ResultData,x // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w STRResultCheckE + beq Pass47 + Fail47: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail47 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(Binary16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + clc // Clear Carry Flag + + // Run Test + ldx.w #0 // X = 0 + rep #$02 // Reset Zero Flag + stz.b ResultData,x // Store Zero + + // Store Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w STRResultCheckF + beq Pass48 + Fail48: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail48 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test STR (Store Memory):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +Binary8Bit: + db "BIN,8" +Binary16Bit: + db "BIN,16" +Fail: + db "FAIL" +Pass: + db "PASS" + +STAAddr: + db "STA addr (Opcode: $8D)" +STALong: + db "STA long (Opcode: $8F)" +STADP: + db "STA dp (Opcode: $85)" +STADPIndirect: + db "STA (dp) (Opcode: $92)" +STADPIndirectLong: + db "STA [dp] (Opcode: $87)" +STAAddrX: + db "STA addr,X (Opcode: $9D)" +STALongX: + db "STA long,X (Opcode: $9F)" +STAAddrY: + db "STA addr,Y (Opcode: $99)" +STADPX: + db "STA dp,X (Opcode: $95)" +STADPIndirectX: + db "STA (dp,X) (Opcode: $81)" +STADPIndirectY: + db "STA (dp),Y (Opcode: $91)" +STADPIndirectLongY: + db "STA [dp],Y (Opcode: $97)" +STASRS: + db "STA sr,S (Opcode: $83)" +STASRSY: + db "STA (sr,S),Y (Opcode: $93)" +STXAddr: + db "STX addr (Opcode: $8E)" +STXDP: + db "STX dp (Opcode: $86)" +STXDPY: + db "STX dp,Y (Opcode: $96)" +STYAddr: + db "STY addr (Opcode: $8C)" +STYDP: + db "STY dp (Opcode: $84)" +STYDPX: + db "STY dp,X (Opcode: $94)" +STZAddr: + db "STZ addr (Opcode: $9C)" +STZDP: + db "STZ dp (Opcode: $64)" +STZAddrX: + db "STZ addr,X (Opcode: $9E)" +STZDPX: + db "STZ dp,X (Opcode: $74)" + +STRResultCheckA: + db $FF +PSRResultCheckA: + db $24 + +STRResultCheckB: + dw $FFFF +PSRResultCheckB: + db $04 + +STRResultCheckC: + db $FF +PSRResultCheckC: + db $34 + +STRResultCheckD: + dw $FFFF +PSRResultCheckD: + db $24 + +STRResultCheckE: + db $00 +PSRResultCheckE: + db $24 + +STRResultCheckF: + dw $0000 +PSRResultCheckF: + db $04 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.png new file mode 100644 index 00000000..3554c51a Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.sfc new file mode 100644 index 00000000..50887680 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..2e6d98cb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST STR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/make.bat new file mode 100644 index 00000000..249e5116 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/STR/make.bat @@ -0,0 +1 @@ +bass CPUSTR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.asm new file mode 100644 index 00000000..04f4f30c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.asm @@ -0,0 +1,3281 @@ +// SNES 65816 CPU Test TRN (Transfer) demo by krom (Peter Lemon): +arch snes.cpu +output "CPUTRN.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSR(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSRFlagTest // Test PSR Flag Data + + bra {#}PSREnd + + {#}PSRFlagTest: + bit.b {SRC} // Test Processor Status Flag Data Bit + bne {#}PSRFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSRFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSREnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +ResultData: + dw 0 // Result Data Word +PSRFlagData: + db 0 // Processor Status Register Flag Data Byte + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 24) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(TRNTAX, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass1 + Fail1: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail1 + Pass1: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail1 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass2 + Fail2: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail2 + Pass2: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail2 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass3 + Fail3: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail3 + Pass3: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail3 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass4 + Fail4: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail4 + Pass4: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail4 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckE + beq Pass5 + Fail5: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail5 + Pass5: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail5 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckF + beq Pass6 + Fail6: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail6 + Pass6: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail6 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass7 + Fail7: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail7 + Pass7: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail7 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tax // X = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass8 + Fail8: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail8 + Pass8: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail8 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTAY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.b #$00 // A = $00 + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass9 + Fail9: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail9 + Pass9: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail9 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.b #$FF // A = $FF + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass10 + Fail10: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail10 + Pass10: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail10 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass11 + Fail11: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail11 + Pass11: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail11 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass12 + Fail12: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail12 + Pass12: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail12 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckE + beq Pass13 + Fail13: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail13 + Pass13: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail13 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckF + beq Pass14 + Fail14: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail14 + Pass14: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail14 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass15 + Fail15: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail15 + Pass15: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail15 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tay // Y = A + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass16 + Fail16: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail16 + Pass16: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail16 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTCD, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phd // Push Direct Page Register To Stack + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass17 + Fail17: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail17 + Pass17: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail17 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + phd // Push Direct Page Register To Stack + rep #$20 // Set 16-Bit Accumulator + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass18 + Fail18: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail18 + Pass18: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail18 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tcd // Direct Page Register = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + phd // Push Direct Page Register To Stack + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass19 + Fail19: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail19 + Pass19: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail19 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tcd // Direct Page Register = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + phd // Push Direct Page Register To Stack + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + plx // Pull X From Stack + stx.b ResultData // Store Result To Memory + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass20 + Fail20: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail20 + Pass20: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail20 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTCS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckI + beq Pass21 + Fail21: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail21 + Pass21: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckI + bne Fail21 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckJ + beq Pass22 + Fail22: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail22 + Pass22: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckJ + bne Fail22 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tas // Stack Pointer = A + tsx // X = Stack Pointer + lda.w #$1FFF // A = $1FFF + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckK + beq Pass23 + Fail23: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail23 + Pass23: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckK + bne Fail23 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tas // Stack Pointer = A + tsx // X = Stack Pointer + lda.w #$1FFF // A = $1FFF + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckL + beq Pass24 + Fail24: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail24 + Pass24: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckL + bne Fail24 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTDC, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + tdc // A = Direct Page Register + + // Store Result & Processor Status Flag Data + rep #$20 // Set 16-Bit Accumulator + sta.b ResultData // Store Result To Memory + sep #$20 // Set 8-Bit Accumulator + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass25 + Fail25: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail25 + Pass25: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail25 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + tdc // A = Direct Page Register + rep #$20 // Set 16-Bit Accumulator + tax // X = A + + // Store Result & Processor Status Flag Data + sep #$20 // Set 8-Bit Accumulator + php // Push Processor Status Register To Stack + rep #$20 // Set 16-Bit Accumulator + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + stx.b ResultData // Store Result To Memory + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass26 + Fail26: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail26 + Pass26: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail26 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$0000 // A = $0000 + tcd // Direct Page Register = A + tdc // A = Direct Page Register + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass27 + Fail27: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail27 + Pass27: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail27 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + tcd // Direct Page Register = A + tdc // A = Direct Page Register + tax // X = A + + // Store Result & Processor Status Flag Data + php // Push Processor Status Register To Stack + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tcd // Direct Page Register = A + stx.b ResultData // Store Result To Memory + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass28 + Fail28: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail28 + Pass28: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail28 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTSC, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.w #$1FFF // X = $1FFF + lda.w #$0000 // A = $0000 + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + tsa // A = Stack Pointer + txs // Stack Pointer = X + + // Store Result & Processor Status Flag Data + rep #$20 // Set 16-Bit Accumulator + sta.b ResultData // Store Result To Memory + sep #$20 // Set 8-Bit Accumulator + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass29 + Fail29: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail29 + Pass29: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail29 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$1FFF // X = $1FFF + lda.w #$FFFF // A = $FFFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + tsa // A = Stack Pointer + txs // Stack Pointer = X + + // Store Result & Processor Status Flag Data + rep #$20 // Set 16-Bit Accumulator + sta.b ResultData // Store Result To Memory + sep #$20 // Set 8-Bit Accumulator + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass30 + Fail30: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail30 + Pass30: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail30 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$1FFF // X = $1FFF + lda.w #$0000 // A = $0000 + tas // Stack Pointer = A + tsa // A = Stack Pointer + txs // Stack Pointer = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass31 + Fail31: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail31 + Pass31: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail31 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$1FFF // X = $1FFF + lda.w #$FFFF // A = $FFFF + tas // Stack Pointer = A + tsa // A = Stack Pointer + txs // Stack Pointer = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass32 + Fail32: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail32 + Pass32: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail32 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTSX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.w #$1FFF // A = $1FFF + ldx.w #$0000 // X = $0000 + txs // Stack Pointer = X + sep #$10 // Set 8-Bit X/Y + tsx // X = Stack Pointer + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckE + beq Pass33 + Fail33: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail33 + Pass33: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckE + bne Fail33 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$1FFF // A = $1FFF + ldx.w #$FFFF // X = $FFFF + txs // Stack Pointer = X + sep #$10 // Set 8-Bit X/Y + tsx // X = Stack Pointer + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckF + beq Pass34 + Fail34: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail34 + Pass34: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckF + bne Fail34 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$1FFF // A = $1FFF + ldx.w #$0000 // X = $0000 + txs // Stack Pointer = X + tsx // X = Stack Pointer + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass35 + Fail35: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail35 + Pass35: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail35 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$1FFF // A = $1FFF + ldx.w #$FFFF // X = $FFFF + txs // Stack Pointer = X + tsx // X = Stack Pointer + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass36 + Fail36: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail36 + Pass36: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail36 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTXA, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass37 + Fail37: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail37 + Pass37: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail37 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass38 + Fail38: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail38 + Pass38: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail38 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + sep #$20 // Set 8-Bit Accumulator + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 1) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckM + beq Pass39 + Fail39: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail39 + Pass39: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckM + bne Fail39 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + sep #$20 // Set 8-Bit Accumulator + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 1) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckN + beq Pass40 + Fail40: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail40 + Pass40: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckN + bne Fail40 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$00 // X = $00 + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckO + beq Pass41 + Fail41: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail41 + Pass41: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckO + bne Fail41 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckP + beq Pass42 + Fail42: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail42 + Pass42: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckP + bne Fail42 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass43 + Fail43: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail43 + Pass43: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail43 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + txa // A = X + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass44 + Fail44: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail44 + Pass44: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail44 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTXS, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.w #$0000 // X = $0000 + sep #$10 // Set 8-Bit X/Y + txs // Stack Pointer = X + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckQ + beq Pass45 + Fail45: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail45 + Pass45: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckQ + bne Fail45 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + sep #$10 // Set 8-Bit X/Y + txs // Stack Pointer = X + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckR + beq Pass46 + Fail46: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail46 + Pass46: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckR + bne Fail46 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + txs // Stack Pointer = X + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckI + beq Pass47 + Fail47: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail47 + Pass47: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckI + bne Fail47 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + txs // Stack Pointer = X + tsx // X = Stack Pointer + rep #$20 // Set 16-Bit Accumulator + lda.w #$1FFF // A = $1FFF + sep #$20 // Set 8-Bit Accumulator + tas // Stack Pointer = A + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckJ + beq Pass48 + Fail48: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail48 + Pass48: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckJ + bne Fail48 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.b #$00 // X = $00 + txy // Y = X + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass49 + Fail49: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail49 + Pass49: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail49 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.b #$FF // X = $FF + txy // Y = X + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass50 + Fail50: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail50 + Pass50: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail50 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$0000 // X = $0000 + txy // Y = X + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass51 + Fail51: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail51 + Pass51: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail51 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + txy // Y = X + + // Store Result & Processor Status Flag Data + sty.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass52 + Fail52: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail52 + Pass52: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail52 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTYA, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass53 + Fail53: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail53 + Pass53: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail53 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass54 + Fail54: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail54 + Pass54: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail54 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + sep #$20 // Set 8-Bit Accumulator + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 1) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckM + beq Pass55 + Fail55: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail55 + Pass55: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckM + bne Fail55 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sep #$20 // Set 8-Bit Accumulator + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 1) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckN + beq Pass56 + Fail56: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail56 + Pass56: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckN + bne Fail56 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$00 // Y = $00 + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FB24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckO + beq Pass57 + Fail57: + PrintText(Fail, $FB32, 4) // Load Text To VRAM Lo Bytes + bra Fail57 + Pass57: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckO + bne Fail57 + PrintText(Pass, $FB32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX8Bit, $FB42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + rep #$10 // Set 16-Bit X/Y + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FB64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckP + beq Pass58 + Fail58: + PrintText(Fail, $FB72, 4) // Load Text To VRAM Lo Bytes + bra Fail58 + Pass58: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckP + bne Fail58 + PrintText(Pass, $FB72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FB82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FB92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckG + beq Pass59 + Fail59: + PrintText(Fail, $FBB2, 4) // Load Text To VRAM Lo Bytes + bra Fail59 + Pass59: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckG + bne Fail59 + PrintText(Pass, $FBB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FBC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + tya // A = Y + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FBD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FBE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckH + beq Pass60 + Fail60: + PrintText(Fail, $FBF2, 4) // Load Text To VRAM Lo Bytes + bra Fail60 + Pass60: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckH + bne Fail60 + PrintText(Pass, $FBF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $100, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNTYX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA02, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy.b #$00 // Y = $00 + tyx // X = Y + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckA + beq Pass61 + Fail61: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail61 + Pass61: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckA + bne Fail61 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX8Bit, $FA42, 5) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + sep #$10 // Set 8-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.b #$FF // Y = $FF + tyx // X = Y + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + rep #$10 // Set 16-Bit X/Y + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckB + beq Pass62 + Fail62: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail62 + Pass62: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckB + bne Fail62 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA82, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$0000 // Y = $0000 + tyx // X = Y + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckC + beq Pass63 + Fail63: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail63 + Pass63: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckC + bne Fail63 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FAC2, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + tyx // X = Y + + // Store Result & Processor Status Flag Data + stx.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckD + beq Pass64 + Fail64: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail64 + Pass64: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckD + bne Fail64 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNXBA, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda.w #$00FF // A = $00FF + sep #$20 // Set 8-Bit Accumulator + xba // A = B + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckM + beq Pass65 + Fail65: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail65 + Pass65: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckM + bne Fail65 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + sep #$20 // Set 8-Bit Accumulator + xba // A = B + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 1) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + lda.b ResultData // A = Result Data + cmp.w TRNResultCheckN + beq Pass66 + Fail66: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail66 + Pass66: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckN + bne Fail66 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$00FF // A = $00FF + xba // A = B + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckS + beq Pass67 + Fail67: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail67 + Pass67: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckS + bne Fail67 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FAC2, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FF00 // A = $FF00 + xba // A = B + + // Store Result & Processor Status Flag Data + sta.b ResultData // Store Result To Memory + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FAD2, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAE4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckT + beq Pass68 + Fail68: + PrintText(Fail, $FAF2, 4) // Load Text To VRAM Lo Bytes + bra Fail68 + Pass68: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckT + bne Fail68 + PrintText(Pass, $FAF2, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(TRNXCE, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA02, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx.w #$FFFF // X = $FFFF + sec // Set Carry Flag + xce // E = C + xce // E = C + + // Store Result & Processor Status Flag Data + rep #$10 // Set 16-Bit X/Y + stx.b ResultData // Store Result To Memory + ldx.w #$1FFF // X = $1FFF + txs // Stack = X + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA12, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA24) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckU + beq Pass69 + Fail69: + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + bra Fail69 + Pass69: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckU + bne Fail69 + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M8BitX16Bit, $FA42, 6) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + sep #$20 // Set 8-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + ldy.w #$FFFF // Y = $FFFF + sec // Set Carry Flag + xce // E = C + xce // E = C + + // Store Result & Processor Status Flag Data + rep #$10 // Set 16-Bit X/Y + sty.b ResultData // Store Result To Memory + ldx.w #$1FFF // X = $1FFF + txs // Stack = X + php // Push Processor Status Register To Stack + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA52, 2) // Print Result Data + PrintPSR(PSRFlagData, $FA64) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckU + beq Pass70 + Fail70: + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + bra Fail70 + Pass70: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckU + bne Fail70 + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Modes Text + PrintText(M16BitX16Bit, $FA82, 7) // Load Text To VRAM Lo Bytes + + // Setup Flags + rep #$08 // Reset Decimal Flag + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + clc // Clear Carry Flag + + // Run Test + lda.w #$FFFF // A = $FFFF + sec // Set Carry Flag + xce // E = C + xce // E = C + + // Store Result & Processor Status Flag Data + rep #$20 // Set 16-Bit Accumulator + rep #$10 // Set 16-Bit X/Y + sta.b ResultData // Store Result To Memory + ldx.w #$1FFF // X = $1FFF + txs // Stack = X + php // Push Processor Status Register To Stack + sep #$20 // Set 8-Bit Accumulator + pla // Pull Accumulator Register From Stack + sta.b PSRFlagData // Store Processor Status Flag Data To Memory + + // Print Result & Processor Status Flag Data + PrintValue(ResultData, $FA92, 2) // Print Result Data + PrintPSR(PSRFlagData, $FAA4) // Print Processor Status Flag Data + + // Check Result & Processor Status Flag Data + ldx.b ResultData // X = Result Data + cpx.w TRNResultCheckV + beq Pass71 + Fail71: + PrintText(Fail, $FAB2, 4) // Load Text To VRAM Lo Bytes + bra Fail71 + Pass71: + lda.b PSRFlagData // A = Processor Status Flag Data + cmp.w PSRResultCheckV + bne Fail71 + PrintText(Pass, $FAB2, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "CPU Test TRN (Transfer):" + +PageBreak: + db "------------------------------" + +Key: + db "Modes | Result | NVZC | Test |" +M8BitX8Bit: + db "M8,X8" +M8BitX16Bit: + db "M8,X16" +M16BitX8Bit: + db "M16,X8" +M16BitX16Bit: + db "M16,X16" +Fail: + db "FAIL" +Pass: + db "PASS" + +TRNTAX: + db "TAX (Opcode: $AA)" +TRNTAY: + db "TAY (Opcode: $A8)" +TRNTCD: + db "TCD/TAD (Opcode: $5B)" +TRNTCS: + db "TCS/TAS (Opcode: $1B)" +TRNTDC: + db "TDC/TDA (Opcode: $7B)" +TRNTSC: + db "TSC/TSA (Opcode: $3B)" +TRNTSX: + db "TSX (Opcode: $BA)" +TRNTXA: + db "TXA (Opcode: $8A)" +TRNTXS: + db "TXS (Opcode: $9A)" +TRNTXY: + db "TXY (Opcode: $9B)" +TRNTYA: + db "TYA (Opcode: $98)" +TRNTYX: + db "TYX (Opcode: $BB)" +TRNXBA: + db "XBA (Opcode: $EB)" +TRNXCE: + db "XCE (Opcode: $FB)" + +TRNResultCheckA: + db $00 +PSRResultCheckA: + db $36 + +TRNResultCheckB: + db $FF +PSRResultCheckB: + db $B4 + +TRNResultCheckC: + dw $0000 +PSRResultCheckC: + db $26 + +TRNResultCheckD: + dw $FFFF +PSRResultCheckD: + db $A4 + +TRNResultCheckE: + db $00 +PSRResultCheckE: + db $16 + +TRNResultCheckF: + db $FF +PSRResultCheckF: + db $94 + +TRNResultCheckG: + dw $0000 +PSRResultCheckG: + db $06 + +TRNResultCheckH: + dw $FFFF +PSRResultCheckH: + db $84 + +TRNResultCheckI: + dw $0000 +PSRResultCheckI: + db $24 + +TRNResultCheckJ: + dw $FFFF +PSRResultCheckJ: + db $24 + +TRNResultCheckK: + dw $0000 +PSRResultCheckK: + db $04 + +TRNResultCheckL: + dw $FFFF +PSRResultCheckL: + db $04 + +TRNResultCheckM: + db $00 +PSRResultCheckM: + db $26 + +TRNResultCheckN: + db $FF +PSRResultCheckN: + db $A4 + +TRNResultCheckO: + dw $0000 +PSRResultCheckO: + db $16 + +TRNResultCheckP: + dw $00FF +PSRResultCheckP: + db $14 + +TRNResultCheckQ: + db $00 +PSRResultCheckQ: + db $34 + +TRNResultCheckR: + db $FF +PSRResultCheckR: + db $34 + +TRNResultCheckS: + dw $FF00 +PSRResultCheckS: + db $06 + +TRNResultCheckT: + dw $00FF +PSRResultCheckT: + db $84 + +TRNResultCheckU: + dw $00FF +PSRResultCheckU: + db $25 + +TRNResultCheckV: + dw $FFFF +PSRResultCheckV: + db $05 + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.png b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.png new file mode 100644 index 00000000..62b266d3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.sfc b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.sfc new file mode 100644 index 00000000..5eeb05b3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..0ed23b15 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "65816 CPU TEST TRN " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/make.bat b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/make.bat new file mode 100644 index 00000000..1b589952 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/CPU/TRN/make.bat @@ -0,0 +1 @@ +bass CPUTRN.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e24ccd6f --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST ADC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.asm new file mode 100644 index 00000000..b7308f54 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.asm @@ -0,0 +1,864 @@ +// SNES SPC700 CPU Test ADC (Add With Carry) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700ADC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ADCConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait15: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0F + bne Wait15 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8F + bne PASS15 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail15: + bra Fail15 + PASS15: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait16: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$10 + bne Wait16 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$90 + bne PASS16 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail16: + bra Fail16 + PASS16: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait17: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$11 + bne Wait17 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$91 + bne PASS17 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail17: + bra Fail17 + PASS17: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait18: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$12 + bne Wait18 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$92 + bne PASS18 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail18: + bra Fail18 + PASS18: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait19: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$13 + bne Wait19 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCIndirectXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$93 + bne PASS19 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail19: + bra Fail19 + PASS19: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait20: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$14 + bne Wait20 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$94 + bne PASS20 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail20: + bra Fail20 + PASS20: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait21: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$15 + bne Wait21 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$95 + bne PASS21 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail21: + bra Fail21 + PASS21: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait22: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$16 + bne Wait22 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$96 + bne PASS22 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail22: + bra Fail22 + PASS22: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait23: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$17 + bne Wait23 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADCDPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$97 + bne PASS23 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail23: + bra Fail23 + PASS23: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait24: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$18 + bne Wait24 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$98 + bne PASS24 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail24: + bra Fail24 + PASS24: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait25: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$19 + bne Wait25 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ADDW, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$99 + bne PASS25 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail25: + bra Fail25 + PASS25: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait26: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1A + bne Wait26 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9A + bne PASS26 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail26: + bra Fail26 + PASS26: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + +Loop: + jmp Loop + +Title: + db "SPC Test ADC (Add With Carry):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +ADCConst: + db "ADC #const (Opcode: $88)" +ADCAddr: + db "ADC addr (Opcode: $85)" +ADCDP: + db "ADC dp (Opcode: $84)" +ADCAddrX: + db "ADC addr,X (Opcode: $95)" +ADCAddrY: + db "ADC addr,Y (Opcode: $96)" +ADCDPX: + db "ADC dp,X (Opcode: $94)" +ADCDPIndirectX: + db "ADC (dp,X) (Opcode: $87)" +ADCDPIndirectY: + db "ADC (dp),Y (Opcode: $97)" +ADCIndirectX: + db "ADC (X) (Opcode: $86)" +ADCIndirectXY: + db "ADC (X)=(Y) (Opcode: $99)" +ADCDPConst: + db "ADC dp=#const(Opcode: $98)" +ADCDPDP: + db "ADC dp=dp (Opcode: $89)" +ADDW: + db "ADW dp (Opcode: $7A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700ADC.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.png new file mode 100644 index 00000000..9d74808c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.sfc new file mode 100644 index 00000000..35913a90 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.spc new file mode 100644 index 00000000..e55d23b9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC_spc.asm new file mode 100644 index 00000000..fad06b90 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC_spc.asm @@ -0,0 +1,901 @@ +// SNES SPC700 CPU Test ADC (Add With Carry) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700ADC.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$7F // A = $7F + adc #$81 // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$0B // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + lda #$7F // A = $7F + adc #$7F // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$C8 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + lda #$7F // A = $7F + adc.w $00E1 // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$0B // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + lda #$7F // A = $7F + adc.w $00E1 // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$C8 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + lda #$7F // A = $7F + adc.b $E1 // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$0B // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + lda #$7F // A = $7F + adc.b $E1 // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$C8 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc.w $00E1,x // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$0B // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc.w $00E1,x // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$C8 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + adc $00E1,y // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpx #$0B // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + adc $00E1,y // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpx #$C8 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc.b $E1,x // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$0B // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc.b $E1,x // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$C8 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc ($E2,x) // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$0B // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + adc ($E2,x) // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$C8 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + adc ($E2),y // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass15 + Fail15: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8F // Store Handshake Between CPU<->APU + Fail15Loop: + bra Fail15Loop + Pass15: + cpx #$0B // PSW Result Check + bne Fail15 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0F // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + adc ($E2),y // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass16 + Fail16: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$90 // Store Handshake Between CPU<->APU + Fail16Loop: + bra Fail16Loop + Pass16: + cpx #$C8 // PSW Result Check + bne Fail16 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$10 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store Indirect Data + lda #$7F // A = $7F + ldx #$E1 // X = Indirect Data + adc (x) // A += $81 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass17 + Fail17: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$91 // Store Handshake Between CPU<->APU + Fail17Loop: + bra Fail17Loop + Pass17: + cpx #$0B // PSW Result Check + bne Fail17 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$11 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store Indirect Data + lda #$7F // A = $7F + ldx #$E1 // X = Indirect Data + adc (x) // A += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass18 + Fail18: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$92 // Store Handshake Between CPU<->APU + Fail18Loop: + bra Fail18Loop + Pass18: + cpx #$C8 // PSW Result Check + bne Fail18 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$12 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store Indirect Data + str $E2=#$7F // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + adc (x)=(y) // (X) += (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass19 + Fail19: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$93 // Store Handshake Between CPU<->APU + Fail19Loop: + bra Fail19Loop + Pass19: + cpx #$0B // PSW Result Check + bne Fail19 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$13 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store Indirect Data + str $E2=#$7F // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + adc (x)=(y) // (X) += (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass20 + Fail20: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$94 // Store Handshake Between CPU<->APU + Fail20Loop: + bra Fail20Loop + Pass20: + cpx #$C8 // PSW Result Check + bne Fail20 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$14 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + adc $E1=#$7F // DP += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass21 + Fail21: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$95 // Store Handshake Between CPU<->APU + Fail21Loop: + bra Fail21Loop + Pass21: + cpx #$0B // PSW Result Check + bne Fail21 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$15 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + adc $E1=#$7F // DP += $7F + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass22 + Fail22: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$96 // Store Handshake Between CPU<->APU + Fail22Loop: + bra Fail22Loop + Pass22: + cpx #$C8 // PSW Result Check + bne Fail22 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$16 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$81 // Store DP Data + str $E2=#$7F // Store DP Data + adc $E1=$E2 // DP += DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass23 + Fail23: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$97 // Store Handshake Between CPU<->APU + Fail23Loop: + bra Fail23Loop + Pass23: + cpx #$0B // PSW Result Check + bne Fail23 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$17 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + str $E2=#$7F // Store DP Data + adc $E1=$E2 // DP += DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass24 + Fail24: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$98 // Store Handshake Between CPU<->APU + Fail24Loop: + bra Fail24Loop + Pass24: + cpx #$C8 // PSW Result Check + bne Fail24 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$18 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + ldy #$80 // Y = $80 + lda #$01 // A = $01 + stw $E1 // Store Word Data + ldy #$7F // Y = $7F + lda #$FF // A = $FF + adw $E1 // YA += Word + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldx #$00 // X = $00 + stx.b $E1 // Store Word + stx.b $E2 + cpw $E1 // Result Check + beq Pass25 + Fail25: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$99 // Store Handshake Between CPU<->APU + Fail25Loop: + bra Fail25Loop + Pass25: + ldx.b $E0 // Load PSW Result + cpx #$0B // PSW Result Check + bne Fail25 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$19 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + ldy #$7F // Y = $7F + lda #$FF // A = $FF + stw $E1 // Store Word Data + ldy #$7F // Y = $7F + lda #$FF // A = $FF + adw $E1 // YA += Word + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldx #$FE // X = $FE + stx.b $E1 // Store Word + ldx #$FF // X = $FF + stx.b $E2 + cpw $E1 // Result Check + beq Pass26 + Fail26: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9A // Store Handshake Between CPU<->APU + Fail26Loop: + bra Fail26Loop + Pass26: + ldx.b $E0 // Load PSW Result + cpx #$C8 // PSW Result Check + bne Fail26 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0A00); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0B00) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/make.bat new file mode 100644 index 00000000..e2b1987e --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ADC/make.bat @@ -0,0 +1,2 @@ +bass SPC700ADC_spc.asm +bass SPC700ADC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..ff62ccef --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST AND " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.asm new file mode 100644 index 00000000..921a987c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.asm @@ -0,0 +1,917 @@ +// SNES SPC700 CPU Test AND (AND With Memory) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700AND.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ANDConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait15: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0F + bne Wait15 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8F + bne PASS15 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail15: + bra Fail15 + PASS15: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait16: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$10 + bne Wait16 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$90 + bne PASS16 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail16: + bra Fail16 + PASS16: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait17: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$11 + bne Wait17 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$91 + bne PASS17 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail17: + bra Fail17 + PASS17: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait18: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$12 + bne Wait18 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$92 + bne PASS18 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail18: + bra Fail18 + PASS18: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait19: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$13 + bne Wait19 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDIndirectXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$93 + bne PASS19 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail19: + bra Fail19 + PASS19: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait20: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$14 + bne Wait20 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$94 + bne PASS20 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail20: + bra Fail20 + PASS20: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait21: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$15 + bne Wait21 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$95 + bne PASS21 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail21: + bra Fail21 + PASS21: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait22: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$16 + bne Wait22 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$96 + bne PASS22 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail22: + bra Fail22 + PASS22: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait23: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$17 + bne Wait23 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDDPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$97 + bne PASS23 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail23: + bra Fail23 + PASS23: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait24: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$18 + bne Wait24 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$98 + bne PASS24 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail24: + bra Fail24 + PASS24: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait25: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$19 + bne Wait25 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDAddrBit, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$99 + bne PASS25 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail25: + bra Fail25 + PASS25: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait26: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1A + bne Wait26 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9A + bne PASS26 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail26: + bra Fail26 + PASS26: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait27: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1B + bne Wait27 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ANDNOTAddrBit, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9B + bne PASS27 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail27: + bra Fail27 + PASS27: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait28: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1C + bne Wait28 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9C + bne PASS28 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail28: + bra Fail28 + PASS28: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + +Loop: + jmp Loop + +Title: + db "SPC Test AND (AND With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +ANDConst: + db "AND #const (Opcode: $28)" +ANDAddr: + db "AND addr (Opcode: $25)" +ANDDP: + db "AND dp (Opcode: $24)" +ANDAddrX: + db "AND addr,X (Opcode: $35)" +ANDAddrY: + db "AND addr,Y (Opcode: $36)" +ANDDPX: + db "AND dp,X (Opcode: $34)" +ANDDPIndirectX: + db "AND (dp,X) (Opcode: $27)" +ANDDPIndirectY: + db "AND (dp),Y (Opcode: $37)" +ANDIndirectX: + db "AND (X) (Opcode: $26)" +ANDIndirectXY: + db "AND (X)=(Y) (Opcode: $39)" +ANDDPConst: + db "AND dp=#const(Opcode: $38)" +ANDDPDP: + db "AND dp=dp (Opcode: $29)" +ANDAddrBit: + db "AND addr:bit (Opcode: $4A)" +ANDNOTAddrBit: + db "AND !addr:bit(Opcode: $6A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700AND.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.png new file mode 100644 index 00000000..8db51c0f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.sfc new file mode 100644 index 00000000..2b0efbc8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.spc new file mode 100644 index 00000000..70394260 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND_spc.asm new file mode 100644 index 00000000..602a3ed7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND_spc.asm @@ -0,0 +1,961 @@ +// SNES SPC700 CPU Test AND (AND With Memory) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700AND.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda #$FF // A = $FF + and #$00 // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$02 // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$FF // A = $FF + and #$FF // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$80 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + and.w $00E1 // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$02 // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + and.w $00E1 // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$80 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + and.b $E1 // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$02 // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + and.b $E1 // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$80 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and.w $00E1,x // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$02 // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and.w $00E1,x // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$80 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + and $00E1,y // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpx #$02 // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + and $00E1,y // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpx #$80 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and.b $E1,x // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$02 // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and.b $E1,x // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$80 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and ($E2,x) // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$02 // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + and ($E2,x) // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$80 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + and ($E2),y // A += $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass15 + Fail15: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8F // Store Handshake Between CPU<->APU + Fail15Loop: + bra Fail15Loop + Pass15: + cpx #$02 // PSW Result Check + bne Fail15 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0F // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + and ($E2),y // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass16 + Fail16: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$90 // Store Handshake Between CPU<->APU + Fail16Loop: + bra Fail16Loop + Pass16: + cpx #$80 // PSW Result Check + bne Fail16 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$10 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$E1 // X = Indirect Data + and (x) // A &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass17 + Fail17: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$91 // Store Handshake Between CPU<->APU + Fail17Loop: + bra Fail17Loop + Pass17: + cpx #$02 // PSW Result Check + bne Fail17 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$11 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store Indirect Data + lda #$FF // A = $FF + ldx #$E1 // X = Indirect Data + and (x) // A &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass18 + Fail18: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$92 // Store Handshake Between CPU<->APU + Fail18Loop: + bra Fail18Loop + Pass18: + cpx #$80 // PSW Result Check + bne Fail18 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$12 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + str $E2=#$FF // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + and (x)=(y) // (X) &= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass19 + Fail19: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$93 // Store Handshake Between CPU<->APU + Fail19Loop: + bra Fail19Loop + Pass19: + cpx #$02 // PSW Result Check + bne Fail19 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$13 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store Indirect Data + str $E2=#$FF // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + and (x)=(y) // (X) &= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass20 + Fail20: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$94 // Store Handshake Between CPU<->APU + Fail20Loop: + bra Fail20Loop + Pass20: + cpx #$80 // PSW Result Check + bne Fail20 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$14 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + and $E1=#$FF // DP &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass21 + Fail21: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$95 // Store Handshake Between CPU<->APU + Fail21Loop: + bra Fail21Loop + Pass21: + cpx #$02 // PSW Result Check + bne Fail21 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$15 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + and $E1=#$FF // DP &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass22 + Fail22: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$96 // Store Handshake Between CPU<->APU + Fail22Loop: + bra Fail22Loop + Pass22: + cpx #$80 // PSW Result Check + bne Fail22 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$16 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$FF // Store DP Data + and $E1=$E2 // DP &= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass23 + Fail23: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$97 // Store Handshake Between CPU<->APU + Fail23Loop: + bra Fail23Loop + Pass23: + cpx #$02 // PSW Result Check + bne Fail23 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$17 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$FF // Store DP Data + and $E1=$E2 // DP &= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass24 + Fail24: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$98 // Store Handshake Between CPU<->APU + Fail24Loop: + bra Fail24Loop + Pass24: + cpx #$80 // PSW Result Check + bne Fail24 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$18 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + and $00E1:7 // Carry Flag &= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass25 + Fail25: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$99 // Store Handshake Between CPU<->APU + Fail25Loop: + bra Fail25Loop + Pass25: + cpx #$02 // PSW Result Check + bne Fail25 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$19 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + and $00E1:7 // Carry Flag &= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass26 + Fail26: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9A // Store Handshake Between CPU<->APU + Fail26Loop: + bra Fail26Loop + Pass26: + cpx #$81 // PSW Result Check + bne Fail26 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$00 // A = $00 + and !$00E1:7 // Carry Flag &= !$FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass27 + Fail27: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9B // Store Handshake Between CPU<->APU + Fail27Loop: + bra Fail25Loop + Pass27: + cpx #$02 // PSW Result Check + bne Fail27 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + and !$00E1:7 // Carry Flag &= !$00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass28 + Fail28: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9C // Store Handshake Between CPU<->APU + Fail28Loop: + bra Fail26Loop + Pass28: + cpx #$81 // PSW Result Check + bne Fail28 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0A00); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0B00) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/make.bat new file mode 100644 index 00000000..95cc2b50 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/AND/make.bat @@ -0,0 +1,2 @@ +bass SPC700AND_spc.asm +bass SPC700AND.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b7943413 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST DEC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.asm new file mode 100644 index 00000000..1b61ea22 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.asm @@ -0,0 +1,546 @@ +// SNES SPC700 CPU Test DEC (Decrement) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700DEC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(DECA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(DECW, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "SPC Test DEC (Decrement):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +DECA: + db "DEC A (Opcode: $9C)" +DECAddr: + db "DEC addr (Opcode: $8C)" +DECDP: + db "DEC dp (Opcode: $8B)" +DECDPX: + db "DEC dp,X (Opcode: $9B)" +DECX: + db "DEX (Opcode: $1D)" +DECY: + db "DEY (Opcode: $DC)" +DECW: + db "DEW dp (Opcode: $1A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700DEC.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.png new file mode 100644 index 00000000..ffc93412 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.sfc new file mode 100644 index 00000000..fd9b4530 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.spc new file mode 100644 index 00000000..0084bc72 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC_spc.asm new file mode 100644 index 00000000..420a45dd --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC_spc.asm @@ -0,0 +1,515 @@ +// SNES SPC700 CPU Test DEC (Decrement) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700DEC.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda #$01 // A = $01 + dec // A-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$02 // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$81 // A = $81 + dec // A-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$80 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$01 // Store DP Data + dec.w $00E1 // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$02 // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$81 // Store DP Data + dec.w $00E1 // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$80 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$01 // Store DP Data + dec.b $E1 // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$02 // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$81 // Store DP Data + dec.b $E1 // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$80 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$01 // Store DP Data + ldx #0 // X = 0 + dec $E1,x // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$02 // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$81 // Store DP Data + ldx #0 // X = 0 + dec $E1,x // Memory-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$80 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx #$01 // X = $01 + dex // X-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + ply // Pull Y Register From Stack (Y = Processor Status Flag Data) + sty.b $E0 // Store PSW Result Data + sty.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stx.b $E1 // Store Result Data + stx.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpx #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpy #$02 // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx #$81 // X = $81 + dex // X-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + ply // Pull Y Register From Stack (Y = Processor Status Flag Data) + sty.b $E0 // Store PSW Result Data + sty.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stx.b $E1 // Store Result Data + stx.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpx #$80 // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpy #$80 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$01 // Y = $01 + dey // Y-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sty.b $E1 // Store Result Data + sty.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpy #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$02 // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$81 // Y = $81 + dey // Y-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sty.b $E1 // Store Result Data + sty.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpy #$80 // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpy #$80 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$00 // Y = $00 + lda #$01 // A = $01 + stw $E1 // Store Result Data + dew $E1 // YA-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + ldw $E1 // Load Result + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldy #$00 // Y = $00 + lda #$00 // A = $00 + cpw $E1 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$02 // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$80 // Y = $80 + lda #$01 // A = $01 + stw $E1 // Store Result Data + dew $E1 // YA-- + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + ldw $E1 // Load Result + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldy #$80 // Y = $80 + lda #$00 // A = $00 + cpw $E1 // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$80 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0700); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0800) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/make.bat new file mode 100644 index 00000000..a8ad79fc --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/DEC/make.bat @@ -0,0 +1,2 @@ +bass SPC700DEC_spc.asm +bass SPC700DEC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..839de8fb --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST EOR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.asm new file mode 100644 index 00000000..64105c15 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.asm @@ -0,0 +1,864 @@ +// SNES SPC700 CPU Test EOR (Exclusive-OR With Memory) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700EOR.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(EORConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait15: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0F + bne Wait15 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8F + bne PASS15 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail15: + bra Fail15 + PASS15: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait16: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$10 + bne Wait16 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$90 + bne PASS16 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail16: + bra Fail16 + PASS16: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait17: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$11 + bne Wait17 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$91 + bne PASS17 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail17: + bra Fail17 + PASS17: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait18: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$12 + bne Wait18 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$92 + bne PASS18 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail18: + bra Fail18 + PASS18: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait19: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$13 + bne Wait19 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORIndirectXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$93 + bne PASS19 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail19: + bra Fail19 + PASS19: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait20: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$14 + bne Wait20 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$94 + bne PASS20 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail20: + bra Fail20 + PASS20: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait21: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$15 + bne Wait21 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$95 + bne PASS21 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail21: + bra Fail21 + PASS21: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait22: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$16 + bne Wait22 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$96 + bne PASS22 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail22: + bra Fail22 + PASS22: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait23: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$17 + bne Wait23 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORDPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$97 + bne PASS23 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail23: + bra Fail23 + PASS23: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait24: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$18 + bne Wait24 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$98 + bne PASS24 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail24: + bra Fail24 + PASS24: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait25: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$19 + bne Wait25 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(EORAddrBit, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$99 + bne PASS25 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail25: + bra Fail25 + PASS25: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait26: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1A + bne Wait26 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9A + bne PASS26 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail26: + bra Fail26 + PASS26: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + +Loop: + jmp Loop + +Title: + db "SPC Test EOR (XOR With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +EORConst: + db "EOR #const (Opcode: $48)" +EORAddr: + db "EOR addr (Opcode: $45)" +EORDP: + db "EOR dp (Opcode: $44)" +EORAddrX: + db "EOR addr,X (Opcode: $55)" +EORAddrY: + db "EOR addr,Y (Opcode: $56)" +EORDPX: + db "EOR dp,X (Opcode: $54)" +EORDPIndirectX: + db "EOR (dp,X) (Opcode: $47)" +EORDPIndirectY: + db "EOR (dp),Y (Opcode: $57)" +EORIndirectX: + db "EOR (X) (Opcode: $46)" +EORIndirectXY: + db "EOR (X)=(Y) (Opcode: $59)" +EORDPConst: + db "EOR dp=#const(Opcode: $58)" +EORDPDP: + db "EOR dp=dp (Opcode: $49)" +EORAddrBit: + db "EOR addr:bit (Opcode: $8A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700EOR.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.png new file mode 100644 index 00000000..661c6886 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.sfc new file mode 100644 index 00000000..709e9ee6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.spc new file mode 100644 index 00000000..c2d5b41f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR_spc.asm new file mode 100644 index 00000000..c25d4603 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR_spc.asm @@ -0,0 +1,899 @@ +// SNES SPC700 CPU Test EOR (Exclusive-OR With Memory) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700EOR.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda #$FF // A = $FF + eor #$FF // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$02 // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$FF // A = $FF + eor #$00 // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$80 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + eor.w $00E1 // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$02 // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + eor.w $00E1 // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$80 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + eor.b $E1 // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$02 // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + eor.b $E1 // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$80 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor.w $00E1,x // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$02 // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor.w $00E1,x // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$80 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + eor $00E1,y // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpx #$02 // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + eor $00E1,y // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpx #$80 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor.b $E1,x // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$02 // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor.b $E1,x // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$80 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor ($E2,x) // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$02 // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$00 // X = 0 + eor ($E2,x) // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$80 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + eor ($E2),y // A += $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass15 + Fail15: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8F // Store Handshake Between CPU<->APU + Fail15Loop: + bra Fail15Loop + Pass15: + cpx #$02 // PSW Result Check + bne Fail15 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0F // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldy #$00 // Y = 0 + eor ($E2),y // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass16 + Fail16: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$90 // Store Handshake Between CPU<->APU + Fail16Loop: + bra Fail16Loop + Pass16: + cpx #$80 // PSW Result Check + bne Fail16 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$10 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store Indirect Data + lda #$FF // A = $FF + ldx #$E1 // X = Indirect Data + eor (x) // A ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass17 + Fail17: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$91 // Store Handshake Between CPU<->APU + Fail17Loop: + bra Fail17Loop + Pass17: + cpx #$02 // PSW Result Check + bne Fail17 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$11 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + lda #$FF // A = $FF + ldx #$E1 // X = Indirect Data + eor (x) // A ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass18 + Fail18: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$92 // Store Handshake Between CPU<->APU + Fail18Loop: + bra Fail18Loop + Pass18: + cpx #$80 // PSW Result Check + bne Fail18 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$12 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store Indirect Data + str $E2=#$FF // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + eor (x)=(y) // (X) ^= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass19 + Fail19: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$93 // Store Handshake Between CPU<->APU + Fail19Loop: + bra Fail19Loop + Pass19: + cpx #$02 // PSW Result Check + bne Fail19 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$13 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + str $E2=#$FF // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + eor (x)=(y) // (X) ^= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass20 + Fail20: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$94 // Store Handshake Between CPU<->APU + Fail20Loop: + bra Fail20Loop + Pass20: + cpx #$80 // PSW Result Check + bne Fail20 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$14 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + eor $E1=#$FF // DP ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass21 + Fail21: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$95 // Store Handshake Between CPU<->APU + Fail21Loop: + bra Fail21Loop + Pass21: + cpx #$02 // PSW Result Check + bne Fail21 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$15 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + eor $E1=#$FF // DP ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass22 + Fail22: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$96 // Store Handshake Between CPU<->APU + Fail22Loop: + bra Fail22Loop + Pass22: + cpx #$80 // PSW Result Check + bne Fail22 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$16 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + str $E2=#$FF // Store DP Data + eor $E1=$E2 // DP ^= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass23 + Fail23: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$97 // Store Handshake Between CPU<->APU + Fail23Loop: + bra Fail23Loop + Pass23: + cpx #$02 // PSW Result Check + bne Fail23 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$17 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$FF // Store DP Data + eor $E1=$E2 // DP ^= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass24 + Fail24: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$98 // Store Handshake Between CPU<->APU + Fail24Loop: + bra Fail24Loop + Pass24: + cpx #$80 // PSW Result Check + bne Fail24 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$18 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + eor $00E1:7 // Carry Flag ^= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass25 + Fail25: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$99 // Store Handshake Between CPU<->APU + Fail25Loop: + bra Fail25Loop + Pass25: + cpx #$03 // PSW Result Check + bne Fail25 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$19 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + eor $00E1:7 // Carry Flag ^= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass26 + Fail26: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9A // Store Handshake Between CPU<->APU + Fail26Loop: + bra Fail26Loop + Pass26: + cpx #$80 // PSW Result Check + bne Fail26 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0A00); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0B00) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/make.bat new file mode 100644 index 00000000..dac3c604 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/EOR/make.bat @@ -0,0 +1,2 @@ +bass SPC700EOR_spc.asm +bass SPC700EOR.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..f31bdf22 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST INC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.asm new file mode 100644 index 00000000..0d34c1f0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.asm @@ -0,0 +1,546 @@ +// SNES SPC700 CPU Test INC (Increment) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700INC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 25) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(INCA, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(INCW, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + +Loop: + jmp Loop + +Title: + db "SPC Test INC (Increment):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +INCA: + db "INC A (Opcode: $BC)" +INCAddr: + db "INC addr (Opcode: $AC)" +INCDP: + db "INC dp (Opcode: $AB)" +INCDPX: + db "INC dp,X (Opcode: $BB)" +INCX: + db "INX (Opcode: $3D)" +INCY: + db "INY (Opcode: $FC)" +INCW: + db "INW dp (Opcode: $3A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700INC.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.png new file mode 100644 index 00000000..8a9980b9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.sfc new file mode 100644 index 00000000..33030a68 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.spc new file mode 100644 index 00000000..19d98240 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC_spc.asm new file mode 100644 index 00000000..487b2e36 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC_spc.asm @@ -0,0 +1,515 @@ +// SNES SPC700 CPU Test INC (Increment) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700INC.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda #$FF // A = $FF + inc // A++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$02 // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$7F // A = $7F + inc // A++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$80 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + inc.w $00E1 // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$02 // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$7F // Store DP Data + inc.w $00E1 // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$80 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + inc.b $E1 // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$02 // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$7F // Store DP Data + inc.b $E1 // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$80 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + ldx #0 // X = 0 + inc $E1,x // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$02 // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$7F // Store DP Data + ldx #0 // X = 0 + inc $E1,x // Memory++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$80 // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$80 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx #$FF // X = $FF + inx // X++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + ply // Pull Y Register From Stack (Y = Processor Status Flag Data) + sty.b $E0 // Store PSW Result Data + sty.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stx.b $E1 // Store Result Data + stx.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpx #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpy #$02 // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldx #$7F // X = $7F + inx // X++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + ply // Pull Y Register From Stack (Y = Processor Status Flag Data) + sty.b $E0 // Store PSW Result Data + sty.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stx.b $E1 // Store Result Data + stx.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpx #$80 // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpy #$80 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$FF // Y = $FF + iny // Y++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sty.b $E1 // Store Result Data + sty.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpy #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$02 // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$7F // Y = $7F + iny // Y++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sty.b $E1 // Store Result Data + sty.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cpy #$80 // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$80 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$FF // Y = $FF + lda #$FF // A = $FF + stw $E1 // Store Result Data + inw $E1 // YA++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + ldw $E1 // Load Result + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldy #$00 // Y = $00 + lda #$00 // A = $00 + cpw $E1 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$02 // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + ldy #$7F // Y = $7F + lda #$FF // A = $FF + stw $E1 // Store Result Data + inw $E1 // YA++ + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + ldw $E1 // Load Result + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldy #$80 // Y = $80 + lda #$00 // A = $00 + cpw $E1 // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$80 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0700); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0800) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/make.bat new file mode 100644 index 00000000..1fe7ee34 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/INC/make.bat @@ -0,0 +1,2 @@ +bass SPC700INC_spc.asm +bass SPC700INC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..33258d19 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST ORA " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.asm new file mode 100644 index 00000000..46861e54 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.asm @@ -0,0 +1,917 @@ +// SNES SPC700 CPU Test ORA (OR With Memory) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700ORA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(ORAConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait15: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0F + bne Wait15 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORADPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8F + bne PASS15 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail15: + bra Fail15 + PASS15: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait16: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$10 + bne Wait16 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$90 + bne PASS16 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail16: + bra Fail16 + PASS16: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait17: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$11 + bne Wait17 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORAIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$91 + bne PASS17 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail17: + bra Fail17 + PASS17: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait18: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$12 + bne Wait18 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$92 + bne PASS18 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail18: + bra Fail18 + PASS18: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait19: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$13 + bne Wait19 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORRIndirectXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$93 + bne PASS19 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail19: + bra Fail19 + PASS19: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait20: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$14 + bne Wait20 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$94 + bne PASS20 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail20: + bra Fail20 + PASS20: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait21: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$15 + bne Wait21 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORRDPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$95 + bne PASS21 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail21: + bra Fail21 + PASS21: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait22: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$16 + bne Wait22 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$96 + bne PASS22 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail22: + bra Fail22 + PASS22: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait23: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$17 + bne Wait23 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORRDPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$97 + bne PASS23 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail23: + bra Fail23 + PASS23: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait24: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$18 + bne Wait24 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$98 + bne PASS24 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail24: + bra Fail24 + PASS24: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait25: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$19 + bne Wait25 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORCAddrBit, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$99 + bne PASS25 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail25: + bra Fail25 + PASS25: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait26: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1A + bne Wait26 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9A + bne PASS26 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail26: + bra Fail26 + PASS26: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait27: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1B + bne Wait27 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(ORCNOTAddrBit, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9B + bne PASS27 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail27: + bra Fail27 + PASS27: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait28: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1C + bne Wait28 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9C + bne PASS28 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail28: + bra Fail28 + PASS28: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + +Loop: + jmp Loop + +Title: + db "SPC Test ORA (OR With Memory):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +ORAConst: + db "ORA #const (Opcode: $08)" +ORAAddr: + db "ORA addr (Opcode: $05)" +ORADP: + db "ORA dp (Opcode: $04)" +ORAAddrX: + db "ORA addr,X (Opcode: $15)" +ORAAddrY: + db "ORA addr,Y (Opcode: $16)" +ORADPX: + db "ORA dp,X (Opcode: $14)" +ORADPIndirectX: + db "ORA (dp,X) (Opcode: $07)" +ORADPIndirectY: + db "ORA (dp),Y (Opcode: $17)" +ORAIndirectX: + db "ORA (X) (Opcode: $06)" +ORRIndirectXY: + db "ORR (X)=(Y) (Opcode: $19)" +ORRDPConst: + db "ORR dp=#const(Opcode: $18)" +ORRDPDP: + db "ORR dp=dp (Opcode: $09)" +ORCAddrBit: + db "ORC addr:bit (Opcode: $0A)" +ORCNOTAddrBit: + db "ORC !addr:bit(Opcode: $2A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700ORA.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.png new file mode 100644 index 00000000..bc78927f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.sfc new file mode 100644 index 00000000..7c84253e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.spc new file mode 100644 index 00000000..3f32a155 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA_spc.asm new file mode 100644 index 00000000..86bcf566 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA_spc.asm @@ -0,0 +1,961 @@ +// SNES SPC700 CPU Test ORA (OR With Memory) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700ORA.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + lda #$00 // A = $00 + ora #$00 // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$02 // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$0F // A = $0F + ora #$F0 // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$80 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + ora.w $00E1 // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$02 // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + lda #$0F // A = $0F + ora.w $00E1 // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$80 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + ora.b $E1 // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$02 // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + lda #$0F // A = $0F + ora.b $E1 // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$80 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + ldx #$00 // X = 0 + ora.w $00E1,x // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$02 // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + lda #$0F // A = $0F + ldx #$00 // X = 0 + ora.w $00E1,x // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$80 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + ldy #$00 // Y = 0 + ora $00E1,y // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpx #$02 // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + lda #$0F // A = $0F + ldy #$00 // Y = 0 + ora $00E1,y // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpx #$80 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + ldx #$00 // X = 0 + ora.b $E1,x // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$02 // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + lda #$0F // A = $0F + ldx #$00 // X = 0 + ora.b $E1,x // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$80 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$00 // A = $00 + ldx #$00 // X = 0 + ora ($E2,x) // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$02 // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$0F // A = $0F + ldx #$00 // X = 0 + ora ($E2,x) // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$80 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$00 // A = $00 + ldy #$00 // Y = 0 + ora ($E2),y // A += $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass15 + Fail15: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8F // Store Handshake Between CPU<->APU + Fail15Loop: + bra Fail15Loop + Pass15: + cpx #$02 // PSW Result Check + bne Fail15 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0F // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$0F // A = $0F + ldy #$00 // Y = 0 + ora ($E2),y // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass16 + Fail16: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$90 // Store Handshake Between CPU<->APU + Fail16Loop: + bra Fail16Loop + Pass16: + cpx #$80 // PSW Result Check + bne Fail16 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$10 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + lda #$00 // A = $00 + ldx #$E1 // X = Indirect Data + ora (x) // A |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass17 + Fail17: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$91 // Store Handshake Between CPU<->APU + Fail17Loop: + bra Fail17Loop + Pass17: + cpx #$02 // PSW Result Check + bne Fail17 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$11 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$F0 // Store Indirect Data + lda #$0F // A = $0F + ldx #$E1 // X = Indirect Data + ora (x) // A |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass18 + Fail18: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$92 // Store Handshake Between CPU<->APU + Fail18Loop: + bra Fail18Loop + Pass18: + cpx #$80 // PSW Result Check + bne Fail18 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$12 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store Indirect Data + str $E2=#$00 // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + orr (x)=(y) // (X) |= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass19 + Fail19: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$93 // Store Handshake Between CPU<->APU + Fail19Loop: + bra Fail19Loop + Pass19: + cpx #$02 // PSW Result Check + bne Fail19 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$13 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$0F // Store Indirect Data + str $E2=#$F0 // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + orr (x)=(y) // (X) |= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass20 + Fail20: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$94 // Store Handshake Between CPU<->APU + Fail20Loop: + bra Fail20Loop + Pass20: + cpx #$80 // PSW Result Check + bne Fail20 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$14 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + orr $E1=#$00 // DP |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass21 + Fail21: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$95 // Store Handshake Between CPU<->APU + Fail21Loop: + bra Fail21Loop + Pass21: + cpx #$02 // PSW Result Check + bne Fail21 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$15 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$0F // Store DP Data + orr $E1=#$F0 // DP |= $F0 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass22 + Fail22: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$96 // Store Handshake Between CPU<->APU + Fail22Loop: + bra Fail22Loop + Pass22: + cpx #$80 // PSW Result Check + bne Fail22 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$16 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + str $E2=#$00 // Store DP Data + orr $E1=$E2 // DP |= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass23 + Fail23: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$97 // Store Handshake Between CPU<->APU + Fail23Loop: + bra Fail23Loop + Pass23: + cpx #$02 // PSW Result Check + bne Fail23 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$17 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$0F // Store DP Data + str $E2=#$F0 // Store DP Data + orr $E1=$E2 // DP |= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass24 + Fail24: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$98 // Store Handshake Between CPU<->APU + Fail24Loop: + bra Fail24Loop + Pass24: + cpx #$80 // PSW Result Check + bne Fail24 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$18 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$00 // A = $00 + orc $00E1:7 // Carry Flag |= $00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass25 + Fail25: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$99 // Store Handshake Between CPU<->APU + Fail25Loop: + bra Fail25Loop + Pass25: + cpx #$02 // PSW Result Check + bne Fail25 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$19 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$FF // A = $FF + orc $00E1:7 // Carry Flag |= $FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass26 + Fail26: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9A // Store Handshake Between CPU<->APU + Fail26Loop: + bra Fail26Loop + Pass26: + cpx #$81 // PSW Result Check + bne Fail26 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + clv // Clear Overflow Flag + + // Run Test + str $E1=#$FF // Store DP Data + lda #$00 // A = $00 + orc !$00E1:7 // Carry Flag |= !$FF + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass27 + Fail27: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9B // Store Handshake Between CPU<->APU + Fail27Loop: + bra Fail25Loop + Pass27: + cpx #$02 // PSW Result Check + bne Fail27 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$00 // Store DP Data + lda #$FF // A = $FF + orc !$00E1:7 // Carry Flag |= !$00 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass28 + Fail28: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9C // Store Handshake Between CPU<->APU + Fail28Loop: + bra Fail26Loop + Pass28: + cpx #$81 // PSW Result Check + bne Fail28 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0A00); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0B00) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/make.bat new file mode 100644 index 00000000..473ee27d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/ORA/make.bat @@ -0,0 +1,2 @@ +bass SPC700ORA_spc.asm +bass SPC700ORA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/Font8x8.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..1bce142d --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPC700 CPU TEST SBC " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.asm new file mode 100644 index 00000000..70e7ed54 --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.asm @@ -0,0 +1,864 @@ +// SNES SPC700 CPU Test SBC (Subtract With Borrow) demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SPC700SBC.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +macro PrintText(SRC, DEST, SIZE) { // Print Text Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + ldx.w #0 // X = 0 Number Of Text Characters To Print + {#}LoopText: + lda.w {SRC},x // A = Text Data + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + inx // X++ + cpx.w #{SIZE} + bne {#}LoopText // IF (X != 0) Loop Text Characters +} + +macro PrintValue(SRC, DEST, SIZE) { // Print HEX Characters To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #$24 // A = "$" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + + ldx.w #{SIZE} // X = Number Of Hex Characters To Print + + {#}LoopHEX: + dex // X-- + ldy.w #0002 // Y = 2 (Char Count) + + lda.w {SRC},x // A = Result Data + lsr // A >>= 4 + lsr + lsr + lsr // A = Result Hi Nibble + + {#}LoopChar: + cmp.b #10 // Compare Hi Nibble To 9 + clc // Clear Carry Flag + bpl {#}HexLetter + adc.b #$30 // Add Hi Nibble To ASCII Numbers + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + bra {#}HexEnd + {#}HexLetter: + adc.b #$37 // Add Hi Nibble To ASCII Letters + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + {#}HexEnd: + + lda.w {SRC},x // A = Result Data + and.b #$F // A = Result Lo Nibble + dey // Y-- + bne {#}LoopChar // IF (Char Count != 0) Loop Char + + cpx.w #0 // Compare X To 0 + bne {#}LoopHEX // IF (X != 0) Loop Hex Characters +} + +macro PrintPSW(SRC, DEST) { // Print Processor Status Flags To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM Address + + lda.b #%10000000 // A = Negative Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%01000000 // A = Overflow Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00001000 // A = Half-carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000010 // A = Zero Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + lda.b #%00000001 // A = Carry Flag Bit + jsr {#}PSWFlagTest // Test PSW Flag Data + + bra {#}PSWEnd + + {#}PSWFlagTest: + bit.w {SRC} // Test Processor Status Flag Data Bit + bne {#}PSWFlagSet + lda.b #$30 // A = "0" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + {#}PSWFlagSet: + lda.b #$31 // A = "1" + sta.w REG_VMDATAL // Store Text To VRAM Lo Byte + rts // Return From Subroutine + + {#}PSWEnd: +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + WaitNMI() // Wait For VSync + + // Print Title Text + PrintText(Title, $F882, 31) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F8C2, 30) // Load Text To VRAM Lo Bytes + + // Print Syntax/Opcode Text + PrintText(SBCConst, $F902, 26) // Load Text To VRAM Lo Bytes + + // Print Key Text + PrintText(Key, $F982, 30) // Load Text To VRAM Lo Bytes + + // Print Page Break Text + PrintText(PageBreak, $F9C2, 30) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait1: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$01 + bne Wait1 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$81 + bne PASS1 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail1: + bra Fail1 + PASS1: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait2: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$02 + bne Wait2 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$82 + bne PASS2 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail2: + bra Fail2 + PASS2: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait3: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$03 + bne Wait3 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddr, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$83 + bne PASS3 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail3: + bra Fail3 + PASS3: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait4: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$04 + bne Wait4 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$84 + bne PASS4 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail4: + bra Fail4 + PASS4: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait5: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$05 + bne Wait5 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$85 + bne PASS5 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail5: + bra Fail5 + PASS5: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait6: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$06 + bne Wait6 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$86 + bne PASS6 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail6: + bra Fail6 + PASS6: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait7: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$07 + bne Wait7 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddrX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$87 + bne PASS7 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail7: + bra Fail7 + PASS7: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait8: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$08 + bne Wait8 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$88 + bne PASS8 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail8: + bra Fail8 + PASS8: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait9: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$09 + bne Wait9 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCAddrY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$89 + bne PASS9 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail9: + bra Fail9 + PASS9: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait10: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0A + bne Wait10 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8A + bne PASS10 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail10: + bra Fail10 + PASS10: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait11: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0B + bne Wait11 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8B + bne PASS11 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail11: + bra Fail11 + PASS11: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait12: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0C + bne Wait12 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8C + bne PASS12 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail12: + bra Fail12 + PASS12: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait13: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0D + bne Wait13 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8D + bne PASS13 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail13: + bra Fail13 + PASS13: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait14: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0E + bne Wait14 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8E + bne PASS14 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail14: + bra Fail14 + PASS14: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait15: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$0F + bne Wait15 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPIndirectY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$8F + bne PASS15 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail15: + bra Fail15 + PASS15: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait16: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$10 + bne Wait16 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$90 + bne PASS16 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail16: + bra Fail16 + PASS16: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait17: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$11 + bne Wait17 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCIndirectX, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$91 + bne PASS17 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail17: + bra Fail17 + PASS17: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait18: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$12 + bne Wait18 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$92 + bne PASS18 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail18: + bra Fail18 + PASS18: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait19: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$13 + bne Wait19 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCIndirectXY, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$93 + bne PASS19 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail19: + bra Fail19 + PASS19: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait20: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$14 + bne Wait20 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$94 + bne PASS20 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail20: + bra Fail20 + PASS20: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait21: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$15 + bne Wait21 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPConst, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$95 + bne PASS21 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail21: + bra Fail21 + PASS21: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait22: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$16 + bne Wait22 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$96 + bne PASS22 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail22: + bra Fail22 + PASS22: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait23: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$17 + bne Wait23 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SBCDPDP, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$97 + bne PASS23 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail23: + bra Fail23 + PASS23: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait24: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$18 + bne Wait24 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 1) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$98 + bne PASS24 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail24: + bra Fail24 + PASS24: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + + ///////////////////////////////////////////////////////////////// + Wait25: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$19 + bne Wait25 + WaitNMI() // Wait For VSync + + ClearVRAM(BGCLEAR, $FA00, $80, 0) // Clear VRAM Map To Fixed Tile Word + + WaitNMI() // Wait For VSync + + // Print Syntax/Opcode Text + PrintText(SUBW, $F902, 26) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA10, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA22) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$99 + bne PASS25 + PrintText(Fail, $FA32, 4) // Load Text To VRAM Lo Bytes + Fail25: + bra Fail25 + PASS25: + PrintText(Pass, $FA32, 4) // Load Text To VRAM Lo Bytes + + ///////////////////////////////////////////////////////////////// + Wait26: + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + and.b #$7F + cmp.b #$1A + bne Wait26 + WaitNMI() // Wait For VSync + + // Print Result & Processor Status Flag Data + PrintValue(REG_APUIO2, $FA50, 2) // Print Result Data + PrintPSW(REG_APUIO1, $FA62) // Print Processor Status Flag Data + + lda.w REG_APUIO0 // Load Handshake Between CPU<->APU + cmp.b #$9A + bne PASS26 + PrintText(Fail, $FA72, 4) // Load Text To VRAM Lo Bytes + Fail26: + bra Fail26 + PASS26: + PrintText(Pass, $FA72, 4) // Load Text To VRAM Lo Bytes + + +Loop: + jmp Loop + +Title: + db "SPC Test SBC (Sub With Borrow):" + +PageBreak: + db "------------------------------" + +Key: + db " Result | NVHZC | Test |" +Fail: + db "FAIL" +Pass: + db "PASS" + +SBCConst: + db "SBC #const (Opcode: $A8)" +SBCAddr: + db "SBC addr (Opcode: $A5)" +SBCDP: + db "SBC dp (Opcode: $A4)" +SBCAddrX: + db "SBC addr,X (Opcode: $B5)" +SBCAddrY: + db "SBC addr,Y (Opcode: $B6)" +SBCDPX: + db "SBC dp,X (Opcode: $B4)" +SBCDPIndirectX: + db "SBC (dp,X) (Opcode: $A7)" +SBCDPIndirectY: + db "SBC (dp),Y (Opcode: $B7)" +SBCIndirectX: + db "SBC (X) (Opcode: $A6)" +SBCIndirectXY: + db "SBC (X)=(Y) (Opcode: $B9)" +SBCDPConst: + db "SBC dp=#const(Opcode: $B8)" +SBCDPDP: + db "SBC dp=dp (Opcode: $A9)" +SUBW: + db "SBW dp (Opcode: $9A)" + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $7800, $7FFF // Blue / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word + +// SPC Code +// BANK 0 +insert SPCROM, "SPC700SBC.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.png b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.png new file mode 100644 index 00000000..d7611fcd Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.png differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.sfc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.sfc new file mode 100644 index 00000000..a2be7564 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.sfc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.spc new file mode 100644 index 00000000..8081040e Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC_spc.asm b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC_spc.asm new file mode 100644 index 00000000..ef20c7fd --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC_spc.asm @@ -0,0 +1,900 @@ +// SNES SPC700 CPU Test SBC (Subtract With Borrow) demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SPC700SBC.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1PITCHL,$00) // Voice 1: Pitch (Lower Byte) + WDSP(DSP_V1PITCHH,$08) // Voice 1: Pitch (Upper Byte) + WDSP(DSP_V1SRCN,0) // Voice 1: Sample + WDSP(DSP_V1ADSR1,%11111010) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,%11100000) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + +SongStart: + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + lda #$7F // A = $7F + sbc #$7E // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass1 + Fail1: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$81 // Store Handshake Between CPU<->APU + Fail1Loop: + bra Fail1Loop + Pass1: + cpx #$0B // PSW Result Check + bne Fail1 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$01 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + lda #$7F // A = $7F + sbc #$80 // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b $E1 // Store Result Data + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass2 + Fail2: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$82 // Store Handshake Between CPU<->APU + Fail2Loop: + bra Fail2Loop + Pass2: + cpx #$C8 // PSW Result Check + bne Fail2 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$02 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + lda #$7F // A = $7F + sbc.w $00E1 // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass3 + Fail3: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$83 // Store Handshake Between CPU<->APU + Fail3Loop: + bra Fail3Loop + Pass3: + cpx #$0B // PSW Result Check + bne Fail3 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$03 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + lda #$7F // A = $7F + sbc.w $00E1 // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass4 + Fail4: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$84 // Store Handshake Between CPU<->APU + Fail4Loop: + bra Fail4Loop + Pass4: + cpx #$C8 // PSW Result Check + bne Fail4 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$04 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + lda #$7F // A = $7F + sbc.b $E1 // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass5 + Fail5: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$85 // Store Handshake Between CPU<->APU + Fail5Loop: + bra Fail5Loop + Pass5: + cpx #$0B // PSW Result Check + bne Fail5 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$05 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + lda #$7F // A = $7F + sbc.b $E1 // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass6 + Fail6: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$86 // Store Handshake Between CPU<->APU + Fail6Loop: + bra Fail6Loop + Pass6: + cpx #$C8 // PSW Result Check + bne Fail6 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$06 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc.w $00E1,x // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass7 + Fail7: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$87 // Store Handshake Between CPU<->APU + Fail7Loop: + bra Fail7Loop + Pass7: + cpx #$0B // PSW Result Check + bne Fail7 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$07 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc.w $00E1,x // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass8 + Fail8: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$88 // Store Handshake Between CPU<->APU + Fail8Loop: + bra Fail8Loop + Pass8: + cpx #$C8 // PSW Result Check + bne Fail8 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$08 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + sbc $00E1,y // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass9 + Fail9: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$89 // Store Handshake Between CPU<->APU + Fail9Loop: + bra Fail9Loop + Pass9: + cpx #$0B // PSW Result Check + bne Fail9 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$09 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + sbc $00E1,y // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass10 + Fail10: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8A // Store Handshake Between CPU<->APU + Fail10Loop: + bra Fail10Loop + Pass10: + cpx #$C8 // PSW Result Check + bne Fail10 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc.b $E1,x // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass11 + Fail11: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8B // Store Handshake Between CPU<->APU + Fail11Loop: + bra Fail11Loop + Pass11: + cpx #$0B // PSW Result Check + bne Fail11 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0B // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc.b $E1,x // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass12 + Fail12: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8C // Store Handshake Between CPU<->APU + Fail12Loop: + bra Fail12Loop + Pass12: + cpx #$C8 // PSW Result Check + bne Fail12 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0C // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc ($E2,x) // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass13 + Fail13: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8D // Store Handshake Between CPU<->APU + Fail13Loop: + bra Fail13Loop + Pass13: + cpx #$0B // PSW Result Check + bne Fail13 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0D // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldx #$00 // X = 0 + sbc ($E2,x) // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass14 + Fail14: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8E // Store Handshake Between CPU<->APU + Fail14Loop: + bra Fail14Loop + Pass14: + cpx #$C8 // PSW Result Check + bne Fail14 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0E // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + sbc ($E2),y // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass15 + Fail15: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$8F // Store Handshake Between CPU<->APU + Fail15Loop: + bra Fail15Loop + Pass15: + cpx #$0B // PSW Result Check + bne Fail15 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$0F // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store DP Data + str $E2=#$E1 // Store Indirect Data + str $E3=#$00 // Store Indirect Data + lda #$7F // A = $7F + ldy #$00 // Y = 0 + sbc ($E2),y // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass16 + Fail16: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$90 // Store Handshake Between CPU<->APU + Fail16Loop: + bra Fail16Loop + Pass16: + cpx #$C8 // PSW Result Check + bne Fail16 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$10 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7E // Store Indirect Data + lda #$7F // A = $7F + ldx #$E1 // X = Indirect Data + sbc (x) // A -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass17 + Fail17: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$91 // Store Handshake Between CPU<->APU + Fail17Loop: + bra Fail17Loop + Pass17: + cpx #$0B // PSW Result Check + bne Fail17 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$11 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$80 // Store Indirect Data + lda #$7F // A = $7F + ldx #$E1 // X = Indirect Data + sbc (x) // A -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass18 + Fail18: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$92 // Store Handshake Between CPU<->APU + Fail18Loop: + bra Fail18Loop + Pass18: + cpx #$C8 // PSW Result Check + bne Fail18 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$12 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7F // Store Indirect Data + str $E2=#$7E // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + sbc (x)=(y) // (X) -= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass19 + Fail19: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$93 // Store Handshake Between CPU<->APU + Fail19Loop: + bra Fail19Loop + Pass19: + cpx #$0B // PSW Result Check + bne Fail19 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$13 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store Indirect Data + str $E2=#$80 // Store Indirect Data + ldx #$E1 // X = Indirect Data + ldy #$E2 // Y = Indirect Data + sbc (x)=(y) // (X) -= (Y) + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass20 + Fail20: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$94 // Store Handshake Between CPU<->APU + Fail20Loop: + bra Fail20Loop + Pass20: + cpx #$C8 // PSW Result Check + bne Fail20 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$14 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + sbc $E1=#$7E // DP -= $7E + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass21 + Fail21: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$95 // Store Handshake Between CPU<->APU + Fail21Loop: + bra Fail21Loop + Pass21: + cpx #$0B // PSW Result Check + bne Fail21 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$15 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + sbc $E1=#$80 // DP -= $80 + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass22 + Fail22: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$96 // Store Handshake Between CPU<->APU + Fail22Loop: + bra Fail22Loop + Pass22: + cpx #$C8 // PSW Result Check + bne Fail22 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$16 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + str $E2=#$7E // Store DP Data + sbc $E1=$E2 // DP -= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$00 // Result Check + beq Pass23 + Fail23: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$97 // Store Handshake Between CPU<->APU + Fail23Loop: + bra Fail23Loop + Pass23: + cpx #$0B // PSW Result Check + bne Fail23 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$17 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + str $E1=#$7F // Store DP Data + str $E2=#$80 // Store DP Data + sbc $E1=$E2 // DP -= DP + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + lda.b $E1 // Load Result + sta.b REG_CPUIO2 // Store Handshake Between CPU<->APU + cmp #$FF // Result Check + beq Pass24 + Fail24: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$98 // Store Handshake Between CPU<->APU + Fail24Loop: + bra Fail24Loop + Pass24: + cpx #$C8 // PSW Result Check + bne Fail24 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$18 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + + ///////////////////////////////////////////////////////////////// + // Setup Flags + clc // Clear Carry Flag + + // Run Test + ldy #$7F // Y = $7F + lda #$FF // A = $FF + stw $E1 // Store Word Data + ldy #$7F // Y = $7F + lda #$FF // A = $FF + sbw $E1 // YA -= Word + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldx #$00 // X = $00 + stx.b $E1 // Store Word + stx.b $E2 + cpw $E1 // Result Check + beq Pass25 + Fail25: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$99 // Store Handshake Between CPU<->APU + Fail25Loop: + bra Fail25Loop + Pass25: + ldx.b $E0 // Load PSW Result + cpx #$0B // PSW Result Check + bne Fail25 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$19 // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + ///////////////////////////////////////////////////////////////// + // Setup Flags + sec // Set Carry Flag + + // Run Test + ldy #$80 // Y = $80 + lda #$00 // A = $00 + stw $E1 // Store Word Data + ldy #$7F // Y = $7F + lda #$FF // A = $FF + sbw $E1 // YA -= Word + php // Push Processor Status Register To Stack + + // Check Result & Processor Status Flag Data + plx // Pull X Register From Stack (X = Processor Status Flag Data) + stx.b $E0 // Store PSW Result Data + stx.b REG_CPUIO1 // Store Handshake Between CPU<->APU + stw REG_CPUIO2 // Store Handshake Between CPU<->APU + ldx #$FF // X = $FE + stx.b $E1 // Store Word + stx.b $E2 + cpw $E1 // Result Check + beq Pass26 + Fail26: + WDSP(DSP_KON,%00000010) // Play Voice 1 (FAIL) + str REG_CPUIO0=#$9A // Store Handshake Between CPU<->APU + Fail26Loop: + bra Fail26Loop + Pass26: + ldx.b $E0 // Load PSW Result + cpx #$C8 // PSW Result Check + bne Fail26 + WDSP(DSP_KON,%00000001) // Play Voice 0 (PASS) + str REG_CPUIO0=#$1A // Store Handshake Between CPU<->APU + + SPCWaitSHIFTMS(256, 2) // Wait For Shifted MilliSecond Amount (8kHz Timer) + + +Loop: + jmp Loop + +seek($0A00); sampleDIR: + dw BRRSample, 0 // BRR Sample Offset, Loop Point + +seek($0B00) // Sample Data + insert BRRSample, "airhorn.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/airhorn.brr b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/airhorn.brr new file mode 100644 index 00000000..482cf99f Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/airhorn.brr differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/make.bat b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/make.bat new file mode 100644 index 00000000..bc708e4b --- /dev/null +++ b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SBC/make.bat @@ -0,0 +1,2 @@ +bass SPC700SBC_spc.asm +bass SPC700SBC.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ADC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ADC.spc new file mode 100644 index 00000000..e95fd129 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ADC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700AND.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700AND.spc new file mode 100644 index 00000000..2d288d58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700AND.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700DEC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700DEC.spc new file mode 100644 index 00000000..0bab1a81 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700DEC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700EOR.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700EOR.spc new file mode 100644 index 00000000..7ce9fc8c Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700EOR.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700INC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700INC.spc new file mode 100644 index 00000000..c3d93d52 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700INC.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ORA.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ORA.spc new file mode 100644 index 00000000..d3126eb8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700ORA.spc differ diff --git a/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700SBC.spc b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700SBC.spc new file mode 100644 index 00000000..08e354ba Binary files /dev/null and b/roms/snes/peter-lemon-snes/CPUTest/SPC700/SPC700SBC.spc differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.pal b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.pal new file mode 100644 index 00000000..8b995080 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.png b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.png new file mode 100644 index 00000000..5ace7a4b Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGMAP.lz b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGMAP.lz new file mode 100644 index 00000000..af033588 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGMAP.lz differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGPIC.lz b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGPIC.lz new file mode 100644 index 00000000..c9766629 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/GFX/BGPIC.lz differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES.INC b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..00ece233 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "LZ77 WRAM GFX " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.asm b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.asm new file mode 100644 index 00000000..8ef0e0dd --- /dev/null +++ b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.asm @@ -0,0 +1,168 @@ +// SNES LZ77 WRAM GFX Demo by krom (Peter Lemon): +arch snes.cpu +output "LZ77WRAMGFX.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +constant LZOUT($7F0000) // LZ Output WRAM Offset (2nd Bank) + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +LZFlagData: + db 0 // LZ Flag Data Byte +LZBlockShift: + db 0 // LZ Block Type Shifter Byte +LZNBDMSB: + db 0 // LZ Number Of Bytes To Copy & Disp MSB's Byte +LZDLSB: + db 0 // LZ Disp LSB's Byte +LZDMSB: + db 0 // LZ Disp MSB's Byte +LZNB: + db 0 // LZ Number Of Bytes To Copy Byte +LZDISP: + dl 0 // LZ Disp Offset Long +LZDEST: + dl 0 // LZ Destination Offset Long +LZSRC: + dl 0 // LZ Source Offset Long +LZSIZE: + dw 0 // LZ Data Byte Size Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + + ldx.w #BGTiles // LZ Source ROM Offset + stx.b LZSRC // Store LZ Source ROM Offset + lda.b #BGTiles >> 16 // A = LZ Source ROM Bank + sta.b LZSRC+2 // Store LZ Source ROM Bank + ldx.w #BGTiles.size // LZ Data Byte Size + stx.b LZSIZE // Store LZ Data Byte Size + jsl LZDecompress // Decompress LZ Data + LoadVRAM(LZOUT, $0000, $40C0, 0) // Load Background Tiles To VRAM + + ldx.w #BGMap // LZ Source ROM Offset + stx.b LZSRC // Store LZ Source ROM Offset + lda.b #BGMap >> 16 // A = LZ Source ROM Bank + sta.b LZSRC+2 // Store LZ Source ROM Bank + ldx.w #BGMap.size // LZ Data Byte Size + stx.b LZSIZE // Store LZ Data Byte Size + jsl LZDecompress // Decompress LZ Data + LoadVRAM(LZOUT, $F200, $0E00, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Scroll Vertical Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Scroll Vertical Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +LZDecompress: // Decompress LZ77/LZSS Data (LZSRC & LZSIZE Required, Maximum 65536 Bytes Output) + ldx.w #LZOUT // LZ Destination WRAM Offset + stx.b LZDEST // Store LZ Destination WRAM Offset + lda.b #LZOUT >> 16 // A = LZ Destination WRAM Bank + sta.b LZDEST+2 // Store LZ Destination WRAM Bank + sta.b LZDISP+2 // Store LZ Disp WRAM Bank + + ldy.w #$0004 // Y = LZ Source Offset Index (Skip LZ Header) + + LZLoop: + lda [LZSRC],y // A = Flag Data For Next 8 Blocks (0 = Uncompressed Byte, 1 = Compressed Bytes) + iny // Add 1 To LZ Source Offset Index + sta.b LZFlagData // Store Flag Data + lda.b #%10000000 // A = Flag Data Block Type Shifter + sta.b LZBlockShift // Store Block Type Shifter + LZBlockLoop: + cpy.b LZSIZE // IF (Source Offset Index == Source End Offset) LZEnd + beq LZEnd + lda.b LZBlockShift // A = Flag Data Block Type Shifter + beq LZLoop // IF (Flag Data Block Type Shifter == 0) LZLoop + lsr LZBlockShift // Shift To Next Flag Data Block Type + bit.b LZFlagData // Test Block Type + bne LZDecode // IF (BlockType != 0) LZDecode Bytes + lda [LZSRC],y // ELSE Copy Uncompressed Byte + iny // Add 1 To LZ Source Offset Index + sta [LZDEST] // Store Uncompressed Byte To Destination + ldx.b LZDEST // X = LZ Destination Offset + inx // Add 1 To LZ Destination Offset + stx.b LZDEST // LZ Destination Offset = X + bra LZBlockLoop // Loop LZ Blocks + + LZDecode: + lda [LZSRC],y // A = Number Of Bytes To Copy & Disp MSB's + iny // Add 1 To LZ Source Offset Index + sta.b LZNBDMSB // Store Number Of Bytes To Copy & Disp MSB's + and.b #$F // A = Disp MSB's + sta.b LZDMSB // Store Disp MSB's + lda [LZSRC],y // A = Disp LSB's + iny // Add 1 To LZ Source Offset Index + sta.b LZDLSB // Store Disp LSB's + lda.b LZNBDMSB // A = Number Of Bytes To Copy & Disp MSB's + lsr // A >>= 4 + lsr + lsr + lsr // A = Number Of Bytes To Copy (Minus 3) + clc // Clear Carry Flag + adc.b #3 // A = Number Of Bytes To Copy + sta.b LZNB // Store Number Of Bytes To Copy + ldx.b LZDLSB // X = Disp + inx // X = Disp + 1 + stx.b LZDISP // Store Disp + rep #$20 // Set 16-Bit Accumulator + lda.b LZDEST // A = LZ Destination Offset + sec // Set Carry Flag + sbc.b LZDISP // A = Destination - Disp - 1 (LZ Disp Offset) + sta.b LZDISP // Store LZ Disp Offset + sep #$20 // Set 8-Bit Accumulator + LZCopy: + lda [LZDISP] // A = Byte To Copy + ldx.b LZDISP // X = LZ Disp Offset + inx // Add 1 To LZ Disp Offset + stx.b LZDISP // LZ Disp Offset = X + sta [LZDEST] // Store Uncompressed Byte To Destination + ldx.b LZDEST // X = LZ Destination Offset + inx // Add 1 To LZ Destination Offset + stx.b LZDEST // LZ Destination Offset = X + dec LZNB // Decrement Number Of Bytes To Copy + bne LZCopy // IF (Number Of Bytes To Copy != 0) LZCopy + bra LZBlockLoop // Loop LZ Blocks + LZEnd: + rtl // Return From Subroutine + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BGMAP.lz" // Include LZ Compressed BG Map Data (971 Bytes) +insert BGTiles, "GFX/BGPIC.lz" // Include LZ Compressed BG Tile Data (6871 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.png b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.png new file mode 100644 index 00000000..3400669a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.png differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.sfc b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.sfc new file mode 100644 index 00000000..ce536fd1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.sfc differ diff --git a/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/make.bat b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/make.bat new file mode 100644 index 00000000..0ed2390d --- /dev/null +++ b/roms/snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/make.bat @@ -0,0 +1 @@ +bass LZ77WRAMGFX.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CharacterSelect.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CharacterSelect.asm new file mode 100644 index 00000000..dbd669c7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CharacterSelect.asm @@ -0,0 +1,709 @@ +//----------------- +// Character Select +//----------------- +LoadVRAM(CharacterSelectDarkBlendTiles, $8000, CharacterSelectDarkBlendTiles.size, 0) // Load Background Tiles To VRAM +LoadVRAM(CharacterSelectDarkBlendMap, $8900, CharacterSelectDarkBlendMap.size, 0) // Load Background Tile Map To VRAM + +LoadPAL(CharacterSelectPal, $80, CharacterSelectPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterSelectTiles, $C000, CharacterSelectTiles.size, 0) // Load Sprite Tiles To VRAM + +//LoadPAL(CharacterRoochoDarkPal, $90, CharacterRoochoDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadPAL(CharacterRoochoPal, $90, CharacterRoochoPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterRoochoTiles, $E000, CharacterRoochoTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CharacterBeochiDarkPal, $A0, CharacterBeochiDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +//LoadPAL(CharacterBeochiPal, $A0, CharacterBeochiPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterBeochiTiles, $E800, CharacterBeochiTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CharacterChitoDarkPal, $B0, CharacterChitoDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +//LoadPAL(CharacterChitoPal, $B0, CharacterChitoPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterChitoTiles, $F000, CharacterChitoTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CharacterGolemDarkPal, $C0, CharacterGolemDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +//LoadPAL(CharacterGolemPal, $C0, CharacterGolemPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterGolemTiles, $F800, CharacterGolemTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CharacterArrowPal, $D0, CharacterArrowPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CharacterArrowTiles, $D800, CourseBorderTiles.size, 0) // Load Sprite Tiles To VRAM + +// Clear OAM +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0080 +lda.b #$E0 +- + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + +ldx.w #$0020 +- + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + +// Character Select OAM Info +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCharacterSelectOAM: + lda.w CharacterSelectOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0140 + bne LoopCharacterSelectOAM + +// Character Select OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCharacterSelectOAMSize: + lda.w CharacterSelectOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0154 + bne LoopCharacterSelectOAMSize + +// Setup Video +lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 & BG2 8x8 Tiles + +// Setup BG1 256 Color Background +lda.b #%01000100 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $8900 (VRAM Address / $400) + +// Setup BG2 16 Color Background +lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + +lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address +sta.w REG_BG12NBA // $210B: BG1 Tile Address = $8000, BG2 Tile Address = $0000 (VRAM Address / $1000) + +lda.b #%00010010 // Enable BG2 & Sprites +sta.w REG_TM // $212C: BG2 & Sprites To Main Screen Designation + +lda.b #%00000001 // Enable BG1 +sta.w REG_TS // $212D: BG1 To Sub Screen Designation + +lda.b #%00000010 // Enable Subscreen BG/OBJ Color ADD/SUB +sta.w REG_CGWSEL // $2130: Color Math Control Register A + +lda.b #%01100010 // Colour Addition On BG2 And Backdrop Colour (Half Result) +sta.w REG_CGADSUB // $2131: Color Math Control Register B + +stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte +stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + +lda.b #31 // Scroll BG1 & BG2 31 Pixels Up +sta.w REG_BG1VOFS // Store A To BG1 Vertical Scroll Position Lo Byte +stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte +sta.w REG_BG2VOFS // Store A To BG Scroll Position Low Byte +stz.w REG_BG2VOFS // Store Zero To BG Scroll Position High Byte + +// HDMA OAM Size & Object Base +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters +lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) +sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #CharacterSelectHDMATableOAM // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address +lda.b #CharacterSelectHDMATableOAM >> 16 // HDMA Table Bank +sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) +lda.b #%00000001 // HDMA Channel Select (Channel 0) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +FadeIN() // Screen Fade In + +CharacterRoocho: + WaitNMI() // Wait VBlank + LoadPAL(CharacterRoochoPal, $90, CharacterRoochoPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Character Roocho Text OAM Info + ldx.w #$0080 // X = $0080 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCharacterRoochoTextOAM: + lda.w CharacterRoochoTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0040 + bne LoopCharacterRoochoTextOAM + + lda.b #15 + CharacterRoochoWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CharacterRoochoWait + + ldy.w #$2D4A // Y = Border Color + + CharacterRoochoLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CharacterRoochoRight // IF (! LEFT Pressed) GOTO Character Roocho Right + LoadPAL(CharacterRoochoDarkPal, $90, CharacterRoochoDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterGolem // ELSE GOTO Character Golem + CharacterRoochoRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CharacterRoochoStart // IF (! RIGHT Pressed) GOTO Character Roocho Up + LoadPAL(CharacterRoochoDarkPal, $90, CharacterRoochoDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterBeochi // ELSE GOTO Character Beochi + CharacterRoochoStart: + ReadJOY({JOY_START}) // Test START Button + beq CharacterRoochoEnd // IF (! START Pressed) GOTO Character Roocho End + lda.b #%00010000 // A = Character Select Roocho Flag + tsb.b CourseCharacterSelect // Store Character Selection + jmp CharacterSelectEnd // ELSE GOTO Character Select End + CharacterRoochoEnd: + + lda.b #$91 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0111110000000000 + cmp.w #%0111110000000000 + beq RoochoBorderDecrementFlag + cmp.w #%0001000000000000 + beq RoochoBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq RoochoBorderIncrement + bne RoochoBorderDecrement + + RoochoBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra RoochoBorderIncrement + + RoochoBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra RoochoBorderDecrement + + RoochoBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra RoochoBorderEnd + + RoochoBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + RoochoBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CharacterRoochoLeft // GOTO Character Roocho Left + +CharacterBeochi: + WaitNMI() // Wait VBlank + LoadPAL(CharacterBeochiPal, $A0, CharacterBeochiPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Character Beochi Text OAM Info + ldx.w #$0080 // X = $0080 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCharacterBeochiTextOAM: + lda.w CharacterBeochiTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0040 + bne LoopCharacterBeochiTextOAM + + lda.b #15 + CharacterBeochiWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CharacterBeochiWait + + ldy.w #$2D4A // Y = Border Color + + CharacterBeochiLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CharacterBeochiRight // IF (! LEFT Pressed) GOTO Character Beochi Right + LoadPAL(CharacterBeochiDarkPal, $A0, CharacterBeochiDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterRoocho // ELSE GOTO Character Roocho + CharacterBeochiRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CharacterBeochiStart // IF (! RIGHT Pressed) GOTO Character Beochi Up + LoadPAL(CharacterBeochiDarkPal, $A0, CharacterBeochiDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterChito // ELSE GOTO Character Chito + CharacterBeochiStart: + ReadJOY({JOY_START}) // Test START Button + beq CharacterBeochiEnd // IF (! START Pressed) GOTO Character Beochi End + lda.b #%00100000 // A = Character Select Beochi Flag + tsb.b CourseCharacterSelect // Store Character Selection + jmp CharacterSelectEnd // ELSE GOTO Character Select End + CharacterBeochiEnd: + + lda.b #$A1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0111110000000000 + cmp.w #%0111110000000000 + beq BeochiBorderDecrementFlag + cmp.w #%0001000000000000 + beq BeochiBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq BeochiBorderIncrement + bne BeochiBorderDecrement + + BeochiBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra BeochiBorderIncrement + + BeochiBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra BeochiBorderDecrement + + BeochiBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra BeochiBorderEnd + + BeochiBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + BeochiBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CharacterBeochiLeft // GOTO Character Beochi Left + +CharacterChito: + WaitNMI() // Wait VBlank + LoadPAL(CharacterChitoPal, $B0, CharacterChitoPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Character Chito Text OAM Info + ldx.w #$0080 // X = $0080 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCharacterChitoTextOAM: + lda.w CharacterChitoTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0040 + bne LoopCharacterChitoTextOAM + + lda.b #15 + CharacterChitoWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CharacterChitoWait + + ldy.w #$2D4A // Y = Border Color + + CharacterChitoLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CharacterChitoRight // IF (! LEFT Pressed) GOTO Character Chito Right + LoadPAL(CharacterChitoDarkPal, $B0, CharacterChitoDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterBeochi // ELSE GOTO Character Beochi + CharacterChitoRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CharacterChitoStart // IF (! RIGHT Pressed) GOTO Character Chito Up + LoadPAL(CharacterChitoDarkPal, $B0, CharacterChitoDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterGolem // ELSE GOTO Character Golem + CharacterChitoStart: + ReadJOY({JOY_START}) // Test START Button + beq CharacterChitoEnd // IF (! START Pressed) GOTO Character Chito End + lda.b #%01000000 // A = Character Select Chito Flag + tsb.b CourseCharacterSelect // Store Character Selection + jmp CharacterSelectEnd // ELSE GOTO Character Select End + CharacterChitoEnd: + + lda.b #$B1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0111110000000000 + cmp.w #%0111110000000000 + beq ChitoBorderDecrementFlag + cmp.w #%0001000000000000 + beq ChitoBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq ChitoBorderIncrement + bne ChitoBorderDecrement + + ChitoBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra ChitoBorderIncrement + + ChitoBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra ChitoBorderDecrement + + ChitoBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra ChitoBorderEnd + + ChitoBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + ChitoBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CharacterChitoLeft // GOTO Character Chito Left + +CharacterGolem: + WaitNMI() // Wait VBlank + LoadPAL(CharacterGolemPal, $C0, CharacterGolemPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Character Golem Text OAM Info + ldx.w #$0080 // X = $0080 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCharacterGolemTextOAM: + lda.w CharacterGolemTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0040 + bne LoopCharacterGolemTextOAM + + lda.b #15 + CharacterGolemWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CharacterGolemWait + + ldy.w #$2D4A // Y = Border Color + + CharacterGolemLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CharacterGolemRight // IF (! LEFT Pressed) GOTO Character Golem Right + LoadPAL(CharacterGolemDarkPal, $C0, CharacterGolemDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterChito // ELSE GOTO Character Chito + CharacterGolemRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CharacterGolemStart // IF (! RIGHT Pressed) GOTO Character Chito Up + LoadPAL(CharacterGolemDarkPal, $C0, CharacterGolemDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CharacterRoocho // ELSE GOTO Character Roocho + CharacterGolemStart: + ReadJOY({JOY_START}) // Test START Button + beq CharacterGolemEnd // IF (! START Pressed) GOTO Character Golem End + lda.b #%10000000 // A = Character Select Golem Flag + tsb.b CourseCharacterSelect // Store Character Selection + jmp CharacterSelectEnd // ELSE GOTO Character Select End + CharacterGolemEnd: + + lda.b #$C1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0111110000000000 + cmp.w #%0111110000000000 + beq GolemBorderDecrementFlag + cmp.w #%0001000000000000 + beq GolemBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq GolemBorderIncrement + bne GolemBorderDecrement + + GolemBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra GolemBorderIncrement + + GolemBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra GolemBorderDecrement + + GolemBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra GolemBorderEnd + + GolemBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + GolemBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CharacterGolemLeft // GOTO Character Golem Left + +CharacterSelectHDMATableOAM: + db 124, %01100011 // Repeat 124 Scanlines, Object Size = 16x16/32x32, Name = 0, Base = $C000 + db 1, %00000010 // Repeat 1 Scanlines, Object Size = 8x8/16x16, Name = 0, Base = $8000 + db 0 // End Of HDMA + +CharacterSelectOAM: + // 16x16 / 32x32 Sprites + // OAM Info (Character Select 200x48) + db 28, 3, 0, %00000000 + db 60, 3, 4, %00000000 + db 92, 3, 8, %00000000 + db 124, 3, 12, %00000000 + db 156, 3, 96, %00000000 + db 188, 3, 100, %00000000 + db 220, 3, 104, %00000000 + + db 28, 35, 64, %00000000 + db 44, 35, 66, %00000000 + db 60, 35, 68, %00000000 + db 76, 35, 70, %00000000 + db 92, 35, 72, %00000000 + db 108, 35, 74, %00000000 + db 124, 35, 76, %00000000 + db 140, 35, 78, %00000000 + db 156, 35, 160, %00000000 + db 172, 35, 162, %00000000 + db 188, 35, 164, %00000000 + db 204, 35, 166, %00000000 + db 220, 35, 168, %00000000 + db 236, 35, 170, %00000000 + + // OAM Info (Character Roocho 48x64) + db 32, 54, 0, %00000011 + db 32, 86, 6, %00000011 + + db 64, 54, 4, %00000011 + db 64, 70, 36, %00000011 + db 64, 86, 10, %00000011 + db 64, 102, 42, %00000011 + + // OAM Info (Character Beochi 48x64) + db 80, 54, 64, %00000101 + db 80, 86, 70, %00000101 + + db 112, 54, 68, %00000101 + db 112, 70, 100, %00000101 + db 112, 86, 74, %00000101 + db 112, 102, 106, %00000101 + + // OAM Info (Character Chito 48x64) + db 128, 54, 128, %00000111 + db 128, 86, 134, %00000111 + + db 160, 54, 132, %00000111 + db 160, 70, 164, %00000111 + db 160, 86, 138, %00000111 + db 160, 102, 170, %00000111 + + // OAM Info (Character Golem 48x64) + db 176, 54, 192, %00001001 + db 176, 86, 198, %00001001 + + db 208, 54, 196, %00001001 + db 208, 70, 228, %00001001 + db 208, 86, 202, %00001001 + db 208, 102, 234, %00001001 + + // OAM Info (Character Arrow 16x16) + db 16, 78, 192, %00001010 + db 224, 78, 192, %01001010 + + map 'a', $00, 26 + map $22, $1A // Double Quote '"' + map '#', $1B + map '$', $1C + map '%', $1D + map '&', $1E + map $27, $1F // Single Quote "'" + map '*', $20 + map '@', $21 + map '/', $22 + map '_', $23 + map $3B, $24 // Semicolon ";" + map ' ', $25 + + map 'A', $80, 26 + map '-', $9A + map '+', $9B + map '0', $9C, 10 + map '!', $A6 + map '(', $A7 + map ')', $A8 + map $2C, $A9 // Comma "," + map '.', $AA + map ':', $AB + map '=', $AC + map '?', $AD + map '`', $AE + + // 8x8 / 16x16 Sprites + // OAM Info (Character Speed Text) + db 85, 142, "S", %00001111 + db 92, 142, "P", %00001111 + db 100, 142, "E", %00001111 + db 108, 142, "E", %00001111 + db 116, 142, "D", %00001111 + db 129, 142, ":", %00001111 + + // OAM Info (Character Accel Text) + db 86, 154, "A", %00001111 + db 94, 154, "C", %00001111 + db 101, 154, "C", %00001111 + db 108, 154, "E", %00001111 + db 116, 154, "L", %00001111 + db 129, 154, ":", %00001111 + + // OAM Info (Character Jump Text) + db 85, 166, "J", %00001111 + db 93, 166, "U", %00001111 + db 101, 166, "M", %00001111 + db 108, 166, "P", %00001111 + db 126, 166, ":", %00001111 + + CharacterRoochoTextOAM: // OAM Info (Character Roocho Text) + db 106, 126, "R", %00001111 + db 114, 126, "O", %00001111 + db 122, 126, "O", %00001111 + db 130, 126, "C", %00001111 + db 137, 126, "H", %00001111 + db 145, 126, "O", %00001111 + + db 137, 142, "H", %00001111 + db 145, 142, "I", %00001111 + db 152, 142, "G", %00001111 + db 160, 142, "H", %00001111 + + db 137, 154, "L", %00001111 + db 144, 154, "O", %00001111 + db 152, 154, "W", %00001111 + + db 135, 166, "M", %00001111 + db 142, 166, "I", %00001111 + db 149, 166, "D", %00001111 + + // OAM Extra Info + db %10101010 + db %00101010 + db %00000000 + db %00000000 + db %00000000 + db %00101000 + db %10000000 + db %00000010 + db %00101000 + db %10000000 + db %00000010 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + CharacterBeochiTextOAM: // OAM Info (Character Beochi Text) + db 106, 126, "B", %00001111 + db 114, 126, "E", %00001111 + db 122, 126, "O", %00001111 + db 130, 126, "C", %00001111 + db 137, 126, "H", %00001111 + db 145, 126, "I", %00001111 + + db 137, 142, "L", %00001111 + db 144, 142, "O", %00001111 + db 152, 142, "W", %00001111 + + db 137, 154, "H", %00001111 + db 145, 154, "I", %00001111 + db 152, 154, "G", %00001111 + db 160, 154, "H", %00001111 + + db 135, 166, "M", %00001111 + db 142, 166, "I", %00001111 + db 149, 166, "D", %00001111 + + CharacterChitoTextOAM: // OAM Info (Character Chito Text) + db 111, 126, "C", %00001111 + db 118, 126, "H", %00001111 + db 126, 126, "I", %00001111 + db 133, 126, "T", %00001111 + db 141, 126, "O", %00001111 + + db 138, 142, "M", %00001111 + db 145, 142, "I", %00001111 + db 152, 142, "D", %00001111 + + db 137, 154, "L", %00001111 + db 144, 154, "O", %00001111 + db 152, 154, "W", %00001111 + + db 134, 166, "H", %00001111 + db 142, 166, "I", %00001111 + db 149, 166, "G", %00001111 + db 157, 166, "H", %00001111 + + db 255, 166, " ", %00001111 + + CharacterGolemTextOAM: // OAM Info (Character Golem Text) + db 111, 126, "G", %00001111 + db 119, 126, "O", %00001111 + db 127, 126, "L", %00001111 + db 134, 126, "E", %00001111 + db 142, 126, "M", %00001111 + + db 137, 142, "H", %00001111 + db 145, 142, "I", %00001111 + db 152, 142, "G", %00001111 + db 160, 142, "H", %00001111 + + db 138, 154, "M", %00001111 + db 145, 154, "I", %00001111 + db 152, 154, "D", %00001111 + + db 134, 166, "L", %00001111 + db 141, 166, "O", %00001111 + db 149, 166, "W", %00001111 + + db 255, 166, " ", %00001111 + +CharacterSelectEnd: + FadeOUT() // Screen Fade Out + + lda.b #$80 + sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) + + stz.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseEasyStage01.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseEasyStage01.asm new file mode 100644 index 00000000..3f271eff --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseEasyStage01.asm @@ -0,0 +1,1123 @@ +//--------------------- +// Course Easy Stage 01 +//--------------------- +// Clear Mode7 VRAM +lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte +sta.w REG_VMAIN // $2115: Video Port Control +ldx.w #$0000 // Set VRAM Destination +stx.w REG_VMADDL // $2116: VRAM +ldy.w #$0000 +LoopClearMode7VRAM: + sty.w REG_VMDATAL // $2118: VRAM Data Write + inx // X++ + cpx.w #$4000 + bne LoopClearMode7VRAM + +LoadPAL(CourseEasyStage01Pal, $00, CourseEasyStage01Pal.size, 0) // Load Background Palette (BG Palette Uses 128 Colors) +LoadHIVRAM(CourseEasyStage01Tiles, $0000, CourseEasyStage01Tiles.size, 0) // Load Background Tiles To VRAM + +LoadPAL(HiScoreLifeHeartPal, $80, HiScoreLifeHeartPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(HiScoreTiles, $8000, HiScoreTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(DistanceGoalLifeScoreTimePal, $90, DistanceGoalLifeScoreTimePal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(DistanceGoalLifeScoreTimeTiles, $8200, DistanceGoalLifeScoreTimeTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(ScoreNumberPal, $A0, ScoreNumberPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadPAL(TimeNumberPal, $B0, TimeNumberPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ScoreTimeNumberTiles, $8A00, ScoreTimeNumberTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadVRAM(LifeHeartTiles, $9440, 64, 0) // Load Sprite Tiles To VRAM +LoadVRAM(LifeHeartTiles + 64, $9640, 64, 0) // Load Sprite Tiles To VRAM + +LoadPAL(ShadowPal, $E0, ShadowPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ShadowTiles, $9500, 128, 0) // Load Sprite Tiles To VRAM +LoadVRAM(ShadowTiles + 128, $9700, 128, 0) // Load Sprite Tiles To VRAM +LoadVRAM(ShadowTiles + 256, $9580, 128, 0) // Load Sprite Tiles To VRAM +LoadVRAM(ShadowTiles + 384, $9780, 128, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CloudDayPal, $F0, CloudDayPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CloudDayTiles, $A800, CloudDayTiles.size, 0) // Load Sprite Tiles To VRAM + +// Set Character Selection Sprite +CharacterSelectionRoochoSprite: + lda.b CourseCharacterSelect + bit.b #%00010000 // Test Roocho Bit + bne CharacterSelectionRoochooSpriteCopy + jmp CharacterSelectionBeochiSprite + CharacterSelectionRoochooSpriteCopy: + LoadPAL(DistanceMarkerRoochoPal, $C0, DistanceMarkerRoochoPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(DistanceMarkerRoochoTiles, $9480, 128, 0) // Load Sprite Tiles To VRAM + LoadVRAM(DistanceMarkerRoochoTiles + 128, $9680, 128, 0) // Load Sprite Tiles To VRAM + LoadPAL(RoochoJumpUpPal, $D0, RoochoJumpUpPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(RoochoJumpUpTiles, $9800, RoochoJumpUpTiles.size, 0) // Load Sprite Tiles To VRAM + jmp CharacterSelectionSpriteEnd +CharacterSelectionBeochiSprite: + bit.b #%00100000 // Test Beochi Bit + bne CharacterSelectionBeochiSpriteCopy + jmp CharacterSelectionChitoSprite + CharacterSelectionBeochiSpriteCopy: + LoadPAL(DistanceMarkerBeochiPal, $C0, DistanceMarkerBeochiPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(DistanceMarkerBeochiTiles, $9480, 128, 0) // Load Sprite Tiles To VRAM + LoadVRAM(DistanceMarkerBeochiTiles + 128, $9680, 128, 0) // Load Sprite Tiles To VRAM + LoadPAL(BeochiJumpUpPal, $D0, BeochiJumpUpPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(BeochiJumpUpTiles, $9800, BeochiJumpUpTiles.size, 0) // Load Sprite Tiles To VRAM + jmp CharacterSelectionSpriteEnd +CharacterSelectionChitoSprite: + bit.b #%01000000 // Test Chito Bit + bne CharacterSelectionChitoSpriteCopy + jmp CharacterSelectionGolemSprite + CharacterSelectionChitoSpriteCopy: + LoadPAL(DistanceMarkerChitoPal, $C0, DistanceMarkerChitoPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(DistanceMarkerChitoTiles, $9480, 128, 0) // Load Sprite Tiles To VRAM + LoadVRAM(DistanceMarkerChitoTiles + 128, $9680, 128, 0) // Load Sprite Tiles To VRAM + LoadPAL(ChitoJumpUpPal, $D0, ChitoJumpUpPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(ChitoJumpUpTiles, $9800, ChitoJumpUpTiles.size, 0) // Load Sprite Tiles To VRAM + jmp CharacterSelectionSpriteEnd +CharacterSelectionGolemSprite: + bit.b #%10000000 // Test Golem Bit + bne CharacterSelectionGolemSpriteCopy + jmp CharacterSelectionSpriteEnd + CharacterSelectionGolemSpriteCopy: + LoadPAL(DistanceMarkerGolemPal, $C0, DistanceMarkerGolemPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(DistanceMarkerGolemTiles, $9480, 128, 0) // Load Sprite Tiles To VRAM + LoadVRAM(DistanceMarkerGolemTiles + 128, $9680, 128, 0) // Load Sprite Tiles To VRAM + LoadPAL(GolemJumpUpPal, $D0, GolemJumpUpPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + LoadVRAM(GolemJumpUpTiles, $9800, GolemJumpUpTiles.size, 0) // Load Sprite Tiles To VRAM +CharacterSelectionSpriteEnd: + +// Clear OAM +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0080 +lda.b #$E0 +- + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + +ldx.w #$0020 +- + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + +// Course Stage OAM Info +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCourseStageOAM: + lda.w CourseStageOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$01D8 + bne LoopCourseStageOAM + +// Course Stage OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCourseStageOAMSize: + lda.w CourseStageOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$01F6 + bne LoopCourseStageOAMSize + +// Setup Video +lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + +lda.b #%00010001 // Enable BG1 & Sprites +sta.w REG_TM // $212C: BG1 & Sprites To Main Screen Designation + +lda.b #%00010000 // Enable Sprites +sta.w REG_TS // $212D: Sprites To Sub Screen Designation + +lda.b #$80 // No Repeat on Mode7 Screen +sta.w REG_M7SEL // $211A: Mode7 Settings + +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7D // $211E: MODE7 COSINE B +stz.w REG_M7D // $211E: MODE7 COSINE B + +ldx.w #-174 // BG1HOFS = -174 +stx.b BG1ScrPosX + +ldx.w #248 // BG1VOFS = 248 +stx.b BG1ScrPosY + +ldx.w #-46 // M7X = -46 +stx.b Mode7PosX + +ldx.w #512 // M7Y = 512 +stx.b Mode7PosY + +lda.b BG1ScrPosX +sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte +lda.b BG1ScrPosX + 1 +sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + +lda.b BG1ScrPosY +sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte +lda.b BG1ScrPosY + 1 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + +lda.b Mode7PosX +sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte +lda.b Mode7PosX + 1 +sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + +lda.b Mode7PosY +sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte +lda.b Mode7PosY + 1 +sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + +// HDMA Mode7 -SIN (A) Scanline +lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice +sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters +lda.b #REG_M7B // $1C: Start At MODE7 SINE A ($211C) +sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7NSINHDMATable // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address +lda.b #M7NSINHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + +// HDMA Mode7 +SIN (D) Scanline +lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice +sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters +lda.b #REG_M7C // $1D: Start At MODE7 SINE B ($211D) +sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7SINHDMATable // HMDA Table Address +stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address +lda.b #M7SINHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + +// HDMA Mode7 Intensity +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters +lda.b #REG_COLDATA // $32: Start At Color Math Sub Screen Backdrop Color ($2132) +sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7IntensityHDMATable // HMDA Table Address +stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address +lda.b #M7IntensityHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + +// HDMA Backdrop/Object Blend +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP3 // $4330: DMA3 DMA/HDMA Parameters +lda.b #REG_CGWSEL // $32: Start At Color Math Control Register A ($2130) +sta.w REG_BBAD3 // $4331: DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #BDOBJBlendHDMATable // HMDA Table Address +stx.w REG_A1T3L // $4332: DMA3 DMA/HDMA Table Start Address +lda.b #BDOBJBlendHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B3 // $4334: DMA3 DMA/HDMA Table Start Address (Bank) + +// HDMA Backdrop/Object Blend DIV +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP4 // $4340: DMA4 DMA/HDMA Parameters +lda.b #REG_CGADSUB // $41: Start At Color Math Control Register B ($2131) +sta.w REG_BBAD4 // $4341: DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #BDOBJBlendDIVHDMATable // HMDA Table Address +stx.w REG_A1T4L // $4342: DMA4 DMA/HDMA Table Start Address +lda.b #BDOBJBlendDIVHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B4 // $4344: DMA4 DMA/HDMA Table Start Address (Bank) + +// HDMA OAM Size & Object Base +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP5 // $4350: DMA5 DMA/HDMA Parameters +lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) +sta.w REG_BBAD5 // $4351: DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #StageHDMATableOAM // HMDA Table Address +stx.w REG_A1T5L // $4352: DMA5 DMA/HDMA Table Start Address +lda.b #StageHDMATableOAM >> 16 // HDMA Table Bank +sta.w REG_A1B5 // $4354: DMA5 DMA/HDMA Table Start Address (Bank) + +lda.b #%00111111 // HDMA Channel Select (Channel 0..5) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +// DMA Load Mode7 Background Map To VRAM +stz.w REG_DMAP6 // Set DMA Mode (Write Byte, Increment Source) ($4360: DMA Control) +lda.b #$18 // Set Destination Register ($2118: VRAM Write) +sta.w REG_BBAD6 // $4361: DMA6 Destination +lda.b #CourseEasyStage01Map >> 16 // Set Source Bank +sta.w REG_A1B6 // $4364: Source Bank +stz.w REG_DAS6H // $4366: DMA6 Transfer Size/HDMA (Hi Byte) + +stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) +ldx.w #$1700 // Set VRAM Destination +stx.w REG_VMADDL // $2116: VRAM + +ldx.w #CourseEasyStage01Map // Set Source Offset +stx.b StageMapOffset // Store Stage Map Offset +ldy.w #36 // Mode7 Play Area Tile Rows + +LoopInitMode7Rows: + stx.w REG_A1T6L // $4362: DMA6 Source + lda.b #128 // Set Size In Bytes To DMA Transfer + sta.w REG_DAS6L // $4365: DMA6 Transfer Size/HDMA (Lo Byte) + + lda.b #%01000000 // Start DMA Transfer On Channel 6 + sta.w REG_MDMAEN // $420B: DMA6 Enable + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #588 // A += Mode7 Play Area Tile Tile columns + tax // X = A + sep #$20 // Set 8-Bit Accumulator + + dey // Y-- + bne LoopInitMode7Rows + +FadeIN() // Screen Fade In + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + // Dynamic Mode7 Background Map + Mode7MapInc: + ldx.b Mode7PosX // X = Mode7 Center Position X + cpx.w #-6 + bne Mode7MapDec // IF (Mode7 Center Position X != -6) Mode7 Map Dec + + ldx.b StageMapOffset // X = Stage Map Offset + cpx.w #$8000 + 460 + beq Mode7MapDec // IF (Stage Map Offset = Last Map Column) Mode7 Map Dec + + ldx.w #-14 // ELSE Mode7 Center Position X = -14, BG1 Position X = -142 + stx.b Mode7PosX + ldx.w #-142 + stx.b BG1ScrPosX + + ldx.b StageMapOffset // Set Source Offset + inx // X++ + stx.b StageMapOffset // Store Stage Map Offset + jmp Mode7Rows + + Mode7MapDec: + ldx.b Mode7PosX // X = Mode7 Center Position X + cpx.w #-15 + bne SkipMode7Rows // IF (Mode7 Center Position X != -15) Skip Mode7 Rows + + ldx.b StageMapOffset // X = Stage Map Offset + cpx.w #$8000 + 0 + beq SkipMode7Rows // IF (Stage Map Offset = First Map Column) Skip Mode7 Rows + + ldx.w #-6 // ELSE Mode7 Center Position X = -6, BG1 Position X = -134 + stx.b Mode7PosX + ldx.w #-134 + stx.b BG1ScrPosX + + ldx.b StageMapOffset // Set Source Offset + dex // X-- + stx.b StageMapOffset // Store Stage Map Offset + + Mode7Rows: + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldy.w #$1700 // Set VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + ldy.w #36 // Mode7 Play Area Tile Rows + + LoopMode7Rows: + stx.w REG_A1T6L // $4362: DMA6 Source + lda.b #128 // Set Size In Bytes To DMA Transfer + sta.w REG_DAS6L // $4365: DMA6 Transfer Size/HDMA (Lo Byte) + + lda.b #%01000000 // Start DMA Transfer On Channel 6 + sta.w REG_MDMAEN // $420B: DMA6 Enable + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #588 // A += Mode7 Play Area Tile Tile columns + tax // X = A + sep #$20 // Set 8-Bit Accumulator + + dey // Y-- + bne LoopMode7Rows + SkipMode7Rows: + + lda.b BG1ScrPosX + sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte + lda.b BG1ScrPosX + 1 + sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + + lda.b BG1ScrPosY + sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte + lda.b BG1ScrPosY + 1 + sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + + lda.b Mode7PosX + sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + lda.b Mode7PosX + 1 + sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + + lda.b Mode7PosY + sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + lda.b Mode7PosY + 1 + sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + JoyUp: + ReadJOY({JOY_UP}) // Test Joypad UP Button + beq JoyDown // IF (UP ! Pressed) Branch Down + ldx.b BG1ScrPosX // Increment BG1 X Pos + inx + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Increment Mode7 X Pos + inx + stx.b Mode7PosX + + JoyDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq JoyLeft // IF (DOWN ! Pressed) Branch Down + ldx.b BG1ScrPosX // Decrement BG1 X Pos + dex + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Decrement Mode7 X Pos + dex + stx.b Mode7PosX + + JoyLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq JoyRight // IF (LEFT ! Pressed) Branch Down + ldx.b BG1ScrPosY // Decrement BG1 Y Pos + dex + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Decrement Mode7 Y Pos + dex + stx.b Mode7PosY + + JoyRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + ldx.b BG1ScrPosY // Increment BG1 Y Pos + inx + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Increment Mode7 Y Pos + inx + stx.b Mode7PosY + +Finish: + jmp InputLoop + +CourseStageOAM: + // 8x8 / 32x32 Sprites + // OAM Info (Course Hi Score 32x8) + db 8, 8, 10, %00110000 + db 16, 8, 11, %00110000 + db 24, 8, 12, %00110000 + db 32, 8, 13, %00110000 + + // OAM Info (Course Hi Score Number 8x8) + db 44, 8, 0, %00110000 + db 50, 8, 0, %00110000 + db 56, 8, 0, %00110000 + db 62, 8, 4, %00110000 + db 68, 8, 2, %00110000 + db 74, 8, 0, %00110000 + db 80, 8, 0, %00110000 + db 86, 8, 0, %00110000 + db 92, 8, 0, %00110000 + + // OAM Info (Course Score 32x16) + db 12, 16, 21, %00110010 + db 20, 16, 22, %00110010 + db 28, 16, 23, %00110010 + db 36, 16, 24, %00110010 + + db 12, 24, 37, %00110010 + db 20, 24, 38, %00110010 + db 28, 24, 39, %00110010 + db 36, 24, 40, %00110010 + + // OAM Info (Course Score Number 8x16) + db 44, 16, 80, %00110100 + db 44, 24, 96, %00110100 + + db 50, 16, 80, %00110100 + db 50, 24, 96, %00110100 + + db 56, 16, 80, %00110100 + db 56, 24, 96, %00110100 + + db 62, 16, 80, %00110100 + db 62, 24, 96, %00110100 + + db 68, 16, 80, %00110100 + db 68, 24, 96, %00110100 + + db 74, 16, 80, %00110100 + db 74, 24, 96, %00110100 + + db 80, 16, 80, %00110100 + db 80, 24, 96, %00110100 + + db 86, 16, 80, %00110100 + db 86, 24, 96, %00110100 + + db 92, 16, 80, %00110100 + db 92, 24, 96, %00110100 + + // 16x16 / 32x32 Sprites + // OAM Info (Distance Marker 16x16) + db 9, 161, 164, %00111000 + + // OAM Info (Goal 24x16) + db 6, 40, 29, %00110010 + db 14, 40, 30, %00110010 + + // OAM Info (Distance Fill 16x112) + db 15, 58, 166, %00111000 + db 15, 74, 166, %00111000 + db 15, 90, 166, %00111000 + db 15, 106, 166, %00111000 + db 15, 122, 166, %00111000 + db 15, 138, 166, %00111000 + db 15, 154, 166, %00111000 + + // OAM Info (Distance Block 16x120) + db 15, 51, 58, %00110010 + db 15, 67, 60, %00110010 + db 15, 83, 60, %00110010 + db 15, 99, 60, %00110010 + db 15, 115, 60, %00110010 + db 15, 131, 60, %00110010 + db 15, 147, 60, %00110010 + db 15, 155, 62, %00110010 + + // OAM Info (Time Number Large 16x24) + db 18, 186, 124, %00110110 + db 18, 194, 140, %00110110 + + db 26, 186, 126, %00110110 + db 26, 194, 142, %00110110 + + // OAM Info (Time Number Small 16x16) + db 35, 202, 160, %00110110 + db 41, 193, 94, %00110110 + + // OAM Info (Time 40x40) + db 13, 174, 16, %00110010 + db 37, 174, 19, %00110010 + db 37, 190, 51, %00110010 + + db 13, 206, 53, %00110010 + db 29, 206, 55, %00110010 + db 37, 206, 56, %00110010 + + // OAM Info (Life 32x16) + db 202, 174, 25, %00110010 + db 218, 174, 27, %00110010 + + // OAM Info (Life Heart X5 16x16) + db 171, 194, 162, %00110000 + db 186, 194, 162, %00110000 + db 201, 194, 162, %00110000 + db 216, 194, 162, %00110000 + db 231, 194, 162, %00110000 + + // OAM Info (Character 96x96) + db 80, 52, 192, %00111010 + db 112, 52, 196, %00111010 + db 144, 52, 200, %00111010 + + db 80, 84, 204, %00111010 + db 112, 84, 0, %00111011 + db 144, 84, 4, %00111011 + + db 80, 116, 8, %00111011 + db 112, 116, 12, %00111011 + + // OAM Info (Shadow 32x32) + db 112, 132, 168, %00001100 + db 128, 132, 170, %00001100 + + db 112, 148, 172, %00001100 + db 128, 148, 174, %00001100 + + // OAM Info (Cloud A 80x48) + db 44, 2, 166, %00001111 + db 76, 2, 170, %00001111 + db 92, 2, 172, %00001111 + + db 44, 34, 230, %00001111 + db 52, 34, 231, %00001111 + db 60, 34, 232, %00001111 + db 68, 34, 233, %00001111 + db 76, 34, 234, %00001111 + db 84, 34, 235, %00001111 + db 92, 34, 236, %00001111 + db 100, 34, 237, %00001111 + db 108, 34, 238, %00001111 + + // OAM Info (Cloud B 80x48) + db 84, 174, 76, %00001111 + db 116, 174, 160, %00001111 + db 148, 174, 164, %00001111 + + db 148, 190, 196, %00001111 + + db 84, 206, 140, %00001111 + db 100, 206, 142, %00001111 + db 116, 206, 224, %00001111 + db 132, 206, 226, %00001111 + db 148, 206, 228, %00001111 + + // OAM Info (Cloud C 96x48) + db 174, 76, 64, %00001111 + db 206, 76, 68, %00001111 + db 238, 76, 72, %00001111 + + db 174, 108, 128, %00001111 + db 190, 108, 130, %00001111 + db 206, 108, 132, %00001111 + db 222, 108, 134, %00001111 + db 238, 108, 136, %00001111 + db 254, 108, 138, %00001111 + + // OAM Extra Info + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %10000000 + db %00000000 + db %00000000 + db %00000000 + db %10101010 + db %10101010 + db %00000000 + db %00101010 + db %00000000 + db %00000000 + db %00001010 + db %00000000 + db %10101000 + db %00000000 + db %10100000 + +M7IntensityHDMATable: + db 1, %11111111 // Repeat 1 Scanlines, RGB Intensity 31 + db 1, %11111110 // Repeat 1 Scanlines, RGB Intensity 30 + db 1, %11111101 // Repeat 1 Scanlines, RGB Intensity 29 + db 1, %11111100 // Repeat 1 Scanlines, RGB Intensity 28 + db 1, %11111011 // Repeat 1 Scanlines, RGB Intensity 27 + db 1, %11111010 // Repeat 1 Scanlines, RGB Intensity 26 + db 1, %11111001 // Repeat 1 Scanlines, RGB Intensity 25 + db 1, %11111000 // Repeat 1 Scanlines, RGB Intensity 24 + db 1, %11110111 // Repeat 1 Scanlines, RGB Intensity 23 + db 1, %11110110 // Repeat 1 Scanlines, RGB Intensity 22 + db 1, %11110101 // Repeat 1 Scanlines, RGB Intensity 21 + db 1, %11110100 // Repeat 1 Scanlines, RGB Intensity 20 + db 1, %11110011 // Repeat 1 Scanlines, RGB Intensity 19 + db 1, %11110010 // Repeat 1 Scanlines, RGB Intensity 18 + db 1, %11110001 // Repeat 1 Scanlines, RGB Intensity 17 + db 2, %11110000 // Repeat 2 Scanlines, RGB Intensity 16 + db 2, %11101111 // Repeat 2 Scanlines, RGB Intensity 15 + db 2, %11101110 // Repeat 2 Scanlines, RGB Intensity 14 + db 2, %11101101 // Repeat 2 Scanlines, RGB Intensity 13 + db 2, %11101100 // Repeat 2 Scanlines, RGB Intensity 12 + db 2, %11101011 // Repeat 2 Scanlines, RGB Intensity 11 + db 2, %11101010 // Repeat 2 Scanlines, RGB Intensity 10 + db 2, %11101001 // Repeat 2 Scanlines, RGB Intensity 9 + db 2, %11101000 // Repeat 2 Scanlines, RGB Intensity 8 + db 2, %11100111 // Repeat 2 Scanlines, RGB Intensity 7 + db 2, %11100110 // Repeat 2 Scanlines, RGB Intensity 6 + db 2, %11100101 // Repeat 2 Scanlines, RGB Intensity 5 + db 2, %11100100 // Repeat 2 Scanlines, RGB Intensity 4 + db 2, %11100011 // Repeat 2 Scanlines, RGB Intensity 3 + db 2, %11100010 // Repeat 2 Scanlines, RGB Intensity 2 + db 2, %11100001 // Repeat 2 Scanlines, RGB Intensity 1 + db 1, %00000000 // Repeat 1 Scanlines, RGB Intensity 0 + db 0 // End Of HDMA + +BDOBJBlendHDMATable: + db 128, %00000000 // Repeat 128 Scanlines, Enable Sub Screen Backdrop Color ADD/SUB + db 4, %00000000 // Repeat 4 Scanlines, Enable Sub Screen Backdrop Color ADD/SUB + db 32, %00000010 // Repeat 32 Scanlines, Enable Sub Screen BG/OBJ/Backdrop Color ADD/SUB + db 1, %00000000 // Repeat 1 Scanlines, Enable Sub Screen Backdrop Color ADD/SUB + db 0 // End Of HDMA + +BDOBJBlendDIVHDMATable: + db 128, %00000001 // Repeat 128 Scanlines, Enable Colour Addition On BG1 + db 4, %00000001 // Repeat 4 Scanlines, Enable Colour Addition On BG1 + db 32, %01000001 // Repeat 32 Scanlines, Enable Colour Addition On BG1, Half Result + db 1, %00000000 // Repeat 1 Scanlines, Enable Colour Addition On BG1 + db 0 // End Of HDMA + +StageHDMATableOAM: + db 40, %00100010 // Repeat 40 Scanlines, Object Size = 8x8/32x32, Name = 0, Base = $8000 + db 1, %01100010 // Repeat 1 Scanlines, Object Size = 16x16/32x32, Name = 0, Base = $8000 + db 0 // End Of HDMA + +M7NSINHDMATable: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20480 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -4096 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2926 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2276 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1862 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1575 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1365 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1205 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1078 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -975 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -931 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -890 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -853 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -819 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -759 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -731 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -706 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -683 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -661 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -640 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -621 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -585 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -569 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -554 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -539 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -525 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -512 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -500 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -488 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -476 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -465 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -455 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -436 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -427 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -418 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -410 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -372 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -359 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -347 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -336 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -325 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -306 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -293 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -288 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -281 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -247 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA + +M7SINHDMATable: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20480 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 4096 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2926 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2276 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1862 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1575 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1365 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1205 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1078 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 975 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 890 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 819 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 759 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 661 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 621 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 585 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 525 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 500 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 476 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 436 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 418 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 372 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 359 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 336 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 288 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 281 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseSelect.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseSelect.asm new file mode 100644 index 00000000..ca7c1e80 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/CourseSelect.asm @@ -0,0 +1,834 @@ +//-------------- +// Course Select +//-------------- +LoadPAL(ComicPal, $00, ComicPal.size, 0) // Load Background Palette (BG Palette Uses 128 Colors) +LoadVRAM(ComicTiles, $0000, ComicTiles.size, 0) // Load Background Tiles To VRAM +LoadVRAM(ComicMap, $7900, ComicMap.size, 0) // Load Background Tile Map To VRAM + +LoadVRAM(CourseSelectDarkBlendTiles, $8000, CourseSelectDarkBlendTiles.size, 0) // Load Background Tiles To VRAM +LoadVRAM(CourseSelectDarkBlendMap, $8900, CourseSelectDarkBlendMap.size, 0) // Load Background Tile Map To VRAM + +LoadPAL(CourseSelectPal, $80, CourseSelectPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CourseSelectTiles, $C000, CourseSelectTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadVRAM(CourseBorderTiles, $D800, CourseBorderTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CourseEasyPal, $90, CourseEasyPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CourseEasyTiles, $E000, CourseEasyTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CourseHardDarkPal, $A0, CourseHardDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CourseHardTiles, $E800, CourseHardTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CourseNormalDarkPal, $B0, CourseNormalDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CourseNormalTiles, $F000, CourseNormalTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(CourseVeryHardDarkPal, $C0, CourseVeryHardDarkPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(CourseVeryHardTiles, $F800, CourseVeryHardTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(FontPal, $F0, CourseSelectPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(FontTiles, $A000, CourseSelectTiles.size, 0) // Load Sprite Tiles To VRAM + +// Clear OAM +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0080 +lda.b #$E0 +- + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + +ldx.w #$0020 +- + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + +// Course Select OAM Info +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCourseSelectOAM: + lda.w CourseSelectOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$01CC + bne LoopCourseSelectOAM + +// Course Select OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopCourseSelectOAMSize: + lda.w CourseSelectOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$01E9 + bne LoopCourseSelectOAMSize + +// Setup Video +lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 & BG2 8x8 Tiles + +// Setup BG1 256 Color Background +lda.b #%01000100 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $8900 (VRAM Address / $400) + +// Setup BG2 16 Color Background +lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + +lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address +sta.w REG_BG12NBA // $210B: BG1 Tile Address = $8000, BG2 Tile Address = $0000 (VRAM Address / $1000) + +lda.b #%00010010 // Enable BG2 & Sprites +sta.w REG_TM // $212C: BG2 & Sprites To Main Screen Designation + +lda.b #%00000001 // Enable BG1 +sta.w REG_TS // $212D: BG1 To Sub Screen Designation + +lda.b #%00000010 // Enable Subscreen BG/OBJ Color ADD/SUB +sta.w REG_CGWSEL // $2130: Color Math Control Register A + +lda.b #%01100010 // Colour Addition On BG2 And Backdrop Colour (Half Result) +sta.w REG_CGADSUB // $2131: Color Math Control Register B + +stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte +stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + +lda.b #31 // Scroll BG1 & BG2 31 Pixels Up +sta.w REG_BG1VOFS // Store A To BG1 Vertical Scroll Position Lo Byte +stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte +sta.w REG_BG2VOFS // Store A To BG Scroll Position Low Byte +stz.w REG_BG2VOFS // Store Zero To BG Scroll Position High Byte + +// HDMA OAM Size & Object Base +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters +lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) +sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #CourseSelectHDMATableOAM // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address +lda.b #CourseSelectHDMATableOAM >> 16 // HDMA Table Bank +sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) +lda.b #%00000001 // HDMA Channel Select (Channel 0) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +FadeIN() // Screen Fade In + +CourseEasy: + WaitNMI() // Wait VBlank + LoadPAL(CourseEasyPal, $90, CourseEasyPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Course Easy Text OAM Info + ldx.w #$00AE // X = $00AE + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCourseEasyTextOAM: + lda.w CourseEasyTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0070 + bne LoopCourseEasyTextOAM + + lda.b #15 + CourseEasyWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CourseEasyWait + + ldy.w #$4083 // Y = Border Color + + CourseEasyLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CourseEasyRight // IF (! LEFT Pressed) GOTO Course Easy Right + LoadPAL(CourseEasyDarkPal, $90, CourseEasyDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseHard // ELSE GOTO Course Hard + CourseEasyRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CourseEasyUp // IF (! RIGHT Pressed) GOTO Course Easy Up + LoadPAL(CourseEasyDarkPal, $90, CourseEasyDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseHard // ELSE GOTO Course Hard + CourseEasyUp: + ReadJOY({JOY_UP}) // Test UP Button + beq CourseEasyDown // IF (! UP Pressed) GOTO Course Easy Down + LoadPAL(CourseEasyDarkPal, $90, CourseEasyDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseNormal // ELSE GOTO Course Normal + CourseEasyDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq CourseEasyStart // IF (! DOWN Pressed) GOTO Course Easy Start + LoadPAL(CourseEasyDarkPal, $90, CourseEasyDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseNormal // ELSE GOTO Course Normal + CourseEasyStart: + ReadJOY({JOY_START}) // Test START Button + beq CourseEasyEnd // IF (! START Pressed) GOTO Course Easy End + lda.b #%00000001 // A = Course Select Easy Flag + sta.b CourseCharacterSelect // Store Course Selection + jmp CourseSelectEnd // ELSE GOTO Course Select End + CourseEasyEnd: + + lda.b #$91 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0111110000000000 + cmp.w #%0111110000000000 + beq EasyBorderDecrementFlag + cmp.w #%0011110000000000 + beq EasyBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq EasyBorderIncrement + bne EasyBorderDecrement + + EasyBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra EasyBorderIncrement + + EasyBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra EasyBorderDecrement + + EasyBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra EasyBorderEnd + + EasyBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + EasyBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CourseEasyLeft // GOTO Course Easy Left + +CourseHard: + WaitNMI() // Wait VBlank + LoadPAL(CourseHardPal, $A0, CourseHardPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Course Hard Text OAM Info + ldx.w #$00AE // X = $00AE + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCourseHardTextOAM: + lda.w CourseHardTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0070 + bne LoopCourseHardTextOAM + + lda.b #15 + CourseHardWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CourseHardWait + + ldy.w #$2610 // Y = Border Color + + CourseHardLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CourseHardRight // IF (! LEFT Pressed) GOTO Course Hard Right + LoadPAL(CourseHardDarkPal, $A0, CourseHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseEasy // ELSE GOTO Course Easy + CourseHardRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CourseHardUp // IF (! RIGHT Pressed) GOTO Course Hard Up + LoadPAL(CourseHardDarkPal, $A0, CourseHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseEasy // ELSE GOTO Course Easy + CourseHardUp: + ReadJOY({JOY_UP}) // Test UP Button + beq CourseHardDown // IF (! UP Pressed) GOTO Course Hard Down + LoadPAL(CourseHardDarkPal, $A0, CourseHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseVeryHard // ELSE GOTO Course Very Hard + CourseHardDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq CourseHardStart // IF (! DOWN Pressed) GOTO Course Hard Start + LoadPAL(CourseHardDarkPal, $A0, CourseHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseVeryHard // ELSE GOTO Course Very Hard + CourseHardStart: + ReadJOY({JOY_START}) // Test START Button + beq CourseHardEnd // IF (! START Pressed) GOTO Course Hard End + lda.b #%00000100 // A = Course Select Hard Flag + sta.b CourseCharacterSelect // Store Course Selection + jmp CourseSelectEnd // ELSE GOTO Course Select End + CourseHardEnd: + + lda.b #$A1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0000001111100000 + cmp.w #%0000001111100000 + beq HardBorderDecrementFlag + cmp.w #%0000000111100000 + beq HardBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq HardBorderIncrement + bne HardBorderDecrement + + HardBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra HardBorderIncrement + + HardBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra HardBorderDecrement + + HardBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra HardBorderEnd + + HardBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + HardBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CourseHardLeft // GOTO Course Hard Left + +CourseNormal: + WaitNMI() // Wait VBlank + LoadPAL(CourseNormalPal, $B0, CourseNormalPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Course Normal Text OAM Info + ldx.w #$00AE // X = $00AE + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCourseNormalTextOAM: + lda.w CourseNormalTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0070 + bne LoopCourseNormalTextOAM + + lda.b #15 + CourseNormalWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CourseNormalWait + + ldy.w #$2A05 // Y = Border Color + + CourseNormalLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CourseNormalRight // IF (! LEFT Pressed) GOTO Course Normal Right + LoadPAL(CourseNormalDarkPal, $B0, CourseNormalDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseVeryHard // ELSE GOTO Course Very Hard + CourseNormalRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CourseNormalUp // IF (! RIGHT Pressed) GOTO Course Normal Up + LoadPAL(CourseNormalDarkPal, $B0, CourseNormalDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseVeryHard // ELSE GOTO Course Very Hard + CourseNormalUp: + ReadJOY({JOY_UP}) // Test UP Button + beq CourseNormalDown // IF (! UP Pressed) GOTO Course Normal Down + LoadPAL(CourseNormalDarkPal, $B0, CourseNormalDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseEasy // ELSE GOTO Course Easy + CourseNormalDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq CourseNormalStart // IF (! DOWN Pressed) GOTO Course Normal Start + LoadPAL(CourseNormalDarkPal, $B0, CourseNormalDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseEasy // ELSE GOTO Course Easy + CourseNormalStart: + ReadJOY({JOY_START}) // Test START Button + beq CourseNormalEnd // IF (! START Pressed) GOTO Course Normal End + lda.b #%00000010 // A = Course Select Normal Flag + sta.b CourseCharacterSelect // Store Course Selection + jmp CourseSelectEnd // ELSE GOTO Course Select End + CourseNormalEnd: + + lda.b #$B1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0000001111100000 + cmp.w #%0000001111100000 + beq NormalBorderDecrementFlag + cmp.w #%0000000111100000 + beq NormalBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq NormalBorderIncrement + bne NormalBorderDecrement + + NormalBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra NormalBorderIncrement + + NormalBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra NormalBorderDecrement + + NormalBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra NormalBorderEnd + + NormalBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + NormalBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CourseNormalLeft // GOTO Course Normal Left + +CourseVeryHard: + WaitNMI() // Wait VBlank + LoadPAL(CourseVeryHardPal, $C0, CourseVeryHardPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + + // Course Very Hard Text OAM Info + ldx.w #$00AE // X = $00AE + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0000 // X = 0 + LoopCourseVeryHardTextOAM: + lda.w CourseVeryHardTextOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0070 + bne LoopCourseVeryHardTextOAM + + lda.b #15 + CourseVeryHardWait: + WaitNMI() // Wait VBlank + dec // A-- + bne CourseVeryHardWait + + ldy.w #$1890 // Y = Border Color + + CourseVeryHardLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq CourseVeryHardRight // IF (! LEFT Pressed) GOTO Course Very Hard Right + LoadPAL(CourseVeryHardDarkPal, $C0, CourseVeryHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseNormal // ELSE GOTO Course Normal + CourseVeryHardRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq CourseVeryHardUp // IF (! RIGHT Pressed) GOTO Course Very Hard Up + LoadPAL(CourseVeryHardDarkPal, $C0, CourseVeryHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseNormal // ELSE GOTO Course Normal + CourseVeryHardUp: + ReadJOY({JOY_UP}) // Test UP Button + beq CourseVeryHardDown // IF (! UP Pressed) GOTO Course Very Hard Down + LoadPAL(CourseVeryHardDarkPal, $C0, CourseVeryHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseHard // ELSE GOTO Course Hard + CourseVeryHardDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq CourseVeryHardStart // IF (! DOWN Pressed) GOTO Course Very Hard Start + LoadPAL(CourseVeryHardDarkPal, $C0, CourseVeryHardDarkPal.size, 1) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + jmp CourseHard // ELSE GOTO Course Hard + CourseVeryHardStart: + ReadJOY({JOY_START}) // Test START Button + beq CourseVeryHardEnd // IF (! START Pressed) GOTO Course Very Hard End + lda.b #%00001000 // A = Course Select Very Hard Flag + sta.b CourseCharacterSelect // Store Course Selection + jmp CourseSelectEnd // ELSE GOTO Course Select End + CourseVeryHardEnd: + + lda.b #$C1 // A = Border Palette CGRAM Address + sta.w REG_CGADD // $2121: Palette CGRAM Address + + rep #$20 // Set 16-Bit Accumulator + tya // A = Y + + and.w #%0000000000011111 + cmp.w #%0000000000011111 + beq VeryHardBorderDecrementFlag + cmp.w #%0000000000001111 + beq VeryHardBorderIncrementFlag + + tya // A = Y + bit.w #$8000 // Test Border Decrement Flag + beq VeryHardBorderIncrement + bne VeryHardBorderDecrement + + VeryHardBorderIncrementFlag: + tya // A = Y + and.w #$7FFF // Clear Border Decrement Flag + bra VeryHardBorderIncrement + + VeryHardBorderDecrementFlag: + tya // A = Y + ora.w #$8000 // Set Border Decrement Flag + bra VeryHardBorderDecrement + + VeryHardBorderIncrement: + clc // Clear Carry Flag + adc.w #%0000010000100001 + bra VeryHardBorderEnd + + VeryHardBorderDecrement: + sec // Set Carry Flag + sbc.w #%0000010000100001 + + VeryHardBorderEnd: + tay // Y = A + sep #$20 // Set 8-Bit Accumulator + + WaitNMI() // Wait VBlank + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + xba // Exchange B & A Accumulators + sta.w REG_CGDATA // $2122: Palette CGRAM Data Write + + jmp CourseVeryHardLeft // GOTO Course Very Hard Left + +CourseSelectHDMATableOAM: + db 128, %01100011 // Repeat 128 Scanlines, Object Size = 16x16/32x32, Name = 0, Base = $C000 + db 58, %01100011 // Repeat 58 Scanlines, Object Size = 16x16/32x32, Name = 0, Base = $C000 + db 1, %00000010 // Repeat 1 Scanlines, Object Size = 8x8/16x16, Name = 0, Base = $8000 + db 0 // End Of HDMA + +CourseSelectOAM: + // 16x16 / 32x32 Sprites + // OAM Info (Course Select 160x48) + db 48, 11, 0, %00000000 + db 80, 11, 4, %00000000 + db 112, 11, 8, %00000000 + db 144, 11, 12, %00000000 + db 176, 11, 96, %00000000 + + db 48, 43, 64, %00000000 + db 64, 43, 66, %00000000 + db 80, 43, 68, %00000000 + db 96, 43, 70, %00000000 + db 112, 43, 72, %00000000 + db 128, 43, 74, %00000000 + db 144, 43, 76, %00000000 + db 160, 43, 78, %00000000 + db 176, 43, 160, %00000000 + db 192, 43, 162, %00000000 + + // OAM Info (Course Easy 112x64) + db 6, 62, 192, %00000010 + db 22, 62, 194, %00000010 + db 38, 62, 196, %00000010 + db 54, 62, 198, %00000010 + db 70, 62, 200, %00000010 + db 86, 62, 202, %00000010 + db 102, 62, 204, %00000010 + + db 6, 78, 0, %00000011 + db 38, 78, 4, %00000011 + db 70, 78, 8, %00000011 + db 102, 78, 12, %00000011 + + db 6, 110, 224, %00000010 + db 22, 110, 226, %00000010 + db 38, 110, 228, %00000010 + db 54, 110, 230, %00000010 + db 70, 110, 232, %00000010 + db 86, 110, 234, %00000010 + db 102, 110, 236, %00000010 + + // OAM Info (Course Hard 112x64) + db 114, 62, 192, %00000100 + db 130, 62, 194, %00000100 + db 146, 62, 196, %00000100 + db 162, 62, 198, %00000100 + db 178, 62, 200, %00000100 + db 194, 62, 202, %00000100 + db 210, 62, 204, %00000100 + + db 114, 78, 64, %00000101 + db 146, 78, 68, %00000101 + db 178, 78, 72, %00000101 + db 210, 78, 76, %00000101 + + db 114, 110, 224, %00000100 + db 130, 110, 226, %00000100 + db 146, 110, 228, %00000100 + db 162, 110, 230, %00000100 + db 178, 110, 232, %00000100 + db 194, 110, 234, %00000100 + db 210, 110, 236, %00000100 + + // OAM Info (Course Normal 112x64) + db 34, 122, 192, %00000110 + db 50, 122, 194, %00000110 + db 66, 122, 196, %00000110 + db 82, 122, 198, %00000110 + db 98, 122, 200, %00000110 + db 114, 122, 202, %00000110 + db 130, 122, 204, %00000110 + + db 34, 138, 128, %00000111 + db 66, 138, 132, %00000111 + db 98, 138, 136, %00000111 + db 130, 138, 140, %00000111 + + db 34, 170, 224, %00000110 + db 50, 170, 226, %00000110 + db 66, 170, 228, %00000110 + db 82, 170, 230, %00000110 + db 98, 170, 232, %00000110 + db 114, 170, 234, %00000110 + db 130, 170, 236, %00000110 + + // OAM Info (Course Very Hard 112x64) + db 142, 122, 192, %00001000 + db 158, 122, 194, %00001000 + db 174, 122, 196, %00001000 + db 190, 122, 198, %00001000 + db 206, 122, 200, %00001000 + db 222, 122, 202, %00001000 + db 238, 122, 204, %00001000 + + db 142, 138, 192, %00001001 + db 174, 138, 196, %00001001 + db 206, 138, 200, %00001001 + db 238, 138, 204, %00001001 + + db 142, 170, 224, %00001000 + db 158, 170, 226, %00001000 + db 174, 170, 228, %00001000 + db 190, 170, 230, %00001000 + db 206, 170, 232, %00001000 + db 222, 170, 234, %00001000 + db 238, 170, 236, %00001000 + + map 'a', $00, 26 + map $22, $1A // Double Quote '"' + map '#', $1B + map '$', $1C + map '%', $1D + map '&', $1E + map $27, $1F // Single Quote "'" + map '*', $20 + map '@', $21 + map '/', $22 + map '_', $23 + map $3B, $24 // Semicolon ";" + map ' ', $25 + + map 'A', $80, 26 + map '-', $9A + map '+', $9B + map '0', $9C, 10 + map '!', $A6 + map '(', $A7 + map ')', $A8 + map $2C, $A9 // Comma "," + map '.', $AA + map ':', $AB + map '=', $AC + map '?', $AD + map '`', $AE + + // 8x8 / 16x16 Sprites + CourseEasyTextOAM: // OAM Info (Course Easy Text) + db 35, 189, "T", %00001111 + db 43, 189, "o", %00001111 + db 49, 189, "t", %00001111 + db 56, 189, "a", %00001111 + db 64, 189, "l", %00001111 + + db 71, 189, "1", %00001111 + db 78, 189, "0", %00001111 + + db 91, 189, "s", %00001111 + db 97, 189, "t", %00001111 + db 104, 189, "a", %00001111 + db 112, 190, "g", %00001111 + db 119, 189, "e", %00001111 + db 126, 189, "s", %00001111 + + db 136, 189, "f", %00001111 + db 142, 189, "o", %00001111 + db 148, 189, "r", %00001111 + + db 158, 189, "b", %00001111 + db 165, 189, "e", %00001111 + db 172, 190, "g", %00001111 + db 179, 189, "i", %00001111 + db 183, 189, "n", %00001111 + db 190, 189, "n", %00001111 + db 197, 189, "e", %00001111 + db 204, 189, "r", %00001111 + db 210, 189, "s", %00001111 + db 216, 190, ".", %00001111 + + db 255, 189, " ", %00001111 + db 255, 189, " ", %00001111 + + // OAM Extra Info + db %10101010 + db %00000010 + db %00000000 + db %00000000 + db %00000000 + db %10100000 + db %00001010 + db %00000000 + db %00000000 + db %00000000 + db %10101010 + db %00000000 + db %00000000 + db %00000000 + db %10100000 + db %00001010 + db %00000000 + db %00000000 + db %00000000 + db %10101010 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + CourseHardTextOAM: // OAM Info (Course Hard Text) + db 43, 189, "H", %00001111 + db 51, 189, "a", %00001111 + db 58, 189, "r", %00001111 + db 65, 189, "d", %00001111 + + db 77, 189, "l", %00001111 + db 80, 189, "e", %00001111 + db 88, 189, "v", %00001111 + db 95, 189, "e", %00001111 + db 103, 189, "l", %00001111 + db 106, 190, ".", %00001111 + + db 114, 189, "T", %00001111 + db 122, 189, "o", %00001111 + db 128, 189, "t", %00001111 + db 135, 189, "a", %00001111 + db 143, 189, "l", %00001111 + + db 150, 189, "2", %00001111 + db 158, 189, "0", %00001111 + + db 171, 189, "s", %00001111 + db 177, 189, "t", %00001111 + db 184, 189, "a", %00001111 + db 192, 190, "g", %00001111 + db 199, 189, "e", %00001111 + db 206, 189, "s", %00001111 + db 212, 190, ".", %00001111 + + db 255, 189, " ", %00001111 + db 255, 189, " ", %00001111 + db 255, 189, " ", %00001111 + db 255, 189, " ", %00001111 + + CourseNormalTextOAM: // OAM Info (Course Normal Text) + db 35, 189, "N", %00001111 + db 43, 189, "o", %00001111 + db 50, 189, "r", %00001111 + db 56, 189, "m", %00001111 + db 64, 189, "a", %00001111 + db 72, 189, "l", %00001111 + + db 81, 189, "l", %00001111 + db 84, 189, "e", %00001111 + db 92, 189, "v", %00001111 + db 99, 189, "e", %00001111 + db 107, 189, "l", %00001111 + db 110, 190, ".", %00001111 + + db 118, 189, "T", %00001111 + db 126, 189, "o", %00001111 + db 132, 189, "t", %00001111 + db 139, 189, "a", %00001111 + db 147, 189, "l", %00001111 + + db 154, 189, "2", %00001111 + db 162, 189, "0", %00001111 + + db 175, 189, "s", %00001111 + db 181, 189, "t", %00001111 + db 188, 189, "a", %00001111 + db 196, 190, "g", %00001111 + db 203, 189, "e", %00001111 + db 210, 189, "s", %00001111 + db 216, 190, ".", %00001111 + + db 255, 189, " ", %00001111 + db 255, 189, " ", %00001111 + + CourseVeryHardTextOAM: // OAM Info (Course Very Hard Text) + db 26, 189, "V", %00001111 + db 34, 189, "e", %00001111 + db 41, 189, "r", %00001111 + db 47, 190, "y", %00001111 + + db 60, 189, "h", %00001111 + db 67, 189, "a", %00001111 + db 74, 189, "r", %00001111 + db 80, 189, "d", %00001111 + + db 92, 189, "l", %00001111 + db 95, 189, "e", %00001111 + db 103, 189, "v", %00001111 + db 110, 189, "e", %00001111 + db 118, 189, "l", %00001111 + db 121, 190, ".", %00001111 + + db 129, 189, "T", %00001111 + db 137, 189, "o", %00001111 + db 143, 189, "t", %00001111 + db 150, 189, "a", %00001111 + db 158, 189, "l", %00001111 + + db 165, 189, "2", %00001111 + db 173, 189, "0", %00001111 + + db 186, 189, "s", %00001111 + db 192, 189, "t", %00001111 + db 199, 189, "a", %00001111 + db 207, 190, "g", %00001111 + db 214, 189, "e", %00001111 + db 221, 189, "s", %00001111 + db 227, 190, ".", %00001111 + +CourseSelectEnd: + FadeOUT() // Screen Fade Out + + lda.b #$80 + sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) + + stz.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pal new file mode 100644 index 00000000..a21eb36c Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pic new file mode 100644 index 00000000..c2f63f71 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Beochi/BeochiJumpUp4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pal new file mode 100644 index 00000000..60d39594 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pic new file mode 100644 index 00000000..fb05a83e Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Chito/ChitoJumpUp4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pal new file mode 100644 index 00000000..2a0c5f29 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pic new file mode 100644 index 00000000..e30193b7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Golem/GolemJumpUp4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pal new file mode 100644 index 00000000..e9999de6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pic new file mode 100644 index 00000000..d28e8dcb Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Roocho/RoochoJumpUp4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pal new file mode 100644 index 00000000..ee54940a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pic new file mode 100644 index 00000000..d166e146 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Character/Shadow4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pal new file mode 100644 index 00000000..7b90b554 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pic new file mode 100644 index 00000000..050462dc Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterArrow4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pal new file mode 100644 index 00000000..71439cdf Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pic new file mode 100644 index 00000000..bb407f9d Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochi4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochiDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochiDark4BPP.pal new file mode 100644 index 00000000..b640f890 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterBeochiDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pal new file mode 100644 index 00000000..5aef5bf4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pic new file mode 100644 index 00000000..6fa891ec Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChito4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChitoDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChitoDark4BPP.pal new file mode 100644 index 00000000..ede5e5b1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterChitoDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pal new file mode 100644 index 00000000..4000ed8e Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pic new file mode 100644 index 00000000..e43db6e8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolem4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolemDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolemDark4BPP.pal new file mode 100644 index 00000000..77aca4a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterGolemDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pal new file mode 100644 index 00000000..ad16e5b4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pic new file mode 100644 index 00000000..9fca2988 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoocho4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoochoDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoochoDark4BPP.pal new file mode 100644 index 00000000..20375238 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterRoochoDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pal new file mode 100644 index 00000000..7f9d2028 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pic new file mode 100644 index 00000000..91d2eb2b Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelect4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.map new file mode 100644 index 00000000..b7c28765 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.pic new file mode 100644 index 00000000..43f1aa7f Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.map new file mode 100644 index 00000000..6cfd3489 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pal new file mode 100644 index 00000000..e184cf9f Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pic new file mode 100644 index 00000000..d4c9d815 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Comic4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pal new file mode 100644 index 00000000..7de79df9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pic new file mode 100644 index 00000000..36f493b6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/CloudDay4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pal new file mode 100644 index 00000000..399c3b14 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pic new file mode 100644 index 00000000..4b915902 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceGoalLifeScoreTime4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerBeochi4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerBeochi4BPP.pal new file mode 100644 index 00000000..1946cb85 Binary files /dev/null and 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b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerChito4BPP.pic new file mode 100644 index 00000000..faa7c1cc Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerChito4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pal new file mode 100644 index 00000000..855f0ffe Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pic new file mode 100644 index 00000000..1ea64101 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerGolem4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pal new file mode 100644 index 00000000..d2dcc159 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pic new file mode 100644 index 00000000..0b65edac Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/DistanceMarkerRoocho4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/Easy/CourseEasyStage01.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/Easy/CourseEasyStage01.map new file mode 100644 index 00000000..4e0f2892 Binary files /dev/null and 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index 00000000..3dbd613c Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/HiScore4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/HiScoreLifeHeart4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/HiScoreLifeHeart4BPP.pal new file mode 100644 index 00000000..3e6d6355 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/HiScoreLifeHeart4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/LifeHeart4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/LifeHeart4BPP.pic new file mode 100644 index 00000000..9cb40727 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/LifeHeart4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreNumber4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreNumber4BPP.pal new file mode 100644 index 00000000..c66e74d4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreNumber4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreTimeNumber4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreTimeNumber4BPP.pic new file mode 100644 index 00000000..9e6041a2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/ScoreTimeNumber4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/TimeNumber4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/TimeNumber4BPP.pal new file mode 100644 index 00000000..56e4276d Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Course/TimeNumber4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseBorder4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseBorder4BPP.pic new file mode 100644 index 00000000..9f1d1ec8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseBorder4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pal new file mode 100644 index 00000000..0bd16ed7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pic new file mode 100644 index 00000000..11910bbc Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasy4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasyDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasyDark4BPP.pal new file mode 100644 index 00000000..8f1a3ce1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseEasyDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pal new file mode 100644 index 00000000..6452c421 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pic new file mode 100644 index 00000000..38f3dbdc Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHard4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHardDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHardDark4BPP.pal new file mode 100644 index 00000000..ca28c2a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseHardDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pal new file mode 100644 index 00000000..8e05c54d Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pic new file mode 100644 index 00000000..9ed803e9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormal4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormalDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormalDark4BPP.pal new file mode 100644 index 00000000..8fc96656 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseNormalDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pal new file mode 100644 index 00000000..50051d4d Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pic new file mode 100644 index 00000000..37272a7f Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelect4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.map new file mode 100644 index 00000000..176288ca Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.pic new file mode 100644 index 00000000..95f606b4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseSelectDarkBlend8BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pal new file mode 100644 index 00000000..65efa823 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pic new file mode 100644 index 00000000..da4d9cf5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHard4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHardDark4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHardDark4BPP.pal new file mode 100644 index 00000000..cec1feac Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/CourseSelect/CourseVeryHardDark4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pal new file mode 100644 index 00000000..489aff5b Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pic new file mode 100644 index 00000000..3f7822cc Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/Font4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.map new file mode 100644 index 00000000..0ced6ebe Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pal new file mode 100644 index 00000000..f36b3b03 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pic new file mode 100644 index 00000000..4c70c2ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/Tecmo2BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.map new file mode 100644 index 00000000..5ce40fc6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pal new file mode 100644 index 00000000..ba1a5174 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pic new file mode 100644 index 00000000..1a738cda Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TecmoLogo/TecmoHiLight4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pal new file mode 100644 index 00000000..ef518e31 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pic new file mode 100644 index 00000000..6bf4c0f1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicA4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pal new file mode 100644 index 00000000..7565b7aa Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pic new file mode 100644 index 00000000..e38029c6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicB4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pal new file mode 100644 index 00000000..227dfb21 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pic new file mode 100644 index 00000000..ee7f0148 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicC4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicCD4BPPMap.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicCD4BPPMap.asm new file mode 100644 index 00000000..30937a5f --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicCD4BPPMap.asm @@ -0,0 +1,13 @@ +// Comic C Map: Comic D Map: +dw $1880,$1881,$1882,$1883,$1884,$1885,$1886,$1887,$1888,$1889,$188A,$188B,$188C,$188D,$188E,$188F, $1D40,$1D41,$1D42,$1D43,$1D44,$1D45,$1D46,$1D47,$1D48,$1D49,$1D4A,$1D4B,$1D4C,$1D4D,$1D4E,$1D4F +dw $1890,$1891,$1892,$1893,$1894,$1895,$1896,$1897,$1898,$1899,$189A,$189B,$189C,$189D,$189E,$189F, $1D50,$1D51,$1D52,$1D53,$1D54,$1D55,$1D56,$1D57,$1D58,$1D59,$1D5A,$1D5B,$1D5C,$1D5D,$1D5E,$1D5F +dw $18A0,$18A1,$18A2,$18A3,$18A4,$18A5,$18A6,$18A7,$18A8,$18A9,$18AA,$18AB,$18AC,$18AD,$18AE,$18AF, $1D60,$1D61,$1D62,$1D63,$1D64,$1D65,$1D66,$1D67,$1D68,$1D69,$1D6A,$1D6B,$1D6C,$1D6D,$1D6E,$1D6F +dw $18B0,$18B1,$18B2,$18B3,$18B4,$18B5,$18B6,$18B7,$18B8,$18B9,$18BA,$18BB,$18BC,$18BD,$18BE,$18BF, $1D70,$1D71,$1D72,$1D73,$1D74,$1D75,$1D76,$1D77,$1D78,$1D79,$1D7A,$1D7B,$1D7C,$1D7D,$1D7E,$1D7F +dw $18C0,$18C1,$18C2,$18C3,$18C4,$18C5,$18C6,$18C7,$18C8,$18C9,$18CA,$18CB,$18CC,$18CD,$18CE,$18CF, $1D80,$1D81,$1D82,$1D83,$1D84,$1D85,$1D86,$1D87,$1D88,$1D89,$1D8A,$1D8B,$1D8C,$1D8D,$1D8E,$1D8F +dw $18D0,$18D1,$18D2,$18D3,$18D4,$18D5,$18D6,$18D7,$18D8,$18D9,$18DA,$18DB,$18DC,$18DD,$18DE,$18DF, $1D90,$1D91,$1D92,$1D93,$1D94,$1D95,$1D96,$1D97,$1D98,$1D99,$1D9A,$1D9B,$1D9C,$1D9D,$1D9E,$1D9F +dw $18E0,$18E1,$18E2,$18E3,$18E4,$18E5,$18E6,$18E7,$18E8,$18E9,$18EA,$18EB,$18EC,$18ED,$18EE,$18EF, $1DA0,$1DA1,$1DA2,$1DA3,$1DA4,$1DA5,$1DA6,$1DA7,$1DA8,$1DA9,$1DAA,$1DAB,$1DAC,$1DAD,$1DAE,$1DAF +dw $18F0,$18F1,$18F2,$18F3,$18F4,$18F5,$18F6,$18F7,$18F8,$18F9,$18FA,$18FB,$18FC,$18FD,$18FE,$18FF, $1DB0,$1DB1,$1DB2,$1DB3,$1DB4,$1DB5,$1DB6,$1DB7,$1DB8,$1DB9,$1DBA,$1DBB,$1DBC,$1DBD,$1DBE,$1DBF +dw $1900,$1901,$1902,$1903,$1904,$1905,$1906,$1907,$1908,$1909,$190A,$190B,$190C,$190D,$190E,$190F, $1DC0,$1DC1,$1DC2,$1DC3,$1DC4,$1DC5,$1DC6,$1DC7,$1DC8,$1DC9,$1DCA,$1DCB,$1DCC,$1DCD,$1DCE,$1DCF +dw $1910,$1911,$1912,$1913,$1914,$1915,$1916,$1917,$1918,$1919,$191A,$191B,$191C,$191D,$191E,$191F, $1DD0,$1DD1,$1DD2,$1DD3,$1DD4,$1DD5,$1DD6,$1DD7,$1DD8,$1DD9,$1DDA,$1DDB,$1DDC,$1DDD,$1DDE,$1DDF +dw $1920,$1921,$1922,$1923,$1924,$1925,$1926,$1927,$1928,$1929,$192A,$192B,$192C,$192D,$192E,$192F, $1DE0,$1DE1,$1DE2,$1DE3,$1DE4,$1DE5,$1DE6,$1DE7,$1DE8,$1DE9,$1DEA,$1DEB,$1DEC,$1DED,$1DEE,$1DEF +dw $1930,$1931,$1932,$1933,$1934,$1935,$1936,$1937,$1938,$1939,$193A,$193B,$193C,$193D,$193E,$193F, $1DF0,$1DF1,$1DF2,$1DF3,$1DF4,$1DF5,$1DF6,$1DF7,$1DF8,$1DF9,$1DFA,$1DFB,$1DFC,$1DFD,$1DFE,$1DFF \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pal new file mode 100644 index 00000000..62a728fe Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pic new file mode 100644 index 00000000..0b87da83 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/ComicD4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.map b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.map new file mode 100644 index 00000000..6dea34d8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.map differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pal new file mode 100644 index 00000000..f28b32ad Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pic new file mode 100644 index 00000000..653c37cb Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/MonsterFarmJump8BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pal new file mode 100644 index 00000000..eb71a68c Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pic new file mode 100644 index 00000000..d045b836 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/PressStartButton4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pal new file mode 100644 index 00000000..a784f76a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pic new file mode 100644 index 00000000..9d395d34 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoCopyright4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pal b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pal new file mode 100644 index 00000000..d8a6478a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pal differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pic b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pic new file mode 100644 index 00000000..c92ac53b Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/GFX/TitleScreen/TecmoMini4BPP.pic differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES.INC b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a7baa37d --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MONSTER FARM JUMP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $09 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.asm new file mode 100644 index 00000000..0ecaa1c1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.asm @@ -0,0 +1,222 @@ +// SNES Monster Farm Jump Game by krom (Peter Lemon): +arch snes.cpu +output "MonsterFarmJump.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $80000 // Fill Upto $FFFF (Bank 15) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +CourseCharacterSelect: + db %00000000 // Course Select (0=Easy, 1=Normal, 2=Hard, 3=Very Hard), Character Select (4=Roocho, 5=Beochi, 6=Chito, 7=Golem) Byte +Mode7PosX: + dw 0 // Mode7 Center Position X Word +Mode7PosY: + dw 0 // Mode7 Center Position Y Word +BG1ScrPosX: + dw 0 // Mode7 BG1 Scroll Position X Word +BG1ScrPosY: + dw 0 // Mode7 BG1 Scroll Position Y Word +StageMapOffset: + dw 0 // Stage Map Offset Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + //----------- + // Tecmo Logo + //----------- + include "TecmoLogo.asm" // Include Tecmo Logo Routine + + //------------- + // Title Screen + //------------- + include "TitleScreen.asm" // Include Title Screen Routine + + //-------------- + // Course Select + //-------------- + include "CourseSelect.asm" // Include Course Select Routine + + //----------------- + // Character Select + //----------------- + include "CharacterSelect.asm" // Include Character Select Routine + + //--------------------- + // Course Easy Stage 01 + //--------------------- + include "CourseEasyStage01.asm" // Include Stage Routine + +Loop: + jmp Loop + +// Character Data +// BANK 1 +seek($18000) +insert TecmoPal, "GFX/TecmoLogo/Tecmo2BPP.pal" // Include BG Palette Data (8 Bytes) +insert TecmoMap, "GFX/TecmoLogo/Tecmo2BPP.map" // Include BG Map Data (3584 Bytes) +insert TecmoTiles, "GFX/TecmoLogo/Tecmo2BPP.pic" // Include BG Tile Data (3936 Bytes) + +insert TecmoHiLightPal, "GFX/TecmoLogo/TecmoHiLight4BPP.pal" // Include BG Palette Data (32 Bytes) +insert TecmoHiLightMap, "GFX/TecmoLogo/TecmoHiLight4BPP.map" // Include BG Map Data (3584 Bytes) +insert TecmoHiLightTiles, "GFX/TecmoLogo/TecmoHiLight4BPP.pic" // Include BG Tile Data (6400 Bytes) + +insert TecmoMiniPal, "GFX/TitleScreen/TecmoMini4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert TecmoMiniTiles, "GFX/TitleScreen/TecmoMini4BPP.pic" // Include Sprite Tile Data (768 Bytes) + +insert TecmoCopyrightPal, "GFX/TitleScreen/TecmoCopyright4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert TecmoCopyrightTiles, "GFX/TitleScreen/TecmoCopyright4BPP.pic" // Include Sprite Tile Data (1024 Bytes) + +insert PressStartButtonPal, "GFX/TitleScreen/PressStartButton4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert PressStartButtonTiles, "GFX/TitleScreen/PressStartButton4BPP.pic" // Include Sprite Tile Data (960 Bytes) + +// BANK 2 +seek($28000) +insert MonsterFarmJumpPal, "GFX/TitleScreen/MonsterFarmJump8BPP.pal" // Include BG Palette Data (192 Bytes) +insert MonsterFarmJumpMap, "GFX/TitleScreen/MonsterFarmJump8BPP.map" // Include BG Map Data (16384 Bytes) +insert MonsterFarmJumpTiles, "GFX/TitleScreen/MonsterFarmJump8BPP.pic" // Include BG Tile Data (15360 Bytes) + +// BANK 3 +seek($38000) +insert ComicAPal, "GFX/TitleScreen/ComicA4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert ComicATiles, "GFX/TitleScreen/ComicA4BPP.pic" // Include Sprite Tile Data (8192 Bytes) + +insert ComicBPal, "GFX/TitleScreen/ComicB4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert ComicBTiles, "GFX/TitleScreen/ComicB4BPP.pic" // Include Sprite Tile Data (8192 Bytes) + +insert ComicCPal, "GFX/TitleScreen/ComicC4BPP.pal" // Include BG/Sprite Palette Data (32 Bytes) +insert ComicCTiles, "GFX/TitleScreen/ComicC4BPP.pic" // Include BG/Sprite Tile Data (6144 Bytes) + +insert ComicDPal, "GFX/TitleScreen/ComicD4BPP.pal" // Include BG/Sprite Palette Data (32 Bytes) +insert ComicDTiles, "GFX/TitleScreen/ComicD4BPP.pic" // Include BG/Sprite Tile Data (6144 Bytes) + +ComicCDMap: + include "GFX/TitleScreen/ComicCD4BPPMap.asm" // Include BG Map Data (768 Bytes) + +insert CourseSelectDarkBlendMap, "GFX/CourseSelect/CourseSelectDarkBlend8BPP.map" // Include BG Map Data (2048 Bytes) +insert CourseSelectDarkBlendTiles, "GFX/CourseSelect/CourseSelectDarkBlend8BPP.pic" // Include BG Tile Data (576 Bytes) + +// BANK 4 +seek($48000) +insert ComicPal, "GFX/Comic4BPP.pal" // Include BG Palette Data (256 Bytes) +insert ComicMap, "GFX/Comic4BPP.map" // Include BG Map Data (1792 Bytes) +insert ComicTiles, "GFX/Comic4BPP.pic" // Include BG Tile Data (28672 Bytes) + +// BANK 5 +seek($58000) +insert CourseSelectPal, "GFX/CourseSelect/CourseSelect4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseSelectTiles, "GFX/CourseSelect/CourseSelect4BPP.pic" // Include Sprite Tile Data (6144 Bytes) + +insert CourseBorderTiles, "GFX/CourseSelect/CourseBorder4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CourseEasyDarkPal, "GFX/CourseSelect/CourseEasyDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseEasyPal, "GFX/CourseSelect/CourseEasy4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseEasyTiles, "GFX/CourseSelect/CourseEasy4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CourseHardDarkPal, "GFX/CourseSelect/CourseHardDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseHardPal, "GFX/CourseSelect/CourseHard4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseHardTiles, "GFX/CourseSelect/CourseHard4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CourseNormalDarkPal, "GFX/CourseSelect/CourseNormalDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseNormalPal, "GFX/CourseSelect/CourseNormal4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseNormalTiles, "GFX/CourseSelect/CourseNormal4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CourseVeryHardDarkPal, "GFX/CourseSelect/CourseVeryHardDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseVeryHardPal, "GFX/CourseSelect/CourseVeryHard4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CourseVeryHardTiles, "GFX/CourseSelect/CourseVeryHard4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert FontPal, "GFX/Font4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert FontTiles, "GFX/Font4BPP.pic" // Include Sprite Tile Data (5632 Bytes) + +insert CharacterSelectDarkBlendMap, "GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.map" // Include BG Map Data (2048 Bytes) +insert CharacterSelectDarkBlendTiles, "GFX/CharacterSelect/CharacterSelectDarkBlend8BPP.pic" // Include BG Tile Data (832 Bytes) + +insert CharacterSelectPal, "GFX/CharacterSelect/CharacterSelect4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterSelectTiles, "GFX/CharacterSelect/CharacterSelect4BPP.pic" // Include Sprite Tile Data (6144 Bytes) + +// BANK 6 +seek($68000) +insert CharacterRoochoDarkPal, "GFX/CharacterSelect/CharacterRoochoDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterRoochoPal, "GFX/CharacterSelect/CharacterRoocho4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterRoochoTiles, "GFX/CharacterSelect/CharacterRoocho4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CharacterBeochiDarkPal, "GFX/CharacterSelect/CharacterBeochiDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterBeochiPal, "GFX/CharacterSelect/CharacterBeochi4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterBeochiTiles, "GFX/CharacterSelect/CharacterBeochi4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CharacterChitoDarkPal, "GFX/CharacterSelect/CharacterChitoDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterChitoPal, "GFX/CharacterSelect/CharacterChito4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterChitoTiles, "GFX/CharacterSelect/CharacterChito4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CharacterGolemDarkPal, "GFX/CharacterSelect/CharacterGolemDark4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterGolemPal, "GFX/CharacterSelect/CharacterGolem4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterGolemTiles, "GFX/CharacterSelect/CharacterGolem4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert CharacterArrowPal, "GFX/CharacterSelect/CharacterArrow4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CharacterArrowTiles, "GFX/CharacterSelect/CharacterArrow4BPP.pic" // Include Sprite Tile Data (1024 Bytes) + +// BANK 7 +seek($78000) +insert HiScoreLifeHeartPal, "GFX/Course/HiScoreLifeHeart4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert HiScoreTiles, "GFX/Course/HiScore4BPP.pic" // Include Sprite Tile Data (512 Bytes) +insert LifeHeartTiles, "GFX/Course/LifeHeart4BPP.pic" // Include Sprite Tile Data (128 Bytes) + +insert DistanceGoalLifeScoreTimePal, "GFX/Course/DistanceGoalLifeScoreTime4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert DistanceGoalLifeScoreTimeTiles, "GFX/Course/DistanceGoalLifeScoreTime4BPP.pic" // Include Sprite Tile Data (2048 Bytes) + +insert ScoreNumberPal, "GFX/Course/ScoreNumber4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert TimeNumberPal, "GFX/Course/TimeNumber4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert ScoreTimeNumberTiles, "GFX/Course/ScoreTimeNumber4BPP.pic" // Include Sprite Tile Data (3584 Bytes) + +insert DistanceMarkerRoochoPal, "GFX/Course/DistanceMarkerRoocho4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert DistanceMarkerRoochoTiles, "GFX/Course/DistanceMarkerRoocho4BPP.pic" // Include Sprite Tile Data (256 Bytes) + +insert DistanceMarkerBeochiPal, "GFX/Course/DistanceMarkerBeochi4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert DistanceMarkerBeochiTiles, "GFX/Course/DistanceMarkerBeochi4BPP.pic" // Include Sprite Tile Data (256 Bytes) + +insert DistanceMarkerChitoPal, "GFX/Course/DistanceMarkerChito4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert DistanceMarkerChitoTiles, "GFX/Course/DistanceMarkerChito4BPP.pic" // Include Sprite Tile Data (256 Bytes) + +insert DistanceMarkerGolemPal, "GFX/Course/DistanceMarkerGolem4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert DistanceMarkerGolemTiles, "GFX/Course/DistanceMarkerGolem4BPP.pic" // Include Sprite Tile Data (256 Bytes) + +insert CloudDayPal, "GFX/Course/CloudDay4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert CloudDayTiles, "GFX/Course/CloudDay4BPP.pic" // Include Sprite Tile Data (6144 Bytes) + +insert ShadowPal, "GFX/Character/Shadow4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert ShadowTiles, "GFX/Character/Shadow4BPP.pic" // Include Sprite Tile Data (512 Bytes) + +// BANK 8 +seek($88000) +insert CourseEasyStage01Pal, "GFX/Course/Easy/CourseEasyStage01.pal" // Include BG Palette Data (256 Bytes) +insert CourseEasyStage01Tiles, "GFX/Course/Easy/CourseEasyStage01.pic" // Include BG Tile Data (14400 Bytes) + +// BANK 9 +seek($98000) +insert CourseEasyStage01Map, "GFX/Course/Easy/CourseEasyStage01.map" // Include BG Map Data (21168 Bytes) + +// BANK 10 +seek($A8000) +insert RoochoJumpUpPal, "GFX/Character/Roocho/RoochoJumpUp4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert RoochoJumpUpTiles, "GFX/Character/Roocho/RoochoJumpUp4BPP.pic" // Include Sprite Tile Data (4096 Bytes) + +insert BeochiJumpUpPal, "GFX/Character/Beochi/BeochiJumpUp4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert BeochiJumpUpTiles, "GFX/Character/Beochi/BeochiJumpUp4BPP.pic" // Include Sprite Tile Data (4096 Bytes) + +insert ChitoJumpUpPal, "GFX/Character/Chito/ChitoJumpUp4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert ChitoJumpUpTiles, "GFX/Character/Chito/ChitoJumpUp4BPP.pic" // Include Sprite Tile Data (4096 Bytes) + +insert GolemJumpUpPal, "GFX/Character/Golem/GolemJumpUp4BPP.pal" // Include Sprite Palette Data (32 Bytes) +insert GolemJumpUpTiles, "GFX/Character/Golem/GolemJumpUp4BPP.pic" // Include Sprite Tile Data (4096 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.png b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.png new file mode 100644 index 00000000..3b7c59d5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.png differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.sfc b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.sfc new file mode 100644 index 00000000..194006c6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.sfc differ diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TecmoLogo.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TecmoLogo.asm new file mode 100644 index 00000000..d9bdd93f --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TecmoLogo.asm @@ -0,0 +1,71 @@ +//----------- +// Tecmo Logo +//----------- +LoadPAL(TecmoPal, $00, TecmoPal.size, 0) // Load Background Palette (BG Palette Uses 4 Colors) +LoadVRAM(TecmoTiles, $0000, TecmoTiles.size, 0) // Load Background Tiles To VRAM +LoadVRAM(TecmoMap, $F200, TecmoMap.size, 0) // Load Background Tile Map To VRAM + +LoadPAL(TecmoHiLightPal, $10, TecmoHiLightPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) +LoadVRAM(TecmoHiLightTiles, $2000, TecmoHiLightTiles.size, 0) // Load Background Tiles To VRAM +LoadVRAM(TecmoHiLightMap, $E200, TecmoHiLightMap.size, 0) // Load Background Tile Map To VRAM + +// Setup Video +lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 & BG2 16x8 Tiles + +lda.b #%00000001 // Interlace Mode On +sta.w REG_SETINI // $2133: Screen Mode Select + +// Setup BG1 16 Color Background & BG2 4 Color Background +lda.b #%01110010 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $E200 (VRAM Address / $400) +lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG2SC // $2108: BG2 64x32, BG2 Map Address = $F200 (VRAM Address / $400) +lda.b #%00000001 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address +sta.w REG_BG12NBA // $210B: BG1 Tile Address = $2000, BG2 Tile Address = $0000 (VRAM Address / $1000) + +lda.b #$03 // Enable BG1 & BG2 +sta.w REG_TM // $212C: BG1 & BG2 To Main Screen Designation +sta.w REG_TS // $212D: BG1 & BG2 To Sub Screen Designation (Needed To Show Interlace GFX) + +lda.b #$30 +sta.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte +stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + +lda.b #62 // Scroll BG 62 Pixels Up +sta.w REG_BG1VOFS // Store A To BG Scroll Vertical Position Lo Byte +stz.w REG_BG1VOFS // Store Zero To BG Scroll Vertical Position Hi Byte +sta.w REG_BG2VOFS // Store A To BG2 Vertical Scroll Position Lo Byte +stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Hi Byte + +// Show Tecmo Logo Animation +FadeIN() // Screen Fade In + +lda.b #180 // A = 180 +LoopHiLightStart: + WaitNMI() // Wait VBlank + dec // A-- + bne LoopHiLightStart // IF (A != 0) Loop HiLight Start + +lda.b #$30 // A = $30 +LoopHiLight: + WaitNMI() // Wait VBlank + sta.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + sec // Set Carry + sbc.b #4 // A -= 4 + cmp.b #$30 // Compare A To $30 + bne LoopHiLight // IF (A != $30) Loop HiLight + +lda.b #240 // A = 240 +LoopHiLightEnd: + WaitNMI() // Wait VBlank + dec // A-- + bne LoopHiLightEnd // IF (A != 0) Loop HiLight End + +FadeOUT() // Screen Fade Out + +lda.b #$80 +sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TitleScreen.asm b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TitleScreen.asm new file mode 100644 index 00000000..334e79e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/TitleScreen.asm @@ -0,0 +1,343 @@ +//------------- +// Title Screen +//------------- +LoadPAL(MonsterFarmJumpPal, $00, MonsterFarmJumpPal.size, 0) // Load Background Palette (BG Palette Uses 96 Colors) +LoadM7VRAM(MonsterFarmJumpMap, MonsterFarmJumpTiles, $0000, MonsterFarmJumpMap.size, MonsterFarmJumpTiles.size, 0) // Load Background Map & Tiles To VRAM + +LoadPAL(TecmoMiniPal, $80, TecmoMiniPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(TecmoMiniTiles, $8000, TecmoMiniTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(TecmoCopyrightPal, $90, TecmoCopyrightPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(TecmoCopyrightTiles, $8400, TecmoCopyrightTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(PressStartButtonPal, $A0, PressStartButtonPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(PressStartButtonTiles, $8C00, PressStartButtonTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(ComicAPal, $B0, ComicAPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ComicATiles, $C000, ComicATiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(ComicBPal, $C0, ComicBPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ComicBTiles, $E000, ComicBTiles.size, 0) // Load Sprite Tiles To VRAM + +LoadPAL(ComicCPal, $D0, ComicCPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ComicCTiles, $9000, ComicCTiles.size, 0) // Load BG/Sprite Tiles To VRAM + +LoadPAL(ComicDPal, $E0, ComicDPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(ComicDTiles, $A800, ComicDTiles.size, 0) // Load BG/Sprite Tiles To VRAM + +LoadPAL(ComicCPal, $60, ComicCPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) +LoadPAL(ComicDPal, $70, ComicDPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) +LoadVRAM(ComicCDMap, $8800, 768, 0) // Load Background Tile Map To VRAM + +// Clear OAM +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0080 +lda.b #$E0 +- + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + +ldx.w #$0020 +- + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + +// Title Screen OAM Info +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopTitleScreenOAM: + lda.w TitleScreenOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0050 + bne LoopTitleScreenOAM + +// Title Screen OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopTitleScreenOAMSize: + lda.w TitleScreenOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0055 + bne LoopTitleScreenOAMSize + +// Setup Video + // Interlace Mode Off +stz.w REG_SETINI // $2133: Screen Mode Select + +lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + +// Setup BG2 16 Color Background +lda.b #%01000100 // AAAAAASS: S = BG Map Size, A = BG Map Address +sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $8800 (VRAM Address / $400) +lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address +sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + +lda.b #%00010011 // Enable BG1 & Sprites +sta.w REG_TM // $212C: BG1 & Sprites To Main Screen Designation + +stz.w REG_M7SEL // $211A: Mode7 Settings + +lda.b #$80 +sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte +lda.b #$01 +sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte +stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + +lda.b #$B8 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte +lda.b #$01 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + +lda.b #127 // Scroll BG2 127 Pixels Up +sta.w REG_BG2VOFS // Store A To BG Scroll Position Low Byte +stz.w REG_BG2VOFS // Store Zero To BG Scroll Position High Byte + +stz.w REG_M7X // $211F: Mode7 Center Position X Lo Byte +lda.b #$02 +sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + +stz.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte +lda.b #$02 +sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + +stz.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand +stz.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand +stz.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) +stz.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + +// HDMA OAM Size & Object Base +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters +lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) +sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #TitleScreenHDMATableOAM1 // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address +lda.b #TitleScreenHDMATableOAM1 >> 16 // HDMA Table Bank +sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) +lda.b #%00000001 // HDMA Channel Select (Channel 0) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +FadeIN() // Screen Fade In + +// Zoom Title Logo +lda.b #$00 +TitleZoomOutInit: + WaitNMI() // Wait VBlank + sta.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + stz.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + sta.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + stz.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + inc // A++ + inc // A++ + bne TitleZoomOutInit + +// HDMA OAM Size & Object Base +ldx.w #TitleScreenHDMATableOAM2 // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + +// HDMA BG Mode & BG Character Size +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters +lda.b #REG_BGMODE // $05: Start At BG Mode & BG Character Size ($2105) +sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #TitleScreenHDMATableBG // HMDA Table Address +stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address +lda.b #TitleScreenHDMATableBG >> 16 // HDMA Table Bank +sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + +// HDMA Main Screen Designation +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters +lda.b #REG_TM // $2C: Start At Main Screen Designation ($212C) +sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #TitleScreenHDMATableTM // HMDA Table Address +stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address +lda.b #TitleScreenHDMATableBG >> 16 // HDMA Table Bank +sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + +lda.b #%00000111 // HDMA Channel Select (Channel 0..2) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +// Title Screen OAM Info +ldx.w #$0010 // X = $0010 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0000 // X = 0 +LoopTitleScreenForeGroundOAM: + lda.w TitleScreenForeGroundOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0070 + bne LoopTitleScreenForeGroundOAM + +// Title Screen OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopTitleScreenForeGroundOAMSize: + lda.w TitleScreenForeGroundOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$0079 + bne LoopTitleScreenForeGroundOAMSize + +ldx.w #$0000 // X = Zoom In / Out Scale +TitleZoomOut: + WaitNMI() // Wait VBlank + ReadJOY({JOY_START}) // Test START Button + beq TitleZoomOutAnim // IF (! START Pressed) Title Zoom Out Anim + jmp TitleScreenEnd // ELSE Title Screen End + + TitleZoomOutAnim: // Zoom Logo Out + txa // A = X + sta.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + lda.b #$01 + sta.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + txa // A = X + sta.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + lda.b #$01 + sta.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + inx // X++ + inx // X++ + cpx #$00C0 + bne TitleZoomOut + +TitleZoomIn: + WaitNMI() // Wait VBlank + ReadJOY({JOY_START}) // Test START Button + beq TitleZoomInAnim // IF (! START Pressed) Branch Down + jmp TitleScreenEnd // ELSE Title Screen End + + TitleZoomInAnim: // Zoom Logo In + txa // A = X + sta.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + lda.b #$01 + sta.w REG_M7A // $211B: Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand + txa // A = X + sta.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + lda.b #$01 + sta.w REG_M7D // $211E: Mode7 Rot/Scale D (COSINE B) + dex // X-- + dex // X-- + bne TitleZoomIn + bra TitleZoomOut + +TitleScreenHDMATableOAM1: + db 128, %10100011 // Repeat 128 Scanlines, Object Size = 32x32/64x64, Name = 0, Base = $C000 + db 1, %10100010 // Repeat 1 Scanlines, Object Size = 32x32/64x64, Name = 0, Base = $8000 + db 0 // End Of HDMA + +TitleScreenHDMATableOAM2: + db 128, %10100011 // Repeat 128 Scanlines, Object Size = 32x32/64x64, Name = 0, Base = $C000 + db 1, %00000010 // Repeat 1 Scanlines, Object Size = 8x8/16x16, Name = 0, Base = $8000 + db 0 // End Of HDMA + +TitleScreenHDMATableBG: + db 128, %00000111 // Repeat 128 Scanlines, BG Mode 7, Priority 0, BG1 8x8 Tiles + db 1, %00000011 // Repeat 1 Scanlines, BG Mode 3, Priority 0, BG2 8x8 Tiles + db 0 // End Of HDMA + +TitleScreenHDMATableTM: + db 128, %00010011 // Repeat 128 Scanlines, BG1 & Sprites To Main Screen Designation + db 1, %00010010 // Repeat 1 Scanlines, BG2 & Sprites To Main Screen Designation + db 0 // End Of HDMA + +TitleScreenOAM: + // 32x32 / 64x64 Sprites + // OAM Info (Comic A 128x128, Comic B 128x128) + db 0, 0, 0, %00000110 + db 64, 0, 8, %00000110 + db 128, 0, 0, %00001001 + db 192, 0, 8, %00001001 + + db 0, 64, 128, %00000110 + db 64, 64, 136, %00000110 + db 128, 64, 128, %00001001 + db 192, 64, 136, %00001001 + + // OAM Info (Comic C 128x96, Comic D 128x96) + db 0, 128, 128, %00001010 + db 64, 128, 136, %00001010 + db 128, 128, 64, %00001101 + db 192, 128, 72, %00001101 + + db 0, 192, 0, %00001011 + db 32, 192, 4, %00001011 + db 64, 192, 8, %00001011 + db 96, 192, 12, %00001011 + db 128, 192, 192, %00001101 + db 160, 192, 196, %00001101 + db 192, 192, 200, %00001101 + db 224, 192, 204, %00001101 + + // OAM Extra Info + db %10101010 + db %10101010 + db %10101010 + db %00000000 + db %00000000 + +TitleScreenForeGroundOAM: + // 8x8 / 16x16 Sprites + // OAM Info (Tecmo Mini 64x16) + db 96, 180, 0, %00000000 + db 112, 180, 2, %00000000 + db 128, 180, 4, %00000000 + db 144, 180, 6, %00000000 + + // OAM Info (Tecmo Copyright 136x16) + db 60, 200, 32, %00000010 + db 68, 200, 33, %00000010 + db 76, 200, 34, %00000010 + db 84, 200, 35, %00000010 + db 92, 200, 36, %00000010 + db 100, 200, 37, %00000010 + db 108, 200, 38, %00000010 + db 116, 200, 39, %00000010 + db 124, 200, 40, %00000010 + db 132, 200, 41, %00000010 + db 140, 200, 42, %00000010 + db 148, 200, 43, %00000010 + db 156, 200, 44, %00000010 + db 164, 200, 45, %00000010 + db 172, 200, 46, %00000010 + db 180, 200, 47, %00000010 + db 188, 200, 48, %00000010 + + // OAM Info (Press Start Button 112x16) + db 72, 144, 96, %00000100 + db 88, 144, 98, %00000100 + db 104, 144, 100, %00000100 + db 120, 144, 102, %00000100 + db 136, 144, 104, %00000100 + db 152, 144, 106, %00000100 + db 168, 144, 108, %00000100 + + // OAM Extra Info (Title Screen Fore Ground OAM Size) + db %10101010 + db %10101010 + db %10101010 + db %00000000 + db %00000000 + + db %00000000 + db %00000000 + db %10101000 + db %10101010 + +TitleScreenEnd: + FadeOUT() // Screen Fade Out + + lda.b #$80 + sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) + + stz.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/make.bat b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/make.bat new file mode 100644 index 00000000..6d421833 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Games/MonsterFarmJump/make.bat @@ -0,0 +1 @@ +bass MonsterFarmJump.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.asm b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.asm new file mode 100644 index 00000000..bc6d36dd --- /dev/null +++ b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.asm @@ -0,0 +1,263 @@ +// SNES "Super Mario Kart" 1500cc Hack by krom (Peter Lemon): +// Special thanks to Dirtbag for the SMK Mashup tool, for helping me get started + +arch snes.cpu +output "Super Mario Kart 1500cc.sfc", create +origin $000000; insert "Super Mario Kart (U) [!].sfc" // Include USA Super Mario Kart SNES ROM +origin $00FFC0 +db "SUPER MARIO KART 1500" // $00FFC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +//------ +// Text +//------ +// Character Table 1 +map '0', $00, 10 // Map Numbers +map 'A', $0A, 26 // Map English "Upper Case" Characters +map '?', $24 +map '.', $25 +map $2C, $26 // Comma ',' +map '!', $27 +map '\s', $28 // Single Quote "'" +map '\d', $29 // Double Quote '"' +map '_', $2A // 'cc' +map ' ', $2F + +// Character Color 1 +map 'b', $08 // Color: Blue +map 'p', $0A // Color: Purple +map 'g', $0C // Color: Green +map 'w', $20 // Color: White + +macro TextStyle1(OFFSET, TEXT) { + origin {OFFSET} // Offset + db {TEXT} // Text +} + +// Title Screen +TextStyle1($58449, "5b0b0b_bCbLbAbSbSb") // "500cc CLASS" +TextStyle1($5845B, "1p0p0p0p_pCpLpApSpSp") // "1000cc CLASS" +TextStyle1($5846F, "1g5g0g0g_gCgLgAgSgSg") // "1500cc CLASS" + +// Results Screen +origin $5BFA0 +dw $BFA8 // "500cc" Pointer +dw $BFB2 // "1000cc" Pointer +dw $BFA6 // "1500cc" Pointer +TextStyle1($5BFA6, "1w5w0w0w_w") ; dw $FFFF // "500cc/1500cc" +TextStyle1($5BFB2, "1w0w0w0w_w") ; dw $FFFF // "1000cc" + +// Character Table 2 +map 'A', $3680 // Map English "Upper Case" Characters +map 'B', $3682 +map 'C', $3684 +map 'D', $3686 +map 'E', $3688 +map 'F', $368A +map 'G', $368C +map 'H', $368E +map 'I', $3690 +map 'J', $3692 +map 'K', $3694 +map 'L', $3696 +map 'M', $3698 +map 'N', $369A +map 'O', $369C +map 'P', $369E +map 'Q', $36A0 +map 'R', $36A2 +map 'S', $36A4 +map 'T', $36A6 +map 'U', $36A8 +map 'V', $36AA +map 'W', $36AC +map 'X', $36AE +map 'Y', $36B0 +map 'Z', $36B2 +map '?', $36B4 +map '.', $36B6 +map $2C, $36B7 // Comma ',' +map '!', $36B8 +map '0', $3708 // Map Numbers +map '1', $370A +map '2', $370C +map '3', $370E +map '4', $3710 +map '5', $3712 +map '6', $3714 +map '7', $3716 +map '8', $3718 +map '9', $371A +map ' ', $E500 + +macro TextStyle2(OFFSET, TEXT) { + origin {OFFSET} // Offset + dw {TEXT} // Text +} + +// GP Select +TextStyle2($4F8EF, "500 CLASS") // 500cc CLASS +TextStyle2($4F903, "1000 CLASS") // 1000cc CLASS +TextStyle2($4F917, "1500 CLASS") // 1500cc CLASS + +// Character Table 3 +map '0', $80, 10 // Map Numbers +map 'A', $8A, 26 // Map English "Upper Case" Characters +map '?', $A4 +map '.', $A5 +map $2C, $A6 // Comma ',' +map '!', $A7 +map '\s', $A8 // Single Quote "'" +map '\d', $A9 // Double Quote '"' +map '_', $AA // 'cc' +map ' ', $AF + +// Character Color 3 +map 'w', $0F // Color: White + +// Podium Screen +origin $5A0C4 +dw $A0CC // "500cc" Pointer +dw $A0D8 // "1000cc" Pointer +dw $A0CA // "1500cc" Pointer +TextStyle1($5A0CA, "1w5w0w0w_w w") ; dw $FFFF // "500cc/1500cc" +TextStyle1($5A0D8, "1w0w0w0w_w w") ; dw $FFFF // "1000cc" + +//----------------- +// Kart Properties +//----------------- + +origin $018000 + +KartTopSpeed: + // ROM Kart Top Speed +dw 84<<4 // $018000 - Mario (FP12.4) (57.0: $0390) +dw 84<<4 // $018002 - Luigi (FP12.4) (57.0: $0390) +dw 86<<4 // $018004 - Bowser (FP12.4) (59.0: $03B0) +dw 82<<4 // $018006 - Princess (FP12.4) (55.0: $0370) +dw 86<<4 // $018008 - D.K.Jr (FP12.4) (59.0: $03B0) +dw 81<<4 // $01800A - Koopa (FP12.4) (54.0: $0360) +dw 81<<4 // $01800C - Toad (FP12.4) (54.0: $0360) +dw 82<<4 // $01800E - Yoshi (FP12.4) (55.0: $0370) + +KartAccelerationSpeed: + // ROM Kart Acceleration Speed +dw $8020 // $018010 - Mario (????) ($8020) +dw $8020 // $018012 - Luigi (????) ($8020) +dw $8050 // $018014 - Bowser (????) ($8050) +dw $8030 // $018016 - Princess (????) ($8030) +dw $8050 // $018018 - D.K.Jr (????) ($8050) +dw $8040 // $01801A - Koopa (????) ($8040) +dw $8040 // $01801C - Toad (????) ($8040) +dw $8030 // $01801E - Yoshi (????) ($8030) + +KartAccelerationCurve: + // ROM Kart Acceleration Curve +db 128,192,160,255,255,255,255,255,255,192,192, 96,96,32,32,24 // $018020 - Mario/Luigi (UINT8) (32, 96, 64,128,192,192,192,128,128, 64, 32, 24,16,8,4,4) +db 160,255,255,255,255,255,255,255,255,160,160,128,32,24,16,16 // $018030 - Princess/Yoshi (UINT8) (64,192,255,255,192,192,192,128,128, 64, 64, 32, 8,4,2,2) +db 160,160,192,255,255,255,255,255,255,160,160, 96,96,32,24,32 // $018040 - Koopa/Toad (UINT8) (64, 64, 96,128,128,192,192,128,128, 64, 32, 24,16,8,4,8) +db 128,128,128,128,160,160,192,192,255,255,255,255,64,64,32,32 // $018050 - Bowser/D.K.Jr (UINT8) (32, 32, 32, 32, 64, 64, 96, 96,128,128,160,160,16,8,8,8) + +KartUnknown01: + // ROM Kart *Unknown* +dw $8070 // $018060 - Mario (????) ($8070) +dw $8070 // $018062 - Luigi (????) ($8070) +dw $8076 // $018064 - Bowser (????) ($8076) +dw $807C // $018066 - Princess (????) ($807C) +dw $8076 // $018068 - D.K.Jr (????) ($8076) +dw $8082 // $01806A - Koopa (????) ($8082) +dw $8082 // $01806C - Toad (????) ($8082) +dw $807C // $01806E - Yoshi (????) ($807C) + +KartOffRoadSpeed: + // ROM Kart Off Road Speed (Dirt, Mud, Snow, Grass, Water, Mud Pool) +db 37,18,34,36,36,41 // $018070 - Mario/Luigi (UINT8) (37,18,34,36,36,41) +db 38,20,33,35,39,42 // $018076 - Bowser/D.K.Jr (UINT8) (38,20,33,35,39,42) +db 39,19,31,38,38,43 // $01807C - Princess/Yoshi (UINT8) (39,19,31,38,38,43) +db 40,21,32,37,37,44 // $018082 - Koopa/Toad (UINT8) (40,21,32,37,37,44) + +KartTurnInertia: + // ROM Kart Turn Inertia +dw $8098 // $018088 - Mario (????) ($8098) +dw $8098 // $01808A - Luigi (????) ($8098) +dw $80C5 // $01808C - Bowser (????) ($80C5) +dw $80A7 // $01808E - Princess (????) ($80A7) +dw $80C5 // $018090 - D.K.Jr (????) ($80C5) +dw $80B6 // $018092 - Koopa (????) ($80B6) +dw $80B6 // $018094 - Toad (????) ($80B6) +dw $80A7 // $018096 - Yoshi (????) ($80A7) + +KartHandlingNormalMarioLuigi: + // ROM Kart Handling Normal Mario/Luigi +dw 2753 // $018098 - Turn Rate (UINT16) (2453: $0995) +db 152 // $01809A - Control (UINT8) ( 152: $98) +db 104 // $01809B - Turning (UINT8) ( 104: $68) +db 112 // $01809C - Grip (UINT8) ( 112: $70) +KartHandlingUnknownMarioLuigi: + // ROM Kart Handling Unknown Mario/Luigi +dw 2988 // $01809D - Turn Rate (UINT16) (2688: $0A80) +db 160 // $01809F - Control (UINT8) ( 160: $A0) +db 120 // $0180A0 - Turning (UINT8) ( 120: $78) +db 128 // $0180A1 - Grip (UINT8) ( 128: $80) +KartHandlingSlidingMarioLuigi: + // ROM Kart Handling Sliding Mario/Luigi +dw 3116 // $0180A2 - Turn Rate (UINT16) (2816: $0B00) +db 176 // $0180A4 - Control (UINT8) ( 176: $B0) +db 136 // $0180A5 - Turning (UINT8) ( 136: $88) +db 144 // $0180A6 - Grip (UINT8) ( 144: $90) + +KartHandlingNormalPrincessYoshi: + // ROM Kart Handling Normal Princess/Yoshi +dw 2753 // $0180A7 - Turn Rate (UINT16) (2453: $0995) +db 152 // $0180A9 - Control (UINT8) ( 152: $98) +db 88 // $0180AA - Turning (UINT8) ( 88: $58) +db 128 // $0180AB - Grip (UINT8) ( 128: $80) +KartHandlingUnknownPrincessYoshi: + // ROM Kart Handling Unknown Princess/Yoshi +dw 2988 // $0180AC - Turn Rate (UINT16) (2688: $0A80) +db 160 // $0180AE - Control (UINT8) ( 160: $A0) +db 104 // $0180AF - Turning (UINT8) ( 104: $68) +db 112 // $0180B0 - Grip (UINT8) ( 112: $70) +KartHandlingSlidingPrincessYoshi: + // ROM Kart Handling Sliding Princess/Yoshi +dw 3116 // $0180B1 - Turn Rate (UINT16) (2816: $0B00) +db 176 // $0180B3 - Control (UINT8) ( 176: $B0) +db 112 // $0180B4 - Turning (UINT8) ( 112: $70) +db 128 // $0180B5 - Grip (UINT8) ( 128: $80) + +KartHandlingNormalKoopaToad: + // ROM Kart Handling Normal Koopa/Toad +dw 2604 // $0180B6 - Turn Rate (UINT16) (2304: $0900) +db 160 // $0180B8 - Control (UINT8) ( 160: $A0) +db 112 // $0180B9 - Turning (UINT8) ( 112: $70) +db 144 // $0180BA - Grip (UINT8) ( 144: $90) +KartHandlingUnknownKoopaToad: + // ROM Kart Handling Unknown Koopa/Toad +dw 2924 // $0180BB - Turn Rate (UINT16) (2624: $0A40) +db 176 // $0180BD - Control (UINT8) ( 176: $B0) +db 128 // $0180BE - Turning (UINT8) ( 128: $80) +db 160 // $0180BF - Grip (UINT8) ( 160: $A0) +KartHandlingSlidingKoopaToad: + // ROM Kart Handling Sliding Koopa/Toad +dw 3052 // $0180C0 - Turn Rate (UINT16) (2752: $0AC0) +db 160 // $0180C2 - Control (UINT8) ( 160: $A0) +db 144 // $0180C3 - Turning (UINT8) ( 144: $90) +db 192 // $0180C4 - Grip (UINT8) ( 192: $C0) + +KartHandlingNormalBowserDKJr: + // ROM Kart Handling Normal Bowser/D.K.Jr +dw 2604 // $0180C5 - Turn Rate (UINT16) (2304: $0900) +db 128 // $0180C7 - Control (UINT8) ( 128: $80) +db 88 // $0180C8 - Turning (UINT8) ( 88: $58) +db 136 // $0180C9 - Grip (UINT8) ( 136: $88) +KartHandlingUnknownBowserDKJr: + // ROM Kart Handling Unknown Bowser/D.K.Jr +dw 2924 // $0180CA - Turn Rate (UINT16) (2624: $0A40) +db 144 // $0180CC - Control (UINT8) ( 144: $90) +db 104 // $0180CD - Turning (UINT8) ( 104: $68) +db 152 // $0180CE - Grip (UINT8) ( 152: $98) +KartHandlingSlidingBowserDKJr: + // ROM Kart Handling Sliding Bowser/D.K.Jr +dw 3052 // $0180CF - Turn Rate (UINT16) (2752: $0AC0) +db 160 // $0180D1 - Control (UINT8) ( 160: $A0) +db 120 // $0180D2 - Turning (UINT8) ( 120: $78) +db 168 // $0180D3 - Grip (UINT8) ( 168: $A8) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.ips b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.ips new file mode 100644 index 00000000..47a83bb3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/Super Mario Kart 1500cc.ips differ diff --git a/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/make.bat b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/make.bat new file mode 100644 index 00000000..eb7d4ab5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Hack/Super Mario Kart 1500cc/make.bat @@ -0,0 +1,2 @@ +bass "Super Mario Kart 1500cc.asm" +ucon64 --nbak --chk "Super Mario Kart 1500cc.sfc" diff --git a/roms/snes/peter-lemon-snes/HelloWorld/Font8x8.asm b/roms/snes/peter-lemon-snes/HelloWorld/Font8x8.asm new file mode 100644 index 00000000..0e8d180c --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/Font8x8.asm @@ -0,0 +1,957 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.asm b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.asm new file mode 100644 index 00000000..93ed35dc --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.asm @@ -0,0 +1,60 @@ +// SNES "Hello, World!" Text Printing demo by krom (Peter Lemon): +// 1. DMA Loads Palette Data To CGRAM +// 2. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 3. DMA Clears VRAM Map To A Space " " Character +// 4. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "HelloWorld.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $3F8, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Text + LoadLOVRAM(HELLOWORLD, $F944, 13, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +HELLOWORLD: + db "Hello, World!" // Hello World Text + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1016 Bytes) +BGPAL: + dw $0000, $7FFF // Black / White Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.png b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.png new file mode 100644 index 00000000..26ea1896 Binary files /dev/null and b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.png differ diff --git a/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.sfc b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.sfc new file mode 100644 index 00000000..c59dc1e5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/HelloWorld/HelloWorld.sfc differ diff --git a/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES.INC b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..23206f92 --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HELLO WORLD TEXT DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/HelloWorld/make.bat b/roms/snes/peter-lemon-snes/HelloWorld/make.bat new file mode 100644 index 00000000..bf6d278b --- /dev/null +++ b/roms/snes/peter-lemon-snes/HelloWorld/make.bat @@ -0,0 +1 @@ +bass HelloWorld.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.asm b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.asm new file mode 100644 index 00000000..78f405d4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.asm @@ -0,0 +1,54 @@ +// SNES Controller Latency Demo by krom (Peter Lemon): +// Pushing any button turns the screen white +// When no buttons are pushed screen is black + +arch snes.cpu +output "ControllerLatency.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + stz.w REG_TM // $212C: Main Screen Designation + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + +InputLoop: + - // Wait For Vertical Blank + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + - // Read Controller + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + ldx.w REG_JOY1L // Read Joypad Register Word + beq DrawBlack // IF (Any Button Is Pressed) Draw White, ELSE Draw Black + + // Load White Background Palette Color + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%11111111 // Load White Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%01111111 // Load White Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + bra InputLoop + + DrawBlack: + // Load Black Background Palette Color + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%00000000 // Load Black Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%00000000 // Load Black Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + bra InputLoop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.png b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.png new file mode 100644 index 00000000..3ad5f730 Binary files /dev/null and b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.png differ diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.sfc b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.sfc new file mode 100644 index 00000000..d5118497 Binary files /dev/null and b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.sfc differ diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES.INC b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..c7215e8c --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "CONTROLLER LATENCY " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/make.bat b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/make.bat new file mode 100644 index 00000000..fdce8700 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/ControllerLatency/make.bat @@ -0,0 +1,2 @@ +bass ControllerLatency.asm +ucon64 --nbak --chk ControllerLatency.sfc \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/Font8x8.asm b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/Font8x8.asm new file mode 100644 index 00000000..a13eefc6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/Font8x8.asm @@ -0,0 +1,967 @@ +fill 8*$20 // Fill Characters 0 to $1F With Zero Bytes + +// $20: Space " " +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $21: Exclamation mark "!" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00000000 +db %00000000 + +// $22: Quotation mark """ +db %01100110 +db %01100110 +db %01000100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $23: Cross hatch "#" +db %00010100 +db %00010100 +db %01111110 +db %00101000 +db %01111110 +db %00101000 +db %00000000 +db %00000000 + +// $24: Dollar sign "$" +db %00111100 +db %01101010 +db %01111100 +db %00111110 +db %01010110 +db %00111100 +db %00010000 +db %00000000 + +// $25: Percent sign "%" +db %00100010 +db %01010100 +db %00101000 +db %00010100 +db %00101010 +db %01000100 +db %00000000 +db %00000000 + +// $26: Ampersand "&" +db %00110000 +db %01001000 +db %00110010 +db %01001100 +db %01001100 +db %00110010 +db %00000000 +db %00000000 + +// $27: Closing single quote "'" +db %00011000 +db %00011000 +db %00010000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $28: Opening parentheses "(" +db %00001100 +db %00011000 +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00011000 +db %00001100 + +// $29: Closing parentheses ")" +db %00110000 +db %00011000 +db %00001100 +db %00001100 +db %00001100 +db %00001100 +db %00011000 +db %00110000 + +// $2A: Asterisk "*" +db %00011000 +db %01111110 +db %00011000 +db %00100100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2B: Plus "+" +db %00000000 +db %00011000 +db %00011000 +db %01111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2C: Comma "," +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $2D: Hyphen "-" +db %00000000 +db %00000000 +db %00000000 +db %00111100 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $2E: Period "." +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $2F: Forward slash "/" +db %00000010 +db %00000110 +db %00001100 +db %00011000 +db %00110000 +db %01100000 +db %01000000 +db %00000000 + +////////////////////////////////////////// +// $30: 0 +db %00111010 +db %01100100 +db %01001010 +db %01010010 +db %00100110 +db %01011100 +db %00000000 +db %00000000 + +// $31: 1 +db %00011000 +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00111100 +db %00000000 +db %00000000 + +// $32: 2 +db %00111000 +db %01001100 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +// $33: 3 +db %00111100 +db %01000110 +db %00011100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $34: 4 +db %00001100 +db %00011100 +db %00101100 +db %01001100 +db %01111110 +db %00001100 +db %00000000 +db %00000000 + +// $35: 5 +db %01111110 +db %01100000 +db %01111100 +db %00000110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $36: 6 +db %00111100 +db %01100000 +db %01111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $37: 7 +db %01111110 +db %01100110 +db %00001100 +db %00111110 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $38: 8 +db %00111100 +db %01100110 +db %00111100 +db %01100110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $39: 9 +db %00111100 +db %01100110 +db %01100110 +db %00111110 +db %00000110 +db %00111100 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $3A: Colon ":" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $3B: Semicolon ";" +db %00000000 +db %00011000 +db %00011000 +db %00000000 +db %00011000 +db %00011000 +db %00010000 +db %00000000 + +// $3C: Less than sign "<" +db %00000000 +db %00000110 +db %00011000 +db %01100000 +db %00011000 +db %00000110 +db %00000000 +db %00000000 + +// $3D: Equals sign "=" +db %00000000 +db %00000000 +db %01111110 +db %00000000 +db %01111110 +db %00000000 +db %00000000 +db %00000000 + +// $3E: Greater than sign ">" +db %00000000 +db %01100000 +db %00011000 +db %00000110 +db %00011000 +db %01100000 +db %00000000 +db %00000000 + +// $3F: Question mark "?" +db %00111100 +db %01100110 +db %01100110 +db %00001100 +db %00011000 +db %00000000 +db %00011000 +db %00000000 + +// $40: At sign "@" +db %01111100 +db %10000010 +db %10111010 +db %10101010 +db %10111110 +db %01000000 +db %00111110 +db %00000000 + +////////////////////////////////////////// +// $41: A +db %00011000 +db %00111100 +db %00100100 +db %01111110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $42: B +db %01111100 +db %01100110 +db %01111100 +db %01100110 +db %01100110 +db %01111100 +db %00000000 +db %00000000 + +// $43: C +db %00111100 +db %01100110 +db %01100000 +db %01100010 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $44: D +db %01111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %01111100 +db %00000000 +db %00000000 + +// $45: E +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $46: F +db %01111110 +db %01100000 +db %01111100 +db %01100000 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $47: G +db %00111100 +db %01100110 +db %01100000 +db %01101110 +db %01100110 +db %00111100 +db %00000000 +db %00000000 + +// $48: H +db %01100110 +db %01100110 +db %01111110 +db %01100110 +db %01100110 +db %01100110 +db %00000000 +db %00000000 + +// $49: I +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4A: J +db %00111110 +db %00001100 +db %00001100 +db %01001100 +db %01111100 +db %00111000 +db %00000000 +db %00000000 + +// $4B: K +db %01100110 +db %01101100 +db %01111000 +db %01111000 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $4C: L +db %01100000 +db %01100000 +db %01100000 +db %01100000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +// $4D: M +db %01000010 +db %01100110 +db %01111110 +db %01011010 +db %01011010 +db %01000010 +db %00000000 +db %00000000 + +// $4E: N +db %01000110 +db %01100110 +db %01110110 +db %01111110 +db %01101110 +db %01100110 +db %00000000 +db %00000000 + +// $4F: O +db %00111100 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $50: P +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $51: Q +db %00111100 +db %01100110 +db %01100010 +db %01101010 +db %01111110 +db %00111100 +db %00000010 +db %00000000 + +// $52: R +db %01111100 +db %01100110 +db %01111110 +db %01111100 +db %01101100 +db %01100110 +db %00000000 +db %00000000 + +// $53: S +db %00111100 +db %01100010 +db %01111100 +db %00111110 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $54: T +db %01111110 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $55: U +db %01100110 +db %01100110 +db %01100110 +db %01100110 +db %01111110 +db %00111100 +db %00000000 +db %00000000 + +// $56: V +db %01100110 +db %01100110 +db %01100110 +db %00100100 +db %00111100 +db %00011000 +db %00000000 +db %00000000 + +// $57: W +db %01000010 +db %01011010 +db %01011010 +db %01111110 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $58: X +db %01100110 +db %00111100 +db %00011000 +db %00111100 +db %01100110 +db %01000010 +db %00000000 +db %00000000 + +// $59: Y +db %01100110 +db %01100110 +db %00111100 +db %00011000 +db %00011000 +db %00011000 +db %00000000 +db %00000000 + +// $5A: Z +db %01111110 +db %00001100 +db %00011000 +db %00110000 +db %01111110 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $5B: Opening square bracket "[" +db %00011100 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011100 + +// $5C: Back slash "\" +db %01000000 +db %01100000 +db %00110000 +db %00011000 +db %00001100 +db %00000110 +db %00000010 +db %00000000 + +// $5D: Closing square bracket "]" +db %00111000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00111000 + +// $5E: Caret "^" +db %00011000 +db %00100100 +db %01000010 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +// $5F: Underscore "_" +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %11111111 + +// $60: Opening single quote "`" +db %00011000 +db %00011000 +db %00001000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $61: a +db %00000000 +db %00000000 +db %00111000 +db %01100100 +db %01100100 +db %00111010 +db %00000000 +db %00000000 + +// $62: b +db %00110000 +db %00110000 +db %00111100 +db %00110010 +db %00110010 +db %01011100 +db %00000000 +db %00000000 + +// $63: c +db %00000000 +db %00000000 +db %00111100 +db %01100000 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $64: d +db %00001100 +db %00001100 +db %00111100 +db %01001100 +db %01001100 +db %00111010 +db %00000000 +db %00000000 + +// $65: e +db %00000000 +db %00000000 +db %00111000 +db %01101000 +db %01110010 +db %00111100 +db %00000000 +db %00000000 + +// $66: f +db %00000000 +db %00000000 +db %00011100 +db %00110010 +db %00110000 +db %01111100 +db %00110000 +db %00110000 + +// $67: g +db %00000000 +db %00000000 +db %00111010 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $68: h +db %01100000 +db %01100000 +db %01111100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $69: i +db %00110000 +db %00000000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6A: j +db %00000110 +db %00000000 +db %00000110 +db %00000110 +db %00000110 +db %00000110 +db %01000110 +db %00111100 + +// $6B: k +db %01100000 +db %01100100 +db %01101000 +db %01111000 +db %01100100 +db %01100010 +db %00000000 +db %00000000 + +// $6C: l +db %00110000 +db %00110000 +db %00110000 +db %00110000 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $6D: m +db %00000000 +db %00000000 +db %01010100 +db %01101010 +db %01101010 +db %01100010 +db %00000000 +db %00000000 + +// $6E: n +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100010 +db %01100010 +db %00000000 +db %00000000 + +// $6F: o +db %00000000 +db %00000000 +db %00111100 +db %01100010 +db %01100010 +db %00111100 +db %00000000 +db %00000000 + +// $70: p +db %00000000 +db %00000000 +db %01011100 +db %01100110 +db %01100110 +db %01111100 +db %01100000 +db %01100000 + +// $71: q +db %00000000 +db %00000000 +db %00110100 +db %01001100 +db %01001100 +db %00111100 +db %00001110 +db %00001100 + +// $72: r +db %00000000 +db %00000000 +db %01011100 +db %01100010 +db %01100000 +db %01100000 +db %00000000 +db %00000000 + +// $73: s +db %00000000 +db %00111100 +db %01100010 +db %00011000 +db %01000110 +db %00111100 +db %00000000 +db %00000000 + +// $74: t +db %00110000 +db %00110000 +db %01111000 +db %00110000 +db %00110010 +db %00011100 +db %00000000 +db %00000000 + +// $75: u +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111010 +db %00000000 +db %00000000 + +// $76: v +db %00000000 +db %00000000 +db %01100010 +db %01100010 +db %00110100 +db %00011000 +db %00000000 +db %00000000 + +// $77: w +db %00000000 +db %00000000 +db %01000010 +db %01011010 +db %01011010 +db %00101100 +db %00000000 +db %00000000 + +// $78: x +db %00000000 +db %00000000 +db %01100010 +db %00110100 +db %00011000 +db %01100110 +db %00000000 +db %00000000 + +// $79: y +db %00000000 +db %00000000 +db %01100110 +db %01100110 +db %01100110 +db %00111110 +db %01000110 +db %00111100 + +// $7A: z +db %00000000 +db %00000000 +db %01111110 +db %00001100 +db %00110000 +db %01111110 +db %00000000 +db %00000000 + +////////////////////////////////////////// +// $7B: Opening curly bracket "{" +db %00011100 +db %00110000 +db %00110000 +db %00011000 +db %00011000 +db %00110000 +db %00110000 +db %00011100 + +// $7C: Vertical line "|" +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 +db %00011000 + +// $7D: Closing curly bracket "{" +db %00111000 +db %00001100 +db %00001100 +db %00011000 +db %00011000 +db %00001100 +db %00001100 +db %00111000 + +// $7E: Tilde "~" +db %00000000 +db %00000000 +db %01110000 +db %01011010 +db %00001110 +db %00000000 +db %00000000 +db %00000000 + +// $7F: Cursor +db %11111111 +db %11111111 +db %11111111 +db %11111111 +db %11111111 +db %11111111 +db %11111111 +db %11111111 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES.INC b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..435eda5a --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "X-BAND KEYBOARD INPUT" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.asm b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.asm new file mode 100644 index 00000000..9c2bfea4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.asm @@ -0,0 +1,347 @@ +// SNES Input X-Band Keyboard Text Printing demo by krom (Peter Lemon): +// 1. DMA Loads Palette Data To CGRAM +// 2. DMA Loads 1BPP Character Tile Data To VRAM (Converts to 2BPP Tiles) +// 3. DMA Clears VRAM Map To A Space " " Character +// 4. Load X-Band Keyboard Buffer With Scancodes +// 5. DMA Prints Text Characters To Lo Bytes Of Map +arch snes.cpu +output "XBandKeyboard.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +constant TEXTCURSOR($7F) // Text Cursor Character Tile # + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +KeyboardBuffer: + fill 16 // X-Band Keyboard Buffer (16 Bytes) +CURSORPOS: + dw 0 // Cursor VRAM Map Position Word +CURSORCOUNT: + db 0 // Cursor Refresh Count +TEXTCOUNT: + db 0 // Text Refresh Count (Used For Delay & Repeat Rate) +KEYSCANCODE: + db 0 // Key Scancode (0 = Key Released) +KEYFLAGS: + db 0 // Bit 0 = Shift State (0 = Shift Released, 1 = Shift On), Bit 1 = CAPSLOCK State (0 = CAPSLOCK Off, 1 = CAPSLOCK On) + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Init Variable Data + ldx.w #$F8C4 >> 1 // Reset Cursor VRAM Map Position + lda.b #$F0 // A = $F0 + sta.b $01 // Initialize Keys To Released State + stx.b CURSORPOS // Store CURSORPOS + stz.b CURSORCOUNT // Rest CURSORCOUNT + stz.b TEXTCOUNT // Reset TEXTCOUNT + stz.b KEYSCANCODE // Reset KEYSCANCODE + stz.b KEYFLAGS // Reset KEYFLAGS + + // Init VRAM Data + LoadPAL(BGPAL, $00, 4, 0) // Load BG Palette Data + LoadLOVRAM(BGCHR, $0000, $400, 0) // Load 1BPP Tiles To VRAM Lo Bytes (Converts To 2BPP Tiles) + ClearVRAM(BGCLEAR, $F800, $400, 0) // Clear VRAM Map To Fixed Tile Word + + // Print Text + LoadLOVRAM(TITLETEXT, $F884, 27, 0) // Load Text To VRAM Lo Bytes + + // Setup Video + lda.b #%00001000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 1, BG1 8x8 Tiles + + // Setup BG1 4 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2108: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + WaitNMI() // Wait For Vertical Blank + + ReadXBAND() // Read X-Band Keyboard ScanCodes To WRAM ($01..$0F) + + // Key Release + lda.b $01 // A = MEM[$01] (Keyboard Buffer Scancode) + cmp.b #$F0 // Compare MEM[$01] To Normal/Special Key Released Code + bne KeyPressed // IF (ScanCode != $F0) Key Pressed + stz.b TEXTCOUNT // Store Zero To TEXTCOUNT + stz.b KEYSCANCODE // Store Zero To KEYSCANCODE + lda.b $02 // A = MEM[$02] (Keyboard Buffer Scancode) + LeftShiftRelease: + cmp.b #$12 // Compare MEM[$02] To Left-SHIFT Key Code + bne RightShiftRelease + lda.b #$01 // A = Shift Bit + trb.b KEYFLAGS // KEYFLAGS: Reset Shift Bit 0 (Shift Released) + jmp SkipChar + RightShiftRelease: + cmp.b #$59 // Compare MEM[$02] To Right-SHIFT Key Code + bne NormalKeyReleased + lda.b #$01 // A = Shift Bit + trb.b KEYFLAGS // KEYFLAGS: Reset Shift Bit 0 (Shift Released) + jmp SkipChar + NormalKeyReleased: + jmp SkipChar + + KeyPressed: // A Key Has Been Pressed + cmp.b KEYSCANCODE // Compare A With Key Scancode + bne KeyDelay // IF (A != Key Scancode) Key Delay + + lda.b TEXTCOUNT // IF (TEXTCOUNT == 0) + beq KeyRepeat // Key Repeat Press + dec.b TEXTCOUNT // ELSE TEXTCOUNT-- + jmp SkipChar // Skip Character + KeyDelay: + sta.b KEYSCANCODE // Key Scancode = A + lda.b #32 // TEXTCOUNT = 32 (Delay Rate) + jmp KeyEnd + KeyRepeat: + lda.b #4 // TEXTCOUNT = 4 (Repeat Rate) + KeyEnd: + sta.b TEXTCOUNT // Store TEXTCOUNT Delay/Repeat Rate + + lda.b KEYSCANCODE // A = Keyboard Scancode + + cmp.b #$E0 // Compare A To Special Key Code + bne CancelKey + jmp SkipChar + + CancelKey: + cmp.b #$76 // Compare A To Cancel Key Pressed Code + bne SwitchKey + jmp SkipChar + + SwitchKey: + cmp.b #$0D // Compare A To Switch Key Pressed Code + bne LeftCtrlKey + jmp SkipChar + + LeftCtrlKey: + cmp.b #$11 // Compare A To Left Ctrl Key Pressed Code + bne RightCtrlKey + jmp SkipChar + + RightCtrlKey: + cmp.b #$14 // Compare A To Right Ctrl Key Pressed Code + bne BackSpace + jmp SkipChar + + BackSpace: + cmp.b #$66 // Compare A To BackSpace Key Pressed Code + bne ReturnKey + ldx.b CURSORPOS // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + lda.b #$20 // A = Space " " Ascii Character + sta.w REG_VMDATAL // $2118: VRAM Write Lo Byte + dex // CURSORPOS-- + stx.b CURSORPOS // Store Cursor Position + jmp SkipChar + + ReturnKey: + cmp.b #$5A // Compare A To Return Key Pressed Code + bne LeftShiftKey + ldx.b CURSORPOS // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + lda.b #$20 // A = Space " " Ascii Character + sta.w REG_VMDATAL // $2118: VRAM Write Lo Byte + lda.b CURSORPOS // Set Cursor Position To Start of Current Row + and.b #$E0 + sta.b CURSORPOS + lda.b #34 // Increment Cursor Position 34 Times (+= 34) + ldx.b CURSORPOS // X = Cursor Position + LoopReturn: + inx // X++ + dec // A-- + bne LoopReturn + cpx.w #$7F42 // Compare Cursor Position To Bottom Of Page + bne ReturnEnd // IF (Cursor Position != Bottom Of Page) Return End + ldx.w #$7F22 // ELSE Cursor Position = $7F22 + ReturnEnd: + stx.b CURSORPOS // Store Cursor Position + jmp SkipChar + + LeftShiftKey: + cmp.b #$12 // Compare A To Left-SHIFT Key Code + bne RightShiftKey + lda.b #$01 // A = Shift Bit + tsb.b KEYFLAGS // KEYFLAGS: Set Shift Bit 0 (Shift On) + jmp SkipChar + + RightShiftKey: + cmp.b #$59 // Compare A To Right-SHIFT Key Code + bne CAPSLOCK + lda.b #$01 // A = KEYFLAGS: Shift Bit + tsb.b KEYFLAGS // KEYFLAGS: Set Shift Bit 0 (Shift On) + jmp SkipChar + + CAPSLOCK: + cmp.b #$58 // Compare A To CAPSLOCK Key Code + bne NormalKey + lda.b #$02 // A = KEYFLAGS: CAPSLOCK Bit + tsb.b KEYFLAGS // KEYFLAGS: Test & Set CAPSLOCK Bit 1 (CAPSLOCK On) + beq CAPSLOCKEnd // IF (Test == 0) CAPSLOCK End + trb.b KEYFLAGS // ELSE KEYFLAGS: Reset CAPSLOCK Bit 1 (CAPSLOCK Off) + CAPSLOCKEnd: + jmp SkipChar + + NormalKey: + lda.b KEYSCANCODE // A = X-Band Shift Ascii Map Offset + tax // X = A + lda.b KEYFLAGS // A = KEYFLAGS + bit.b #$01 // Test Bit 0 (Shift State) + bne ShiftOn // IF (KEYFLAGS.BIT0 != 0) Shift On + bit.b #$02 // Test Bit 1 (CAPSLOCK State) + bne CAPSOn // IF (KEYFLAGS.BIT1 != 0) CAPSLOCK On + lda.w XBANDASCIIMAP,x // Load Ascii Character From Map + sta.b $00 // Store Ascii Character to MEM[$00] + jmp PrintChar + + ShiftOn: + bit.b #$02 // Test Bit 1 (CAPSLOCK State) + bne ShiftCAPSOn // IF (KEYFLAGS.BIT1 != 0) Shift & CAPSLOCK On + lda.w XBANDSHIFTASCIIMAP,x // Load Ascii Character From Map + sta.b $00 // Store Ascii Character to MEM[$00] + jmp PrintChar + + CAPSOn: + lda.w XBANDCAPSASCIIMAP,x // Load Ascii Character From Map + sta.b $00 // Store Ascii Character to MEM[$00] + jmp PrintChar + + ShiftCAPSOn: + lda.w XBANDSHIFTCAPSASCIIMAP,x // Load Ascii Character From Map + sta.b $00 // Store Ascii Character to MEM[$00] + + PrintChar: // Print Character To VRAM Lo Byte + ldx.b CURSORPOS // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + lda.b $00 // A = Ascii Character + sta.w REG_VMDATAL // $2118: VRAM Write Lo Byte + inx // CURSORPOS++ + stx.b CURSORPOS // Store Cursor Position + SkipChar: + + + // Cursor + ldx.b CURSORPOS // Set VRAM Destination + + CursorTop: + cpx.w #$7C41 + bne CursorBottom + inx + stx.b CURSORPOS // Store Cursor Position + jmp CURSORON + CursorBottom: + cpx.w #$7F3E + bne CursorLeftRight + dex + stx.b CURSORPOS // Store Cursor Position + jmp CURSORON + + CursorLeftRight: + txa // A = X (Lo Byte) + and.b #$1F + CursorLeftDetect: + cmp.b #$01 + beq CursorLeft + jmp CursorRightDetect + CursorLeft: + dex + dex + dex + dex + stx.b CURSORPOS // Store Cursor Position + CursorRightDetect: + cmp.b #$1E + beq CursorRight + jmp CURSORON + CursorRight: + inx + inx + inx + inx + stx.b CURSORPOS // Store Cursor Position + + CURSORON: + stx.w REG_VMADDL // $2116: VRAM + lda.b #$0F + cmp.b CURSORCOUNT + bpl CURSOROFF + lda.b #TEXTCURSOR // A = Text Cursor Character + jmp CURSOREND + CURSOROFF: + lda.b #$20 // A = Space " " Character (Clear Cursor) + CURSOREND: + sta.w REG_VMDATAL // $2118: VRAM Write Lo Byte + inc.b CURSORCOUNT // Cursor Refresh Count++ + lda.b #$1F // A = $1F + and.b CURSORCOUNT // Cursor Refresh Count &= $1F + sta.b CURSORCOUNT // Store Cursor Refresh Count + + jmp Loop + +XBANDASCIIMAP: + db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, "`", $00 + db $00, $00, $00, $00, $00, "q", "1", $00, $00, $00, "z", "s", "a", "w", "2", $00 + db $00, "c", "x", "d", "e", "4", "3", $00, $00, " ", "v", "f", "t", "r", "5", $00 + db $00, "n", "b", "h", "g", "y", "6", $00, $00, $00, "m", "j", "u", "7", "8", $00 + db $00, ",", "k", "i", "o", "0", "9", $00, $00, ".", "/", "l", ";", "p", "-", $00 + db $00, $00, $27, $00, "[", "=", $00, $00, $00, $00, $00, "]", $00, "\", $00, $00 + db $00, $00, $00, $00, $00, $00, " ", $00, $00, $00, $00, $00, $00, $00, $00, $00 + +XBANDCAPSASCIIMAP: + db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, "`", $00 + db $00, $00, $00, $00, $00, "Q", "1", $00, $00, $00, "Z", "S", "A", "W", "2", $00 + db $00, "C", "X", "D", "E", "4", "3", $00, $00, " ", "V", "F", "T", "R", "5", $00 + db $00, "N", "B", "H", "G", "Y", "6", $00, $00, $00, "M", "J", "U", "7", "8", $00 + db $00, ",", "K", "I", "O", "0", "9", $00, $00, ".", "/", "L", ";", "P", "-", $00 + db $00, $00, $27, $00, "[", "=", $00, $00, $00, $00, $00, "]", $00, "\", $00, $00 + db $00, $00, $00, $00, $00, $00, " ", $00, $00, $00, $00, $00, $00, $00, $00, $00 + +XBANDSHIFTASCIIMAP: + db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, "~", $00 + db $00, $00, $00, $00, $00, "Q", "!", $00, $00, $00, "Z", "S", "A", "W", "@", $00 + db $00, "C", "X", "D", "E", "$", "#", $00, $00, " ", "V", "F", "T", "R", "%", $00 + db $00, "N", "B", "H", "G", "Y", "^", $00, $00, $00, "M", "J", "U", "&", "*", $00 + db $00, "<", "K", "I", "O", ")", "(", $00, $00, ">", "?", "L", ":", "P", "_", $00 + db $00, $00, $22, $00, "{", "+", $00, $00, $00, $00, $00, "}", $00, "|", $00, $00 + db $00, $00, $00, $00, $00, $00, " ", $00, $00, $00, $00, $00, $00, $00, $00, $00 + +XBANDSHIFTCAPSASCIIMAP: + db $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, "~", $00 + db $00, $00, $00, $00, $00, "q", "!", $00, $00, $00, "z", "s", "a", "w", "@", $00 + db $00, "c", "x", "d", "e", "$", "#", $00, $00, " ", "v", "f", "t", "r", "%", $00 + db $00, "n", "b", "h", "g", "y", "^", $00, $00, $00, "m", "j", "u", "&", "*", $00 + db $00, "<", "k", "i", "o", ")", "(", $00, $00, ">", "?", "l", ":", "p", "_", $00 + db $00, $00, $22, $00, "{", "+", $00, $00, $00, $00, $00, "}", $00, "|", $00, $00 + db $00, $00, $00, $00, $00, $00, " ", $00, $00, $00, $00, $00, $00, $00, $00, $00 + +TITLETEXT: + db "X-Band Keyboard Input Test:" // Title Text + +BGCHR: + include "Font8x8.asm" // Include BG 1BPP 8x8 Tile Font Character Data (1024 Bytes) +BGPAL: + dw $7FFF, $0000 // White / Black Palette (4 Bytes) +BGCLEAR: + dw $0020 // BG Clear Character Space " " Fixed Word \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.png b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.png new file mode 100644 index 00000000..e35068b7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.png differ diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.sfc b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.sfc new file mode 100644 index 00000000..96f8f377 Binary files /dev/null and b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.sfc differ diff --git a/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/make.bat b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/make.bat new file mode 100644 index 00000000..84263d27 --- /dev/null +++ b/roms/snes/peter-lemon-snes/INPUT/XBandKeyboard/make.bat @@ -0,0 +1 @@ +bass XBandKeyboard.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES.INC b/roms/snes/peter-lemon-snes/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_GSU.INC b/roms/snes/peter-lemon-snes/LIB/SNES_GSU.INC new file mode 100644 index 00000000..c55e5f8e --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_GSU.INC @@ -0,0 +1,118 @@ +//========== +// SNES GSU +//========== +// GSU Memory Map (SNES) +// $00..$3F/$80..$BF:$6000..$7FFF: Mirror Of $70:$0000..$1FFF (1st 8KB Of Game PAK RAM) +// $70..$71:$0000..$FFFF: Game Pak RAM (128KB Max, Usually 32KB Or 64KB) +// $78..$79:$0000..$FFFF: Additional Backup RAM (128KB Max, Usually None) + +// GSU Memory Map (GSU) +// $00..$3F:$0000..$7FFF: Mirror of LoROM at 00-3F:8000-FFFF (for "GETB R15" vectors) +// $00..$3F:$8000..$FFFF: Game PAK ROM In LoROM Mapping (2MB Max) +// $40..$5F:$0000..$FFFF: Game PAK ROM In HiROM Mapping (Mirror Of Above 2MB) +// $70..$71:$0000..$FFFF: Game PAK RAM (128KB Max, Usually 32KB Or 64KB) +// PBR:$0000..$01FF: Code-Cache (Manually Stored Opcodes) +// PBR Can Be Set To ROM/RAM/Cache Regions, ROMBR Only To ROM Region ($00..$5F), RAMBR Only To RAM Region ($70..$71) + +// GSU CPU Registers - Access From SNES CPU For R0..R15 (Read/Write, 2 Byte) +// (During GSU Operation, Only SFR, SCMR, & VCR May Be Accessed From SNES CPU) +constant GSU_R0($3000) // GSU R0: Default Source/Destination Register +constant GSU_R1($3002) // GSU R1: PLOT Instruction (X Coordinate) +constant GSU_R2($3004) // GSU R2: PLOT Instruction (Y Coordinate) +constant GSU_R3($3006) // GSU R3: General Purpose Register +constant GSU_R4($3008) // GSU R4: LMULT Instruction (Lower 16-Bit Result) +constant GSU_R5($300A) // GSU R5: General Purpose Register +constant GSU_R6($300C) // GSU R6: FMULT & LMULT Instructions, Multiplier +constant GSU_R7($300E) // GSU R7: MERGE Instruction (Source 1) +constant GSU_R8($3010) // GSU R8: MERGE Instruction (Source 2) +constant GSU_R9($3012) // GSU R9: General Purpose Register +constant GSU_R10($3014) // GSU R10: General Purpose Register (Conventionally Stack Pointer) +constant GSU_R11($3016) // GSU R11: LINK Instruction Destination Register (Used For Return Address) +constant GSU_R12($3018) // GSU R12: LOOP Instruction Counter Register +constant GSU_R13($301A) // GSU R13: LOOP Instruction Branch Address Register +constant GSU_R14($301C) // GSU R14: Gamepak ROM Address Pointer For GETXX Opcodes +constant GSU_R15($301E) // GSU R15: Program Counter (Write MSB To Start Operation) + +// GSU Pixel Registers - SNES CPU Access Disabled For COLR & POR Registers (1 Byte) +constant GSU_COLR($0000) // GSU COLR: Color Register (%PPPPPPPP: P = Palette Entry Used By Plot Instruction) (GSU Access Uses COLOR & GETC Instructions) +constant GSU_POR($0000) // GSU POR: Plot Option Register (GSU Access Uses CMODE Instruction) +// GSU Plot Option Register Flags: (%---OFHDT: O = Sprite Mode, F = Freeze Upper 4-Bit, H = Upper 4-Bit Color, D = Dither, T = Transparency) +constant GSU_POR_OPAQUE($01) // GSU Plot Option Bit 0: Transparency To Plot Color 0 (0 = Don't Plot Color 0 (Transparency On), 1 = Plot Color 0) +constant GSU_POR_DITHER($02) // GSU Plot Option Bit 1: Dither (0 = Off, 1 = On) (4BPP Only: IF (R1 & 1 == R2 & 1) Plot Lower 4-Bit Of Color Register, ELSE Plot Upper 4-Bit Of Color Register) +constant GSU_POR_COLOR_SRC_HIGH($04) // GSU Plot Option Bit 2: Upper 4-Bit Color (0 = Off, 1 = On) (4BPP, Or 8BPP With F Set) When Enabled, Upper 4-Bit In Source Register Stored To Lower 4-Bit, When Using COLOR & GETC (Allows Data For 2 Pixels, Stored In 1 Byte) +constant GSU_POR_FIX_HIGH_4BITS($08) // GSU Plot Option Bit 3: Freeze Upper 4-Bit (0 = Off, 1 = On) (8BPP Only) Locks Upper 4-Bit Color Register While Processing COLOR & GETC, & Change Lower 4-Bit Only +constant GSU_POR_OBJ($10) // GSU Plot Option Bit 4: Sprite Mode To Specify Bitmap (0 = Off, 1 = Specify Bitmap In Sprite Mode) + +// GSU Status/Flag Register - Access From SNES CPU (Read/Write, 2 Byte) +constant GSU_SFR($3030) // GSU Status/Flag Register +// GSU Status/Flag Register Flags: (%I--BHL21-RGVSCZ-: I = Interrupt, B = Prefix (MOVE/MOVES), H = Immediate Upper 8-Bit, L = Immediate Lower 8-Bit, 2 & 1 = Prefix (ALT1/ALT2/ALT3), R = ROM[R14] Read, G = GSU Running, V = Overflow, S = Sign, C = Carry, Z = Zero) +constant GSU_SFR_ZERO($0002) // GSU Status/Flag Bit 1: Zero Flag +constant GSU_SFR_CARRY($0004) // GSU Status/Flag Bit 2: Carry Flag +constant GSU_SFR_SIGN($0008) // GSU Status/Flag Bit 3: Sign Flag +constant GSU_SFR_OVERFLOW($0010) // GSU Status/Flag Bit 4: Overflow Flag +constant GSU_SFR_GSU($0020) // GSU Status/Flag Bit 5: GSU Running (Cleared On STOP) (Set 0 To Force GSU Stop) +constant GSU_SFR_ROM($0040) // GSU Status/Flag Bit 6: ROM[R14] Read (0 = Off, 1 = Read ROM Via R14 Address) +constant GSU_SFR_PF1($0100) // GSU Status/Flag Bit 8: Prefix Flag 1 For ALT1/ALT2/ALT3 +constant GSU_SFR_PF2($0200) // GSU Status/Flag Bit 9: Prefix Flag 2 For ALT1/ALT2/ALT3 +constant GSU_SFR_LO($0400) // GSU Status/Flag Bit 10: Immediate Lower 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_HI($0800) // GSU Status/Flag Bit 11: Immediate Upper 8-Bit Flag (Set/Reset Internally When Processing Opcodes With Immediate Operands) +constant GSU_SFR_PFB($1000) // GSU Status/Flag Bit 12: Prefix Flag B For MOVE/MOVES (WITH Prefix) +constant GSU_SFR_INT($8000) // GSU Status/Flag Bit 15: Interrupt Flag (Reset On READ, Set On STOP) (Also Set IF IRQ Masked In GSU_CFGR ($3037)) + +// GSU Backup (S)RAM Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_BRAMR($3033) // GSU Backup (S)RAM Register (0 = Disable BRAM, 1 = Enable BRAM) +// GSU Backup (S)RAM Register Flags: (%-------B: B = Disable/Enable BRAM) +constant GSU_BRAMR_DISABLE($00) // GSU Backup (S)RAM Bit 0: Disable BRAM +constant GSU_BRAMR_ENABLE($01) // GSU Backup (S)RAM Bit 0: Enable BRAM + +// GSU Program Bank Register - Access From SNES CPU (Read/Write, 1 Byte) +constant GSU_PBR($3034) // GSU Program Bank Register (%BBBBBBBB: B = Bank) (Works Like SNES CPU Program Bank Register) +// GSU Game PAK ROM Bank Register - Access From SNES CPU (Read) +constant GSU_ROMBR($3036) // GSU Game PAK ROM Bank Register For ROM Buffering (%BBBBBBBB: B = Bank) (Specifies Bank For Instructions Using ROM Buffer) + +// GSU Config Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CFGR($3037) // GSU Config Register +// GSU Config Register Flags: (%I-M-----: I = IRQ Mask, M = Multiplier Speed Select) +constant GSU_CFGR_FASTMUL($20) // GSU Config Bit 7: Multiplier Speed Select (0 = Standard Speed, 1 = High Speed) +constant GSU_CFGR_IRQ_MASK($80) // GSU Config Bit 5: IRQ Mask (0 = Off, 1 = On) (Mask GSU Triggered IRQ) + +// GSU Screen Base Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCBR($3038) // GSU Screen Base Register (%AAAAAAAA: A = Start Address (1KB Units) For Plot Area) + +// GSU Clock Select Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CLSR($3039) // GSU Clock Select Register (0 = 10.7MHz, 1 = 21.4MHz) +// GSU Clock Select Register Flags (%-------S: S = Clock Speed) +constant GSU_CLSR_10MHz($00) // GSU Clock Select Bit 0: Clock Speed 10.7MHz +constant GSU_CLSR_21MHz($01) // GSU Clock Select Bit 0: Clock Speed 21.4MHz + +// GSU Screen Mode Register - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_SCMR($303A) // GSU Screen Mode Register +// GSU Screen Mode Register Flags (%--HOAHCC: O = RON, A = RAN, H = Screen Height, C = Color Depth Mode) +constant GSU_SCMR_2BPP($00) // GSU Screen Mode Bit 0..1: Color Depth Mode 0 (2BPP) +constant GSU_SCMR_4BPP($01) // GSU Screen Mode Bit 0..1: Color Depth Mode 1 (4BPP) +constant GSU_SCMR_8BPP($03) // GSU Screen Mode Bit 0..1: Color Depth Mode 3 (8BPP) +constant GSU_SCMR_H128($00) // GSU Screen Mode Bit 2 & 5: Screen Height 0 (128 Pixels) +constant GSU_SCMR_H160($04) // GSU Screen Mode Bit 2 & 5: Screen Height 1 (160 Pixels) +constant GSU_SCMR_H192($20) // GSU Screen Mode Bit 2 & 5: Screen Height 2 (192 Pixels) +constant GSU_SCMR_OBJ($24) // GSU Screen Mode Bit 2 & 5: Screen Height 4 (Object Mode) +constant GSU_RAN($08) // GSU Screen Mode Bit 3: RAN (0 = RAM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK RAM, 1 = Give Game PAK RAM Access Back To GSU & Resume Processing) +constant GSU_RON($10) // GSU Screen Mode Bit 4: RON (0 = ROM Enable To Put GSU In WAIT Mode, Allows SCPU Access To Game PAK ROM, 1 = Give Game PAK ROM Access Back To GSU & Resume Processing) + +// GSU Version Code Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_VCR($303B) // GSU Version Code Register (%VVVVVVVV: V = Version Code) (1 = MARIO, 2 = GSU-0, 3 = GSU-1, 4 = GSU-2) +constant GSU_VCR_MARIO($01) // GSU Version Code Bit 0..7: Version Code 1 (MARIO Chip) +constant GSU_VCR_GSU0($02) // GSU Version Code Bit 0..7: Version Code 2 (GSU-0 Chip) +constant GSU_VCR_GSU1($03) // GSU Version Code Bit 0..7: Version Code 3 (GSU-1 Chip) +constant GSU_VCR_GSU2($04) // GSU Version Code Bit 0..7: Version Code 4 (GSU-2 Chip) + +// GSU Game PAK RAM Bank Register - Access From SNES CPU (Read Only, 1 Byte) +constant GSU_RAMBR($303C) // GSU Game PAK RAM Bank Register (0 = $70, 1 = $71) +// GSU Game PAK RAM Bank Register Flags (%-------A: A = Bank Select) +constant GSU_RAMBR_70($00) // GSU Game PAK RAM Bank Bit 0: Bank Select ($70) +constant GSU_RAMBR_71($01) // GSU Game PAK RAM Bank Bit 0: Bank Select ($71) + +// GSU Cache Base Register - Access From SNES CPU (Read Only, 2 Byte) +constant GSU_CBR($303E) // GSU Cache Base Register (%CCCCCCCCCCCC----: C = Cache Address Base) (Starting Address When Data Is Loaded From ROM Or Game PAK RAM To Cache RAM) + +// GSU Cache Start Exposed To SCPU - Access From SNES CPU (Write Only, 1 Byte) +constant GSU_CACHE($3100) // GSU Cache Start Exposed To SCPU (%CCCCCCCC: C = Cache Start Exposed To SCPU) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..72a6f568 --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SNES PROGRAM TITLE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $8000 // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_SA-1.INC b/roms/snes/peter-lemon-snes/LIB/SNES_SA-1.INC new file mode 100644 index 00000000..2eb7a2b2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_SA-1.INC @@ -0,0 +1,91 @@ +//=========== +// SNES SA-1 +//=========== + +// SA-1 Write Registers +constant SA1_CCNT($2200) // SA-1 CPU Control (4.1.1) +constant SA1_SIE($2201) // SNES CPU Interrupt Enable (4.1.2) +constant SA1_SIC($2202) // SNES CPU Interrupt Clear (4.1.3) +constant SA1_CRVL($2203) // SA-1 CPU Reset Vector Lo (4.1.4) (Bits 0..7) +constant SA1_CRVH($2204) // SA-1 CPU Reset Vector Hi (4.1.4) (Bits 8..15) +constant SA1_CNVL($2205) // SA-1 CPU NMI Vector Lo (4.1.5) (Bits 0..7) +constant SA1_CNVH($2206) // SA-1 CPU NMI Vector Hi (4.1.5) (Bits 8..15) +constant SA1_CIVL($2207) // SA-1 CPU IRQ Vector Lo (4.1.6) (Bits 0..7) +constant SA1_CIVH($2208) // SA-1 CPU IRQ Vector Hi (4.1.6) (Bits 8..15) +constant SA1_SCNT($2209) // SNES CPU Control (4.1.7) +constant SA1_CIE($220A) // SA-1 CPU Interrupt Enable (4.1.8) +constant SA1_CIC($220B) // SA-1 CPU Interrupt Clear (4.1.9) +constant SA1_SNVL($220C) // SNES CPU NMI Vector Lo (4.1.10) (Bits 0..7) +constant SA1_SNVH($220D) // SNES CPU NMI Vector Hi (4.1.10) (Bits 8..15) +constant SA1_SIVL($220E) // SNES CPU IRQ Vector Lo (4.1.11) (Bits 0..7) +constant SA1_SIVH($220F) // SNES CPU IRQ Vector Hi (4.1.11) (Bits 8..15) +constant SA1_TMC($2210) // H/V Timer Control (4.1.12) +constant SA1_CTR($2211) // SA-1 CPU Timer Restart (4.1.13) +constant SA1_HCNTL($2212) // Set H-Count Lo (4.1.14) (Bits 0..7) +constant SA1_HCNTH($2213) // Set H-Count Hi (4.1.14) (Bits 8..15) (Only Bit 8 Used) +constant SA1_VCNTL($2214) // Set V-Count Lo (4.1.15) (Bits 0..7) +constant SA1_VCNTH($2215) // Set V-Count Hi (4.1.15) (Bits 8..15) (Only Bit 8 Used) +constant SA1_CXB($2220) // Set Super MMC Bank C (4.1.16) +constant SA1_DXB($2221) // Set Super MMC Bank D (4.1.17) +constant SA1_EXB($2222) // Set Super MMC Bank E (4.1.18) +constant SA1_FXB($2223) // Set Super MMC Bank F (4.1.19) +constant SA1_BMAPS($2224) // SNES CPU BW-RAM Address Mapping (4.1.20) +constant SA1_BMAP($2225) // SA-1 CPU BW-RAM Address Mapping (4.1.21) +constant SA1_SBWE($2226) // SNES CPU BW-RAM Write Enable (4.1.22) +constant SA1_CBWE($2227) // SA-1 CPU BW-RAM Write Enable (4.1.23) +constant SA1_BWPA($2228) // BW-RAM Write Protected Area (4.1.24) +constant SA1_SIWP($2229) // SA-1 I-RAM Write Protection (4.1.25) (S-CPU Controlled) +constant SA1_CIWP($222A) // SA-1 I-RAM Write Protection (4.1.26) (SA-1 Controlled) +constant SA1_DCNT($2230) // DMA Control (4.1.27) +constant SA1_CDMA($2231) // Character Conversion OMA Parameters (4.1.28) +constant SA1_SDAL($2232) // DMA Source Device Start Address Lo (4.1.29) (Bits 0..7) +constant SA1_SDAH($2233) // DMA Source Device Start Address Hi (4.1.29) (Bits 8..15) +constant SA1_SDAB($2234) // DMA Source Device Start Address B (4.1.29) (Bits 16..23) +constant SA1_DDAL($2235) // DMA Destination Start Address Lo (4.1.30) (Bits 0..7) +constant SA1_DDAH($2236) // DMA Destination Start Address Hi (4.1.30) (Bits 8..15) +constant SA1_DDAB($2237) // DMA Destination Start Address B (4.1.30) (Bits 16..23) +constant SA1_DTCL($2238) // DMA Terminal Counter Lo (4.1.31) (Bits 0..7) +constant SA1_DTCH($2239) // DMA Terminal Counter Hi (4.1.31) (Bits 8..15) +constant SA1_BBF($223F) // BW-RAM Bit Map Format (4.1.32) +constant SA1_BRF0($2240) // Bit Map Register File 0 (4.1.33) +constant SA1_BRF1($2241) // Bit Map Register File 1 (4.1.33) +constant SA1_BRF2($2242) // Bit Map Register File 2 (4.1.33) +constant SA1_BRF3($2243) // Bit Map Register File 3 (4.1.33) +constant SA1_BRF4($2244) // Bit Map Register File 4 (4.1.33) +constant SA1_BRF5($2245) // Bit Map Register File 5 (4.1.33) +constant SA1_BRF6($2246) // Bit Map Register File 6 (4.1.33) +constant SA1_BRF7($2247) // Bit Map Register File 7 (4.1.33) +constant SA1_BRF8($2248) // Bit Map Register File 8 (4.1.33) +constant SA1_BRF9($2249) // Bit Map Register File 9 (4.1.33) +constant SA1_BRFA($224A) // Bit Map Register File A (4.1.33) +constant SA1_BRFB($224B) // Bit Map Register File B (4.1.33) +constant SA1_BRFC($224C) // Bit Map Register File C (4.1.33) +constant SA1_BRFD($224D) // Bit Map Register File D (4.1.33) +constant SA1_BRFE($224E) // Bit Map Register File E (4.1.33) +constant SA1_BRFF($224F) // Bit Map Register File F (4.1.33) +constant SA1_MCNT($2250) // Arithmetic Control (4.1.34) +constant SA1_MAL($2251) // Arithmetic Parameters: Multiplicand/Dividend Lo (4.1.35) (Bits 0..7) +constant SA1_MAH($2252) // Arithmetic Parameters: Multiplicand/Dividend Hi (4.1.35) (Bits 8..15) +constant SA1_MBL($2253) // Arithmetic Parameters: Multiplier/Divisor Lo (4.1.36) (Bits 0..7) +constant SA1_MBH($2254) // Arithmetic Parameters: Multiplier/Divisor Hi (4.1.36) (Bits 8..15) +constant SA1_VBD($2258) // Variable Length Bit Processing (4.1.37) +constant SA1_VDAL($2259) // Variable Length Bit Game Pak ROM Start Address Lo (4.1.38) (Bits 0..7) +constant SA1_VDAH($225A) // Variable Length Bit Game Pak ROM Start Address Hi (4.1.38) (Bits 8..15) +constant SA1_VDAB($225B) // Variable Length Bit Game Pak ROM Start Address B (4.1.38) (Bits 16..23) + +// SA-1 Read Registers +constant SA1_SFR($2300) // SNES CPU Flag Read (4.1.39) +constant SA1_CFR($2301) // SA-1 CPU Flag Read (4.1.40) +constant SA1_HCRL($2302) // H-Count Read Lo (4.1.41) +constant SA1_HCRH($2303) // H-Count Read Hi (4.1.41) +constant SA1_VCRL($2304) // V-Count Read Lo (4.1.42) +constant SA1_VCRH($2305) // V-Count Read Hi (4.1.42) +constant SA1_MR1($2306) // Arithmetic Result (Product/Quotient/Accumulative Sum) 1 (4.1.43) (Bits 0..7) +constant SA1_MR2($2307) // Arithmetic Result (Product/Quotient/Accumulative Sum) 2 (4.1.43) (Bits 8..15) +constant SA1_MR3($2308) // Arithmetic Result (Product/Quotient/Accumulative Sum) 3 (4.1.43) (Bits 16..23) +constant SA1_MR4($2309) // Arithmetic Result (Product/Quotient/Accumulative Sum) 4 (4.1.43) (Bits 24..31) +constant SA1_MR5($230A) // Arithmetic Result (Product/Quotient/Accumulative Sum) 5 (4.1.43) (Bits 32..39) +constant SA1_OF($230B) // Arithmetic Overflow Flag (4.1.44) +constant SA1_VDPL($230C) // Variable Length Data Read Port Lo (4.1.45) (Bits 0..7) +constant SA1_VDPH($230D) // Variable Length Data Read Port Hi (4.1.45) (Bits 8..15) +constant SA1_VC($230E) // Version Code Register (4.1.46) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO-0.pcm b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO-0.pcm new file mode 100644 index 00000000..6b6215e9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.asm b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.asm new file mode 100644 index 00000000..422da69f --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.asm @@ -0,0 +1,38 @@ +// SNES MSU1 Audio Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "AUDIO.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "AUDIO.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.msu b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.msu new file mode 100644 index 00000000..e69de29b diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.sfc b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.sfc new file mode 100644 index 00000000..7c69d234 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.spc b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO_spc.asm b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO_spc.asm new file mode 100644 index 00000000..eda8cc19 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/AUDIO_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Audio Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "AUDIO.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..016e7e1a --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "AUDIO DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/make.bat b/roms/snes/peter-lemon-snes/MSU/AUDIO/make.bat new file mode 100644 index 00000000..04ebd700 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/make.bat @@ -0,0 +1,2 @@ +bass AUDIO_spc.asm +bass AUDIO.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/AUDIO/manifest.bml b/roms/snes/peter-lemon-snes/MSU/AUDIO/manifest.bml new file mode 100644 index 00000000..c90e5d09 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/AUDIO/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=AUDIO.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=AUDIO.msu size=0 + track number=0 name=AUDIO-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: AUDIO diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d01887d1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MSU1 TOUHOU BAD APPLE" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace-0.pcm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace-0.pcm new file mode 100644 index 00000000..f38742f9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.asm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.asm new file mode 100644 index 00000000..545a2cb4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.asm @@ -0,0 +1,193 @@ +// SNES MSU1 Touhou - Bad Apple! 15 Frames Per Second 16 Color Interlace Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "Touhou-BadApple!15FPS16ColInterlace.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG1 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + // Setup Tile DMA On Channel 0 + ldx.w #$0000 // VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + ldx.w #3289>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + + ldy.w #32 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) +VIDLoop: + ldx.w #8192 // VRAM Size In Bytes To DMA Transfer + + //////////////////////////////////////////////////////// + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG1 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $7200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG1 16 Colour Background + lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $8000 (VRAM Address / $1000) + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 12, %10000000 // Repeat 12 Scanlines, Turn Off Screen, Zero Brightness + db 20, %00001111 // Repeat 20 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +// SPC Code +// BANK 0 +insert SPCROM, "Touhou-BadApple!15FPS16ColInterlace.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.msu.7z b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.msu.7z new file mode 100644 index 00000000..39b5723e Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.msu.7z differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.png b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.png new file mode 100644 index 00000000..18eb6906 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.sfc b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.sfc new file mode 100644 index 00000000..64cef6f0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.spc b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace_spc.asm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace_spc.asm new file mode 100644 index 00000000..62ac006e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Touhou - Bad Apple! 15 Frames Per Second 16 Color Interlace Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "Touhou-BadApple!15FPS16ColInterlace.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/make.bat b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/make.bat new file mode 100644 index 00000000..d28b6f3d --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/make.bat @@ -0,0 +1,2 @@ +bass Touhou-BadApple!15FPS16ColInterlace_spc.asm +bass Touhou-BadApple!15FPS16ColInterlace.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/manifest.bml b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/manifest.bml new file mode 100644 index 00000000..80cd33b0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=Touhou-BadApple!15FPS16ColInterlace.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=Touhou-BadApple!15FPS16ColInterlace.msu size=0 + track number=0 name=Touhou-BadApple!15FPS16ColInterlace-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Touhou - Bad Apple! 15 Frames Per Second 16 Color Interlace diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..d01887d1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MSU1 TOUHOU BAD APPLE" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace-0.pcm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace-0.pcm new file mode 100644 index 00000000..f38742f9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.asm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.asm new file mode 100644 index 00000000..ff3039d3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.asm @@ -0,0 +1,215 @@ +// SNES MSU1 Touhou - Bad Apple! 30 Frames Per Second 4 Color Interlace Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "Touhou-BadApple!30FPS4ColInterlace.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG2 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG2 62 Pixels Up + sta.w REG_BG2VOFS // Store A To BG2 Vertical Scroll Position Lo Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Hi Byte + + lda.b #$02 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + sta.w REG_TS // $212D: BG2 To Sub Screen Designation (Needed To Show Interlace GFX) + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + // Setup Tile DMA On Channel 0 + ldx.w #$0000 // VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + ldx.w #6572>>2 // Load Frame Count / 4 + stx.b FrameCount // Store Frame Count + + ldy.w #8 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) +VIDLoop: + ldx.w #8192 // VRAM Size In Bytes To DMA Transfer + + //////////////////////////////////////////////////////// + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG2 4 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00011010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 64x32, BG2 Map Address = $3200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG2 4 Colour Background + lda.b #%00100000 // BBBBAAAA: A = BG2 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $4000 (VRAM Address / $1000) + lda.b #%00111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 64x32, BG2 Map Address = $7200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + // Load Frame 3 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 3 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 3 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 3 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 3 BG2 4 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG2 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + lda.b #%01011010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 64x32, BG2 Map Address = $B200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + // Load Frame 4 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 4 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 4 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 4 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 4 BG2 4 Colour Background + lda.b #%01100000 // BBBBAAAA: A = BG2 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $C000 (VRAM Address / $1000) + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 64x32, BG2 Map Address = $F200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 12, %10000000 // Repeat 12 Scanlines, Turn Off Screen, Zero Brightness + db 20, %00001111 // Repeat 20 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +// SPC Code +// BANK 0 +insert SPCROM, "Touhou-BadApple!30FPS4ColInterlace.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.msu.7z b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.msu.7z new file mode 100644 index 00000000..8e299681 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.msu.7z differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.png b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.png new file mode 100644 index 00000000..0a3636ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.sfc b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.sfc new file mode 100644 index 00000000..9e186345 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.spc b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace_spc.asm b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace_spc.asm new file mode 100644 index 00000000..2df3c5d5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Touhou - Bad Apple! 30 Frames Per Second 4 Color Interlace Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "Touhou-BadApple!30FPS4ColInterlace.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/make.bat b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/make.bat new file mode 100644 index 00000000..38b3a2c0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/make.bat @@ -0,0 +1,2 @@ +bass Touhou-BadApple!30FPS4ColInterlace_spc.asm +bass Touhou-BadApple!30FPS4ColInterlace.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/manifest.bml b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/manifest.bml new file mode 100644 index 00000000..a9576cd3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=Touhou-BadApple!30FPS4ColInterlace.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=Touhou-BadApple!30FPS4ColInterlace.msu size=0 + track number=0 name=Touhou-BadApple!30FPS4ColInterlace-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Touhou - Bad Apple! 30 Frames Per Second 4 Color Interlace diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..2fad24b3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "VIDEO15FPS 15COL16PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/TileMap16PAL256x224.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/TileMap16PAL256x224.asm new file mode 100644 index 00000000..fb118e97 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/TileMap16PAL256x224.asm @@ -0,0 +1,29 @@ +dw $0040, $0041, $0042, $0043, $0044, $0045, $0046, $0047, $0448, $0449, $044A, $044B, $044C, $044D, $044E, $044F, $08C0, $08C1, $08C2, $08C3, $08C4, $08C5, $08C6, $08C7, $0CC8, $0CC9, $0CCA, $0CCB, $0CCC, $0CCD, $0CCE, $0CCF +dw $0050, $0051, $0052, $0053, $0054, $0055, $0056, $0057, $0458, $0459, $045A, $045B, $045C, $045D, $045E, $045F, $08D0, $08D1, $08D2, $08D3, $08D4, $08D5, $08D6, $08D7, $0CD8, $0CD9, $0CDA, $0CDB, $0CDC, $0CDD, $0CDE, $0CDF +dw $0060, $0061, $0062, $0063, $0064, $0065, $0066, $0067, $0468, $0469, $046A, $046B, $046C, $046D, $046E, $046F, $08E0, $08E1, $08E2, $08E3, $08E4, $08E5, $08E6, $08E7, $0CE8, $0CE9, $0CEA, $0CEB, $0CEC, $0CED, $0CEE, $0CEF +dw $0070, $0071, $0072, $0073, $0074, $0075, $0076, $0077, $0478, $0479, $047A, $047B, $047C, $047D, $047E, $047F, $08F0, $08F1, $08F2, $08F3, $08F4, $08F5, $08F6, $08F7, $0CF8, $0CF9, $0CFA, $0CFB, $0CFC, $0CFD, $0CFE, $0CFF +dw $0080, $0081, $0082, $0083, $0084, $0085, $0086, $0087, $0488, $0489, $048A, $048B, $048C, $048D, $048E, $048F, $0900, $0901, $0902, $0903, $0904, $0905, $0906, $0907, $0D08, $0D09, $0D0A, $0D0B, $0D0C, $0D0D, $0D0E, $0D0F +dw $0090, $0091, $0092, $0093, $0094, $0095, $0096, $0097, $0498, $0499, $049A, $049B, $049C, $049D, $049E, $049F, $0910, $0911, $0912, $0913, $0914, $0915, $0916, $0917, $0D18, $0D19, $0D1A, $0D1B, $0D1C, $0D1D, $0D1E, $0D1F +dw $00A0, $00A1, $00A2, $00A3, $00A4, $00A5, $00A6, $00A7, $04A8, $04A9, $04AA, $04AB, $04AC, $04AD, $04AE, $04AF, $0920, $0921, $0922, $0923, $0924, $0925, $0926, $0927, $0D28, $0D29, $0D2A, $0D2B, $0D2C, $0D2D, $0D2E, $0D2F +dw $00B0, $00B1, $00B2, $00B3, $00B4, $00B5, $00B6, $00B7, $04B8, $04B9, $04BA, $04BB, $04BC, $04BD, $04BE, $04BF, $0930, $0931, $0932, $0933, $0934, $0935, $0936, $0937, $0D38, $0D39, $0D3A, $0D3B, $0D3C, $0D3D, $0D3E, $0D3F +dw $1140, $1141, $1142, $1143, $1144, $1145, $1146, $1147, $1548, $1549, $154A, $154B, $154C, $154D, $154E, $154F, $19A0, $19A1, $19A2, $19A3, $19A4, $19A5, $19A6, $19A7, $1DA8, $1DA9, $1DAA, $1DAB, $1DAC, $1DAD, $1DAE, $1DAF +dw $1150, $1151, $1152, $1153, $1154, $1155, $1156, $1157, $1558, $1559, $155A, $155B, $155C, $155D, $155E, $155F, $19B0, $19B1, $19B2, $19B3, $19B4, $19B5, $19B6, $19B7, $1DB8, $1DB9, $1DBA, $1DBB, $1DBC, $1DBD, $1DBE, $1DBF +dw $1160, $1161, $1162, $1163, $1164, $1165, $1166, $1167, $1568, $1569, $156A, $156B, $156C, $156D, $156E, $156F, $19C0, $19C1, $19C2, $19C3, $19C4, $19C5, $19C6, $19C7, $1DC8, $1DC9, $1DCA, $1DCB, $1DCC, $1DCD, $1DCE, $1DCF +dw $1170, $1171, $1172, $1173, $1174, $1175, $1176, $1177, $1578, $1579, $157A, $157B, $157C, $157D, $157E, $157F, $19D0, $19D1, $19D2, $19D3, $19D4, $19D5, $19D6, $19D7, $1DD8, $1DD9, $1DDA, $1DDB, $1DDC, $1DDD, $1DDE, $1DDF +dw $1180, $1181, $1182, $1183, $1184, $1185, $1186, $1187, $1588, $1589, $158A, $158B, $158C, $158D, $158E, $158F, $19E0, $19E1, $19E2, $19E3, $19E4, $19E5, $19E6, $19E7, $1DE8, $1DE9, $1DEA, $1DEB, $1DEC, $1DED, $1DEE, $1DEF +dw $1190, $1191, $1192, $1193, $1194, $1195, $1196, $1197, $1598, $1599, $159A, $159B, $159C, $159D, $159E, $159F, $19F0, $19F1, $19F2, $19F3, $19F4, $19F5, $19F6, $19F7, $1DF8, $1DF9, $1DFA, $1DFB, $1DFC, $1DFD, $1DFE, $1DFF + +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 +dw $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0, $03C0 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal-0.pcm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal-0.pcm new file mode 100644 index 00000000..aed0a4db Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.asm new file mode 100644 index 00000000..ec6fb6a2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.asm @@ -0,0 +1,326 @@ +// SNES MSU1 Video 15 Frames Per Second 15 Color 16 Palette Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "VIDEO15FPS15Col16Pal.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup Frame 1 & 2 Background Tile Map + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #%00010010 // Enable BG2 & Sprites + sta.w REG_TM // $212C: BG2 & Sprites To Main Screen Designation + + LoadVRAM(BGMap, $7900, 1792, 0) // Load Frame 1 & 2 Background Tile Map To VRAM + + // Clear OAM + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Copy OAM Info + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + - + lda.w OAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$00A0 + bne - + + // Copy OAM Extra Info + ldy.w #$0100 // Y = $0100 + sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + - + lda.w OAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$00AA + bne - + + + // Setup Tile DMA On Channel 0 + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + ldx.w #1528>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + + stz.w REG_CGADD // $2121: CGRAM + + WaitNMI() // Wait For Vertical Blank + +VIDLoop: + //////////////////////////////////////////////////////// + ldx.w #7296 // VRAM Size In Bytes To DMA Transfer + ldy.w #$0800 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM, Followed By Palette To CGRAM + ldx.w #6784 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #512 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + + // Setup Frame 1 OBJ 16 Color Sprites + lda.b #%01100001 // Object Size = 16x16/32x32, Name = 0, Base = $4000 + sta.w REG_OBSEL // $2101: Object Size & Object Base + + //////////////////////////////////////////////////////// + ldx.w #7296 // VRAM Size In Bytes To DMA Transfer + ldy.w #$8800 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM, Followed By Palette To CGRAM + ldx.w #6784 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #512 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG2 16 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + + // Setup Frame 2 OBJ 16 Color Sprites + lda.b #%01100011 // Object Size = 16x16/32x32, Name = 0, Base = $C000 + sta.w REG_OBSEL // $2101: Object Size & Object Base + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 7, %10000000 // Repeat 7 Scanlines, Turn Off Screen, Zero Brightness + db 25, %00001111 // Repeat 25 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +OAM: + // OAM Info (16x16 Sprites) + db 0, 112, 0, %00000000 + db 16, 112, 2, %00000000 + db 32, 112, 4, %00000000 + db 48, 112, 6, %00000000 + + db 64, 112, 8, %00000010 + db 80, 112, 10, %00000010 + db 96, 112, 12, %00000010 + db 112, 112, 14, %00000010 + + db 128, 112, 96, %00000100 + db 144, 112, 98, %00000100 + db 160, 112, 100, %00000100 + db 176, 112, 102, %00000100 + + db 192, 112, 104, %00000110 + db 208, 112, 106, %00000110 + db 224, 112, 108, %00000110 + db 240, 112, 110, %00000110 + + // OAM Info (32x32 Sprites) + db 0, 128, 32, %00000000 + db 32, 128, 36, %00000000 + + db 64, 128, 40, %00000010 + db 96, 128, 44, %00000010 + + db 128, 128, 128, %00000100 + db 160, 128, 132, %00000100 + + db 192, 128, 136, %00000110 + db 224, 128, 140, %00000110 + + + db 0, 160, 192, %00001000 + db 32, 160, 196, %00001000 + + db 64, 160, 200, %00001010 + db 96, 160, 204, %00001010 + + db 128, 160, 64, %00001101 + db 160, 160, 68, %00001101 + + db 192, 160, 72, %00001111 + db 224, 160, 76, %00001111 + + + db 0, 192, 0, %00001001 + db 32, 192, 4, %00001001 + + db 64, 192, 8, %00001011 + db 96, 192, 12, %00001011 + + db 128, 192, 128, %00001101 + db 160, 192, 132, %00001101 + + db 192, 192, 136, %00001111 + db 224, 192, 140, %00001111 + + // OAM Extra Info (16x16 Sprites) + db %00000000 + db %00000000 + db %00000000 + db %00000000 + + // OAM Extra Info (32x32 Sprites) + db %10101010 + db %10101010 + db %10101010 + db %10101010 + db %10101010 + db %10101010 + +BGMap: + include "TileMap16PAL256x224.asm" // Include BG Map Data (1792 Bytes) + +// SPC Code +// BANK 0 +insert SPCROM, "VIDEO15FPS15Col16Pal.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.msu b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.msu new file mode 100644 index 00000000..a2d33fc1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.msu differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.png b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.png new file mode 100644 index 00000000..271b7439 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.sfc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.sfc new file mode 100644 index 00000000..951be24b Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.spc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal_spc.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal_spc.asm new file mode 100644 index 00000000..c817c839 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Video 15 Frames Per Second 15 Color 16 Palette Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "VIDEO15FPS15Col16Pal.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/make.bat b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/make.bat new file mode 100644 index 00000000..b3bd08c8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/make.bat @@ -0,0 +1,2 @@ +bass VIDEO15FPS15Col16Pal_spc.asm +bass VIDEO15FPS15Col16Pal.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/manifest.bml b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/manifest.bml new file mode 100644 index 00000000..50bd86e8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=VIDEO15FPS15Col16Pal.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=VIDEO15FPS15Col16Pal.msu size=0 + track number=0 name=VIDEO15FPS15Col16Pal-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Video 15 Frames Per Second 15 Color 16 Palette diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..6ea37402 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "VIDEO 15FPS 15COL8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/TileMap8PAL256x224.asm new file mode 100644 index 00000000..d127b2b2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $0000, $0001, $0002, $0003, $0004, $0005, $0006, $0007, $0008, $0009, $000a, $000b, $000c, $000d, $000e, $000f, $0010, $0011, $0012, $0013, $0014, $0015, $0016, $0017, $0018, $0019, $001a, $001b, $001c, $001d, $001e, $001f +dw $0020, $0021, $0022, $0023, $0024, $0025, $0026, $0027, $0028, $0029, $002a, $002b, $002c, $002d, $002e, $002f, $0030, $0031, $0032, $0033, $0034, $0035, $0036, $0037, $0038, $0039, $003a, $003b, $003c, $003d, $003e, $003f +dw $0040, $0041, $0042, $0043, $0044, $0045, $0046, $0047, $0048, $0049, $004a, $004b, $004c, $004d, $004e, $004f, $0050, $0051, $0052, $0053, $0054, $0055, $0056, $0057, $0058, $0059, $005a, $005b, $005c, $005d, $005e, $005f +dw $0060, $0061, $0062, $0063, $0064, $0065, $0066, $0067, $0068, $0069, $006a, $006b, $006c, $006d, $006e, $006f, $0070, $0071, $0072, $0073, $0074, $0075, $0076, $0077, $0078, $0079, $007a, $007b, $007c, $007d, $007e, $007f +dw $0480, $0481, $0482, $0483, $0484, $0485, $0486, $0487, $0488, $0489, $048a, $048b, $048c, $048d, $048e, $048f, $0490, $0491, $0492, $0493, $0494, $0495, $0496, $0497, $0498, $0499, $049a, $049b, $049c, $049d, $049e, $049f +dw $04a0, $04a1, $04a2, $04a3, $04a4, $04a5, $04a6, $04a7, $04a8, $04a9, $04aa, $04ab, $04ac, $04ad, $04ae, $04af, $04b0, $04b1, $04b2, $04b3, $04b4, $04b5, $04b6, $04b7, $04b8, $04b9, $04ba, $04bb, $04bc, $04bd, $04be, $04bf +dw $04c0, $04c1, $04c2, $04c3, $04c4, $04c5, $04c6, $04c7, $04c8, $04c9, $04ca, $04cb, $04cc, $04cd, $04ce, $04cf, $04d0, $04d1, $04d2, $04d3, $04d4, $04d5, $04d6, $04d7, $04d8, $04d9, $04da, $04db, $04dc, $04dd, $04de, $04df +dw $04e0, $04e1, $04e2, $04e3, $04e4, $04e5, $04e6, $04e7, $04e8, $04e9, $04ea, $04eb, $04ec, $04ed, $04ee, $04ef, $04f0, $04f1, $04f2, $04f3, $04f4, $04f5, $04f6, $04f7, $04f8, $04f9, $04fa, $04fb, $04fc, $04fd, $04fe, $04ff +dw $0900, $0901, $0902, $0903, $0904, $0905, $0906, $0907, $0908, $0909, $090a, $090b, $090c, $090d, $090e, $090f, $0910, $0911, $0912, $0913, $0914, $0915, $0916, $0917, $0918, $0919, $091a, $091b, $091c, $091d, $091e, $091f +dw $0920, $0921, $0922, $0923, $0924, $0925, $0926, $0927, $0928, $0929, $092a, $092b, $092c, $092d, $092e, $092f, $0930, $0931, $0932, $0933, $0934, $0935, $0936, $0937, $0938, $0939, $093a, $093b, $093c, $093d, $093e, $093f +dw $0940, $0941, $0942, $0943, $0944, $0945, $0946, $0947, $0948, $0949, $094a, $094b, $094c, $094d, $094e, $094f, $0950, $0951, $0952, $0953, $0954, $0955, $0956, $0957, $0958, $0959, $095a, $095b, $095c, $095d, $095e, $095f +dw $0D60, $0D61, $0D62, $0D63, $0D64, $0D65, $0D66, $0D67, $0D68, $0D69, $0D6a, $0D6b, $0D6c, $0D6d, $0D6e, $0D6f, $0D70, $0D71, $0D72, $0D73, $0D74, $0D75, $0D76, $0D77, $0D78, $0D79, $0D7a, $0D7b, $0D7c, $0D7d, $0D7e, $0D7f +dw $0D80, $0D81, $0D82, $0D83, $0D84, $0D85, $0D86, $0D87, $0D88, $0D89, $0D8a, $0D8b, $0D8c, $0D8d, $0D8e, $0D8f, $0D90, $0D91, $0D92, $0D93, $0D94, $0D95, $0D96, $0D97, $0D98, $0D99, $0D9a, $0D9b, $0D9c, $0D9d, $0D9e, $0D9f +dw $0Da0, $0Da1, $0Da2, $0Da3, $0Da4, $0Da5, $0Da6, $0Da7, $0Da8, $0Da9, $0Daa, $0Dab, $0Dac, $0Dad, $0Dae, $0Daf, $0Db0, $0Db1, $0Db2, $0Db3, $0Db4, $0Db5, $0Db6, $0Db7, $0Db8, $0Db9, $0Dba, $0Dbb, $0Dbc, $0Dbd, $0Dbe, $0Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal-0.pcm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal-0.pcm new file mode 100644 index 00000000..aed0a4db Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.asm new file mode 100644 index 00000000..16c4172a --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.asm @@ -0,0 +1,203 @@ +// SNES MSU1 Video 15 Frames Per Second 15 Color 8 Palette Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "VIDEO15FPS15Col8Pal.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup Frame 1 & 2 Background Tile Map + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + LoadVRAM(BGMap, $7900, 1792, 0) // Load Frame 1 Background Tile Map To VRAM + + // Setup Tile DMA On Channel 0 + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + ldx.w #1528>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + + WaitNMI() // Wait For Vertical Blank + +VIDLoop: + //////////////////////////////////////////////////////// + ldx.w #7232 // VRAM Size In Bytes To DMA Transfer + ldy.w #$0000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + ldx.w #6976 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #256 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + + //////////////////////////////////////////////////////// + ldx.w #7232 // VRAM Size In Bytes To DMA Transfer + ldy.w #$8000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + ldx.w #6976 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #256 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG2 16 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 7, %10000000 // Repeat 7 Scanlines, Turn Off Screen, Zero Brightness + db 25, %00001111 // Repeat 25 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) + +// SPC Code +// BANK 0 +insert SPCROM, "VIDEO15FPS15Col8Pal.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.msu b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.msu new file mode 100644 index 00000000..59795c78 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.msu differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.png b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.png new file mode 100644 index 00000000..0f3ddd5d Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.sfc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.sfc new file mode 100644 index 00000000..99326822 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.spc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal_spc.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal_spc.asm new file mode 100644 index 00000000..36bef7da --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Video 15 Frames Per Second 15 Color 8 Palette Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "VIDEO15FPS15Col8Pal.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/make.bat b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/make.bat new file mode 100644 index 00000000..1fd2f463 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/make.bat @@ -0,0 +1,2 @@ +bass VIDEO15FPS15Col8Pal_spc.asm +bass VIDEO15FPS15Col8Pal.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/manifest.bml b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/manifest.bml new file mode 100644 index 00000000..136db348 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=VIDEO15FPS15Col8Pal.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=VIDEO15FPS15Col8Pal.msu size=0 + track number=0 name=VIDEO15FPS15Col8Pal-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Video 15 Frames Per Second 15 Color 8 Palette diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..0d4449b0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "VIDEO 15FPS 16COL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/TileMap256x224.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/TileMap256x224.asm new file mode 100644 index 00000000..efce79e4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/TileMap256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $080, $081, $082, $083, $084, $085, $086, $087, $088, $089, $08a, $08b, $08c, $08d, $08e, $08f, $090, $091, $092, $093, $094, $095, $096, $097, $098, $099, $09a, $09b, $09c, $09d, $09e, $09f +dw $0a0, $0a1, $0a2, $0a3, $0a4, $0a5, $0a6, $0a7, $0a8, $0a9, $0aa, $0ab, $0ac, $0ad, $0ae, $0af, $0b0, $0b1, $0b2, $0b3, $0b4, $0b5, $0b6, $0b7, $0b8, $0b9, $0ba, $0bb, $0bc, $0bd, $0be, $0bf +dw $0c0, $0c1, $0c2, $0c3, $0c4, $0c5, $0c6, $0c7, $0c8, $0c9, $0ca, $0cb, $0cc, $0cd, $0ce, $0cf, $0d0, $0d1, $0d2, $0d3, $0d4, $0d5, $0d6, $0d7, $0d8, $0d9, $0da, $0db, $0dc, $0dd, $0de, $0df +dw $0e0, $0e1, $0e2, $0e3, $0e4, $0e5, $0e6, $0e7, $0e8, $0e9, $0ea, $0eb, $0ec, $0ed, $0ee, $0ef, $0f0, $0f1, $0f2, $0f3, $0f4, $0f5, $0f6, $0f7, $0f8, $0f9, $0fa, $0fb, $0fc, $0fd, $0fe, $0ff +dw $100, $101, $102, $103, $104, $105, $106, $107, $108, $109, $10a, $10b, $10c, $10d, $10e, $10f, $110, $111, $112, $113, $114, $115, $116, $117, $118, $119, $11a, $11b, $11c, $11d, $11e, $11f +dw $120, $121, $122, $123, $124, $125, $126, $127, $128, $129, $12a, $12b, $12c, $12d, $12e, $12f, $130, $131, $132, $133, $134, $135, $136, $137, $138, $139, $13a, $13b, $13c, $13d, $13e, $13f +dw $140, $141, $142, $143, $144, $145, $146, $147, $148, $149, $14a, $14b, $14c, $14d, $14e, $14f, $150, $151, $152, $153, $154, $155, $156, $157, $158, $159, $15a, $15b, $15c, $15d, $15e, $15f +dw $160, $161, $162, $163, $164, $165, $166, $167, $168, $169, $16a, $16b, $16c, $16d, $16e, $16f, $170, $171, $172, $173, $174, $175, $176, $177, $178, $179, $17a, $17b, $17c, $17d, $17e, $17f +dw $180, $181, $182, $183, $184, $185, $186, $187, $188, $189, $18a, $18b, $18c, $18d, $18e, $18f, $190, $191, $192, $193, $194, $195, $196, $197, $198, $199, $19a, $19b, $19c, $19d, $19e, $19f +dw $1a0, $1a1, $1a2, $1a3, $1a4, $1a5, $1a6, $1a7, $1a8, $1a9, $1aa, $1ab, $1ac, $1ad, $1ae, $1af, $1b0, $1b1, $1b2, $1b3, $1b4, $1b5, $1b6, $1b7, $1b8, $1b9, $1ba, $1bb, $1bc, $1bd, $1be, $1bf +dw $1c0, $1c1, $1c2, $1c3, $1c4, $1c5, $1c6, $1c7, $1c8, $1c9, $1ca, $1cb, $1cc, $1cd, $1ce, $1cf, $1d0, $1d1, $1d2, $1d3, $1d4, $1d5, $1d6, $1d7, $1d8, $1d9, $1da, $1db, $1dc, $1dd, $1de, $1df +dw $1e0, $1e1, $1e2, $1e3, $1e4, $1e5, $1e6, $1e7, $1e8, $1e9, $1ea, $1eb, $1ec, $1ed, $1ee, $1ef, $1f0, $1f1, $1f2, $1f3, $1f4, $1f5, $1f6, $1f7, $1f8, $1f9, $1fa, $1fb, $1fc, $1fd, $1fe, $1ff +dw $200, $201, $202, $203, $204, $205, $206, $207, $208, $209, $20a, $20b, $20c, $20d, $20e, $20f, $210, $211, $212, $213, $214, $215, $216, $217, $218, $219, $21a, $21b, $21c, $21d, $21e, $21f +dw $220, $221, $222, $223, $224, $225, $226, $227, $228, $229, $22a, $22b, $22c, $22d, $22e, $22f, $230, $231, $232, $233, $234, $235, $236, $237, $238, $239, $23a, $23b, $23c, $23d, $23e, $23f +dw $240, $241, $242, $243, $244, $245, $246, $247, $248, $249, $24a, $24b, $24c, $24d, $24e, $24f, $250, $251, $252, $253, $254, $255, $256, $257, $258, $259, $25a, $25b, $25c, $25d, $25e, $25f +dw $260, $261, $262, $263, $264, $265, $266, $267, $268, $269, $26a, $26b, $26c, $26d, $26e, $26f, $270, $271, $272, $273, $274, $275, $276, $277, $278, $279, $27a, $27b, $27c, $27d, $27e, $27f +dw $280, $281, $282, $283, $284, $285, $286, $287, $288, $289, $28a, $28b, $28c, $28d, $28e, $28f, $290, $291, $292, $293, $294, $295, $296, $297, $298, $299, $29a, $29b, $29c, $29d, $29e, $29f +dw $2a0, $2a1, $2a2, $2a3, $2a4, $2a5, $2a6, $2a7, $2a8, $2a9, $2aa, $2ab, $2ac, $2ad, $2ae, $2af, $2b0, $2b1, $2b2, $2b3, $2b4, $2b5, $2b6, $2b7, $2b8, $2b9, $2ba, $2bb, $2bc, $2bd, $2be, $2bf +dw $2c0, $2c1, $2c2, $2c3, $2c4, $2c5, $2c6, $2c7, $2c8, $2c9, $2ca, $2cb, $2cc, $2cd, $2ce, $2cf, $2d0, $2d1, $2d2, $2d3, $2d4, $2d5, $2d6, $2d7, $2d8, $2d9, $2da, $2db, $2dc, $2dd, $2de, $2df +dw $2e0, $2e1, $2e2, $2e3, $2e4, $2e5, $2e6, $2e7, $2e8, $2e9, $2ea, $2eb, $2ec, $2ed, $2ee, $2ef, $2f0, $2f1, $2f2, $2f3, $2f4, $2f5, $2f6, $2f7, $2f8, $2f9, $2fa, $2fb, $2fc, $2fd, $2fe, $2ff +dw $300, $301, $302, $303, $304, $305, $306, $307, $308, $309, $30a, $30b, $30c, $30d, $30e, $30f, $310, $311, $312, $313, $314, $315, $316, $317, $318, $319, $31a, $31b, $31c, $31d, $31e, $31f +dw $320, $321, $322, $323, $324, $325, $326, $327, $328, $329, $32a, $32b, $32c, $32d, $32e, $32f, $330, $331, $332, $333, $334, $335, $336, $337, $338, $339, $33a, $33b, $33c, $33d, $33e, $33f +dw $340, $341, $342, $343, $344, $345, $346, $347, $348, $349, $34a, $34b, $34c, $34d, $34e, $34f, $350, $351, $352, $353, $354, $355, $356, $357, $358, $359, $35a, $35b, $35c, $35d, $35e, $35f +dw $360, $361, $362, $363, $364, $365, $366, $367, $368, $369, $36a, $36b, $36c, $36d, $36e, $36f, $370, $371, $372, $373, $374, $375, $376, $377, $378, $379, $37a, $37b, $37c, $37d, $37e, $37f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col-0.pcm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col-0.pcm new file mode 100644 index 00000000..aed0a4db Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.asm new file mode 100644 index 00000000..800c961d --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.asm @@ -0,0 +1,199 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "VIDEO15FPS16Col.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #$02 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + LoadVRAM(BGMap, $7900, 1792, 0) // Load Frame 1 Background Tile Map To VRAM + LoadVRAM(BGMap, $F900, 1792, 0) // Load Frame 2 Background Tile Map To VRAM + + // Setup Tile DMA On Channel 0 + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + ldx.w #1528>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + +VIDLoop: + ldx.w #7168 // VRAM Size In Bytes To DMA Transfer + + //////////////////////////////////////////////////////// + ldy.w #$0000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000101 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #32 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000111 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + ldy.w #$8000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000101 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #32 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000111 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG2 16 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $F800 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 6, %10000000 // Repeat 6 Scanlines, Turn Off Screen, Zero Brightness + db 26, %00001111 // Repeat 26 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +BGMap: + include "TileMap256x224.asm" // Include BG Map Data (1792 Bytes) + +// SPC Code +// BANK 0 +insert SPCROM, "VIDEO15FPS16Col.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.msu b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.msu new file mode 100644 index 00000000..f39236c1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.msu differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.png b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.png new file mode 100644 index 00000000..9b7c125d Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.sfc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.sfc new file mode 100644 index 00000000..3af99992 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.spc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col_spc.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col_spc.asm new file mode 100644 index 00000000..4cb7e6e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "VIDEO15FPS16Col.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/make.bat b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/make.bat new file mode 100644 index 00000000..e66822e9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/make.bat @@ -0,0 +1,2 @@ +bass VIDEO15FPS16Col_spc.asm +bass VIDEO15FPS16Col.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/manifest.bml b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/manifest.bml new file mode 100644 index 00000000..57b92929 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=VIDEO15FPS16Col.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=VIDEO15FPS16Col.msu size=0 + track number=0 name=VIDEO15FPS16Col-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Video 15 Frames Per Second 16 Color diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..188cfb55 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "VIDEO 15FPS 16COL8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/TileMap8PAL256x224.asm new file mode 100644 index 00000000..d127b2b2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $0000, $0001, $0002, $0003, $0004, $0005, $0006, $0007, $0008, $0009, $000a, $000b, $000c, $000d, $000e, $000f, $0010, $0011, $0012, $0013, $0014, $0015, $0016, $0017, $0018, $0019, $001a, $001b, $001c, $001d, $001e, $001f +dw $0020, $0021, $0022, $0023, $0024, $0025, $0026, $0027, $0028, $0029, $002a, $002b, $002c, $002d, $002e, $002f, $0030, $0031, $0032, $0033, $0034, $0035, $0036, $0037, $0038, $0039, $003a, $003b, $003c, $003d, $003e, $003f +dw $0040, $0041, $0042, $0043, $0044, $0045, $0046, $0047, $0048, $0049, $004a, $004b, $004c, $004d, $004e, $004f, $0050, $0051, $0052, $0053, $0054, $0055, $0056, $0057, $0058, $0059, $005a, $005b, $005c, $005d, $005e, $005f +dw $0060, $0061, $0062, $0063, $0064, $0065, $0066, $0067, $0068, $0069, $006a, $006b, $006c, $006d, $006e, $006f, $0070, $0071, $0072, $0073, $0074, $0075, $0076, $0077, $0078, $0079, $007a, $007b, $007c, $007d, $007e, $007f +dw $0480, $0481, $0482, $0483, $0484, $0485, $0486, $0487, $0488, $0489, $048a, $048b, $048c, $048d, $048e, $048f, $0490, $0491, $0492, $0493, $0494, $0495, $0496, $0497, $0498, $0499, $049a, $049b, $049c, $049d, $049e, $049f +dw $04a0, $04a1, $04a2, $04a3, $04a4, $04a5, $04a6, $04a7, $04a8, $04a9, $04aa, $04ab, $04ac, $04ad, $04ae, $04af, $04b0, $04b1, $04b2, $04b3, $04b4, $04b5, $04b6, $04b7, $04b8, $04b9, $04ba, $04bb, $04bc, $04bd, $04be, $04bf +dw $04c0, $04c1, $04c2, $04c3, $04c4, $04c5, $04c6, $04c7, $04c8, $04c9, $04ca, $04cb, $04cc, $04cd, $04ce, $04cf, $04d0, $04d1, $04d2, $04d3, $04d4, $04d5, $04d6, $04d7, $04d8, $04d9, $04da, $04db, $04dc, $04dd, $04de, $04df +dw $04e0, $04e1, $04e2, $04e3, $04e4, $04e5, $04e6, $04e7, $04e8, $04e9, $04ea, $04eb, $04ec, $04ed, $04ee, $04ef, $04f0, $04f1, $04f2, $04f3, $04f4, $04f5, $04f6, $04f7, $04f8, $04f9, $04fa, $04fb, $04fc, $04fd, $04fe, $04ff +dw $0900, $0901, $0902, $0903, $0904, $0905, $0906, $0907, $0908, $0909, $090a, $090b, $090c, $090d, $090e, $090f, $0910, $0911, $0912, $0913, $0914, $0915, $0916, $0917, $0918, $0919, $091a, $091b, $091c, $091d, $091e, $091f +dw $0920, $0921, $0922, $0923, $0924, $0925, $0926, $0927, $0928, $0929, $092a, $092b, $092c, $092d, $092e, $092f, $0930, $0931, $0932, $0933, $0934, $0935, $0936, $0937, $0938, $0939, $093a, $093b, $093c, $093d, $093e, $093f +dw $0940, $0941, $0942, $0943, $0944, $0945, $0946, $0947, $0948, $0949, $094a, $094b, $094c, $094d, $094e, $094f, $0950, $0951, $0952, $0953, $0954, $0955, $0956, $0957, $0958, $0959, $095a, $095b, $095c, $095d, $095e, $095f +dw $0D60, $0D61, $0D62, $0D63, $0D64, $0D65, $0D66, $0D67, $0D68, $0D69, $0D6a, $0D6b, $0D6c, $0D6d, $0D6e, $0D6f, $0D70, $0D71, $0D72, $0D73, $0D74, $0D75, $0D76, $0D77, $0D78, $0D79, $0D7a, $0D7b, $0D7c, $0D7d, $0D7e, $0D7f +dw $0D80, $0D81, $0D82, $0D83, $0D84, $0D85, $0D86, $0D87, $0D88, $0D89, $0D8a, $0D8b, $0D8c, $0D8d, $0D8e, $0D8f, $0D90, $0D91, $0D92, $0D93, $0D94, $0D95, $0D96, $0D97, $0D98, $0D99, $0D9a, $0D9b, $0D9c, $0D9d, $0D9e, $0D9f +dw $0Da0, $0Da1, $0Da2, $0Da3, $0Da4, $0Da5, $0Da6, $0Da7, $0Da8, $0Da9, $0Daa, $0Dab, $0Dac, $0Dad, $0Dae, $0Daf, $0Db0, $0Db1, $0Db2, $0Db3, $0Db4, $0Db5, $0Db6, $0Db7, $0Db8, $0Db9, $0Dba, $0Dbb, $0Dbc, $0Dbd, $0Dbe, $0Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal-0.pcm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal-0.pcm new file mode 100644 index 00000000..aed0a4db Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.asm new file mode 100644 index 00000000..2babac70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.asm @@ -0,0 +1,203 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color 8 Palette Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "VIDEO15FPS16Col8Pal.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup Frame 1 & 2 Background Tile Map + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + LoadVRAM(BGMap, $7900, 1792, 0) // Load Frame 1 & 2 Background Tile Map To VRAM + + // Setup Tile DMA On Channel 0 + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + ldx.w #1528>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + + WaitNMI() // Wait For Vertical Blank + +VIDLoop: + //////////////////////////////////////////////////////// + ldx.w #7232 // VRAM Size In Bytes To DMA Transfer + ldy.w #$0000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + ldx.w #6976 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #256 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + + //////////////////////////////////////////////////////// + ldx.w #7232 // VRAM Size In Bytes To DMA Transfer + ldy.w #$8000 >> 1 // VRAM Destination + sty.w REG_VMADDL // $2116: VRAM + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + ldx.w #6976 // VRAM Size In Bytes To DMA Transfer + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + ldy.w #256 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG2 16 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $8000 (VRAM Address / $1000) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 7, %10000000 // Repeat 7 Scanlines, Turn Off Screen, Zero Brightness + db 25, %00001111 // Repeat 25 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) + +// SPC Code +// BANK 0 +insert SPCROM, "VIDEO15FPS16Col8Pal.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.msu b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.msu new file mode 100644 index 00000000..f4c210d9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.msu differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.png b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.png new file mode 100644 index 00000000..88e7f640 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.sfc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.sfc new file mode 100644 index 00000000..c116fb99 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.spc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal_spc.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal_spc.asm new file mode 100644 index 00000000..4f75510e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color 8 Palette Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "VIDEO15FPS16Col8Pal.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/make.bat b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/make.bat new file mode 100644 index 00000000..35a86b2b --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/make.bat @@ -0,0 +1,2 @@ +bass VIDEO15FPS16Col8Pal_spc.asm +bass VIDEO15FPS16Col8Pal.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/manifest.bml b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/manifest.bml new file mode 100644 index 00000000..5cc9ce6b --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=VIDEO15FPS16Col8Pal.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=VIDEO15FPS16Col8Pal.msu size=0 + track number=0 name=VIDEO15FPS16Col8Pal-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Video 15 Frames Per Second 16 Color 8 Palette diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..26e8349e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "VIDEO 15FPS 16COL INT" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_MSU1.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_MSU1.INC new file mode 100644 index 00000000..c1ae557e --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_MSU1.INC @@ -0,0 +1,120 @@ +//=========== +// SNES MSU1 +//=========== + +// MSU1 Read Registers +constant MSU_STATUS($2000) // MSU1 Status Register 1B/R +constant MSU_READ($2001) // MSU1 Read Register 1B/R +constant MSU_ID($2002) // MSU1 ID Register ("S-MSU1") 6B/R + +// MSU1 Write Registers +constant MSU_SEEK($2000) // MSU1 Seek Register 2B/W +constant MSU_SEEKBANK($2002) // MSU1 Seek Bank Register 2B/W +constant MSU_TRACK($2004) // MSU1 Track Register 2B/W +constant MSU_VOLUME($2006) // MSU1 Volume Register 1B/W +constant MSU_CONTROL($2007) // MSU1 Control Register 1B/W + +macro MSUWaitAudioBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bvs - // Wait For MSU1 Audio Busy Flag Status Bit To Clear +} + +macro MSUWaitDataBusy() { + - + bit.w MSU_STATUS // $2000: MSU1 Status Register + bmi - // Wait For MSU1 Data Busy Flag Status Bit To Clear +} + +//============================================================= +// MSULoadPAL - Load Palette Data To CGRAM (Seek Position Set) +//============================================================= +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadPAL(DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + lda.b #$08 + sta.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Fixed Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================================= +// MSULoadVRAM - Load GFX Data To VRAM (Seek Position Set) +//========================================================= +// DEST: 16-Bit VRAM Destination Address (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadVRAM(DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 // Set DMA Mode (Write Word, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================================================= +// MSULoadM7VRAM - Load Mode7 GFX Data To VRAM (Seek Position Set) +//================================================================= +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro MSULoadM7VRAM(DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + stz.w REG_A1B{CHAN} // Set Source Bank To Zero ($43X4: Source Bank) + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #MSU_READ // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace-0.pcm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace-0.pcm new file mode 100644 index 00000000..67a6eb16 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace-0.pcm differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.asm new file mode 100644 index 00000000..03306090 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.asm @@ -0,0 +1,193 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color Interlace Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "VIDEO15FPS16ColInterlace.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_MSU1.INC" // Include MSU1 Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +FrameCount: + dw 0 // Frame Count Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG1 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + +RestartVid: + // Audio + lda.b #$FF // Load Audio Volume Byte + sta.w MSU_VOLUME // $2006: MSU1 Volume Register + + ldx.w #$0000 // Load Track Number 0 + stx.w MSU_TRACK // $2004: MSU1 Track Register + MSUWaitAudioBusy() // Wait For MSU1 Audio Busy Flag Status Bit To Clear + + lda.b #%00000011 // Play & Repeat Sound (%000000RP R = Repeat On/Off, P = Play On/Off) + sta.w MSU_CONTROL // $2007: MSU1 Control Register + + // Video + ldx.w #$0000 // Seek To $0000:0000, In The Data .MSU File + stx.w MSU_SEEK // $2000: MSU1 Seek Register + ldx.w #$0000 // Set Seek Bank Register + stx.w MSU_SEEKBANK // $2002: MSU1 Seek Bank Register + MSUWaitDataBusy() // Wait For MSU1 Data Busy Flag Status Bit To Clear + + // Setup Tile DMA On Channel 0 + ldx.w #$0000 // VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$09 + sta.w REG_DMAP0 // Set DMA Mode (Word, Normal Non Increment) ($4300: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T0L // Store Data Offset Into DMA Source Offset ($4302: DMA Source) + stz.w REG_A1B0 // Store Zero Into DMA Source Bank ($4304: Source Bank) + + // Setup Palette DMA On Channel 1 + lda.b #$08 + sta.w REG_DMAP1 // Set DMA Mode (Byte, Normal Non Increment) ($4310: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + ldx.w #MSU_READ // Source Data + stx.w REG_A1T1L // Store Data Offset Into DMA Source Offset ($4312: DMA Source) + stz.w REG_A1B1 // Store Zero Into DMA Source Bank ($4314: Source Bank) + + WaitNMI() // Wait For Vertical Blank Before Starting HDMA + + // Screen Display HDMA Channel 2 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start Screen Display ($2100) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + lda.b #%00000100 // HDMA Channel Select (Channel 2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + ldx.w #770>>1 // Load Frame Count / 2 + stx.b FrameCount // Store Frame Count + + ldy.w #32 // CGRAM Size In Bytes To DMA Transfer (2 Bytes For Each Colour) +VIDLoop: + ldx.w #8192 // VRAM Size In Bytes To DMA Transfer + + //////////////////////////////////////////////////////// + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 1 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 1 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 1 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 1 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 1 BG1 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $7200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + lda.b #%00000001 // Initiate DMA Transfer (Channel 0) + WaitNMI() // Wait For Frame 2 1st Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 2nd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data To VRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + WaitNMI() // Wait For Frame 2 3rd Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Frame 2 Tile Data & Map To VRAM, Followed By Palette To CGRAM + stz.w REG_CGADD // $2121: CGRAM + stx.w REG_DAS0L // Store Size Of Data Block ($4305: DMA Transfer Size/HDMA) + sty.w REG_DAS1L // Store Size Of Data Block ($4315: DMA Transfer Size/HDMA) + lda.b #%00000011 // Initiate DMA Transfer (Channel 0&1) + WaitNMI() // Wait For Frame 2 4th Vertical Blank + sta.w REG_MDMAEN // $420B: DMA Enable + + // Setup Frame 2 BG1 16 Colour Background + lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $8000 (VRAM Address / $1000) + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + + //////////////////////////////////////////////////////// + + ldx.w FrameCount + dex + stx.w FrameCount + beq Restart + jmp VIDLoop +Restart: + jmp RestartVid + +HDMATable: + db 12, %10000000 // Repeat 12 Scanlines, Turn Off Screen, Zero Brightness + db 20, %00001111 // Repeat 20 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 32, %00001111 // Repeat 32 Scanlines, Turn On Screen, Full Brightness + db 1, %10000000 // Repeat 1 Scanline, Turn Off Screen, Zero Brightness + db $00 // End Of HDMA + +// SPC Code +// BANK 0 +insert SPCROM, "VIDEO15FPS16ColInterlace.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.msu b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.msu new file mode 100644 index 00000000..63f54f1b Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.msu differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.png b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.png new file mode 100644 index 00000000..2c0b6a58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.png differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.sfc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.sfc new file mode 100644 index 00000000..0b07f0a3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.sfc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.spc b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.spc new file mode 100644 index 00000000..b9c058fa Binary files /dev/null and b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.spc differ diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace_spc.asm b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace_spc.asm new file mode 100644 index 00000000..494a9450 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace_spc.asm @@ -0,0 +1,16 @@ +// SNES MSU1 Video 15 Frames Per Second 16 Color Interlace Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "VIDEO15FPS16ColInterlace.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/make.bat b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/make.bat new file mode 100644 index 00000000..e9dd48d5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/make.bat @@ -0,0 +1,2 @@ +bass VIDEO15FPS16ColInterlace_spc.asm +bass VIDEO15FPS16ColInterlace.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/manifest.bml b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/manifest.bml new file mode 100644 index 00000000..845d3317 --- /dev/null +++ b/roms/snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/manifest.bml @@ -0,0 +1,12 @@ +cartridge region=NTSC + rom name=VIDEO15FPS16ColInterlace.sfc size=0x8000 + map id=rom address=00-3f,80-bf:8000-ffff + map id=rom address=40-7f,c0-ff:0000-ffff + + msu1 + rom name=VIDEO15FPS16ColInterlace.msu size=0 + track number=0 name=VIDEO15FPS16ColInterlace-0.pcm + map id=io address=00-3f,80-bf:2000-2007 + +information + title: Video 15 Frames Per Second 16 Color Interlace diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.asm new file mode 100644 index 00000000..ed1c56a2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.asm @@ -0,0 +1,50 @@ +// SNES PPU BG1 8x8 2BPP 32x32 8 Palette Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BG1Map2BPP32x328PAL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 32 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, 1792, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00000000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 0, BG1 8x8 Tiles + + // Setup BG1 4 Colour Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG2 Map Address = $F800 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX\BG.pal" // Include BG Palette Data ($64 Bytes) +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data ($14336 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.png new file mode 100644 index 00000000..685f9ddd Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.sfc new file mode 100644 index 00000000..259615ae Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pal new file mode 100644 index 00000000..f6cb5acf --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pal @@ -0,0 +1 @@ +j!i~XoIM~zo(6vV{ OZ R"U$t&o$q^X2 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pic new file mode 100644 index 00000000..cd2c7ff6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGA.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGA.png new file mode 100644 index 00000000..0b0f540c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGB.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGB.png new file mode 100644 index 00000000..65e62688 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGB.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGC.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGC.png new file mode 100644 index 00000000..2a22b49a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGC.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGD.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGD.png new file mode 100644 index 00000000..e0b68894 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGD.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGE.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGE.png new file mode 100644 index 00000000..86b37960 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGE.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGF.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGF.png new file mode 100644 index 00000000..9a082012 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGF.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGG.png new file mode 100644 index 00000000..ff1e1cea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGH.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGH.png new file mode 100644 index 00000000..010c3c58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/GFX/BGH.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..229f18dc --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG1 8X8 2BPP 8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/TileMap8PAL256x224.asm new file mode 100644 index 00000000..1d053a3b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $480, $481, $482, $483, $484, $485, $486, $487, $488, $489, $48a, $48b, $48c, $48d, $48e, $48f, $490, $491, $492, $493, $494, $495, $496, $497, $498, $499, $49a, $49b, $49c, $49d, $49e, $49f +dw $4a0, $4a1, $4a2, $4a3, $4a4, $4a5, $4a6, $4a7, $4a8, $4a9, $4aa, $4ab, $4ac, $4ad, $4ae, $4af, $4b0, $4b1, $4b2, $4b3, $4b4, $4b5, $4b6, $4b7, $4b8, $4b9, $4ba, $4bb, $4bc, $4bd, $4be, $4bf +dw $4c0, $4c1, $4c2, $4c3, $4c4, $4c5, $4c6, $4c7, $4c8, $4c9, $4ca, $4cb, $4cc, $4cd, $4ce, $4cf, $4d0, $4d1, $4d2, $4d3, $4d4, $4d5, $4d6, $4d7, $4d8, $4d9, $4da, $4db, $4dc, $4dd, $4de, $4df +dw $4e0, $4e1, $4e2, $4e3, $4e4, $4e5, $4e6, $4e7, $4e8, $4e9, $4ea, $4eb, $4ec, $4ed, $4ee, $4ef, $4f0, $4f1, $4f2, $4f3, $4f4, $4f5, $4f6, $4f7, $4f8, $4f9, $4fa, $4fb, $4fc, $4fd, $4fe, $4ff +dw $900, $901, $902, $903, $904, $905, $906, $907, $908, $909, $90a, $90b, $90c, $90d, $90e, $90f, $910, $911, $912, $913, $914, $915, $916, $917, $918, $919, $91a, $91b, $91c, $91d, $91e, $91f +dw $920, $921, $922, $923, $924, $925, $926, $927, $928, $929, $92a, $92b, $92c, $92d, $92e, $92f, $930, $931, $932, $933, $934, $935, $936, $937, $938, $939, $93a, $93b, $93c, $93d, $93e, $93f +dw $940, $941, $942, $943, $944, $945, $946, $947, $948, $949, $94a, $94b, $94c, $94d, $94e, $94f, $950, $951, $952, $953, $954, $955, $956, $957, $958, $959, $95a, $95b, $95c, $95d, $95e, $95f +dw $D60, $D61, $D62, $D63, $D64, $D65, $D66, $D67, $D68, $D69, $D6a, $D6b, $D6c, $D6d, $D6e, $D6f, $D70, $D71, $D72, $D73, $D74, $D75, $D76, $D77, $D78, $D79, $D7a, $D7b, $D7c, $D7d, $D7e, $D7f +dw $D80, $D81, $D82, $D83, $D84, $D85, $D86, $D87, $D88, $D89, $D8a, $D8b, $D8c, $D8d, $D8e, $D8f, $D90, $D91, $D92, $D93, $D94, $D95, $D96, $D97, $D98, $D99, $D9a, $D9b, $D9c, $D9d, $D9e, $D9f +dw $Da0, $Da1, $Da2, $Da3, $Da4, $Da5, $Da6, $Da7, $Da8, $Da9, $Daa, $Dab, $Dac, $Dad, $Dae, $Daf, $Db0, $Db1, $Db2, $Db3, $Db4, $Db5, $Db6, $Db7, $Db8, $Db9, $Dba, $Dbb, $Dbc, $Dbd, $Dbe, $Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/make.bat new file mode 100644 index 00000000..edd9c708 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/make.bat @@ -0,0 +1 @@ +bass 8x8BG1Map2BPP32x328PAL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.asm new file mode 100644 index 00000000..d3140bac --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.asm @@ -0,0 +1,50 @@ +// SNES PPU BG2 8x8 2BPP 32x32 8 Palette Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BG2Map2BPP32x328PAL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $20, BGPal.size, 0) // Load Background Palette (BG Palette Uses 32 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, 1792, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00000000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 0, BG2 8x8 Tiles + + // Setup BG2 4 Colour Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2107: BG2 32x32, BG2 Map Address = $F800 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX\BG.pal" // Include BG Palette Data ($64 Bytes) +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data ($14336 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.png new file mode 100644 index 00000000..d49b38f0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.sfc new file mode 100644 index 00000000..4b00726b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pal new file mode 100644 index 00000000..f6cb5acf --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pal @@ -0,0 +1 @@ +j!i~XoIM~zo(6vV{ OZ R"U$t&o$q^X2 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pic new file mode 100644 index 00000000..cd2c7ff6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGA.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGA.png new file mode 100644 index 00000000..0b0f540c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGB.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGB.png new file mode 100644 index 00000000..65e62688 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGB.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGC.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGC.png new file mode 100644 index 00000000..2a22b49a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGC.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGD.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGD.png new file mode 100644 index 00000000..e0b68894 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGD.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGE.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGE.png new file mode 100644 index 00000000..86b37960 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGE.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGF.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGF.png new file mode 100644 index 00000000..9a082012 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGF.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGG.png new file mode 100644 index 00000000..ff1e1cea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGH.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGH.png new file mode 100644 index 00000000..010c3c58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/GFX/BGH.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..724e04b7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG2 8X8 2BPP 8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/TileMap8PAL256x224.asm new file mode 100644 index 00000000..1d053a3b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $480, $481, $482, $483, $484, $485, $486, $487, $488, $489, $48a, $48b, $48c, $48d, $48e, $48f, $490, $491, $492, $493, $494, $495, $496, $497, $498, $499, $49a, $49b, $49c, $49d, $49e, $49f +dw $4a0, $4a1, $4a2, $4a3, $4a4, $4a5, $4a6, $4a7, $4a8, $4a9, $4aa, $4ab, $4ac, $4ad, $4ae, $4af, $4b0, $4b1, $4b2, $4b3, $4b4, $4b5, $4b6, $4b7, $4b8, $4b9, $4ba, $4bb, $4bc, $4bd, $4be, $4bf +dw $4c0, $4c1, $4c2, $4c3, $4c4, $4c5, $4c6, $4c7, $4c8, $4c9, $4ca, $4cb, $4cc, $4cd, $4ce, $4cf, $4d0, $4d1, $4d2, $4d3, $4d4, $4d5, $4d6, $4d7, $4d8, $4d9, $4da, $4db, $4dc, $4dd, $4de, $4df +dw $4e0, $4e1, $4e2, $4e3, $4e4, $4e5, $4e6, $4e7, $4e8, $4e9, $4ea, $4eb, $4ec, $4ed, $4ee, $4ef, $4f0, $4f1, $4f2, $4f3, $4f4, $4f5, $4f6, $4f7, $4f8, $4f9, $4fa, $4fb, $4fc, $4fd, $4fe, $4ff +dw $900, $901, $902, $903, $904, $905, $906, $907, $908, $909, $90a, $90b, $90c, $90d, $90e, $90f, $910, $911, $912, $913, $914, $915, $916, $917, $918, $919, $91a, $91b, $91c, $91d, $91e, $91f +dw $920, $921, $922, $923, $924, $925, $926, $927, $928, $929, $92a, $92b, $92c, $92d, $92e, $92f, $930, $931, $932, $933, $934, $935, $936, $937, $938, $939, $93a, $93b, $93c, $93d, $93e, $93f +dw $940, $941, $942, $943, $944, $945, $946, $947, $948, $949, $94a, $94b, $94c, $94d, $94e, $94f, $950, $951, $952, $953, $954, $955, $956, $957, $958, $959, $95a, $95b, $95c, $95d, $95e, $95f +dw $D60, $D61, $D62, $D63, $D64, $D65, $D66, $D67, $D68, $D69, $D6a, $D6b, $D6c, $D6d, $D6e, $D6f, $D70, $D71, $D72, $D73, $D74, $D75, $D76, $D77, $D78, $D79, $D7a, $D7b, $D7c, $D7d, $D7e, $D7f +dw $D80, $D81, $D82, $D83, $D84, $D85, $D86, $D87, $D88, $D89, $D8a, $D8b, $D8c, $D8d, $D8e, $D8f, $D90, $D91, $D92, $D93, $D94, $D95, $D96, $D97, $D98, $D99, $D9a, $D9b, $D9c, $D9d, $D9e, $D9f +dw $Da0, $Da1, $Da2, $Da3, $Da4, $Da5, $Da6, $Da7, $Da8, $Da9, $Daa, $Dab, $Dac, $Dad, $Dae, $Daf, $Db0, $Db1, $Db2, $Db3, $Db4, $Db5, $Db6, $Db7, $Db8, $Db9, $Dba, $Dbb, $Dbc, $Dbd, $Dbe, $Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/make.bat new file mode 100644 index 00000000..c924589d --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/make.bat @@ -0,0 +1 @@ +bass 8x8BG2Map2BPP32x328PAL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.asm new file mode 100644 index 00000000..7ebbee21 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.asm @@ -0,0 +1,50 @@ +// SNES PPU BG3 8x8 2BPP 32x32 8 Palette Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BG3Map2BPP32x328PAL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $40, BGPal.size, 0) // Load Background Palette (BG Palette Uses 32 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, 1792, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00000000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 0, BG3 8x8 Tiles + + // Setup BG3 4 Colour Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG3SC // $2107: BG2 32x32, BG3 Map Address = $F800 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG3 Tile Address, B = BG4 Tile Address + sta.w REG_BG34NBA // $210B: BG3 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000100 // Enable BG3 + sta.w REG_TM // $212C: BG3 To Main Screen Designation + + stz.w REG_BG3HOFS // Store Zero To BG3 Horizontal Scroll Pos Low Byte + stz.w REG_BG3HOFS // Store Zero To BG3 Horizontal Scroll Pos High Byte + stz.w REG_BG3VOFS // Store Zero To BG3 Vertical Scroll Pos Low Byte + stz.w REG_BG3VOFS // Store Zero To BG3 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX\BG.pal" // Include BG Palette Data ($64 Bytes) +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data ($14336 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.png new file mode 100644 index 00000000..d49b38f0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.sfc new file mode 100644 index 00000000..05685d99 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pal new file mode 100644 index 00000000..f6cb5acf --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pal @@ -0,0 +1 @@ +j!i~XoIM~zo(6vV{ OZ R"U$t&o$q^X2 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pic new file mode 100644 index 00000000..cd2c7ff6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGA.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGA.png new file mode 100644 index 00000000..0b0f540c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGB.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGB.png new file mode 100644 index 00000000..65e62688 Binary files /dev/null and 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files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGE.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGF.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGF.png new file mode 100644 index 00000000..9a082012 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGF.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGG.png new file mode 100644 index 00000000..ff1e1cea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGH.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGH.png new file mode 100644 index 00000000..010c3c58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/GFX/BGH.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..ca9ad690 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG3 8X8 2BPP 8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/TileMap8PAL256x224.asm new file mode 100644 index 00000000..1d053a3b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $480, $481, $482, $483, $484, $485, $486, $487, $488, $489, $48a, $48b, $48c, $48d, $48e, $48f, $490, $491, $492, $493, $494, $495, $496, $497, $498, $499, $49a, $49b, $49c, $49d, $49e, $49f +dw $4a0, $4a1, $4a2, $4a3, $4a4, $4a5, $4a6, $4a7, $4a8, $4a9, $4aa, $4ab, $4ac, $4ad, $4ae, $4af, $4b0, $4b1, $4b2, $4b3, $4b4, $4b5, $4b6, $4b7, $4b8, $4b9, $4ba, $4bb, $4bc, $4bd, $4be, $4bf +dw $4c0, $4c1, $4c2, $4c3, $4c4, $4c5, $4c6, $4c7, $4c8, $4c9, $4ca, $4cb, $4cc, $4cd, $4ce, $4cf, $4d0, $4d1, $4d2, $4d3, $4d4, $4d5, $4d6, $4d7, $4d8, $4d9, $4da, $4db, $4dc, $4dd, $4de, $4df +dw $4e0, $4e1, $4e2, $4e3, $4e4, $4e5, $4e6, $4e7, $4e8, $4e9, $4ea, $4eb, $4ec, $4ed, $4ee, $4ef, $4f0, $4f1, $4f2, $4f3, $4f4, $4f5, $4f6, $4f7, $4f8, $4f9, $4fa, $4fb, $4fc, $4fd, $4fe, $4ff +dw $900, $901, $902, $903, $904, $905, $906, $907, $908, $909, $90a, $90b, $90c, $90d, $90e, $90f, $910, $911, $912, $913, $914, $915, $916, $917, $918, $919, $91a, $91b, $91c, $91d, $91e, $91f +dw $920, $921, $922, $923, $924, $925, $926, $927, $928, $929, $92a, $92b, $92c, $92d, $92e, $92f, $930, $931, $932, $933, $934, $935, $936, $937, $938, $939, $93a, $93b, $93c, $93d, $93e, $93f +dw $940, $941, $942, $943, $944, $945, $946, $947, $948, $949, $94a, $94b, $94c, $94d, $94e, $94f, $950, $951, $952, $953, $954, $955, $956, $957, $958, $959, $95a, $95b, $95c, $95d, $95e, $95f +dw $D60, $D61, $D62, $D63, $D64, $D65, $D66, $D67, $D68, $D69, $D6a, $D6b, $D6c, $D6d, $D6e, $D6f, $D70, $D71, $D72, $D73, $D74, $D75, $D76, $D77, $D78, $D79, $D7a, $D7b, $D7c, $D7d, $D7e, $D7f +dw $D80, $D81, $D82, $D83, $D84, $D85, $D86, $D87, $D88, $D89, $D8a, $D8b, $D8c, $D8d, $D8e, $D8f, $D90, $D91, $D92, $D93, $D94, $D95, $D96, $D97, $D98, $D99, $D9a, $D9b, $D9c, $D9d, $D9e, $D9f +dw $Da0, $Da1, $Da2, $Da3, $Da4, $Da5, $Da6, $Da7, $Da8, $Da9, $Daa, $Dab, $Dac, $Dad, $Dae, $Daf, $Db0, $Db1, $Db2, $Db3, $Db4, $Db5, $Db6, $Db7, $Db8, $Db9, $Dba, $Dbb, $Dbc, $Dbd, $Dbe, $Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/make.bat new file mode 100644 index 00000000..0f85ca1a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/make.bat @@ -0,0 +1 @@ +bass 8x8BG3Map2BPP32x328PAL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.asm new file mode 100644 index 00000000..10bf3467 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.asm @@ -0,0 +1,50 @@ +// SNES PPU BG4 8x8 2BPP 32x32 8 Palette Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BG4Map2BPP32x328PAL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $60, BGPal.size, 0) // Load Background Palette (BG Palette Uses 32 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, 1792, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00000000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 0, BG4 8x8 Tiles + + // Setup BG4 4 Colour Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG4SC // $2107: BG4 32x32, BG3 Map Address = $F800 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG3 Tile Address, B = BG4 Tile Address + sta.w REG_BG34NBA // $210B: BG4 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00001000 // Enable BG4 + sta.w REG_TM // $212C: BG4 To Main Screen Designation + + stz.w REG_BG4HOFS // Store Zero To BG4 Horizontal Scroll Pos Low Byte + stz.w REG_BG4HOFS // Store Zero To BG4 Horizontal Scroll Pos High Byte + stz.w REG_BG4VOFS // Store Zero To BG4 Vertical Scroll Pos Low Byte + stz.w REG_BG4VOFS // Store Zero To BG4 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX\BG.pal" // Include BG Palette Data ($64 Bytes) +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data ($14336 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.png new file mode 100644 index 00000000..d49b38f0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.sfc new file mode 100644 index 00000000..6b07b464 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pal new file mode 100644 index 00000000..f6cb5acf --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pal @@ -0,0 +1 @@ +j!i~XoIM~zo(6vV{ OZ R"U$t&o$q^X2 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pic new file mode 100644 index 00000000..cd2c7ff6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGA.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGA.png new file mode 100644 index 00000000..0b0f540c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGB.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGB.png new file mode 100644 index 00000000..65e62688 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGB.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGC.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGC.png new file mode 100644 index 00000000..2a22b49a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGC.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGD.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGD.png new file mode 100644 index 00000000..e0b68894 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGD.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGE.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGE.png new file mode 100644 index 00000000..86b37960 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGE.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGF.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGF.png new file mode 100644 index 00000000..9a082012 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGF.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGG.png new file mode 100644 index 00000000..ff1e1cea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGH.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGH.png new file mode 100644 index 00000000..010c3c58 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/GFX/BGH.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..2665afd8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG4 8X8 2BPP 8PAL" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/TileMap8PAL256x224.asm new file mode 100644 index 00000000..1d053a3b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $480, $481, $482, $483, $484, $485, $486, $487, $488, $489, $48a, $48b, $48c, $48d, $48e, $48f, $490, $491, $492, $493, $494, $495, $496, $497, $498, $499, $49a, $49b, $49c, $49d, $49e, $49f +dw $4a0, $4a1, $4a2, $4a3, $4a4, $4a5, $4a6, $4a7, $4a8, $4a9, $4aa, $4ab, $4ac, $4ad, $4ae, $4af, $4b0, $4b1, $4b2, $4b3, $4b4, $4b5, $4b6, $4b7, $4b8, $4b9, $4ba, $4bb, $4bc, $4bd, $4be, $4bf +dw $4c0, $4c1, $4c2, $4c3, $4c4, $4c5, $4c6, $4c7, $4c8, $4c9, $4ca, $4cb, $4cc, $4cd, $4ce, $4cf, $4d0, $4d1, $4d2, $4d3, $4d4, $4d5, $4d6, $4d7, $4d8, $4d9, $4da, $4db, $4dc, $4dd, $4de, $4df +dw $4e0, $4e1, $4e2, $4e3, $4e4, $4e5, $4e6, $4e7, $4e8, $4e9, $4ea, $4eb, $4ec, $4ed, $4ee, $4ef, $4f0, $4f1, $4f2, $4f3, $4f4, $4f5, $4f6, $4f7, $4f8, $4f9, $4fa, $4fb, $4fc, $4fd, $4fe, $4ff +dw $900, $901, $902, $903, $904, $905, $906, $907, $908, $909, $90a, $90b, $90c, $90d, $90e, $90f, $910, $911, $912, $913, $914, $915, $916, $917, $918, $919, $91a, $91b, $91c, $91d, $91e, $91f +dw $920, $921, $922, $923, $924, $925, $926, $927, $928, $929, $92a, $92b, $92c, $92d, $92e, $92f, $930, $931, $932, $933, $934, $935, $936, $937, $938, $939, $93a, $93b, $93c, $93d, $93e, $93f +dw $940, $941, $942, $943, $944, $945, $946, $947, $948, $949, $94a, $94b, $94c, $94d, $94e, $94f, $950, $951, $952, $953, $954, $955, $956, $957, $958, $959, $95a, $95b, $95c, $95d, $95e, $95f +dw $D60, $D61, $D62, $D63, $D64, $D65, $D66, $D67, $D68, $D69, $D6a, $D6b, $D6c, $D6d, $D6e, $D6f, $D70, $D71, $D72, $D73, $D74, $D75, $D76, $D77, $D78, $D79, $D7a, $D7b, $D7c, $D7d, $D7e, $D7f +dw $D80, $D81, $D82, $D83, $D84, $D85, $D86, $D87, $D88, $D89, $D8a, $D8b, $D8c, $D8d, $D8e, $D8f, $D90, $D91, $D92, $D93, $D94, $D95, $D96, $D97, $D98, $D99, $D9a, $D9b, $D9c, $D9d, $D9e, $D9f +dw $Da0, $Da1, $Da2, $Da3, $Da4, $Da5, $Da6, $Da7, $Da8, $Da9, $Daa, $Dab, $Dac, $Dad, $Dae, $Daf, $Db0, $Db1, $Db2, $Db3, $Db4, $Db5, $Db6, $Db7, $Db8, $Db9, $Dba, $Dbb, $Dbc, $Dbd, $Dbe, $Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/make.bat new file mode 100644 index 00000000..b1eed87a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/make.bat @@ -0,0 +1 @@ +bass 8x8BG4Map2BPP32x328PAL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.asm new file mode 100644 index 00000000..6d6522cc --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.asm @@ -0,0 +1,50 @@ +// SNES PPU BG 8x8 4BPP 32x32 8 Palette Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMap4BPP32x328PAL.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 128 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, 1792, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG2 16 Colour Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2107: BG2 32x32, BG2 Map Address = $3D (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX\BG.pal" // Include BG Palette Data (256 Bytes) +BGMap: + include "TileMap8PAL256x224.asm" // Include BG Map Data (1792 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data (28672 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.png new file mode 100644 index 00000000..653deb0a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.sfc new file mode 100644 index 00000000..3bc12cbf Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pal new file mode 100644 index 00000000..43dc0963 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pal @@ -0,0 +1 @@ +(i!=My]~RL~PJzrW(h)I=]}K~PBrjzVe( H5j!Q !-bWU 1 )/RobVJ[kv 1 %* *%rN^V6Y"R{)1,%q!3"R"3Fq"p69W2UD !)5J!PSB8*r&p^}4{WssCB$ ,!J5Q V!J6j=K \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pic new file mode 100644 index 00000000..cda4ab03 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGA.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGA.png new file mode 100644 index 00000000..8ea73442 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGB.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGB.png new file mode 100644 index 00000000..286f07be Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGB.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGC.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGC.png new file mode 100644 index 00000000..a8615409 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGC.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGD.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGD.png new file mode 100644 index 00000000..7c2fbdab Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGD.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGE.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGE.png new file mode 100644 index 00000000..e8a019a6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGE.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGF.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGF.png new file mode 100644 index 00000000..75ee548a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGF.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGG.png new file mode 100644 index 00000000..3752fb9e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGH.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGH.png new file mode 100644 index 00000000..d5e6d3f5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/GFX/BGH.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..03deb9d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 4BPP 8PAL " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/TileMap8PAL256x224.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/TileMap8PAL256x224.asm new file mode 100644 index 00000000..1d053a3b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/TileMap8PAL256x224.asm @@ -0,0 +1,28 @@ +dw $000, $001, $002, $003, $004, $005, $006, $007, $008, $009, $00a, $00b, $00c, $00d, $00e, $00f, $010, $011, $012, $013, $014, $015, $016, $017, $018, $019, $01a, $01b, $01c, $01d, $01e, $01f +dw $020, $021, $022, $023, $024, $025, $026, $027, $028, $029, $02a, $02b, $02c, $02d, $02e, $02f, $030, $031, $032, $033, $034, $035, $036, $037, $038, $039, $03a, $03b, $03c, $03d, $03e, $03f +dw $040, $041, $042, $043, $044, $045, $046, $047, $048, $049, $04a, $04b, $04c, $04d, $04e, $04f, $050, $051, $052, $053, $054, $055, $056, $057, $058, $059, $05a, $05b, $05c, $05d, $05e, $05f +dw $060, $061, $062, $063, $064, $065, $066, $067, $068, $069, $06a, $06b, $06c, $06d, $06e, $06f, $070, $071, $072, $073, $074, $075, $076, $077, $078, $079, $07a, $07b, $07c, $07d, $07e, $07f +dw $480, $481, $482, $483, $484, $485, $486, $487, $488, $489, $48a, $48b, $48c, $48d, $48e, $48f, $490, $491, $492, $493, $494, $495, $496, $497, $498, $499, $49a, $49b, $49c, $49d, $49e, $49f +dw $4a0, $4a1, $4a2, $4a3, $4a4, $4a5, $4a6, $4a7, $4a8, $4a9, $4aa, $4ab, $4ac, $4ad, $4ae, $4af, $4b0, $4b1, $4b2, $4b3, $4b4, $4b5, $4b6, $4b7, $4b8, $4b9, $4ba, $4bb, $4bc, $4bd, $4be, $4bf +dw $4c0, $4c1, $4c2, $4c3, $4c4, $4c5, $4c6, $4c7, $4c8, $4c9, $4ca, $4cb, $4cc, $4cd, $4ce, $4cf, $4d0, $4d1, $4d2, $4d3, $4d4, $4d5, $4d6, $4d7, $4d8, $4d9, $4da, $4db, $4dc, $4dd, $4de, $4df +dw $4e0, $4e1, $4e2, $4e3, $4e4, $4e5, $4e6, $4e7, $4e8, $4e9, $4ea, $4eb, $4ec, $4ed, $4ee, $4ef, $4f0, $4f1, $4f2, $4f3, $4f4, $4f5, $4f6, $4f7, $4f8, $4f9, $4fa, $4fb, $4fc, $4fd, $4fe, $4ff +dw $900, $901, $902, $903, $904, $905, $906, $907, $908, $909, $90a, $90b, $90c, $90d, $90e, $90f, $910, $911, $912, $913, $914, $915, $916, $917, $918, $919, $91a, $91b, $91c, $91d, $91e, $91f +dw $920, $921, $922, $923, $924, $925, $926, $927, $928, $929, $92a, $92b, $92c, $92d, $92e, $92f, $930, $931, $932, $933, $934, $935, $936, $937, $938, $939, $93a, $93b, $93c, $93d, $93e, $93f +dw $940, $941, $942, $943, $944, $945, $946, $947, $948, $949, $94a, $94b, $94c, $94d, $94e, $94f, $950, $951, $952, $953, $954, $955, $956, $957, $958, $959, $95a, $95b, $95c, $95d, $95e, $95f +dw $D60, $D61, $D62, $D63, $D64, $D65, $D66, $D67, $D68, $D69, $D6a, $D6b, $D6c, $D6d, $D6e, $D6f, $D70, $D71, $D72, $D73, $D74, $D75, $D76, $D77, $D78, $D79, $D7a, $D7b, $D7c, $D7d, $D7e, $D7f +dw $D80, $D81, $D82, $D83, $D84, $D85, $D86, $D87, $D88, $D89, $D8a, $D8b, $D8c, $D8d, $D8e, $D8f, $D90, $D91, $D92, $D93, $D94, $D95, $D96, $D97, $D98, $D99, $D9a, $D9b, $D9c, $D9d, $D9e, $D9f +dw $Da0, $Da1, $Da2, $Da3, $Da4, $Da5, $Da6, $Da7, $Da8, $Da9, $Daa, $Dab, $Dac, $Dad, $Dae, $Daf, $Db0, $Db1, $Db2, $Db3, $Db4, $Db5, $Db6, $Db7, $Db8, $Db9, $Dba, $Dbb, $Dbc, $Dbd, $Dbe, $Dbf +dw $11c0, $11c1, $11c2, $11c3, $11c4, $11c5, $11c6, $11c7, $11c8, $11c9, $11ca, $11cb, $11cc, $11cd, $11ce, $11cf, $11d0, $11d1, $11d2, $11d3, $11d4, $11d5, $11d6, $11d7, $11d8, $11d9, $11da, $11db, $11dc, $11dd, $11de, $11df +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $11e8, $11e9, $11ea, $11eb, $11ec, $11ed, $11ee, $11ef, $11f0, $11f1, $11f2, $11f3, $11f4, $11f5, $11f6, $11f7, $11f8, $11f9, $11fa, $11fb, $11fc, $11fd, $11fe, $11ff +dw $1200, $1201, $1202, $1203, $1204, $1205, $1206, $1207, $1208, $1209, $120a, $120b, $120c, $120d, $120e, $120f, $1210, $1211, $1212, $1213, $1214, $1215, $1216, $1217, $1218, $1219, $121a, $121b, $121c, $121d, $121e, $121f +dw $1620, $1621, $1622, $1623, $1624, $1625, $1626, $1627, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1630, $1631, $1632, $1633, $1634, $1635, $1636, $1637, $1638, $1639, $163a, $163b, $163c, $163d, $163e, $163f +dw $1640, $1641, $1642, $1643, $1644, $1645, $1646, $1647, $1648, $1649, $164a, $164b, $164c, $164d, $164e, $164f, $1650, $1651, $1652, $1653, $1654, $1655, $1656, $1657, $1658, $1659, $165a, $165b, $165c, $165d, $165e, $165f +dw $1660, $1661, $1662, $1663, $1664, $1665, $1666, $1667, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1670, $1671, $1672, $1673, $1674, $1675, $1676, $1677, $1678, $1679, $167a, $167b, $167c, $167d, $167e, $167f +dw $1a80, $1a81, $1a82, $1a83, $1a84, $1a85, $1a86, $1a87, $1a88, $1a89, $1a8a, $1a8b, $1a8c, $1a8d, $1a8e, $1a8f, $1a90, $1a91, $1a92, $1a93, $1a94, $1a95, $1a96, $1a97, $1a98, $1a99, $1a9a, $1a9b, $1a9c, $1a9d, $1a9e, $1a9f +dw $1aa0, $1aa1, $1aa2, $1aa3, $1aa4, $1aa5, $1aa6, $1aa7, $1aa8, $1aa9, $1aaa, $1aab, $1aac, $1aad, $1aae, $1aaf, $1ab0, $1ab1, $1ab2, $1ab3, $1ab4, $1ab5, $1ab6, $1ab7, $1ab8, $1ab9, $1aba, $1abb, $1abc, $1abd, $1abe, $1abf +dw $1ac0, $1ac1, $1ac2, $1ac3, $1ac4, $1ac5, $1ac6, $1ac7, $1ac8, $1ac9, $1aca, $1acb, $1acc, $1acd, $1ace, $1acf, $1ad0, $1ad1, $1ad2, $1ad3, $1ad4, $1ad5, $1ad6, $1ad7, $1ad8, $1ad9, $1ada, $1adb, $1adc, $1add, $1ade, $1adf +dw $1ae0, $1ae1, $1ae2, $1ae3, $1ae4, $1ae5, $1ae6, $1ae7, $1ae8, $1ae9, $1aea, $1aeb, $1aec, $1aed, $1aee, $1aef, $1af0, $1af1, $1af2, $1af3, $1af4, $1af5, $1af6, $1af7, $1af8, $1af9, $1afa, $1afb, $1afc, $1afd, $1afe, $1aff +dw $1f00, $1f01, $1f02, $1f03, $1f04, $1f05, $1f06, $1f07, $1f08, $1f09, $1f0a, $1f0b, $1f0c, $1f0d, $1f0e, $1f0f, $1f10, $1f11, $1f12, $1f13, $1f14, $1f15, $1f16, $1f17, $1f18, $1f19, $1f1a, $1f1b, $1f1c, $1f1d, $1f1e, $1f1f +dw $1f20, $1f21, $1f22, $1f23, $1f24, $1f25, $1f26, $1f27, $1f28, $1f29, $1f2a, $1f2b, $1f2c, $1f2d, $1f2e, $1f2f, $1f30, $1f31, $1f32, $1f33, $1f34, $1f35, $1f36, $1f37, $1f38, $1f39, $1f3a, $1f3b, $1f3c, $1f3d, $1f3e, $1f3f +dw $1f40, $1f41, $1f42, $1f43, $1f44, $1f45, $1f46, $1f47, $1f48, $1f49, $1f4a, $1f4b, $1f4c, $1f4d, $1f4e, $1f4f, $1f50, $1f51, $1f52, $1f53, $1f54, $1f55, $1f56, $1f57, $1f58, $1f59, $1f5a, $1f5b, $1f5c, $1f5d, $1f5e, $1f5f +dw $1f60, $1f61, $1f62, $1f63, $1f64, $1f65, $1f66, $1f67, $1f68, $1f69, $1f6a, $1f6b, $1f6c, $1f6d, $1f6e, $1f6f, $1f70, $1f71, $1f72, $1f73, $1f74, $1f75, $1f76, $1f77, $1f78, $1f79, $1f7a, $1f7b, $1f7c, $1f7d, $1f7e, $1f7f \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/make.bat new file mode 100644 index 00000000..a55f0dbc --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/make.bat @@ -0,0 +1 @@ +bass 8x8BGMap4BPP32x328PAL.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.asm new file mode 100644 index 00000000..6ef6af14 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.asm @@ -0,0 +1,58 @@ +// SNES PPU BG 8x8 8BPP 32x32 Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMap8BPP32x32.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $2000, BGTiles.size, 0) // Load VRAM SRCDATA, DEST, SIZE, CHAN + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000000 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000001 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $2000 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +lda.b #0 // A = X/Y Scroll +Loop: + WaitNMI() // Wait VBlank + sta.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + sta.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + inc // A++ + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (2048 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.sfc new file mode 100644 index 00000000..a926cf76 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/8x8BGMap8BPP32x32.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.map new file mode 100644 index 00000000..16585e41 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pic new file mode 100644 index 00000000..de25dde6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.png new file mode 100644 index 00000000..3c23b057 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..87737bc8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 8BPP 32X32" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/make.bat new file mode 100644 index 00000000..0ff74dfd --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x32/make.bat @@ -0,0 +1 @@ +bass 8x8BGMap8BPP32x32.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.asm new file mode 100644 index 00000000..7cef26b3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.asm @@ -0,0 +1,74 @@ +// SNES PPU BG 8x8 8BPP 32x64 Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMap8BPP32x64.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $2000, BGTiles.size, 0) // Load VRAM SRCDATA, DEST, SIZE, CHAN + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x64, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000001 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $2000 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + cpy.w #$0000 // Check If At Top Of Screen + beq Down // Skip BG Scrolling If Top + ReadJOY({JOY_UP}) // Test UP Button + beq Down // "UP" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Y Pos + + Down: + cpy.w #$00FF // Check If At Bottom Of Screen + beq Finish // Skip BG Scrolling If Bottom + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Finish // "DOWN" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Y Pos + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (4096 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.sfc new file mode 100644 index 00000000..bfdb47fc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/8x8BGMap8BPP32x64.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.map new file mode 100644 index 00000000..841e128f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pic new file mode 100644 index 00000000..52dd8c5b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.png new file mode 100644 index 00000000..3729c749 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..f2eff449 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 8BPP 32X64" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/make.bat new file mode 100644 index 00000000..a6c4af07 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/32x64/make.bat @@ -0,0 +1 @@ +bass 8x8BGMap8BPP32x64.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.asm new file mode 100644 index 00000000..60d94183 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.asm @@ -0,0 +1,89 @@ +// SNES PPU BG 8x8 8BPP 64x32 Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMap8BPP64x32.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $2000, BGTiles.size, 0) // Load VRAM SRCDATA, DEST, SIZE, CHAN + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000001 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000001 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $2000 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +ldx.w #$0000 // Reset BG X Position +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + cpy.w #$0000 // Check If At Top Of Screen + beq Down // Skip BG Scrolling If Top + ReadJOY({JOY_UP}) // Test UP Button + beq Down // "UP" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Y Pos + + Down: + cpy.w #$001F // Check If At Bottom Of Screen + beq Left // Skip BG Scrolling If Bottom + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // "DOWN" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Y Pos + + Left: + cpx.w #$0000 // Check If At Left Of Screen + beq Right // Skip BG Scrolling If Left + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // "LEFT" Not Pressed? Branch Down + BGScroll8I(x, REG_BG1HOFS, de) // Decrement BG1 X Pos + + Right: + cpx.w #$00FF // Check If At Right Of Screen + beq Finish // Skip BG Scrolling If Right + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // "RIGHT" Not Pressed? Branch Down + BGScroll8I(x, REG_BG1HOFS, in) // Increment BG1 X Pos + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (4096 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.sfc new file mode 100644 index 00000000..de52e523 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/8x8BGMap8BPP64x32.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.map new file mode 100644 index 00000000..e2c00d6c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pic new file mode 100644 index 00000000..a9464194 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.png new file mode 100644 index 00000000..1b0e6604 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4040d26f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 8BPP 64X32" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/make.bat new file mode 100644 index 00000000..1f7bf7dc --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x32/make.bat @@ -0,0 +1 @@ +bass 8x8BGMap8BPP64x32.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.asm new file mode 100644 index 00000000..1135b044 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.asm @@ -0,0 +1,89 @@ +// SNES PPU BG 8x8 8BPP 64x64 Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMap8BPP64x64.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $2000, BGTiles.size, 0) // Load VRAM SRCDATA, DEST, SIZE, CHAN + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x64, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000001 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $2000 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +ldx.w #$0000 // Reset BG X Position +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + cpy.w #$0000 // Check If At Top Of Screen + beq Down // Skip BG Scrolling If Top + ReadJOY({JOY_UP}) // Test UP Button + beq Down // "UP" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Y Pos + + Down: + cpy.w #$00FF // Check If At Bottom Of Screen + beq Left // Skip BG Scrolling If Bottom + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // "DOWN" Not Pressed? Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Y Pos + + Left: + cpx.w #$0000 // Check If At Left Of Screen + beq Right // Skip BG Scrolling If Left + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // "LEFT" Not Pressed? Branch Down + BGScroll8I(x, REG_BG1HOFS, de) // Decrement BG1 X Pos + + Right: + cpx.w #$00FF // Check If At Right Of Screen + beq Finish // Skip BG Scrolling If Right + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // "RIGHT" Not Pressed? Branch Down + BGScroll8I(x, REG_BG1HOFS, in) // Increment BG1 X Pos + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (8192 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.sfc new file mode 100644 index 00000000..a7fe9b3e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/8x8BGMap8BPP64x64.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.map new file mode 100644 index 00000000..1c7c27c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pic new file mode 100644 index 00000000..2e15fe45 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.png new file mode 100644 index 00000000..1c9e7187 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..56b32217 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 8BPP 64X64" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/make.bat new file mode 100644 index 00000000..e2efc86a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/64x64/make.bat @@ -0,0 +1 @@ +bass 8x8BGMap8BPP64x64.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.asm b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.asm new file mode 100644 index 00000000..cd2b6f8c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.asm @@ -0,0 +1,49 @@ +// SNES PPU BG 8x8 Tile Flip Demo by krom (Peter Lemon): +arch snes.cpu +output "8x8BGMapTileFlip.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, BGMap.size, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (2048 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (128 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.png new file mode 100644 index 00000000..abc660c8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.sfc b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.sfc new file mode 100644 index 00000000..10486aea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.map new file mode 100644 index 00000000..03b29ee5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pal new file mode 100644 index 00000000..86346443 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pic new file mode 100644 index 00000000..445bb383 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.png new file mode 100644 index 00000000..c47c6bd4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9425e558 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU BG 8X8 TILE FLIP " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/make.bat b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/make.bat new file mode 100644 index 00000000..77863969 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/make.bat @@ -0,0 +1 @@ +bass 8x8BGMapTileFlip.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.map new file mode 100644 index 00000000..13c6bcf2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.pic new file mode 100644 index 00000000..6df5a8b5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.png new file mode 100644 index 00000000..88eef80b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/B16.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/BGR256.pal b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/BGR256.pal new file mode 100644 index 00000000..104fb764 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/BGR256.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.map new file mode 100644 index 00000000..6258d711 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.pic new file mode 100644 index 00000000..d544e86c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.png new file mode 100644 index 00000000..9d7a717c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/GFX/GR240.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.asm b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.asm new file mode 100644 index 00000000..0de18310 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.asm @@ -0,0 +1,74 @@ +// SNES Blend Hi Color (1241 On Screen) Dragon's Lair Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor1241DLair.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPalBGR, $00, BGPalBGR.size, 0) // Load 2 BG Palettes (BG Palettes Use 240 & 16 Colors) + LoadVRAM(BGTiles240, $0000, $8000, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles240+$10000, $8000, $5F40, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles16, $E000, BGTiles16.size, 0) // Load BG2 16 Tiles To VRAM + LoadVRAM(BGMap240, $F000, BGMap240.size, 0) // Load BG1 256 Tile Map To VRAM + LoadVRAM(BGMap16, $F800, BGMap16.size, 0) // Load BG2 16 Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 & BG2 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111000 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $F000 (VRAM Address / $400) + lda.b #%11110000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000, BG2 Tile Address = $E000 (VRAM Address / $1000) + + // Setup BG2 16 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2107: BG2 32x32, BG2 Map Address = $F800 (VRAM Address / $400) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + lda.b #%00000010 // Enable BG2 + sta.w REG_TS // $212D: BG2 To Sub Screen Designation + + lda.b #$02 + sta.w REG_CGWSEL // $2130: Enable Subscreen Color ADD/SUB + + lda.b #%00100001 + sta.w REG_CGADSUB // $2131: Colour Addition On BG1 And Backdrop Colour + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Lo Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPalBGR, "GFX/BGR256.pal" // Include 2 BG Palette Data (512 Bytes) +insert BGMap240, "GFX/GR240.map" // Include BG Map Data (1792 Bytes) +insert BGMap16, "GFX/B16.map" // Include BG Map Data (1792 Bytes) +insert BGTiles16, "GFX/B16.pic" // Include BG Tile Data (512 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles240, "GFX/GR240.pic" // Include BG Tile Data (57152 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.png new file mode 100644 index 00000000..096411b4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.sfc b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.sfc new file mode 100644 index 00000000..a227edf6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..bee510e6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HI COLOR BLEND DLAIR " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/make.bat b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/make.bat new file mode 100644 index 00000000..0e9b648a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/make.bat @@ -0,0 +1 @@ +bass HiColor1241DLair.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.map new file mode 100644 index 00000000..ebbafe1c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.pic new file mode 100644 index 00000000..6a1107a9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.png new file mode 100644 index 00000000..efb534f3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColGB240.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.map new file mode 100644 index 00000000..e5628504 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.pic new file mode 100644 index 00000000..f19f8d14 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.png new file mode 100644 index 00000000..e400061f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColR16.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColRGB.pal b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColRGB.pal new file mode 100644 index 00000000..8a212feb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/GFX/MaxColRGB.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.asm b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.asm new file mode 100644 index 00000000..68ef1b08 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.asm @@ -0,0 +1,73 @@ +// SNES Blend Hi Color (3840 On Screen) Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor3840.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPalBRG, $00, BGPalBRG.size, 0) // Load 2 BG Palettes (BG Palettes Use 240 & 16 Colors) + LoadVRAM(BGTiles240, $0000, $8000, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles240+$10000, $8000, $30C0, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles16, $C000, BGTiles16.size, 0) // Load BG2 16 Tiles To VRAM + LoadVRAM(BGMap240, $F000, BGMap240.size + BGMap16.size, 0) // Load 2 Background Tile Maps To VRAM (2 * $800 bytes) + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 & BG2 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111000 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $F000 (VRAM Address / $400) + lda.b #%11100000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000, BG2 Tile Address = $E000 (VRAM Address / $1000) + + // Setup BG2 16 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2107: BG2 32x32, BG2 Map Address = $F800 (VRAM Address / $400) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + lda.b #%00000010 // Enable BG2 + sta.w REG_TS // $212D: BG2 To Sub Screen Designation + + lda.b #$02 + sta.w REG_CGWSEL // $2130: Enable Subscreen Color ADD/SUB + + lda.b #%00100001 + sta.w REG_CGADSUB // $2131: Colour Addition On BG1 And Backdrop Colour + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Lo Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPalBRG, "GFX/MaxColRGB.pal" // Include 2 BG Palette Data (512 Bytes) +insert BGMap240, "GFX/MaxColGB240.map" // Include BG Map Data (2048 Bytes) +insert BGMap16, "GFX/MaxColR16.map" // Include BG Map Data (2048 Bytes) +insert BGTiles16, "GFX/MaxColR16.pic" // Include BG Tile Data (96 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles240, "GFX/MaxColGB240.pic" // Include BG Tile Data (28736 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.png new file mode 100644 index 00000000..7108ffe0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.sfc b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.sfc new file mode 100644 index 00000000..455ec9f8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..5bf9c91b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HI COLOR BLEND DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/make.bat b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/make.bat new file mode 100644 index 00000000..f1a826bb --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/make.bat @@ -0,0 +1 @@ +bass HiColor3840.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.map new file mode 100644 index 00000000..7410d1d2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.pic new file mode 100644 index 00000000..26be6b73 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.png new file mode 100644 index 00000000..0d905a9a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/B16.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/BGR256.pal b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/BGR256.pal new file mode 100644 index 00000000..3f274057 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/BGR256.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.map b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.map new file mode 100644 index 00000000..576af937 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.pic b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.pic new file mode 100644 index 00000000..3f7104c4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.png new file mode 100644 index 00000000..e45a1d73 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/GFX/GR241.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.asm b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.asm new file mode 100644 index 00000000..53e4277a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.asm @@ -0,0 +1,76 @@ +// SNES Blend Hi Color (575 On Screen) Myst Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor575Myst.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPalBGR, $00, BGPalBGR.size, 0) // Load 2 BG Palettes (BG Palettes Use 240 & 16 Colors) + LoadVRAM(BGTiles241, $0000, $8000, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles241+$10000, $8000, $2000, 0) // Load BG1 256 Tiles To VRAM + LoadVRAM(BGTiles16, $C000, BGTiles16.size, 0) // Load BG2 16 Tiles To VRAM + LoadVRAM(BGMap241, $B900, BGMap241.size, 0) // Load BG1 256 Tile Map To VRAM + LoadVRAM(BGMap16, $F900, BGMap16.size, 0) // Load BG2 16 Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 & BG2 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%01011100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $B900 (VRAM Address / $400) + + // Setup BG2 16 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2107: BG2 32x32, BG2 Map Address = $F900 (VRAM Address / $400) + + lda.b #%01100000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000, BG2 Tile Address = $C000 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + lda.b #%00000010 // Enable BG2 + sta.w REG_TS // $212D: BG2 To Sub Screen Designation + + lda.b #$02 + sta.w REG_CGWSEL // $2130: Enable Subscreen Color ADD/SUB + + lda.b #%00100001 + sta.w REG_CGADSUB // $2131: Colour Addition On BG1 And Backdrop Colour + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Lo Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Position Hi Byte + + lda.b #31 // Scroll BG1 & BG2 31 Pixels Up + sta.w REG_BG1VOFS // Store A To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + sta.w REG_BG2VOFS // Store A To BG2 Vertical Scroll Position Lo Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPalBGR, "GFX/BGR256.pal" // Include 2 BG Palette Data (512 Bytes) +insert BGMap241, "GFX/GR241.map" // Include BG Map Data (1792 Bytes) +insert BGMap16, "GFX/B16.map" // Include BG Map Data (1792 Bytes) +insert BGTiles16, "GFX/B16.pic" // Include BG Tile Data (14560 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles241, "GFX/GR241.pic" // Include BG Tile Data (40960 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.png b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.png new file mode 100644 index 00000000..c38b7c75 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.sfc b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.sfc new file mode 100644 index 00000000..7a87371f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..36661b9b --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HI COLOR BLEND MYST " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/make.bat b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/make.bat new file mode 100644 index 00000000..a4c64dcb --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/make.bat @@ -0,0 +1 @@ +bass HiColor575Myst.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.asm b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.asm new file mode 100644 index 00000000..78b1bf00 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.asm @@ -0,0 +1,30 @@ +// SNES Green Space Demo by krom (Peter Lemon): +arch snes.cpu +output "GreenSpace.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Load Green Background Palette Color + stz.w REG_CGADD // $2121: CGRAM Address + lda.b #%11100000 // Load Green Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%00000011 // Load Green Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + stz.w REG_TM // $212C: Main Screen Designation + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + +Loop: + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.png b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.png new file mode 100644 index 00000000..f9f664bc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.sfc b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.sfc new file mode 100644 index 00000000..2fcbf0c5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..92e91284 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/GreenSpace/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "GREEN SPACE DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/GreenSpace/make.bat b/roms/snes/peter-lemon-snes/PPU/GreenSpace/make.bat new file mode 100644 index 00000000..b6096df7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/GreenSpace/make.bat @@ -0,0 +1 @@ +bass GreenSpace.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pal b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pal new file mode 100644 index 00000000..8de8b64a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pic new file mode 100644 index 00000000..dc08052c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.png new file mode 100644 index 00000000..91fd9fdb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/BGOBJ.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/SNESBGOBJPAL128tilerow.py b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/SNESBGOBJPAL128tilerow.py new file mode 100644 index 00000000..83bf0454 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/GFX/SNESBGOBJPAL128tilerow.py @@ -0,0 +1,156 @@ +# Syntax: SNESBGOBJPAL128tilerow.py image.in file.out +# Notes: image.in needs to be 256x224 pixel resolution image +# Written for Python 3.6.2 with the Pillow 4.2.1 library +import sys +import struct +import PIL.Image + +# Quantize Options: +colors = 15 # The desired number of colors, <= 256 +method = 0 # 0 = median cut 1 = maximum coverage 2 = fast octree 3 = libimagequant +kmeans = 3 # Integer + +def convert_pal(image, filedata): # Convert To SNES 16 Color Palette Data + palette = image.getpalette()[:(15*3)] # Get 15 * R,G,B Palette Entries + filedata.write(struct.pack('H', 0)) # Store Black To Palette Color Index 0 + for i in range(15): + R = palette[i*3] + G = palette[(i*3)+1] + B = palette[(i*3)+2] + SNEScol = ((B & 0xF8) << 7) | ((G & 0xF8) << 2) | ((R & 0xF8) >> 3) + filedata.write(struct.pack('H', SNEScol)) + +def convert_tile(image, tilenum, filedata): # Convert To SNES 8x8 4BPP Tile Data + pixels = image.getdata() + + tile = [] + i = tilenum * 8 + for y in range(8): + for x in range(8): + tile.append(pixels[i] + 1) + i += 1 + i += 24 # Tile Row Segment Stride + + SNEStile = [0] * 32 # Set SNES Tile Array (32 Bytes) + for y in range(8): # Rows + byte1 = byte2 = byte3 = byte4 = 0 + for x in range(8): # Columns + byte1 += (tile[(y<<3)+x] & 1)<<(7-x) + byte2 += ((tile[(y<<3)+x]>>1) & 1)<<(7-x) + byte3 += ((tile[(y<<3)+x]>>2) & 1)<<(7-x) + byte4 += ((tile[(y<<3)+x]>>3) & 1)<<(7-x) + SNEStile[(y*2)] = byte1 + SNEStile[(y*2)+1] = byte2 + SNEStile[(y*2)+16] = byte3 + SNEStile[(y*2)+17] = byte4 + + for i in range(32): filedata.write(struct.pack('B', SNEStile[i])) # Write 4BPP 8x8 Tile (32 Bytes) + +def convert_segment(image, height, filedata): + for i in range(int(height/8)): # Convert Tile Data From 128 Pixel Wide Picture Segment + tilerowsegment = image.crop((0, i*8, 32, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_tile(tilerowsegment, 0, filedata) + convert_tile(tilerowsegment, 1, filedata) + convert_tile(tilerowsegment, 2, filedata) + convert_tile(tilerowsegment, 3, filedata) + + tilerowsegment = image.crop((32, i*8, 64, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_tile(tilerowsegment, 0, filedata) + convert_tile(tilerowsegment, 1, filedata) + convert_tile(tilerowsegment, 2, filedata) + convert_tile(tilerowsegment, 3, filedata) + + tilerowsegment = image.crop((64, i*8, 96, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_tile(tilerowsegment, 0, filedata) + convert_tile(tilerowsegment, 1, filedata) + convert_tile(tilerowsegment, 2, filedata) + convert_tile(tilerowsegment, 3, filedata) + + tilerowsegment = image.crop((96, i*8, 128, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_tile(tilerowsegment, 0, filedata) + convert_tile(tilerowsegment, 1, filedata) + convert_tile(tilerowsegment, 2, filedata) + convert_tile(tilerowsegment, 3, filedata) + +def main(argv=None): + if argv is None: + argv = sys.argv[1:] + infilename, outfilename = argv + outpal = open(outfilename+'.pal', 'wb') + outtile = open(outfilename+'.pic', 'wb') + in_img = PIL.Image.open(infilename) + width, height = in_img.size + + # PASS 1: Convert Tile Row Palettes From Full Picture + for i in range(int(height/8)): + tilerowsegment = in_img.crop((0, i*8, 32, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((32, i*8, 64, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((64, i*8, 96, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((96, i*8, 128, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((128, i*8, 160, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((160, i*8, 192, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((192, i*8, 224, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + tilerowsegment = in_img.crop((224, i*8, 256, (i*8)+8)) + tilerowsegment = tilerowsegment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(tilerowsegment, outpal) + + # PASS 2: Convert Tile Data From Cropped Picture Segments + segment = in_img.crop((0, 0, 128, 64)) # Convert Tile Data From 128x64 Picture Segment (Top Left) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((128, 0, 256, 64)) # Convert Tile Data From 128x64 Picture Segment (Top Right) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((0, 64, 128, 128)) # Convert Tile Data From 128x64 Picture Segment (Upper Middle Left) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((128, 64, 256, 128)) # Convert Tile Data From 128x64 Picture Segment (Upper Middle Right) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((0, 128, 128, 192)) # Convert Tile Data From 128x64 Picture Segment (Lower Middle Left) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((128, 128, 256, 192)) # Convert Tile Data From 128x64 Picture Segment (Lower Middle Right) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((0, 192, 128, 224)) # Convert Tile Data From 128x32 Picture Segment (Bottom Left) + width, height = segment.size + convert_segment(segment, height, outtile) + + segment = in_img.crop((128, 192, 256, 224)) # Convert Tile Data From 128x32 Picture Segment (Bottom Right) + width, height = segment.size + convert_segment(segment, height, outtile) + +if __name__ == '__main__': + main() diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.asm new file mode 100644 index 00000000..e3d09ff4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.asm @@ -0,0 +1,227 @@ +// SNES Hi Color (128 Per Tile Row) Using 4BPP BG & Sprites Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor128PerTileRow.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #%00010010 // Enable BG2 & Sprites + sta.w REG_TM // $212C: BG2 & Sprites To Main Screen Designation + + LoadVRAM(BGOBJTiles, $0000, BGOBJTiles.size, 0) // Load Background/Object Tile Data To VRAM + LoadVRAM(BGMap, $7900, 1792, 0) // Load Background Tile Map To VRAM + + // Clear OAM + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Copy OAM Info + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + - + lda.w OAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$00A0 + bne - + + // Copy OAM Extra Info + ldy.w #$0100 // Y = $0100 + sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + - + lda.w OAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$00AA + bne - + + // DMA Palette Data On Interrupt (DMA Channel 0) + lda.b #%00000000 // DMA: Write 1 Byte, Increment Source + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGDATA // $22: Start At Palette CGRAM Address ($2122) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + lda.b #BGOBJPal >> 16 // DMA Source Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + // HDMA OAM Size & Object Base (HDMA Channel 1) + lda.b #%00000000 // HDMA: Write 1 Bytes Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #OAMHDMATable // HDMA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #OAMHDMATable >> 16 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + + lda.b #%00000010 // HDMA Channel Select (Channel 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + lda.b #$0F + sta.w REG_INIDISP // $80: Turn On Screen, Full Brightness ($2100) + + // IRQ + lda.b #170 // Value Depends On How Long Horizontal IRQ Takes To Start DMA + sta.w REG_HTIMEL // $4207: H-Count Timer Setting (Lower 8-Bit) + lda.b #%10010000 // NMI & Horizontal IRQ + sta.w REG_NMITIMEN // $4200: Interrupt Enable & Joypad Request (Enable NMI) + + WaitNMI() // Wait For Vertical Blank + cli // Enable Interrupts + +loop: + wai + jmp loop + +VBLANKIRQ: + stz.w REG_CGADD // $2121: Palette CGRAM Address = 0 + ldx.w #BGOBJPal // DMA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + ldx.w #256 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + rti + +HTIMERIRQ: + lda.w REG_TIMEUP // $4211: H/V-Timer IRQ Flag (Read/Ack) (Clear IRQ Line) + + lda.w REG_SLHV // $2137: PPU1 Latch H/V-Counter By Software (Read=Strobe) + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Lo Byte) + xba // Exchange B & A Accumulators + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Hi Byte) + and.b #$01 // A &= 1 (Bit 9 Of Vertical Counter) + xba // Exchange B & A Accumulators (A = Scanline Lo Byte) + tax // Transfer A To X Index (X = Scanline Count) + + cpx.w #216 // Compare Scanline Count To 216 + bpl SkipDMA // IF (Scanline Count < 216) Skip DMA + + ldx.w #32 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + + SkipDMA: + rti + +OAMHDMATable: + db 128, %11000000 // Repeat 128 Scanlines, Object Size = 16x32/32x64, Name = 0, Base = $0000 + db 1, %11000001 // Repeat 1 Scanlines, Object Size = 16x32/32x64, Name = 0, Base = $4000 + db 0 // End Of HDMA + +OAM: + // OAM Info (32x64 Sprites) + db 0, 0, 0, %00000000 // ROW 1..7 + db 32, 0, 4, %00000010 + db 64, 0, 8, %00000100 + db 96, 0, 12, %00000110 + db 128, 0, 128, %00001000 + db 160, 0, 132, %00001010 + db 192, 0, 136, %00001100 + db 224, 0, 140, %00001110 + + db 0, 64, 0, %00000001 // ROW 9..15 + db 32, 64, 4, %00000011 + db 64, 64, 8, %00000101 + db 96, 64, 12, %00000111 + db 128, 64, 128, %00001001 + db 160, 64, 132, %00001011 + db 192, 64, 136, %00001101 + db 224, 64, 140, %00001111 + + db 0, 128, 0, %00000000 // ROW 17..23 + db 32, 128, 4, %00000010 + db 64, 128, 8, %00000100 + db 96, 128, 12, %00000110 + db 128, 128, 128, %00001000 + db 160, 128, 132, %00001010 + db 192, 128, 136, %00001100 + db 224, 128, 140, %00001110 + + // OAM Info (16x32 Sprites) + db 0, 192, 0, %00000001 // ROW 25..27 + db 16, 192, 2, %00000001 + db 32, 192, 4, %00000011 + db 48, 192, 6, %00000011 + db 64, 192, 8, %00000101 + db 80, 192, 10, %00000101 + db 96, 192, 12, %00000111 + db 112, 192, 14, %00000111 + + db 128, 192, 64, %00001001 + db 144, 192, 66, %00001001 + db 160, 192, 68, %00001011 + db 176, 192, 70, %00001011 + db 192, 192, 72, %00001101 + db 208, 192, 74, %00001101 + db 224, 192, 76, %00001111 + db 240, 192, 78, %00001111 + + // OAM Extra Info (32x64 Sprites) + db %10101010 // ROW 1..7 + db %10101010 + + db %10101010 // ROW 9..15 + db %10101010 + + db %10101010 // ROW 17..23 + db %10101010 + + // OAM Extra Info (16x32 Sprites) + db %00000000 // ROW 25..27 + db %00000000 + + db %00000000 + db %00000000 + +BGMap: + include "TileMap8PAL128ColPerTileRow256x224.asm" // Include BG Map Data (1792 Bytes) + +// Character Data +// BANK 0 +insert BGOBJPal, "GFX/BGOBJ.pal" // Include BG Tile Row 0..27 Palette Data (7168 Bytes) +// BANK 1 +seek($18000) +insert BGOBJTiles, "GFX/BGOBJ.pic" // Include BG Tile Data (28672 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.png new file mode 100644 index 00000000..8c963281 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.sfc new file mode 100644 index 00000000..a590c512 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..464325f8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HICOL128 PER TILE ROW" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw VBLANKIRQ // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw HTIMERIRQ // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ.png new file mode 100644 index 00000000..3d53b50c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.png new file mode 100644 index 00000000..2d55e2a9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.sfc new file mode 100644 index 00000000..9485da8d Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png new file mode 100644 index 00000000..91fd9fdb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.png new file mode 100644 index 00000000..8c963281 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.sfc new file mode 100644 index 00000000..a590c512 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna.png new file mode 100644 index 00000000..9358d9f8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.png new file mode 100644 index 00000000..759ddf45 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.sfc new file mode 100644 index 00000000..df496190 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill.png new file mode 100644 index 00000000..4e751954 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.png new file mode 100644 index 00000000..b6ba491f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.sfc new file mode 100644 index 00000000..75f694b3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TileMap8PAL128ColPerTileRow256x224.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TileMap8PAL128ColPerTileRow256x224.asm new file mode 100644 index 00000000..ac8a4fd5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TileMap8PAL128ColPerTileRow256x224.asm @@ -0,0 +1,28 @@ +dw $2000, $2001, $2002, $2003, $2404, $2405, $2406, $2407, $2808, $2809, $280A, $280B, $2C0C, $2C0D, $2C0E, $2C0F, $3080, $3081, $3082, $3083, $3484, $3485, $3486, $3487, $3888, $3889, $388A, $388B, $3C8C, $3C8D, $3C8E, $3C8F // ROW 0: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW 1: OBJ +dw $2020, $2021, $2022, $2023, $2424, $2425, $2426, $2427, $2828, $2829, $282A, $282B, $2C2C, $2C2D, $2C2E, $2C2F, $30A0, $30A1, $30A2, $30A3, $34A4, $34A5, $34A6, $34A7, $38A8, $38A9, $38AA, $38AB, $3CAC, $3CAD, $3CAE, $3CAF // ROW 2: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW 3: OBJ +dw $2040, $2041, $2042, $2043, $2444, $2445, $2446, $2447, $2848, $2849, $284A, $284B, $2C4C, $2C4D, $2C4E, $2C4F, $30C0, $30C1, $30C2, $30C3, $34C4, $34C5, $34C6, $34C7, $38C8, $38C9, $38CA, $38CB, $3CCC, $3CCD, $3CCE, $3CCF // ROW 4: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW 5: OBJ +dw $2060, $2061, $2062, $2063, $2464, $2465, $2466, $2467, $2868, $2869, $286A, $286B, $2C6C, $2C6D, $2C6E, $2C6F, $30E0, $30E1, $30E2, $30E3, $34E4, $34E5, $34E6, $34E7, $38E8, $38E9, $38EA, $38EB, $3CEC, $3CED, $3CEE, $3CEF // ROW 6: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW 7: OBJ +dw $2100, $2101, $2102, $2103, $2504, $2505, $2506, $2507, $2908, $2909, $290A, $290B, $2D0C, $2D0D, $2D0E, $2D0F, $3180, $3181, $3182, $3183, $3584, $3585, $3586, $3587, $3988, $3989, $398A, $398B, $3D8C, $3D8D, $3D8E, $3D8F // ROW 8: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW 9: OBJ +dw $2120, $2121, $2122, $2123, $2524, $2525, $2526, $2527, $2928, $2929, $292A, $292B, $2D2C, $2D2D, $2D2E, $2D2F, $31A0, $31A1, $31A2, $31A3, $35A4, $35A5, $35A6, $35A7, $39A8, $39A9, $39AA, $39AB, $3DAC, $3DAD, $3DAE, $3DAF // ROW10: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW11: OBJ +dw $2140, $2141, $2142, $2143, $2544, $2545, $2546, $2547, $2948, $2949, $294A, $294B, $2D4C, $2D4D, $2D4E, $2D4F, $31C0, $31C1, $31C2, $31C3, $35C4, $35C5, $35C6, $35C7, $39C8, $39C9, $39CA, $39CB, $3DCC, $3DCD, $3DCE, $3DCF // ROW12: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW13: OBJ +dw $2160, $2161, $2162, $2163, $2564, $2565, $2566, $2567, $2968, $2969, $296A, $296B, $2D6C, $2D6D, $2D6E, $2D6F, $31E0, $31E1, $31E2, $31E3, $35E4, $35E5, $35E6, $35E7, $39E8, $39E9, $39EA, $39EB, $3DEC, $3DED, $3DEE, $3DEF // ROW14: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW15: OBJ +dw $2200, $2201, $2202, $2203, $2604, $2605, $2606, $2607, $2A08, $2A09, $2A0A, $2A0B, $2E0C, $2E0D, $2E0E, $2E0F, $3280, $3281, $3282, $3283, $3684, $3685, $3686, $3687, $3A88, $3A89, $3A8A, $3A8B, $3E8C, $3E8D, $3E8E, $3E8F // ROW16: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW17: OBJ +dw $2220, $2221, $2222, $2223, $2624, $2625, $2626, $2627, $2A28, $2A29, $2A2A, $2A2B, $2E2C, $2E2D, $2E2E, $2E2F, $32A0, $32A1, $32A2, $32A3, $36A4, $36A5, $36A6, $36A7, $3AA8, $3AA9, $3AAA, $3AAB, $3EAC, $3EAD, $3EAE, $3EAF // ROW18: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW19: OBJ +dw $2240, $2241, $2242, $2243, $2644, $2645, $2646, $2647, $2A48, $2A49, $2A4A, $2A4B, $2E4C, $2E4D, $2E4E, $2E4F, $32C0, $32C1, $32C2, $32C3, $36C4, $36C5, $36C6, $36C7, $3AC8, $3AC9, $3ACA, $3ACB, $3ECC, $3ECD, $3ECE, $3ECF // ROW20: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW21: OBJ +dw $2260, $2261, $2262, $2263, $2664, $2665, $2666, $2667, $2A68, $2A69, $2A6A, $2A6B, $2E6C, $2E6D, $2E6E, $2E6F, $32E0, $32E1, $32E2, $32E3, $36E4, $36E5, $36E6, $36E7, $3AE8, $3AE9, $3AEA, $3AEB, $3EEC, $3EED, $3EEE, $3EEF // ROW22: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW23: OBJ +dw $2300, $2301, $2302, $2303, $2704, $2705, $2706, $2707, $2B08, $2B09, $2B0A, $2B0B, $2F0C, $2F0D, $2F0E, $2F0F, $3340, $3341, $3342, $3343, $3744, $3745, $3746, $3747, $3B48, $3B49, $3B4A, $3B4B, $3F4C, $3F4D, $3F4E, $3F4F // ROW24: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW25: OBJ +dw $2320, $2321, $2322, $2323, $2724, $2725, $2726, $2727, $2B28, $2B29, $2B2A, $2B2B, $2F2C, $2F2D, $2F2E, $2F2F, $3360, $3361, $3362, $3363, $3764, $3765, $3766, $3767, $3B68, $3B69, $3B6A, $3B6B, $3F6C, $3F6D, $3F6E, $3F6F // ROW26: BG +dw $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380, $2380 // ROW27: OBJ \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/make.bat new file mode 100644 index 00000000..565ec3b6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/make.bat @@ -0,0 +1 @@ +bass HiColor128PerTileRow.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pal new file mode 100644 index 00000000..e8362187 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pic new file mode 100644 index 00000000..7138ea9f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.png new file mode 100644 index 00000000..91fd9fdb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/SNESBGPAL64tilerow.py b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/SNESBGPAL64tilerow.py new file mode 100644 index 00000000..6afdffd7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/GFX/SNESBGPAL64tilerow.py @@ -0,0 +1,91 @@ +# Syntax: SNESBGPAL64tilerow.py image.in file.out +# Notes: image.in needs to be 256x224 pixel resolution image +# Written for Python 3.6.2 with the Pillow 4.2.1 library +import sys +import struct +import PIL.Image + +# Quantize Options: +colors = 15 # The desired number of colors, <= 256 +method = 0 # 0 = median cut 1 = maximum coverage 2 = fast octree 3 = libimagequant +kmeans = 3 # Integer + +def convert_pal(image, filedata): # Convert To SNES 16 Color Palette Data + palette = image.getpalette()[:(15*3)] # Get 15 * R,G,B Palette Entries + filedata.write(struct.pack('H', 0)) # Store Black To Palette Color Index 0 + for i in range(15): + R = palette[i*3] + G = palette[(i*3)+1] + B = palette[(i*3)+2] + SNEScol = ((B & 0xF8) << 7) | ((G & 0xF8) << 2) | ((R & 0xF8) >> 3) + filedata.write(struct.pack('H', SNEScol)) + +def convert_tile(image, tilenum, filedata): # Convert To SNES 8x8 4BPP Tile Data + pixels = image.getdata() + + tile = [] + i = tilenum * 8 + for y in range(8): + for x in range(8): + tile.append(pixels[i] + 1) + i += 1 + i += 56 # Tile Row Segment Stride + + SNEStile = [0] * 32 # Set SNES Tile Array (32 Bytes) + for y in range(8): # Rows + byte1 = byte2 = byte3 = byte4 = 0 + for x in range(8): # Columns + byte1 += (tile[(y<<3)+x] & 1)<<(7-x) + byte2 += ((tile[(y<<3)+x]>>1) & 1)<<(7-x) + byte3 += ((tile[(y<<3)+x]>>2) & 1)<<(7-x) + byte4 += ((tile[(y<<3)+x]>>3) & 1)<<(7-x) + SNEStile[(y*2)] = byte1 + SNEStile[(y*2)+1] = byte2 + SNEStile[(y*2)+16] = byte3 + SNEStile[(y*2)+17] = byte4 + + for i in range(32): filedata.write(struct.pack('B', SNEStile[i])) # Write 4BPP 8x8 Tile (32 Bytes) + +def convert_segment(image, filedata): # Convert Tile Data From 64x8 Picture Segment + convert_tile(image, 0, filedata) + convert_tile(image, 1, filedata) + convert_tile(image, 2, filedata) + convert_tile(image, 3, filedata) + convert_tile(image, 4, filedata) + convert_tile(image, 5, filedata) + convert_tile(image, 6, filedata) + convert_tile(image, 7, filedata) + +def main(argv=None): + if argv is None: + argv = sys.argv[1:] + infilename, outfilename = argv + outpal = open(outfilename+'.pal', 'wb') + outtile = open(outfilename+'.pic', 'wb') + in_img = PIL.Image.open(infilename) + width, height = in_img.size + + # Convert Tile Row Data & Palette From Full Picture + for i in range(int(height/8)): + segment = in_img.crop((0, i*8, 64, (i*8)+8)) # Convert Tile Data & Palette From 64x8 Picture Segment (Left) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment(segment, outtile) + + segment = in_img.crop((64, i*8, 128, (i*8)+8)) # Convert Tile Data & Palette From 64x8 Picture Segment (Middle Left) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment(segment, outtile) + + segment = in_img.crop((128, i*8, 192, (i*8)+8)) # Convert Tile Data & Palette From 64x8 Picture Segment (Middle Right) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment(segment, outtile) + + segment = in_img.crop((192, i*8, 256, (i*8)+8)) # Convert Tile Data & Palette From 64x8 Picture Segment (Right) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment(segment, outtile) + +if __name__ == '__main__': + main() diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.asm new file mode 100644 index 00000000..bc6a9ae7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.asm @@ -0,0 +1,111 @@ +// SNES Hi Color (64 Per Tile Row) Using 4BPP BG Mode Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor64PerTileRow.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG2 8x8 Tiles + + // Setup BG2 16 Colour Background + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG2 Tile Address = $0000 (VRAM Address / $1000) + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG2VOFS // Store A into BG Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG Scroll Pos High Byte + + lda.b #%00000010 // Enable BG2 + sta.w REG_TM // $212C: BG2 To Main Screen Designation + + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGMap, $7900, 1792, 0) // Load Background Tile Map To VRAM + + // DMA Palette Data On Interrupt (DMA Channel 0) + lda.b #%00000000 // DMA: Write 1 Byte, Increment Source + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGDATA // $22: Start At Palette CGRAM Address ($2122) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + lda.b #BGPal >> 16 // DMA Source Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + lda.b #$0F + sta.w REG_INIDISP // $80: Turn On Screen, Full Brightness ($2100) + + // IRQ + lda.b #190 // Value Depends On How Long Horizontal IRQ Takes To Start DMA + sta.w REG_HTIMEL // $4207: H-Count Timer Setting (Lower 8-Bit) + lda.b #%10010000 // NMI & Horizontal IRQ + sta.w REG_NMITIMEN // $4200: Interrupt Enable & Joypad Request (Enable NMI) + + WaitNMI() // Wait For Vertical Blank + cli // Enable Interrupts + +loop: + wai + jmp loop + +VBLANKIRQ: + stz.w REG_CGADD // $2121: Palette CGRAM Address = 0 + ldx.w #BGPal // DMA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + ldx.w #128 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + rti + +HTIMERIRQ: + lda.w REG_TIMEUP // $4211: H/V-Timer IRQ Flag (Read/Ack) (Clear IRQ Line) + + lda.w REG_SLHV // $2137: PPU1 Latch H/V-Counter By Software (Read=Strobe) + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Lo Byte) + xba // Exchange B & A Accumulators + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Hi Byte) + and.b #$01 // A &= 1 (Bit 9 Of Vertical Counter) + xba // Exchange B & A Accumulators (A = Scanline Lo Byte) + tax // Transfer A To X Index (X = Scanline Count) + + cpx.w #216 // Compare Scanline Count To 216 + bpl SkipDMA // IF (Scanline Count < 216) Skip DMA + + and.b #$F // A &= $F + cmp.b #$8 // Compare A To 8 + bne DMAPAL // IF (Scanline Count != Muliple Of 8) DMA Palette, ELSE Reset Palette Address + stz.w REG_CGADD // $2121: Palette CGRAM Address = 0 + + DMAPAL: + ldx.w #16 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + + SkipDMA: + rti + +BGMap: + include "TileMap4PAL64ColPerTileRow256x224.asm" // Include BG Map Data (1792 Bytes) + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Tile Row 00 Palette Data (3584 Bytes) +// BANK 1 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (28672 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.png new file mode 100644 index 00000000..a275557f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.sfc new file mode 100644 index 00000000..7b67c4ea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..eb6d0fa3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HICOL 64 PER TILE ROW" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw VBLANKIRQ // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw HTIMERIRQ // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ.png new file mode 100644 index 00000000..3d53b50c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.png new file mode 100644 index 00000000..dcfa1b62 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.sfc new file mode 100644 index 00000000..ef87516e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png new file mode 100644 index 00000000..91fd9fdb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.png new file mode 100644 index 00000000..a275557f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.sfc new file mode 100644 index 00000000..7b67c4ea Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna.png new file mode 100644 index 00000000..9358d9f8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.png new file mode 100644 index 00000000..d00e68f6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.sfc new file mode 100644 index 00000000..7c688184 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill.png new file mode 100644 index 00000000..4e751954 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.png new file mode 100644 index 00000000..3296d312 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.sfc new file mode 100644 index 00000000..e9c9c6fd Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TileMap4PAL64ColPerTileRow256x224.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TileMap4PAL64ColPerTileRow256x224.asm new file mode 100644 index 00000000..d4bbe57a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TileMap4PAL64ColPerTileRow256x224.asm @@ -0,0 +1,28 @@ +dw $0000, $0001, $0002, $0003, $0004, $0005, $0006, $0007, $0408, $0409, $040a, $040b, $040c, $040d, $040e, $040f, $0810, $0811, $0812, $0813, $0814, $0815, $0816, $0817, $0C18, $0C19, $0C1a, $0C1b, $0C1c, $0C1d, $0C1e, $0C1f +dw $1020, $1021, $1022, $1023, $1024, $1025, $1026, $1027, $1428, $1429, $142a, $142b, $142c, $142d, $142e, $142f, $1830, $1831, $1832, $1833, $1834, $1835, $1836, $1837, $1C38, $1C39, $1C3a, $1C3b, $1C3c, $1C3d, $1C3e, $1C3f +dw $0040, $0041, $0042, $0043, $0044, $0045, $0046, $0047, $0448, $0449, $044a, $044b, $044c, $044d, $044e, $044f, $0850, $0851, $0852, $0853, $0854, $0855, $0856, $0857, $0C58, $0C59, $0C5a, $0C5b, $0C5c, $0C5d, $0C5e, $0C5f +dw $1060, $1061, $1062, $1063, $1064, $1065, $1066, $1067, $1468, $1469, $146a, $146b, $146c, $146d, $146e, $146f, $1870, $1871, $1872, $1873, $1874, $1875, $1876, $1877, $1C78, $1C79, $1C7a, $1C7b, $1C7c, $1C7d, $1C7e, $1C7f +dw $0080, $0081, $0082, $0083, $0084, $0085, $0086, $0087, $0488, $0489, $048a, $048b, $048c, $048d, $048e, $048f, $0890, $0891, $0892, $0893, $0894, $0895, $0896, $0897, $0C98, $0C99, $0C9a, $0C9b, $0C9c, $0C9d, $0C9e, $0C9f +dw $10a0, $10a1, $10a2, $10a3, $10a4, $10a5, $10a6, $10a7, $14a8, $14a9, $14aa, $14ab, $14ac, $14ad, $14ae, $14af, $18b0, $18b1, $18b2, $18b3, $18b4, $18b5, $18b6, $18b7, $1Cb8, $1Cb9, $1Cba, $1Cbb, $1Cbc, $1Cbd, $1Cbe, $1Cbf +dw $00c0, $00c1, $00c2, $00c3, $00c4, $00c5, $00c6, $00c7, $04c8, $04c9, $04ca, $04cb, $04cc, $04cd, $04ce, $04cf, $08d0, $08d1, $08d2, $08d3, $08d4, $08d5, $08d6, $08d7, $0Cd8, $0Cd9, $0Cda, $0Cdb, $0Cdc, $0Cdd, $0Cde, $0Cdf +dw $10e0, $10e1, $10e2, $10e3, $10e4, $10e5, $10e6, $10e7, $14e8, $14e9, $14ea, $14eb, $14ec, $14ed, $14ee, $14ef, $18f0, $18f1, $18f2, $18f3, $18f4, $18f5, $18f6, $18f7, $1Cf8, $1Cf9, $1Cfa, $1Cfb, $1Cfc, $1Cfd, $1Cfe, $1Cff +dw $0100, $0101, $0102, $0103, $0104, $0105, $0106, $0107, $0508, $0509, $050a, $050b, $050c, $050d, $050e, $050f, $0910, $0911, $0912, $0913, $0914, $0915, $0916, $0917, $0D18, $0D19, $0D1a, $0D1b, $0D1c, $0D1d, $0D1e, $0D1f +dw $1120, $1121, $1122, $1123, $1124, $1125, $1126, $1127, $1528, $1529, $152a, $152b, $152c, $152d, $152e, $152f, $1930, $1931, $1932, $1933, $1934, $1935, $1936, $1937, $1D38, $1D39, $1D3a, $1D3b, $1D3c, $1D3d, $1D3e, $1D3f +dw $0140, $0141, $0142, $0143, $0144, $0145, $0146, $0147, $0548, $0549, $054a, $054b, $054c, $054d, $054e, $054f, $0950, $0951, $0952, $0953, $0954, $0955, $0956, $0957, $0D58, $0D59, $0D5a, $0D5b, $0D5c, $0D5d, $0D5e, $0D5f +dw $1160, $1161, $1162, $1163, $1164, $1165, $1166, $1167, $1568, $1569, $156a, $156b, $156c, $156d, $156e, $156f, $1970, $1971, $1972, $1973, $1974, $1975, $1976, $1977, $1D78, $1D79, $1D7a, $1D7b, $1D7c, $1D7d, $1D7e, $1D7f +dw $0180, $0181, $0182, $0183, $0184, $0185, $0186, $0187, $0588, $0589, $058a, $058b, $058c, $058d, $058e, $058f, $0990, $0991, $0992, $0993, $0994, $0995, $0996, $0997, $0D98, $0D99, $0D9a, $0D9b, $0D9c, $0D9d, $0D9e, $0D9f +dw $11a0, $11a1, $11a2, $11a3, $11a4, $11a5, $11a6, $11a7, $15a8, $15a9, $15aa, $15ab, $15ac, $15ad, $15ae, $15af, $19b0, $19b1, $19b2, $19b3, $19b4, $19b5, $19b6, $19b7, $1Db8, $1Db9, $1Dba, $1Dbb, $1Dbc, $1Dbd, $1Dbe, $1Dbf +dw $01c0, $01c1, $01c2, $01c3, $01c4, $01c5, $01c6, $01c7, $05c8, $05c9, $05ca, $05cb, $05cc, $05cd, $05ce, $05cf, $09d0, $09d1, $09d2, $09d3, $09d4, $09d5, $09d6, $09d7, $0Dd8, $0Dd9, $0Dda, $0Ddb, $0Ddc, $0Ddd, $0Dde, $0Ddf +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $15e8, $15e9, $15ea, $15eb, $15ec, $15ed, $15ee, $15ef, $19f0, $19f1, $19f2, $19f3, $19f4, $19f5, $19f6, $19f7, $1Df8, $1Df9, $1Dfa, $1Dfb, $1Dfc, $1Dfd, $1Dfe, $1Dff +dw $0200, $0201, $0202, $0203, $0204, $0205, $0206, $0207, $0608, $0609, $060a, $060b, $060c, $060d, $060e, $060f, $0A10, $0A11, $0A12, $0A13, $0A14, $0A15, $0A16, $0A17, $0E18, $0E19, $0E1a, $0E1b, $0E1c, $0E1d, $0E1e, $0E1f +dw $1220, $1221, $1222, $1223, $1224, $1225, $1226, $1227, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1A30, $1A31, $1A32, $1A33, $1A34, $1A35, $1A36, $1A37, $1E38, $1E39, $1E3a, $1E3b, $1E3c, $1E3d, $1E3e, $1E3f +dw $0240, $0241, $0242, $0243, $0244, $0245, $0246, $0247, $0648, $0649, $064a, $064b, $064c, $064d, $064e, $064f, $0A50, $0A51, $0A52, $0A53, $0A54, $0A55, $0A56, $0A57, $0E58, $0E59, $0E5a, $0E5b, $0E5c, $0E5d, $0E5e, $0E5f +dw $1260, $1261, $1262, $1263, $1264, $1265, $1266, $1267, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1A70, $1A71, $1A72, $1A73, $1A74, $1A75, $1A76, $1A77, $1E78, $1E79, $1E7a, $1E7b, $1E7c, $1E7d, $1E7e, $1E7f +dw $0280, $0281, $0282, $0283, $0284, $0285, $0286, $0287, $0688, $0689, $068a, $068b, $068c, $068d, $068e, $068f, $0A90, $0A91, $0A92, $0A93, $0A94, $0A95, $0A96, $0A97, $0E98, $0E99, $0E9a, $0E9b, $0E9c, $0E9d, $0E9e, $0E9f +dw $12a0, $12a1, $12a2, $12a3, $12a4, $12a5, $12a6, $12a7, $16a8, $16a9, $16aa, $16ab, $16ac, $16ad, $16ae, $16af, $1Ab0, $1Ab1, $1Ab2, $1Ab3, $1Ab4, $1Ab5, $1Ab6, $1Ab7, $1Eb8, $1Eb9, $1Eba, $1Ebb, $1Ebc, $1Ebd, $1Ebe, $1Ebf +dw $02c0, $02c1, $02c2, $02c3, $02c4, $02c5, $02c6, $02c7, $06c8, $06c9, $06ca, $06cb, $06cc, $06cd, $06ce, $06cf, $0Ad0, $0Ad1, $0Ad2, $0Ad3, $0Ad4, $0Ad5, $0Ad6, $0Ad7, $0Ed8, $0Ed9, $0Eda, $0Edb, $0Edc, $0Edd, $0Ede, $0Edf +dw $12e0, $12e1, $12e2, $12e3, $12e4, $12e5, $12e6, $12e7, $16e8, $16e9, $16ea, $16eb, $16ec, $16ed, $16ee, $16ef, $1Af0, $1Af1, $1Af2, $1Af3, $1Af4, $1Af5, $1Af6, $1Af7, $1Ef8, $1Ef9, $1Efa, $1Efb, $1Efc, $1Efd, $1Efe, $1Eff +dw $0300, $0301, $0302, $0303, $0304, $0305, $0306, $0307, $0708, $0709, $070a, $070b, $070c, $070d, $070e, $070f, $0B10, $0B11, $0B12, $0B13, $0B14, $0B15, $0B16, $0B17, $0F18, $0F19, $0F1a, $0F1b, $0F1c, $0F1d, $0F1e, $0F1f +dw $1320, $1321, $1322, $1323, $1324, $1325, $1326, $1327, $1728, $1729, $172a, $172b, $172c, $172d, $172e, $172f, $1B30, $1B31, $1B32, $1B33, $1B34, $1B35, $1B36, $1B37, $1F38, $1F39, $1F3a, $1F3b, $1F3c, $1F3d, $1F3e, $1F3f +dw $0340, $0341, $0342, $0343, $0344, $0345, $0346, $0347, $0748, $0749, $074a, $074b, $074c, $074d, $074e, $074f, $0B50, $0B51, $0B52, $0B53, $0B54, $0B55, $0B56, $0B57, $0F58, $0F59, $0F5a, $0F5b, $0F5c, $0F5d, $0F5e, $0F5f +dw $1360, $1361, $1362, $1363, $1364, $1365, $1366, $1367, $1768, $1769, $176a, $176b, $176c, $176d, $176e, $176f, $1B70, $1B71, $1B72, $1B73, $1B74, $1B75, $1B76, $1B77, $1F78, $1F79, $1F7a, $1F7b, $1F7c, $1F7d, $1F7e, $1F7f diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/make.bat new file mode 100644 index 00000000..b4d53c34 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/make.bat @@ -0,0 +1 @@ +bass HiColor64PerTileRow.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.pal new file mode 100644 index 00000000..b23a6cb7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.png new file mode 100644 index 00000000..1155fb86 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG1.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG1.pic new file mode 100644 index 00000000..6847918a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG1.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG2.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG2.pic new file mode 100644 index 00000000..117a8eca Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/BG2.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/RGB_24bits_palette_color_test_chart.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/RGB_24bits_palette_color_test_chart.png new file mode 100644 index 00000000..5bb0ce8b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/RGB_24bits_palette_color_test_chart.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/SNESBGPAL64tilerowHiRes.py b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/SNESBGPAL64tilerowHiRes.py new file mode 100644 index 00000000..6aec74f3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/GFX/SNESBGPAL64tilerowHiRes.py @@ -0,0 +1,132 @@ +# Syntax: SNESBGPAL64tilerowinterlace.py image.in file.out +# Notes: image.in needs to be 512x224 pixel resolution image +# Written for Python 3.6.2 with the Pillow 4.2.1 library +import sys +import struct +import PIL.Image + +# Quantize Options: +colors = 15 # The desired number of colors, <= 256 +method = 0 # 0 = median cut 1 = maximum coverage 2 = fast octree 3 = libimagequant +kmeans = 3 # Integer + +def convert_pal(image, filedata): # Convert To SNES 16 Color Palette Data + palette = image.getpalette()[:(15*3)] # Get 15 * R,G,B Palette Entries + filedata.write(struct.pack('H', 0)) # Store Black To Palette Color Index 0 + for i in range(15): + R = palette[i*3] + G = palette[(i*3)+1] + B = palette[(i*3)+2] + SNEScol = ((B & 0xF8) << 7) | ((G & 0xF8) << 2) | ((R & 0xF8) >> 3) + filedata.write(struct.pack('H', SNEScol)) + +def convert_tile1(image, tilenum, filedata): # Convert To SNES 8x8 4BPP Tile Data + pixels = image.getdata() + + tile = [] + i = (tilenum * 16) + 1 + for y in range(8): + for x in range(8): + tile.append(pixels[i] + 1) + i += 2 + i += 112 # Tile Row Segment Stride + + SNEStile = [0] * 32 # Set SNES Tile Array (32 Bytes) + for y in range(8): # Rows + byte1 = byte2 = byte3 = byte4 = 0 + for x in range(8): # Columns + byte1 += (tile[(y<<3)+x] & 1)<<(7-x) + byte2 += ((tile[(y<<3)+x]>>1) & 1)<<(7-x) + byte3 += ((tile[(y<<3)+x]>>2) & 1)<<(7-x) + byte4 += ((tile[(y<<3)+x]>>3) & 1)<<(7-x) + SNEStile[(y*2)] = byte1 + SNEStile[(y*2)+1] = byte2 + SNEStile[(y*2)+16] = byte3 + SNEStile[(y*2)+17] = byte4 + + for i in range(32): filedata.write(struct.pack('B', SNEStile[i])) # Write 4BPP 8x8 Tile (32 Bytes) + +def convert_tile2(image, tilenum, filedata): # Convert To SNES 8x8 4BPP Tile Data + pixels = image.getdata() + + tile = [] + i = tilenum * 16 + for y in range(8): + for x in range(8): + tile.append(pixels[i] + 1) + i += 2 + i += 112 # Tile Row Segment Stride + + SNEStile = [0] * 32 # Set SNES Tile Array (32 Bytes) + for y in range(8): # Rows + byte1 = byte2 = byte3 = byte4 = 0 + for x in range(8): # Columns + byte1 += (tile[(y<<3)+x] & 1)<<(7-x) + byte2 += ((tile[(y<<3)+x]>>1) & 1)<<(7-x) + byte3 += ((tile[(y<<3)+x]>>2) & 1)<<(7-x) + byte4 += ((tile[(y<<3)+x]>>3) & 1)<<(7-x) + SNEStile[(y*2)] = byte1 + SNEStile[(y*2)+1] = byte2 + SNEStile[(y*2)+16] = byte3 + SNEStile[(y*2)+17] = byte4 + + for i in range(32): filedata.write(struct.pack('B', SNEStile[i])) # Write 4BPP 8x8 Tile (32 Bytes) + +def convert_segment1(image, filedata): # Convert Tile Data From 128x8 Picture Segment (Odd Pixels) + convert_tile1(image, 0, filedata) + convert_tile1(image, 1, filedata) + convert_tile1(image, 2, filedata) + convert_tile1(image, 3, filedata) + convert_tile1(image, 4, filedata) + convert_tile1(image, 5, filedata) + convert_tile1(image, 6, filedata) + convert_tile1(image, 7, filedata) + +def convert_segment2(image, filedata): # Convert Tile Data From 128x8 Picture Segment (Even Pixels) + convert_tile2(image, 0, filedata) + convert_tile2(image, 1, filedata) + convert_tile2(image, 2, filedata) + convert_tile2(image, 3, filedata) + convert_tile2(image, 4, filedata) + convert_tile2(image, 5, filedata) + convert_tile2(image, 6, filedata) + convert_tile2(image, 7, filedata) + +def main(argv=None): + if argv is None: + argv = sys.argv[1:] + infilename, outfilename = argv + outpal = open(outfilename+'.pal', 'wb') + outtile1 = open(outfilename+'1.pic', 'wb') + outtile2 = open(outfilename+'2.pic', 'wb') + in_img = PIL.Image.open(infilename) + width, height = in_img.size + + # Convert Tile Row Data & Palette From Full Picture + for i in range(int(height/8)): + segment = in_img.crop((0, i*8, 128, (i*8)+8)) # Convert Tile Data & Palette From 128x8 Picture Segment (Left) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment1(segment, outtile1) + convert_segment2(segment, outtile2) + + segment = in_img.crop((128, i*8, 256, (i*8)+8)) # Convert Tile Data & Palette From 128x8 Picture Segment (Middle Left) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment1(segment, outtile1) + convert_segment2(segment, outtile2) + + segment = in_img.crop((256, i*8, 384, (i*8)+8)) # Convert Tile Data & Palette From 128x8 Picture Segment (Middle Right) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment1(segment, outtile1) + convert_segment2(segment, outtile2) + + segment = in_img.crop((384, i*8, 512, (i*8)+8)) # Convert Tile Data & Palette From 128x8 Picture Segment (Right) + segment = segment.quantize(colors=colors, method=method, kmeans=kmeans) + convert_pal(segment, outpal) + convert_segment1(segment, outtile1) + convert_segment2(segment, outtile2) + +if __name__ == '__main__': + main() diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.asm new file mode 100644 index 00000000..68ab72c1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.asm @@ -0,0 +1,132 @@ +// SNES Hi Color (64 Per Tile Row) Pseudo Horizontal High-Resolution (512x224) Using 4BPP BG Mode Demo by krom (Peter Lemon): +arch snes.cpu +output "HiColor64PerTileRowPseudoHiRes.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Setup Video + lda.b #%00001001 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 1, Priority 1, BG2 8x8 Tiles + + lda.b #%00001000 // Pseudo Horizontal High-Resolution + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 & BG2 16 Colour Background + lda.b #%01000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000, BG2 Tile Address = $8000 (VRAM Address / $1000) + lda.b #%00111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + sta.w REG_BG2SC // $2108: BG2 32x32, BG2 Map Address = $7800 (VRAM Address / $400) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + + lda.b #31 // Scroll BG2 31 Pixels Up + sta.w REG_BG1VOFS // Store A into BG1 Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store zero into BG1 Scroll Pos High Byte + sta.w REG_BG2VOFS // Store A into BG2 Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store zero into BG2 Scroll Pos High Byte + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + lda.b #%00000010 // Enable BG2 + sta.w REG_TS // $212D: BG2 To Sub Screen Designation + + lda.b #$02 + sta.w REG_CGWSEL // $2130: Enable Subscreen Color ADD/SUB + + lda.b #%01100001 + sta.w REG_CGADSUB // $2131: Colour Addition On BG1 And Backdrop Colour, Result / 2 + + LoadVRAM(BG1Tiles, $0000, BG1Tiles.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BG2Tiles, $8000, BG2Tiles.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGMap, $7900, 1792, 0) // Load Background Tile Map To VRAM + + // DMA Palette Data On Interrupt (DMA Channel 0) + lda.b #%00000000 // DMA: Write 1 Byte, Increment Source + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGDATA // $22: Start At Palette CGRAM Address ($2122) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + lda.b #BGPal >> 16 // DMA Source Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + lda.b #$0F + sta.w REG_INIDISP // $80: Turn On Screen, Full Brightness ($2100) + + // IRQ + lda.b #190 // Value Depends On How Long Horizontal IRQ Takes To Start DMA + sta.w REG_HTIMEL // $4207: H-Count Timer Setting (Lower 8-Bit) + lda.b #%10010000 // NMI & Horizontal IRQ + sta.w REG_NMITIMEN // $4200: Interrupt Enable & Joypad Request (Enable NMI) + + WaitNMI() // Wait For Vertical Blank + cli // Enable Interrupts + +loop: + wai + jmp loop + +VBLANKIRQ: + stz.w REG_CGADD // $2121: Palette CGRAM Address = 0 + ldx.w #BGPal // DMA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + ldx.w #128 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + rti + +HTIMERIRQ: + lda.w REG_TIMEUP // $4211: H/V-Timer IRQ Flag (Read/Ack) (Clear IRQ Line) + + lda.w REG_SLHV // $2137: PPU1 Latch H/V-Counter By Software (Read=Strobe) + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Lo Byte) + xba // Exchange B & A Accumulators + lda.w REG_OPVCT // $213D: PPU2 Vertical Counter Latch (Scanline Hi Byte) + and.b #$01 // A &= 1 (Bit 9 Of Vertical Counter) + xba // Exchange B & A Accumulators (A = Scanline Lo Byte) + tax // Transfer A To X Index (X = Scanline Count) + + cpx.w #216 // Compare Scanline Count To 216 + bpl SkipDMA // IF (Scanline Count < 216) Skip DMA + + and.b #$F // A &= $F + cmp.b #$8 // Compare A To 8 + bne DMAPAL // IF (Scanline Count != Muliple Of 8) DMA Palette, ELSE Reset Palette Address + stz.w REG_CGADD // $2121: Palette CGRAM Address = 0 + + DMAPAL: + ldx.w #16 // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer (Channel 0) + sta.w REG_MDMAEN // $420B: DMA Enable + + SkipDMA: + rti + +BGMap: + include "TileMap4PAL64ColPerTileRow256x224.asm" // Include BG Map Data (1792 Bytes) + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Tile Row 00 Palette Data (3584 Bytes) +// BANK 1 +seek($18000) +insert BG1Tiles, "GFX/BG1.pic" // Include BG Tile Data (28672 Bytes) +// BANK 2 +seek($28000) +insert BG2Tiles, "GFX/BG2.pic" // Include BG Tile Data (28672 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.png new file mode 100644 index 00000000..1be76ded Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.sfc new file mode 100644 index 00000000..90c0746e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..5bb61d35 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "HICOL 64 PER TILE ROW" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw VBLANKIRQ // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw HTIMERIRQ // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart.png new file mode 100644 index 00000000..5bb0ce8b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.png new file mode 100644 index 00000000..cb43ff68 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.sfc new file mode 100644 index 00000000..4e5ddda5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna.png new file mode 100644 index 00000000..2bca991b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.png new file mode 100644 index 00000000..0c76eedb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.sfc new file mode 100644 index 00000000..104b9d68 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill.png new file mode 100644 index 00000000..1155fb86 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.png b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.png new file mode 100644 index 00000000..1be76ded Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.sfc new file mode 100644 index 00000000..90c0746e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TileMap4PAL64ColPerTileRow256x224.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TileMap4PAL64ColPerTileRow256x224.asm new file mode 100644 index 00000000..d4bbe57a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TileMap4PAL64ColPerTileRow256x224.asm @@ -0,0 +1,28 @@ +dw $0000, $0001, $0002, $0003, $0004, $0005, $0006, $0007, $0408, $0409, $040a, $040b, $040c, $040d, $040e, $040f, $0810, $0811, $0812, $0813, $0814, $0815, $0816, $0817, $0C18, $0C19, $0C1a, $0C1b, $0C1c, $0C1d, $0C1e, $0C1f +dw $1020, $1021, $1022, $1023, $1024, $1025, $1026, $1027, $1428, $1429, $142a, $142b, $142c, $142d, $142e, $142f, $1830, $1831, $1832, $1833, $1834, $1835, $1836, $1837, $1C38, $1C39, $1C3a, $1C3b, $1C3c, $1C3d, $1C3e, $1C3f +dw $0040, $0041, $0042, $0043, $0044, $0045, $0046, $0047, $0448, $0449, $044a, $044b, $044c, $044d, $044e, $044f, $0850, $0851, $0852, $0853, $0854, $0855, $0856, $0857, $0C58, $0C59, $0C5a, $0C5b, $0C5c, $0C5d, $0C5e, $0C5f +dw $1060, $1061, $1062, $1063, $1064, $1065, $1066, $1067, $1468, $1469, $146a, $146b, $146c, $146d, $146e, $146f, $1870, $1871, $1872, $1873, $1874, $1875, $1876, $1877, $1C78, $1C79, $1C7a, $1C7b, $1C7c, $1C7d, $1C7e, $1C7f +dw $0080, $0081, $0082, $0083, $0084, $0085, $0086, $0087, $0488, $0489, $048a, $048b, $048c, $048d, $048e, $048f, $0890, $0891, $0892, $0893, $0894, $0895, $0896, $0897, $0C98, $0C99, $0C9a, $0C9b, $0C9c, $0C9d, $0C9e, $0C9f +dw $10a0, $10a1, $10a2, $10a3, $10a4, $10a5, $10a6, $10a7, $14a8, $14a9, $14aa, $14ab, $14ac, $14ad, $14ae, $14af, $18b0, $18b1, $18b2, $18b3, $18b4, $18b5, $18b6, $18b7, $1Cb8, $1Cb9, $1Cba, $1Cbb, $1Cbc, $1Cbd, $1Cbe, $1Cbf +dw $00c0, $00c1, $00c2, $00c3, $00c4, $00c5, $00c6, $00c7, $04c8, $04c9, $04ca, $04cb, $04cc, $04cd, $04ce, $04cf, $08d0, $08d1, $08d2, $08d3, $08d4, $08d5, $08d6, $08d7, $0Cd8, $0Cd9, $0Cda, $0Cdb, $0Cdc, $0Cdd, $0Cde, $0Cdf +dw $10e0, $10e1, $10e2, $10e3, $10e4, $10e5, $10e6, $10e7, $14e8, $14e9, $14ea, $14eb, $14ec, $14ed, $14ee, $14ef, $18f0, $18f1, $18f2, $18f3, $18f4, $18f5, $18f6, $18f7, $1Cf8, $1Cf9, $1Cfa, $1Cfb, $1Cfc, $1Cfd, $1Cfe, $1Cff +dw $0100, $0101, $0102, $0103, $0104, $0105, $0106, $0107, $0508, $0509, $050a, $050b, $050c, $050d, $050e, $050f, $0910, $0911, $0912, $0913, $0914, $0915, $0916, $0917, $0D18, $0D19, $0D1a, $0D1b, $0D1c, $0D1d, $0D1e, $0D1f +dw $1120, $1121, $1122, $1123, $1124, $1125, $1126, $1127, $1528, $1529, $152a, $152b, $152c, $152d, $152e, $152f, $1930, $1931, $1932, $1933, $1934, $1935, $1936, $1937, $1D38, $1D39, $1D3a, $1D3b, $1D3c, $1D3d, $1D3e, $1D3f +dw $0140, $0141, $0142, $0143, $0144, $0145, $0146, $0147, $0548, $0549, $054a, $054b, $054c, $054d, $054e, $054f, $0950, $0951, $0952, $0953, $0954, $0955, $0956, $0957, $0D58, $0D59, $0D5a, $0D5b, $0D5c, $0D5d, $0D5e, $0D5f +dw $1160, $1161, $1162, $1163, $1164, $1165, $1166, $1167, $1568, $1569, $156a, $156b, $156c, $156d, $156e, $156f, $1970, $1971, $1972, $1973, $1974, $1975, $1976, $1977, $1D78, $1D79, $1D7a, $1D7b, $1D7c, $1D7d, $1D7e, $1D7f +dw $0180, $0181, $0182, $0183, $0184, $0185, $0186, $0187, $0588, $0589, $058a, $058b, $058c, $058d, $058e, $058f, $0990, $0991, $0992, $0993, $0994, $0995, $0996, $0997, $0D98, $0D99, $0D9a, $0D9b, $0D9c, $0D9d, $0D9e, $0D9f +dw $11a0, $11a1, $11a2, $11a3, $11a4, $11a5, $11a6, $11a7, $15a8, $15a9, $15aa, $15ab, $15ac, $15ad, $15ae, $15af, $19b0, $19b1, $19b2, $19b3, $19b4, $19b5, $19b6, $19b7, $1Db8, $1Db9, $1Dba, $1Dbb, $1Dbc, $1Dbd, $1Dbe, $1Dbf +dw $01c0, $01c1, $01c2, $01c3, $01c4, $01c5, $01c6, $01c7, $05c8, $05c9, $05ca, $05cb, $05cc, $05cd, $05ce, $05cf, $09d0, $09d1, $09d2, $09d3, $09d4, $09d5, $09d6, $09d7, $0Dd8, $0Dd9, $0Dda, $0Ddb, $0Ddc, $0Ddd, $0Dde, $0Ddf +dw $11e0, $11e1, $11e2, $11e3, $11e4, $11e5, $11e6, $11e7, $15e8, $15e9, $15ea, $15eb, $15ec, $15ed, $15ee, $15ef, $19f0, $19f1, $19f2, $19f3, $19f4, $19f5, $19f6, $19f7, $1Df8, $1Df9, $1Dfa, $1Dfb, $1Dfc, $1Dfd, $1Dfe, $1Dff +dw $0200, $0201, $0202, $0203, $0204, $0205, $0206, $0207, $0608, $0609, $060a, $060b, $060c, $060d, $060e, $060f, $0A10, $0A11, $0A12, $0A13, $0A14, $0A15, $0A16, $0A17, $0E18, $0E19, $0E1a, $0E1b, $0E1c, $0E1d, $0E1e, $0E1f +dw $1220, $1221, $1222, $1223, $1224, $1225, $1226, $1227, $1628, $1629, $162a, $162b, $162c, $162d, $162e, $162f, $1A30, $1A31, $1A32, $1A33, $1A34, $1A35, $1A36, $1A37, $1E38, $1E39, $1E3a, $1E3b, $1E3c, $1E3d, $1E3e, $1E3f +dw $0240, $0241, $0242, $0243, $0244, $0245, $0246, $0247, $0648, $0649, $064a, $064b, $064c, $064d, $064e, $064f, $0A50, $0A51, $0A52, $0A53, $0A54, $0A55, $0A56, $0A57, $0E58, $0E59, $0E5a, $0E5b, $0E5c, $0E5d, $0E5e, $0E5f +dw $1260, $1261, $1262, $1263, $1264, $1265, $1266, $1267, $1668, $1669, $166a, $166b, $166c, $166d, $166e, $166f, $1A70, $1A71, $1A72, $1A73, $1A74, $1A75, $1A76, $1A77, $1E78, $1E79, $1E7a, $1E7b, $1E7c, $1E7d, $1E7e, $1E7f +dw $0280, $0281, $0282, $0283, $0284, $0285, $0286, $0287, $0688, $0689, $068a, $068b, $068c, $068d, $068e, $068f, $0A90, $0A91, $0A92, $0A93, $0A94, $0A95, $0A96, $0A97, $0E98, $0E99, $0E9a, $0E9b, $0E9c, $0E9d, $0E9e, $0E9f +dw $12a0, $12a1, $12a2, $12a3, $12a4, $12a5, $12a6, $12a7, $16a8, $16a9, $16aa, $16ab, $16ac, $16ad, $16ae, $16af, $1Ab0, $1Ab1, $1Ab2, $1Ab3, $1Ab4, $1Ab5, $1Ab6, $1Ab7, $1Eb8, $1Eb9, $1Eba, $1Ebb, $1Ebc, $1Ebd, $1Ebe, $1Ebf +dw $02c0, $02c1, $02c2, $02c3, $02c4, $02c5, $02c6, $02c7, $06c8, $06c9, $06ca, $06cb, $06cc, $06cd, $06ce, $06cf, $0Ad0, $0Ad1, $0Ad2, $0Ad3, $0Ad4, $0Ad5, $0Ad6, $0Ad7, $0Ed8, $0Ed9, $0Eda, $0Edb, $0Edc, $0Edd, $0Ede, $0Edf +dw $12e0, $12e1, $12e2, $12e3, $12e4, $12e5, $12e6, $12e7, $16e8, $16e9, $16ea, $16eb, $16ec, $16ed, $16ee, $16ef, $1Af0, $1Af1, $1Af2, $1Af3, $1Af4, $1Af5, $1Af6, $1Af7, $1Ef8, $1Ef9, $1Efa, $1Efb, $1Efc, $1Efd, $1Efe, $1Eff +dw $0300, $0301, $0302, $0303, $0304, $0305, $0306, $0307, $0708, $0709, $070a, $070b, $070c, $070d, $070e, $070f, $0B10, $0B11, $0B12, $0B13, $0B14, $0B15, $0B16, $0B17, $0F18, $0F19, $0F1a, $0F1b, $0F1c, $0F1d, $0F1e, $0F1f +dw $1320, $1321, $1322, $1323, $1324, $1325, $1326, $1327, $1728, $1729, $172a, $172b, $172c, $172d, $172e, $172f, $1B30, $1B31, $1B32, $1B33, $1B34, $1B35, $1B36, $1B37, $1F38, $1F39, $1F3a, $1F3b, $1F3c, $1F3d, $1F3e, $1F3f +dw $0340, $0341, $0342, $0343, $0344, $0345, $0346, $0347, $0748, $0749, $074a, $074b, $074c, $074d, $074e, $074f, $0B50, $0B51, $0B52, $0B53, $0B54, $0B55, $0B56, $0B57, $0F58, $0F59, $0F5a, $0F5b, $0F5c, $0F5d, $0F5e, $0F5f +dw $1360, $1361, $1362, $1363, $1364, $1365, $1366, $1367, $1768, $1769, $176a, $176b, $176c, $176d, $176e, $176f, $1B70, $1B71, $1B72, $1B73, $1B74, $1B75, $1B76, $1B77, $1F78, $1F79, $1F7a, $1F7b, $1F7c, $1F7d, $1F7e, $1F7f diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/make.bat new file mode 100644 index 00000000..e6d03793 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/make.bat @@ -0,0 +1 @@ +bass HiColor64PerTileRowPseudoHiRes.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.map new file mode 100644 index 00000000..fced587c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pal new file mode 100644 index 00000000..45afebe1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pic new file mode 100644 index 00000000..b2b78812 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.png new file mode 100644 index 00000000..33d27ad7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..43814af2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MODE7 HDMA DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.asm new file mode 100644 index 00000000..dd2955e8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.asm @@ -0,0 +1,334 @@ +// SNES Mode7 HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "Mode7HDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +Mode7PosX: + dw 0 // Mode7 Center Pos X Word +BG1ScrPosX: + dw 0 // Mode7 BG1 Scroll Position X Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadM7VRAM(BGMap, BGTiles, $0000, BGMap.size, BGTiles.size, 0) // Load Background Map & Tiles To VRAM + + lda.b #$01 // Enable Joypad NMI Reading Interrupt + sta.w REG_NMITIMEN + + // Setup Video + lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_M7SEL // $211A: MODE7 Settings + + stz.w REG_M7A // $211B: MODE7 COSINE A Lo Byte + sta.w REG_M7A // $211B: MODE7 COSINE A Hi Byte + + stz.w REG_M7B // $211B: MODE7 SINE A Lo Byte + stz.w REG_M7B // $211B: MODE7 SINE A Hi Byte + + stz.w REG_M7C // $211B: MODE7 SINE B Lo Byte + stz.w REG_M7C // $211B: MODE7 SINE B Hi Byte + + stz.w REG_M7D // $211E: MODE7 COSINE B Lo Byte + sta.w REG_M7D // $211E: MODE7 COSINE B Hi Byte + + ldx.w #$0000 // Reset BG1 X Position + stx.b BG1ScrPosX + + lda.b #$00 // Reset BG1 Y Position + sta.w REG_BG1VOFS // $210E: BG1 Vertical Scroll Position Lo Byte + sta.w REG_BG1VOFS // $210E: BG1 Vertical Scroll Position Hi Byte + + ldx.w #$0080 // Reset MODE7 Center X Pos + stx.b Mode7PosX + + lda.b #$00 // Reset MODE7 Center Y Pos + sta.w REG_M7Y // $2120: MODE7 Center Position Y Lo Byte + sta.w REG_M7Y // $2120: MODE7 Center Position Y Hi Byte + + // HDMA Mode7 Scanline Zoom (X) + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_M7A // $1B: Start At MODE7 COSINE A ($211B) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable0 // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + // HDMA Mode7 Scanline Zoom (Y) + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_M7D // $1E: Start At MODE7 COSINE B ($211E) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable1 // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + + // HDMA Mode7 Scanline Centre (Y) + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_M7Y // $20: Start At MODE7 Center Pos Y ($2120) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable2 // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + + lda.b #%00000111 // HDMA Channel Select (Channel 0,1,2) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + lda.b BG1ScrPosX + sta.w REG_BG1HOFS // $210D: BG1 Horizontal Scroll Position Lo Byte + lda.b BG1ScrPosX + 1 + sta.w REG_BG1HOFS // $210D: BG1 Horizontal Scroll Position Hi Byte + + lda.b Mode7PosX + sta.w REG_M7X // $211F: MODE7 Center Position X Lo Byte + lda.b Mode7PosX + 1 + sta.w REG_M7X // $211F: MODE7 Center Position X Hi Byte + + JoyLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq JoyRight // IF (LEFT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Decrement BG1 Horizontal Scroll Position + dex + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Decrement Mode7 X Position + dex + stx.b Mode7PosX + + JoyRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Increment BG1 Horizontal Scroll Position + inx + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Increment Mode7 X Position + inx + stx.b Mode7PosX + +Finish: + jmp InputLoop + +HDMATable0: // X Zoom Values + db 32; dw $0400 // Repeat 32 Scanlines, Zoom Value 1 (Sun) + db 32; dw $0400 // Repeat 32 Scanlines, Zoom Value 2 (Sun) + db 32; dw $0300 // Repeat 32 Scanlines, Zoom Value 3 (Trees) + db 24; dw $0300 // Repeat 24 Scanlines, Zoom Value 6 (Trees) + db 24; dw $0200 // Repeat 24 Scanlines, Zoom Value 7 (Pipes) + + db 1; dw $0200 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01F8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01F0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01E8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01E0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01D8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01D0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01C8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01C0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01B8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01B0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01A8 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $01A0 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0198 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0190 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0188 // Repeat 1 Scanlines, Zoom Value 9 + + db 1; dw $0180 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $017C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0178 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0174 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0170 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $016C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0168 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0164 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0160 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $015C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0158 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0154 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0150 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $014C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0148 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0144 // Repeat 1 Scanlines, Zoom Value 9 + + db 1; dw $0140 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $013C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0138 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0134 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0130 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $012C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0128 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0124 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0120 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $011C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0118 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0114 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0110 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $010C // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0108 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0104 // Repeat 1 Scanlines, Zoom Value 9 + + db 32; dw $0100 // Repeat 32 Scanlines, Zoom Value 10 + db $00 // End Of HDMA + + +HDMATable1: // Y Zoom Values + db 32; dw $0400 // Repeat 32 Scanlines, Zoom Value 1 (Sun) + db 32; dw $0400 // Repeat 32 Scanlines, Zoom Value 2 (Sun) + db 32; dw $0300 // Repeat 32 Scanlines, Zoom Value 3 (Trees) + db 24; dw $0300 // Repeat 24 Scanlines, Zoom Value 6 (Trees) + db 24; dw $0200 // Repeat 24 Scanlines, Zoom Value 7 (Pipes) + + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + db 1; dw $0800 // Repeat 1 Scanlines, Zoom Value 9 + + db 32; dw $0200 // Repeat 32 Scanlines, Zoom Value 10 + db $00 // End Of HDMA + +HDMATable2: // MODE7 Center Y Pos Values + db 32; dw $0000 // Repeat 32 Scanlines, Center Y Pos Value 1 (Sun) + db 32; dw $0000 // Repeat 32 Scanlines, Center Y Pos Value 2 (Sun) + db 32; dw $01C0 // Repeat 32 Scanlines, Center Y Pos Value 3 (Trees) + db 24; dw $01C0 // Repeat 24 Scanlines, Center Y Pos Value 6 (Trees) + db 24; dw $0300 // Repeat 24 Scanlines, Center Y Pos Value 7 (Pipes) + + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + db 1; dw $0600 // Repeat 1 Scanlines, Center Y Pos Value 9 + + db 32; dw $05C0 // Repeat 32 Scanlines, Center Y Pos Value 10 + db $00 // End Of HDMA + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (16384 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (10112 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.png b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.png new file mode 100644 index 00000000..4cf63f66 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.sfc new file mode 100644 index 00000000..e9d438d7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/make.bat new file mode 100644 index 00000000..9fa00e68 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/make.bat @@ -0,0 +1 @@ +bass Mode7HDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/Gradient.py b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/Gradient.py new file mode 100644 index 00000000..a87c66ab --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/Gradient.py @@ -0,0 +1,48 @@ +colbri = [] +for col in range(32): + for bri in range(16): + colbri.append(((col+1)/16)*(bri+1)) + #print('Color = 0x%02X, Brightness = 0x%01X, Calculation = %f' %(col, bri, ((col+1)/16)*(bri+1))) + +print('COLHDMATable:') +currentcol = 0x1F +currentbri = 0xF +currentcolbri = 32.0 +for scanline in range(224): + #print('Color = 0x%02X, Brightness = 0x%01X, Calculation = %f' %(currentcol, currentbri, currentcolbri)) + print(' db $01; dw $0000, $00%02X // Repeat 1 Scanline, Palette Address 0, Gradient Color %d' %(currentcol, scanline)) + tempcol = 0 + tempbri = 0 + tempcolbri = 0.0 + for col in range(32): + for bri in range(16): + if colbri[(col*16)+bri] < currentcolbri and colbri[(col*16)+bri] > tempcolbri and col != currentcol and bri != currentbri: + tempcolbri = colbri[(col*16)+bri] + tempcol = col + tempbri = bri + currentcolbri = tempcolbri + currentcol = tempcol + currentbri = tempbri +print(' db $00 // End Of HDMA\n') + +print('BRIHDMATable:') +currentcol = 0x1F +currentbri = 0xF +currentcolbri = 32.0 +for scanline in range(224): + #print('Color = 0x%02X, Brightness = 0x%01X, Calculation = %f' %(currentcol, currentbri, currentcolbri)) + print(' db $01, $%01X // Repeat 1 Scanline, Screen Brightness %d' %(currentbri, scanline)) + tempcol = 0 + tempbri = 0 + tempcolbri = 0.0 + for col in range(32): + for bri in range(16): + if colbri[(col*16)+bri] < currentcolbri and colbri[(col*16)+bri] > tempcolbri and col != currentcol and bri != currentbri: + tempcolbri = colbri[(col*16)+bri] + tempcol = col + tempbri = bri + currentcolbri = tempcolbri + currentcol = tempcol + currentbri = tempbri +print(' db $00 // End Of HDMA') + diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..490eb8fd --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "REDSPACE9BITHDMA DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.asm new file mode 100644 index 00000000..b0aba98f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.asm @@ -0,0 +1,498 @@ +// SNES Red Space 9-Bit HDMA Demo by krom (Peter Lemon): +// Uses Brightness Register For Extra Color Space (9-Bit) +arch snes.cpu +output "RedSpace9BitHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Load Red HDMA Gradient Backround Palette Color With DMA Channel 0 + lda.b #%00000011 // HMDA: Write 4 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGADD // $21: Start At Palette CGRAM Address ($2121) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #COLHDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + // Load HDMA Screen Display Brightness With DMA Channel 1 + lda.b #%00000000 // HMDA: Write 1 Byte Each Scanline + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_INIDISP // $00: Start At Display Control 1 ($2100) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #BRIHDMATable // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + + lda.b #%00000011 // HDMA Channel Select (Channel 0 & 1) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_TM // $212C: Main Screen Designation + +Loop: + jmp Loop + +COLHDMATable: + db $01; dw $0000, $001F // Repeat 1 Scanline, Palette Address 0, Gradient Color 0 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 1 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 2 + db $01; dw $0000, $001D // Repeat 1 Scanline, Palette Address 0, Gradient Color 3 + db $01; dw $0000, $001B // Repeat 1 Scanline, Palette Address 0, Gradient Color 4 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 5 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 6 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 7 + db $01; dw $0000, $001B // Repeat 1 Scanline, Palette Address 0, Gradient Color 8 + db $01; dw $0000, $0019 // Repeat 1 Scanline, Palette Address 0, Gradient Color 9 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 10 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 11 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 12 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 13 + db $01; dw $0000, $001B // Repeat 1 Scanline, Palette Address 0, Gradient Color 14 + db $01; dw $0000, $0019 // Repeat 1 Scanline, Palette Address 0, Gradient Color 15 + db $01; dw $0000, $0017 // Repeat 1 Scanline, Palette Address 0, Gradient Color 16 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 17 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 18 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 19 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 20 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 21 + db $01; dw $0000, $0019 // Repeat 1 Scanline, Palette Address 0, Gradient Color 22 + db $01; dw $0000, $0017 // Repeat 1 Scanline, Palette Address 0, Gradient Color 23 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 24 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 25 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 26 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 27 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 28 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 29 + db $01; dw $0000, $0019 // Repeat 1 Scanline, Palette Address 0, Gradient Color 30 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 31 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 32 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 33 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 34 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 35 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 36 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 37 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 38 + db $01; dw $0000, $0017 // Repeat 1 Scanline, Palette Address 0, Gradient Color 39 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 40 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 41 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 42 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 43 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 44 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 45 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 46 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 47 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 48 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 49 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 50 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 51 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 52 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 53 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 54 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 55 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 56 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 57 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 58 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 59 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 60 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 61 + db $01; dw $0000, $000F // Repeat 1 Scanline, Palette Address 0, Gradient Color 62 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 63 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 64 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 65 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 66 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 67 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 68 + db $01; dw $0000, $001A // Repeat 1 Scanline, Palette Address 0, Gradient Color 69 + db $01; dw $0000, $0015 // Repeat 1 Scanline, Palette Address 0, Gradient Color 70 + db $01; dw $0000, $000E // Repeat 1 Scanline, Palette Address 0, Gradient Color 71 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 72 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 73 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 74 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 75 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 76 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 77 + db $01; dw $0000, $000E // Repeat 1 Scanline, Palette Address 0, Gradient Color 78 + db $01; dw $0000, $000D // Repeat 1 Scanline, Palette Address 0, Gradient Color 79 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 80 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 81 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 82 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 83 + db $01; dw $0000, $000D // Repeat 1 Scanline, Palette Address 0, Gradient Color 84 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 85 + db $01; dw $0000, $000C // Repeat 1 Scanline, Palette Address 0, Gradient Color 86 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 87 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 88 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 89 + db $01; dw $0000, $0013 // Repeat 1 Scanline, Palette Address 0, Gradient Color 90 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 91 + db $01; dw $0000, $000D // Repeat 1 Scanline, Palette Address 0, Gradient Color 92 + db $01; dw $0000, $000C // Repeat 1 Scanline, Palette Address 0, Gradient Color 93 + db $01; dw $0000, $000B // Repeat 1 Scanline, Palette Address 0, Gradient Color 94 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 95 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 96 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 97 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 98 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 99 + db $01; dw $0000, $000C // Repeat 1 Scanline, Palette Address 0, Gradient Color 100 + db $01; dw $0000, $000B // Repeat 1 Scanline, Palette Address 0, Gradient Color 101 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 102 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 103 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 104 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 105 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 106 + db $01; dw $0000, $000C // Repeat 1 Scanline, Palette Address 0, Gradient Color 107 + db $01; dw $0000, $000B // Repeat 1 Scanline, Palette Address 0, Gradient Color 108 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 109 + db $01; dw $0000, $0011 // Repeat 1 Scanline, Palette Address 0, Gradient Color 110 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 111 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 112 + db $01; dw $0000, $000B // Repeat 1 Scanline, Palette Address 0, Gradient Color 113 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 114 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 115 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 116 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 117 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 118 + db $01; dw $0000, $0014 // Repeat 1 Scanline, Palette Address 0, Gradient Color 119 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 120 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 121 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 122 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 123 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 124 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 125 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 126 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 127 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 128 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 129 + db $01; dw $0000, $0007 // Repeat 1 Scanline, Palette Address 0, Gradient Color 130 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 131 + db $01; dw $0000, $0018 // Repeat 1 Scanline, Palette Address 0, Gradient Color 132 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 133 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 134 + db $01; dw $0000, $0007 // Repeat 1 Scanline, Palette Address 0, Gradient Color 135 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 136 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 137 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 138 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 139 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 140 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 141 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 142 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 143 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 144 + db $01; dw $0000, $0007 // Repeat 1 Scanline, Palette Address 0, Gradient Color 145 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 146 + db $01; dw $0000, $0009 // Repeat 1 Scanline, Palette Address 0, Gradient Color 147 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 148 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 149 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 150 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 151 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 152 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 153 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 154 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 155 + db $01; dw $0000, $0007 // Repeat 1 Scanline, Palette Address 0, Gradient Color 156 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 157 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 158 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 159 + db $01; dw $0000, $0008 // Repeat 1 Scanline, Palette Address 0, Gradient Color 160 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 161 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 162 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 163 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 164 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 165 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 166 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 167 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 168 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 169 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 170 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 171 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 172 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 173 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 174 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 175 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 176 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 177 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 178 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 179 + db $01; dw $0000, $0005 // Repeat 1 Scanline, Palette Address 0, Gradient Color 180 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 181 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 182 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 183 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 184 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 185 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 186 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 187 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 188 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 189 + db $01; dw $0000, $0003 // Repeat 1 Scanline, Palette Address 0, Gradient Color 190 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 191 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 192 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 193 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 194 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 195 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 196 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 197 + db $01; dw $0000, $001E // Repeat 1 Scanline, Palette Address 0, Gradient Color 198 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 199 + db $01; dw $0000, $001C // Repeat 1 Scanline, Palette Address 0, Gradient Color 200 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 201 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 202 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 203 + db $01; dw $0000, $0004 // Repeat 1 Scanline, Palette Address 0, Gradient Color 204 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 205 + db $01; dw $0000, $0016 // Repeat 1 Scanline, Palette Address 0, Gradient Color 206 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 207 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 208 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 209 + db $01; dw $0000, $0012 // Repeat 1 Scanline, Palette Address 0, Gradient Color 210 + db $01; dw $0000, $0001 // Repeat 1 Scanline, Palette Address 0, Gradient Color 211 + db $01; dw $0000, $0010 // Repeat 1 Scanline, Palette Address 0, Gradient Color 212 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 213 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 214 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 215 + db $01; dw $0000, $000C // Repeat 1 Scanline, Palette Address 0, Gradient Color 216 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 217 + db $01; dw $0000, $000A // Repeat 1 Scanline, Palette Address 0, Gradient Color 218 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 219 + db $01; dw $0000, $0002 // Repeat 1 Scanline, Palette Address 0, Gradient Color 220 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 221 + db $01; dw $0000, $0006 // Repeat 1 Scanline, Palette Address 0, Gradient Color 222 + db $01; dw $0000, $0000 // Repeat 1 Scanline, Palette Address 0, Gradient Color 223 + db $00 // End Of HDMA + +BRIHDMATable: + db $01, $F // Repeat 1 Scanline, Screen Brightness 0 + db $01, $E // Repeat 1 Scanline, Screen Brightness 1 + db $01, $F // Repeat 1 Scanline, Screen Brightness 2 + db $01, $E // Repeat 1 Scanline, Screen Brightness 3 + db $01, $F // Repeat 1 Scanline, Screen Brightness 4 + db $01, $E // Repeat 1 Scanline, Screen Brightness 5 + db $01, $D // Repeat 1 Scanline, Screen Brightness 6 + db $01, $F // Repeat 1 Scanline, Screen Brightness 7 + db $01, $E // Repeat 1 Scanline, Screen Brightness 8 + db $01, $F // Repeat 1 Scanline, Screen Brightness 9 + db $01, $D // Repeat 1 Scanline, Screen Brightness 10 + db $01, $E // Repeat 1 Scanline, Screen Brightness 11 + db $01, $C // Repeat 1 Scanline, Screen Brightness 12 + db $01, $F // Repeat 1 Scanline, Screen Brightness 13 + db $01, $D // Repeat 1 Scanline, Screen Brightness 14 + db $01, $E // Repeat 1 Scanline, Screen Brightness 15 + db $01, $F // Repeat 1 Scanline, Screen Brightness 16 + db $01, $D // Repeat 1 Scanline, Screen Brightness 17 + db $01, $C // Repeat 1 Scanline, Screen Brightness 18 + db $01, $E // Repeat 1 Scanline, Screen Brightness 19 + db $01, $B // Repeat 1 Scanline, Screen Brightness 20 + db $01, $F // Repeat 1 Scanline, Screen Brightness 21 + db $01, $D // Repeat 1 Scanline, Screen Brightness 22 + db $01, $E // Repeat 1 Scanline, Screen Brightness 23 + db $01, $F // Repeat 1 Scanline, Screen Brightness 24 + db $01, $C // Repeat 1 Scanline, Screen Brightness 25 + db $01, $D // Repeat 1 Scanline, Screen Brightness 26 + db $01, $B // Repeat 1 Scanline, Screen Brightness 27 + db $01, $E // Repeat 1 Scanline, Screen Brightness 28 + db $01, $A // Repeat 1 Scanline, Screen Brightness 29 + db $01, $C // Repeat 1 Scanline, Screen Brightness 30 + db $01, $F // Repeat 1 Scanline, Screen Brightness 31 + db $01, $E // Repeat 1 Scanline, Screen Brightness 32 + db $01, $C // Repeat 1 Scanline, Screen Brightness 33 + db $01, $B // Repeat 1 Scanline, Screen Brightness 34 + db $01, $D // Repeat 1 Scanline, Screen Brightness 35 + db $01, $F // Repeat 1 Scanline, Screen Brightness 36 + db $01, $A // Repeat 1 Scanline, Screen Brightness 37 + db $01, $E // Repeat 1 Scanline, Screen Brightness 38 + db $01, $C // Repeat 1 Scanline, Screen Brightness 39 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 40 + db $01, $D // Repeat 1 Scanline, Screen Brightness 41 + db $01, $F // Repeat 1 Scanline, Screen Brightness 42 + db $01, $E // Repeat 1 Scanline, Screen Brightness 43 + db $01, $C // Repeat 1 Scanline, Screen Brightness 44 + db $01, $A // Repeat 1 Scanline, Screen Brightness 45 + db $01, $D // Repeat 1 Scanline, Screen Brightness 46 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 47 + db $01, $F // Repeat 1 Scanline, Screen Brightness 48 + db $01, $C // Repeat 1 Scanline, Screen Brightness 49 + db $01, $E // Repeat 1 Scanline, Screen Brightness 50 + db $01, $D // Repeat 1 Scanline, Screen Brightness 51 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 52 + db $01, $B // Repeat 1 Scanline, Screen Brightness 53 + db $01, $A // Repeat 1 Scanline, Screen Brightness 54 + db $01, $C // Repeat 1 Scanline, Screen Brightness 55 + db $01, $F // Repeat 1 Scanline, Screen Brightness 56 + db $01, $E // Repeat 1 Scanline, Screen Brightness 57 + db $01, $D // Repeat 1 Scanline, Screen Brightness 58 + db $01, $B // Repeat 1 Scanline, Screen Brightness 59 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 60 + db $01, $C // Repeat 1 Scanline, Screen Brightness 61 + db $01, $F // Repeat 1 Scanline, Screen Brightness 62 + db $01, $E // Repeat 1 Scanline, Screen Brightness 63 + db $01, $A // Repeat 1 Scanline, Screen Brightness 64 + db $01, $D // Repeat 1 Scanline, Screen Brightness 65 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 66 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 67 + db $01, $C // Repeat 1 Scanline, Screen Brightness 68 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 69 + db $01, $A // Repeat 1 Scanline, Screen Brightness 70 + db $01, $F // Repeat 1 Scanline, Screen Brightness 71 + db $01, $D // Repeat 1 Scanline, Screen Brightness 72 + db $01, $C // Repeat 1 Scanline, Screen Brightness 73 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 74 + db $01, $A // Repeat 1 Scanline, Screen Brightness 75 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 76 + db $01, $B // Repeat 1 Scanline, Screen Brightness 77 + db $01, $E // Repeat 1 Scanline, Screen Brightness 78 + db $01, $F // Repeat 1 Scanline, Screen Brightness 79 + db $01, $C // Repeat 1 Scanline, Screen Brightness 80 + db $01, $A // Repeat 1 Scanline, Screen Brightness 81 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 82 + db $01, $B // Repeat 1 Scanline, Screen Brightness 83 + db $01, $E // Repeat 1 Scanline, Screen Brightness 84 + db $01, $A // Repeat 1 Scanline, Screen Brightness 85 + db $01, $F // Repeat 1 Scanline, Screen Brightness 86 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 87 + db $01, $B // Repeat 1 Scanline, Screen Brightness 88 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 89 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 90 + db $01, $A // Repeat 1 Scanline, Screen Brightness 91 + db $01, $D // Repeat 1 Scanline, Screen Brightness 92 + db $01, $E // Repeat 1 Scanline, Screen Brightness 93 + db $01, $F // Repeat 1 Scanline, Screen Brightness 94 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 95 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 96 + db $01, $A // Repeat 1 Scanline, Screen Brightness 97 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 98 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 99 + db $01, $D // Repeat 1 Scanline, Screen Brightness 100 + db $01, $E // Repeat 1 Scanline, Screen Brightness 101 + db $01, $F // Repeat 1 Scanline, Screen Brightness 102 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 103 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 104 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 105 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 106 + db $01, $C // Repeat 1 Scanline, Screen Brightness 107 + db $01, $D // Repeat 1 Scanline, Screen Brightness 108 + db $01, $E // Repeat 1 Scanline, Screen Brightness 109 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 110 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 111 + db $01, $F // Repeat 1 Scanline, Screen Brightness 112 + db $01, $C // Repeat 1 Scanline, Screen Brightness 113 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 114 + db $01, $D // Repeat 1 Scanline, Screen Brightness 115 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 116 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 117 + db $01, $E // Repeat 1 Scanline, Screen Brightness 118 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 119 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 120 + db $01, $F // Repeat 1 Scanline, Screen Brightness 121 + db $01, $C // Repeat 1 Scanline, Screen Brightness 122 + db $01, $D // Repeat 1 Scanline, Screen Brightness 123 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 124 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 125 + db $01, $E // Repeat 1 Scanline, Screen Brightness 126 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 127 + db $01, $B // Repeat 1 Scanline, Screen Brightness 128 + db $01, $C // Repeat 1 Scanline, Screen Brightness 129 + db $01, $F // Repeat 1 Scanline, Screen Brightness 130 + db $01, $D // Repeat 1 Scanline, Screen Brightness 131 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 132 + db $01, $3 // Repeat 1 Scanline, Screen Brightness 133 + db $01, $A // Repeat 1 Scanline, Screen Brightness 134 + db $01, $E // Repeat 1 Scanline, Screen Brightness 135 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 136 + db $01, $C // Repeat 1 Scanline, Screen Brightness 137 + db $01, $3 // Repeat 1 Scanline, Screen Brightness 138 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 139 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 140 + db $01, $F // Repeat 1 Scanline, Screen Brightness 141 + db $01, $A // Repeat 1 Scanline, Screen Brightness 142 + db $01, $B // Repeat 1 Scanline, Screen Brightness 143 + db $01, $E // Repeat 1 Scanline, Screen Brightness 144 + db $01, $C // Repeat 1 Scanline, Screen Brightness 145 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 146 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 147 + db $01, $A // Repeat 1 Scanline, Screen Brightness 148 + db $01, $D // Repeat 1 Scanline, Screen Brightness 149 + db $01, $F // Repeat 1 Scanline, Screen Brightness 150 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 151 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 152 + db $01, $3 // Repeat 1 Scanline, Screen Brightness 153 + db $01, $C // Repeat 1 Scanline, Screen Brightness 154 + db $01, $E // Repeat 1 Scanline, Screen Brightness 155 + db $01, $A // Repeat 1 Scanline, Screen Brightness 156 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 157 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 158 + db $01, $D // Repeat 1 Scanline, Screen Brightness 159 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 160 + db $01, $F // Repeat 1 Scanline, Screen Brightness 161 + db $01, $C // Repeat 1 Scanline, Screen Brightness 162 + db $01, $A // Repeat 1 Scanline, Screen Brightness 163 + db $01, $3 // Repeat 1 Scanline, Screen Brightness 164 + db $01, $E // Repeat 1 Scanline, Screen Brightness 165 + db $01, $B // Repeat 1 Scanline, Screen Brightness 166 + db $01, $D // Repeat 1 Scanline, Screen Brightness 167 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 168 + db $01, $3 // Repeat 1 Scanline, Screen Brightness 169 + db $01, $A // Repeat 1 Scanline, Screen Brightness 170 + db $01, $C // Repeat 1 Scanline, Screen Brightness 171 + db $01, $F // Repeat 1 Scanline, Screen Brightness 172 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 173 + db $01, $1 // Repeat 1 Scanline, Screen Brightness 174 + db $01, $E // Repeat 1 Scanline, Screen Brightness 175 + db $01, $1 // Repeat 1 Scanline, Screen Brightness 176 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 177 + db $01, $D // Repeat 1 Scanline, Screen Brightness 178 + db $01, $A // Repeat 1 Scanline, Screen Brightness 179 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 180 + db $01, $C // Repeat 1 Scanline, Screen Brightness 181 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 182 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 183 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 184 + db $01, $F // Repeat 1 Scanline, Screen Brightness 185 + db $01, $1 // Repeat 1 Scanline, Screen Brightness 186 + db $01, $E // Repeat 1 Scanline, Screen Brightness 187 + db $01, $A // Repeat 1 Scanline, Screen Brightness 188 + db $01, $D // Repeat 1 Scanline, Screen Brightness 189 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 190 + db $01, $C // Repeat 1 Scanline, Screen Brightness 191 + db $01, $1 // Repeat 1 Scanline, Screen Brightness 192 + db $01, $B // Repeat 1 Scanline, Screen Brightness 193 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 194 + db $01, $1 // Repeat 1 Scanline, Screen Brightness 195 + db $01, $A // Repeat 1 Scanline, Screen Brightness 196 + db $01, $F // Repeat 1 Scanline, Screen Brightness 197 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 198 + db $01, $E // Repeat 1 Scanline, Screen Brightness 199 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 200 + db $01, $D // Repeat 1 Scanline, Screen Brightness 201 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 202 + db $01, $C // Repeat 1 Scanline, Screen Brightness 203 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 204 + db $01, $B // Repeat 1 Scanline, Screen Brightness 205 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 206 + db $01, $A // Repeat 1 Scanline, Screen Brightness 207 + db $01, $6 // Repeat 1 Scanline, Screen Brightness 208 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 209 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 210 + db $01, $8 // Repeat 1 Scanline, Screen Brightness 211 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 212 + db $01, $F // Repeat 1 Scanline, Screen Brightness 213 + db $01, $4 // Repeat 1 Scanline, Screen Brightness 214 + db $01, $D // Repeat 1 Scanline, Screen Brightness 215 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 216 + db $01, $B // Repeat 1 Scanline, Screen Brightness 217 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 218 + db $01, $9 // Repeat 1 Scanline, Screen Brightness 219 + db $01, $2 // Repeat 1 Scanline, Screen Brightness 220 + db $01, $7 // Repeat 1 Scanline, Screen Brightness 221 + db $01, $0 // Repeat 1 Scanline, Screen Brightness 222 + db $01, $5 // Repeat 1 Scanline, Screen Brightness 223 + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.png b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.png new file mode 100644 index 00000000..a0f298c9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.sfc new file mode 100644 index 00000000..5407723f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMAColEmu.png b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMAColEmu.png new file mode 100644 index 00000000..854f6fc2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMAColEmu.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/make.bat new file mode 100644 index 00000000..45c9755d --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/make.bat @@ -0,0 +1 @@ +bass RedSpace9BitHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4a002110 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "RED SPACE HDMA DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.asm new file mode 100644 index 00000000..b6453c09 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.asm @@ -0,0 +1,70 @@ +// SNES Red Space HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "RedSpaceHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Load Red HDMA Gradient Backround Palette Color + lda.b #%00000011 // HMDA: Write 4 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGADD // $21: Start At Palette CGRAM Address ($2121) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_TM // $212C: Main Screen Designation + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + +Loop: + jmp Loop + +HDMATable: + db $07; dw $0000, $001F // Repeat 7 Scanlines, Palette Address 0, Gradient Color0 + db $07; dw $0000, $001E // Repeat 7 Scanlines, Palette Address 0, Gradient Color1 + db $07; dw $0000, $001D // Repeat 7 Scanlines, Palette Address 0, Gradient Color2 + db $07; dw $0000, $001C // Repeat 7 Scanlines, Palette Address 0, Gradient Color3 + db $07; dw $0000, $001B // Repeat 7 Scanlines, Palette Address 0, Gradient Color4 + db $07; dw $0000, $001A // Repeat 7 Scanlines, Palette Address 0, Gradient Color5 + db $07; dw $0000, $0019 // Repeat 7 Scanlines, Palette Address 0, Gradient Color6 + db $07; dw $0000, $0018 // Repeat 7 Scanlines, Palette Address 0, Gradient Color7 + db $07; dw $0000, $0017 // Repeat 7 Scanlines, Palette Address 0, Gradient Color8 + db $07; dw $0000, $0016 // Repeat 7 Scanlines, Palette Address 0, Gradient Color9 + db $07; dw $0000, $0015 // Repeat 7 Scanlines, Palette Address 0, Gradient Color10 + db $07; dw $0000, $0014 // Repeat 7 Scanlines, Palette Address 0, Gradient Color11 + db $07; dw $0000, $0013 // Repeat 7 Scanlines, Palette Address 0, Gradient Color12 + db $07; dw $0000, $0012 // Repeat 7 Scanlines, Palette Address 0, Gradient Color13 + db $07; dw $0000, $0011 // Repeat 7 Scanlines, Palette Address 0, Gradient Color14 + db $07; dw $0000, $0010 // Repeat 7 Scanlines, Palette Address 0, Gradient Color15 + db $07; dw $0000, $000F // Repeat 7 Scanlines, Palette Address 0, Gradient Color16 + db $07; dw $0000, $000E // Repeat 7 Scanlines, Palette Address 0, Gradient Color17 + db $07; dw $0000, $000D // Repeat 7 Scanlines, Palette Address 0, Gradient Color18 + db $07; dw $0000, $000C // Repeat 7 Scanlines, Palette Address 0, Gradient Color19 + db $07; dw $0000, $000B // Repeat 7 Scanlines, Palette Address 0, Gradient Color20 + db $07; dw $0000, $000A // Repeat 7 Scanlines, Palette Address 0, Gradient Color21 + db $07; dw $0000, $0009 // Repeat 7 Scanlines, Palette Address 0, Gradient Color22 + db $07; dw $0000, $0008 // Repeat 7 Scanlines, Palette Address 0, Gradient Color23 + db $07; dw $0000, $0007 // Repeat 7 Scanlines, Palette Address 0, Gradient Color24 + db $07; dw $0000, $0006 // Repeat 7 Scanlines, Palette Address 0, Gradient Color25 + db $07; dw $0000, $0005 // Repeat 7 Scanlines, Palette Address 0, Gradient Color26 + db $07; dw $0000, $0004 // Repeat 7 Scanlines, Palette Address 0, Gradient Color27 + db $07; dw $0000, $0003 // Repeat 7 Scanlines, Palette Address 0, Gradient Color28 + db $07; dw $0000, $0002 // Repeat 7 Scanlines, Palette Address 0, Gradient Color29 + db $07; dw $0000, $0001 // Repeat 7 Scanlines, Palette Address 0, Gradient Color30 + db $07; dw $0000, $0000 // Repeat 7 Scanlines, Palette Address 0, Gradient Color31 + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.sfc new file mode 100644 index 00000000..6ca050cd Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedspaceHDMA.png b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedspaceHDMA.png new file mode 100644 index 00000000..2e80f01a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedspaceHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/make.bat new file mode 100644 index 00000000..1001fbde --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/make.bat @@ -0,0 +1 @@ +bass RedSpaceHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9ca527f6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "REDSPACE INDIRECTHDMA" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.asm new file mode 100644 index 00000000..6e2df49c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.asm @@ -0,0 +1,204 @@ +// SNES Red Space Indirect HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "RedSpaceIndirectHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +HDMAIndirectData: + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + dw 0, 0 // Palette Address, Gradient Color + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + // Fill HDMAIndirectData + lda.b #$1F // Gradient Color0 + sta.b HDMAIndirectData+2 + + lda.b #$1E // Gradient Color1 + sta.b HDMAIndirectData+6 + + lda.b #$1D // Gradient Color2 + sta.b HDMAIndirectData+10 + + lda.b #$1C // Gradient Color3 + sta.b HDMAIndirectData+14 + + lda.b #$1B // Gradient Color4 + sta.b HDMAIndirectData+18 + + lda.b #$1A // Gradient Color5 + sta.b HDMAIndirectData+22 + + lda.b #$19 // Gradient Color6 + sta.b HDMAIndirectData+26 + + lda.b #$18 // Gradient Color7 + sta.b HDMAIndirectData+30 + + lda.b #$17 // Gradient Color8 + sta.b HDMAIndirectData+34 + + lda.b #$16 // Gradient Color9 + sta.b HDMAIndirectData+38 + + lda.b #$15 // Gradient Color10 + sta.b HDMAIndirectData+42 + + lda.b #$14 // Gradient Color11 + sta.b HDMAIndirectData+46 + + lda.b #$13 // Gradient Color12 + sta.b HDMAIndirectData+50 + + lda.b #$12 // Gradient Color13 + sta.b HDMAIndirectData+54 + + lda.b #$11 // Gradient Color14 + sta.b HDMAIndirectData+58 + + lda.b #$10 // Gradient Color15 + sta.b HDMAIndirectData+62 + + lda.b #$0F // Gradient Color16 + sta.b HDMAIndirectData+66 + + lda.b #$0E // Gradient Color17 + sta.b HDMAIndirectData+70 + + lda.b #$0D // Gradient Color18 + sta.b HDMAIndirectData+74 + + lda.b #$0C // Gradient Color19 + sta.b HDMAIndirectData+78 + + lda.b #$0B // Gradient Color20 + sta.b HDMAIndirectData+82 + + lda.b #$0A // Gradient Color21 + sta.b HDMAIndirectData+86 + + lda.b #$09 // Gradient Color22 + sta.b HDMAIndirectData+90 + + lda.b #$08 // Gradient Color23 + sta.b HDMAIndirectData+94 + + lda.b #$07 // Gradient Color24 + sta.b HDMAIndirectData+98 + + lda.b #$06 // Gradient Color25 + sta.b HDMAIndirectData+102 + + lda.b #$05 // Gradient Color26 + sta.b HDMAIndirectData+106 + + lda.b #$04 // Gradient Color27 + sta.b HDMAIndirectData+110 + + lda.b #$03 // Gradient Color28 + sta.b HDMAIndirectData+114 + + lda.b #$02 // Gradient Color29 + sta.b HDMAIndirectData+118 + + lda.b #$01 // Gradient Color30 + sta.b HDMAIndirectData+122 + + lda.b #$00 // Gradient Color31 + sta.b HDMAIndirectData+126 + + // Load Red HDMA Gradient Backround Palette Color + lda.b #%01000011 // HMDA: Write 4 Bytes Each Scanline, Repeat A/B-bus Address Twice, Indirect HDMA + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_CGADD // $21: Start At Palette CGRAM Address ($2121) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + sta.w REG_DASB0 // $4307: DMA0 Indirect HDMA Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_TM // $212C: Main Screen Designation + + lda.b #$F // Turn On Screen, Maximum Brightness + sta.w REG_INIDISP // $2100: Screen Display + +Loop: + jmp Loop + +HDMATable: + db $07; dw HDMAIndirectData // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+4 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+8 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+12 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+16 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+20 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+24 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+28 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+32 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+36 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+40 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+44 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+48 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+52 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+56 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+60 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+64 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+68 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+72 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+76 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+80 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+84 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+88 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+92 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+96 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+100 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+104 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+108 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+112 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+116 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+120 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $07; dw HDMAIndirectData+124 // Repeat 7 Scanlines, HDMA Indirect Data Address + db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.sfc new file mode 100644 index 00000000..3be6a0c4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedspaceIndirectHDMA.png b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedspaceIndirectHDMA.png new file mode 100644 index 00000000..2e80f01a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedspaceIndirectHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/make.bat new file mode 100644 index 00000000..fb906497 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/make.bat @@ -0,0 +1 @@ +bass RedSpaceIndirectHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.map new file mode 100644 index 00000000..e6d55e4f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pal new file mode 100644 index 00000000..0a6c09bc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pic new file mode 100644 index 00000000..4ee05358 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..3075d4bb --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "WAVE HDMA " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/SineCalc/SineCalc.py b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/SineCalc/SineCalc.py new file mode 100644 index 00000000..189ee5e5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/SineCalc/SineCalc.py @@ -0,0 +1,7 @@ +from math import sin + +i = 0.0 +while i < 224: + sinval = round(sin(i) * 10) + i += 0.25 + print("db 1; dw", sinval) diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.asm b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.asm new file mode 100644 index 00000000..2f3b7408 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.asm @@ -0,0 +1,972 @@ +// SNES Wave HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "WaveHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGTiles, $0000, $8000, 0) // Load Background Tiles To VRAM + LoadVRAM(BGTiles + $10000, $8000, $6040, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, BGMap.size, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + // Load HDMA Table + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_BG1HOFS // $0D: Start At BG1 Horizontal Scroll (X) ($210D) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + FadeIN() // Screen Fade In + +ldx.w #HDMATable +Loop: + WaitNMI() // Wait VBlank + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + inx + inx + inx + cpx.w #HDMATable + (672 * 3) + bne SkipLoop + ldx.w #HDMATable + SkipLoop: + jmp Loop + +HDMATable: +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 4 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -3 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 6 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 6 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -2 +db 1; dw 0 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -6 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 3 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -4 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -4 +db 1; dw -2 +db 1; dw 0 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 3 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -2 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -6 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 6 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 6 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -2 +db 1; dw 0 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -6 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 3 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -4 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -4 +db 1; dw -2 +db 1; dw 0 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 3 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -7 +db 1; dw -5 +db 1; dw -2 +db 1; dw 0 +db 1; dw 3 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 1 +db 1; dw -1 +db 1; dw -4 +db 1; dw -6 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw 0 +db 1; dw 2 +db 1; dw 5 +db 1; dw 7 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw -1 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -5 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 6 +db 1; dw 4 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -7 +db 1; dw -6 +db 1; dw -3 +db 1; dw -1 +db 1; dw 2 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 8 +db 1; dw 7 +db 1; dw 5 +db 1; dw 2 +db 1; dw 0 +db 1; dw -3 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -10 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -1 +db 1; dw 1 +db 1; dw 4 +db 1; dw 6 +db 1; dw 8 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 0 +db 1; dw -2 +db 1; dw -5 +db 1; dw -7 +db 1; dw -8 +db 1; dw -9 +db 1; dw -10 +db 1; dw -10 +db 1; dw -9 +db 1; dw -8 +db 1; dw -6 +db 1; dw -4 +db 1; dw -2 +db 1; dw 1 +db 1; dw 3 +db 1; dw 6 +db 1; dw 7 +db 1; dw 9 +db 1; dw 10 +db 1; dw 10 +db 1; dw 10 +db 1; dw 9 +db 1; dw 7 +db 1; dw 5 +db 1; dw 3 +db 1; dw 1 +db 1; dw -2 +db 1; dw -4 +db 1; dw -6 + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (2048 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (57408 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.png b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.png new file mode 100644 index 00000000..b81d94c0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.sfc new file mode 100644 index 00000000..e25dfe57 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/make.bat new file mode 100644 index 00000000..3c68eefe --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/make.bat @@ -0,0 +1 @@ +bass WaveHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/GFX/BG.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/GFX/BG.asm new file mode 100644 index 00000000..e31bb194 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/GFX/BG.asm @@ -0,0 +1,2698 @@ +BGPal: // BG Palette Data ($20 Bytes) + dw $0000, $7FFF, $0000, $0000, $0000, $0000, $0000, $0000 + dw $0000, $0000, $0000, $0000, $0000, $0000, $0000, $0000 + +BGTiles: // BG Tile Data ($1640 Bytes) ($20 Bytes Per Tile / $40 Bytes Per Half) + //========================= + // ASCii SNES Font (16x16) + //========================= + + // $20 - Space " " (Upper & Lower Half $00) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $21 - Exclamation mark "!" (Upper Half $02) + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $21 - Exclamation mark "!" (Lower Half $04) + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $22 - Quotation mark """ (Upper Half $06) + db %00000010, %00000000 + db %00001100, %00000000 + db %00011100, %00000000 + db %00111110, %00000000 + db %00111110, %00000000 + db %00111110, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000100, %00000000 + db %00011000, %00000000 + db %00111000, %00000000 + db %01111100, %00000000 + db %01111100, %00000000 + db %01111100, %00000000 + db %00111000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $23 - Cross hatch "#" (Upper & Lower Half $08) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00011111, %00000000 + db %00111111, %00000000 + db %00011111, %00000000 + db %00000110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00110000, %00000000 + db %00110000, %00000000 + db %11111000, %00000000 + db %11111100, %00000000 + db %11111000, %00000000 + db %01100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $24 - Dollar sign "$" (Upper & Lower Half $0A) + db %00000000, %00000000 + db %00000011, %00000000 + db %00001111, %00000000 + db %00011111, %00000000 + db %00011101, %00000000 + db %00011101, %00000000 + db %00011111, %00000000 + db %00001111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11000000, %00000000 + db %11110000, %00000000 + db %11111000, %00000000 + db %10111000, %00000000 + db %10010000, %00000000 + db %10000000, %00000000 + db %11110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $25 - Percent sign "%" (Upper & Lower Half $0C) + db %00000000, %00000000 + db %00111100, %00000000 + db %01111110, %00000000 + db %01100110, %00000000 + db %01100110, %00000000 + db %01111110, %00000000 + db %00111100, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00001110, %00000000 + db %00011100, %00000000 + db %00111000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $26 - Ampersand "&" (Upper Half $0E) + db %00000000, %00000000 + db %00000111, %00000000 + db %00001111, %00000000 + db %00011111, %00000000 + db %00011000, %00000000 + db %00011000, %00000000 + db %00011101, %00000000 + db %00001111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $26 - Ampersand "&" (Lower Half $10) + db %00011111, %00000000 + db %00011111, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %11011100, %00000000 + db %11111000, %00000000 + db %01110000, %00000000 + db %11110000, %00000000 + db %11111000, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $27 - Closing single quote "'" (Upper Half $12) + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $28 - Opening parentheses "(" (Upper & Lower $14) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00011000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2A - Asterisk "*" (Upper Half $16) + db %00000000, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00111111, %00000000 + db %00011111, %00000000 + db %00001111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11111100, %00000000 + db %11111000, %00000000 + db %11110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2A - Asterisk "*" (Lower Half $18) + db %00000111, %00000000 + db %00000111, %00000000 + db %00001111, %00000000 + db %00001110, %00000000 + db %00011000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %11100000, %00000000 + db %11110000, %00000000 + db %01110000, %00000000 + db %00011000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2B - Plus "+" (Upper & Lower Half $1A) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %11111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2C - Comma "," (Lower Half $1C) + db %00000000, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2D - Hyphen "-" (Upper & Lower Half $1E) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2E - Period "." (Lower Half $20) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $2F - Forward slash "/" (Upper & Lower Half $22) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + db %00011100, %00000000 + db %00111000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $30 - 0 (Upper & Lower Half $24) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011100, %00000000 + db %00011000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %00111000, %00000000 + db %00011000, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $31 - 1 (Upper Half $26) + db %00000000, %00000000 + db %00000011, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $31 - 1 (Lower Half $28) + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11111000, %00000000 + db %11111000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $32 - 2 (Upper Half $2A) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $32 - 2 (Lower Half $2C) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + db %00001111, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $33 - 3 (Upper & Lower Half $2E) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $34 - 4 (Upper Half $30) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00110000, %00000000 + db %01110000, %00000000 + db %11110000, %00000000 + db %11110000, %00000000 + db %11110000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $34 - 4 (Lower Half $32) + db %00011100, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %01110000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $35 - 5 (Upper Half $34) + db %00000000, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11111000, %00000000 + db %11111000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $35 - 5 (Lower Half $36) + db %00011111, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $36 - 6 (Upper Half $38) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + db %00011110, %00000000 + db %00011111, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $36 - 6 (Lower Half $3A) + db %00111111, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $37 - 7 (Upper Half $3C) + db %00000000, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11111000, %00000000 + db %11111000, %00000000 + db %00111000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $37 - 7 (Lower Half $3E) + db %00000001, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $38 - 8 (Upper & Lower Half $40) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $3C - Less than sign "<" (Upper & Lower Half $42) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $3D - Equals sign "=" (Upper & Lower Half $44) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $3F - Question mark "?" (Upper Half $46) + db %00000011, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + db %00001100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11000000, %00000000 + db %11100000, %00000000 + db %01110000, %00000000 + db %00110000, %00000000 + db %00110000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $40 - At sign "@" (Upper Half $48) + db %00000000, %00000000 + db %00000011, %00000000 + db %00001111, %00000000 + db %00011111, %00000000 + db %00111000, %00000000 + db %00110001, %00000000 + db %01100011, %00000000 + db %01100110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11000000, %00000000 + db %11110000, %00000000 + db %11111000, %00000000 + db %0011100, %00000000 + db %11101100, %00000000 + db %11100110, %00000000 + db %01100110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $40 - At sign "@" (Lower Half $4A) + db %01100110, %00000000 + db %01100110, %00000000 + db %00110110, %00000000 + db %00110001, %00000000 + db %00011100, %00000000 + db %00001111, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %01100110, %00000000 + db %01100110, %00000000 + db %01101100, %00000000 + db %10111000, %00000000 + db %00000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $41 - A (Upper Half $4C) + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00001111, %00000000 + db %00001111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11100000, %00000000 + db %11100000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $41 - A (Lower Half $4E) + db %00011110, %00000000 + db %00011111, %00000000 + db %00111111, %00000000 + db %00111100, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %01110000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111000, %00000000 + db %11111000, %00000000 + db %11111100, %00000000 + db %00011100, %00000000 + db %00001110, %00000000 + db %00001110, %00000000 + db %00000110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $42 - B (Upper & Lower Half $50) + db %00000000, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $43 - C (Upper & Lower Half $52) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111110, %00000000 + db %00111000, %00000000 + db %01111000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $44 - D (Upper & Lower Half $54) + db %00000000, %00000000 + db %01111111, %00000000 + db %01111111, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00011110, %00000000 + db %00001110, %00000000 + db %00001110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $45 - E (Upper & Lower Half $56) + db %00000000, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $46 - F (Lower Half $58) + db %00111111, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $47 - G (Lower Half $5A) + db %01110000, %00000000 + db %01110000, %00000000 + db %01111000, %00000000 + db %00111000, %00000000 + db %00111110, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11111100, %00000000 + db %11111100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $48 - H (Upper & Lower Half $5C) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %11111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $49 - I (Upper & Lower Half $5E) + db %00000000, %00000000 + db %00001111, %00000000 + db %00001111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11110000, %00000000 + db %11110000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4A - J (Lower Half $60) + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00111011, %00000000 + db %00111111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4B - K (Upper & Lower Half $62) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111101, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %01111000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4C - L (Upper Half $64) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4C - L (Lower Half $66) + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4D - M (Upper Half $68) + db %00000000, %00000000 + db %01111000, %00000000 + db %01111100, %00000000 + db %01111100, %00000000 + db %01111110, %00000000 + db %01111110, %00000000 + db %01111111, %00000000 + db %01111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011110, %00000000 + db %00111110, %00000000 + db %00111110, %00000000 + db %01111110, %00000000 + db %01111110, %00000000 + db %11111110, %00000000 + db %11111110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4D - M (Lower Half $6A) + db %01111111, %00000000 + db %01111111, %00000000 + db %01111011, %00000000 + db %01111001, %00000000 + db %01111001, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11111110, %00000000 + db %11111110, %00000000 + db %11011110, %00000000 + db %10011110, %00000000 + db %10011110, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4E - N (Upper & Lower Half $6C) + db %00000000, %00000000 + db %01110000, %00000000 + db %01111000, %00000000 + db %01111100, %00000000 + db %01111110, %00000000 + db %01111111, %00000000 + db %01111111, %00000000 + db %01111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %10011110, %00000000 + db %11011110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $4F - O (Upper & Lower Half $6E) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111110, %00000000 + db %00111000, %00000000 + db %01111000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %01111100, %00000000 + db %00011100, %00000000 + db %00011110, %00000000 + db %00001110, %00000000 + db %00001110, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $51 - Q (Lower Half $70) + db %01110000, %00000000 + db %01110000, %00000000 + db %01111001, %00000000 + db %00111000, %00000000 + db %00111110, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00001110, %00000000 + db %11001110, %00000000 + db %11111110, %00000000 + db %01111100, %00000000 + db %01111100, %00000000 + db %11111110, %00000000 + db %11100110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $52 - R (Lower Half $72) + db %00111111, %00000000 + db %00111111, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %11110000, %00000000 + db %01110000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $53 - S (Upper & Lower Half $74) + db %00000000, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11100000, %00000000 + db %11111000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $54 - T (Upper Half $76) + db %00000000, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $54 - T (Lower Half $78) + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $55 - U (Upper Half $7A) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $55 - U (Lower Half $7C) + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111110, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $56 - V (Upper Half $7E) + db %00000000, %00000000 + db %01111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00001111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00011110, %00000000 + db %00011100, %00000000 + db %00011100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %01110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $56 - V (Lower Half $80) + db %00001111, %00000000 + db %00001111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %01110000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11100000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $58 - X (Upper & Lower Half $82) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00001111, %00000000 + db %00001111, %00000000 + db %00000111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %01111000, %00000000 + db %01111000, %00000000 + db %11110000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $59 - Y (Lower Half $84) + db %00000111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $5A - Z (Upper & Lower Half $86) + db %00000000, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %01111100, %00000000 + db %11111000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $5B - Opening square bracket "[" (Upper & Lower Half $88) + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %11100000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $5E - Caret "^" (Upper Half $8A) + db %00000001, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00001110, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %11000000, %00000000 + db %11100000, %00000000 + db %01110000, %00000000 + db %00111000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $5F - Underscore "_" (Lower Half $8C) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11111111, %00000000 + db %11111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $60 - Opening single quote "`" (Upper Half $8E) + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000001, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $61 - a (Upper Half $90) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11110000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $65 - e (Lower Half $92) + db %00011111, %00000000 + db %00111100, %00000000 + db %00111111, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11111000, %00000000 + db %00111100, %00000000 + db %11111100, %00000000 + db %00000000, %00000000 + db %00111100, %00000000 + db %11111000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $66 - f (Lower Half $94) + db %00001111, %00000000 + db %00001111, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11110000, %00000000 + db %11110000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $67 - g (Upper Half $96) + db %00111100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %00111100, %00000000 + db %00011111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %01111100, %00000000 + db %11111100, %00000000 + db %11111100, %00000000 + db %00111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $67 - g (Lower Half $98) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111000, %00000000 + db %00111111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111000, %00000000 + db %01111000, %00000000 + db %11110000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $69 - i (Upper Half $9A) + db %00000000, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000011, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %11000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $6B - k (Upper Half $9C) + db %00000000, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111100, %00000000 + db %00111101, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %01110000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $6D - m (Upper Half $9E) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00111100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $6D - m (Lower Half $A0) + db %01111111, %00000000 + db %01111111, %00000000 + db %01111001, %00000000 + db %01111001, %00000000 + db %01111001, %00000000 + db %01111001, %00000000 + db %01111001, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %01111110, %00000000 + db %11111110, %00000000 + db %11001110, %00000000 + db %11001110, %00000000 + db %11001110, %00000000 + db %11001110, %00000000 + db %11001110, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $73 - s (Lower Half $A2) + db %00011100, %00000000 + db %00011000, %00000000 + db %00001111, %00000000 + db %00000011, %00000000 + db %00111000, %00000000 + db %00111110, %00000000 + db %00001111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111000, %00000000 + db %00011100, %00000000 + db %10000000, %00000000 + db %11110000, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %11111000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $76 - v (Lower Half $A4) + db %00111100, %00000000 + db %00011110, %00000000 + db %00011110, %00000000 + db %00001111, %00000000 + db %00001111, %00000000 + db %00000111, %00000000 + db %00000111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00011100, %00000000 + db %00111000, %00000000 + db %00111000, %00000000 + db %01110000, %00000000 + db %01110000, %00000000 + db %11100000, %00000000 + db %11100000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $77 - w (Lower Half $A6) + db %00111100, %00000000 + db %00111100, %00000000 + db %00111101, %00000000 + db %00111111, %00000000 + db %00111111, %00000000 + db %00111110, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00011100, %00000000 + db %10011100, %00000000 + db %11011100, %00000000 + db %11111100, %00000000 + db %01111100, %00000000 + db %00111100, %00000000 + db %00011100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $78 - x (Lower Half $A8) + db %00111100, %00000000 + db %00011110, %00000000 + db %00001111, %00000000 + db %00000111, %00000000 + db %00001111, %00000000 + db %00011110, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00111100, %00000000 + db %01111000, %00000000 + db %11110000, %00000000 + db %11100000, %00000000 + db %11110000, %00000000 + db %01111000, %00000000 + db %00111100, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $7A - z (Lower Half $AA) + db %00000111, %00000000 + db %00000000, %00000000 + db %00000001, %00000000 + db %00000011, %00000000 + db %00000111, %00000000 + db %00011111, %00000000 + db %00011111, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11110000, %00000000 + db %11100000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %00000000, %00000000 + db %11111000, %00000000 + db %11111000, %00000000 + db %00000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $7B - Opening curly bracket "{" (Upper & Lower Half $AC) + db %00000000, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000011, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %11100000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %11000000, %00000000 + db %11000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $7C - Vertical line "|" (Upper & Lower Half $AE) + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + db %00000001, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + db %10000000, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + // $7E - Tilde "~" (Upper & Lower Half $B0) + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00001110, %00000000 + db %00111111, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %00000000, %00000000 + db %10000100, %00000000 + + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + db %00000000, %00000000, %00000000, %00000000 + +BGMap: // BG Map Data ($2000 Bytes) + dw $0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000 + + // ! " # $ % & ' ( ) * + , - . / 0 1 2 3 4 5 6 7 8 9 : ; < = > ? @ + dw $0002,$0006,$0008,$000A,$000C,$000E,$0012,$0014,$4014,$0016,$001A,$0000,$001E,$0000,$0022,$0024,$0026,$002A,$002E,$0030,$0034,$0038,$003C,$0040,$C03A,$0020,$0020,$0042,$0044,$4042,$0046,$0048 + dw $0004,$0000,$C008,$C00A,$C00C,$0010,$0000,$8014,$C014,$0018,$801A,$001C,$801E,$0020,$C022,$8024,$0028,$002C,$802E,$0032,$0036,$003A,$003E,$8040,$C038,$0020,$001C,$8042,$8044,$C042,$0004,$004A + + // A B C D E F G H I J K L M N O P Q R S T U V W X Y Z [ \ ] ^ _ ` + dw $004C,$0050,$0052,$0054,$0056,$0056,$0052,$005C,$005E,$005E,$0062,$0064,$0068,$006C,$006E,$0050,$006E,$0050,$0074,$0076,$007A,$007E,$806A,$0082,$0082,$0086,$0088,$4022,$4088,$008A,$0000,$008E + dw $004E,$8050,$8052,$8054,$8056,$0058,$005A,$805C,$805E,$0060,$8062,$0066,$006A,$C06C,$806E,$0058,$0070,$0072,$C074,$0078,$007C,$0080,$8068,$8082,$0084,$C086,$8088,$8022,$C088,$0000,$008C,$0000 + + // a b c d e f g h i j k l m n o p q r s t u v w x y z { | } ~ + dw $0090,$8058,$4090,$C058,$4090,$C060,$4090,$8058,$009A,$009A,$009C,$8078,$009E,$0090,$0090,$0090,$4090,$0090,$0090,$8094,$009E,$009E,$009E,$009E,$009E,$0090,$00AC,$00AE,$40AC,$00B0,$0000,$0000 + dw $C050,$8050,$4036,$C050,$0092,$0094,$0096,$805C,$0078,$0060,$8062,$0078,$00A0,$805C,$8040,$4096,$0096,$0058,$00A2,$4060,$007C,$00A4,$00A6,$00A8,$0096,$00AA,$80AC,$80AE,$C0AC,$C0B0,$0000,$0000 + dw $0000,$0000,$0000,$0000,$0000,$0000,$0098,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$8064,$C064,$0000,$0000,$0000,$0000,$0000,$0000,$0000,$0098,$0000,$0000,$0000,$0000,$0000,$0000,$0000 + + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + + + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + + + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 + dw $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00, $00 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.asm new file mode 100644 index 00000000..78341db3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.asm @@ -0,0 +1,51 @@ +// SNES Interlace Font Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceFont.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, 32, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGMap, $4000, $2000, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $8000, $1640, 0) // Load Background Tiles To VRAM + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%00100010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $8000 (VRAM Address / $400) + lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $4000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +include "GFX/BG.asm" // Include BG \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.png new file mode 100644 index 00000000..a40af586 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.sfc new file mode 100644 index 00000000..4a4b15e3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..54d0f8d5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE FONT " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/make.bat b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/make.bat new file mode 100644 index 00000000..5671c8bd --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/make.bat @@ -0,0 +1 @@ +bass InterlaceFont.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.map new file mode 100644 index 00000000..9c000f52 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pal new file mode 100644 index 00000000..8b995080 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pic new file mode 100644 index 00000000..45cfe6c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.png new file mode 100644 index 00000000..5ace7a4b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.asm new file mode 100644 index 00000000..d6ade2c9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.asm @@ -0,0 +1,55 @@ +// SNES Interlace Moogle Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceMoogle.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F200, BGMap.size, 0) // Load Background Tile Map To VRAM + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Scroll Vertical Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Scroll Vertical Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (3584 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (16576 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.png new file mode 100644 index 00000000..5ace7a4b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.sfc new file mode 100644 index 00000000..a5aadabd Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..35d52182 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE MOOGLE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/make.bat b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/make.bat new file mode 100644 index 00000000..fd64c787 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/make.bat @@ -0,0 +1 @@ +bass InterlaceMoogle.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.map new file mode 100644 index 00000000..ac59ade9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.pal new file mode 100644 index 00000000..fc9a3de8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.pic new file mode 100644 index 00000000..349fe23d Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.png new file mode 100644 index 00000000..3e6bf3a9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGHI.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.pic new file mode 100644 index 00000000..0c69e829 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.png new file mode 100644 index 00000000..ae7acc1e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/GFX/BGLO.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.asm new file mode 100644 index 00000000..e63c00a6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.asm @@ -0,0 +1,76 @@ +// SNES Interlace Myst HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceMystHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGTilesHI, $0000, BGTilesHI.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGTilesLO, $6000, BGTilesLO.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F200, BGMap.size, 0) // Load Background Tile Map To VRAM + +SetupVideo: + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + // HDMA BG1 Tile Address + lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_BG12NBA // $0B: Start At BG1 Tile Address ($210B) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_BG1HOFS // Store Zero To BG Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +HDMATable: + db 112, 0 // Repeat 112 Scanlines, BG1 Tile Address = $0000 + db 112, 3 // Repeat 112 Scanlines, BG1 Tile Address = $3000 + db 0 // End Of HDMA + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (3584 Bytes) +insert BGTilesHI, "GFX/BGHI.pic" // Include BG Tile Data (23488 Bytes) +// BANK 1 +seek($18000) +insert BGTilesLO, "GFX/BGLO.pic" // Include BG Tile Data (29952 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.png new file mode 100644 index 00000000..727e3f7a Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.sfc new file mode 100644 index 00000000..463aff46 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..74560d65 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE MYST HDMA " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/make.bat new file mode 100644 index 00000000..9c415678 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/make.bat @@ -0,0 +1 @@ +bass InterlaceMystHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.map new file mode 100644 index 00000000..027b3ee6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pal new file mode 100644 index 00000000..be7689ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pic new file mode 100644 index 00000000..1c503452 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.png new file mode 100644 index 00000000..5f46c088 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BGPC98.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BGPC98.png new file mode 100644 index 00000000..e8bb84f7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/BGPC98.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pal new file mode 100644 index 00000000..ecf5055e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pic new file mode 100644 index 00000000..a2c8d97f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.png new file mode 100644 index 00000000..817c5330 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/Sprite.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/SpritePC98.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/SpritePC98.png new file mode 100644 index 00000000..1043a357 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/GFX/SpritePC98.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.asm new file mode 100644 index 00000000..1cb55606 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.asm @@ -0,0 +1,116 @@ +// SNES Interlace RPG Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceRPG.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F200, BGMap.size, 0) // Load Background Tile Map To VRAM + + LoadPAL(SpritePal, $80, SpritePal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) + //LoadVRAM(SpriteTiles, $8000, SpriteTiles.size, 0) // Load Sprite Tiles To VRAM + LoadVRAMStride(SpriteTiles, $8400, 128, $200, 6, 0) // Load Sprite Tiles To VRAM + + // Clear OAM + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Sprite OAM Info + ldx.w #$0000 // X = $0000 + stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + LoopSpriteOAM: + lda.w SpriteOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$04 + bne LoopSpriteOAM + + // Sprite OAM Extra Info + ldy.w #$0100 // Y = $0100 + sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation + LoopSpriteOAMSize: + lda.w SpriteOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #$05 + bne LoopSpriteOAMSize + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000011 // Object High-Resolution & Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #%00010001 // Enable BG1 & Sprites + sta.w REG_TM // $212C: BG1 & Sprites To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Scroll Vertical Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Scroll Vertical Position Hi Byte + + // Setup Sprites + lda.b #%11000010 // Object Size = 16x32/32x64, Name = 0, Base = $8000 + sta.w REG_OBSEL // $2101: Object Size & Object Base + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +// OAM Data +SpriteOAM: + // 16x32 / 32x64 Sprites + // OAM Info (Sprite 32x64) + db 112, -4, 0, %00110000 + + // OAM Extra Info + db %00000010 + +// Character Data +// BANK 0 +insert SpritePal, "GFX/Sprite.pal" // Include Sprite Palette Data (32 Bytes) +insert SpriteTiles, "GFX/Sprite.pic" // Include Sprite Tile Data (768 Bytes) +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (3584 Bytes) +// BANK 1 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32512 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.png new file mode 100644 index 00000000..26d4b4c6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.sfc new file mode 100644 index 00000000..73683638 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..1764b9e0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE RPG " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/make.bat b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/make.bat new file mode 100644 index 00000000..288bb095 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/make.bat @@ -0,0 +1 @@ +bass InterlaceRPG.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.map new file mode 100644 index 00000000..4f44fe40 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pal new file mode 100644 index 00000000..19e2c44e Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pic new file mode 100644 index 00000000..92297d15 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.png new file mode 100644 index 00000000..07559dbc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.asm new file mode 100644 index 00000000..3a1c427f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.asm @@ -0,0 +1,83 @@ +// SNES Interlace Scroll Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceScroll.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGMap, $4000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $8000, BGTiles.size, 0) // Load Background Tiles To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 tiles + + lda.b #%00000001 // Sets Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%00100011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x64, BG1 Map Address = $4000 (VRAM Address / $400) + lda.b #%00000100 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $8000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +ldx.w #$0000 // Reset BG X Position +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + ReadJOY({JOY_UP}) // Test Joypad UP Button + beq Down // IF (UP ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Vertical Scroll Position + + Down: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // IF (DOWN ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Vertical Scroll Position + + Left: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // IF (LEFT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, de) // Decrement BG1 Horizontal Scroll Position + + Right: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, in) // Increment BG1 Horizontal Scroll Position + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (8192 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (128 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.png new file mode 100644 index 00000000..0fd31cb5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.sfc new file mode 100644 index 00000000..125db079 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a47b6b1d --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE SCROLL DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/make.bat b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/make.bat new file mode 100644 index 00000000..14bc8c4e --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/make.bat @@ -0,0 +1 @@ +bass InterlaceScroll.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.map new file mode 100644 index 00000000..03d28144 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.pal new file mode 100644 index 00000000..0eb4e56a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BG.pal @@ -0,0 +1 @@ +C $`e l!! .jTNVz2;w \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.pic new file mode 100644 index 00000000..11a9d9d9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.png new file mode 100644 index 00000000..44d20417 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGHI.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.pic b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.pic new file mode 100644 index 00000000..7558a863 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.png new file mode 100644 index 00000000..540239c3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/GFX/BGLO.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.asm b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.asm new file mode 100644 index 00000000..7657be3c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.asm @@ -0,0 +1,77 @@ +// SNES Interlace Simpsons HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "InterlaceSimpsonsHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGTilesHI, $0000, BGTilesHI.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGTilesLO, $8000, BGTilesLO.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F200, BGMap.size, 0) // Load Background Tile Map To VRAM + +SetupVideo: + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + // HDMA BG1 Tile Address + lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_BG12NBA // $0B: Start At BG1 Tile Address ($210B) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_BG1HOFS // Store Zero To BG Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +Loop: + jmp Loop + +HDMATable: + db 112, 0 // Repeat 112 Scanlines, BG1 Tile Address = $0000 + db 32, 0 // Repeat 32 Scanlines, BG1 Tile Address = $0000 + db 80, 4 // Repeat 80 Scanlines, BG1 Tile Address = $4000 + db 0 // End Of HDMA + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (3584 Bytes) +insert BGTilesLO, "GFX/BGLO.pic" // Include BG Tile Data (27776 Bytes) +// BANK 1 +seek($18000) +insert BGTilesHI, "GFX/BGHI.pic" // Include BG Tile Data (29312 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.png b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.png new file mode 100644 index 00000000..768ec63d Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.sfc new file mode 100644 index 00000000..8de06b09 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..eda16b2a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "INTERLACE SIMPSONS " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw 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b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.pic new file mode 100644 index 00000000..6613c1f1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.png new file mode 100644 index 00000000..e99d197b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..a52d9335 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MODE7PERSPECTIVE DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $04 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7COSTable.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7COSTable.asm new file mode 100644 index 00000000..e013a075 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7COSTable.asm @@ -0,0 +1,10848 @@ +M7COSTable0: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20480 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 4096 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2926 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2276 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1862 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1575 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1365 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1205 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 1078 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 975 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 890 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 819 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 759 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 661 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 621 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 585 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 525 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 500 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 476 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 436 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 418 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 372 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 359 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 336 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 288 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 281 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable1: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable2: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable3: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable4: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable5: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable6: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable7: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable8: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable9: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable10: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable11: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable12: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable13: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable14: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable15: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable16: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable17: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable18: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable19: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable20: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable21: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable22: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable23: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable24: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20480 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -4096 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2926 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2276 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1862 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1575 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1365 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1205 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -1078 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -975 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -890 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -819 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -759 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -661 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -621 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -585 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -525 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -500 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -476 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -436 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -418 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -372 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -359 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -336 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -288 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -281 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable25: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable26: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable27: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable28: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable29: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable30: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable31: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable32: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable33: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable34: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable35: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable36: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable37: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable38: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable39: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable40: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable41: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable42: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable43: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable44: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable45: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable46: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA +M7COSTable47: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7NSINTable.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7NSINTable.asm new file mode 100644 index 00000000..48546be3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7NSINTable.asm @@ -0,0 +1,10848 @@ +M7NSINTable0: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable1: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable2: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable3: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable4: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable5: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable6: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable7: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable8: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable9: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable10: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable11: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable12: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20480 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -4096 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2926 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2276 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1862 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1575 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1365 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1205 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1078 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -975 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -931 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -890 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -853 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -819 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -759 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -731 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -706 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -683 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -661 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -640 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -621 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -585 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -569 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -554 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -539 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -525 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -512 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -500 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -488 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -476 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -465 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -455 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -436 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -427 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -418 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -410 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -372 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -359 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -347 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -336 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -325 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -306 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -293 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -288 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -281 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -247 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable13: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable14: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable15: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable16: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable17: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable18: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable19: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable20: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable21: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable22: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable23: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable24: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable25: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable26: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable27: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable28: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable29: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable30: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable31: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable32: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable33: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable34: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable35: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable36: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20480 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 4096 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2926 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2276 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1862 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1575 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1365 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1205 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 1078 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 975 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 931 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 890 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 853 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 819 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 788 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 759 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 731 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 706 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 683 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 661 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 640 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 621 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 602 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 585 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 569 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 554 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 539 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 525 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 512 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 500 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 488 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 476 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 465 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 455 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 445 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 436 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 427 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 418 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 410 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 402 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 386 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 379 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 372 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 366 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 359 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 347 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 336 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 330 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 325 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 320 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 315 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 310 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 306 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 297 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 293 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 288 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 284 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 281 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 273 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 269 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 266 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 259 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 256 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 253 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 247 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 238 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 235 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 207 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 205 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable37: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable38: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable39: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable40: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable41: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable42: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable43: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable44: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable45: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable46: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA +M7NSINTable47: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 -SIN Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 -SIN Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 -SIN Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 -SIN Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 -SIN Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 -SIN Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 -SIN Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 -SIN Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 -SIN Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 -SIN Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 -SIN Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 -SIN Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 -SIN Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 -SIN Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 -SIN Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 -SIN Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 -SIN Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 -SIN Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 -SIN Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 -SIN Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 -SIN Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 -SIN Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 -SIN Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 -SIN Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 -SIN Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 -SIN Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 -SIN Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 -SIN Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 -SIN Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 -SIN Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 -SIN Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 -SIN Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 -SIN Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 -SIN Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 -SIN Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 -SIN Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 -SIN Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 -SIN Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 -SIN Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 -SIN Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 -SIN Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 -SIN Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 -SIN Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 -SIN Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 -SIN Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 -SIN Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 -SIN Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 -SIN Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 -SIN Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 -SIN Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 -SIN Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 -SIN Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 -SIN Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 -SIN Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 -SIN Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 -SIN Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 -SIN Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 -SIN Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 -SIN Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 -SIN Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 -SIN Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 -SIN Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 -SIN Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 -SIN Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 -SIN Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 -SIN Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 -SIN Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 -SIN Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 -SIN Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 -SIN Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 -SIN Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 -SIN Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 -SIN Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 -SIN Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 -SIN Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 -SIN Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 -SIN Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 -SIN Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 -SIN Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 -SIN Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 -SIN Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 -SIN Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 -SIN Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 -SIN Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 -SIN Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 -SIN Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 -SIN Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 -SIN Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 -SIN Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 -SIN Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 -SIN Scanline 224 +db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7SINTable.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7SINTable.asm new file mode 100644 index 00000000..fd7ea8db --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/M7SINTable.asm @@ -0,0 +1,10848 @@ +M7SINTable0: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable1: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable2: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable3: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable4: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable5: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable6: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable7: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable8: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable9: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable10: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable11: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable12: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20480 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 4096 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2926 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2276 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1862 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1575 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1365 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1205 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1078 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 975 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 890 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 819 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 759 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 661 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 621 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 585 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 525 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 500 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 476 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 436 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 418 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 372 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 359 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 336 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 288 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 281 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable13: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 20305 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 10152 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6768 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 5076 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 4061 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3384 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2901 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2538 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2256 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 2030 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1846 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1692 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1562 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1450 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1269 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1194 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1128 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1069 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 967 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 923 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 846 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 781 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 752 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 725 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 700 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 655 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 635 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 615 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 597 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 564 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 549 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 534 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 472 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 441 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 432 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 423 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 398 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 383 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 376 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 363 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 333 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 303 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 299 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 251 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 248 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 242 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable14: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 19782 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 9891 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6594 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4946 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3956 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3297 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2826 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2473 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2198 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1978 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1798 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1649 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1522 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1413 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1319 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1236 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1164 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1099 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 1041 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 989 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 942 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 899 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 824 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 791 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 761 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 707 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 659 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 638 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 618 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 599 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 582 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 565 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 550 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 521 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 495 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 471 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 460 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 450 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 421 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 404 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 388 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 380 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 360 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 324 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 314 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 309 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 200 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 194 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable15: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 18921 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 9461 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 6307 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4730 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3784 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 3154 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2703 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2365 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 2102 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1892 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1720 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1577 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1455 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1352 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1261 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1183 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1113 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 1051 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 996 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 946 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 901 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 860 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 823 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 728 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 701 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 676 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 652 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 631 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 610 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 573 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 541 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 526 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 511 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 498 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 485 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 473 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 420 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 411 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 364 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 357 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 326 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 321 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 305 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 300 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 287 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 274 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 184 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable16: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 17736 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 8868 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 5912 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4434 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3547 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2956 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2534 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2217 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1971 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1774 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1612 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1478 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1364 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1267 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1182 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1109 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 1043 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 985 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 933 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 887 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 845 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 806 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 771 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 709 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 682 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 657 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 633 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 612 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 591 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 572 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 537 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 507 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 493 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 479 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 443 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 433 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 422 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 403 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 377 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 370 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 355 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 348 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 335 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 317 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 311 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 291 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 257 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 236 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 222 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable17: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 16248 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 8124 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 5416 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 4062 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 3250 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2708 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2321 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 2031 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1805 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1625 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1477 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1250 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1161 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 1083 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 956 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 903 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 855 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 812 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 774 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 739 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 677 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 650 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 625 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 580 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 524 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 508 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 492 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 478 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 464 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 451 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 428 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 417 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 396 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 387 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 361 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 338 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 332 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 319 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 307 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 285 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 262 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 258 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 246 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 239 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 232 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 229 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 175 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 169 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable18: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 14482 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 7241 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 4827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 3620 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2896 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2414 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 2069 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1810 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1609 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1448 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1317 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1207 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 1114 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 1034 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 965 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 905 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 852 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 805 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 762 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 724 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 690 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 658 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 630 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 579 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 557 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 536 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 517 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 483 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 467 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 453 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 439 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 426 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 391 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 381 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 371 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 345 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 329 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 322 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 302 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 296 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 278 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 268 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 179 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 172 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 159 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 132 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable19: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 12467 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 6234 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 4156 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 3117 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2493 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 2078 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1558 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1385 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1247 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 1133 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 1039 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 959 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 831 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 779 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 733 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 693 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 656 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 623 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 594 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 567 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 542 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 519 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 499 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 480 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 462 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 430 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 416 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 378 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 367 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 346 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 337 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 304 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 283 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 260 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 249 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 227 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 215 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 181 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 176 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 173 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 164 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 162 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 152 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 150 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 105 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable20: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 180 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 168 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 165 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 158 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 155 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 153 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 146 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 144 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 138 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 130 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 125 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 101 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable21: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 7837 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 3919 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 2612 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 1959 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 1567 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 1306 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 1120 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 980 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 871 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 784 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 712 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 653 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 603 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 560 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 522 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 490 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 461 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 435 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 412 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 392 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 373 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 327 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 313 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 280 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 270 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 224 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 182 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 174 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 170 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 163 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 160 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 154 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 148 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 145 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 142 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 140 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 137 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 135 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 131 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 128 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 124 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 121 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 119 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 117 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 114 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 112 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 109 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 97 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 94 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable22: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 5301 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 2650 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 1767 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 1325 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 1060 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 883 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 757 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 663 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 589 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 530 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 442 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 408 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 331 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 312 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 294 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 265 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 252 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 177 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 171 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 166 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 161 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 156 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 151 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 147 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 143 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 139 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 136 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 133 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 129 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 126 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 123 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 120 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 118 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 115 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 113 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 110 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 108 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 106 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 104 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 102 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 100 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 98 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 96 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 93 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 91 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 90 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 88 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 87 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 85 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 83 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 82 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 80 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 78 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 77 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 75 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 73 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 71 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 68 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 66 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 63 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 60 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 54 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable23: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 2673 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 1337 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 891 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 668 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 535 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 446 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 382 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 334 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 267 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 243 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 178 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 167 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 157 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 149 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 141 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 134 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 127 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 122 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 116 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 111 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 107 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 103 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 99 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 95 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 92 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 89 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 86 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 84 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 81 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 79 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 76 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 74 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 72 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 70 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 69 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 67 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 65 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 64 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 62 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 61 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 59 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 58 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 57 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 56 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 55 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 53 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 52 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 51 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 50 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 49 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 48 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 47 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 46 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 45 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 44 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 43 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 42 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 41 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 40 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 39 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 38 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 37 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 36 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 35 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 34 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 33 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 32 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 31 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 30 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 29 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 28 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 27 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 26 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 25 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 24 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 23 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 22 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 21 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 20 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 19 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 18 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 17 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 16 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 15 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 14 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 13 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 12 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable24: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw 0 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable25: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable26: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable27: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable28: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable29: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable30: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable31: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable32: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable33: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable34: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable35: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable36: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20480 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -4096 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2926 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2276 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1862 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1575 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1365 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1205 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -1078 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -975 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -890 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -819 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -759 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -661 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -621 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -585 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -525 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -500 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -476 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -436 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -418 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -372 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -359 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -336 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -288 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -281 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable37: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -20305 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -10152 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6768 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -5076 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -4061 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3384 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2901 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2538 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2256 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -2030 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1846 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1692 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1562 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1450 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1269 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1194 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1128 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -1069 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -967 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -923 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -846 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -781 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -752 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -725 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -700 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -655 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -635 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -615 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -597 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -564 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -549 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -534 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -472 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -441 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -432 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -423 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -398 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -383 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -376 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -363 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -333 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -303 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -299 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -251 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -248 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -242 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable38: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -19782 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -9891 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6594 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4946 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3956 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3297 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2826 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2473 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2198 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1978 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1798 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1649 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1522 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1413 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1319 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1236 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1164 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1099 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -1041 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -989 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -942 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -899 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -824 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -791 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -761 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -707 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -659 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -638 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -618 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -599 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -582 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -565 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -550 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -521 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -495 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -471 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -460 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -450 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -421 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -404 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -388 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -380 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -360 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -347 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -324 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -314 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -309 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -264 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -247 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -200 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -194 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable39: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -18921 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -9461 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -6307 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4730 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3784 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -3154 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2703 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2365 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -2102 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1892 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1720 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1577 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1455 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1352 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1261 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1183 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1113 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -1051 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -996 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -946 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -901 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -860 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -823 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -728 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -701 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -676 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -652 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -631 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -610 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -573 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -541 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -526 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -511 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -498 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -485 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -473 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -440 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -420 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -411 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -364 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -357 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -350 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -344 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -326 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -321 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -305 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -300 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -287 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -274 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -184 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable40: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -17736 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -8868 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -5912 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4434 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3547 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2956 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2534 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2217 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1971 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1774 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1612 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1478 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1364 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1267 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1182 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1109 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -1043 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -985 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -933 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -887 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -845 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -806 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -771 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -709 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -682 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -657 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -633 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -612 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -591 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -572 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -554 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -537 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -507 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -493 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -479 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -455 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -443 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -433 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -422 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -403 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -386 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -377 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -370 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -355 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -348 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -335 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -317 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -311 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -306 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -291 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -286 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -282 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -257 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -236 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -225 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -222 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -202 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -199 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable41: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -16248 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -8124 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -5416 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -4062 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -3250 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2708 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2321 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -2031 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1805 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1625 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1477 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1354 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1250 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1161 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -1083 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -1015 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -956 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -903 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -855 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -812 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -774 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -739 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -706 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -677 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -650 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -625 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -580 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -524 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -508 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -492 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -478 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -464 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -451 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -428 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -417 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -406 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -396 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -387 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -369 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -361 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -338 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -332 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -325 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -319 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -307 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -295 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -285 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -275 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -266 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -262 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -258 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -246 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -239 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -232 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -229 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -220 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -217 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -214 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -203 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -185 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -175 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -169 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable42: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -14482 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -7241 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -4827 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -3620 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2896 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2414 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -2069 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1810 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1609 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1448 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1317 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1207 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -1114 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -1034 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -965 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -905 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -852 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -805 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -762 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -724 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -690 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -658 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -630 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -579 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -557 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -536 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -517 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -483 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -467 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -453 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -439 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -426 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -414 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -391 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -381 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -371 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -362 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -345 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -329 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -322 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -315 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -308 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -302 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -296 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -278 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -273 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -268 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -259 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -234 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -226 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -216 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -210 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -207 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -188 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -179 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -172 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -159 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -132 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable43: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -12467 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -6234 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -4156 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -3117 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2493 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -2078 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1781 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1558 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1385 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1247 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -1133 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -1039 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -959 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -831 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -779 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -733 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -693 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -656 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -623 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -594 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -567 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -542 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -519 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -499 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -480 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -462 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -430 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -416 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -402 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -390 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -378 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -367 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -346 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -337 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -328 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -304 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -283 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -271 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -260 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -254 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -249 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -240 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -235 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -227 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -219 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -215 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -211 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -208 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -198 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -195 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -192 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -181 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -176 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -173 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -164 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -162 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -152 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -150 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -105 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable44: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -10240 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -5120 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -3413 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -2560 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -2048 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -1707 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1463 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -1280 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -1138 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -1024 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -931 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -853 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -788 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -731 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -683 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -640 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -602 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -569 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -539 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -512 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -488 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -465 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -445 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -427 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -410 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -394 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -366 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -330 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -320 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -310 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -293 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -284 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -277 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -269 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -263 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -256 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -250 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -244 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -238 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -233 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -228 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -213 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -209 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -205 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -197 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -193 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -190 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -186 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -180 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -168 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -165 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -158 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -155 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -153 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -146 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -144 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -138 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -130 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -125 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -101 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable45: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -7837 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -3919 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -2612 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -1959 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -1567 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -1306 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -1120 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -980 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -871 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -784 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -712 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -653 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -603 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -560 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -522 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -490 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -461 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -435 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -412 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -392 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -373 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -356 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -341 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -327 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -313 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -301 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -290 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -280 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -270 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -261 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -253 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -245 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -237 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -231 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -224 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -218 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -201 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -187 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -182 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -174 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -170 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -163 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -160 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -154 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -148 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -145 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -142 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -140 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -137 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -135 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -131 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -128 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -124 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -121 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -119 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -117 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -114 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -112 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -109 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -97 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -94 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable46: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -5301 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -2650 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -1767 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -1325 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -1060 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -883 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -757 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -663 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -589 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -530 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -482 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -442 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -408 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -379 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -353 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -331 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -312 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -294 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -279 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -265 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -252 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -241 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -230 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -221 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -212 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -204 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -196 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -189 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -183 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -177 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -171 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -166 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -161 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -156 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -151 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -147 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -143 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -139 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -136 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -133 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -129 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -126 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -123 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -120 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -118 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -115 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -113 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -110 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -108 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -106 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -104 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -102 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -100 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -98 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -96 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -93 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -91 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -90 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -88 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -87 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -85 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -83 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -82 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -80 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -78 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -77 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -75 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -73 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -71 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -68 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -66 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -63 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -60 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -54 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA +M7SINTable47: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw -2673 // Repeat 1 Scanline, Mode7 +SIN Scanline 1 +db $01; dw -1337 // Repeat 1 Scanline, Mode7 +SIN Scanline 2 +db $01; dw -891 // Repeat 1 Scanline, Mode7 +SIN Scanline 3 +db $01; dw -668 // Repeat 1 Scanline, Mode7 +SIN Scanline 4 +db $01; dw -535 // Repeat 1 Scanline, Mode7 +SIN Scanline 5 +db $01; dw -446 // Repeat 1 Scanline, Mode7 +SIN Scanline 6 +db $01; dw -382 // Repeat 1 Scanline, Mode7 +SIN Scanline 7 +db $01; dw -334 // Repeat 1 Scanline, Mode7 +SIN Scanline 8 +db $01; dw -297 // Repeat 1 Scanline, Mode7 +SIN Scanline 9 +db $01; dw -267 // Repeat 1 Scanline, Mode7 +SIN Scanline 10 +db $01; dw -243 // Repeat 1 Scanline, Mode7 +SIN Scanline 11 +db $01; dw -223 // Repeat 1 Scanline, Mode7 +SIN Scanline 12 +db $01; dw -206 // Repeat 1 Scanline, Mode7 +SIN Scanline 13 +db $01; dw -191 // Repeat 1 Scanline, Mode7 +SIN Scanline 14 +db $01; dw -178 // Repeat 1 Scanline, Mode7 +SIN Scanline 15 +db $01; dw -167 // Repeat 1 Scanline, Mode7 +SIN Scanline 16 +db $01; dw -157 // Repeat 1 Scanline, Mode7 +SIN Scanline 17 +db $01; dw -149 // Repeat 1 Scanline, Mode7 +SIN Scanline 18 +db $01; dw -141 // Repeat 1 Scanline, Mode7 +SIN Scanline 19 +db $01; dw -134 // Repeat 1 Scanline, Mode7 +SIN Scanline 20 +db $01; dw -127 // Repeat 1 Scanline, Mode7 +SIN Scanline 21 +db $01; dw -122 // Repeat 1 Scanline, Mode7 +SIN Scanline 22 +db $01; dw -116 // Repeat 1 Scanline, Mode7 +SIN Scanline 23 +db $01; dw -111 // Repeat 1 Scanline, Mode7 +SIN Scanline 24 +db $01; dw -107 // Repeat 1 Scanline, Mode7 +SIN Scanline 25 +db $01; dw -103 // Repeat 1 Scanline, Mode7 +SIN Scanline 26 +db $01; dw -99 // Repeat 1 Scanline, Mode7 +SIN Scanline 27 +db $01; dw -95 // Repeat 1 Scanline, Mode7 +SIN Scanline 28 +db $01; dw -92 // Repeat 1 Scanline, Mode7 +SIN Scanline 29 +db $01; dw -89 // Repeat 1 Scanline, Mode7 +SIN Scanline 30 +db $01; dw -86 // Repeat 1 Scanline, Mode7 +SIN Scanline 31 +db $01; dw -84 // Repeat 1 Scanline, Mode7 +SIN Scanline 32 +db $01; dw -81 // Repeat 1 Scanline, Mode7 +SIN Scanline 33 +db $01; dw -79 // Repeat 1 Scanline, Mode7 +SIN Scanline 34 +db $01; dw -76 // Repeat 1 Scanline, Mode7 +SIN Scanline 35 +db $01; dw -74 // Repeat 1 Scanline, Mode7 +SIN Scanline 36 +db $01; dw -72 // Repeat 1 Scanline, Mode7 +SIN Scanline 37 +db $01; dw -70 // Repeat 1 Scanline, Mode7 +SIN Scanline 38 +db $01; dw -69 // Repeat 1 Scanline, Mode7 +SIN Scanline 39 +db $01; dw -67 // Repeat 1 Scanline, Mode7 +SIN Scanline 40 +db $01; dw -65 // Repeat 1 Scanline, Mode7 +SIN Scanline 41 +db $01; dw -64 // Repeat 1 Scanline, Mode7 +SIN Scanline 42 +db $01; dw -62 // Repeat 1 Scanline, Mode7 +SIN Scanline 43 +db $01; dw -61 // Repeat 1 Scanline, Mode7 +SIN Scanline 44 +db $01; dw -59 // Repeat 1 Scanline, Mode7 +SIN Scanline 45 +db $01; dw -58 // Repeat 1 Scanline, Mode7 +SIN Scanline 46 +db $01; dw -57 // Repeat 1 Scanline, Mode7 +SIN Scanline 47 +db $01; dw -56 // Repeat 1 Scanline, Mode7 +SIN Scanline 48 +db $01; dw -55 // Repeat 1 Scanline, Mode7 +SIN Scanline 49 +db $01; dw -53 // Repeat 1 Scanline, Mode7 +SIN Scanline 50 +db $01; dw -52 // Repeat 1 Scanline, Mode7 +SIN Scanline 51 +db $01; dw -51 // Repeat 1 Scanline, Mode7 +SIN Scanline 52 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 53 +db $01; dw -50 // Repeat 1 Scanline, Mode7 +SIN Scanline 54 +db $01; dw -49 // Repeat 1 Scanline, Mode7 +SIN Scanline 55 +db $01; dw -48 // Repeat 1 Scanline, Mode7 +SIN Scanline 56 +db $01; dw -47 // Repeat 1 Scanline, Mode7 +SIN Scanline 57 +db $01; dw -46 // Repeat 1 Scanline, Mode7 +SIN Scanline 58 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 59 +db $01; dw -45 // Repeat 1 Scanline, Mode7 +SIN Scanline 60 +db $01; dw -44 // Repeat 1 Scanline, Mode7 +SIN Scanline 61 +db $01; dw -43 // Repeat 1 Scanline, Mode7 +SIN Scanline 62 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 63 +db $01; dw -42 // Repeat 1 Scanline, Mode7 +SIN Scanline 64 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 65 +db $01; dw -41 // Repeat 1 Scanline, Mode7 +SIN Scanline 66 +db $01; dw -40 // Repeat 1 Scanline, Mode7 +SIN Scanline 67 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 68 +db $01; dw -39 // Repeat 1 Scanline, Mode7 +SIN Scanline 69 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 70 +db $01; dw -38 // Repeat 1 Scanline, Mode7 +SIN Scanline 71 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 72 +db $01; dw -37 // Repeat 1 Scanline, Mode7 +SIN Scanline 73 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 74 +db $01; dw -36 // Repeat 1 Scanline, Mode7 +SIN Scanline 75 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 76 +db $01; dw -35 // Repeat 1 Scanline, Mode7 +SIN Scanline 77 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 78 +db $01; dw -34 // Repeat 1 Scanline, Mode7 +SIN Scanline 79 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 80 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 81 +db $01; dw -33 // Repeat 1 Scanline, Mode7 +SIN Scanline 82 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 83 +db $01; dw -32 // Repeat 1 Scanline, Mode7 +SIN Scanline 84 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 85 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 86 +db $01; dw -31 // Repeat 1 Scanline, Mode7 +SIN Scanline 87 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 88 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 89 +db $01; dw -30 // Repeat 1 Scanline, Mode7 +SIN Scanline 90 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 91 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 92 +db $01; dw -29 // Repeat 1 Scanline, Mode7 +SIN Scanline 93 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 94 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 95 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 96 +db $01; dw -28 // Repeat 1 Scanline, Mode7 +SIN Scanline 97 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 98 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 99 +db $01; dw -27 // Repeat 1 Scanline, Mode7 +SIN Scanline 100 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 101 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 102 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 103 +db $01; dw -26 // Repeat 1 Scanline, Mode7 +SIN Scanline 104 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 105 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 106 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 107 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 108 +db $01; dw -25 // Repeat 1 Scanline, Mode7 +SIN Scanline 109 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 110 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 111 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 112 +db $01; dw -24 // Repeat 1 Scanline, Mode7 +SIN Scanline 113 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 114 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 115 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 116 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 117 +db $01; dw -23 // Repeat 1 Scanline, Mode7 +SIN Scanline 118 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 119 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 120 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 121 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 122 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 123 +db $01; dw -22 // Repeat 1 Scanline, Mode7 +SIN Scanline 124 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 125 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 126 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 127 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 128 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 129 +db $01; dw -21 // Repeat 1 Scanline, Mode7 +SIN Scanline 130 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 131 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 132 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 133 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 134 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 135 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 136 +db $01; dw -20 // Repeat 1 Scanline, Mode7 +SIN Scanline 137 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 138 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 139 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 140 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 141 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 142 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 143 +db $01; dw -19 // Repeat 1 Scanline, Mode7 +SIN Scanline 144 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 145 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 146 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 147 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 148 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 149 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 150 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 151 +db $01; dw -18 // Repeat 1 Scanline, Mode7 +SIN Scanline 152 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 153 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 154 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 155 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 156 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 157 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 158 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 159 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 160 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 161 +db $01; dw -17 // Repeat 1 Scanline, Mode7 +SIN Scanline 162 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 163 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 164 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 165 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 166 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 167 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 168 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 169 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 170 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 171 +db $01; dw -16 // Repeat 1 Scanline, Mode7 +SIN Scanline 172 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 173 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 174 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 175 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 176 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 177 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 178 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 179 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 180 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 181 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 182 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 183 +db $01; dw -15 // Repeat 1 Scanline, Mode7 +SIN Scanline 184 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 185 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 186 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 187 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 188 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 189 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 190 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 191 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 192 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 193 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 194 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 195 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 196 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 197 +db $01; dw -14 // Repeat 1 Scanline, Mode7 +SIN Scanline 198 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 199 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 200 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 201 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 202 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 203 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 204 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 205 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 206 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 207 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 208 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 209 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 210 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 211 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 212 +db $01; dw -13 // Repeat 1 Scanline, Mode7 +SIN Scanline 213 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 214 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 215 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 216 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 217 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 218 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 219 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 220 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 221 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 222 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 223 +db $01; dw -12 // Repeat 1 Scanline, Mode7 +SIN Scanline 224 +db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcCOS.py b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcCOS.py new file mode 100644 index 00000000..6f13b4b1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcCOS.py @@ -0,0 +1,29 @@ +import math + +cam_pos_y = 80 # Camera Position Y + +twoPI = math.pi * 2 +points = 48 # Number Of Direction Points +angle = 0 # Direction Angle + +while angle < points: + print ("M7COSTable%d: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional)" % angle) + + g_cosf = math.cos((twoPI / points) * angle) # cos(phi) + g_sinf = math.sin((twoPI / points) * angle) # sin(phi) + + REG_VCOUNT = 1 # Scanline + + while REG_VCOUNT <= 224: + + # Zoom * Rotation + + lam = cam_pos_y / REG_VCOUNT # lam = ScaleXY + + M7_COS = g_cosf * lam # M7A & M7D = +COS(angle) * ScaleXY + + print ("db $01; dw", round(M7_COS*256), "// Repeat 1 Scanline, Mode7 +COS Scanline", REG_VCOUNT) + REG_VCOUNT += 1 + + print ("db $00 // End Of HDMA") + angle += 1 diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcNSIN.py b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcNSIN.py new file mode 100644 index 00000000..1b15fdff --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcNSIN.py @@ -0,0 +1,29 @@ +import math + +cam_pos_y = 80 # Camera Position Y + +twoPI = math.pi * 2 +points = 48 # Number Of Direction Points +angle = 0 # Direction Angle + +while angle < points: + print ("M7NSINTable%d: // Mode7 -SIN (C) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional)" % angle) + + g_cosf = math.cos((twoPI / points) * angle) # cos(phi) + g_sinf = math.sin((twoPI / points) * angle) # sin(phi) + + REG_VCOUNT = 1 # Scanline + + while REG_VCOUNT <= 224: + + # Zoom * Rotation + + lam = cam_pos_y / REG_VCOUNT # lam = ScaleXY + + M7_NSIN = -g_sinf * lam # M7C = -SIN(angle) * ScaleXY + + print ("db $01; dw", round(M7_NSIN*256), "// Repeat 1 Scanline, Mode7 -SIN Scanline", REG_VCOUNT) + REG_VCOUNT += 1 + + print ("db $00 // End Of HDMA") + angle += 1 diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcSIN.py b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcSIN.py new file mode 100644 index 00000000..8e103564 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/MODE7Calc/MODE7CalcSIN.py @@ -0,0 +1,29 @@ +import math + +cam_pos_y = 80 # Camera Position Y + +twoPI = math.pi * 2 +points = 48 # Number Of Direction Points +angle = 0 # Direction Angle + +while angle < points: + print ("M7SINTable%d: // Mode7 +SIN (B) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional)" % angle) + + g_cosf = math.cos((twoPI / points) * angle) # cos(phi) + g_sinf = math.sin((twoPI / points) * angle) # sin(phi) + + REG_VCOUNT = 1 # Scanline + + while REG_VCOUNT <= 224: + + # Zoom * Rotation + + lam = cam_pos_y / REG_VCOUNT # lam = ScaleXY + + M7_SIN = g_sinf * lam # M7B = +SIN(angle) * ScaleXY + + print ("db $01; dw", round(M7_SIN*256), "// Repeat 1 Scanline, Mode7 +SIN Scanline", REG_VCOUNT) + REG_VCOUNT += 1 + + print ("db $00 // End Of HDMA") + angle += 1 diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.asm new file mode 100644 index 00000000..ad43ddee --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.asm @@ -0,0 +1,312 @@ +// SNES Mode7 Perspective Demo by krom (Peter Lemon): +// Direction Pad Changes BG Mode7 X/Z Position +// L/R Buttons Rotate BG Mode7 Clockwise/Anti-Clockwise +// X/B Buttons Changes BG Mode7 FOV (Mode7 Distance) +// Y/A Buttons Changes BG Mode7 Perspective Center Position +arch snes.cpu +output "Perspective.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $20000 // Fill Upto $FFFF (Bank 3) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +Mode7PosX: + dw 0 // Mode7 Center Position X Word +Mode7PosY: + dw 0 // Mode7 Center Position Y Word +BG1ScrPosX: + dw 0 // Mode7 BG1 Scroll Position X Word +BG1ScrPosY: + dw 0 // Mode7 BG1 Scroll Position Y Word + +Mode7Angle: + db 0 // Mode7 Angle 0..15 + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadM7VRAM(BGMap, BGTiles, $0000, BGMap.size, BGTiles.size, 0) // Load Background Map & Tiles To VRAM + + lda.b #$01 // Enable Joypad NMI Reading Interrupt + sta.w REG_NMITIMEN + + // Setup Video + lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: Set BG1 To Main Screen Designation + + lda.b #$80 + sta.w REG_M7SEL // $211A: Mode7 Settings + + + + ldx.w #384 // BG1HOFS = 384 + stx.b BG1ScrPosX + + ldx.w #768 // BG1VOFS = 768 + stx.b BG1ScrPosY + + ldx.w #512 // M7X = 512 + stx.b Mode7PosX + + ldx.w #1152 // M7Y = 1152 + stx.b Mode7PosY + + stz.b Mode7Angle // Mode7 Angle = 0 + + + + // HDMA Mode7 +COS (A) Scanline + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_M7A // $1B: Start At MODE7 COSINE A ($211B) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #M7COSTable0 // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #1 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + + // HDMA Mode7 +SIN (B) Scanline + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters + lda.b #REG_M7B // $1C: Start At MODE7 SINE A ($211C) + sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #M7SINTable0 // HMDA Table Address + stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + lda.b #2 // HDMA Table Bank + sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + + // HDMA Mode7 -SIN (C) Scanline + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters + lda.b #REG_M7C // $1D: Start At MODE7 SINE B ($211D) + sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #M7NSINTable0 // HMDA Table Address + stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + lda.b #3 // HDMA Table Bank + sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + + // HDMA Mode7 +COS (D) Scanline + lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice + sta.w REG_DMAP3 // $4330: DMA3 DMA/HDMA Parameters + lda.b #REG_M7D // $1E: Start At MODE7 COSINE B ($211E) + sta.w REG_BBAD3 // $4331: DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #M7COSTable0 // HMDA Table Address + stx.w REG_A1T3L // $4332: DMA3 DMA/HDMA Table Start Address + lda.b #1 // HDMA Table Bank + sta.w REG_A1B3 // $4334: DMA3 DMA/HDMA Table Start Address (Bank) + + lda.b #%00001111 // HDMA Channel Select (Channel 0,1,2,3) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + lda.b #$F // Turn On Screen, Full Brightness + sta.w REG_INIDISP // $2100: Screen Display + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + lda.b BG1ScrPosX + sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte + lda.b BG1ScrPosX + 1 + sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + + lda.b BG1ScrPosY + sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte + lda.b BG1ScrPosY + 1 + sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + + lda.b Mode7PosX + sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + lda.b Mode7PosX + 1 + sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + + lda.b Mode7PosY + sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + lda.b Mode7PosY + 1 + sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + lda.b Mode7Angle // A = Mode7 Angle + asl // A * 2 + tax // X = A + ldy.w M7COSTable,x // HMDA Table Address + sty.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + sty.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address + sty.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address + sty.w REG_A1T3L // $4332: DMA3 DMA/HDMA Table Start Address + + JoyL: + ReadJOY({JOY_L}) // Test L Button + beq JoyR // IF (L ! Pressed) Branch Down + lda.b Mode7Angle + inc + cmp.b #$30 + bne JoyLEnd + lda.b #$00 + JoyLEnd: + sta.b Mode7Angle + + JoyR: + ReadJOY({JOY_R}) // Test R Button + beq JoyUp // IF (R ! Pressed) Branch Down + lda.b Mode7Angle + dec + cmp.b #$FF + bne JoyREnd + lda.b #$2F + JoyREnd: + sta.b Mode7Angle + + JoyUp: + ReadJOY({JOY_UP}) // Test Joypad UP Button + beq JoyDown // IF (UP ! Pressed) Branch Down + ldx.b BG1ScrPosY // Decrement BG1 Y Pos + dex + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Decrement Mode7 Y Pos + dex + stx.b Mode7PosY + + JoyDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq JoyLeft // IF (DOWN ! Pressed) Branch Down + ldx.b BG1ScrPosY // Increment BG1 Y Pos + inx + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Increment Mode7 Y Pos + inx + stx.b Mode7PosY + + JoyLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq JoyRight // IF (LEFT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Decrement BG1 X Pos + dex + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Decrement Mode7 X Pos + dex + stx.b Mode7PosX + + JoyRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq JoyY // IF (RIGHT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Increment BG1 X Pos + inx + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Increment Mode7 X Pos + inx + stx.b Mode7PosX + + JoyY: + ReadJOY({JOY_Y}) // Test Y Button + beq JoyA // IF (Y ! Pressed) Branch Down + ldx.b Mode7PosX // Decrement Mode7 X Pos + dex + stx.b Mode7PosX + + JoyA: + ReadJOY({JOY_A}) // Test A Button + beq JoyX // IF (A ! Pressed) Branch Down + ldx.b Mode7PosX // Increment Mode7 X Pos + inx + stx.b Mode7PosX + + JoyX: + ReadJOY({JOY_X}) // Test X Button + beq JoyB // IF (X ! Pressed) Branch Down + ldx.b Mode7PosY // Decrement Mode7 Y Pos + dex + stx.b Mode7PosY + + JoyB: + ReadJOY({JOY_B}) // Test B Button + beq Finish // IF (B ! Pressed) Branch Down + ldx.b Mode7PosY // Increment Mode7 Y Pos + inx + stx.b Mode7PosY + +Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (16384 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (10944 Bytes) + +M7COSTable: + dw M7COSTable0 + dw M7COSTable1 + dw M7COSTable2 + dw M7COSTable3 + dw M7COSTable4 + dw M7COSTable5 + dw M7COSTable6 + dw M7COSTable7 + dw M7COSTable8 + dw M7COSTable9 + dw M7COSTable10 + dw M7COSTable11 + dw M7COSTable12 + dw M7COSTable13 + dw M7COSTable14 + dw M7COSTable15 + dw M7COSTable16 + dw M7COSTable17 + dw M7COSTable18 + dw M7COSTable19 + dw M7COSTable20 + dw M7COSTable21 + dw M7COSTable22 + dw M7COSTable23 + dw M7COSTable24 + dw M7COSTable25 + dw M7COSTable26 + dw M7COSTable27 + dw M7COSTable28 + dw M7COSTable29 + dw M7COSTable30 + dw M7COSTable31 + dw M7COSTable32 + dw M7COSTable33 + dw M7COSTable34 + dw M7COSTable35 + dw M7COSTable36 + dw M7COSTable37 + dw M7COSTable38 + dw M7COSTable39 + dw M7COSTable40 + dw M7COSTable41 + dw M7COSTable42 + dw M7COSTable43 + dw M7COSTable44 + dw M7COSTable45 + dw M7COSTable46 + dw M7COSTable47 + +// BANK 1 +seek($18000) +include "M7COSTable.asm" // Include Mode7 +COS (A & D) Table + +// BANK 2 +seek($28000) +include "M7SINTable.asm" // Include Mode7 +SIN (B) Table + +// BANK 3 +seek($38000) +include "M7NSINTable.asm" // Include Mode7 -SIN (C) Table \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.png b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.png new file mode 100644 index 00000000..8d141c88 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.sfc b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.sfc new file mode 100644 index 00000000..ee9c8f30 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/make.bat b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/make.bat new file mode 100644 index 00000000..f0f78d44 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/Perspective/make.bat @@ -0,0 +1 @@ +bass Perspective.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.map new file mode 100644 index 00000000..e387cd09 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.map @@ -0,0 +1,7399 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +  + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + 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00000000..6613c1f1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.png new file mode 100644 index 00000000..e99d197b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9b5a8a7a --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "MODE7ROTATE ZOOM DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.asm new file mode 100644 index 00000000..85d695c1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.asm @@ -0,0 +1,218 @@ +// SNES Mode7 Rotation & Zoom Demo by krom (Peter Lemon): +arch snes.cpu +output "RotZoom.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +Mode7Angle: + db 0 // Mode7 Angle Byte +Mode7A: + dw 0 // Mode7 COS A Word +Mode7B: + dw 0 // Mode7 SIN A Word +Mode7C: + dw 0 // Mode7 SIN B Word +Mode7D: + dw 0 // Mode7 COS B Word +Mode7ScaleX: + dw 0 // Mode7 Scale X Word +Mode7ScaleY: + dw 0 // Mode7 Scale Y Word +Mode7PosX: + dw 0 // Mode7 Center Position X Word +Mode7PosY: + dw 0 // Mode7 Center Position Y Word +BG1ScrPosX: + dw 0 // Mode7 BG1 Scroll Position X Word +BG1ScrPosY: + dw 0 // Mode7 BG1 Scroll Position Y Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadM7VRAM(BGMap, BGTiles, $0000, BGMap.size, BGTiles.size, 0) // Load Background Map & Tiles To VRAM + + lda.b #$01 // Enable Joypad NMI Reading Interrupt + sta.w REG_NMITIMEN + + // Setup Video + lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: Set BG1 To Main Screen Designation + + stz.w REG_M7SEL // $211A: Mode7 Settings + + stz.b Mode7Angle // Reset Angle + + ldx.w #$0000 // Reset BG Position + stx.b BG1ScrPosX + stx.b BG1ScrPosY + + ldx.w #$0100 // Reset Scale + stx.b Mode7ScaleX + stx.b Mode7ScaleY + + ldx.w #$0080 // Reset Mode7 Center Position + stx.b Mode7PosX + stx.b Mode7PosY + + lda.b #$80 + sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + stz.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + stz.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + lda.b #$F // Turn On Screen, Full Brightness + sta.w REG_INIDISP // $2100: Screen Display + +InputLoop: + WaitNMI() // Wait For Vertical Blank + Mode7CALC(Mode7A, Mode7B, Mode7C, Mode7D, Mode7Angle, Mode7ScaleX, Mode7ScaleY, SINCOS256) // Calculate Mode 7 matrix + + lda.b BG1ScrPosX + sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte + lda.b BG1ScrPosX + 1 + sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + + lda.b BG1ScrPosY + sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte + lda.b BG1ScrPosY + 1 + sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + + lda.b Mode7PosX + sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + lda.b Mode7PosX + 1 + sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + + lda.b Mode7PosY + sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + lda.b Mode7PosY + 1 + sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + JoyA: + ReadJOY({JOY_A}) // Test A Button + beq JoyB // IF (A ! Pressed) Branch Down + ldx.w Mode7ScaleX + inx + stx.w Mode7ScaleX + stx.w Mode7ScaleY + + JoyB: + ReadJOY({JOY_B}) // Test B Button + beq JoyL // IF (B ! Pressed) Branch Down + ldx.w Mode7ScaleX + dex + stx.w Mode7ScaleX + stx.w Mode7ScaleY + + JoyL: + ReadJOY({JOY_L}) // Test L Button + beq JoyR // IF (L ! Pressed) Branch Down + dec.b Mode7Angle + + JoyR: + ReadJOY({JOY_R}) // Test R Button + beq JoyUp // IF (R ! Pressed) Branch Down + inc.b Mode7Angle + + JoyUp: + ReadJOY({JOY_UP}) // Test Joypad UP Button + beq JoyDown // IF (UP ! Pressed) Branch Down + ldx.b BG1ScrPosY // Decrement BG1 Y Pos + dex + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Decrement Mode7 Y Pos + dex + stx.b Mode7PosY + + JoyDown: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq JoyLeft // IF (DOWN ! Pressed) Branch Down + ldx.b BG1ScrPosY // Increment BG1 Y Pos + inx + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Increment Mode7 Y Pos + inx + stx.b Mode7PosY + + JoyLeft: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq JoyRight // IF (LEFT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Decrement BG1 X Pos + dex + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Decrement Mode7 X Pos + dex + stx.b Mode7PosX + + JoyRight: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + ldx.b BG1ScrPosX // Increment BG1 X Pos + inx + stx.b BG1ScrPosX + + ldx.b Mode7PosX // Increment Mode7 X Pos + inx + stx.b Mode7PosX + +Finish: + jmp InputLoop + +// Const Data +SINCOS256: // 256 SINE Values Ranging From -127 To 127 (Add 64 To Offset To Get COS) + db 0, 3, 6, 9, 12, 16, 19, 22 + db 25, 28, 31, 34, 37, 40, 43, 46 + db 48, 51, 54, 57, 60, 62, 65, 68 + db 70, 73, 75, 78, 80, 83, 85, 87 + db 90, 92, 94, 96, 98, 100, 102, 104 + db 105, 107, 109, 110, 112, 113, 115, 116 + db 117, 118, 119, 120, 121, 122, 123, 124 + db 124, 125, 126, 126, 126, 127, 127, 127 + db 127, 127, 127, 127, 126, 126, 126, 125 + db 125, 124, 123, 123, 122, 121, 120, 119 + db 118, 116, 115, 114, 112, 111, 109, 108 + db 106, 104, 102, 101, 99, 97, 95, 93 + db 90, 88, 86, 84, 81, 79, 76, 74 + db 71, 69, 66, 63, 61, 58, 55, 52 + db 49, 47, 44, 41, 38, 35, 32, 29 + db 26, 23, 20, 17, 14, 10, 7, 4 + db 1, -2, -5, -8, -11, -14, -17, -21 + db -24, -27, -30, -33, -36, -39, -42, -45 + db -47, -50, -53, -56, -59, -61, -64, -67 + db -69, -72, -75, -77, -80, -82, -84, -87 + db -89, -91, -93, -95, -97, -99, -101, -103 + db -105, -107, -108, -110, -111, -113, -114, -115 + db -117, -118, -119, -120, -121, -122, -123, -124 + db -124, -125, -125, -126, -126, -127, -127, -127 + db -127, -127, -127, -127, -127, -126, -126, -125 + db -125, -124, -124, -123, -122, -121, -120, -119 + db -118, -117, -116, -114, -113, -111, -110, -108 + db -107, -105, -103, -101, -99, -97, -95, -93 + db -91, -89, -87, -84, -82, -80, -77, -75 + db -72, -70, -67, -64, -62, -59, -56, -53 + db -51, -48, -45, -42, -39, -36, -33, -30 + db -27, -24, -21, -18, -15, -12, -8, -5 + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (16384 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (10944 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.png b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.png new file mode 100644 index 00000000..b8e1892b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.sfc b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.sfc new file mode 100644 index 00000000..64bd3a15 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/make.bat b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/make.bat new file mode 100644 index 00000000..65fa4653 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/RotZoom/make.bat @@ -0,0 +1 @@ +bass RotZoom.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFont.pic b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFont.pic new file mode 100644 index 00000000..5b3ee020 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFont.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.pal b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.pal new file mode 100644 index 00000000..ce2d9040 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.png b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.png new file mode 100644 index 00000000..634d7bfc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontBlue.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.pal b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.pal new file mode 100644 index 00000000..f393e6eb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.png b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.png new file mode 100644 index 00000000..b63024aa Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsFontYellow.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.map b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.map new file mode 100644 index 00000000..7416d873 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pal b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pal new file mode 100644 index 00000000..ca4d52dc Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pic b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pic new file mode 100644 index 00000000..39ab650d Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.png b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.png new file mode 100644 index 00000000..e4ba377f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsLogo.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pal b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pal new file mode 100644 index 00000000..a2ace790 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pic b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pic new file mode 100644 index 00000000..76a8f636 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.png b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.png new file mode 100644 index 00000000..99ecb72c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/GFX/StarWarsStars.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Intro.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Intro.asm new file mode 100644 index 00000000..9b4d441f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Intro.asm @@ -0,0 +1,82 @@ +//------- +// Intro +//------- +// Clear Mode7 VRAM +lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte +sta.w REG_VMAIN // $2115: Video Port Control +ldx.w #$0000 // Set VRAM Destination +stx.w REG_VMADDL // $2116: VRAM +ldy.w #$0000 +- + sty.w REG_VMDATAL // $2118: VRAM Data Write + inx // X++ + cpx.w #$4000 + bne - + +LoadPAL(FontBluePal, $00, FontYellowPal.size, 0) // Load Background Palette +LoadHIVRAM(FontTiles, $0000, FontTiles.size, 0) // Load Background Tiles To VRAM +LoadLOVRAM(IntroFontMap, $0000, 1280, 0) // Load Background Tile Map To VRAM + +// Setup Video +lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + +lda.b #%00000001 // Enable BG1 +sta.w REG_TM // $212C: BG1 To Main Screen Designation + +lda.b #$80 // No Repeat on Mode7 Screen +sta.w REG_M7SEL // $211A: Mode7 Settings + +lda.b #$9A // Reset Scale +sta.w REG_M7A // $211B: MODE7 COSINE A +lda.b #$01 +sta.w REG_M7A // $211B: MODE7 COSINE A +lda.b #$00 +sta.w REG_M7D // $211E: MODE7 COSINE B +lda.b #$01 +sta.w REG_M7D // $211E: MODE7 COSINE B + +ldx.w #382 // BG1HOFS = 384 +stx.b BG1ScrPosX + +ldx.w #-90 // BG1VOFS = 0 +stx.b BG1ScrPosY + +ldx.w #512 // M7X = 512 +stx.b Mode7PosX + +ldx.w #-90 // M7Y = 0 +stx.b Mode7PosY + +lda.b BG1ScrPosX +sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte +lda.b BG1ScrPosX + 1 +sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + +lda.b BG1ScrPosY +sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte +lda.b BG1ScrPosY + 1 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + +lda.b Mode7PosX +sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte +lda.b Mode7PosX + 1 +sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + +lda.b Mode7PosY +sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte +lda.b Mode7PosY + 1 +sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + +FadeIN() // Screen Fade In + +ldx.w #120 +IntroLoop: + WaitNMI() // Wait For Vertical Blank + dex + bne IntroLoop + +FadeOUT() // Screen Fade Out + +lda.b #$80 +sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..11fb12c1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "STAR WARS " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $04 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Logo.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Logo.asm new file mode 100644 index 00000000..fc2ca13f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Logo.asm @@ -0,0 +1,210 @@ +//------ +// Logo +//------ +// Clear Mode7 VRAM +lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte +sta.w REG_VMAIN // $2115: Video Port Control +ldx.w #$0000 // Set VRAM Destination +stx.w REG_VMADDL // $2116: VRAM +ldy.w #$0000 +- + sty.w REG_VMDATAL // $2118: VRAM Data Write + inx // X++ + cpx.w #$4000 + bne - + +LoadPAL(LogoPal, $00, LogoPal.size, 0) // Load Background Palette +LoadHIVRAM(LogoTiles, $0000, FontTiles.size, 0) // Load Background Tiles To VRAM +LoadLOVRAM(LogoMap, $0000, LogoMap.size, 0) // Load Background Tile Map To VRAM + +LoadPAL(StarsPal, $80, StarsPal.size, 0) // Load Sprite Palette (Sprite Palette Uses 16 Colors) +LoadVRAM(StarsTiles, $8000, StarsTiles.size, 0) // Load Sprite Tiles To VRAM + +// Clear OAM +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +ldx.w #$0080 +lda.b #$E0 +- + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + +ldx.w #$0020 +- + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + +// Scroller OAM Info +ldx.w #$0000 // X = $0000 +stx.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopStarsOAM: + lda.w StarsOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #80 + bne LoopStarsOAM + +// Scroller OAM Extra Info +ldy.w #$0100 // Y = $0100 +sty.w REG_OAMADDL // $2102: OAM Address & Priority Rotation +LoopStarsOAMSize: + lda.w StarsOAM,x + sta.w REG_OAMDATA // Store Byte Of Sprite Attribute + inx // X++ + cpx.w #85 + bne LoopStarsOAMSize + +// Setup Video +lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size +sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + +lda.b #%00010001 // Enable BG1 & Sprites +sta.w REG_TM // $212C: BG1 & Sprites To Main Screen Designation + +lda.b #%00010000 // Enable Sprites +sta.w REG_TS // $212D: Sprites To Sub Screen Designation + +lda.b #$80 // No Repeat on Mode7 Screen +sta.w REG_M7SEL // $211A: Mode7 Settings + +// Reset Scale +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7D // $211E: MODE7 COSINE B +stz.w REG_M7D // $211E: MODE7 COSINE B + +ldx.w #384 // BG1HOFS = 384 +stx.b BG1ScrPosX + +ldx.w #400 // BG1VOFS = 400 +stx.b BG1ScrPosY + +ldx.w #512 // M7X = 512 +stx.b Mode7PosX + +ldx.w #512 // M7Y = 512 +stx.b Mode7PosY + +lda.b BG1ScrPosX +sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte +lda.b BG1ScrPosX + 1 +sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + +lda.b BG1ScrPosY +sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte +lda.b BG1ScrPosY + 1 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + +lda.b Mode7PosX +sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte +lda.b Mode7PosX + 1 +sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + +lda.b Mode7PosY +sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte +lda.b Mode7PosY + 1 +sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + +// Setup Blend +stz.w REG_CGWSEL // $2130: Color Math Control Register A +lda.b #%10000001 // Enable Sub Screen Backdrop Color SUB +sta.w REG_CGADSUB // $2131: Color Math Control Register B +stz.w REG_COLDATA // $2132: Color Math Sub Screen Backdrop Color (RGB Intensity) + +// Setup Sprites +lda.b #%10100010 // Object Size = 32x32/64x64, Name = 0, Base = $8000 +sta.w REG_OBSEL // $2101: Object Size & Object Base + +// HDMA OAM Size & Object Base +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP3 // $4330: DMA3 DMA/HDMA Parameters +lda.b #REG_OBSEL // $01: Start At Object Size & Object Base ($2101) +sta.w REG_BBAD3 // $4331: DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #StarsHDMATableOAM // HMDA Table Address +stx.w REG_A1T3L // $4332: DMA3 DMA/HDMA Table Start Address +lda.b #StarsHDMATableOAM >> 16 // HDMA Table Bank +sta.w REG_A1B3 // $4334: DMA3 DMA/HDMA Table Start Address (Bank) + +lda.b #%00001000 // HDMA Channel Select (Channel 3) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +FadeIN() // Screen Fade In + +lda.b #$00 // Zoom Value +xba +lda.b #$00 +LogoLoop: + WaitNMI() // Wait For Vertical Blank + + // Scale Logo + sta.w REG_M7A // $211B: MODE7 COSINE A + xba + sta.w REG_M7A // $211B: MODE7 COSINE A + xba + sta.w REG_M7D // $211E: MODE7 COSINE B + xba + sta.w REG_M7D // $211E: MODE7 COSINE B + //sta.w REG_COLDATA // $2132: Color Math Sub Screen Backdrop Color (RGB Intensity) + xba + + inc // Zoom Value Lo++ + inc // Zoom Value Lo++ + inc // Zoom Value Lo++ + inc // Zoom Value Lo++ + bne LogoLoop // IF (Zoom Value != 0) Logo Loop + xba // ELSE INC B + inc // Zoom Value Hi++ + tax // X = A + asl + ora.b #%11100000 + sta.w REG_COLDATA // $2132: Color Math Sub Screen Backdrop Color (RGB Intensity) + cmp.b #$FE // IF (RGB Intensity == $FE) Logo Finish + beq LogoFinish + txa // A = X + xba + bra LogoLoop + +StarsOAM: + // Stars 64x64) + db 0, 0, 0, %00000000 + db 64, 0, 8, %00000000 + db 128, 0, 128, %00000000 + db 192, 0, 136, %00000000 + + db 0, 64, 0, %00000001 + db 64, 64, 8, %00000001 + db 128, 64, 128, %00000001 + db 192, 64, 136, %00000001 + + db 0, 128, 0, %00000000 + db 64, 128, 8, %00000000 + db 128, 128, 128, %00000000 + db 192, 128, 136, %00000000 + + db 0, 192, 0, %00000001 + db 32, 192, 4, %00000001 + db 64, 192, 8, %00000001 + db 96, 192, 12, %00000001 + db 128, 192, 16, %00000001 + db 160, 192, 20, %00000001 + db 192, 192, 24, %00000001 + db 224, 192, 28, %00000001 + + // OAM Extra Info + db %10101010 + db %10101010 + db %10101010 + db %00000000 + db %00000000 + +StarsHDMATableOAM: + db 128, %10100010 // Repeat 40 Scanlines, Object Size = 32x32/64x64, Name = 0, Base = $8000 + db 1, %10100011 // Repeat 1 Scanlines, Object Size = 32x32/64x64, Name = 0, Base = $C000 + db 0 // End Of HDMA + +LogoFinish: \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/MODE7Calc/MODE7CalcCOS.py b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/MODE7Calc/MODE7CalcCOS.py new file mode 100644 index 00000000..f53cc884 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/MODE7Calc/MODE7CalcCOS.py @@ -0,0 +1,29 @@ +import math + +cam_pos_y = 160 # Camera Position Y + +twoPI = math.pi * 2 +points = 1 # Number Of Direction Points +angle = 0 # Direction Angle + +while angle < points: + print ("M7COSTable%d: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional)" % angle) + + g_cosf = math.cos((twoPI / points) * angle) # cos(phi) + g_sinf = math.sin((twoPI / points) * angle) # sin(phi) + + REG_VCOUNT = 1 # Scanline + + while REG_VCOUNT <= 224: + + # Zoom * Rotation + + lam = cam_pos_y / REG_VCOUNT # lam = ScaleXY + + M7_COS = g_cosf * lam # M7A & M7D = +COS(angle) * ScaleXY + + print ("db $01; dw", round(M7_COS*256), "// Repeat 1 Scanline, Mode7 +COS Scanline", REG_VCOUNT) + REG_VCOUNT += 1 + + print ("db $00 // End Of HDMA") + angle += 1 diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Scroller.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Scroller.asm new file mode 100644 index 00000000..74512647 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/Scroller.asm @@ -0,0 +1,402 @@ +//---------- +// Scroller +//---------- +LoadPAL(FontYellowPal, $00, FontYellowPal.size, 0) // Load Background Palette + +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles, $0000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$0800, $1000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$1000, $2000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$1800, $3000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$2000, $4000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$2800, $5000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$3000, $6000, $0800, 0) // Load Background Tiles To VRAM +WaitNMI() // Wait For Vertical Blank +LoadHIVRAM(FontTiles+$3800, $7000, $0800, 0) // Load Background Tiles To VRAM + +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap, $0000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$0800, $1000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$1000, $2000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$1800, $3000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$2000, $4000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$2800, $5000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$3000, $6000, $0800, 0) // Load Background Tile Map To VRAM +WaitNMI() // Wait For Vertical Blank +LoadLOVRAM(ScrollerFontMap+$3800, $7000, $0800, 0) // Load Background Tile Map To VRAM + +// Setup Video +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7A // $211B: MODE7 COSINE A +stz.w REG_M7D // $211E: MODE7 COSINE B +stz.w REG_M7D // $211E: MODE7 COSINE B + +ldx.w #384 // BG1HOFS = 384 +stx.b BG1ScrPosX + +ldx.w #-256 // BG1VOFS = -256 +stx.b BG1ScrPosY + +ldx.w #512 // M7X = 512 +stx.b Mode7PosX + +ldx.w #0 // M7Y = 0 +stx.b Mode7PosY + +lda.b BG1ScrPosX +sta.w REG_BG1HOFS // $210D: BG1 Position X Lo Byte +lda.b BG1ScrPosX + 1 +sta.w REG_BG1HOFS // $210D: BG1 Position X Hi Byte + +lda.b BG1ScrPosY +sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte +lda.b BG1ScrPosY + 1 +sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + +lda.b Mode7PosX +sta.w REG_M7X // $211F: Mode7 Center Position X Lo Byte +lda.b Mode7PosX + 1 +sta.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + +lda.b Mode7PosY +sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte +lda.b Mode7PosY + 1 +sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + +// HDMA Mode7 +COS (A) Scanline +lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice +sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters +lda.b #REG_M7A // $1B: Start At MODE7 COSINE A ($211B) +sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7COSHDMATable // HMDA Table Address +stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address +lda.b #M7COSHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + +// HDMA Mode7 +COS (D) Scanline +lda.b #%00000010 // HMDA: Write 2 Bytes Each Scanline, Repeat A/B-bus Address Twice +sta.w REG_DMAP1 // $4310: DMA1 DMA/HDMA Parameters +lda.b #REG_M7D // $1E: Start At MODE7 COSINE B ($211E) +sta.w REG_BBAD1 // $4311: DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7COSHDMATable // HMDA Table Address +stx.w REG_A1T1L // $4312: DMA1 DMA/HDMA Table Start Address +lda.b #M7COSHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B1 // $4314: DMA1 DMA/HDMA Table Start Address (Bank) + +// HDMA Mode7 Intensity +lda.b #%00000000 // HMDA: Write 1 Bytes Each Scanline +sta.w REG_DMAP2 // $4320: DMA2 DMA/HDMA Parameters +lda.b #REG_COLDATA // $32: Start At Color Math Sub Screen Backdrop Color ($2132) +sta.w REG_BBAD2 // $4321: DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) +ldx.w #M7IntensityHDMATable // HMDA Table Address +stx.w REG_A1T2L // $4322: DMA2 DMA/HDMA Table Start Address +lda.b #M7IntensityHDMATable >> 16 // HDMA Table Bank +sta.w REG_A1B2 // $4324: DMA2 DMA/HDMA Table Start Address (Bank) + +lda.b #%00001111 // HDMA Channel Select (Channel 0..3) +sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + +ScrollerLoop: + WaitNMI() // Wait For Vertical Blank + + lda.b BG1ScrPosY + sta.w REG_BG1VOFS // $210E: BG1 Position Y Lo Byte + lda.b BG1ScrPosY + 1 + sta.w REG_BG1VOFS // $210E: BG1 Position Y Hi Byte + + lda.b Mode7PosY + sta.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + lda.b Mode7PosY + 1 + sta.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + ldx.b BG1ScrPosY // Increment BG1 Y Pos + inx + stx.b BG1ScrPosY + + ldx.b Mode7PosY // Increment Mode7 Y Pos + inx + stx.b Mode7PosY + + cpx.w #$600 // IF (Mode7Pos != $600) Loop Scroller + bne ScrollerLoop + +FadeOUT() // Screen Fade Out + +lda.b #$80 +sta.w REG_INIDISP // $80: Turn Off Screen, Zero Brightness ($2100) + +jmp Start // Loop Demo + +M7IntensityHDMATable: + db 32, %11111111 // Repeat 32 Scanlines, RGB Intensity 31 + db 1, %11111110 // Repeat 1 Scanlines, RGB Intensity 30 + db 1, %11111101 // Repeat 1 Scanlines, RGB Intensity 29 + db 1, %11111100 // Repeat 1 Scanlines, RGB Intensity 28 + db 1, %11111011 // Repeat 1 Scanlines, RGB Intensity 27 + db 1, %11111010 // Repeat 1 Scanlines, RGB Intensity 26 + db 1, %11111001 // Repeat 1 Scanlines, RGB Intensity 25 + db 1, %11111000 // Repeat 1 Scanlines, RGB Intensity 24 + db 1, %11110111 // Repeat 1 Scanlines, RGB Intensity 23 + db 1, %11110110 // Repeat 1 Scanlines, RGB Intensity 22 + db 1, %11110101 // Repeat 1 Scanlines, RGB Intensity 21 + db 1, %11110100 // Repeat 1 Scanlines, RGB Intensity 20 + db 1, %11110011 // Repeat 1 Scanlines, RGB Intensity 19 + db 1, %11110010 // Repeat 1 Scanlines, RGB Intensity 18 + db 1, %11110001 // Repeat 1 Scanlines, RGB Intensity 17 + db 2, %11110000 // Repeat 2 Scanlines, RGB Intensity 16 + db 2, %11101111 // Repeat 2 Scanlines, RGB Intensity 15 + db 2, %11101110 // Repeat 2 Scanlines, RGB Intensity 14 + db 2, %11101101 // Repeat 2 Scanlines, RGB Intensity 13 + db 2, %11101100 // Repeat 2 Scanlines, RGB Intensity 12 + db 2, %11101011 // Repeat 2 Scanlines, RGB Intensity 11 + db 2, %11101010 // Repeat 2 Scanlines, RGB Intensity 10 + db 2, %11101001 // Repeat 2 Scanlines, RGB Intensity 9 + db 2, %11101000 // Repeat 2 Scanlines, RGB Intensity 8 + db 2, %11100111 // Repeat 2 Scanlines, RGB Intensity 7 + db 2, %11100110 // Repeat 2 Scanlines, RGB Intensity 6 + db 2, %11100101 // Repeat 2 Scanlines, RGB Intensity 5 + db 2, %11100100 // Repeat 2 Scanlines, RGB Intensity 4 + db 2, %11100011 // Repeat 2 Scanlines, RGB Intensity 3 + db 2, %11100010 // Repeat 2 Scanlines, RGB Intensity 2 + db 2, %11100001 // Repeat 2 Scanlines, RGB Intensity 1 + db 1, %00000000 // Repeat 1 Scanlines, RGB Intensity 0 + db 0 // End Of HDMA + +M7COSHDMATable: // Mode7 +COS (A & D) Table 224 * Rotation / Scaling Ratios (Last 8-Bits Fractional) +db $01; dw 40960 // Repeat 1 Scanline, Mode7 +COS Scanline 1 +db $01; dw 20480 // Repeat 1 Scanline, Mode7 +COS Scanline 2 +db $01; dw 13653 // Repeat 1 Scanline, Mode7 +COS Scanline 3 +db $01; dw 10240 // Repeat 1 Scanline, Mode7 +COS Scanline 4 +db $01; dw 8192 // Repeat 1 Scanline, Mode7 +COS Scanline 5 +db $01; dw 6827 // Repeat 1 Scanline, Mode7 +COS Scanline 6 +db $01; dw 5851 // Repeat 1 Scanline, Mode7 +COS Scanline 7 +db $01; dw 5120 // Repeat 1 Scanline, Mode7 +COS Scanline 8 +db $01; dw 4551 // Repeat 1 Scanline, Mode7 +COS Scanline 9 +db $01; dw 4096 // Repeat 1 Scanline, Mode7 +COS Scanline 10 +db $01; dw 3724 // Repeat 1 Scanline, Mode7 +COS Scanline 11 +db $01; dw 3413 // Repeat 1 Scanline, Mode7 +COS Scanline 12 +db $01; dw 3151 // Repeat 1 Scanline, Mode7 +COS Scanline 13 +db $01; dw 2926 // Repeat 1 Scanline, Mode7 +COS Scanline 14 +db $01; dw 2731 // Repeat 1 Scanline, Mode7 +COS Scanline 15 +db $01; dw 2560 // Repeat 1 Scanline, Mode7 +COS Scanline 16 +db $01; dw 2409 // Repeat 1 Scanline, Mode7 +COS Scanline 17 +db $01; dw 2276 // Repeat 1 Scanline, Mode7 +COS Scanline 18 +db $01; dw 2156 // Repeat 1 Scanline, Mode7 +COS Scanline 19 +db $01; dw 2048 // Repeat 1 Scanline, Mode7 +COS Scanline 20 +db $01; dw 1950 // Repeat 1 Scanline, Mode7 +COS Scanline 21 +db $01; dw 1862 // Repeat 1 Scanline, Mode7 +COS Scanline 22 +db $01; dw 1781 // Repeat 1 Scanline, Mode7 +COS Scanline 23 +db $01; dw 1707 // Repeat 1 Scanline, Mode7 +COS Scanline 24 +db $01; dw 1638 // Repeat 1 Scanline, Mode7 +COS Scanline 25 +db $01; dw 1575 // Repeat 1 Scanline, Mode7 +COS Scanline 26 +db $01; dw 1517 // Repeat 1 Scanline, Mode7 +COS Scanline 27 +db $01; dw 1463 // Repeat 1 Scanline, Mode7 +COS Scanline 28 +db $01; dw 1412 // Repeat 1 Scanline, Mode7 +COS Scanline 29 +db $01; dw 1365 // Repeat 1 Scanline, Mode7 +COS Scanline 30 +db $01; dw 1321 // Repeat 1 Scanline, Mode7 +COS Scanline 31 +db $01; dw 1280 // Repeat 1 Scanline, Mode7 +COS Scanline 32 +db $01; dw 1241 // Repeat 1 Scanline, Mode7 +COS Scanline 33 +db $01; dw 1205 // Repeat 1 Scanline, Mode7 +COS Scanline 34 +db $01; dw 1170 // Repeat 1 Scanline, Mode7 +COS Scanline 35 +db $01; dw 1138 // Repeat 1 Scanline, Mode7 +COS Scanline 36 +db $01; dw 1107 // Repeat 1 Scanline, Mode7 +COS Scanline 37 +db $01; dw 1078 // Repeat 1 Scanline, Mode7 +COS Scanline 38 +db $01; dw 1050 // Repeat 1 Scanline, Mode7 +COS Scanline 39 +db $01; dw 1024 // Repeat 1 Scanline, Mode7 +COS Scanline 40 +db $01; dw 999 // Repeat 1 Scanline, Mode7 +COS Scanline 41 +db $01; dw 975 // Repeat 1 Scanline, Mode7 +COS Scanline 42 +db $01; dw 953 // Repeat 1 Scanline, Mode7 +COS Scanline 43 +db $01; dw 931 // Repeat 1 Scanline, Mode7 +COS Scanline 44 +db $01; dw 910 // Repeat 1 Scanline, Mode7 +COS Scanline 45 +db $01; dw 890 // Repeat 1 Scanline, Mode7 +COS Scanline 46 +db $01; dw 871 // Repeat 1 Scanline, Mode7 +COS Scanline 47 +db $01; dw 853 // Repeat 1 Scanline, Mode7 +COS Scanline 48 +db $01; dw 836 // Repeat 1 Scanline, Mode7 +COS Scanline 49 +db $01; dw 819 // Repeat 1 Scanline, Mode7 +COS Scanline 50 +db $01; dw 803 // Repeat 1 Scanline, Mode7 +COS Scanline 51 +db $01; dw 788 // Repeat 1 Scanline, Mode7 +COS Scanline 52 +db $01; dw 773 // Repeat 1 Scanline, Mode7 +COS Scanline 53 +db $01; dw 759 // Repeat 1 Scanline, Mode7 +COS Scanline 54 +db $01; dw 745 // Repeat 1 Scanline, Mode7 +COS Scanline 55 +db $01; dw 731 // Repeat 1 Scanline, Mode7 +COS Scanline 56 +db $01; dw 719 // Repeat 1 Scanline, Mode7 +COS Scanline 57 +db $01; dw 706 // Repeat 1 Scanline, Mode7 +COS Scanline 58 +db $01; dw 694 // Repeat 1 Scanline, Mode7 +COS Scanline 59 +db $01; dw 683 // Repeat 1 Scanline, Mode7 +COS Scanline 60 +db $01; dw 671 // Repeat 1 Scanline, Mode7 +COS Scanline 61 +db $01; dw 661 // Repeat 1 Scanline, Mode7 +COS Scanline 62 +db $01; dw 650 // Repeat 1 Scanline, Mode7 +COS Scanline 63 +db $01; dw 640 // Repeat 1 Scanline, Mode7 +COS Scanline 64 +db $01; dw 630 // Repeat 1 Scanline, Mode7 +COS Scanline 65 +db $01; dw 621 // Repeat 1 Scanline, Mode7 +COS Scanline 66 +db $01; dw 611 // Repeat 1 Scanline, Mode7 +COS Scanline 67 +db $01; dw 602 // Repeat 1 Scanline, Mode7 +COS Scanline 68 +db $01; dw 594 // Repeat 1 Scanline, Mode7 +COS Scanline 69 +db $01; dw 585 // Repeat 1 Scanline, Mode7 +COS Scanline 70 +db $01; dw 577 // Repeat 1 Scanline, Mode7 +COS Scanline 71 +db $01; dw 569 // Repeat 1 Scanline, Mode7 +COS Scanline 72 +db $01; dw 561 // Repeat 1 Scanline, Mode7 +COS Scanline 73 +db $01; dw 554 // Repeat 1 Scanline, Mode7 +COS Scanline 74 +db $01; dw 546 // Repeat 1 Scanline, Mode7 +COS Scanline 75 +db $01; dw 539 // Repeat 1 Scanline, Mode7 +COS Scanline 76 +db $01; dw 532 // Repeat 1 Scanline, Mode7 +COS Scanline 77 +db $01; dw 525 // Repeat 1 Scanline, Mode7 +COS Scanline 78 +db $01; dw 518 // Repeat 1 Scanline, Mode7 +COS Scanline 79 +db $01; dw 512 // Repeat 1 Scanline, Mode7 +COS Scanline 80 +db $01; dw 506 // Repeat 1 Scanline, Mode7 +COS Scanline 81 +db $01; dw 500 // Repeat 1 Scanline, Mode7 +COS Scanline 82 +db $01; dw 493 // Repeat 1 Scanline, Mode7 +COS Scanline 83 +db $01; dw 488 // Repeat 1 Scanline, Mode7 +COS Scanline 84 +db $01; dw 482 // Repeat 1 Scanline, Mode7 +COS Scanline 85 +db $01; dw 476 // Repeat 1 Scanline, Mode7 +COS Scanline 86 +db $01; dw 471 // Repeat 1 Scanline, Mode7 +COS Scanline 87 +db $01; dw 465 // Repeat 1 Scanline, Mode7 +COS Scanline 88 +db $01; dw 460 // Repeat 1 Scanline, Mode7 +COS Scanline 89 +db $01; dw 455 // Repeat 1 Scanline, Mode7 +COS Scanline 90 +db $01; dw 450 // Repeat 1 Scanline, Mode7 +COS Scanline 91 +db $01; dw 445 // Repeat 1 Scanline, Mode7 +COS Scanline 92 +db $01; dw 440 // Repeat 1 Scanline, Mode7 +COS Scanline 93 +db $01; dw 436 // Repeat 1 Scanline, Mode7 +COS Scanline 94 +db $01; dw 431 // Repeat 1 Scanline, Mode7 +COS Scanline 95 +db $01; dw 427 // Repeat 1 Scanline, Mode7 +COS Scanline 96 +db $01; dw 422 // Repeat 1 Scanline, Mode7 +COS Scanline 97 +db $01; dw 418 // Repeat 1 Scanline, Mode7 +COS Scanline 98 +db $01; dw 414 // Repeat 1 Scanline, Mode7 +COS Scanline 99 +db $01; dw 410 // Repeat 1 Scanline, Mode7 +COS Scanline 100 +db $01; dw 406 // Repeat 1 Scanline, Mode7 +COS Scanline 101 +db $01; dw 402 // Repeat 1 Scanline, Mode7 +COS Scanline 102 +db $01; dw 398 // Repeat 1 Scanline, Mode7 +COS Scanline 103 +db $01; dw 394 // Repeat 1 Scanline, Mode7 +COS Scanline 104 +db $01; dw 390 // Repeat 1 Scanline, Mode7 +COS Scanline 105 +db $01; dw 386 // Repeat 1 Scanline, Mode7 +COS Scanline 106 +db $01; dw 383 // Repeat 1 Scanline, Mode7 +COS Scanline 107 +db $01; dw 379 // Repeat 1 Scanline, Mode7 +COS Scanline 108 +db $01; dw 376 // Repeat 1 Scanline, Mode7 +COS Scanline 109 +db $01; dw 372 // Repeat 1 Scanline, Mode7 +COS Scanline 110 +db $01; dw 369 // Repeat 1 Scanline, Mode7 +COS Scanline 111 +db $01; dw 366 // Repeat 1 Scanline, Mode7 +COS Scanline 112 +db $01; dw 362 // Repeat 1 Scanline, Mode7 +COS Scanline 113 +db $01; dw 359 // Repeat 1 Scanline, Mode7 +COS Scanline 114 +db $01; dw 356 // Repeat 1 Scanline, Mode7 +COS Scanline 115 +db $01; dw 353 // Repeat 1 Scanline, Mode7 +COS Scanline 116 +db $01; dw 350 // Repeat 1 Scanline, Mode7 +COS Scanline 117 +db $01; dw 347 // Repeat 1 Scanline, Mode7 +COS Scanline 118 +db $01; dw 344 // Repeat 1 Scanline, Mode7 +COS Scanline 119 +db $01; dw 341 // Repeat 1 Scanline, Mode7 +COS Scanline 120 +db $01; dw 339 // Repeat 1 Scanline, Mode7 +COS Scanline 121 +db $01; dw 336 // Repeat 1 Scanline, Mode7 +COS Scanline 122 +db $01; dw 333 // Repeat 1 Scanline, Mode7 +COS Scanline 123 +db $01; dw 330 // Repeat 1 Scanline, Mode7 +COS Scanline 124 +db $01; dw 328 // Repeat 1 Scanline, Mode7 +COS Scanline 125 +db $01; dw 325 // Repeat 1 Scanline, Mode7 +COS Scanline 126 +db $01; dw 323 // Repeat 1 Scanline, Mode7 +COS Scanline 127 +db $01; dw 320 // Repeat 1 Scanline, Mode7 +COS Scanline 128 +db $01; dw 318 // Repeat 1 Scanline, Mode7 +COS Scanline 129 +db $01; dw 315 // Repeat 1 Scanline, Mode7 +COS Scanline 130 +db $01; dw 313 // Repeat 1 Scanline, Mode7 +COS Scanline 131 +db $01; dw 310 // Repeat 1 Scanline, Mode7 +COS Scanline 132 +db $01; dw 308 // Repeat 1 Scanline, Mode7 +COS Scanline 133 +db $01; dw 306 // Repeat 1 Scanline, Mode7 +COS Scanline 134 +db $01; dw 303 // Repeat 1 Scanline, Mode7 +COS Scanline 135 +db $01; dw 301 // Repeat 1 Scanline, Mode7 +COS Scanline 136 +db $01; dw 299 // Repeat 1 Scanline, Mode7 +COS Scanline 137 +db $01; dw 297 // Repeat 1 Scanline, Mode7 +COS Scanline 138 +db $01; dw 295 // Repeat 1 Scanline, Mode7 +COS Scanline 139 +db $01; dw 293 // Repeat 1 Scanline, Mode7 +COS Scanline 140 +db $01; dw 290 // Repeat 1 Scanline, Mode7 +COS Scanline 141 +db $01; dw 288 // Repeat 1 Scanline, Mode7 +COS Scanline 142 +db $01; dw 286 // Repeat 1 Scanline, Mode7 +COS Scanline 143 +db $01; dw 284 // Repeat 1 Scanline, Mode7 +COS Scanline 144 +db $01; dw 282 // Repeat 1 Scanline, Mode7 +COS Scanline 145 +db $01; dw 281 // Repeat 1 Scanline, Mode7 +COS Scanline 146 +db $01; dw 279 // Repeat 1 Scanline, Mode7 +COS Scanline 147 +db $01; dw 277 // Repeat 1 Scanline, Mode7 +COS Scanline 148 +db $01; dw 275 // Repeat 1 Scanline, Mode7 +COS Scanline 149 +db $01; dw 273 // Repeat 1 Scanline, Mode7 +COS Scanline 150 +db $01; dw 271 // Repeat 1 Scanline, Mode7 +COS Scanline 151 +db $01; dw 269 // Repeat 1 Scanline, Mode7 +COS Scanline 152 +db $01; dw 268 // Repeat 1 Scanline, Mode7 +COS Scanline 153 +db $01; dw 266 // Repeat 1 Scanline, Mode7 +COS Scanline 154 +db $01; dw 264 // Repeat 1 Scanline, Mode7 +COS Scanline 155 +db $01; dw 263 // Repeat 1 Scanline, Mode7 +COS Scanline 156 +db $01; dw 261 // Repeat 1 Scanline, Mode7 +COS Scanline 157 +db $01; dw 259 // Repeat 1 Scanline, Mode7 +COS Scanline 158 +db $01; dw 258 // Repeat 1 Scanline, Mode7 +COS Scanline 159 +db $01; dw 256 // Repeat 1 Scanline, Mode7 +COS Scanline 160 +db $01; dw 254 // Repeat 1 Scanline, Mode7 +COS Scanline 161 +db $01; dw 253 // Repeat 1 Scanline, Mode7 +COS Scanline 162 +db $01; dw 251 // Repeat 1 Scanline, Mode7 +COS Scanline 163 +db $01; dw 250 // Repeat 1 Scanline, Mode7 +COS Scanline 164 +db $01; dw 248 // Repeat 1 Scanline, Mode7 +COS Scanline 165 +db $01; dw 247 // Repeat 1 Scanline, Mode7 +COS Scanline 166 +db $01; dw 245 // Repeat 1 Scanline, Mode7 +COS Scanline 167 +db $01; dw 244 // Repeat 1 Scanline, Mode7 +COS Scanline 168 +db $01; dw 242 // Repeat 1 Scanline, Mode7 +COS Scanline 169 +db $01; dw 241 // Repeat 1 Scanline, Mode7 +COS Scanline 170 +db $01; dw 240 // Repeat 1 Scanline, Mode7 +COS Scanline 171 +db $01; dw 238 // Repeat 1 Scanline, Mode7 +COS Scanline 172 +db $01; dw 237 // Repeat 1 Scanline, Mode7 +COS Scanline 173 +db $01; dw 235 // Repeat 1 Scanline, Mode7 +COS Scanline 174 +db $01; dw 234 // Repeat 1 Scanline, Mode7 +COS Scanline 175 +db $01; dw 233 // Repeat 1 Scanline, Mode7 +COS Scanline 176 +db $01; dw 231 // Repeat 1 Scanline, Mode7 +COS Scanline 177 +db $01; dw 230 // Repeat 1 Scanline, Mode7 +COS Scanline 178 +db $01; dw 229 // Repeat 1 Scanline, Mode7 +COS Scanline 179 +db $01; dw 228 // Repeat 1 Scanline, Mode7 +COS Scanline 180 +db $01; dw 226 // Repeat 1 Scanline, Mode7 +COS Scanline 181 +db $01; dw 225 // Repeat 1 Scanline, Mode7 +COS Scanline 182 +db $01; dw 224 // Repeat 1 Scanline, Mode7 +COS Scanline 183 +db $01; dw 223 // Repeat 1 Scanline, Mode7 +COS Scanline 184 +db $01; dw 221 // Repeat 1 Scanline, Mode7 +COS Scanline 185 +db $01; dw 220 // Repeat 1 Scanline, Mode7 +COS Scanline 186 +db $01; dw 219 // Repeat 1 Scanline, Mode7 +COS Scanline 187 +db $01; dw 218 // Repeat 1 Scanline, Mode7 +COS Scanline 188 +db $01; dw 217 // Repeat 1 Scanline, Mode7 +COS Scanline 189 +db $01; dw 216 // Repeat 1 Scanline, Mode7 +COS Scanline 190 +db $01; dw 214 // Repeat 1 Scanline, Mode7 +COS Scanline 191 +db $01; dw 213 // Repeat 1 Scanline, Mode7 +COS Scanline 192 +db $01; dw 212 // Repeat 1 Scanline, Mode7 +COS Scanline 193 +db $01; dw 211 // Repeat 1 Scanline, Mode7 +COS Scanline 194 +db $01; dw 210 // Repeat 1 Scanline, Mode7 +COS Scanline 195 +db $01; dw 209 // Repeat 1 Scanline, Mode7 +COS Scanline 196 +db $01; dw 208 // Repeat 1 Scanline, Mode7 +COS Scanline 197 +db $01; dw 207 // Repeat 1 Scanline, Mode7 +COS Scanline 198 +db $01; dw 206 // Repeat 1 Scanline, Mode7 +COS Scanline 199 +db $01; dw 205 // Repeat 1 Scanline, Mode7 +COS Scanline 200 +db $01; dw 204 // Repeat 1 Scanline, Mode7 +COS Scanline 201 +db $01; dw 203 // Repeat 1 Scanline, Mode7 +COS Scanline 202 +db $01; dw 202 // Repeat 1 Scanline, Mode7 +COS Scanline 203 +db $01; dw 201 // Repeat 1 Scanline, Mode7 +COS Scanline 204 +db $01; dw 200 // Repeat 1 Scanline, Mode7 +COS Scanline 205 +db $01; dw 199 // Repeat 1 Scanline, Mode7 +COS Scanline 206 +db $01; dw 198 // Repeat 1 Scanline, Mode7 +COS Scanline 207 +db $01; dw 197 // Repeat 1 Scanline, Mode7 +COS Scanline 208 +db $01; dw 196 // Repeat 1 Scanline, Mode7 +COS Scanline 209 +db $01; dw 195 // Repeat 1 Scanline, Mode7 +COS Scanline 210 +db $01; dw 194 // Repeat 1 Scanline, Mode7 +COS Scanline 211 +db $01; dw 193 // Repeat 1 Scanline, Mode7 +COS Scanline 212 +db $01; dw 192 // Repeat 1 Scanline, Mode7 +COS Scanline 213 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 214 +db $01; dw 191 // Repeat 1 Scanline, Mode7 +COS Scanline 215 +db $01; dw 190 // Repeat 1 Scanline, Mode7 +COS Scanline 216 +db $01; dw 189 // Repeat 1 Scanline, Mode7 +COS Scanline 217 +db $01; dw 188 // Repeat 1 Scanline, Mode7 +COS Scanline 218 +db $01; dw 187 // Repeat 1 Scanline, Mode7 +COS Scanline 219 +db $01; dw 186 // Repeat 1 Scanline, Mode7 +COS Scanline 220 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 221 +db $01; dw 185 // Repeat 1 Scanline, Mode7 +COS Scanline 222 +db $01; dw 184 // Repeat 1 Scanline, Mode7 +COS Scanline 223 +db $01; dw 183 // Repeat 1 Scanline, Mode7 +COS Scanline 224 +db $00 // End Of HDMA \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.asm b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.asm new file mode 100644 index 00000000..237724a5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.asm @@ -0,0 +1,627 @@ +// SNES Star Wars demo by krom (Peter Lemon): +arch snes.cpu +output "StarWars.sfc", create + +macro TextMap(OFFSET, SIZE, TEXT) { + variable offset({OFFSET}) + + // Map Font HI + map ' ', $00 + map 'W', $030201 + map 'A', $0504 + map 'B', $0706 + map 'C', $0908 + map 'D', $0B0A + map 'E', $0D0C + map 'F', $0F0E + map 'G', $2120 + map 'H', $2322 + map 'I', $24 + map 'J', $25 + map 'K', $2726 + map 'L', $2928 + map 'M', $2B2A + map 'N', $2D2C + map 'O', $2F2E + map 'P', $4140 + map 'R', $4342 + map 'S', $4544 + map 'T', $4746 + map 'U', $4948 + map 'V', $4B4A + map 'X', $4D4C + map 'Y', $4F4E + map 'Z', $6160 + map 'a', $6362 + map 'b', $6564 + map 'c', $6766 + map 'd', $6968 + map 'e', $6B6A + map 'f', $6C + map 'h', $6E6D + map 'i', $6F + map 'k', $8180 + map 'l', $82 + map 'm', $8483 + map 'n', $8685 + map 'o', $8887 + map 'r', $89 + map 's', $8B8A + map 't', $8C + map 'u', $8E8D + map $2C, $00 // map ',' + map 'v', $A1A0 + map 'w', $A3A2 + map 'x', $A5A4 + map 'g', $A7A6 + map 'p', $A9A8 + map 'q', $ABAA + map 'y', $ADAC + map 'Q', $AFAE + map '@', $CAC9 + map '.', $00 + map ':', $CE // Combine 2 Full Stops + map $3B, $CE // Combine Full Stop & Comma (map ';') + map 'z', $C1C0 + map '!', $C2 + map '?', $C4C3 + map '-', $00 + map '_', $0000 + map '&', $E1E0 + map '*', $E3E2 + map '`', $E4 + map '+', $E6E5 + map 'j', $D7 + map '\s', $F8 // map "'" + map '\', $00D8 + map '/', $DB00 + map '\d', $FB // map '"' + map '(', $DC + map ')', $DD + map '[', $DE + map ']', $DF + + origin offset // Offset + {SIZE} {TEXT} + + // Map Font MID + map ' ', $00 + map 'W', $131211 + map 'A', $1514 + map 'B', $1716 + map 'C', $1918 + map 'D', $1B1A + map 'E', $1D1C + map 'F', $1F1E + map 'G', $3130 + map 'H', $3332 + map 'I', $34 + map 'J', $35 + map 'K', $3736 + map 'L', $3938 + map 'M', $3B3A + map 'N', $3D3C + map 'O', $3F3E + map 'P', $5150 + map 'R', $5352 + map 'S', $5554 + map 'T', $5756 + map 'U', $5958 + map 'V', $5B5A + map 'X', $5D5C + map 'Y', $5F5E + map 'Z', $7170 + map 'a', $7372 + map 'b', $7574 + map 'c', $7776 + map 'd', $7978 + map 'e', $7B7A + map 'f', $7C + map 'h', $7E7D + map 'i', $7F + map 'k', $9190 + map 'l', $92 + map 'm', $9493 + map 'n', $9695 + map 'o', $9897 + map 'r', $99 + map 's', $9B9A + map 't', $9C + map 'u', $9E9D + map $2C, $8F // map ',' + map 'v', $B1B0 + map 'w', $B3B2 + map 'x', $B5B4 + map 'g', $B7B6 + map 'p', $B9B8 + map 'q', $BBBA + map 'y', $BDBC + map 'Q', $BFBE + map '@', $DAD9 + map '.', $CE + map ':', $CE // Combine 2 Full Stops + map $3B, $8F // Combine Full Stop & Comma (map ';') + map 'z', $D1D0 + map '!', $D2 + map '?', $D4D3 + map '-', $C5 + map '_', $0000 + map '&', $F1F0 + map '*', $F3F2 + map '`', $F4 + map '+', $F6F5 + map 'j', $E7 + map '\s', $00 // map "'" + map '\', $E9E8 + map '/', $EBEA + map '\d', $00 // map '"' + map '(', $EC + map ')', $ED + map '[', $EE + map ']', $EF + + origin offset+128 // Offset + {SIZE} {TEXT} + + // Map Font LO + map ' ', $00 + map 'W', $000000 + map 'A', $0000 + map 'B', $0000 + map 'C', $0000 + map 'D', $0000 + map 'E', $0000 + map 'F', $0000 + map 'G', $0000 + map 'H', $0000 + map 'I', $00 + map 'J', $00 + map 'K', $0000 + map 'L', $0000 + map 'M', $0000 + map 'N', $0000 + map 'O', $0000 + map 'P', $0000 + map 'R', $0000 + map 'S', $0000 + map 'T', $0000 + map 'U', $0000 + map 'V', $0000 + map 'X', $0000 + map 'Y', $0000 + map 'Z', $0000 + map 'a', $0000 + map 'b', $0000 + map 'c', $0000 + map 'd', $0000 + map 'e', $0000 + map 'f', $00 + map 'h', $0000 + map 'i', $00 + map 'k', $0000 + map 'l', $00 + map 'm', $0000 + map 'n', $0000 + map 'o', $0000 + map 'r', $00 + map 's', $0000 + map 't', $00 + map 'u', $0000 + map $2C, $9F // map ',' + map 'v', $0000 + map 'w', $0000 + map 'x', $0000 + map 'g', $C7C6 + map 'p', $00C8 + map 'q', $CB00 + map 'y', $CDCC + map 'Q', $CF00 + map '@', $0000 + map '.', $00 + map ':', $00 // Combine 2 Full Stops + map $3B, $9F // Combine Full Stop & Comma (map ';') + map 'z', $0000 + map '!', $00 + map '?', $0000 + map '-', $00 // C5 + map '_', $D6D5 + map '&', $0000 + map '*', $0000 + map '`', $00 + map '+', $0000 + map 'j', $F7 + map '\s', $00 // map "'" + map '\', $F900 + map '/', $00FA + map '\d', $00 // map '"' + map '(', $FC + map ')', $FD + map '[', $FE + map ']', $FF + + origin offset+256 // Offset + {SIZE} {TEXT} +} + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $20000 // Fill Upto $1FFFF (Bank 4) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +CourseCharacterSelect: + db %00000000 // Course Select (0=Easy, 1=Normal, 2=Hard, 3=Very Hard), Character Select (4=Roocho, 5=Beochi, 6=Chito, 7=Golem) Byte +Mode7PosX: + dw 0 // Mode7 Center Position X Word +Mode7PosY: + dw 0 // Mode7 Center Position Y Word +BG1ScrPosX: + dw 0 // Mode7 BG1 Scroll Position X Word +BG1ScrPosY: + dw 0 // Mode7 BG1 Scroll Position Y Word +StageMapOffset: + dw 0 // Stage Map Offset Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + //------- + // Intro + //------- + include "Intro.asm" // Include Intro Routine + + //------ + // Logo + //------ + include "Logo.asm" // Include Logo Routine + + //---------- + // Scroller + //---------- + include "Scroller.asm" // Include Scroller Routine + +Loop: + jmp Loop + +// Palette Data +// BANK 0 +insert LogoPal, "GFX/StarWarsLogo.pal" // Include BG Palette Data (6 Bytes) +insert FontBluePal, "GFX/StarWarsFontBlue.pal" // Include BG Palette Data (64 Bytes) +insert FontYellowPal, "GFX/StarWarsFontYellow.pal" // Include BG Palette Data (64 Bytes) + +// Character Data +// BANK 1 +seek($18000) +insert LogoTiles, "GFX/StarWarsLogo.pic" // Include BG Tile Data (16384 Bytes) +insert LogoMap, "GFX/StarWarsLogo.map" // Include BG Map Data (16384 Bytes) + +// Character Data +// BANK 2 +seek($28000) +insert FontTiles, "GFX/StarWarsFont.pic" // Include BG Tile Data (16384 Bytes) + +ScrollerFontMap: + TextMap(origin()+42, db, "It i") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "pe") + TextMap(origin()-256, db, "ri") + TextMap(origin()-256, dw, "od") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, "f ") + TextMap(origin()-256, dw, "c") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "v") + TextMap(origin()-256, db, "il ") + TextMap(origin()-256, dw, "wa") + TextMap(origin()-256, db, "r.") + + TextMap(origin()+212, dw, "Rebe") + TextMap(origin()-256, db, "l ") + TextMap(origin()-256, dw, "spacesh") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "ps") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, "tri") + TextMap(origin()-256, dw, "k") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "ng") + + TextMap(origin()+212, db, "fr") + TextMap(origin()-256, dw, "om") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "h") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "dden") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "base") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, dw, "have") + + TextMap(origin()+212, dw, "won") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, "ir") + TextMap(origin()-256, db, " fir") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, "t ") + TextMap(origin()-256, dw, "v") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "c") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "y") + + TextMap(origin()+212, dw, "aga") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "ns") + TextMap(origin()-256, db, "t t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "ev") + TextMap(origin()-256, db, "il ") + TextMap(origin()-256, dw, "Ga") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "ac") + TextMap(origin()-256, db, "ti") + TextMap(origin()-256, dw, "c") + + TextMap(origin()+212, dw, "Emp") + TextMap(origin()-256, db, "ir") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, ".") + + TextMap(origin()+757, dw, "Du") + TextMap(origin()-256, db, "ri") + TextMap(origin()-256, dw, "ng") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "ba") + TextMap(origin()-256, db, "ttl") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "ebe") + TextMap(origin()-256, db, "l") + + TextMap(origin()+212, dw, "sp") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "es") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "managed") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "ea") + TextMap(origin()-256, db, "l") + + TextMap(origin()+212, dw, "sec") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, "t ") + TextMap(origin()-256, dw, "p") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "ans") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "Emp") + TextMap(origin()-256, db, "ir") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "s") + + TextMap(origin()-515, db, ",") + + TextMap(origin()+470, dw, "u") + TextMap(origin()-256, db, " l t i ") + TextMap(origin()-256, dw, "m") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, " t ") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "weapon") + TextMap(origin()-256, db, ", t") + TextMap(origin()-256, dw, "he") + + TextMap(origin()+212, dw, "DEATH") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "STAR") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, dw, "an") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "mo") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "ed") + + TextMap(origin()+212, dw, "space") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, "ti") + TextMap(origin()-256, dw, "on") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "w") + TextMap(origin()-256, db, "it") + TextMap(origin()-256, dw, "h") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "enough") + + TextMap(origin()+212, dw, "powe") + TextMap(origin()-256, db, "r t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "des") + TextMap(origin()-256, db, "tr") + TextMap(origin()-256, dw, "oy") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "an") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "en") + TextMap(origin()-256, db, "tir") + TextMap(origin()-256, dw, "e") + + TextMap(origin()+212, dw, "p") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "ane") + TextMap(origin()-256, db, "t.") + + TextMap(origin()+757, dw, "Pu") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "sued") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "by") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "Emp") + TextMap(origin()-256, db, "ir") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "s") + + TextMap(origin()-515, db, ",") + + TextMap(origin()+470, dw, "s") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "n") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, "r ") + TextMap(origin()-256, dw, "agen") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "s") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, dw, "P") + TextMap(origin()-256, db, "ri") + TextMap(origin()-256, dw, "ncess") + + TextMap(origin()+212, dw, "Le") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, " r") + TextMap(origin()-256, dw, "aces") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "home") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "aboa") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "d") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, "r") + + TextMap(origin()+212, dw, "s") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "sh") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "p") + TextMap(origin()-256, db, ", ") + TextMap(origin()-256, dw, "cus") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "od") + TextMap(origin()-256, db, "i") + TextMap(origin()-256, dw, "an") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, "f t") + TextMap(origin()-256, dw, "he") + + TextMap(origin()+212, dw, "s") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "en") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "p") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "ans") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "ha") + TextMap(origin()-256, db, "t ") + TextMap(origin()-256, dw, "can") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "save") + + TextMap(origin()+212, dw, "he") + TextMap(origin()-256, db, "r ") + TextMap(origin()-256, dw, "peop") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "e") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "and") + TextMap(origin()-256, db, " r") + TextMap(origin()-256, dw, "es") + TextMap(origin()-256, db, "t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, "r") + TextMap(origin()-256, dw, "e") + + TextMap(origin()+212, db, "fr") + TextMap(origin()-256, dw, "eedom") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "o") + TextMap(origin()-256, db, " t") + TextMap(origin()-256, dw, "he") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "ga") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "axy") + TextMap(origin()-256, db, "....") + +// BANK 3 +seek($38000) +insert StarsPal, "GFX/StarWarsStars.pal" // Include BG Palette Data (32 Bytes) +insert StarsTiles, "GFX/StarWarsStars.pic" // Include BG Tile Data (28672 Bytes) + +IntroFontMap: + TextMap(origin()+39, dw, "A") + TextMap(origin()-256, db, " l") + TextMap(origin()-256, dw, "ong") + TextMap(origin()-256, db, " ti") + TextMap(origin()-256, dw, "me") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "ago") + TextMap(origin()-256, db, " i") + TextMap(origin()-256, dw, "n") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, " ") + TextMap(origin()-256, dw, "ga") + TextMap(origin()-256, db, "l") + TextMap(origin()-256, dw, "axy") + TextMap(origin()-256, db, " f") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, "r,") + + TextMap(origin()+207, db, "f") + TextMap(origin()-256, dw, "a") + TextMap(origin()-256, db, "r ") + TextMap(origin()-256, dw, "away") + TextMap(origin()-256, db, "....") \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.png b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.png new file mode 100644 index 00000000..97918431 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.sfc b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.sfc new file mode 100644 index 00000000..fa3b3723 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/make.bat b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/make.bat new file mode 100644 index 00000000..fd4785e4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mode7/StarWars/make.bat @@ -0,0 +1 @@ +bass StarWars.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.map new file mode 100644 index 00000000..e6d55e4f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pal new file mode 100644 index 00000000..afa4353c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pal @@ -0,0 +1,4 @@ +"C "c cdeeecb b    '  $& $ !)()F%'! + (((()I *,kiF-K)ik 1LK1!&1J1,- M4-%m5E5M'50m 15-!5.-).G=%/===5 --)P1A!kEfEP>MB-I0"Q:'IPJR&2)3.ES"Ip2MMr/Nqsr&NNp>t!N>M4&Q"t*VUN"5:,VvJV"VUoZ ^]O^^76R +aaxF8"8&bx2%8g ff:Tcinjj6kZ5orysXonr rROvucVwv5w]/:5w}_wsy&{~G +z3{}~}~~WL~~3wx*~m~VU \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pic new file mode 100644 index 00000000..fc2f7d01 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.png new file mode 100644 index 00000000..2bc4f1de Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..4915bd72 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU MOSAIC MODE3 DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.asm b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.asm new file mode 100644 index 00000000..ba249747 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.asm @@ -0,0 +1,90 @@ +// SNES Mosaic Mode3 Demo by krom (Peter Lemon): +// L Button = Decrement Mosaic Size +// R Button = Increment Mosaic Size +arch snes.cpu +output "MosaicMode3.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $1FFFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGTiles, $0000, $8000, 0) // Load Background Tiles To VRAM + LoadVRAM(BGTiles + $10000, $8000, $6040, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F800, BGMap.size, 0) // Load Background Tile Map To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%11111100 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 32x32, BG1 Map Address = $3F (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000001 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + FadeIN() // Screen Fade In + +lda.b #%00000001 +sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable +xba + +InputLoop: + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + + LButton: + ReadJOY({JOY_L}) // Test L Button + beq RButton // IF (L ! Pressed) Branch Down + xba // Decrement BG1 Mosaic Size + sec + sbc.b #$10 + sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable + xba + + RButton: + ReadJOY({JOY_R}) // Test R Button + beq Finish // IF (R ! Pressed) Branch Down + xba // Increment BG1 Mosaic Size + clc + adc.b #$10 + sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable + xba + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (2048 Bytes) +// BANK 1 & 2 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (57408 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.png b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.png new file mode 100644 index 00000000..e55a5a73 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.sfc b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.sfc new file mode 100644 index 00000000..e4c9bff8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/make.bat b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/make.bat new file mode 100644 index 00000000..b19af9ee --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode3/make.bat @@ -0,0 +1 @@ +bass MosaicMode3.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.map new file mode 100644 index 00000000..9c000f52 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pal new file mode 100644 index 00000000..8b995080 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pic new file mode 100644 index 00000000..45cfe6c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.png new file mode 100644 index 00000000..5ace7a4b Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..78103ba9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU MOSAIC MODE5 DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.asm b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.asm new file mode 100644 index 00000000..49df4f52 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.asm @@ -0,0 +1,93 @@ +// SNES Mosaic Mode5 Demo by krom (Peter Lemon): +// L Button = Decrement Mosaic Size +// R Button = Increment Mosaic Size +arch snes.cpu +output "MosaicMode5.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 16 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $F200, BGMap.size, 0) // Load Background Tile Map To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001101 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 5, Priority 1, BG1 16x8 Tiles + + lda.b #%00000001 // Interlace Mode On + sta.w REG_SETINI // $2133: Screen Mode Select + + // Setup BG1 16 Color Background + lda.b #%01111010 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x32, BG1 Map Address = $F200 (VRAM Address / $400) + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + sta.w REG_TS // $212D: BG1 To Sub Screen Designation (Needed To Show Interlace GFX) + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + + lda.b #62 // Scroll BG 62 Pixels Up + sta.w REG_BG1VOFS // Store A To BG Scroll Vertical Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG Scroll Vertical Position Hi Byte + + FadeIN() // Screen Fade In + +lda.b #%00000001 +sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable +xba + +InputLoop: + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + WaitNMI() // Wait For Vertical Blank + + LButton: + ReadJOY({JOY_L}) // Test L Button + beq RButton // IF (L ! Pressed) Branch Down + xba // Decrement BG1 Mosaic Size + sec + sbc.b #$10 + sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable + xba + + RButton: + ReadJOY({JOY_R}) // Test R Button + beq Finish // IF (R ! Pressed) Branch Down + xba // Increment BG1 Mosaic Size + clc + adc.b #$10 + sta.w REG_MOSAIC // $2106: Mosaic Size & Mosaic Enable + xba + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (32 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (3584 Bytes) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (16576 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.png b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.png new file mode 100644 index 00000000..232ff7a3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.sfc b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.sfc new file mode 100644 index 00000000..afbea638 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/make.bat b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/make.bat new file mode 100644 index 00000000..01687ff0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Mosaic/Mode5/make.bat @@ -0,0 +1 @@ +bass MosaicMode5.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.map new file mode 100644 index 00000000..4d86c3fb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.pic new file mode 100644 index 00000000..763c03cb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGGreen.pal b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGGreen.pal new file mode 100644 index 00000000..0ead78a6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGGreen.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGRed.pal b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGRed.pal new file mode 100644 index 00000000..36b03813 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/GFX/BGRed.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..7092d0ca --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PPU RINGS " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/Rings.asm b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.asm new file mode 100644 index 00000000..79419e89 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.asm @@ -0,0 +1,133 @@ +// SNES PPU Rings Demo by krom (Peter Lemon): +arch snes.cpu +output "Rings.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +BG1X: + dw 0 // BG1 Position X Word +BG1Y: + dw 0 // BG1 Position Y Word +BG2X: + dw 0 // BG2 Position X Word +BG2Y: + dw 0 // BG2 Position Y Word + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGRedPal, $00, BGRedPal.size, 0) // Load Background Palette (BG1 Palette Uses 4 Colors) + LoadPAL(BGGreenPal, $20, BGGreenPal.size, 0) // Load Background Palette (BG2 Palette Uses 4 Colors) + LoadVRAM(BGTiles, $0000, BGTiles.size, 0) // Load Background Tiles To VRAM + LoadVRAM(BGMap, $E000, BGMap.size, 0) // Load Background Tile Map To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00000000 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 0, Priority 0, BG1 & BG2 8x8 Tiles + + // Setup BG1 4 Colour Background + lda.b #%11110011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x64, BG1 Map Address = $E000 (VRAM Address / $400) + + // Setup BG2 4 Colour Background + lda.b #%11110011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG2SC // $2108: BG2 64x64, BG2 Map Address = $E000 (VRAM Address / $400) + + lda.b #%00000000 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $0, BG1 Tile Address = $0 (VRAM Address / $1000) + + lda.b #%00000011 // Enable BG1 & BG2 + sta.w REG_TM // $212C: BG1 & BG2 To Main Screen Designation + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos Low Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Pos High Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Pos Low Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Pos High Byte + + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos Low Byte + stz.w REG_BG2HOFS // Store Zero To BG2 Horizontal Scroll Pos High Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Scroll Pos Low Byte + stz.w REG_BG2VOFS // Store Zero To BG2 Vertical Pos High Byte + + // Initialize Variables + ldx.w #192 + stx.b BG1X // Store BG1 Position X Word + WriteD16(BG1X, REG_BG1HOFS) // Write Memory To Double 8-bit (16-Bit) + ldx.w #192 + stx.b BG1Y // Store BG1 Position Y Word + WriteD16(BG1Y, REG_BG1VOFS) // Write Memory To Double 8-bit (16-Bit) + ldx.w #64 + stx.b BG2X // Store BG2 Position X Word + WriteD16(BG2X, REG_BG2HOFS) // Write Memory To Double 8-bit (16-Bit) + ldx.w #96 + stx.b BG2Y // Store BG2 Position Y Word + WriteD16(BG2Y, REG_BG2VOFS) // Write Memory To Double 8-bit (16-Bit) + + FadeIN() // Screen Fade In + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + ReadJOY({JOY_UP}) // Test UP Button + beq Down // "UP" Not Pressed? Branch Down + BGScroll16(BG1Y, REG_BG1VOFS, in) // Increment BG1 Y Pos + + Down: + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // "DOWN" Not Pressed? Branch Down + BGScroll16(BG1Y, REG_BG1VOFS, de) // Decrement BG1 Y Pos + + Left: + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // "LEFT" Not Pressed? Branch Down + BGScroll16(BG1X, REG_BG1HOFS, in) // Increment BG1 X Pos + + Right: + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq XButton // "RIGHT" Not Pressed? Branch Down + BGScroll16(BG1X, REG_BG1HOFS, de) // Decrement BG1 X Pos + + XButton: + ReadJOY({JOY_X}) // Test X Button + beq BButton // "X" Not Pressed? Branch Down + BGScroll16(BG2Y, REG_BG2VOFS, in) // Increment BG2 Y Pos + + BButton: + ReadJOY({JOY_B}) // Test B Button + beq YButton // "B" Not Pressed? Branch Down + BGScroll16(BG2Y, REG_BG2VOFS, de) // Decrement BG2 Y Pos + + YButton: + ReadJOY({JOY_Y}) // Test Y Button + beq AButton // "Y" Not Pressed? Branch Down + BGScroll16(BG2X, REG_BG2HOFS, in) // Increment BG2 X Pos + + AButton: + ReadJOY({JOY_A}) // Test A Button + beq Finish // "A" Not Pressed? Branch Down + BGScroll16(BG2X, REG_BG2HOFS, de) // Decrement BG2 X Pos + + Finish: + jmp InputLoop + +// Character Data +// BANK 0 +insert BGRedPal, "GFX\BGRed.pal" // Include BG Palette Data (8 Bytes) +insert BGGreenPal, "GFX\BGGreen.pal" // Include BG Palette Data (8 Bytes) +insert BGMap, "GFX\BG.map" // Include BG Map Data (8192 Bytes) +insert BGTiles, "GFX\BG.pic" // Include BG Tile Data (14640 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/Rings.png b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.png new file mode 100644 index 00000000..d02d31eb Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/Rings.sfc b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.sfc new file mode 100644 index 00000000..931eae84 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Rings/Rings.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Rings/make.bat b/roms/snes/peter-lemon-snes/PPU/Rings/make.bat new file mode 100644 index 00000000..bd876884 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Rings/make.bat @@ -0,0 +1 @@ +bass Rings.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.map new file mode 100644 index 00000000..1c7c27c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pic new file mode 100644 index 00000000..2e15fe45 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.png new file mode 100644 index 00000000..ede5399c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..9aeee7f6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "WINDOW HDMA DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.asm b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.asm new file mode 100644 index 00000000..68e6f504 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.asm @@ -0,0 +1,130 @@ +// SNES Window HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "WindowHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $4000, BGTiles.size, 0) // Load Background Tiles To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x64, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000010 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $4000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Green Background / Window + lda.b #%11100000 // Load Green Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%00000011 // Load Green Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Window + lda.b #3 // Load Window BG1 Inside + sta.w REG_W12SEL // $2123: Window BG1/BG2 Mask Settings Write Byte + lda.b #1 // Load Window BG1 Disable + sta.w REG_TMW // $212E: Window Area Main Screen Disable Write Byte + + // HDMA Window + lda.b #%00000001 // HMDA: Write 2 Bytes Each Scanline + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_WH0 // $26: Start At Window 1 Left Position (X1)($2126) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +ldx.w #$0000 // Reset BG X Position +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + cpy.w #$0000 // Check If At Top Of Screen + beq Down // Skip BG Scrolling If Top + ReadJOY({JOY_UP}) // Test UP Button + beq Down // IF (UP ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Vertical Position + + Down: + cpy.w #$00FF // Check If At Bottom Of Screen + beq Left // Skip BG Scrolling If Bottom + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // IF (DOWN ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Vertical Position + + Left: + cpx.w #$0000 // Check If At Left Of Screen + beq Right // Skip BG Scrolling If Left + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // IF (LEFT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, de) // Decrement BG1 Horizontal Position + + Right: + cpx.w #$00FF // Check If At Right Of Screen + beq Finish // Skip BG Scrolling If Right + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, in) // Increment BG1 Horizontal Position + + Finish: + jmp InputLoop + +HDMATable: + db 16, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 15, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 14, 241 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 13, 242 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 12, 243 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 11, 244 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 10, 245 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 10, 245 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 11, 244 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 12, 243 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 13, 242 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 14, 241 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 15, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 16, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2 + db 0 // End Of HDMA + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (8192 Bytes) +// BANK 1 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.png b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.png new file mode 100644 index 00000000..303ec580 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.sfc new file mode 100644 index 00000000..6ffc08d6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/make.bat new file mode 100644 index 00000000..e3e0a4aa --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowHDMA/make.bat @@ -0,0 +1 @@ +bass WindowHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.map b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.map new file mode 100644 index 00000000..1c7c27c2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.map differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pal b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pal new file mode 100644 index 00000000..eb39f5a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pal differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pic b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pic new file mode 100644 index 00000000..2e15fe45 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.pic differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.png b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.png new file mode 100644 index 00000000..ede5399c Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/GFX/BG.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..16589957 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "WINDOWMULTI HDMA DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.asm b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.asm new file mode 100644 index 00000000..78b5a10d --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.asm @@ -0,0 +1,132 @@ +// SNES Window Multi HDMA Demo by krom (Peter Lemon): +arch snes.cpu +output "WindowMultiHDMA.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, BGPal.size, 0) // Load Background Palette (BG Palette Uses 256 Colors) + LoadVRAM(BGMap, $0000, BGMap.size, 0) // Load Background Tile Map To VRAM + LoadVRAM(BGTiles, $4000, BGTiles.size, 0) // Load Background Tiles To VRAM + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + // Setup Video + lda.b #%00001011 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 3, Priority 1, BG1 8x8 Tiles + + // Setup BG1 256 Color Background + lda.b #%00000011 // AAAAAASS: S = BG Map Size, A = BG Map Address + sta.w REG_BG1SC // $2107: BG1 64x64, BG1 Map Address = $0000 (VRAM Address / $400) + lda.b #%00000010 // BBBBAAAA: A = BG1 Tile Address, B = BG2 Tile Address + sta.w REG_BG12NBA // $210B: BG1 Tile Address = $4000 (VRAM Address / $1000) + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: BG1 To Main Screen Designation + + // Green Background / Window + lda.b #%11100000 // Load Green Colour Lo Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Lo Byte + lda.b #%00000011 // Load Green Colour Hi Byte + sta.w REG_CGDATA // $2122: CGRAM Data Write Hi Byte + + // Window + lda.b #%00001111 // Load Window 1 & 2 BG1 Inside + sta.w REG_W12SEL // $2123: Window BG1/BG2 Mask Settings Write Byte + lda.b #1 // Load Window BG1 Disable + sta.w REG_TMW // $212E: Window Area Main Screen Disable Write Byte + lda.b #1 // Load Window 1 & 2 BG Mask Logic Settings (BG1 = AND) + sta.w REG_WBGLOG // $212E: Window Area Main Screen Disable Write Byte + + // HDMA Window + lda.b #%00000100 // HMDA: Write 4 Bytes Each Scanline + sta.w REG_DMAP0 // $4300: DMA0 DMA/HDMA Parameters + lda.b #REG_WH0 // $26: Start At Window 1 Left Position (X1)($2126) + sta.w REG_BBAD0 // $4301: DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) + ldx.w #HDMATable // HMDA Table Address + stx.w REG_A1T0L // $4302: DMA0 DMA/HDMA Table Start Address + lda.b #0 // HDMA Table Bank + sta.w REG_A1B0 // $4304: DMA0 DMA/HDMA Table Start Address (Bank) + lda.b #%00000001 // HDMA Channel Select (Channel 0) + sta.w REG_HDMAEN // $420C: Select H-Blank DMA (H-DMA) Channels + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + FadeIN() // Screen Fade In + +ldx.w #$0000 // Reset BG X Position +ldy.w #$0000 // Reset BG Y Position + +InputLoop: + WaitNMI() // Wait For Vertical Blank + + Up: + cpy.w #$0000 // Check If At Top Of Screen + beq Down // Skip BG Scrolling If Top + ReadJOY({JOY_UP}) // Test UP Button + beq Down // IF (UP ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, de) // Decrement BG1 Vertical Position + + Down: + cpy.w #$00FF // Check If At Bottom Of Screen + beq Left // Skip BG Scrolling If Bottom + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // IF (DOWN ! Pressed) Branch Down + BGScroll8I(y, REG_BG1VOFS, in) // Increment BG1 Vertical Position + + Left: + cpx.w #$0000 // Check If At Left Of Screen + beq Right // Skip BG Scrolling If Left + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // IF (LEFT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, de) // Decrement BG1 Horizontal Position + + Right: + cpx.w #$00FF // Check If At Right Of Screen + beq Finish // Skip BG Scrolling If Right + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq Finish // IF (RIGHT ! Pressed) Branch Down + BGScroll8I(x, REG_BG1HOFS, in) // Increment BG1 Horizontal Position + + Finish: + jmp InputLoop + +HDMATable: + db 16, 1, 0, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 1, 0, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 1, 0, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 16, 112, 144, 240 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 16, 1, 0, 1, 0 // Repeat 16 Scanlines, Window 1 X1, Window 1 X2, Window 2 X1, Window 2 X2 + db 0 // End Of HDMA + +// Character Data +// BANK 0 +insert BGPal, "GFX/BG.pal" // Include BG Palette Data (512 Bytes) +insert BGMap, "GFX/BG.map" // Include BG Map Data (8192 Bytes) +// BANK 1 +seek($18000) +insert BGTiles, "GFX/BG.pic" // Include BG Tile Data (32384 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.png b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.png new file mode 100644 index 00000000..8ff3195f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.png differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.sfc b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.sfc new file mode 100644 index 00000000..57fc187f Binary files /dev/null and b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.sfc differ diff --git a/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/make.bat b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/make.bat new file mode 100644 index 00000000..ff99dabf --- /dev/null +++ b/roms/snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/make.bat @@ -0,0 +1 @@ +bass WindowMultiHDMA.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..72ffce7f --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PLOT LINE MODE7 DEMO " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $30 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.asm b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.asm new file mode 100644 index 00000000..1b1401a9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.asm @@ -0,0 +1,378 @@ +// SNES Plot Line Mode7 Demo by krom (Peter Lemon): +arch snes.cpu +output "PlotLineMode7.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros +include "LIB/SNES_INPUT.INC" // Include Input Macros + +// Variable Data +seek(WRAM) // 8Kb WRAM Mirror ($0000..$1FFF) +X1: + dw 0 // Line Point 1 X Word (X1) +Y1: + dw 0 // Line Point 1 Y Byte (Y1) +X2: + dw 0 // Line Point 2 X Word (X2) +Y2: + dw 0 // Line Point 2 Y Byte (Y2) + +DX: + dw 0 // Line Delta X Byte (DX) +DY: + dw 0 // Line Delta Y Byte (DY) + +SX: + dw 0 // Line Signed Change X Word (SX) +SY: + dw 0 // Line Signed Change Y Word (SY) + +P1: + dw 0 // Point Start Word (P1) +P2: + dw 0 // Point End Word (P2) + +Count: + dw 0 // Line Count X/Y Byte (Count) + +Error: + dw 0 // Line Error X/Y Byte (Error) + +seek($8000); Start: + SNES_INIT(FASTROM) // Run SNES Initialisation Routine + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + + LoadPAL(BGPal, $00, 4, 0) // Load Background Palette (BG Palette Uses 256 Colors) + ClearLOVRAM(BGTiles, $0000, 16384, 0) // Clear Background Map In VRAM To Static Byte + LoadHIVRAM(BGTiles, $0000, 16384, 0) // Load Background Tiles To VRAM + + // Setup Mode7 128x128 Linear Screen + lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: Set BG1 To Main Screen Designation + + stz.w REG_M7SEL // $211A: MODE7 Settings + + lda.b #$04 // Set Mode7 X Scale + stz.w REG_M7A // $211B: MODE7 COSINE A Lo Byte + sta.w REG_M7A // $211B: MODE7 COSINE A Hi Byte + + stz.w REG_M7B // $211C: MODE7 SINE A Lo Byte + stz.w REG_M7B // $211C: MODE7 SINE A Hi Byte + + stz.w REG_M7C // $211D: MODE7 SINE B Lo Byte + stz.w REG_M7C // $211D: MODE7 SINE B Hi Byte + + lda.b #$90 // Set Mode7 Y Scale + sta.w REG_M7D // $211E: MODE7 COSINE B Lo Byte + lda.b #$04 + sta.w REG_M7D // $211E: MODE7 COSINE B Hi Byte + + stz.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + stz.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + stz.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + stz.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + + // Setup Clear Screen DMA + lda.b #$01 // Set WRAM Destination + sta.w REG_WMADDH // $2183: WRAM Address (Upper 1-Bit) + lda.b #$0A // Set DMA Mode (Write 2 Bytes, Fixed Source) + sta.w REG_DMAP0 // $4300: DMA Control + lda.b #REG_WMDATA // $80: Set Destination Register ($2180: WRAM Write) + sta.w REG_BBAD0 // $4301: DMA Destination + ldx.w #BGPal // Set Source Offset + stx.w REG_A1T0L // $4302: DMA Source + lda.b #BGPal>>16 // Set Source Bank + sta.w REG_A1B0 // $4304: Source Bank + + // Setup Copy Frame Buffer DMA + lda.b #$02 // Set DMA Mode (Write 2 Bytes, Increment Source) + sta.w REG_DMAP1 // $4310: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD1 // $4311: DMA Destination + lda.b #$7F // Set Source Bank + sta.w REG_A1B1 // $4314: Source Bank + + // Setup Variable Data + ldx.w #0 // X = Line Point 1 X (X1) + stx.b X1 // Store X1 + ldx.w #0 // X = Line Point 1 Y (Y1) + stx.b Y1 // Store Y1 + ldx.w #127 // X = Line Point 2 X (X2) + stx.b X2 // Store X2 + ldx.w #127 // X = Line Point 2 Y (Y2) + stx.b Y2 // Store Y2 + + lda.b #$F // Turn On Screen, Full Brightness + sta.w REG_INIDISP // $2100: Screen Display + +Refresh: + // Clear Screen + ldx.w #$0000 // Set WRAM Destination + stx.w REG_WMADDL // $2181: WRAM Address + ldx.w #$4000 // Set Size In Bytes To DMA Transfer + stx.w REG_DAS0L // $4305: DMA Transfer Size/HDMA + lda.b #%00000001 // Start DMA Transfer On Channel 0 + sta.w REG_MDMAEN // $420B: DMA Enable + + // Plot Line + rep #%00100000 // A Set To 16-Bit + lda.b X2 // A = Line Point 2 X (X2) + sec // Set Carry + sbc.b X1 // A = X2 - X1 (DX) + bmi DXNEG + ldx.w #1 // X = 1 (SX) + bra DXSX + DXNEG: + eor.w #$FFFF // A ^= $FFFF + inc // A = ABS(DX) + ldx.w #-1 // X = -1 (SX) + DXSX: + sta.b DX // Store DX + stx.b SX // Store SX + + lda.b Y2 // A = Line Point 2 Y (Y2) + sec // Set Carry + sbc.b Y1 // A = Y2 - Y1 (DY) + bmi DYNEG + ldx.w #128 // X = 128 (SY) + bra DYSY + DYNEG: + eor.w #$FFFF // A ^= $FFFF + inc // A = ABS(DY) + ldx.w #-128 // X = -128 (SY) + DYSY: + sta.b DY // Store DY + stx.b SY // Store SY + + lda.b Y1 // A = Line Point 1 Y + xba // A *= 256 + and.w #$FF00 // Clear A + lsr // A /= 2 (Line Point 1 Y * 128) + adc.b X1 // A += Line Point 1 X + sta.b P1 // Store Point Start (P1) + + lda.b Y2 // A = Line Point 2 Y + xba // A *= 256 + and.w #$FF00 // Clear A + lsr // A /= 2 (Line Point 2 Y * 128) + adc.b X2 // A += Line Point 2 X + sta.b P2 // Store Point End (P2) + + lda.b DX // A = Delta X (DX) + cmp.b DY // Compare DX To DY + bmi YError // IF (DX > DY) X Error = DX / 2 + sta.b Count // Store X Count + lsr // A = DX / 2 + sta.b Error // Store X Error + bra LoopX // Loop X + YError: // ELSE Y Error = DY / 2 + lda.b DY // A = Delta Y (DY) + sta.b Count // Store Y Count + lsr // A = DY / 2 + sta.b Error // Store Y Error + bra LoopY // Loop Y + + LoopX: // X Line Drawing + ldx.b P1 // X = Point Start (P1) + sep #%00100000 // A Set To 8-Bit + lda.b #1 // A = Pixel Color White + sta.l $7F0000,x // WRAM Data Write + rep #%00100000 // A Set To 16-Bit + lda.b P1 // A = Point Start (P1) + clc // Clear Carry + adc.b SX // P1 += SX + sta.b P1 // Store P1 + dec.b Count // X Count--, Compare X Count To Zero + bmi LineEnd // IF (X Count < 0) Line End + + ldx.b P2 // X = Point End (P2) + sep #%00100000 // A Set To 8-Bit + lda.b #1 // A = Pixel Color White + sta.l $7F0000,x // WRAM Data Write + rep #%00100000 // A Set To 16-Bit + lda.b P2 // A = Point Start (P2) + sec // Set Carry + sbc.b SX // P2 -= SX + sta.b P2 // Store P2 + dec.b Count // X Count--, Compare X Count To Zero + bmi LineEnd // IF (X Count < 0) Line End + + lda.b Error // A = X Error + sec // Set Carry + sbc.b DY // X Error -= DY, Compare X Error To Zero + sta.b Error // Store X Error + bpl LoopX // Loop X + adc.b DX // IF (X Error < 0) X Error += DX + sta.b Error // Store X Error + lda.b P1 // A = Point Start (P1) + clc // Clear Carry + adc.b SY // IF (X Error < 0) Point Start += SY + sta.b P1 // Store Point Start (P1) + lda.b P2 // A = Point End (P2) + sec // Set Carry + sbc.b SY // IF (X Error < 0) Point End -= SY + sta.b P2 // Store Point End (P2) + bra LoopX // Loop X + + LoopY: // Y Line Drawing + ldx.b P1 // X = Point Start (P1) + sep #%00100000 // A Set To 8-Bit + lda.b #1 // A = Pixel Color White + sta.l $7F0000,x // WRAM Data Write + rep #%00100000 // A Set To 16-Bit + lda.b P1 // A = Point Start (P1) + clc // Clear Carry + adc.b SY // P1 += SY + sta.b P1 // Store P1 + dec.b Count // Y Count--, Compare Y Count To Zero + bmi LineEnd // IF (Y Count < 0) Line End + + ldx.b P2 // X = Point End (P2) + sep #%00100000 // A Set To 8-Bit + lda.b #1 // A = Pixel Color White + sta.l $7F0000,x // WRAM Data Write + rep #%00100000 // A Set To 16-Bit + lda.b P2 // A = Point Start (P2) + sec // Set Carry + sbc.b SY // P2 -= SY + sta.b P2 // Store P2 + dec.b Count // Y Count--, Compare Y Count To Zero + bmi LineEnd // IF (Y Count < 0) Line End + + lda.b Error // A = Y Error + sec // Set Carry + sbc.b DX // Y Error -= DX, Compare Y Error To Zero + sta.b Error // Store Y Error + bpl LoopY // Loop Y + adc.b DY // IF (Y Error < 0) Y Error += DY + sta.b Error // Store X Error + lda.b P1 // A = Point Start (P1) + clc // Clear Carry + adc.b SX // IF (Y Error < 0) Point Start += SX + sta.b P1 // Store Point Start (P1) + lda.b P2 // A = Point End (P2) + sec // Set Carry + sbc.b SX // IF (Y Error < 0) Point End -= SX + sta.b P2 // Store Point End (P2) + bra LoopY // Loop Y + + LineEnd: // End of Line Drawing + sep #%00100000 // A Set To 8-Bit + + Up: + lda.b Y1 // A = Y1 + cmp.b #0 // IF (Y1 == 0) Skip + beq Down + ReadJOY({JOY_UP}) // Test UP Button + beq Down // "UP" Not Pressed? Branch Down + dec.b Y1 // Y1-- + Down: + lda.b Y1 // A = Y1 + cmp.b #127 // IF (Y1 == 127) Skip + beq Left + ReadJOY({JOY_DOWN}) // Test DOWN Button + beq Left // "DOWN" Not Pressed? Branch Down + inc.b Y1 // Y1++ + Left: + lda.b X1 // A = X1 + cmp.b #0 // IF (X1 == 0) Skip + beq Right + ReadJOY({JOY_LEFT}) // Test LEFT Button + beq Right // "LEFT" Not Pressed? Branch Down + dec.b X1 // X1-- + Right: + lda.b X1 // A = X1 + cmp.b #127 // IF (X1 == 127) Skip + beq X + ReadJOY({JOY_RIGHT}) // Test RIGHT Button + beq X // "RIGHT" Not Pressed? Branch Down + inc.b X1 // X1++ + X: + lda.b Y2 // B = Y2 + cmp.b #0 // IF (Y2 == 0) Skip + beq B + ReadJOY({JOY_X}) // Test X Button + beq B // "X" Not Pressed? Branch Down + dec.b Y2 // Y2-- + B: + lda.b Y2 // B = Y2 + cmp.b #127 // IF (Y2 == 127) Skip + beq Y + ReadJOY({JOY_B}) // Test B Button + beq Y // "B" Not Pressed? Branch Down + inc.b Y2 // Y2++ + Y: + lda.b X2 // B = X2 + cmp.b #0 // IF (X2 == 0) Skip + beq A + ReadJOY({JOY_Y}) // Test Y Button + beq A // "Y" Not Pressed? Branch Down + dec.b X2 // X2-- + A: + lda.b X2 // B = X2 + cmp.b #127 // IF (X2 == 127) Skip + beq Finish + ReadJOY({JOY_A}) // Test A Button + beq Finish // "A" Not Pressed? Branch Down + inc.b X2 // X2++ + Finish: + + ldx.w #$0000 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + ldx.w #$0000 // Set Source Offset + stx.w REG_A1T1L // $4312: DMA Source + WaitNMI() // Wait For NMI Flag + ldx.w #$1700 // Set Size In Bytes To DMA Transfer + stx.w REG_DAS1L // $4315: DMA Transfer Size/HDMA + lda.b #%000000010 // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + WaitNMI() // Wait For NMI Flag + ldx.w #$1700 // Set Size In Bytes To DMA Transfer + stx.w REG_DAS1L // $4315: DMA Transfer Size/HDMA + lda.b #%000000010 // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + WaitNMI() // Wait For NMI Flag + ldx.w #$1200 // Set Size In Bytes To DMA Transfer + stx.w REG_DAS1L // $4315: DMA Transfer Size/HDMA + lda.b #%000000010 // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + jmp Refresh + +BGPal: + dw $0000, $7FFF // Black, White (4 Bytes) + +BGTiles: // Include BG Tile Data (16384 Bytes) + define i(0) + while {i} < 256 { // Create 256 Tiles Which Map To 256 Palette Colors + db {i},{i},{i},{i},{i},{i},{i},{i} // Clear Tile/Pixel Color = ($00) + db {i},{i},{i},{i},{i},{i},{i},{i} // Rest Of Colors ($01..$FF) + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + evaluate i({i} + 1) + } \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.png b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.png new file mode 100644 index 00000000..f53a12c1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.png differ diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.sfc b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.sfc new file mode 100644 index 00000000..9294adf2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.sfc differ diff --git a/roms/snes/peter-lemon-snes/PlotLine/Mode7/make.bat b/roms/snes/peter-lemon-snes/PlotLine/Mode7/make.bat new file mode 100644 index 00000000..67393612 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotLine/Mode7/make.bat @@ -0,0 +1 @@ +bass PlotLineMode7.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES.INC b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_GFX.INC b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_GFX.INC new file mode 100644 index 00000000..92b58895 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_GFX.INC @@ -0,0 +1,558 @@ +//=============== +// SNES Graphics +//=============== + +//============================= +// WaitNMI - Wait For NMI Flag +//============================= +macro WaitNMI() { + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag +} + +//====================================== +// WaitHV - Wait For H/V Timer IRQ Flag +//====================================== +macro WaitHV() { + - + bit.w REG_TIMEUP // $4210: Read H/V-Timer IRQ Flag + bpl - // Wait For H/V Timer IRQ Flag +} + +//======================================== +// WaitHVB - Wait For V-Blank Period Flag +//======================================== +macro WaitHVB() { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag +} + +//================================================================ +// FadeIN - Increment Screen Brightness From 0..15 (VSYNC Timing) +//================================================================ +macro FadeIN() { + ldx.w #$0000 // Set X To Mininmum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + inx // Increments Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$0F // Compare With Maximum Brightness Level (15) + bne - // IF (Screen != Maximum Brightness Level) Loop +} + +//================================================================= +// FadeOUT - Decrement Screen Brightness From 15..0 (VSYNC Timing) +//================================================================= +macro FadeOUT() { + ldx.w #$000F // Set X To Maximum Brightness Level + - + bit.w REG_RDNMI // $4210: Read NMI Flag Register + bpl - // Wait For NMI Flag + + dex // Decrement Brightness Level + txa // Swap 16-Bit X To 8-Bit A + sta.w REG_INIDISP // $2100: Turn Screen To Brightness Level + cmp.b #$00 // Compare With Minimum Brightness Level + bne - // IF (Screen != Minimum Brightness Level) Loop +} + +//====================================== +// LoadPAL - Load Palette Data To CGRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadPAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//========================================== +// UpdatePAL - Update Palette Data To CGRAM +//========================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 9-Bit CGRAM Destination Address (Color # To Start On) +// SIZE: Size Of Data (# Of Colors To Copy) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdatePAL(SRC, DEST, SIZE, CHAN) { + lda.b #{DEST} // Set CGRAM Destination + sta.w REG_CGADD // $2121: CGRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$22 // Set Destination Register ($2122: CGRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer (2 Bytes For Each Color) + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearLOVRAM - Clear VRAM Lo Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearLOVRAM(SRC, DEST, SIZE, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================== +// ClearHIVRAM - Clear VRAM Hi Fixed Byte +//======================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearHIVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=================================== +// ClearVRAM - Clear VRAM Fixed Word +//=================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro ClearVRAM(SRC, DEST, SIZE, CHAN) { + // Transfer Lo Byte + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$08 // Set DMA Mode (Write Byte, Fixed Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset (Lo Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Transfer Hi Byte + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #({SRC} + 1) // Set Source Offset (Hi Byte) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//================================== +// LoadVRAM - Load GFX Data To VRAM +//================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//======================================================== +// LoadVRAMStride - Load GFX Data To VRAM With DMA Stride +//======================================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// STRIDE: Dest Offset Stride +// COUNT: Number Of DMA Transfers +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadVRAMStride(SRC, DEST, SIZE, STRIDE, COUNT, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + + ldx.w #{DEST} >> 1 // Set VRAM Destination + - + stx.w REG_VMADDL // $2116: VRAM + + rep #$20 // Set 16-Bit Accumulator + txa // A = X + clc // Clear Carry Flag + adc.w #{STRIDE} >> 1 + tax // X = A + lda.w #{SIZE} // Set Size In Bytes To DMA Transfer + sta.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + sep #$20 // Set 8-Bit Accumulator + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + cpx.w #({DEST} + ({STRIDE} * {COUNT})) >> 1 + bne - +} + +//====================================== +// UpdateVRAM - Update GFX Data To VRAM +//====================================== +// SRC: 24-Bit Address Of Source Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZE: Size Of Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro UpdateVRAM(SRC, DEST, SIZE, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$01 // Set DMA Mode (Write Word, Increment Source) + sta.w REG_DMAP{CHAN} // $43X0: DMA Control + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRC} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRC} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZE} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bpl - // Wait For V-Blank Period Flag + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=========================================== +// LoadM7VRAM - Load Mode 7 GFX Data To VRAM +//=========================================== +// SRCMAP: 24-Bit Address Of Source Map Data +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZEMAP: Size Of Map Data (BYTE Size) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadM7VRAM(SRCMAP, SRCTILES, DEST, SIZEMAP, SIZETILES, CHAN) { + // Load Mode7 Map Data To VRAM + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCMAP} // Set Source Offset (Map) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCMAP} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZEMAP} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable + + // Load Mode7 Tile Data To VRAM (Needs To Be On Same Bank As Map) + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset (Tiles) + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadLOVRAM - Load GFX Data To VRAM Lo Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadLOVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$18 // Set Destination Register ($2118: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//============================================= +// LoadHIVRAM - Load GFX Data To VRAM Hi Bytes +//============================================= +// SRCTILES: 24-Bit Address Of Source Tile Data +// DEST: 16-Bit VRAM Destination (WORD Address) +// SIZETILES: Size Of Tile Data (BYTE Size) +// CHAN: DMA Channel To Transfer Data (0..7) +macro LoadHIVRAM(SRCTILES, DEST, SIZETILES, CHAN) { + lda.b #$80 // Set Increment VRAM Address After Accessing Hi Byte + sta.w REG_VMAIN // $2115: Video Port Control + ldx.w #{DEST} >> 1 // Set VRAM Destination + stx.w REG_VMADDL // $2116: VRAM + + stz.w REG_DMAP{CHAN} // Set DMA Mode (Write Byte, Increment Source) ($43X0: DMA Control) + lda.b #$19 // Set Destination Register ($2119: VRAM Write) + sta.w REG_BBAD{CHAN} // $43X1: DMA Destination + ldx.w #{SRCTILES} // Set Source Offset + stx.w REG_A1T{CHAN}L // $43X2: DMA Source + lda.b #{SRCTILES} >> 16 // Set Source Bank + sta.w REG_A1B{CHAN} // $43X4: Source Bank + ldx.w #{SIZETILES} // Set Size In Bytes To DMA Transfer + stx.w REG_DAS{CHAN}L // $43X5: DMA Transfer Size/HDMA + + lda.b #$01 << {CHAN} // Start DMA Transfer On Channel + sta.w REG_MDMAEN // $420B: DMA Enable +} + +//=============================================== +// BGScroll8 - Scroll GFX BG From Memory (8-Bit) +//=============================================== +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8(BGSCR, BGPOS, DIR) { + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Low Byte + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16 - Scroll GFX BG From Memory (16-Bit) +//================================================= +// BGSCR: Source BG Scroll Position +// BGPOS: Destination BG Pos Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16(BGSCR, BGPOS, DIR) { + rep #$38 // Set 16-Bit Accumulator & Index + {DIR}c {BGSCR} // Decrement Or Increment BG Scroll Position Word + sep #$20 // Set 8-Bit Accumulator + lda {BGSCR} // Load BG Scroll Position Low Byte + sta {BGPOS} // Store BG Scroll Position Low Byte + lda {BGSCR} + 1 // Load BG Scroll Position High Byte + sta {BGPOS} // Store BG Scroll Position High Byte +} + +//=============================================== +// BGScroll8I - Scroll GFX BG From Index (8-Bit) +//=============================================== +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll8I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Low Byte + t{REG}a // Swaps 8-Bit Index To 8-Bit A + sta {BGPOS} // Store A To BG Scroll Position Low Byte + stz {BGPOS} // Store Zero To BG Scroll Position High Byte +} + +//================================================= +// BGScroll16I - Scroll GFX BG From Index (16-Bit) +//================================================= +// REG: Source Index Register (x, y) +// BGPOS: Destination BG Position Register +// DIR: Direction To Scroll (de = Decrement, in = Increment) +macro BGScroll16I(REG, BGPOS, DIR) { + {DIR}{REG} // Decrement Or Increment BG Scroll Position Word + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Swaps 16-Bit Index To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {BGPOS} // Store A To BG Scroll Position Low Byte + xba // Exchange B & A Accumulators + sta {BGPOS} // Store A To BG Scroll Position High Byte +} + +//====================================== +// Mode7CALC - Mode7 Matrix Calculation +//====================================== +// A: Mode7 COS A Word +// B: Mode7 SIN A Word +// C: Mode7 SIN B Word +// D: Mode7 COS B Word +// ANGLE: Mode7 Angle Byte +// SX: Mode7 Scale X Word +// SY: Mode7 Scale Y Word +// SINCOS: Mode7 SINCOS Table +macro Mode7CALC(A, B, C, D, ANGLE, SX, SY, SINCOS) { + lda.b {ANGLE} // Load Angle To A + tax // Transfer A To X + + // Calculate B & C (SIN) + // B + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {B} + // C + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 // High Byte + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // SIN(X) + eor.b #$FF // Make Negative + inc + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {C} + + // Change X Index To Point To COS Values (X + 64) + txa // Transfer X Index To A + clc // Clear Carry Flag + adc.b #64 // Add 64 With Carry + tax // Transfer A To X Index + + // Calculate A & D (COS) + // A + lda.b {SX} // Scale X + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SX} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {A} + // D + lda.b {SY} // Scale Y + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {SY} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.w {SINCOS},x // COS(X) + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + ldy.w REG_MPYM // $2135: Multiplication Result -> 8.8 + sty.w {D} + + // Store Result To Matrix + lda.b {A} + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + lda.b {A} + 1 + sta.w REG_M7A // $211B: MODE7 COSINE A (Multiplicand A) + + lda.b {B} + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + lda.b {B} + 1 + sta.w REG_M7B // $211C: MODE7 SINE A (Multiplicand B) + + lda.b {C} + sta.w REG_M7C // $211D: MODE7 SINE B + lda.b {C} + 1 + sta.w REG_M7C // $211D: MODE7 SINE B + + lda.b {D} + sta.w REG_M7D // $211E: MODE7 COSINE B + lda.b {D} + 1 + sta.w REG_M7D // $211E: MODE7 COSINE B +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e1fbe38e --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PLOT PIXEL MODE7 DEMO" +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $30 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.asm b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.asm new file mode 100644 index 00000000..71317e9c --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.asm @@ -0,0 +1,91 @@ +// SNES Plot Pixel Mode7 Demo by krom (Peter Lemon): +arch snes.cpu +output "PlotPixelMode7.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_GFX.INC" // Include Graphics Macros + +seek($8000); Start: + SNES_INIT(FASTROM) // Run SNES Initialisation Routine + + LoadPAL(BGPal, $00, 4, 0) // Load Background Palette (BG Palette Uses 256 Colors) + ClearLOVRAM(BGTiles, $0000, 16384, 0) // Clear Background Map In VRAM To Static Byte + LoadHIVRAM(BGTiles, $0000, 16384, 0) // Load Background Tiles To VRAM + + // Setup Mode7 128x128 Linear Screen + lda.b #%00000111 // DCBAPMMM: M = Mode, P = Priority, ABCD = BG1,2,3,4 Tile Size + sta.w REG_BGMODE // $2105: BG Mode 7, Priority 0, BG1 8x8 Tiles + + lda.b #$01 // Enable BG1 + sta.w REG_TM // $212C: Set BG1 To Main Screen Designation + + stz.w REG_M7SEL // $211A: MODE7 Settings + + lda.b #$04 // Set Mode7 X Scale + stz.w REG_M7A // $211B: MODE7 COSINE A Lo Byte + sta.w REG_M7A // $211B: MODE7 COSINE A Hi Byte + + stz.w REG_M7B // $211C: MODE7 SINE A Lo Byte + stz.w REG_M7B // $211C: MODE7 SINE A Hi Byte + + stz.w REG_M7C // $211D: MODE7 SINE B Lo Byte + stz.w REG_M7C // $211D: MODE7 SINE B Hi Byte + + lda.b #$90 // Set Mode7 Y Scale + sta.w REG_M7D // $211E: MODE7 COSINE B Lo Byte + lda.b #$04 + sta.w REG_M7D // $211E: MODE7 COSINE B Hi Byte + + stz.w REG_M7X // $211F: Mode7 Center Position X Lo Byte + stz.w REG_M7X // $211F: Mode7 Center Position X Hi Byte + stz.w REG_M7Y // $2120: Mode7 Center Position Y Lo Byte + stz.w REG_M7Y // $2120: Mode7 Center Position Y Hi Byte + + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Lo Byte + stz.w REG_BG1HOFS // Store Zero To BG1 Horizontal Scroll Position Hi Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Lo Byte + stz.w REG_BG1VOFS // Store Zero To BG1 Vertical Scroll Position Hi Byte + + stz.w REG_VMAIN // Set Increment VRAM Address After Accessing Lo Byte ($2115: Video Port Control) + + // Plot Pixel + lda.b #48 // A = Plot Y Coord + xba // A *= 256 + and.b #$00 // Clear A + rep #%00100000 // A Set To 16-Bit + lsr // A /= 2 (A = Plot Y Coord * 128) + adc.w #40 // A += Plot X Coord (A = VRAM Address) + sta.w REG_VMADDL // $2116: VRAM Address Write (16-Bit) + sep #%00100000 // A Set To 8-Bit + lda.b #1 // A = Pixel Color White + sta.w REG_VMDATAL // $2118: VRAM Data Write (Lo 8-Bit) + + lda.b #$F // Turn On Screen, Full Brightness + sta.w REG_INIDISP // $2100: Screen Display + +Loop: + jmp Loop + +BGPal: + dw $0000, $7FFF // Black, White (4 Bytes) + +BGTiles: // Include BG Tile Data (16384 Bytes) + define i(0) + while {i} < 256 { // Create 256 Tiles Which Map To 256 Palette Colors + db {i},{i},{i},{i},{i},{i},{i},{i} // Clear Tile/Pixel Color = ($00) + db {i},{i},{i},{i},{i},{i},{i},{i} // Rest Of Colors ($01..$FF) + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + db {i},{i},{i},{i},{i},{i},{i},{i} + evaluate i({i} + 1) + } \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.png b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.png new file mode 100644 index 00000000..6c28dd5d Binary files /dev/null and b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.png differ diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.sfc b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.sfc new file mode 100644 index 00000000..b98977da Binary files /dev/null and b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.sfc differ diff --git a/roms/snes/peter-lemon-snes/PlotPixel/Mode7/make.bat b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/make.bat new file mode 100644 index 00000000..d10a4512 --- /dev/null +++ b/roms/snes/peter-lemon-snes/PlotPixel/Mode7/make.bat @@ -0,0 +1 @@ +bass PlotPixelMode7.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/README.md b/roms/snes/peter-lemon-snes/README.md new file mode 100644 index 00000000..db355275 --- /dev/null +++ b/roms/snes/peter-lemon-snes/README.md @@ -0,0 +1,25 @@ +SNES +==== +
    +SNES Assembly Code by krom (Peter Lemon).
    +
    +All code compiles out of box with the bass (v14) assembler by Near.
    +I use a special version of bass by ARM9 which has been updated with SuperFX/GSU Risc output:
    +https://github.com/ARM9/bass
    +I have included binaries of all the demos.
    +
    +Special thanks to Near, for making the higan emulator, & the bass assembler =D
    +Please check out higan, a cycle accurate SNES Emulator:
    +https://github.com/higan-emu/higan
    +
    +Also thanks to ARM9, for helping me with my SNES initialisation routine, my SuperFX/GSU LIB file, & his SuperFX/GSU bass assembler.
    +
    +Howto Compile:
    +All the code compiles into a single binary (ROMNAME.sfc) file.
    +Using bass Run: make.bat
    +
    +Howto Run:
    +I only test with a real SNES using a SD2SNES Cartridge by ikari:
    +http://sd2snes.de
    +
    +You can also use SNES emulators like higan & the MAME SNES Driver. diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F.spc b/roms/snes/peter-lemon-snes/SPC700/Axel-F.spc new file mode 100644 index 00000000..5567459d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.asm b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.asm new file mode 100644 index 00000000..a48acd0e --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.asm @@ -0,0 +1,29 @@ +// SNES SPC700 Axel-F Song Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "Axel-F.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, $8000) // Load SPC File To SMP/DSP + TransferBlockSPC($28000, SPCRAM+$8000, SPCROM.size-$8000) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 1 & 2 +seek($18000) +insert SPCROM, "Axel-F.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.sfc b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.sfc new file mode 100644 index 00000000..ec00e018 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.spc b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.spc new file mode 100644 index 00000000..0b69091f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F_spc.asm b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F_spc.asm new file mode 100644 index 00000000..25e4a8ec --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/Axel-F_spc.asm @@ -0,0 +1,309 @@ +// SNES SPC700 Axel-F Song Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "Axel-F.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(128) // Maximum Quantization ms +constant PatternSize(64) // Pattern Size (1..256) +constant ChannelCount(6) // (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($C000,$40) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$C0) // Echo Source Address + WDSP(DSP_EDL,8) // Echo Delay + WDSP(DSP_EON,%00001011) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,100) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,50) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,50) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: SawTooth + WDSP(DSP_V0ADSR1,$FA) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,50) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,50) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,0) // Voice 1: SawTooth + WDSP(DSP_V1ADSR1,$FA) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,127) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,127) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,1) // Voice 2: SynthBass + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$F0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,80) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,80) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,2) // Voice 3: Clap + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$F0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,127) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,127) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,3) // Voice 4: KickDrum + WDSP(DSP_V4ADSR1,$FF) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$F0) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,127) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,127) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,4) // Voice 5: Snare + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$F0) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + +StartSong: // Each Bar = 2048ms, Each Beat = 512ms, 3/4 Beat = 384ms, 1/2 Beat = 256ms, 1/4 Beat 128ms + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, SawToothPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, SawToothDetunePitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, SynthBassPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, ClapPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, KickDrumPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, SnarePitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..6 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List Change Address + lda #PATTERNLISTCHANGE // A = Pattern List Change (LSB) + ldy #PATTERNLISTCHANGE>>8 // Y = Pattern List Change (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternCmpEnd // IF (Pattern Offset != Pattern List Change Offset) Pattern Compare End, ELSE Set Pattern Change Offset + + WDSP(DSP_KOFF,%00000011) // DSP Register Data = Key Off Flags + + // Set Staccato Saw Tooth (Channel 1) + WDSP(DSP_V0VOLL,100) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,100) // Voice 0: Volume Right + WDSP(DSP_V0ADSR1,$FE) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$2F) // Voice 0: ADSR2 + + // Set Staccato Saw Tooth Detune (Channel 2) + WDSP(DSP_V1VOLL,100) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,100) // Voice 1: Volume Right + WDSP(DSP_V1ADSR1,$FE) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$2F) // Voice 1: ADSR2 + + PatternCmpEnd: // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + WDSP(DSP_KOFF,%00000011) // DSP Register Data = Key Off Flags + + // Set Saw Tooth (Channel 1) + WDSP(DSP_V0VOLL,50) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,50) // Voice 0: Volume Right + WDSP(DSP_V0ADSR1,$FA) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2 + + // Set Saw Tooth Detune (Channel 2) + WDSP(DSP_V1VOLL,50) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,50) // Voice 1: Volume Right + WDSP(DSP_V1ADSR1,$FA) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2 + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +SawToothPitchTable: + WritePitchTable($8868) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SawToothDetunePitchTable: + WritePitchTable($8748) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SynthBassPitchTable: + WritePitchTable($8868) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +ClapPitchTable: + dw $9468 // Write Sample Pitch Table +KickDrumPitchTable: + dw $8868 // Write Sample Pitch Table +SnarePitchTable: + dw $9668 // Write Sample Pitch Table + +PATTERN00: // Pattern 00: Rest (Channel 1..8) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 1 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 2 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 3 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 4 + +PATTERN01: // Pattern 01: Saw Tooth / Saw Tooth Detune (Channel 1 & 2) + db F5, SUST, SUST, SUST, G5s, SUST, SUST, F5, SUST, F5, A5s, SUST, F5, SUST, D5s, SUST // 1 + db F5, SUST, SUST, SUST, C6, SUST, SUST, F5, SUST, F5, C6s, SUST, C6, SUST, G5s, SUST // 2 + db F5, SUST, C6, SUST, F6, SUST, F5, D5s, SUST, D5s, C5, SUST, G5, SUST, F5, SUST // 3 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 4 + +PATTERN02: // Pattern 02: Bass (Channel 3) + db F3, SUST, SUST, SUST, F4, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 9 + db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, C3, C4, SUST, D4s, SUST, F4, SUST // 10 + db C3s, SUST, SUST, SUST, C4s, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 11 + db F3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, F4, C4, SUST, A3s, SUST, G3s, SUST // 12 +PATTERN03: // Pattern 03: Bass (Channel 3) + db F3, SUST, SUST, SUST, F4, SUST, SUST, D3s, SUST, D4s, C3, SUST, C4, SUST, D3s, SUST // 21 + db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, C3, C4, SUST, D4s, SUST, F4, SUST // 22 + db C3s, SUST, SUST, SUST, C4s, SUST, SUST, D3s, SUST, SUST, SUST, SUST, D4s, SUST, SUST, SUST // 23 + db F3, SUST, SUST, SUST, F4, SUST, SUST, SUST, SUST, F4, C4, SUST, A3s, SUST, G3s, SUST // 24 + +PATTERN04: // Pattern 04: Clap (Channel 4) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 9 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 10 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 11 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 12 +PATTERN05: // Pattern 05: Clap (Channel 4) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 13 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, SUST, HIT, SUST, HIT, SUST // 14 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 15 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 16 + +PATTERN06: // Pattern 06: Kick Drum (Channel 5) + db HIT, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, HIT, HIT, SUST, SUST, SUST, SUST, SUST // 13 + db HIT, SUST, SUST, SUST, HIT, SUST, SUST, SUST, SUST, HIT, HIT, SUST, SUST, SUST, SUST, SUST // 14 + db HIT, SUST, SUST, SUST, HIT, SUST, SUST, HIT, SUST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 15 + db HIT, SUST, SUST, SUST, HIT, SUST, SUST, SUST, SUST, HIT, HIT, SUST, HIT, SUST, HIT, SUST // 16 + +PATTERN07: // Pattern 07: Snare (Channel 6) + db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 17 + db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 18 + db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 19 + db REST, REST, REST, REST, HIT, SUST, SUST, SUST, SUST, SUST, SUST, SUST, HIT, SUST, SUST, SUST // 20 + +PATTERN08: // Pattern 08: Staccato Saw Tooth (Channel 1) + db REST, REST, F5, SUST, SUST, SUST, F5, G5, SUST, G5, SUST, G5, F5, SUST, F5, SUST // 21 + db SUST, SUST, F5, SUST, F5, SUST, F5, G5, SUST, G5, F5, SUST, F5, SUST, SUST, SUST // 22 + db SUST, SUST, C5s, SUST, C5s, SUST, C5s, SUST, C5s, D5s, SUST, D5s, SUST, D5s, SUST, D5s // 23 + db D5s, SUST, F5, SUST, F5, SUST, F5, SUST, D5s, F5, SUST, F5, SUST, SUST, SUST, SUST // 24 +PATTERN09: // Pattern 09: Staccato Saw Tooth Detune (Channel 2) + db REST, REST, C6, SUST, SUST, SUST, C6, D6s, SUST, D6s, SUST, D6s, D6, SUST, D6, SUST // 21 + db SUST, SUST, C6, SUST, C6, SUST, C6, D6s, SUST, D6s, D6, SUST, C6, SUST, SUST, SUST // 22 + db SUST, SUST, G5s, SUST, G5s, SUST, G5s, SUST, G5s, A5s, SUST, A5s, SUST, A5s, SUST, A5s // 23 + db A5s, SUST, C6, SUST, C6, SUST, C6, SUST, A5s, C6, SUST, C6, SUST, SUST, SUST, SUST // 24 + +PATTERNLIST: + dw PATTERN01,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List + dw PATTERN01,PATTERN01,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List + dw PATTERN00,PATTERN00,PATTERN02,PATTERN04,PATTERN00,PATTERN00 // Channel 1..6 Pattern Address List + dw PATTERN00,PATTERN00,PATTERN02,PATTERN05,PATTERN06,PATTERN00 // Channel 1..6 Pattern Address List +PATTERNLISTLOOP: + dw PATTERN01,PATTERN01,PATTERN02,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List + dw PATTERN01,PATTERN01,PATTERN02,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List +PATTERNLISTCHANGE: + dw PATTERN08,PATTERN09,PATTERN03,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List + dw PATTERN08,PATTERN09,PATTERN03,PATTERN04,PATTERN06,PATTERN07 // Channel 1..6 Pattern Address List +PATTERNLISTEND: + +seek($2A00); sampleDIR: + dw SawTooth, SawTooth + 2691 // 0 + dw SynthBass, 0 // 1 + dw Clap, 0 // 2 + dw KickDrum, 0 // 3 + dw Snare, 0 // 4 + +seek($2B00) // Sample Data + insert SawTooth, "BRR/MSAWTOOF(Loop=2691,AD=$FA,SR=$F0,Echo)(C9Pitch=$8868).brr" + insert SynthBass, "BRR/SYNBSS3(AD=$FF,SR=$F0)(C9Pitch=$8868).brr" + insert Clap, "BRR/CLAPTRAP(AD=$FF,SR=$F0)(C9Pitch=$8868).brr" + insert KickDrum, "BRR/KICK5(AD=$FF,SR=$F0)(C9Pitch=$8868).brr" + insert Snare, "BRR/SNAREA13(AD=$FF,SR=$F0)(C9Pitch=$8868).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/CLAPTRAP(AD=$FF,SR=$F0)(C9Pitch=$8868).brr b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/CLAPTRAP(AD=$FF,SR=$F0)(C9Pitch=$8868).brr new file mode 100644 index 00000000..0f04c1dc Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/CLAPTRAP(AD=$FF,SR=$F0)(C9Pitch=$8868).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/KICK5(AD=$FF,SR=$F0)(C9Pitch=$8868).brr b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/KICK5(AD=$FF,SR=$F0)(C9Pitch=$8868).brr new file mode 100644 index 00000000..819a6c45 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/KICK5(AD=$FF,SR=$F0)(C9Pitch=$8868).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/MSAWTOOF(Loop=2691,AD=$FA,SR=$F0,Echo)(C9Pitch=$8868).brr b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/MSAWTOOF(Loop=2691,AD=$FA,SR=$F0,Echo)(C9Pitch=$8868).brr new file mode 100644 index 00000000..131e5685 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/MSAWTOOF(Loop=2691,AD=$FA,SR=$F0,Echo)(C9Pitch=$8868).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SNAREA13(AD=$FF,SR=$F0)(C9Pitch=$8868).brr b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SNAREA13(AD=$FF,SR=$F0)(C9Pitch=$8868).brr new file mode 100644 index 00000000..749e9b3f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SNAREA13(AD=$FF,SR=$F0)(C9Pitch=$8868).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SYNBSS3(AD=$FF,SR=$F0)(C9Pitch=$8868).brr b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SYNBSS3(AD=$FF,SR=$F0)(C9Pitch=$8868).brr new file mode 100644 index 00000000..b6bf6a5f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Axel-F/BRR/SYNBSS3(AD=$FF,SR=$F0)(C9Pitch=$8868).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e08e980d --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "AXEL-F SONG " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Axel-F/make.bat b/roms/snes/peter-lemon-snes/SPC700/Axel-F/make.bat new file mode 100644 index 00000000..e03ef7af --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Axel-F/make.bat @@ -0,0 +1,2 @@ +bass Axel-F_spc.asm +bass Axel-F.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 010. Trumpet (Loop=747,AD=$AF,SR=$82,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 010. Trumpet (Loop=747,AD=$AF,SR=$82,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..e76d0b0f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 010. Trumpet (Loop=747,AD=$AF,SR=$82,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 011. French Horn (Loop=1863,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 011. French Horn (Loop=1863,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..5a3e2813 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 011. French Horn (Loop=1863,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 012. Strings (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 012. Strings (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..c7e786b6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 012. Strings (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 013. Bass Guitar (Loop=1755,AD=$CF,SR=$D0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 013. Bass Guitar (Loop=1755,AD=$CF,SR=$D0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..257dea34 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 013. Bass Guitar (Loop=1755,AD=$CF,SR=$D0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 014. Snare (AD=$FF,SR=$E0)(C9Pitch=$FEF0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 014. Snare (AD=$FF,SR=$E0)(C9Pitch=$FEF0).brr new file mode 100644 index 00000000..bdb86074 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 014. Snare (AD=$FF,SR=$E0)(C9Pitch=$FEF0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 015. Cymbal (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$D2F0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 015. Cymbal (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$D2F0).brr new file mode 100644 index 00000000..f68dd912 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/101. Memories of the Past - 015. Cymbal (Loop=27,AD=$F9,SR=$E0,Echo)(C9Pitch=$D2F0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 005. Glockenspiel (Loop=1584,AD=$AF,SR=$10,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 005. Glockenspiel (Loop=1584,AD=$AF,SR=$10,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..fbc74b17 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 005. Glockenspiel (Loop=1584,AD=$AF,SR=$10,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 010. Voice Soprano (Loop=9,AD=$F8,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 010. Voice Soprano (Loop=9,AD=$F8,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..c6e5f114 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/102. The Other Side of Reminiscence - 010. Voice Soprano (Loop=9,AD=$F8,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 011. Euphonium (Loop=1062,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 011. Euphonium (Loop=1062,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..8c19e48b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 011. Euphonium (Loop=1062,AD=$FF,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 013. Harp (Loop=1755,AD=$DE,SR=$CF,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 013. Harp (Loop=1755,AD=$DE,SR=$CF,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..ce1c378a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/103. Beyond the Empty Space - 013. Harp (Loop=1755,AD=$DE,SR=$CF,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/104. An Offering to the Holy King Gort - 011. Flute (Loop=774,AD=$FF,SR=$E0)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/104. An Offering to the Holy King Gort - 011. Flute (Loop=774,AD=$FF,SR=$E0)(C9Pitch=$9600).brr new file mode 100644 index 00000000..be80499e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/104. An Offering to the Holy King Gort - 011. Flute (Loop=774,AD=$FF,SR=$E0)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/105. Gathering of Comrades - 013. Tuba (Loop=9,AD=$8B,SR=$6A,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/105. Gathering of Comrades - 013. Tuba (Loop=9,AD=$8B,SR=$6A,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..cc3a1421 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/105. Gathering of Comrades - 013. Tuba (Loop=9,AD=$8B,SR=$6A,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 011. String Pluck (Loop=1665,AD=$CF,SR=$16,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 011. String Pluck (Loop=1665,AD=$CF,SR=$16,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..ea8cb323 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 011. String Pluck (Loop=1665,AD=$CF,SR=$16,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 013. Harmonica (Loop=1116,AD=$F7,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 013. Harmonica (Loop=1116,AD=$F7,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..3244a6a4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/106. Hometown Tibelis - 013. Harmonica (Loop=1116,AD=$F7,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 013. Tamborine (AD=$FF,SR=$E0,Echo)(C9Pitch=$AF80).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 013. Tamborine (AD=$FF,SR=$E0,Echo)(C9Pitch=$AF80).brr new file mode 100644 index 00000000..c8fb9792 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 013. Tamborine (AD=$FF,SR=$E0,Echo)(C9Pitch=$AF80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 014. Violin (Loop=1026,AD=$FA,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 014. Violin (Loop=1026,AD=$FA,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..77529c07 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/108. Fine Goods - 014. Violin (Loop=1026,AD=$FA,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 012. Hi-hat Closed (AD=$FC,SR=$F8)(C9Pitch=$E860).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 012. Hi-hat Closed (AD=$FC,SR=$F8)(C9Pitch=$E860).brr new file mode 100644 index 00000000..a504970f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 012. Hi-hat Closed (AD=$FC,SR=$F8)(C9Pitch=$E860).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 013. Hi-hat Open (AD=$FC,SR=$EF)(C9Pitch=$E160).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 013. Hi-hat Open (AD=$FC,SR=$EF)(C9Pitch=$E160).brr new file mode 100644 index 00000000..c2b5f9ad Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 013. Hi-hat Open (AD=$FC,SR=$EF)(C9Pitch=$E160).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 015. Bass Drum (AD=$FF,SR=$F6)(C9Pitch=$FEF0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 015. Bass Drum (AD=$FF,SR=$F6)(C9Pitch=$FEF0).brr new file mode 100644 index 00000000..22f68728 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 015. Bass Drum (AD=$FF,SR=$F6)(C9Pitch=$FEF0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 016. Tom-tom (AD=$FF,SR=$F8,Echo)(C9Pitch=$FEF0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 016. Tom-tom (AD=$FF,SR=$F8,Echo)(C9Pitch=$FEF0).brr new file mode 100644 index 00000000..388fa3ca Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 016. Tom-tom (AD=$FF,SR=$F8,Echo)(C9Pitch=$FEF0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 018. Tom-tom Floor (Loop=1098,AD=$FF,SR=$F5)(C9Pitch=$FEF0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 018. Tom-tom Floor (Loop=1098,AD=$FF,SR=$F5)(C9Pitch=$FEF0).brr new file mode 100644 index 00000000..72dfd300 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 018. Tom-tom Floor (Loop=1098,AD=$FF,SR=$F5)(C9Pitch=$FEF0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 019. Orchestra Hit (AD=$FE,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 019. Orchestra Hit (AD=$FE,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..f0ba8d3e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/111. Roar of the Beast - 019. Orchestra Hit (AD=$FE,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/112. Fire Raid - 017. Synth (Loop=9,AD=$CF,SR=$00,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/112. Fire Raid - 017. Synth (Loop=9,AD=$CF,SR=$00,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..36a0784d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/112. Fire Raid - 017. Synth (Loop=9,AD=$CF,SR=$00,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/113. At the Base of Gort's Flag - 012. Timpani (Loop=819,AD=$8F,SR=$B4,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/113. At the Base of Gort's Flag - 012. Timpani (Loop=819,AD=$8F,SR=$B4,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..1ff88582 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/113. At the Base of Gort's Flag - 012. Timpani (Loop=819,AD=$8F,SR=$B4,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/114. Goodnight, Sophia - 011. Voice Bass (Loop=9,AD=$DB,SR=$A0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/114. Goodnight, Sophia - 011. Voice Bass (Loop=9,AD=$DB,SR=$A0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..a0e21773 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/114. Goodnight, Sophia - 011. Voice Bass (Loop=9,AD=$DB,SR=$A0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/116. Clouds Riding the Wind - 011. Clarinet (Loop=1008,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/116. Clouds Riding the Wind - 011. Clarinet (Loop=1008,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..244d1077 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/116. Clouds Riding the Wind - 011. Clarinet (Loop=1008,AD=$F9,SR=$E0,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/117. We're Cheerful Workers! - 016. Xylophone (Loop=864,AD=$FF,SR=$50,Echo)(C9Pitch=$9600).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/117. We're Cheerful Workers! - 016. Xylophone (Loop=864,AD=$FF,SR=$50,Echo)(C9Pitch=$9600).brr new file mode 100644 index 00000000..ffde8c1d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/117. We're Cheerful Workers! - 016. Xylophone (Loop=864,AD=$FF,SR=$50,Echo)(C9Pitch=$9600).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/125. World of Twilight - 013. Piccolo (Loop=9,AD=$FA,SR=$A0,Echo)(C9Pitch=$9600) b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/125. World of Twilight - 013. Piccolo (Loop=9,AD=$FA,SR=$A0,Echo)(C9Pitch=$9600) new file mode 100644 index 00000000..ef80bf59 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/125. World of Twilight - 013. Piccolo (Loop=9,AD=$FA,SR=$A0,Echo)(C9Pitch=$9600) differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/135. Sunsoft - 010. Sunsoft (AD=$FF,SR=$E0,Echo)(C9Pitch=$80A0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/135. Sunsoft - 010. Sunsoft (AD=$FF,SR=$E0,Echo)(C9Pitch=$80A0).brr new file mode 100644 index 00000000..cd117955 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Albert Odyssey/135. Sunsoft - 010. Sunsoft (AD=$FF,SR=$E0,Echo)(C9Pitch=$80A0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 032. Church Organ (Loop=729,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 032. Church Organ (Loop=729,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr new file mode 100644 index 00000000..2266e654 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 032. Church Organ (Loop=729,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 033. Voice Soprano (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$BB10).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 033. Voice Soprano (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$BB10).brr new file mode 100644 index 00000000..6cc66126 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 033. Voice Soprano (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$BB10).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 034. Voice Bass Short (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 034. Voice Bass Short (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr new file mode 100644 index 00000000..edb54fbc Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 034. Voice Bass Short (Loop=531,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 035. Piano (Loop=5265,AD=$FF,SR=$EF)(C9Pitch=$D180).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 035. Piano (Loop=5265,AD=$FF,SR=$EF)(C9Pitch=$D180).brr new file mode 100644 index 00000000..eff9cd53 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 1). 035. Piano (Loop=5265,AD=$FF,SR=$EF)(C9Pitch=$D180).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 032. Strings (Loop=801,AD=$F4,SR=$E6,Echo)(C9Pitch=$D060).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 032. Strings (Loop=801,AD=$F4,SR=$E6,Echo)(C9Pitch=$D060).brr new file mode 100644 index 00000000..ec0b6fd7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 032. Strings (Loop=801,AD=$F4,SR=$E6,Echo)(C9Pitch=$D060).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 033. French Horn (Loop=2052,AD=$FF,SR=$E5,Echo)(C9Pitch=96B0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 033. French Horn (Loop=2052,AD=$FF,SR=$E5,Echo)(C9Pitch=96B0).brr new file mode 100644 index 00000000..31035158 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 033. French Horn (Loop=2052,AD=$FF,SR=$E5,Echo)(C9Pitch=96B0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Pitch=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Pitch=$C900).brr new file mode 100644 index 00000000..2a42437f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Pitch=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 035. Trumpet (Loop=1026,AD=$FF,SR=$E0,Echo)(C9Pitch=$C8E0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 035. Trumpet (Loop=1026,AD=$FF,SR=$E0,Echo)(C9Pitch=$C8E0).brr new file mode 100644 index 00000000..000bf2e2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 035. Trumpet (Loop=1026,AD=$FF,SR=$E0,Echo)(C9Pitch=$C8E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 036. Harp Bass (Loop=1152,AD=$FA,SR=$E9)(C9Pitch=$C920).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 036. Harp Bass (Loop=1152,AD=$FA,SR=$E9)(C9Pitch=$C920).brr new file mode 100644 index 00000000..82a24f76 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 036. Harp Bass (Loop=1152,AD=$FA,SR=$E9)(C9Pitch=$C920).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 037. Flute (Loop=1089,AD=$FF,SR=$E0,Echo)(C9Pitch=$85E0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 037. Flute (Loop=1089,AD=$FF,SR=$E0,Echo)(C9Pitch=$85E0).brr new file mode 100644 index 00000000..210f5ad7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 037. Flute (Loop=1089,AD=$FF,SR=$E0,Echo)(C9Pitch=$85E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 038. Chime (Loop=3393,AD=$FF,SR=$EA,Echo)(C9Pitch=$A1A0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 038. Chime (Loop=3393,AD=$FF,SR=$EA,Echo)(C9Pitch=$A1A0).brr new file mode 100644 index 00000000..f6777402 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 038. Chime (Loop=3393,AD=$FF,SR=$EA,Echo)(C9Pitch=$A1A0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 039. Tuba (Loop=2196,AD=$FF,SR=$E9,Echo)(C9Pitch=$C920).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 039. Tuba (Loop=2196,AD=$FF,SR=$E9,Echo)(C9Pitch=$C920).brr new file mode 100644 index 00000000..19b4e4b3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 2). 039. Tuba (Loop=2196,AD=$FF,SR=$E9,Echo)(C9Pitch=$C920).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 032. Oboe (Loop=1494,AD=$F8,SR=$E6,Echo)(C9Pitch=$C8E0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 032. Oboe (Loop=1494,AD=$F8,SR=$E6,Echo)(C9Pitch=$C8E0).brr new file mode 100644 index 00000000..022dd955 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 032. Oboe (Loop=1494,AD=$F8,SR=$E6,Echo)(C9Pitch=$C8E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 036. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 036. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..fd1e6d4d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 036. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 037. Bass Guitar (Loop=945,AD=$FF,SR=$EE)(C9Pitch=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 037. Bass Guitar (Loop=945,AD=$FF,SR=$EE)(C9Pitch=$C900).brr new file mode 100644 index 00000000..f493e425 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/101. Opening Theme (part 3). 037. Bass Guitar (Loop=945,AD=$FF,SR=$EE)(C9Pitch=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 033. Double Bass (Loop=1656,AD=$FF,SR=$EC,Echo)(C9Pitch=$D9A0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 033. Double Bass (Loop=1656,AD=$FF,SR=$EC,Echo)(C9Pitch=$D9A0).brr new file mode 100644 index 00000000..d2c27751 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 033. Double Bass (Loop=1656,AD=$FF,SR=$EC,Echo)(C9Pitch=$D9A0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 035. Finger Click Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 035. Finger Click Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..6c52014b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 035. Finger Click Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 038. Breath Noise (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 038. Breath Noise (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..42713f77 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/102. The Mines of Narshe. 038. Breath Noise (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 034. Cymbal (Loop=2700,AD=$FF,SR=$EE)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 034. Cymbal (Loop=2700,AD=$FF,SR=$EE)(C9Pitch=$8000).brr new file mode 100644 index 00000000..dc9e8648 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 034. Cymbal (Loop=2700,AD=$FF,SR=$EE)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 036. Tom-tom (AD=$FF,SR=$E0)(C9Pitch=$9400).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 036. Tom-tom (AD=$FF,SR=$E0)(C9Pitch=$9400).brr new file mode 100644 index 00000000..308527f0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 036. Tom-tom (AD=$FF,SR=$E0)(C9Pitch=$9400).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 037. Strings Bass (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$EA20).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 037. Strings Bass (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$EA20).brr new file mode 100644 index 00000000..cb489a62 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/104. Locke. 037. Strings Bass (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$EA20).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 034. Electric Guitar (Loop=1530,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 034. Electric Guitar (Loop=1530,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr new file mode 100644 index 00000000..29a9105d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 034. Electric Guitar (Loop=1530,AD=$FF,SR=$E0,Echo)(C9Pitch=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 036. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 036. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..c9105bb1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 036. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 037. Hi-hat Open (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 037. Hi-hat Open (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..70627683 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 037. Hi-hat Open (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 039. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 039. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..45122bbe Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/105. Battle Theme. 039. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/108. Kefka. 032. String Pluck (Loop=1485,AD=$FF,SR=$EF)(C9Pitch=$DAC0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/108. Kefka. 032. String Pluck (Loop=1485,AD=$FF,SR=$EF)(C9Pitch=$DAC0).brr new file mode 100644 index 00000000..e4ae4e29 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/108. Kefka. 032. String Pluck (Loop=1485,AD=$FF,SR=$EF)(C9Pitch=$DAC0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 034. Organ (Loop=315,AD=$FF,SR=$E0,Echo)(C9Pitch=$E240).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 034. Organ (Loop=315,AD=$FF,SR=$E0,Echo)(C9Pitch=$E240).brr new file mode 100644 index 00000000..45e0719e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 034. Organ (Loop=315,AD=$FF,SR=$E0,Echo)(C9Pitch=$E240).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 038. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 038. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..deb482d0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/109. Mt. Koltz. 038. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 032. Jaw Harp (AD=$FF,SR=$E0,Echo)(C9Pitch=$E9A0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 032. Jaw Harp (AD=$FF,SR=$E0,Echo)(C9Pitch=$E9A0).brr new file mode 100644 index 00000000..59d08b63 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 032. Jaw Harp (AD=$FF,SR=$E0,Echo)(C9Pitch=$E9A0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 033. Whistle (Loop=999,AD=$FF,SR=$E0,Echo)(C9Pitch=$DC80).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 033. Whistle (Loop=999,AD=$FF,SR=$E0,Echo)(C9Pitch=$DC80).brr new file mode 100644 index 00000000..b0833414 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 033. Whistle (Loop=999,AD=$FF,SR=$E0,Echo)(C9Pitch=$DC80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 034. Guitar (Loop=3069,AD=$FF,SR=$F0)(C9Pitch=$D620).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 034. Guitar (Loop=3069,AD=$FF,SR=$F0)(C9Pitch=$D620).brr new file mode 100644 index 00000000..d6bbd208 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 034. Guitar (Loop=3069,AD=$FF,SR=$F0)(C9Pitch=$D620).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 040. Side Stick (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 040. Side Stick (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..6feb1e9b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/111. Shadow. 040. Side Stick (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 033. Shakuhachi (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$9790).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 033. Shakuhachi (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$9790).brr new file mode 100644 index 00000000..0d4b2126 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 033. Shakuhachi (Loop=1143,AD=$FF,SR=$E0,Echo)(C9Pitch=$9790).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 035. Jingle Bell (AD=$FF,SR=$EC,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 035. Jingle Bell (AD=$FF,SR=$EC,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..7142dd6b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/113. Cyan. 035. Jingle Bell (AD=$FF,SR=$EC,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/115. The Phantom Forest. 034. Voice ''Ooh'' (Loop=1593,AD=$FF,SR=$E0,Echo)(C9Pitch=$D060).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/115. The Phantom Forest. 034. Voice ''Ooh'' (Loop=1593,AD=$FF,SR=$E0,Echo)(C9Pitch=$D060).brr new file mode 100644 index 00000000..8abcd1cf Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/115. The Phantom Forest. 034. Voice ''Ooh'' (Loop=1593,AD=$FF,SR=$E0,Echo)(C9Pitch=$D060).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/116. The Phantom Train. 004. Snare Synth (Loop=27,AD=$FF,SR=$00,Echo,Noise)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/116. The Phantom Train. 004. Snare Synth (Loop=27,AD=$FF,SR=$00,Echo,Noise)(C9Pitch=$8000).brr new file mode 100644 index 00000000..494a7297 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/116. The Phantom Train. 004. Snare Synth (Loop=27,AD=$FF,SR=$00,Echo,Noise)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 034. Cabasa (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 034. Cabasa (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..adeefdd9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 034. Cabasa (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 036. Bongo (Loop=2268,AD=$FF,SR=$F3)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 036. Bongo (Loop=2268,AD=$FF,SR=$F3)(C9Pitch=$8000).brr new file mode 100644 index 00000000..15e40981 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 036. Bongo (Loop=2268,AD=$FF,SR=$F3)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 038. Guiro (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 038. Guiro (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..56367eba Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 038. Guiro (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 040. Glass Bottle (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 040. Glass Bottle (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..6a41724b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/117. Wild West. 040. Glass Bottle (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr new file mode 100644 index 00000000..2782ade7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 036. Guitar Treble (Loop=2952,AD=$FF,SR=$F1)(C9Pitch=$969D).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 036. Guitar Treble (Loop=2952,AD=$FF,SR=$F1)(C9Pitch=$969D).brr new file mode 100644 index 00000000..0dae4d95 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/118. Gau. 036. Guitar Treble (Loop=2952,AD=$FF,SR=$F1)(C9Pitch=$969D).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 032. Recorder Harmony (Loop=2583,AD=$FF,SR=$E0,Echo)(C9Pitch=$A7A0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 032. Recorder Harmony (Loop=2583,AD=$FF,SR=$E0,Echo)(C9Pitch=$A7A0).brr new file mode 100644 index 00000000..135a0c8d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 032. Recorder Harmony (Loop=2583,AD=$FF,SR=$E0,Echo)(C9Pitch=$A7A0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 036. Recorder (Loop=1260,AD=$FF,SR=$E0,Echo)(C9Pitch=$C920).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 036. Recorder (Loop=1260,AD=$FF,SR=$E0,Echo)(C9Pitch=$C920).brr new file mode 100644 index 00000000..78bd15af Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/120. Kids Run Through the City. 036. Recorder (Loop=1260,AD=$FF,SR=$E0,Echo)(C9Pitch=$C920).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/122. Celes. 035. Glockenspiel (Loop=3096,AD=$FF,SR=$EA,Echo)(C9Pitch=$C8E0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/122. Celes. 035. Glockenspiel (Loop=3096,AD=$FF,SR=$EA,Echo)(C9Pitch=$C8E0).brr new file mode 100644 index 00000000..9c8cf9e2 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/122. Celes. 035. Glockenspiel (Loop=3096,AD=$FF,SR=$EA,Echo)(C9Pitch=$C8E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/124. The Decisive Battle. 040. Snare Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/124. The Decisive Battle. 040. Snare Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..96a70459 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/124. The Decisive Battle. 040. Snare Bass (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 032. Pan Flute (Loop=1881,AD=$FF,SR=$E0,Echo)(C9Freq=$D18A).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 032. Pan Flute (Loop=1881,AD=$FF,SR=$E0,Echo)(C9Freq=$D18A).brr new file mode 100644 index 00000000..c7f8b9e0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 032. Pan Flute (Loop=1881,AD=$FF,SR=$E0,Echo)(C9Freq=$D18A).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 035. Banjo (Loop=891,AD=$FF,SR=$F0)(C9Freq=$965C).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 035. Banjo (Loop=891,AD=$FF,SR=$F0)(C9Freq=$965C).brr new file mode 100644 index 00000000..014884be Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/201. Terra. 035. Banjo (Loop=891,AD=$FF,SR=$F0)(C9Freq=$965C).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/202. Coin Song. 003. Sine Wave Synth (Loop=27,AD=$FF,SR=$ED,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/202. Coin Song. 003. Sine Wave Synth (Loop=27,AD=$FF,SR=$ED,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..69e79012 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/202. Coin Song. 003. Sine Wave Synth (Loop=27,AD=$FF,SR=$ED,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..175071e0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 005. Sawtooth Wave Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 005. Sawtooth Wave Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..ee5676ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 005. Sawtooth Wave Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 040. Vocoder ''Cho'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 040. Vocoder ''Cho'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..12a8294a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 040. Vocoder ''Cho'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 041. Vocoder ''Co'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 041. Vocoder ''Co'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..4a0745d8 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 041. Vocoder ''Co'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 042. Vocoder ''Bo'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 042. Vocoder ''Bo'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..fc7f7110 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/203. Techno de Chocobo. 042. Vocoder ''Bo'' (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 001. Piano Synth (Loop=0,AD=$FF,SR=$F4,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 001. Piano Synth (Loop=0,AD=$FF,SR=$F4,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..482594be Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 001. Piano Synth (Loop=0,AD=$FF,SR=$F4,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 006. Bass Synth (Loop=0,AD=$FF,SR=$F4)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 006. Bass Synth (Loop=0,AD=$FF,SR=$F4)(C9Freq=$8610).brr new file mode 100644 index 00000000..96a2b810 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 006. Bass Synth (Loop=0,AD=$FF,SR=$F4)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 007. Noise Synth (Loop=27,AD=$F4,SR=$E0,Echo,PitchMod)(C9Freq=$C918).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 007. Noise Synth (Loop=27,AD=$F4,SR=$E0,Echo,PitchMod)(C9Freq=$C918).brr new file mode 100644 index 00000000..4037b3f1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/205. Slam Shuffle. 007. Noise Synth (Loop=27,AD=$F4,SR=$E0,Echo,PitchMod)(C9Freq=$C918).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/207. Overture (part 2). 034. Voice Bass (Loop=1143,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/207. Overture (part 2). 034. Voice Bass (Loop=1143,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr new file mode 100644 index 00000000..be69c3ed Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/207. Overture (part 2). 034. Voice Bass (Loop=1143,AD=$FA,SR=$E0,Echo)(C9Pitch=$AB40).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/210. Grand Finale (part 1). 032. Audience (Loop=18,AD=$FF,SR=$E0,Echo)(C9Pitch=$0200).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/210. Grand Finale (part 1). 032. Audience (Loop=18,AD=$FF,SR=$E0,Echo)(C9Pitch=$0200).brr new file mode 100644 index 00000000..1ebe2a5b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/210. Grand Finale (part 1). 032. Audience (Loop=18,AD=$FF,SR=$E0,Echo)(C9Pitch=$0200).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 000. Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Pitch=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 000. Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Pitch=$8610).brr new file mode 100644 index 00000000..4de2cc2c Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 000. Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Pitch=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 036. Drill (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 036. Drill (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..032f8191 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 036. Drill (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 037. Anvil (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 037. Anvil (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr new file mode 100644 index 00000000..12b4c021 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/214. Devil's Lab. 037. Anvil (AD=$FF,SR=$E0,Echo)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 032. Xylophone (Loop=1620,AD=$FF,SR=$F5)(C9Pitch=$C920).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 032. Xylophone (Loop=1620,AD=$FF,SR=$F5)(C9Pitch=$C920).brr new file mode 100644 index 00000000..2834432d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 032. Xylophone (Loop=1620,AD=$FF,SR=$F5)(C9Pitch=$C920).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 034. Wood Block (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 034. Wood Block (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..c237bb92 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 034. Wood Block (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 035. Voice Whoop (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 035. Voice Whoop (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..95d2cd4c Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/216. ____. 035. Voice Whoop (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/217. Mog. 036. Banjo Bass (Loop=3897,AD=$FF,SR=$F3)(C9Freq=$9CE0).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/217. Mog. 036. Banjo Bass (Loop=3897,AD=$FF,SR=$F3)(C9Freq=$9CE0).brr new file mode 100644 index 00000000..59a8714d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/217. Mog. 036. Banjo Bass (Loop=3897,AD=$FF,SR=$F3)(C9Freq=$9CE0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/218. Strago. 039. Finger Click (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/218. Strago. 039. Finger Click (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..86d99ae9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/218. Strago. 039. Finger Click (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/219. Relm. 032. Bag Pipes (Loop=3042,AD=$FF,SR=$E0,Echo)(C9Pitch=$CD70).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/219. Relm. 032. Bag Pipes (Loop=3042,AD=$FF,SR=$E0,Echo)(C9Pitch=$CD70).brr new file mode 100644 index 00000000..a051cf22 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/219. Relm. 032. Bag Pipes (Loop=3042,AD=$FF,SR=$E0,Echo)(C9Pitch=$CD70).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/303. The Fierce Battle. 040. Pitch Mod Synth (Loop=909,AD=$FF,SR=$E0,Echo)(C9Pitch=$AB20).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/303. The Fierce Battle. 040. Pitch Mod Synth (Loop=909,AD=$FF,SR=$E0,Echo)(C9Pitch=$AB20).brr new file mode 100644 index 00000000..684ca726 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/303. The Fierce Battle. 040. Pitch Mod Synth (Loop=909,AD=$FF,SR=$E0,Echo)(C9Pitch=$AB20).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/305. Dark World. 033. Piano Harp (Loop=1602,AD=$FF,SR=$ED,Echo)(C9Pitch=$9830).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/305. Dark World. 033. Piano Harp (Loop=1602,AD=$FF,SR=$ED,Echo)(C9Pitch=$9830).brr new file mode 100644 index 00000000..6eaab3e4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/305. Dark World. 033. Piano Harp (Loop=1602,AD=$FF,SR=$ED,Echo)(C9Pitch=$9830).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/314. Dancing Mad (Full). 033. Church Organ Bass (Loop=27,AD=$FF,SR=$E0,Echo)(C9Pitch=$B120).brr b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/314. Dancing Mad (Full). 033. Church Organ Bass (Loop=27,AD=$FF,SR=$E0,Echo)(C9Pitch=$B120).brr new file mode 100644 index 00000000..56286ed7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/BRRSamples/Final Fantasy 6/314. Dancing Mad (Full). 033. Church Organ Bass (Loop=27,AD=$FF,SR=$E0,Echo)(C9Pitch=$B120).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude.spc b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude.spc new file mode 100644 index 00000000..fce416aa Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/001. Synth Harp (Loop=9,AD=$FB,SR=$F6,Echo)(C9Freq=$EC80).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/001. Synth Harp (Loop=9,AD=$FB,SR=$F6,Echo)(C9Freq=$EC80).brr new file mode 100644 index 00000000..9493faa0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/001. Synth Harp (Loop=9,AD=$FB,SR=$F6,Echo)(C9Freq=$EC80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/002. Oboe (Loop=4770,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/002. Oboe (Loop=4770,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr new file mode 100644 index 00000000..4ba018f5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/002. Oboe (Loop=4770,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/003. Bassoon (Loop=3015,AD=$FF,SR=$E0,Echo)(C9Freq=$B080).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/003. Bassoon (Loop=3015,AD=$FF,SR=$E0,Echo)(C9Freq=$B080).brr new file mode 100644 index 00000000..acc54942 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/003. Bassoon (Loop=3015,AD=$FF,SR=$E0,Echo)(C9Freq=$B080).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/004. French Horn (Loop=5301,AD=$FF,SR=$E0,Echo)(C9Freq=$FE80).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/004. French Horn (Loop=5301,AD=$FF,SR=$E0,Echo)(C9Freq=$FE80).brr new file mode 100644 index 00000000..36a9568f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/004. French Horn (Loop=5301,AD=$FF,SR=$E0,Echo)(C9Freq=$FE80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/005. Strings (Loop=5616,AD=$F4,SR=$E6,Echo)(C9Freq=$F880).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/005. Strings (Loop=5616,AD=$F4,SR=$E6,Echo)(C9Freq=$F880).brr new file mode 100644 index 00000000..dee15951 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/005. Strings (Loop=5616,AD=$F4,SR=$E6,Echo)(C9Freq=$F880).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/006. Flute (Loop=2322,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/006. Flute (Loop=2322,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr new file mode 100644 index 00000000..cfaed34c Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/006. Flute (Loop=2322,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/007. Clarinet (Loop=3852,AD=$FF,SR=$E0,Echo)(C9Freq=$D080).brr b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/007. Clarinet (Loop=3852,AD=$FF,SR=$E0,Echo)(C9Freq=$D080).brr new file mode 100644 index 00000000..c71aa2e1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/BRR/007. Clarinet (Loop=3852,AD=$FF,SR=$E0,Echo)(C9Freq=$D080).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.asm b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.asm new file mode 100644 index 00000000..d7e3e7ae --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.asm @@ -0,0 +1,29 @@ +// SNES SPC700 FFVII Prelude Song Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "FFVIIPrelude.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, $8000) // Load SPC File To SMP/DSP + TransferBlockSPC($28000, SPCRAM+$8000, SPCROM.size-$8000) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 1 & 2 +seek($18000) +insert SPCROM, "FFVIIPrelude.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.sfc b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.sfc new file mode 100644 index 00000000..8626c713 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.spc b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.spc new file mode 100644 index 00000000..50dcf9ba Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude_spc.asm b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude_spc.asm new file mode 100644 index 00000000..81bc4386 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/FFVIIPrelude_spc.asm @@ -0,0 +1,498 @@ +// SNES SPC700 FFVII Prelude Song Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "FFVIIPrelude.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(180) // Maximum Quantization ms +constant PatternSize(256) // Pattern Size (1..256) +constant ChannelCount(8) // Channel Count (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($B800,$48) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$B8) // Echo Source Address + WDSP(DSP_EDL,9) // Echo Delay + WDSP(DSP_EON,%11111111) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,70) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,25) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,25) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: Synth Harp + WDSP(DSP_V0ADSR1,$FB) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$F6) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,25) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,25) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,1) // Voice 1: Flute + WDSP(DSP_V1ADSR1,$FF) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$E0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,25) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,25) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,2) // Voice 2: Oboe + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$E0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,25) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,25) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,3) // Voice 3: Clarinet + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$E0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,25) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,25) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,4) // Voice 4: Bassoon + WDSP(DSP_V4ADSR1,$FF) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$E0) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,25) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,25) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,5) // Voice 5: French Horn + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$E0) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + + WDSP(DSP_V6VOLL,25) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,25) // Voice 6: Volume Right + WDSP(DSP_V6SRCN,6) // Voice 6: Strings + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$E0) // Voice 6: ADSR2 + WDSP(DSP_V6GAIN,127) // Voice 6: Gain + + WDSP(DSP_V7VOLL,25) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,25) // Voice 7: Volume Right + WDSP(DSP_V7SRCN,6) // Voice 7: Strings + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + WDSP(DSP_V7GAIN,127) // Voice 7: Gain + +StartSong: + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, SynthHarpPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, FlutePitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, OboePitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, ClarinetPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, BassoonPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, FrenchHornPitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(6, 6, StringsPitchTable) // Channel 7 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(7, 7, StringsPitchTable) // Channel 8 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..8 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +SynthHarpPitchTable: + WritePitchTable($EC80) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +FlutePitchTable: + WritePitchTable($EC80) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +OboePitchTable: + WritePitchTable($EC80) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +ClarinetPitchTable: + WritePitchTable($D080) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +BassoonPitchTable: + WritePitchTable($B080) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +FrenchHornPitchTable: + WritePitchTable($FE80) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +StringsPitchTable: + WritePitchTable($F880) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + +PATTERN00: // Pattern 00: Rest (Channel 1..8) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 1 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 2 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 3 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 4 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 5 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 6 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 7 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 8 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 9 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 10 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 11 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 12 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 13 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 14 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 15 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 16 + +PATTERN01: // Pattern 01: Synth Harp (Channel 1) + db C2, D2, E2, G2, C3, D3, E3, G3, C4, D4, E4, G4, C5, D5, E5, G5 // 1 + db C6, G5, E5, D5, C5, G4, E4, D4, C4, G3, E3, D3, C3, G2, E2, D2 // 2 + db A1, B1, C2, E2, A2, B2, C3, E3, A3, B3, C4, E4, A4, B4, C5, E5 // 3 + db A5, E5, C5, B4, A4, E4, C4, B3, A3, E3, C3, B2, A2, E2, C2, B1 // 4 + db C2, D2, E2, G2, C3, D3, E3, G3, C4, D4, E4, G4, C5, D5, E5, G5 // 5 + db C6, G5, E5, D5, C5, G4, E4, D4, C4, G3, E3, D3, C3, G2, E2, D2 // 6 + db A1, B1, C2, E2, A2, B2, C3, E3, A3, B3, C4, E4, A4, B4, C5, E5 // 7 + db A5, E5, C5, B4, A4, E4, C4, B3, A3, E3, C3, B2, A2, E2, C2, B1 // 8 + db A1, C2, F2, G2, A2, C3, F3, G3, A3, C4, F4, G4, A4, C5, F5, G5 // 9 + db A5, G5, F5, C5, A4, G4, F4, C4, A3, G3, F3, C3, A2, G2, F2, C2 // 10 + db B1, D2, G2, A2, B2, D3, G3, A3, B3, D4, G4, A4, B4, D5, G5, A5 // 11 + db B5, A5, G5, D5, B4, A4, G4, D4, B3, A3, G3, D3, B2, A2, G2, D2 // 12 + db G1s, C2, E2b, G2, G2s, C3, E3b, G3, G3s, C4, E4b, G4, G4s, C5, E5b, G5 // 13 + db G5s, G5, E5b, C5, G4s, G4, E4b, C4, G3s, G3, E3b, C3, G2s, G2, E2b, C2 // 14 + db B1b, D2, F2, A2, B2b, D3, F3, A3, B3b, D4, F4, A4, B4b, D5, F5, A5 // 15 + db B5b, A5, F5, D5, B4b, A4, F4, D4, B3b, A3, F3, D3, B2b, A2, F2, D2 // 16 + +PATTERN02: // Pattern 02: Flute (Channel 2) + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 17 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, F4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 18 + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 21 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, F4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db F4, SUST, G4, SUST, E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 23 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 24 + db C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 25 + db B3, SUST, SUST, SUST, SUST, SUST, SUST, REST, C4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, E4, SUST, SUST, REST // 27 + db F4, SUST, SUST, SUST, SUST, SUST, SUST, REST, D4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db D4, SUST, SUST, SUST, C4, SUST, B3b, SUST, G3s, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 29 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 30 + db E4b, SUST, SUST, SUST, D4, SUST, C4, SUST, B3b, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN03: // Pattern 03: Flute (Channel 2) + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 33 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, F4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 37 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, F4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db F4, SUST, G4, SUST, E4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db F4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 41 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 43 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db F4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN04: // Pattern 04: Oboe (Channel 3) + db C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 17 + db B3, SUST, SUST, SUST, SUST, SUST, SUST, REST, D4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 18 + db C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 21 + db B3, SUST, SUST, SUST, SUST, SUST, SUST, REST, D4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db D4, SUST, E4, SUST, C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 23 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 24 + db A3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 25 + db G3, SUST, SUST, SUST, SUST, SUST, SUST, REST, A3, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db B3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C4, SUST, SUST, REST // 27 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, G4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db F4, SUST, SUST, SUST, E4b, SUST, D4, SUST, C4, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 29 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 30 + db G4, SUST, SUST, SUST, F4, SUST, E4b, SUST, D4, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN05: // Pattern 05: Oboe (Channel 3) + db G3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 33 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db A3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db G3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 37 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db A3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db A3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 41 + db G3, SUST, SUST, SUST, SUST, SUST, SUST, REST, A3, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db B3, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C4, SUST, SUST, REST // 43 + db D4, SUST, SUST, SUST, SUST, SUST, SUST, REST, B3, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db G3s, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db B3b, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN06: // Pattern 06: Clarinet (Channel 4) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 17 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 18 + db A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 19 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, REST, C5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 21 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 23 + db C5, SUST, SUST, REST, D5, SUST, SUST, REST, E5, SUST, SUST, REST, G5, SUST, SUST, REST // 24 + db A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 25 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, REST, F5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 27 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 29 + db C5, SUST, SUST, REST, D5, SUST, SUST, REST, E5b, SUST, SUST, REST, F5, SUST, SUST, REST // 30 + db G5, SUST, SUST, REST, F5, SUST, E5b, SUST, D5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN07: // Pattern 07: Clarinet (Channel 4) + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 33 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, REST, D5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 37 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 37 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, REST, D5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db D5, SUST, E5, SUST, C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 41 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, REST, C5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, E5, SUST, SUST, REST // 43 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, REST, D5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN08: // Pattern 08: Bassoon (Channel 5) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 17 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 18 + db C7, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 19 + db B6, SUST, SUST, SUST, SUST, SUST, SUST, REST, A6, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db E7, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 21 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 23 + db A6, SUST, SUST, REST, B6, SUST, SUST, REST, C7, SUST, SUST, REST, E7, SUST, SUST, REST // 24 + db F7, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 25 + db E7, SUST, SUST, SUST, SUST, SUST, SUST, REST, D7, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db B6, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C7, SUST, SUST, REST // 27 + db D7, SUST, SUST, SUST, SUST, SUST, SUST, REST, B6, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 29 + db G6s, SUST, SUST, REST, B6b, SUST, SUST, REST, C7, SUST, SUST, REST, D7, SUST, SUST, REST // 30 + db E7b, SUST, SUST, REST, D7, SUST, C7, SUST, B6b, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN09: // Pattern 09: Bassoon (Channel 5) + db C6, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 33 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db C6, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 37 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 41 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 43 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db G5s, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db B5b, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN10: // Pattern 10: FrenchHorn (Channel 6) + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 33 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, REST, D5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 37 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, REST, D5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db D5, SUST, E5, SUST, C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 41 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, REST, A4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C5, SUST, SUST, REST // 43 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, G5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db F5, SUST, SUST, REST, E5b, SUST, D5, SUST, C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db G5, SUST, SUST, REST, F5, SUST, E5b, SUST, D5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, B4b, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN11: // Pattern 11: Strings (Channel 7) + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 17 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, F5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 18 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 21 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, F5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db F5, SUST, G5, SUST, E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 23 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 24 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 25 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 27 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 29 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 30 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN12: // Pattern 12: Strings (Channel 7) + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 33 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, F5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 37 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, F5, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db F5, SUST, G5, SUST, E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 41 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 43 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERN13: // Pattern 13: Strings (Channel 8) + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 17 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 18 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 20 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 21 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 22 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 23 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 24 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 25 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, REST, A4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 26 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C5, SUST, SUST, REST // 27 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, B4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 28 + db G4s, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 29 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 30 + db B4b, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 31 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 32 +PATTERN14: // Pattern 14: Strings (Channel 8) + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 33 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 34 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 35 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 36 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 37 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 38 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 39 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 40 + db A4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 41 + db G4, SUST, SUST, SUST, SUST, SUST, SUST, REST, A4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 42 + db B4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST, C5, SUST, SUST, REST // 43 + db D5, SUST, SUST, SUST, SUST, SUST, SUST, REST, B4, SUST, SUST, SUST, SUST, SUST, SUST, REST // 44 + db G4s, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 45 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 46 + db B4b, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 47 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, REST // 48 + +PATTERNLIST: + dw PATTERN01,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..8 Pattern Address List +PATTERNLISTLOOP: + dw PATTERN01,PATTERN02,PATTERN04,PATTERN06,PATTERN08,PATTERN00,PATTERN11,PATTERN13 // Channel 1..8 Pattern Address List + dw PATTERN01,PATTERN03,PATTERN05,PATTERN07,PATTERN09,PATTERN10,PATTERN12,PATTERN14 // Channel 1..8 Pattern Address List +PATTERNLISTEND: + +seek($3000); sampleDIR: + dw SynthHarp, SynthHarp + 9 // 0 + dw Flute, Flute + 2322 // 1 + dw Oboe, Oboe + 4770 // 2 + dw Clarinet, Clarinet + 3852 // 3 + dw Bassoon, Bassoon + 3015 // 4 + dw FrenchHorn, FrenchHorn + 5301 // 5 + dw Strings, Strings + 5616 // 6 + +seek($3100) // Sample Data + insert SynthHarp, "BRR/001. Synth Harp (Loop=9,AD=$FB,SR=$F6,Echo)(C9Freq=$EC80).brr" + insert Flute, "BRR/006. Flute (Loop=2322,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr" + insert Oboe, "BRR/002. Oboe (Loop=4770,AD=$FF,SR=$E0,Echo)(C9Freq=$EC80).brr" + insert Clarinet, "BRR/007. Clarinet (Loop=3852,AD=$FF,SR=$E0,Echo)(C9Freq=$D080).brr" + insert Bassoon, "BRR/003. Bassoon (Loop=3015,AD=$FF,SR=$E0,Echo)(C9Freq=$B080).brr" + insert FrenchHorn, "BRR/004. French Horn (Loop=5301,AD=$FF,SR=$E0,Echo)(C9Freq=$FE80).brr" + insert Strings, "BRR/005. Strings (Loop=5616,AD=$F4,SR=$E6,Echo)(C9Freq=$F880).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..baf60845 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "FFVII PRELUDE SONG " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/make.bat b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/make.bat new file mode 100644 index 00000000..14a047c4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/FFVIIPrelude/make.bat @@ -0,0 +1,2 @@ +bass FFVIIPrelude_spc.asm +bass FFVIIPrelude.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest.spc b/roms/snes/peter-lemon-snes/SPC700/ItaloTest.spc new file mode 100644 index 00000000..770a8f7d Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr new file mode 100644 index 00000000..9037b1e3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..f54a6926 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..357940ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..8c5fe470 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..2f859c6b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr new file mode 100644 index 00000000..24f02b8a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr new file mode 100644 index 00000000..e4d80062 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..2a1fe869 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..175071e0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.asm b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.asm new file mode 100644 index 00000000..31b0d168 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.asm @@ -0,0 +1,27 @@ +// SNES SPC700 Italo Disco Test Song Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "ItaloTest.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "ItaloTest.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.sfc b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.sfc new file mode 100644 index 00000000..8a6f57d0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.spc b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.spc new file mode 100644 index 00000000..115ad5ea Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest_spc.asm b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest_spc.asm new file mode 100644 index 00000000..82e67ab5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/ItaloTest_spc.asm @@ -0,0 +1,380 @@ +// SNES SPC700 Italo Disco Test Song Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "ItaloTest.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(120) // Maximum Quantization ms +constant PatternSize(64) // Pattern Size (1..256) +constant ChannelCount(10) // Channel Count (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,12) // Echo Delay + WDSP(DSP_EON,%11110000) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,50) // Echo Feedback + WDSP(DSP_FIR0,12) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,33) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,43) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,43) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,19) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,-2) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,-13) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,-7) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,40) // Echo Volume Left + WDSP(DSP_EVOLR,30) // Echo Volume Right + + WDSP(DSP_V0VOLL,64) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,64) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: BassDrum + WDSP(DSP_V0ADSR1,$FF) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$E0) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,64) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,64) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,1) // Voice 1: Snare + WDSP(DSP_V1ADSR1,$FF) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$E0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,48) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,48) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,2) // Voice 2: HihatClosed + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$E0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,127) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,127) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,3) // Voice 3: TomtomFloor + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$E0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,64) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,64) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,4) // Voice 4: BassGuitar + WDSP(DSP_V4ADSR1,$FC) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$FE) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,127) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,127) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,5) // Voice 5: BassSynth + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$F8) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + + WDSP(DSP_V6VOLL,32) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,32) // Voice 6: Volume Right + WDSP(DSP_V6SRCN,6) // Voice 6: ElectroSynth + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + WDSP(DSP_V6GAIN,127) // Voice 6: Gain + + WDSP(DSP_V7VOLL,8) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,8) // Voice 7: Volume Right + WDSP(DSP_V7SRCN,5) // Voice 7: BassSynth + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + WDSP(DSP_V7GAIN,127) // Voice 7: Gain + +StartSong: // Each Bar = 1920ms, Each Beat = 480ms, 3/4 Beat = 360ms, 1/2 Beat = 240ms, 1/4 Beat 120ms + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, BassDrumPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, SnarePitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, HihatClosedPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, TomtomFloorPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, BassGuitarPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, BassSynthPitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(6, 6, ElectroSynthPitchTable) // Channel 7 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(7, 7, BassSynthPitchTable) // Channel 8 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(8, 6, SynthPitchTable) // Channel 9 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(9, 7, HandClapPitchTable) // Channel 10 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..10 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List Change Address + lda #PATTERNLISTCHANGE // A = Pattern List Change (LSB) + ldy #PATTERNLISTCHANGE>>8 // Y = Pattern List Change (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternCmpEnd // IF (Pattern Offset != Pattern List Change Offset) Pattern Compare End, ELSE Set Pattern Change Offset + + WDSP(DSP_KOFF,%11000000) // DSP Register Data = Key Off Flags + + // Set Synth (Channel 6) + WDSP(DSP_V6SRCN,7) // Voice 6: Synth + WDSP(DSP_V6VOLL,40) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,40) // Voice 6: Volume Right + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F8) // Voice 6: ADSR2 + + // Set Synth (Channel 7) + WDSP(DSP_V7SRCN,8) // Voice 7: Hand Clap + WDSP(DSP_V7VOLL,64) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,64) // Voice 7: Volume Right + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + + PatternCmpEnd: // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + WDSP(DSP_KOFF,%11000000) // DSP Register Data = Key Off Flags + + // Set Electro Synth (Channel 6) + WDSP(DSP_V6SRCN,6) // Voice 6: ElectroSynth + WDSP(DSP_V6VOLL,32) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,32) // Voice 6: Volume Right + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + + // Set Bass Synth (Channel 7) + WDSP(DSP_V7SRCN,5) // Voice 7: BassSynth + WDSP(DSP_V7VOLL,8) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,8) // Voice 7: Volume Right + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +BassDrumPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SnarePitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +HihatClosedPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +TomtomFloorPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +BassGuitarPitchTable: + WritePitchTable($A820) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +BassSynthPitchTable: + WritePitchTable($B2C8) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +ElectroSynthPitchTable: + WritePitchTable($8610) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SynthPitchTable: + WritePitchTable($FB00) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +HandClapPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + +PATTERN00: // Pattern 00: Rest (Channel 1..10) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 1 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 2 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 3 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 4 + +PATTERN01: // Pattern 01: Sustain (Channel 1..10) + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 1 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 2 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 3 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 4 + +PATTERN02: // Pattern 02: Bass Drum (Channel 1) + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 2 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 3 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 4 + +PATTERN03: // Pattern 03: Snare (Channel 2) + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 2 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 3 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 4 + +PATTERN04: // Pattern 04: Hihat Closed (Channel 3) + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 1 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 2 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 3 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 4 + +PATTERN05: // Pattern 05: Tomtom Floor (Channel 4) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 25 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 26 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 27 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, E5, SUST, SUST, SUST, SUST, SUST // 28 + +PATTERN06: // Pattern 06: Bass Guitar (Channel 5) + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 1 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 2 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 3 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 4 + +PATTERN07: // Pattern 07: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 5 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 6 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 7 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 8 +PATTERN08: // Pattern 08: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 9 + db C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST // 10 + db E3, SUST, E4, SUST, E3, SUST, E4, SUST, E3, SUST, E4, SUST, E3, SUST, E4, SUST // 11 + db G4, SUST, G5, SUST, G4, SUST, G5, SUST, G4, SUST, G5, SUST, G4, SUST, G5, SUST // 12 +PATTERN09: // Pattern 09: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 17 + db C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST // 18 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 19 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 20 +PATTERN10: // Pattern 10: Bass Synth (Channel 6) + db F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST // 25 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 26 + db F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST // 27 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 28 + +PATTERN11: // Pattern 11: Electro Synth (Channel 7) + db A4, SUST, SUST, SUST, E5, SUST, C5, SUST, SUST, SUST, A4, SUST, E5, SUST, SUST, SUST // 9 + db C5, SUST, SUST, SUST, G5, SUST, E5, SUST, SUST, SUST, C5, SUST, G5, SUST, SUST, SUST // 10 + db E5, SUST, SUST, SUST, B5, SUST, G5, SUST, SUST, SUST, E5, SUST, B5, SUST, SUST, SUST // 11 + db G5, SUST, SUST, SUST, D6, SUST, B5, SUST, SUST, SUST, G5, SUST, D6, SUST, SUST, SUST // 12 + +PATTERN12: // Pattern 12: Bass Synth (Channel 8) + db A4, SUST, SUST, SUST, SUST, SUST, SUST, C5, E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 9 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, E5, G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 10 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, G5, B5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 11 + db D6, SUST, SUST, SUST, SUST, SUST, SUST, B5, SUST, SUST, G5, SUST, SUST, SUST, SUST, SUST // 12 + +PATTERN13: // Pattern 13: Synth (Channel 9) + db G4, A4, C5, E5, C5, D5, G4, C5, SUST, SUST, D5, A4, C5, SUST, D5, SUST // 17 + db G4, A4, C5, E5, C5, D5, G4, C5, SUST, SUST, D5, A4, C5, SUST, D5, SUST // 18 + db B4, C5, D5, G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db B4, C5, D5, G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 20 +PATTERN14: // Pattern 14: Synth (Channel 9) + db F4, B4, C5, E5, C5, D5, A4, SUST, SUST, SUST, C5, SUST, D5, C5, D5, SUST // 17 + db G4, A4, C5, E5, C5, D5, A4, E5, SUST, SUST, G5, SUST, A5, SUST, SUST, SUST // 18 + db F4, B4, C5, E5, C5, D5, A4, SUST, SUST, SUST, C5, SUST, D5, C5, D5, SUST // 19 + db G4, A4, C5, E5, C5, D5, A4, E5, SUST, SUST, G5, SUST, A5, SUST, SUST, SUST // 20 + +PATTERN15: // Pattern 15: Hand Clap (Channel 10) + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 25 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 26 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 27 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 28 + +PATTERNLIST: +PATTERNLISTLOOP: + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN07,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN08,PATTERN11,PATTERN12,PATTERN01,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN08,PATTERN11,PATTERN12,PATTERN01,PATTERN01 // Channel 1..11 Pattern Address List +PATTERNLISTCHANGE: + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN09,PATTERN01,PATTERN01,PATTERN13,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN09,PATTERN01,PATTERN01,PATTERN13,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN05,PATTERN06,PATTERN10,PATTERN01,PATTERN01,PATTERN14,PATTERN15 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN05,PATTERN06,PATTERN10,PATTERN01,PATTERN01,PATTERN14,PATTERN15 // Channel 1..11 Pattern Address List +PATTERNLISTEND: + +seek($3A00); sampleDIR: + dw BassDrum, 0 // 0 + dw Snare, 0 // 1 + dw HihatClosed, 0 // 2 + dw TomtomFloor, 0 // 3 + dw BassGuitar, BassGuitar + 900 // 4 + dw BassSynth, BassSynth + 378 // 5 + dw ElectroSynth, ElectroSynth + 0 // 6 + dw Synth, Synth + 405 // 7 + dw HandClap, 0 // 8 + +seek($3B00) // Sample Data + insert BassDrum, "BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert Snare, "BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert HihatClosed, "BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert TomtomFloor, "BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert BassGuitar, "BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr" + insert BassSynth, "BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr" + insert ElectroSynth, "BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr" + insert Synth, "BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr" + insert HandClap, "BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..f34d375a --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "ITALO DISCO TEST " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/ItaloTest/make.bat b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/make.bat new file mode 100644 index 00000000..f4b44e4c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/ItaloTest/make.bat @@ -0,0 +1,2 @@ +bass ItaloTest_spc.asm +bass ItaloTest.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/BRR/032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr b/roms/snes/peter-lemon-snes/SPC700/PitchMod/BRR/032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr new file mode 100644 index 00000000..2782ade7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PitchMod/BRR/032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..e32a9771 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PITCH MODULATION " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.asm b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.asm new file mode 100644 index 00000000..bf2b6b80 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.asm @@ -0,0 +1,27 @@ +// SNES SPC700 Pitch Modulation Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "PitchMod.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "PitchMod.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.sfc b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.sfc new file mode 100644 index 00000000..20c91081 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.spc b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.spc new file mode 100644 index 00000000..9a977b14 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod_spc.asm b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod_spc.asm new file mode 100644 index 00000000..7c0ad723 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/PitchMod_spc.asm @@ -0,0 +1,69 @@ +// SNES SPC700 Pitch Modulation Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "PitchMod.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +constant CelloC9Pitch($8BB0) + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,15) // Echo Delay + WDSP(DSP_EON,%00000010) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,100) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0SRCN,0) // Voice 0: Sine Wave + WDSP(DSP_V1SRCN,1) // Voice 1: Strings + WDSP(DSP_PMON,%00000010) // Pitch Modulation + +SongStart: + WDSP(DSP_V0VOLL,0) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,0) // Voice 0: Volume Right + WDSP(DSP_V0GAIN,2) // Voice 0: Gain + + WDSP(DSP_V1VOLL,127) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,127) // Voice 1: Volume Right + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V0PITCHL,$03) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$00) // Voice 0: Pitch (Upper Byte) + + SetPitch(1,C,5,CelloC9Pitch) + WDSP(DSP_KON,%00000010) // Play Voices + SPCWaitSHIFTMS(250, 2) // Wait 250*4 ms + + WDSP(DSP_KON,%00000001) // Play Voices + +seek($0400); sampleDIR: + dw sineWave, sineWave // DIR 0: Sine Wave + dw Cello, Cello+4167 // DIR 1: Strings Wave + +seek($0500) // Sample Data + sineWave: + db $C3, $77, $99, $77, $99, $77, $99, $77, $99 + insert Cello, "BRR/032. Cello (Loop=4167,AD=$FF,SR=$E8,Echo)(C9Pitch=$8BB0).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PitchMod/make.bat b/roms/snes/peter-lemon-snes/SPC700/PitchMod/make.bat new file mode 100644 index 00000000..1f8ba80a --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PitchMod/make.bat @@ -0,0 +1,2 @@ +bass PitchMod_spc.asm +bass PitchMod.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..b92e7644 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PLAY BRR SAMPLE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.asm b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.asm new file mode 100644 index 00000000..74ca914e --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.asm @@ -0,0 +1,27 @@ +// SNES SPC700 Play BRR Sample Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "PlayBRRSample.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "PlayBRRSample.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.sfc b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.sfc new file mode 100644 index 00000000..cc047e1e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.spc b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.spc new file mode 100644 index 00000000..abc4c79e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample_spc.asm b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample_spc.asm new file mode 100644 index 00000000..c075b7df --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/PlayBRRSample_spc.asm @@ -0,0 +1,56 @@ +// SNES SPC700 Play BRR Sample Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "PlayBRRSample.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000001) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + +SongStart: + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0SRCN,0) // Voice 0: Sample + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + WDSP(DSP_KON,%00000001) // Play Voice 0 + +Loop: + jmp Loop + +seek($0300); sampleDIR: + dw BRRSample, BRRSample + ((2032 / 16) * 9) // BRR Sample Offset, Loop Point + +seek($0400) // Sample Data + insert BRRSample, "test.brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/make.bat b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/make.bat new file mode 100644 index 00000000..8fc1365d --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/make.bat @@ -0,0 +1,2 @@ +bass PlayBRRSample_spc.asm +bass PlayBRRSample.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/test.brr b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/test.brr new file mode 100644 index 00000000..be69c3ed Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayBRRSample/test.brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..218bb686 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PLAY NOISE " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.asm b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.asm new file mode 100644 index 00000000..e38c9fc2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.asm @@ -0,0 +1,27 @@ +// SNES SPC700 Play Noise Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "PlayNoise.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "PlayNoise.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.sfc b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.sfc new file mode 100644 index 00000000..82804d37 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.spc b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.spc new file mode 100644 index 00000000..54ddbcd7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise_spc.asm b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise_spc.asm new file mode 100644 index 00000000..be3d02d1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/PlayNoise_spc.asm @@ -0,0 +1,71 @@ +// SNES SPC700 Play Noise Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "PlayNoise.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,5) // Echo Delay + WDSP(DSP_EON,%00000001) // Echo On Flags + WDSP(DSP_NON,%00000001) // Noise On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,80) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + +SongStart: + WDSP(DSP_V0VOLL,127) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0: Volume Right + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + +Loop: +// Kick + WDSP(DSP_FLG,14) // Enable Echo Buffer Writes, Noise Frequency = 14Hz + WDSP(DSP_V0ADSR1,%10001110) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11110110) // Voice 0: ADSR2 + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitSHIFTMS(240,1) // Wait 240*2 ms + +// Hi-Hat Closed + WDSP(DSP_FLG,30) // Enable Echo Buffer Writes, Noise Frequency = 16kHz + WDSP(DSP_V0ADSR1,%10101111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(240) // Wait 240 ms + +// Hi-Hat Open + WDSP(DSP_FLG,30) // Enable Echo Buffer Writes, Noise Frequency = 16kHz + WDSP(DSP_V0ADSR1,%10001100) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%10011100) // Voice 0: ADSR2 + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(240) // Wait 240 ms + +// Snare + WDSP(DSP_FLG,29) // Enable Echo Buffer Writes, Noise Frequency = 8kHz + WDSP(DSP_V0ADSR1,%11111010) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111000) // Voice 0: ADSR2 + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitSHIFTMS(240,2) // Wait 240*4 ms + + jmp Loop \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayNoise/make.bat b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/make.bat new file mode 100644 index 00000000..2cf2a768 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayNoise/make.bat @@ -0,0 +1,2 @@ +bass PlayNoise_spc.asm +bass PlayNoise.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr new file mode 100644 index 00000000..9037b1e3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr new file mode 100644 index 00000000..2a42437f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..f54a6926 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..357940ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..8c5fe470 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..2f859c6b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr new file mode 100644 index 00000000..24f02b8a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr new file mode 100644 index 00000000..e4d80062 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr new file mode 100644 index 00000000..2a1fe869 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr new file mode 100644 index 00000000..175071e0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..ad8536fb --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "PLAY TWO SONG " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $02 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_INPUT.INC b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_INPUT.INC new file mode 100644 index 00000000..666fee70 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_INPUT.INC @@ -0,0 +1,120 @@ +//============ +// SNES Input +//============ +define JOY_R(REG_JOY1L, %00010000) +define JOY_L(REG_JOY1L, %00100000) +define JOY_X(REG_JOY1L, %01000000) +define JOY_A(REG_JOY1L, %10000000) +define JOY_RIGHT(REG_JOY1H, %00000001) +define JOY_LEFT(REG_JOY1H, %00000010) +define JOY_DOWN(REG_JOY1H, %00000100) +define JOY_UP(REG_JOY1H, %00001000) +define JOY_START(REG_JOY1H, %00010000) +define JOY_SELECT(REG_JOY1H, %00100000) +define JOY_Y(REG_JOY1H, %01000000) +define JOY_B(REG_JOY1H, %10000000) + +//================================ +// ReadJOY - Read Joypad Register +//================================ +// JOYREG: Joypad Register +// JOYINP: Joypad Button Code (BYSSUDLR = REG_JOY1H, AXLR---- = REG_JOY1L) +macro ReadJOY(JOYREG, INPUT) { + - + bit.w REG_HVBJOY // $4212: Read H/V-Blank Flag & Joypad Busy Flag + bmi - // Wait Until Joypad Is Ready + + lda.w {JOYREG} // Read Joypad Register Byte + and.b #{INPUT} // Test Button Bit +} + +//===================================================== +// ReadXBAND - Read X-Band Keyboard Scancodes Register +//===================================================== +// Uses 16 Bytes Of WRAM ($00..$0F) +// Byte $00 = ID/NUM, Bytes $01..$0F = Keyboard Scancodes +macro ReadXBAND() { + lda.b #$7F // Set IOBIT = 0 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // ID = GETBITS(8) // Read ID Byte, Must Be $78 ("x") + ldy.w #4 // GETBITS(N) + {#}ReadIDBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadIDBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $00 // MEM[$00] = ID + + lda.b #$FF // IF CAPS=OFF [$4201]=$FF // Set IOBIT=1 (When CAPS=OFF) (CAPS LED) + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) + + // NUM = GETBITS(4) // Read NUMber Of Scancodes + ldy.w #2 // GETBITS(N) + {#}ReadNUMBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $00 // MEM[$00] >> 1 + lsr.b $00 // MEM[$00] >> 1 + ora.b $00 // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $00 // Store X + dey // Decrement N/2 + bne {#}ReadNUMBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + lsr + lsr + lsr + lsr + sta.b $00 // MEM[$00] = NUM + + beq {#}SkipScanCodes // IF NUM>0 THEN FOR I=1 TO NUM + + ldx.w #14 // Clear Keyboard Buffer (15 Bytes) + {#}ClearKBUF: + stz.b $01,x + dex + bne {#}ClearKBUF + + ldx.w #0 // X = DST Offset + {#}NextScanCode: // DST = GETBITS(8) // Read Scancodes + ldy.w #4 // GETBITS(N) + {#}ReadDSTBits: // FOR I=1 TO N/2 // Read 2 Bits At Once (LSB First) + lda.w REG_JOYB // X = (X SHR 2) OR ([$4017] SHL 6) + asl + asl + asl + asl + asl + asl // A = [$4017] SHL 6 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + lsr.b $01,x // MEM[$01+DST Offset] >> 1 + ora.b $01,x // A = (X SHR 2) OR ([$4017] SHL 6) + sta.b $01,x // Store X + dey // Decrement N/2 + bne {#}ReadDSTBits // NEXT + eor.b #$FF // X = (X XOR $FF) SHR (8-N) // Invert & Move Result To LSBs + sta.b $01,x // MEM[$01+DST Offset] = DST + + inx // DST Offset++ + dec.b $00 // NUM-- + bne {#}NextScanCode + + {#}SkipScanCodes: + lda.b #$FF // Set IOBIT=1 + sta.w REG_WRIO // $4201: Programmable I/O Port (Open-Collector Output) +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.asm b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.asm new file mode 100644 index 00000000..05452ee3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.asm @@ -0,0 +1,53 @@ +// SNES SPC700 Play Two Song Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "PlayTwoSong.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $10000 // Fill Upto $FFFF (Bank 1) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_INPUT.INC" // Include Input Macros +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + lda.b #$01 + sta.w REG_NMITIMEN // Enable Joypad NMI Reading Interrupt + +InputLoop: + PressA: + ReadJOY({JOY_A}) // Test A Button + beq PressB // "A" Not Pressed? Branch Down + + lda.b $01 // Uses "1" For Reset Check + sta.w REG_APUIO0 // Run A Handshake Between CPU<->APU + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM1, SPCRAM, SPCROM1.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + + PressB: + ReadJOY({JOY_B}) // Test B Button + beq Finish // "B" Not Pressed? Branch Down + + lda.b $01 // Uses "1" For Reset Check + sta.w REG_APUIO0 // Run A Handshake Between CPU<->APU + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM2, SPCRAM, SPCROM2.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Finish: + jmp InputLoop + +// SPC Code +// BANK 0 +insert SPCROM1, "PlayTwoSong1.spc" +// BANK 1 +seek($18000) +insert SPCROM2, "PlayTwoSong2.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.sfc b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.sfc new file mode 100644 index 00000000..f3af1a25 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1.spc b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1.spc new file mode 100644 index 00000000..19435aa0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1_spc.asm b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1_spc.asm new file mode 100644 index 00000000..d05d0d6a --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong1_spc.asm @@ -0,0 +1,267 @@ +// SNES SPC700 Play Two Song Demo, Song 1 (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "PlayTwoSong1.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + jsr ResetCheck // Check For Reset + + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(256) // Maximum Quantization ms +constant PatternSize(8) // Pattern Size (1..256) +constant ChannelCount(7) // Channel Count (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,15) // Echo Delay + WDSP(DSP_EON,%11111111) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,100) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,25) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,25) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: Harp + WDSP(DSP_V0ADSR1,$FF) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,25) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,25) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,0) // Voice 1: Harp + WDSP(DSP_V1ADSR1,$FF) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,25) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,25) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,0) // Voice 2: Harp + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$F0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,25) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,25) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,0) // Voice 3: Harp + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$F0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,25) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,25) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,0) // Voice 4: Harp + WDSP(DSP_V4ADSR1,$FF) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$F0) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,25) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,25) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,0) // Voice 5: Harp + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$F0) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + + WDSP(DSP_V6VOLL,25) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,25) // Voice 6: Volume Right + WDSP(DSP_V6SRCN,0) // Voice 6: Harp + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + WDSP(DSP_V6GAIN,127) // Voice 6: Gain + +StartSong: + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, HarpPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, HarpPitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, HarpPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, HarpPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, HarpPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, HarpPitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(6, 6, HarpPitchTable) // Channel 7 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..8 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +HarpPitchTable: + WritePitchTable($C900) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + +PATTERN00: // Pattern 00: Harp (Channel 1) + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN01: // Pattern 01: Harp (Channel 1) + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN02: // Pattern 02: Harp (Channel 1) + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN03: // Pattern 03: Harp (Channel 2) + db SUST, C5, SUST, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN04: // Pattern 04: Harp (Channel 2) + db SUST, F5, SUST, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN05: // Pattern 05: Harp (Channel 2) + db SUST, G5, SUST, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN06: // Pattern 06: Harp (Channel 3) + db SUST, SUST, G5, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN07: // Pattern 07: Harp (Channel 3) + db SUST, SUST, E5, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN08: // Pattern 08: Harp (Channel 3) + db SUST, SUST, F5, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN09: // Pattern 09: Harp (Channel 4) + db SUST, SUST, SUST, G5, SUST, SUST, SUST, SUST // 1 +PATTERN10: // Pattern 10: Harp (Channel 4) + db SUST, SUST, SUST, E5, SUST, SUST, SUST, SUST // 2 +PATTERN11: // Pattern 11: Harp (Channel 4) + db SUST, SUST, SUST, F5, SUST, SUST, SUST, SUST // 3 + +PATTERN12: // Pattern 12: Harp (Channel 5) + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 +PATTERN13: // Pattern 13: Harp (Channel 5) + db SUST, SUST, SUST, SUST, D5, SUST, SUST, SUST // 2 +PATTERN14: // Pattern 14: Harp (Channel 5) + db SUST, SUST, SUST, SUST, E5, SUST, SUST, SUST // 3 + +PATTERN15: // Pattern 15: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST // 1 +PATTERN16: // Pattern 16: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, D5, SUST, SUST // 2 +PATTERN17: // Pattern 17: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, E5, SUST, SUST // 3 + +PATTERN18: // Pattern 18: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, G5, SUST // 1 +PATTERN19: // Pattern 19: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, C5, SUST // 2 +PATTERN20: // Pattern 20: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, D5, SUST // 3 + +PATTERNLIST: +PATTERNLISTLOOP: + dw PATTERN00,PATTERN03,PATTERN06,PATTERN09,PATTERN12,PATTERN15,PATTERN18 // Channel 1..7 Pattern Address List + dw PATTERN01,PATTERN04,PATTERN07,PATTERN10,PATTERN13,PATTERN16,PATTERN19 // Channel 1..7 Pattern Address List + dw PATTERN02,PATTERN05,PATTERN08,PATTERN11,PATTERN14,PATTERN17,PATTERN20 // Channel 1..7 Pattern Address List + dw PATTERN02,PATTERN05,PATTERN08,PATTERN11,PATTERN14,PATTERN17,PATTERN20 // Channel 1..7 Pattern Address List + dw PATTERN00,PATTERN03,PATTERN06,PATTERN09,PATTERN12,PATTERN15,PATTERN18 // Channel 1..7 Pattern Address List + dw PATTERN01,PATTERN04,PATTERN07,PATTERN10,PATTERN13,PATTERN16,PATTERN19 // Channel 1..7 Pattern Address List +PATTERNLISTEND: + +ResetCheck: + lda #$00 + cmp.b REG_CPUIO0 // Wait For Echo + bne PlaySong // IF (!= 0) PlaySong, ELSE Run Boot ROM + + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + SPCBoot() // Reboot SPC +PlaySong: + rts + +seek($0A00); sampleDIR: + dw Harp, Harp + 927 // 0 + +seek($0B00) // Sample Data + insert Harp, "BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2.spc b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2.spc new file mode 100644 index 00000000..6db6fbe1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2_spc.asm b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2_spc.asm new file mode 100644 index 00000000..19355096 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/PlayTwoSong2_spc.asm @@ -0,0 +1,393 @@ +// SNES SPC700 Play Two Song Demo, Song 2 (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "PlayTwoSong2.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + jsr ResetCheck // Check For Reset + + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(120) // Maximum Quantization ms +constant PatternSize(64) // Pattern Size (1..256) +constant ChannelCount(10) // Channel Count (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,12) // Echo Delay + WDSP(DSP_EON,%11110000) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,50) // Echo Feedback + WDSP(DSP_FIR0,12) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,33) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,43) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,43) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,19) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,-2) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,-13) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,-7) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,40) // Echo Volume Left + WDSP(DSP_EVOLR,30) // Echo Volume Right + + WDSP(DSP_V0VOLL,64) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,64) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: BassDrum + WDSP(DSP_V0ADSR1,$FF) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$E0) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,64) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,64) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,1) // Voice 1: Snare + WDSP(DSP_V1ADSR1,$FF) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$E0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,48) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,48) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,2) // Voice 2: HihatClosed + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$E0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,127) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,127) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,3) // Voice 3: TomtomFloor + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$E0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,64) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,64) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,4) // Voice 4: BassGuitar + WDSP(DSP_V4ADSR1,$FC) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$FE) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,127) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,127) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,5) // Voice 5: BassSynth + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$F8) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + + WDSP(DSP_V6VOLL,32) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,32) // Voice 6: Volume Right + WDSP(DSP_V6SRCN,6) // Voice 6: ElectroSynth + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + WDSP(DSP_V6GAIN,127) // Voice 6: Gain + + WDSP(DSP_V7VOLL,8) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,8) // Voice 7: Volume Right + WDSP(DSP_V7SRCN,5) // Voice 7: BassSynth + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + WDSP(DSP_V7GAIN,127) // Voice 7: Gain + +StartSong: // Each Bar = 1920ms, Each Beat = 480ms, 3/4 Beat = 360ms, 1/2 Beat = 240ms, 1/4 Beat 120ms + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, BassDrumPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, SnarePitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, HihatClosedPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, TomtomFloorPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, BassGuitarPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, BassSynthPitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(6, 6, ElectroSynthPitchTable) // Channel 7 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(7, 7, BassSynthPitchTable) // Channel 8 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(8, 6, SynthPitchTable) // Channel 9 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(9, 7, HandClapPitchTable) // Channel 10 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..10 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List Change Address + lda #PATTERNLISTCHANGE // A = Pattern List Change (LSB) + ldy #PATTERNLISTCHANGE>>8 // Y = Pattern List Change (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternCmpEnd // IF (Pattern Offset != Pattern List Change Offset) Pattern Compare End, ELSE Set Pattern Change Offset + + WDSP(DSP_KOFF,%11000000) // DSP Register Data = Key Off Flags + + // Set Synth (Channel 6) + WDSP(DSP_V6SRCN,7) // Voice 6: Synth + WDSP(DSP_V6VOLL,40) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,40) // Voice 6: Volume Right + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F8) // Voice 6: ADSR2 + + // Set Synth (Channel 7) + WDSP(DSP_V7SRCN,8) // Voice 7: Hand Clap + WDSP(DSP_V7VOLL,64) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,64) // Voice 7: Volume Right + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + + PatternCmpEnd: // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + WDSP(DSP_KOFF,%11000000) // DSP Register Data = Key Off Flags + + // Set Electro Synth (Channel 6) + WDSP(DSP_V6SRCN,6) // Voice 6: ElectroSynth + WDSP(DSP_V6VOLL,32) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,32) // Voice 6: Volume Right + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + + // Set Bass Synth (Channel 7) + WDSP(DSP_V7SRCN,5) // Voice 7: BassSynth + WDSP(DSP_V7VOLL,8) // Voice 7: Volume Left + WDSP(DSP_V7VOLR,8) // Voice 7: Volume Right + WDSP(DSP_V7ADSR1,$FF) // Voice 7: ADSR1 + WDSP(DSP_V7ADSR2,$E0) // Voice 7: ADSR2 + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +BassDrumPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SnarePitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +HihatClosedPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +TomtomFloorPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +BassGuitarPitchTable: + WritePitchTable($A820) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +BassSynthPitchTable: + WritePitchTable($B2C8) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +ElectroSynthPitchTable: + WritePitchTable($8610) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +SynthPitchTable: + WritePitchTable($FB00) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) +HandClapPitchTable: + WritePitchTable($8000) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + +PATTERN00: // Pattern 00: Rest (Channel 1..10) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 1 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 2 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 3 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 4 + +PATTERN01: // Pattern 01: Sustain (Channel 1..10) + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 1 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 2 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 3 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 4 + +PATTERN02: // Pattern 02: Bass Drum (Channel 1) + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 2 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 3 + db A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST, A5, SUST, SUST, SUST // 4 + +PATTERN03: // Pattern 03: Snare (Channel 2) + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 2 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 3 + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 4 + +PATTERN04: // Pattern 04: Hihat Closed (Channel 3) + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 1 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 2 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 3 + db A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST, A6, SUST // 4 + +PATTERN05: // Pattern 05: Tomtom Floor (Channel 4) + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 25 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 26 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, REST // 27 + db REST, REST, REST, REST, REST, REST, REST, REST, REST, REST, E5, SUST, SUST, SUST, SUST, SUST // 28 + +PATTERN06: // Pattern 06: Bass Guitar (Channel 5) + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 1 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 2 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 3 + db A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5, A5 // 4 + +PATTERN07: // Pattern 07: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 5 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 6 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 7 + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 8 +PATTERN08: // Pattern 08: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 9 + db C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST // 10 + db E3, SUST, E4, SUST, E3, SUST, E4, SUST, E3, SUST, E4, SUST, E3, SUST, E4, SUST // 11 + db G4, SUST, G5, SUST, G4, SUST, G5, SUST, G4, SUST, G5, SUST, G4, SUST, G5, SUST // 12 +PATTERN09: // Pattern 09: Bass Synth (Channel 6) + db A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST, A3, SUST, A4, SUST // 17 + db C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST, C4, SUST, C5, SUST // 18 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 19 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 20 +PATTERN10: // Pattern 10: Bass Synth (Channel 6) + db F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST // 25 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 26 + db F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST, F3, SUST, F4, SUST // 27 + db G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST, G3, SUST, G4, SUST // 28 + +PATTERN11: // Pattern 11: Electro Synth (Channel 7) + db A4, SUST, SUST, SUST, E5, SUST, C5, SUST, SUST, SUST, A4, SUST, E5, SUST, SUST, SUST // 9 + db C5, SUST, SUST, SUST, G5, SUST, E5, SUST, SUST, SUST, C5, SUST, G5, SUST, SUST, SUST // 10 + db E5, SUST, SUST, SUST, B5, SUST, G5, SUST, SUST, SUST, E5, SUST, B5, SUST, SUST, SUST // 11 + db G5, SUST, SUST, SUST, D6, SUST, B5, SUST, SUST, SUST, G5, SUST, D6, SUST, SUST, SUST // 12 + +PATTERN12: // Pattern 12: Bass Synth (Channel 8) + db A4, SUST, SUST, SUST, SUST, SUST, SUST, C5, E5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 9 + db C5, SUST, SUST, SUST, SUST, SUST, SUST, E5, G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 10 + db E5, SUST, SUST, SUST, SUST, SUST, SUST, G5, B5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 11 + db D6, SUST, SUST, SUST, SUST, SUST, SUST, B5, SUST, SUST, G5, SUST, SUST, SUST, SUST, SUST // 12 + +PATTERN13: // Pattern 13: Synth (Channel 9) + db G4, A4, C5, E5, C5, D5, G4, C5, SUST, SUST, D5, A4, C5, SUST, D5, SUST // 17 + db G4, A4, C5, E5, C5, D5, G4, C5, SUST, SUST, D5, A4, C5, SUST, D5, SUST // 18 + db B4, C5, D5, G4, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 19 + db B4, C5, D5, G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 20 +PATTERN14: // Pattern 14: Synth (Channel 9) + db F4, B4, C5, E5, C5, D5, A4, SUST, SUST, SUST, C5, SUST, D5, C5, D5, SUST // 17 + db G4, A4, C5, E5, C5, D5, A4, E5, SUST, SUST, G5, SUST, A5, SUST, SUST, SUST // 18 + db F4, B4, C5, E5, C5, D5, A4, SUST, SUST, SUST, C5, SUST, D5, C5, D5, SUST // 19 + db G4, A4, C5, E5, C5, D5, A4, E5, SUST, SUST, G5, SUST, A5, SUST, SUST, SUST // 20 + +PATTERN15: // Pattern 15: Hand Clap (Channel 10) + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 25 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 26 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 27 + db SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, SUST, C6, SUST, C6, C6, SUST, SUST // 28 + +PATTERNLIST: +PATTERNLISTLOOP: + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN00,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN07,PATTERN00,PATTERN00,PATTERN00,PATTERN00 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN08,PATTERN11,PATTERN12,PATTERN01,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN08,PATTERN11,PATTERN12,PATTERN01,PATTERN01 // Channel 1..11 Pattern Address List +PATTERNLISTCHANGE: + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN09,PATTERN01,PATTERN01,PATTERN13,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN00,PATTERN06,PATTERN09,PATTERN01,PATTERN01,PATTERN13,PATTERN01 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN05,PATTERN06,PATTERN10,PATTERN01,PATTERN01,PATTERN14,PATTERN15 // Channel 1..11 Pattern Address List + dw PATTERN02,PATTERN03,PATTERN04,PATTERN05,PATTERN06,PATTERN10,PATTERN01,PATTERN01,PATTERN14,PATTERN15 // Channel 1..11 Pattern Address List +PATTERNLISTEND: + +ResetCheck: + lda #$00 + cmp.b REG_CPUIO0 // Wait For Echo + bne PlaySong // IF (!= 0) PlaySong, ELSE Run Boot ROM + + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + SPCBoot() // Reboot SPC +PlaySong: + rts + +seek($3A00); sampleDIR: + dw BassDrum, 0 // 0 + dw Snare, 0 // 1 + dw HihatClosed, 0 // 2 + dw TomtomFloor, 0 // 3 + dw BassGuitar, BassGuitar + 900 // 4 + dw BassSynth, BassSynth + 378 // 5 + dw ElectroSynth, ElectroSynth + 0 // 6 + dw Synth, Synth + 405 // 7 + dw HandClap, 0 // 8 + +seek($3B00) // Sample Data + insert BassDrum, "BRR/101. Axelay. 000. Bass Drum (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert Snare, "BRR/101. Axelay. 001. Snare (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert HihatClosed, "BRR/101. Axelay. 002. Hi-hat Closed (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert TomtomFloor, "BRR/101. Axelay. 003. Tom-tom Floor (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" + insert BassGuitar, "BRR/101. Axelay. 020. Bass Guitar (Loop=900,AD=$F0,SR=$E2)(C9Freq=$A820).brr" + insert BassSynth, "BRR/102. Set Up. 014. Bass Synth (Loop=378,AD=$FF,SR=$E0)(C9Freq=$B2C8).brr" + insert ElectroSynth, "BRR/203. Techno de Chocobo. 002. Electro Synth (Loop=0,AD=$FF,SR=$E0,Echo)(C9Freq=$8610).brr" + insert Synth, "BRR/01. Halken Logo. 020. Synth (Loop=405,AD=$FF,SR=$EF)(C9Freq=$FB00).brr" + insert HandClap, "BRR/104. Always Together. 034. Hand Clap (AD=$FF,SR=$E0)(C9Pitch=$8000).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/make.bat b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/make.bat new file mode 100644 index 00000000..772d68d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/PlayTwoSong/make.bat @@ -0,0 +1,3 @@ +bass PlayTwoSong1_spc.asm +bass PlayTwoSong2_spc.asm +bass PlayTwoSong.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth.spc b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth.spc new file mode 100644 index 00000000..c26954c7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/01. b (Loop=468,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/01. b (Loop=468,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..106e2369 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/01. b (Loop=468,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/02. d (Loop=468,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/02. d (Loop=468,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..d3eedcdd Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/02. d (Loop=468,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/03. f (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/03. f (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..7b9ef30b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/03. f (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/04. g (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/04. g (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..b45f6d65 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/04. g (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/05. h (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/05. h (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..e73670cb Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/05. h (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/07. k (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/07. k (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..b6db09cb Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/07. k (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/08. l (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/08. l (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..ff7d2c4f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/08. l (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/09. m (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/09. m (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..9dbe28bb Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/09. m (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/10. n (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/10. n (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..bf52e386 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/10. n (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/11. p (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/11. p (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..cc66e129 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/11. p (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/12. r (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/12. r (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..6736b6cd Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/12. r (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/13. s (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/13. s (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..767af42a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/13. s (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/14. t (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/14. t (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..0b58be62 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/14. t (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/15. v (Loop=468,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/15. v (Loop=468,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..d53a0619 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/15. v (Loop=468,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/16. w (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/16. w (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..f65f7e1f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/16. w (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/17. z (Loop=468,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/17. z (Loop=468,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..f2bc3e0b Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/17. z (Loop=468,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/18. si (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/18. si (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..51bc9092 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/18. si (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/20. sh (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/20. sh (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..61dd5896 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/20. sh (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/21. th (AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/21. th (AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..90a66be0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/21. th (AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/22. thv (Loop=468,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/22. thv (Loop=468,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..fcd1f072 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/22. thv (Loop=468,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/23. ng (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/23. ng (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..761cafab Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/23. ng (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/24. j (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/24. j (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..60af6135 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/24. j (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/27. e (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/27. e (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..51df1f03 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/27. e (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/28. i (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/28. i (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..214b04cb Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/28. i (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/29. ie (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/29. ie (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..0470259e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/29. ie (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/31. au (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/31. au (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..45d45def Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/31. au (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/33. o (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/33. o (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..d0ee6ba0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/33. o (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/34. ou (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/34. ou (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..296b9fda Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/34. ou (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/35. u (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/35. u (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..2a0e4094 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/35. u (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/38. er (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/38. er (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..5c1a8862 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/38. er (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/40. a (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/40. a (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..6e310112 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/40. a (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/42. aw (Loop=9,AD=$FF,SR=$E0).brr b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/42. aw (Loop=9,AD=$FF,SR=$E0).brr new file mode 100644 index 00000000..d0f0cebb Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/BRR/42. aw (Loop=9,AD=$FF,SR=$E0).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..6e58903d --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "SPEECH SYNTHESIS " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $03 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.asm b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.asm new file mode 100644 index 00000000..5400cbc3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.asm @@ -0,0 +1,29 @@ +// SNES SPC700 Speech Synthesis Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "SpeechSynth.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $18000 // Fill Upto $17FFF (Bank 2) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, $8000) // Load SPC File To SMP/DSP + TransferBlockSPC($28000, SPCRAM+$8000, SPCROM.size-$8000) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 1 & 2 +seek($18000) +insert SPCROM, "SpeechSynth.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.sfc b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.sfc new file mode 100644 index 00000000..aa11fe3a Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.spc b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.spc new file mode 100644 index 00000000..f9bcdd2c Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth_spc.asm b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth_spc.asm new file mode 100644 index 00000000..7ba6f010 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/SpeechSynth_spc.asm @@ -0,0 +1,221 @@ +// SNES SPC700 Speech Synthesis Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "SpeechSynth.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Consonants Sample Index +constant BB(0) +constant DD(1) +constant FF(2) +constant GG(3) +constant HH(4) +constant CK(5) +constant LL(6) +constant MM(7) +constant NN(8) +constant PP(9) +constant RR(10) +constant SS(11) +constant TT(12) +constant VV(13) +constant WW(14) +constant ZZ(15) +constant SI(16) +constant SH(17) +constant TH(18) +constant THV(19) +constant NG(20) +constant JY(21) + +// Vowels Sample Index +constant EA(22) +constant EE(23) +constant IE(24) +constant AU(25) +constant OO(26) +constant OU(27) +constant UE(28) +constant ER(29) +constant AA(30) +constant AW(31) + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,127) // Master Volume Left + WDSP(DSP_MVOLR,127) // Master Volume Right + + WDSP(DSP_ESA,$00) // Echo Source Address + WDSP(DSP_EDL,0) // Echo Delay + WDSP(DSP_EON,%00000000) // Echo On Flags + WDSP(DSP_FLG,%00100000) // Disable Echo Buffer Writes + WDSP(DSP_EFB,0) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,0) // Echo Volume Left + WDSP(DSP_EVOLR,0) // Echo Volume Right + + WDSP(DSP_V0VOLL,127) // Voice 0; Volume Left + WDSP(DSP_V0VOLR,127) // Voice 0; Volume Right + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + +SongStart: + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11111111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,PP) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(32) // Wait 256 ms + + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,EE) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(256) // Wait 256 ms + + WDSP(DSP_V0ADSR1,%11111111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11100000) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,TT) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(32) // Wait 256 ms + + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,AA) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(256) // Wait 256 ms + + + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$15) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,LL) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(32) // Wait 256 ms + + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,EA) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(256) // Wait 256 ms + + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$15) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,MM) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(32) // Wait 256 ms + + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$10) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,AA) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(32) // Wait 256 ms + + WDSP(DSP_V0PITCHL,$00) // Voice 0: Pitch (Lower Byte) + WDSP(DSP_V0PITCHH,$15) // Voice 0: Pitch (Upper Byte) + WDSP(DSP_V0ADSR1,%11110111) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,%11111100) // Voice 0: ADSR2 + WDSP(DSP_V0SRCN,NN) // Voice 0: Sample + WDSP(DSP_KON,%00000001) // Play Voice 0 + SPCWaitMS(256) // Wait 256 ms + + SPCWaitMS(256) // Wait 256 ms +Loop: + jmp SongStart + +seek($8000); sampleDIR: + // Consonants + dw ConBB, ConBB + 468 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConDD, ConDD + 468 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConFF, 0 // BRR Sample Offset, No Loop Point + dw ConGG, 0 // BRR Sample Offset, No Loop Point + dw ConHH, 0 // BRR Sample Offset, No Loop Point + dw ConCK, 0 // BRR Sample Offset, No Loop Point + dw ConLL, ConLL + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConMM, ConMM + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConNN, ConNN + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConPP, 0 // BRR Sample Offset, No Loop Point + dw ConRR, ConRR + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConSS, 0 // BRR Sample Offset, No Loop Point + dw ConTT, 0 // BRR Sample Offset, No Loop Point + dw ConVV, ConVV + 468 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConWW, ConWW + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConZZ, ConZZ + 468 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConSI, 0 // BRR Sample Offset, No Loop Point + dw ConSH, 0 // BRR Sample Offset, No Loop Point + dw ConTH, 0 // BRR Sample Offset, No Loop Point + dw ConTHV, ConTHV + 468 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConNG, ConNG + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw ConJY, ConJY + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + + // Vowels + dw VowEA, VowEA + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowEE, VowEE + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowIE, VowIE + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowAU, VowAU + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowOO, VowOO + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowOU, VowOU + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowUE, VowUE + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowER, VowER + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowAA, VowAA + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + dw VowAW, VowAW + 9 // BRR Sample Offset, Loop Point (BRR Loop Sample Offset) + +seek($8100) // Sample Data + // Consonants + insert ConBB, "BRR/01. b (Loop=468,AD=$FF,SR=$E0).brr" + insert ConDD, "BRR/02. d (Loop=468,AD=$FF,SR=$E0).brr" + insert ConFF, "BRR/03. f (AD=$FF,SR=$E0).brr" + insert ConGG, "BRR/04. g (AD=$FF,SR=$E0).brr" + insert ConHH, "BRR/05. h (AD=$FF,SR=$E0).brr" + insert ConCK, "BRR/07. k (AD=$FF,SR=$E0).brr" + insert ConLL, "BRR/08. l (Loop=9,AD=$FF,SR=$E0).brr" + insert ConMM, "BRR/09. m (Loop=9,AD=$FF,SR=$E0).brr" + insert ConNN, "BRR/10. n (Loop=9,AD=$FF,SR=$E0).brr" + insert ConPP, "BRR/11. p (AD=$FF,SR=$E0).brr" + insert ConRR, "BRR/12. r (Loop=9,AD=$FF,SR=$E0).brr" + insert ConSS, "BRR/13. s (AD=$FF,SR=$E0).brr" + insert ConTT, "BRR/14. t (AD=$FF,SR=$E0).brr" + insert ConVV, "BRR/15. v (Loop=468,AD=$FF,SR=$E0).brr" + insert ConWW, "BRR/16. w (Loop=9,AD=$FF,SR=$E0).brr" + insert ConZZ, "BRR/17. z (Loop=468,AD=$FF,SR=$E0).brr" + insert ConSI, "BRR/18. si (AD=$FF,SR=$E0).brr" + insert ConSH, "BRR/20. sh (AD=$FF,SR=$E0).brr" + insert ConTH, "BRR/21. th (AD=$FF,SR=$E0).brr" + insert ConTHV, "BRR/22. thv (Loop=468,AD=$FF,SR=$E0).brr" + insert ConNG, "BRR/23. ng (Loop=9,AD=$FF,SR=$E0).brr" + insert ConJY, "BRR/24. j (Loop=9,AD=$FF,SR=$E0).brr" + + // Vowels + insert VowEA, "BRR/27. e (Loop=9,AD=$FF,SR=$E0).brr" + insert VowEE, "BRR/28. i (Loop=9,AD=$FF,SR=$E0).brr" + insert VowIE, "BRR/29. ie (Loop=9,AD=$FF,SR=$E0).brr" + insert VowAU, "BRR/31. au (Loop=9,AD=$FF,SR=$E0).brr" + insert VowOO, "BRR/33. o (Loop=9,AD=$FF,SR=$E0).brr" + insert VowOU, "BRR/34. ou (Loop=9,AD=$FF,SR=$E0).brr" + insert VowUE, "BRR/35. u (Loop=9,AD=$FF,SR=$E0).brr" + insert VowER, "BRR/38. er (Loop=9,AD=$FF,SR=$E0).brr" + insert VowAA, "BRR/40. a (Loop=9,AD=$FF,SR=$E0).brr" + insert VowAW, "BRR/42. aw (Loop=9,AD=$FF,SR=$E0).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/make.bat b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/make.bat new file mode 100644 index 00000000..d3e1211e --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/SpeechSynth/make.bat @@ -0,0 +1,2 @@ +bass SpeechSynth_spc.asm +bass SpeechSynth.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle.spc b/roms/snes/peter-lemon-snes/SPC700/Twinkle.spc new file mode 100644 index 00000000..b0c6f88e Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Twinkle.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr b/roms/snes/peter-lemon-snes/SPC700/Twinkle/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr new file mode 100644 index 00000000..2a42437f Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Twinkle/BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES.INC b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES.INC new file mode 100644 index 00000000..dba4793c --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES.INC @@ -0,0 +1,507 @@ +//============== (Key: R=Read, W=Write, D=Double Read/Write) +// SNES Include +//============== +// Memory Map +constant WRAM($0000) // WRAM Mirror ($7E0000-$7E1FFF) 8KB/RW + +// PPU Picture Processing Unit Ports (Write-Only) +constant REG_INIDISP($2100) // Display Control 1 1B/W +constant REG_OBSEL($2101) // Object Size & Object Base 1B/W +constant REG_OAMADDL($2102) // OAM Address (Lower 8-Bit) 2B/W +constant REG_OAMADDH($2103) // OAM Address (Upper 1-Bit) & Priority Rotation 1B/W +constant REG_OAMDATA($2104) // OAM Data Write 1B/W D +constant REG_BGMODE($2105) // BG Mode & BG Character Size 1B/W +constant REG_MOSAIC($2106) // Mosaic Size & Mosaic Enable 1B/W +constant REG_BG1SC($2107) // BG1 Screen Base & Screen Size 1B/W +constant REG_BG2SC($2108) // BG2 Screen Base & Screen Size 1B/W +constant REG_BG3SC($2109) // BG3 Screen Base & Screen Size 1B/W +constant REG_BG4SC($210A) // BG4 Screen Base & Screen Size 1B/W +constant REG_BG12NBA($210B) // BG1/BG2 Character Data Area Designation 1B/W +constant REG_BG34NBA($210C) // BG3/BG4 Character Data Area Designation 1B/W +constant REG_BG1HOFS($210D) // BG1 Horizontal Scroll (X) / M7HOFS 1B/W D +constant REG_BG1VOFS($210E) // BG1 Vertical Scroll (Y) / M7VOFS 1B/W D +constant REG_BG2HOFS($210F) // BG2 Horizontal Scroll (X) 1B/W D +constant REG_BG2VOFS($2110) // BG2 Vertical Scroll (Y) 1B/W D +constant REG_BG3HOFS($2111) // BG3 Horizontal Scroll (X) 1B/W D +constant REG_BG3VOFS($2112) // BG3 Vertical Scroll (Y) 1B/W D +constant REG_BG4HOFS($2113) // BG4 Horizontal Scroll (X) 1B/W D +constant REG_BG4VOFS($2114) // BG4 Vertical Scroll (Y) 1B/W D +constant REG_VMAIN($2115) // VRAM Address Increment Mode 1B/W +constant REG_VMADDL($2116) // VRAM Address (Lower 8-Bit) 2B/W +constant REG_VMADDH($2117) // VRAM Address (Upper 8-Bit) 1B/W +constant REG_VMDATAL($2118) // VRAM Data Write (Lower 8-Bit) 2B/W +constant REG_VMDATAH($2119) // VRAM Data Write (Upper 8-Bit) 1B/W +constant REG_M7SEL($211A) // Mode7 Rot/Scale Mode Settings 1B/W +constant REG_M7A($211B) // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand 1B/W D +constant REG_M7B($211C) // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand 1B/W D +constant REG_M7C($211D) // Mode7 Rot/Scale C (SINE B) 1B/W D +constant REG_M7D($211E) // Mode7 Rot/Scale D (COSINE B) 1B/W D +constant REG_M7X($211F) // Mode7 Rot/Scale Center Coordinate X 1B/W D +constant REG_M7Y($2120) // Mode7 Rot/Scale Center Coordinate Y 1B/W D +constant REG_CGADD($2121) // Palette CGRAM Address 1B/W +constant REG_CGDATA($2122) // Palette CGRAM Data Write 1B/W D +constant REG_W12SEL($2123) // Window BG1/BG2 Mask Settings 1B/W +constant REG_W34SEL($2124) // Window BG3/BG4 Mask Settings 1B/W +constant REG_WOBJSEL($2125) // Window OBJ/MATH Mask Settings 1B/W +constant REG_WH0($2126) // Window 1 Left Position (X1) 1B/W +constant REG_WH1($2127) // Window 1 Right Position (X2) 1B/W +constant REG_WH2($2128) // Window 2 Left Position (X1) 1B/W +constant REG_WH3($2129) // Window 2 Right Position (X2) 1B/W +constant REG_WBGLOG($212A) // Window 1/2 Mask Logic (BG1..BG4) 1B/W +constant REG_WOBJLOG($212B) // Window 1/2 Mask Logic (OBJ/MATH) 1B/W +constant REG_TM($212C) // Main Screen Designation 1B/W +constant REG_TS($212D) // Sub Screen Designation 1B/W +constant REG_TMW($212E) // Window Area Main Screen Disable 1B/W +constant REG_TSW($212F) // Window Area Sub Screen Disable 1B/W +constant REG_CGWSEL($2130) // Color Math Control Register A 1B/W +constant REG_CGADSUB($2131) // Color Math Control Register B 1B/W +constant REG_COLDATA($2132) // Color Math Sub Screen Backdrop Color 1B/W +constant REG_SETINI($2133) // Display Control 2 1B/W + +// PPU Picture Processing Unit Ports (Read-Only) +constant REG_MPYL($2134) // PPU1 Signed Multiply Result (Lower 8-Bit) 1B/R +constant REG_MPYM($2135) // PPU1 Signed Multiply Result (Middle 8-Bit) 1B/R +constant REG_MPYH($2136) // PPU1 Signed Multiply Result (Upper 8-Bit) 1B/R +constant REG_SLHV($2137) // PPU1 Latch H/V-Counter By Software (Read=Strobe) 1B/R +constant REG_RDOAM($2138) // PPU1 OAM Data Read 1B/R D +constant REG_RDVRAML($2139) // PPU1 VRAM Data Read (Lower 8-Bit) 1B/R +constant REG_RDVRAMH($213A) // PPU1 VRAM Data Read (Upper 8-Bit) 1B/R +constant REG_RDCGRAM($213B) // PPU2 CGRAM Data Read (Palette) 1B/R D +constant REG_OPHCT($213C) // PPU2 Horizontal Counter Latch (Scanline X) 1B/R D +constant REG_OPVCT($213D) // PPU2 Vertical Counter Latch (Scanline Y) 1B/R D +constant REG_STAT77($213E) // PPU1 Status & PPU1 Version Number 1B/R +constant REG_STAT78($213F) // PPU2 Status & PPU2 Version Number (Bit 7=0) 1B/R + +// APU Audio Processing Unit Ports (Read/Write) +constant REG_APUIO0($2140) // Main CPU To Sound CPU Communication Port 0 1B/RW +constant REG_APUIO1($2141) // Main CPU To Sound CPU Communication Port 1 1B/RW +constant REG_APUIO2($2142) // Main CPU To Sound CPU Communication Port 2 1B/RW +constant REG_APUIO3($2143) // Main CPU To Sound CPU Communication Port 3 1B/RW +// $2140..$2143 - APU Ports Mirrored To $2144..$217F + +// WRAM Access Ports +constant REG_WMDATA($2180) // WRAM Data Read/Write 1B/RW +constant REG_WMADDL($2181) // WRAM Address (Lower 8-Bit) 1B/W +constant REG_WMADDM($2182) // WRAM Address (Middle 8-Bit) 1B/W +constant REG_WMADDH($2183) // WRAM Address (Upper 1-Bit) 1B/W +// $2184..$21FF - Unused Region (Open Bus)/Expansion (B-Bus) +// $2200..$3FFF - Unused Region (A-Bus) + +// CPU On-Chip I/O Ports (These Have Long Waitstates: 1.78MHz Cycles Instead Of 3.5MHz) +// ($4000..$4015 - Unused Region (Open Bus) +constant REG_JOYWR($4016) // Joypad Output 1B/W +constant REG_JOYA($4016) // Joypad Input Register A (Joypad Auto Polling) 1B/R +constant REG_JOYB($4017) // Joypad Input Register B (Joypad Auto Polling) 1B/R +// $4018..$41FF - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Write-only, Read=Open Bus) +constant REG_NMITIMEN($4200) // Interrupt Enable & Joypad Request 1B/W +constant REG_WRIO($4201) // Programmable I/O Port (Open-Collector Output) 1B/W +constant REG_WRMPYA($4202) // Set Unsigned 8-Bit Multiplicand 1B/W +constant REG_WRMPYB($4203) // Set Unsigned 8-Bit Multiplier & Start Multiplication 1B/W +constant REG_WRDIVL($4204) // Set Unsigned 16-Bit Dividend (Lower 8-Bit) 2B/W +constant REG_WRDIVH($4205) // Set Unsigned 16-Bit Dividend (Upper 8-Bit) 1B/W +constant REG_WRDIVB($4206) // Set Unsigned 8-Bit Divisor & Start Division 1B/W +constant REG_HTIMEL($4207) // H-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_HTIMEH($4208) // H-Count Timer Setting (Upper 1bit) 1B/W +constant REG_VTIMEL($4209) // V-Count Timer Setting (Lower 8-Bit) 2B/W +constant REG_VTIMEH($420A) // V-Count Timer Setting (Upper 1-Bit) 1B/W +constant REG_MDMAEN($420B) // Select General Purpose DMA Channels & Start Transfer 1B/W +constant REG_HDMAEN($420C) // Select H-Blank DMA (H-DMA) Channels 1B/W +constant REG_MEMSEL($420D) // Memory-2 Waitstate Control 1B/W +// $420E..$420F - Unused Region (Open Bus) + +// CPU On-Chip I/O Ports (Read-only) +constant REG_RDNMI($4210) // V-Blank NMI Flag and CPU Version Number (Read/Ack) 1B/R +constant REG_TIMEUP($4211) // H/V-Timer IRQ Flag (Read/Ack) 1B/R +constant REG_HVBJOY($4212) // H/V-Blank Flag & Joypad Busy Flag 1B/R +constant REG_RDIO($4213) // Joypad Programmable I/O Port (Input) 1B/R +constant REG_RDDIVL($4214) // Unsigned Div Result (Quotient) (Lower 8-Bit) 2B/R +constant REG_RDDIVH($4215) // Unsigned Div Result (Quotient) (Upper 8-Bit) 1B/R +constant REG_RDMPYL($4216) // Unsigned Div Remainder / Mul Product (Lower 8-Bit) 2B/R +constant REG_RDMPYH($4217) // Unsigned Div Remainder / Mul Product (Upper 8-Bit) 1B/R +constant REG_JOY1L($4218) // Joypad 1 (Gameport 1, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY1H($4219) // Joypad 1 (Gameport 1, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY2L($421A) // Joypad 2 (Gameport 2, Pin 4) (Lower 8-Bit) 2B/R +constant REG_JOY2H($421B) // Joypad 2 (Gameport 2, Pin 4) (Upper 8-Bit) 1B/R +constant REG_JOY3L($421C) // Joypad 3 (Gameport 1, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY3H($421D) // Joypad 3 (Gameport 1, Pin 5) (Upper 8-Bit) 1B/R +constant REG_JOY4L($421E) // Joypad 4 (Gameport 2, Pin 5) (Lower 8-Bit) 2B/R +constant REG_JOY4H($421F) // Joypad 4 (Gameport 2, Pin 5) (Upper 8-Bit) 1B/R +// $4220..$42FF - Unused Region (Open Bus) + +// CPU DMA Ports (Read/Write) ($43XP X = Channel Number 0..7, P = Port) +constant REG_DMAP0($4300) // DMA0 DMA/HDMA Parameters 1B/RW +constant REG_BBAD0($4301) // DMA0 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T0L($4302) // DMA0 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T0H($4303) // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B0($4304) // DMA0 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS0L($4305) // DMA0 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS0H($4306) // DMA0 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB0($4307) // DMA0 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A0L($4308) // DMA0 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A0H($4309) // DMA0 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL0($430A) // DMA0 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED0($430B) // DMA0 Unused Byte 1B/RW +// $430C..$430E - Unused Region (Open Bus) +constant REG_MIRR0($430F) // DMA0 Mirror Of $430B 1B/RW + +constant REG_DMAP1($4310) // DMA1 DMA/HDMA Parameters 1B/RW +constant REG_BBAD1($4311) // DMA1 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T1L($4312) // DMA1 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T1H($4313) // DMA1 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B1($4314) // DMA1 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS1L($4315) // DMA1 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS1H($4316) // DMA1 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB1($4317) // DMA1 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A1L($4318) // DMA1 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A1H($4319) // DMA1 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL1($431A) // DMA1 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED1($431B) // DMA1 Unused Byte 1B/RW +// $431C..$431E - Unused Region (Open Bus) +constant REG_MIRR1($431F) // DMA1 Mirror Of $431B 1B/RW + +constant REG_DMAP2($4320) // DMA2 DMA/HDMA Parameters 1B/RW +constant REG_BBAD2($4321) // DMA2 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T2L($4322) // DMA2 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T2H($4323) // DMA2 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B2($4324) // DMA2 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS2L($4325) // DMA2 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS2H($4326) // DMA2 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB2($4327) // DMA2 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A2L($4328) // DMA2 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A2H($4329) // DMA2 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL2($432A) // DMA2 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED2($432B) // DMA2 Unused Byte 1B/RW +// $432C..$432E - Unused Region (Open Bus) +constant REG_MIRR2($432F) // DMA2 Mirror Of $432B 1B/RW + +constant REG_DMAP3($4330) // DMA3 DMA/HDMA Parameters 1B/RW +constant REG_BBAD3($4331) // DMA3 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T3L($4332) // DMA3 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T3H($4333) // DMA3 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B3($4334) // DMA3 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS3L($4335) // DMA3 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS3H($4336) // DMA3 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB3($4337) // DMA3 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A3L($4338) // DMA3 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A3H($4339) // DMA3 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL3($433A) // DMA3 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED3($433B) // DMA3 Unused Byte 1B/RW +// $433C..$433E - Unused Region (Open Bus) +constant REG_MIRR3($433F) // DMA3 Mirror Of $433B 1B/RW + +constant REG_DMAP4($4340) // DMA4 DMA/HDMA Parameters 1B/RW +constant REG_BBAD4($4341) // DMA4 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T4L($4342) // DMA4 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T4H($4343) // DMA4 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B4($4344) // DMA4 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS4L($4345) // DMA4 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS4H($4346) // DMA4 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB4($4347) // DMA4 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A4L($4348) // DMA4 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A4H($4349) // DMA4 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL4($434A) // DMA4 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED4($434B) // DMA4 Unused Byte 1B/RW +// $434C..$434E - Unused Region (Open Bus) +constant REG_MIRR4($434F) // DMA4 Mirror Of $434B 1B/RW + +constant REG_DMAP5($4350) // DMA5 DMA/HDMA Parameters 1B/RW +constant REG_BBAD5($4351) // DMA5 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T5L($4352) // DMA5 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T5H($4353) // DMA5 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B5($4354) // DMA5 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS5L($4355) // DMA5 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS5H($4356) // DMA5 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB5($4357) // DMA5 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A5L($4358) // DMA5 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A5H($4359) // DMA5 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL5($435A) // DMA5 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED5($435B) // DMA5 Unused Byte 1B/RW +// $435C..$435E - Unused Region (Open Bus) +constant REG_MIRR5($435F) // DMA5 Mirror Of $435B 1B/RW + +constant REG_DMAP6($4360) // DMA6 DMA/HDMA Parameters 1B/RW +constant REG_BBAD6($4361) // DMA6 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T6L($4362) // DMA6 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T6H($4363) // DMA6 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B6($4364) // DMA6 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS6L($4365) // DMA6 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS6H($4366) // DMA6 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB6($4367) // DMA6 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A6L($4368) // DMA6 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A6H($4369) // DMA6 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL6($436A) // DMA6 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED6($436B) // DMA6 Unused Byte 1B/RW +// $436C..$436E - Unused Region (Open Bus) +constant REG_MIRR6($436F) // DMA6 Mirror Of $436B 1B/RW + +constant REG_DMAP7($4370) // DMA7 DMA/HDMA Parameters 1B/RW +constant REG_BBAD7($4371) // DMA7 DMA/HDMA I/O-Bus Address (PPU-Bus AKA B-Bus) 1B/RW +constant REG_A1T7L($4372) // DMA7 DMA/HDMA Table Start Address (Lower 8-Bit) 2B/RW +constant REG_A1T7H($4373) // DMA7 DMA/HDMA Table Start Address (Upper 8-Bit) 1B/RW +constant REG_A1B7($4374) // DMA7 DMA/HDMA Table Start Address (Bank) 1B/RW +constant REG_DAS7L($4375) // DMA7 DMA Count / Indirect HDMA Address (Lower 8-Bit) 2B/RW +constant REG_DAS7H($4376) // DMA7 DMA Count / Indirect HDMA Address (Upper 8-Bit) 1B/RW +constant REG_DASB7($4377) // DMA7 Indirect HDMA Address (Bank) 1B/RW +constant REG_A2A7L($4378) // DMA7 HDMA Table Current Address (Lower 8-Bit) 2B/RW +constant REG_A2A7H($4379) // DMA7 HDMA Table Current Address (Upper 8-Bit) 1B/RW +constant REG_NTRL7($437A) // DMA7 HDMA Line-Counter (From Current Table entry) 1B/RW +constant REG_UNUSED7($437B) // DMA7 Unused Byte 1B/RW +// $437C..$437E - Unused Region (Open Bus) +constant REG_MIRR7($437F) // DMA7 Mirror Of $437B 1B/RW +// $4380..$5FFF - Unused Region (Open Bus) + +// Further Memory +// $6000..$7FFF - Expansion (Battery Backed RAM, In HiROM Cartridges) +// $8000..$FFFF - Cartridge ROM + +//================================================ +// ReadD16 - Read Double 8-bit To Memory (16-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro ReadD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} // Load Source High Byte + sta {DEST} + 1 // Store Destination High Byte +} + +//==================================================== +// ReadD16Index - Read Double 8-bit To Index (16-Bit) +//==================================================== +// SRC: Source Address +// REG: Destination Index Register (x, y) +macro ReadD16Index(SRC, REG) { + lda {SRC} // Load Source Low Byte + xba // Exchange B & A Accumulators + lda {SRC} // Load Source High Byte + xba // Exchange B & A Accumulators + ta{REG} // Transfer 16-Bit A To 16-Bit REG +} + +//================================================ +// WriteD8 - Write Memory To Double 8-bit (8-Bit) +//================================================ +// SRC: Source Address +// DEST: Destination Address +macro WriteD8(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//================================================== +// WriteD16 - Write Memory To Double 8-bit (16-Bit) +//================================================== +// SRC: Source Address +// DEST: Destination Address +macro WriteD16(SRC, DEST) { + lda {SRC} // Load Source Low Byte + sta {DEST} // Store Destination Low Byte + lda {SRC} + 1 // Load Source High Byte + sta {DEST} // Store Destination High Byte +} + +//==================================================== +// WriteD8Index - Write Index To Double 8-bit (8-Bit) +//==================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD8Index(REG, DEST) { + t{REG}a // Transfer 8-Bit REG To 8-Bit A + sta {DEST} // Store Destination Low Byte + stz {DEST} // Store Zero To Destination High Byte +} + +//====================================================== +// WriteD16Index - Write Index To Double 8-bit (16-Bit) +//====================================================== +// REG: Source Index Register (x, y) +// DEST: Destination Address +macro WriteD16Index(REG, DEST) { + rep #$38 // Set 16-Bit Accumulator & Index + t{REG}a // Transfer 16-Bit REG To 16-Bit A + sep #$20 // Set 8-Bit Accumulator + sta {DEST} // Store Destination Low Byte + xba // Exchange B & A Accumulators + sta {DEST} // Store Destination High Byte +} + +//===================== +// SNES Initialisation +//===================== +// ROMSPEED: ROM Speed (SLOWROM, FASTROM) +constant SLOWROM(0) // Access Cycle Designation (Slow ROM) +constant FASTROM(1) // Access Cycle Designation (Fast ROM) +macro SNES_INIT(ROMSPEED) { + sei // Disable Interrupts + clc // Clear Carry To Switch To Native Mode + xce // Xchange Carry & Emulation Bit (Native Mode) + + phk + plb + rep #$38 + + ldx.w #$1FFF // Set Stack To $1FFF + txs // Transfer Index Register X To Stack Pointer + + lda.w #$0000 + tcd + + sep #$20 // Set 8-Bit Accumulator + + lda.b #{ROMSPEED} // Romspeed: Slow ROM = 0, Fast ROM = 1 + sta.w REG_MEMSEL // Access Cycle Designation (Slow ROM / Fast ROM) + + lda.b #$8F // Force VBlank (Screen Off, Maximum Brightness) + sta.w REG_INIDISP // Display Control 1: Brightness & Screen Enable Register ($2100) + + stz.w REG_OBSEL // Object Size & Object Base ($2101) + stz.w REG_OAMADDL // OAM Address (Lower 8-Bit) ($2102) + stz.w REG_OAMADDH // OAM Address (Upper 1-Bit) & Priority Rotation ($2103) + stz.w REG_BGMODE // BG Mode & BG Character Size: Set Graphics Mode 0 ($2105) + stz.w REG_MOSAIC // Mosaic Size & Mosaic Enable: No Planes, No Mosiac ($2106) + stz.w REG_BG1SC // BG1 Screen Base & Screen Size: BG1 Map VRAM Location = $0000 ($2107) + stz.w REG_BG2SC // BG2 Screen Base & Screen Size: BG2 Map VRAM Location = $0000 ($2108) + stz.w REG_BG3SC // BG3 Screen Base & Screen Size: BG3 Map VRAM Location = $0000 ($2109) + stz.w REG_BG4SC // BG4 Screen Base & Screen Size: BG4 Map VRAM Location = $0000 ($210A) + stz.w REG_BG12NBA // BG1/BG2 Character Data Area Designation: BG1/BG2 Tile Data Location = $0000 ($210B) + stz.w REG_BG34NBA // BG3/BG4 Character Data Area Designation: BG3/BG4 Tile Data Location = $0000 ($210C) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210D) + stz.w REG_BG1HOFS // BG1 Horizontal Scroll (X) / M7HOFS: BG1 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210D) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($210E) + stz.w REG_BG1VOFS // BG1 Vertical Scroll (Y) / M7VOFS: BG1 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($210E) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($210F) + stz.w REG_BG2HOFS // BG2 Horizontal Scroll (X): BG2 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($210F) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2110) + stz.w REG_BG2VOFS // BG2 Vertical Scroll (Y): BG2 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2110) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2111) + stz.w REG_BG3HOFS // BG3 Horizontal Scroll (X): BG3 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2111) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2112) + stz.w REG_BG3VOFS // BG3 Vertical Scroll (Y): BG3 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2112) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 1st Write = 0 (Lower 8-Bit) ($2113) + stz.w REG_BG4HOFS // BG4 Horizontal Scroll (X): BG4 Horizontal Scroll 2nd Write = 0 (Upper 3-Bit) ($2113) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 1st Write = 0 (Lower 8-Bit) ($2114) + stz.w REG_BG4VOFS // BG4 Vertical Scroll (Y): BG4 Vertical Scroll 2nd Write = 0 (Upper 3-Bit) ($2114) + + lda.b #$01 + stz.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 1st Write = 0 (Lower 8-Bit) ($211B) + sta.w REG_M7A // Mode7 Rot/Scale A (COSINE A) & Maths 16-Bit Operand: 2nd Write = 1 (Upper 8-Bit) ($211B) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 1st Write = 0 (Lower 8-Bit) ($211C) + stz.w REG_M7B // Mode7 Rot/Scale B (SINE A) & Maths 8-bit Operand: 2nd Write = 0 (Upper 8-Bit) ($211C) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 1st Write = 0 (Lower 8-Bit) ($211D) + stz.w REG_M7C // Mode7 Rot/Scale C (SINE B): 2nd Write = 0 (Upper 8-Bit) ($211D) + stz.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 1st Write = 0 (Lower 8-Bit) ($211E) + sta.w REG_M7D // Mode7 Rot/Scale D (COSINE B): 2nd Write = 1 (Upper 8-Bit) ($211E) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 1st Write = 0 (Lower 8-Bit) ($211F) + stz.w REG_M7X // Mode7 Rot/Scale Center Coordinate X: 2nd Write = 0 (Upper 8-Bit) ($211F) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 1st Write = 0 (Lower 8-Bit) ($2120) + stz.w REG_M7Y // Mode7 Rot/Scale Center Coordinate Y: 2nd Write = 0 (Upper 8-Bit) ($2120) + + stz.w REG_W12SEL // Window BG1/BG2 Mask Settings = 0 ($2123) + stz.w REG_W34SEL // Window BG3/BG4 Mask Settings = 0 ($2124) + stz.w REG_WOBJSEL // Window OBJ/MATH Mask Settings = 0 ($2125) + stz.w REG_WH0 // Window 1 Left Position (X1) = 0 ($2126) + stz.w REG_WH1 // Window 1 Right Position (X2) = 0 ($2127) + stz.w REG_WH2 // Window 2 Left Position (X1) = 0 ($2128) + stz.w REG_WH3 // Window 2 Right Position (X2) = 0 ($2129) + stz.w REG_WBGLOG // Window 1/2 Mask Logic (BG1..BG4) = 0 ($212A) + stz.w REG_WOBJLOG // Window 1/2 Mask Logic (OBJ/MATH) = 0 ($212B) + stz.w REG_TM // Main Screen Designation = 0 ($212C) + stz.w REG_TS // Sub Screen Designation = 0 ($212D) + stz.w REG_TMW // Window Area Main Screen Disable = 0 ($212E) + stz.w REG_TSW // Window Area Sub Screen Disable = 0 ($212F) + + lda.b #$30 + sta.w REG_CGWSEL // Color Math Control Register A = $30 ($2130) + stz.w REG_CGADSUB // Color Math Control Register B = 0 ($2131) + + lda.b #$E0 + sta.w REG_COLDATA // Color Math Sub Screen Backdrop Color = $E0 ($2132) + stz.w REG_SETINI // Display Control 2 = 0 ($2133) + + stz.w REG_JOYWR // Joypad Output = 0 ($4016) + + stz.w REG_NMITIMEN // Interrupt Enable & Joypad Request: Reset VBlank, Interrupt, Joypad ($4200) + + lda.b #$FF + sta.w REG_WRIO // Programmable I/O Port (Open-Collector Output) = $FF ($4201) + + stz.w REG_WRMPYA // Set Unsigned 8-Bit Multiplicand = 0 ($4202) + stz.w REG_WRMPYB // Set Unsigned 8-Bit Multiplier & Start Multiplication = 0 ($4203) + stz.w REG_WRDIVL // Set Unsigned 16-Bit Dividend (Lower 8-Bit) = 0 ($4204) + stz.w REG_WRDIVH // Set Unsigned 16-Bit Dividend (Upper 8-Bit) = 0 ($4205) + stz.w REG_WRDIVB // Set Unsigned 8-Bit Divisor & Start Division = 0 ($4206) + stz.w REG_HTIMEL // H-Count Timer Setting (Lower 8-Bit) = 0 ($4207) + stz.w REG_HTIMEH // H-Count Timer Setting (Upper 1-Bit) = 0 ($4208) + stz.w REG_VTIMEL // V-Count Timer Setting (Lower 8-Bit) = 0 ($4209) + stz.w REG_VTIMEH // V-Count Timer Setting (Upper 1-Bit) = 0 ($420A) + stz.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer = 0 ($420B) + stz.w REG_HDMAEN // Select H-Blank DMA (H-DMA) Channels = 0 ($420C) + + // Clear OAM + ldx.w #$0080 + lda.b #$E0 + - + sta.w REG_OAMDATA // OAM Data Write 1st Write = $E0 (Lower 8-Bit) ($2104) + sta.w REG_OAMDATA // OAM Data Write 2nd Write = $E0 (Upper 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 1st Write = 0 (Lower 8-Bit) ($2104) + stz.w REG_OAMDATA // OAM Data Write 2nd Write = 0 (Upper 8-Bit) ($2104) + dex + bne - + + ldx.w #$0020 + - + stz.w REG_OAMDATA // OAM Data Write 1st/2nd Write = 0 (Lower/Upper 8-Bit) ($2104) + dex + bne - + + // Clear WRAM + ldy.w #$0000 + sty.w REG_WMADDL // WRAM Address (Lower 8-Bit): Transfer To $7E:0000 ($2181) + stz.w REG_WMADDH // WRAM Address (Upper 1-Bit): Select 1st WRAM Bank = $7E ($2183) + + ldx.w #$8008 // Fixed Source Byte Write To REG_WMDATA: WRAM Data Read/Write ($2180) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + ldx.w #CONST_ZERO // Load Lower 16-Bit Address Of Zero Data In Rom + lda.b #CONST_ZERO>>16 // Load Upper 8-Bit Address Of Zero Data In ROM (Bank) + stx.w REG_A1T0L // DMA0 DMA/HDMA Table Start Address (Lower 16-Bit) ($4302) + sta.w REG_A1B0 // DMA0 DMA/HDMA Table Start Address (Upper 8-Bit) (Bank) ($4304) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + nop // Delay + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer: $2181..$2183 & $4305 Wrap Appropriately ($420B) + + // VRAM + lda.b #$80 // Increment VRAM Address On Writes To REG_VMDATAH: VRAM Data Write (Upper 8-Bit) ($2119) + sta.w REG_VMAIN // VRAM Address Increment Mode ($2115) + ldy.w #$0000 + sty.w REG_VMADDL // VRAM Address: Begin At VRAM Address $0000 ($2116) + sty.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address: Transfer 64KB ($4305) + + ldx.w #$1809 // Fixed Source Alternate Byte Write To REG_VMDATAL/REG_VMDATAH: VRAM Data Write (Lower/Upper 8-Bit) ($2118/$2119) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + + lda.b #$01 + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + // CGRAM + stz.w REG_CGADD // Palette CGRAM Address = 0 ($2121) + ldx.w #$200 // 512 Byte + stx.w REG_DAS0L // DMA0 DMA Count / Indirect HDMA Address ($4305) + ldx.w #$2208 // Fixed Source Byte Write To REG_CGDATA: Palette CGRAM Data Write ($2122) + stx.w REG_DMAP0 // DMA0 DMA/HDMA Parameters ($4300) + sta.w REG_MDMAEN // Select General Purpose DMA Channels & Start Transfer ($420B) + + jml + + +CONST_ZERO: + dw $0000 + + + +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_HEADER.ASM b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_HEADER.ASM new file mode 100644 index 00000000..29e1140f --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_HEADER.ASM @@ -0,0 +1,93 @@ +//============= +// SNES Header +//============= +seek($FFC0) +// PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) +db "TWINKLE SONG " +// "123456789012345678901" + +// ROM MODE/SPEED (Bits 7-4 = Speed, Bits 3-0 = Map Mode) +db $20 +// ||___________________Map Mode: +// | $X0 = LoROM/32K Banks (Mode 20) +// | $X1 = HiROM/64K Banks (Mode 21) +// | $X2 = LoROM/32K Banks + S-DD1 (Mode 22 Mappable) +// Speed: $X3 = LoROM/32K Banks + SA-1 (Mode 23 Mappable) +// $2X = SlowROM (200ns) $X5 = HiROM/64K Banks (Mode 25 ExHiROM) +// $3X = FastROM (120ns) $XA = HiROM/64K Banks + SPC7110 (Mode 2A Mappable) + +// ROM TYPE (Bits 7-4 = Co-processor, Bits 3-0 = Type) +db $00 +// ||___________________Type: +// | $00 = ROM +// | $01 = ROM+RAM +// Co-processor: $02 = ROM+RAM+Battery +// $0X = DSP $X3 = ROM+Co-processor +// $1X = GSU $X4 = ROM+Co-processor+RAM +// $2X = OBC1 $X5 = ROM+Co-processor+RAM+Battery +// $3X = SA-1 $X6 = ROM+Co-processor+Battery +// $4X = S-DD1 $X9 = ROM+Co-processor+RAM+Battery+RTC-4513 +// $5X = S-RTC $XA = ROM+Co-processor+RAM+Battery+Overclocked + +// ROM SIZE (Values are rounded-up for carts with 10,12,20,24 Mbits) +db $01 +// $01 = 1 Bank = 32Kb (0.25 Mbit), $07 = 7 Banks = 224Kb (1.75 Mbit) +// $02 = 2 Banks = 64Kb (0.50 Mbit), $08 = 8 Banks = 256Kb (2.00 Mbit) +// $03 = 3 Banks = 96Kb (0.75 Mbit), $09 = 16 Banks = 512Kb (4.00 Mbit) +// $04 = 4 Banks = 128Kb (1.00 Mbit), $0A = 32 Banks = 1024Kb (8.00 Mbit) +// $05 = 5 Banks = 160Kb (1.25 Mbit), $0B = 64 Banks = 2048Kb (16.00 Mbit) +// $06 = 6 Banks = 192Kb (1.50 Mbit), $0C = 128 Banks = 4096Kb (32.00 Mbit) + +// RAM SIZE +db $00 +// $00 = None, $04 = 16Kb +// $01 = 2Kb, $05 = 32Kb +// $02 = 4Kb, $06 = 64Kb +// $03 = 8Kb, $07 = 128Kb + +// COUNTRY/VIDEO REFRESH (NTSC/PAL-M = 60 Hz, PAL/SECAM = 50 Hz) +db $00 +// $00 = (J)apan (NTSC), $09 = (D)Germany, Austria, Switz (PAL) +// $01 = (E)USA, Canada (NTSC), $0A = (I)taly (PAL) +// $02 = Euro(P)e (PAL), $0B = (C)hina, Hong Kong (PAL) +// $03 = S(W)eden, Scandinavia (PAL), $0C = Indonesia (PAL) +// $04 = Finland (PAL), $0D = South (K)orea (NTSC) +// $05 = Denmark (PAL), $0E = (A)Common (ANY) +// $06 = (F)rance (SECAM), $0F = Ca(N)ada (NTSC) +// $07 = (H)olland (PAL), $10 = (B)razil (PAL-M) +// $08 = (S)pain (PAL), $11 = (U)Australia (PAL) + +// DEVELOPER ID CODE +db $00 +// $00 = None +// $01 = Nintendo +// $33 = New (Uses Extended Header) + +// ROM VERSION NUMBER +db $00 +// $00 = 1.00, $01 = 1.01 + +// COMPLEMENT CHECK +db "CC" +// CHECKSUM +db "CS" + +// NATIVE VECTOR (65C816 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (BRK Opcode) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw $0000 // RESET VECTOR (Unused) +dw $0000 // IRQ VECTOR (H/V-Timer/External Interrupt) + +// EMU VECTOR (6502 Mode) +dw $0000 // RESERVED +dw $0000 // RESERVED +dw $0000 // COP VECTOR (COP Opcode) +dw $0000 // BRK VECTOR (Unused) +dw $0000 // ABORT VECTOR (Unused) +dw $0000 // NMI VECTOR (V-Blank Interrupt) +dw Start // RESET VECTOR (CPU is always in 6502 mode on RESET) +dw $0000 // IRQ/BRK VECTOR \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_SPC700.INC b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_SPC700.INC new file mode 100644 index 00000000..ef99d356 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/LIB/SNES_SPC700.INC @@ -0,0 +1,601 @@ +//============= (Key: R=Read, W=Write) +// SNES SPC700 +//============= +// Memory Map +constant SPCPAGE0($0000) // RAM Page 0 (Typically Used For CPU Pointers/Variables) 240B/RW +// $00F0..$00FF - I/O Ports (Writes Are Also Passed To RAM) +constant SPCPAGE1($0100) // RAM Page 1 (Typically Used For CPU Stack) 256B/RW +constant SPCRAM($0200) // RAM (Code, Data, Dir-Table, BRR-Samples, Echo-Buffer) 64960B/RW +constant SPCIPL($FFC0) // 64-Byte IPL Boot ROM Or RAM (Selectable Via Port $00F1) 64B/RW + +// I/O Ports (CPU Includes 16 Memory Mapper Ports At Address $00F0..$00FF) +constant REG_TEST($F0) // Testing Functions 1B/W +constant REG_CONTROL($F1) // Timer, I/O & ROM Control 1B/W +constant REG_DSPADDR($F2) // DSP Register Index 1B/RW +constant REG_DSPDATA($F3) // DSP Register Data 1B/RW +constant REG_CPUIO0($F4) // CPU Input & Output Register 0 1B/RW +constant REG_CPUIO1($F5) // CPU Input & Output Register 1 1B/RW +constant REG_CPUIO2($F6) // CPU Input & Output Register 2 1B/RW +constant REG_CPUIO3($F7) // CPU Input & Output Register 3 1B/RW +constant REG_AUXIO4($F8) // External I/O Port P4 (S-SMP Pins 34-27) 1B/RW +constant REG_AUXIO5($F9) // External I/O Port P5 (S-SMP Pins 25-18) 1B/RW +constant REG_T0DIV($FA) // Timer 0 Divider (8000Hz Clock Source) 1B/W +constant REG_T1DIV($FB) // Timer 1 Divider (8000Hz Clock Source) 1B/W +constant REG_T2DIV($FC) // Timer 2 Divider (64000Hz Clock Source) 1B/W +constant REG_T0OUT($FD) // Timer 0 Output 1B/R +constant REG_T1OUT($FE) // Timer 1 Output 1B/R +constant REG_T2OUT($FF) // Timer 2 Output 1B/R + +// DSP Registers (128 DSP Registers Are Indirectly Accessed Via I/O Ports $00F2/$00F3) +constant DSP_MVOLL($0C) // Left Channel Master Volume 1B/RW +constant DSP_MVOLR($1C) // Right Channel Master Volume 1B/RW +constant DSP_EVOLL($2C) // Left Channel Echo Volume 1B/RW +constant DSP_EVOLR($3C) // Right Channel Echo Volume 1B/RW +constant DSP_KON($4C) // Voice 0..7 Key On Flags 1B/W +constant DSP_KOFF($5C) // Voice 0..7 Key Off Flags 1B/RW +constant DSP_FLG($6C) // DSP Reset, Mute, Echo-Write Flags & Noise Clock 1B/RW +constant DSP_ENDX($7C) // Voice 0..7 End Flags 1B/R + +constant DSP_EFB($0D) // Echo Feedback Volume 1B/RW +constant DSP_UNUSED($1D) // Unused Byte (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_PMON($2D) // Voice 0..7 Pitch Modulation Enable Flags 1B/RW +constant DSP_NON($3D) // Voice 0..7 Noise Enable Flags 1B/RW +constant DSP_EON($4D) // Voice 0..7 Echo Enable Flags 1B/RW +constant DSP_DIR($5D) // Sample Table Address (DIR * $100) 1B/RW +constant DSP_ESA($6D) // Echo Ring Buffer Address (ESA * $100) 1B/RW +constant DSP_EDL($7D) // Echo Delay (Ring Buffer Size) 1B/RW + +constant DSP_FIR0($0F) // Echo FIR Filter Coefficient 0 1B/RW +constant DSP_FIR1($1F) // Echo FIR Filter Coefficient 1 1B/RW +constant DSP_FIR2($2F) // Echo FIR Filter Coefficient 2 1B/RW +constant DSP_FIR3($3F) // Echo FIR Filter Coefficient 3 1B/RW +constant DSP_FIR4($4F) // Echo FIR Filter Coefficient 4 1B/RW +constant DSP_FIR5($5F) // Echo FIR Filter Coefficient 5 1B/RW +constant DSP_FIR6($6F) // Echo FIR Filter Coefficient 6 1B/RW +constant DSP_FIR7($7F) // Echo FIR Filter Coefficient 7 1B/RW + +constant DSP_V0VOLL($00) // Voice 0 Left Volume 1B/RW +constant DSP_V0VOLR($01) // Voice 0 Right Volume 1B/RW +constant DSP_V0PITCHL($02) // Voice 0 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V0PITCHH($03) // Voice 0 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V0SRCN($04) // Voice 0 Source Number (0-255) 1B/RW +constant DSP_V0ADSR1($05) // Voice 0 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V0ADSR2($06) // Voice 0 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V0GAIN($07) // Voice 0 Gain Settings 1B/RW +constant DSP_V0ENVX($08) // Voice 0 Current Envelope Value 1B/R +constant DSP_V0OUTX($09) // Voice 0 Current Sample Value 1B/R +constant DSP_V0UNUSEDA($0A) // Voice 0 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDB($0B) // Voice 0 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V0UNUSEDC($0E) // Voice 0 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V1VOLL($10) // Voice 1 Left Volume 1B/RW +constant DSP_V1VOLR($11) // Voice 1 Right Volume 1B/RW +constant DSP_V1PITCHL($12) // Voice 1 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V1PITCHH($13) // Voice 1 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V1SRCN($14) // Voice 1 Source Number (0-255) 1B/RW +constant DSP_V1ADSR1($15) // Voice 1 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V1ADSR2($16) // Voice 1 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V1GAIN($17) // Voice 1 Gain Settings 1B/RW +constant DSP_V1ENVX($18) // Voice 1 Current Envelope Value 1B/R +constant DSP_V1OUTX($19) // Voice 1 Current Sample Value 1B/R +constant DSP_V1UNUSEDA($1A) // Voice 1 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDB($1B) // Voice 1 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V1UNUSEDC($1E) // Voice 1 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V2VOLL($20) // Voice 2 Left Volume 1B/RW +constant DSP_V2VOLR($21) // Voice 2 Right Volume 1B/RW +constant DSP_V2PITCHL($22) // Voice 2 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V2PITCHH($23) // Voice 2 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V2SRCN($24) // Voice 2 Source Number (0-255) 1B/RW +constant DSP_V2ADSR1($25) // Voice 2 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V2ADSR2($26) // Voice 2 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V2GAIN($27) // Voice 2 Gain Settings 1B/RW +constant DSP_V2ENVX($28) // Voice 2 Current Envelope Value 1B/R +constant DSP_V2OUTX($29) // Voice 2 Current Sample Value 1B/R +constant DSP_V2UNUSEDA($2A) // Voice 2 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDB($2B) // Voice 2 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V2UNUSEDC($2E) // Voice 2 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V3VOLL($30) // Voice 3 Left Volume 1B/RW +constant DSP_V3VOLR($31) // Voice 3 Right Volume 1B/RW +constant DSP_V3PITCHL($32) // Voice 3 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V3PITCHH($33) // Voice 3 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V3SRCN($34) // Voice 3 Source Number (0-255) 1B/RW +constant DSP_V3ADSR1($35) // Voice 3 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V3ADSR2($36) // Voice 3 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V3GAIN($37) // Voice 3 Gain Settings 1B/RW +constant DSP_V3ENVX($38) // Voice 3 Current Envelope Value 1B/R +constant DSP_V3OUTX($39) // Voice 3 Current Sample Value 1B/R +constant DSP_V3UNUSEDA($3A) // Voice 3 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDB($3B) // Voice 3 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V3UNUSEDC($3E) // Voice 3 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V4VOLL($40) // Voice 4 Left Volume 1B/RW +constant DSP_V4VOLR($41) // Voice 4 Right Volume 1B/RW +constant DSP_V4PITCHL($42) // Voice 4 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V4PITCHH($43) // Voice 4 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V4SRCN($44) // Voice 4 Source Number (0-255) 1B/RW +constant DSP_V4ADSR1($45) // Voice 4 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V4ADSR2($46) // Voice 4 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V4GAIN($47) // Voice 4 Gain Settings 1B/RW +constant DSP_V4ENVX($48) // Voice 4 Current Envelope Value 1B/R +constant DSP_V4OUTX($49) // Voice 4 Current Sample Value 1B/R +constant DSP_V4UNUSEDA($4A) // Voice 4 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDB($4B) // Voice 4 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V4UNUSEDC($4E) // Voice 4 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V5VOLL($50) // Voice 5 Left Volume 1B/RW +constant DSP_V5VOLR($51) // Voice 5 Right Volume 1B/RW +constant DSP_V5PITCHL($52) // Voice 5 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V5PITCHH($53) // Voice 5 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V5SRCN($54) // Voice 5 Source Number (0-255) 1B/RW +constant DSP_V5ADSR1($55) // Voice 5 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V5ADSR2($56) // Voice 5 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V5GAIN($57) // Voice 5 Gain Settings 1B/RW +constant DSP_V5ENVX($58) // Voice 5 Current Envelope Value 1B/R +constant DSP_V5OUTX($59) // Voice 5 Current Sample Value 1B/R +constant DSP_V5UNUSEDA($5A) // Voice 5 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDB($5B) // Voice 5 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V5UNUSEDC($5E) // Voice 5 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V6VOLL($60) // Voice 6 Left Volume 1B/RW +constant DSP_V6VOLR($61) // Voice 6 Right Volume 1B/RW +constant DSP_V6PITCHL($62) // Voice 6 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V6PITCHH($63) // Voice 6 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V6SRCN($64) // Voice 6 Source Number (0-255) 1B/RW +constant DSP_V6ADSR1($65) // Voice 6 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V6ADSR2($66) // Voice 6 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V6GAIN($67) // Voice 6 Gain Settings 1B/RW +constant DSP_V6ENVX($68) // Voice 6 Current Envelope Value 1B/R +constant DSP_V6OUTX($69) // Voice 6 Current Sample Value 1B/R +constant DSP_V6UNUSEDA($6A) // Voice 6 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDB($6B) // Voice 6 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V6UNUSEDC($6E) // Voice 6 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW + +constant DSP_V7VOLL($70) // Voice 7 Left Volume 1B/RW +constant DSP_V7VOLR($71) // Voice 7 Right Volume 1B/RW +constant DSP_V7PITCHL($72) // Voice 7 Pitch Scaler (Lower 8bit) 2B/RW +constant DSP_V7PITCHH($73) // Voice 7 Pitch Scaler (Upper 6bit) 1B/RW +constant DSP_V7SRCN($74) // Voice 7 Source Number (0-255) 1B/RW +constant DSP_V7ADSR1($75) // Voice 7 ADSR Settings (Lower 8bit) 2B/RW +constant DSP_V7ADSR2($76) // Voice 7 ADSR Settings (Upper 8bit) 1B/RW +constant DSP_V7GAIN($77) // Voice 7 Gain Settings 1B/RW +constant DSP_V7ENVX($78) // Voice 7 Current Envelope Value 1B/R +constant DSP_V7OUTX($79) // Voice 7 Current Sample Value 1B/R +constant DSP_V7UNUSEDA($7A) // Voice 7 Unused Byte A (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDB($7B) // Voice 7 Unused Byte B (1 Byte Of General-Purpose RAM) 1B/RW +constant DSP_V7UNUSEDC($7E) // Voice 7 Unused Byte C (1 Byte Of General-Purpose RAM) 1B/RW +// $80..$FF - Read-Only Mirror Of $00..$7F + +// SPC700 Macros +macro WDSP(REG, variable DATA) { + str REG_DSPADDR=#{REG} + str REG_DSPDATA=#DATA +} + +macro WDSP_REG(REG) { + str REG_DSPADDR=#{REG} +} + +macro WDSP_DATA(variable DATA) { + str REG_DSPDATA=#DATA +} + +macro SPC_INIT() { // SPC700 Initialisation + WDSP(DSP_FLG,$20) // Disable Echo Buffer Writes + WDSP(DSP_KON,$00) // Reset Key On Flags + WDSP(DSP_KOFF,$FF) // Set Key Off Flags + WDSP(DSP_PMON,$00) // Reset Pitch Modulation Enable Flags + WDSP(DSP_NON,$00) // Reset Noise Enable Flags + WDSP(DSP_EON,$00) // Reset Echo On Flags + WDSP(DSP_EVOLL,0) // Reset Echo Volume Left + WDSP(DSP_EVOLR,0) // Reset Echo Volume Right +} + +macro SPCWaitMS(AMOUNT) { // Wait For MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (8kHz Timer) + ldy #{AMOUNT} // Granularity = 1..16ms, Max Wait = 256 * 1..16ms + str REG_T0DIV=#(8 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms, 3 = 8ms, 4 = 16ms) + str REG_CONTROL=#$01 +- + bbc REG_T0OUT:0=- // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCWaitSHIFTMS64(AMOUNT, SHIFT) { // Wait For Shifted MilliSecond Amount (64kHz Timer) + ldy #{AMOUNT} // Granularity = 1..4ms, Max Wait = 256 * 1..4ms + str REG_T2DIV=#($40 << {SHIFT}) & $FF // Shift MilliSecond (0 = 1ms, 1 = 2ms, 2 = 4ms) + str REG_CONTROL=#$04 +- + bbc REG_T2OUT:0=- // IF (REG_T2OUT.BIT0 == 0) Wait For Timer + bne --y=- // Y--, IF (Y != 0) Loop Timer Wait +} + +macro SPCRAMClear(ADDR, AMOUNT) { // Clear SPC RAM in 256 Byte Chunks * Amount + lda #$00 // Clear Byte + ldx #{AMOUNT} // Clear Amount High Byte + ldy #$00 // Echo Buffer Index +- + sta {ADDR},y // Store Clear Byte Into RAM Using 16-Bit Offset + bne --y=- // Y--, IF (Y != 0) Loop Clear Byte + + variable modifyoffset(-) + inc modifyoffset + 2 // Self Modify (Increment) 16-Bit ADDR (Hi Byte) Offset Above + dex // Decrement X Clear Amount High Byte + bne - // Loop Another 256 Byte Chunk +} + +macro SPCBoot() { // Run SPC Bootloader + str REG_CONTROL=#$80 // REG_CONTROL = $80 (Boot ROM ON) + jmp SPCIPL // Jump To $FFC0 (Start of Boot ROM) +} + +// 65C816 Macros +macro WaitAPUIO(PORT) { +- + cmp.w REG_APUIO{PORT} + bne - +} + +macro SPCWaitBoot() { // Wait For SPC To Boot (Call At first Use Of SPC & After Re-Run of BootROM) + lda.b #$AA + WaitAPUIO(0) + sta.w REG_APUIO0 // Clear In Case It Contains $CC + lda.b #$BB + WaitAPUIO(1) +} + +macro SPCExecute(ADDR) { // Starts Executing At SPC ADDR X + ldx.w #{ADDR} + stx.w REG_APUIO2 + stz.w REG_APUIO1 + lda.w REG_APUIO0 + clc + adc.b #$22 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCLoadByte() { // Loads Byte A To SPC & Increments X + sta.w REG_APUIO1 + txa // Ready Signal + sta.w REG_APUIO0 + inx // Increment X + WaitAPUIO(0) // Wait For Acknowledgement +} + +macro SPCBeginUpload() { // Starts Upload To SPC ADDR X & Sets X To 0 For Use As Index With SPCLoadByte + stx.w REG_APUIO2 + lda.w REG_APUIO0 // Send Command + clc + adc.b #$22 + bne + // Special Case Fully Verified + inc ++ + sta.w REG_APUIO1 + sta.w REG_APUIO0 + WaitAPUIO(0) // Wait For Acknowledgement + ldx.w #0 // Initialize X Index To 0 +} + +macro TransferBlockSPC(SRC_ADDR, SPC_ADDR, SIZE) { // Transfer A Block Of Data To SPC RAM + ldx.w #{SPC_ADDR} + SPCBeginUpload() +- + lda.l {SRC_ADDR},x + SPCLoadByte() + cpx.w #{SIZE} + bne -- +} + +macro WriteDSP(REG, BYTE) { // Write Byte To SPC-700 DSP Register + ldx.w #REG_DSPADDR // Do A Two Byte Upload To $00F2..$00F3, Setting DSP Register & Data Byte + SPCBeginUpload() + lda.b #{REG} + SPCLoadByte() // DSP REG To $F2 + lda.b #{BYTE} + SPCLoadByte() // DSP DATA To $F3 +} + +macro WriteCTRL(BYTE) { // Write Byte To SPC-700 Control Register + ldx.w #REG_CONTROL // Do A Byte Upload To $00F1, Writing Control Register + SPCBeginUpload() + lda.b #{BYTE} + SPCLoadByte() // Control DATA To $F1 +} + +constant Cs(11) +constant Db(11) +constant D(10) +constant Ds(9) +constant Eb(9) +constant E(8) +constant F(7) +constant Fs(6) +constant Gb(6) +constant G(5) +constant Gs(4) +constant Ab(4) +constant A(3) +constant As(2) +constant Bb(2) +constant B(1) +constant C(0) + +macro SetPitch(voice, note, octave, C9Pitch) { + variable pitch({C9Pitch}) + + if {note} >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if {note} == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + if {note} { + pitch = (pitch >> (8-{octave})) + } + if ! {note} { + pitch = (pitch >> (9-{octave})) + } + + WDSP(DSP_V{voice}PITCHL,pitch & $FF) // Voice X: Pitch (Lower Byte) + WDSP(DSP_V{voice}PITCHH,pitch >> 8) // Voice X: Pitch (Upper Byte) +} + +// Frequency WORD Offsets For Sample Pitch Table +constant HIT($00) + +constant C1($00) +constant C1s($02) +constant D1b($02) +constant D1($04) +constant D1s($06) +constant E1b($06) +constant E1($08) +constant F1($0A) +constant F1s($0C) +constant G1b($0C) +constant G1($0E) +constant G1s($10) +constant A1b($10) +constant A1($12) +constant A1s($14) +constant B1b($14) +constant B1($16) + +constant C2($18) +constant C2s($1A) +constant D2b($1A) +constant D2($1C) +constant D2s($1E) +constant E2b($1E) +constant E2($20) +constant F2($22) +constant F2s($24) +constant G2b($24) +constant G2($26) +constant G2s($28) +constant A2b($28) +constant A2($2A) +constant A2s($2C) +constant B2b($2C) +constant B2($2E) + +constant C3($30) +constant C3s($32) +constant D3b($32) +constant D3($34) +constant D3s($36) +constant E3b($36) +constant E3($38) +constant F3($3A) +constant F3s($3C) +constant G3b($3C) +constant G3($3E) +constant G3s($40) +constant A3b($40) +constant A3($42) +constant A3s($44) +constant B3b($44) +constant B3($46) + +constant C4($48) +constant C4s($4A) +constant D4b($4A) +constant D4($4C) +constant D4s($4E) +constant E4b($4E) +constant E4($50) +constant F4($52) +constant F4s($54) +constant G4b($54) +constant G4($56) +constant G4s($58) +constant A4b($58) +constant A4($5A) +constant A4s($5C) +constant B4b($5C) +constant B4($5E) + +constant C5($60) +constant C5s($62) +constant D5b($62) +constant D5($64) +constant D5s($66) +constant E5b($66) +constant E5($68) +constant F5($6A) +constant F5s($6C) +constant G5b($6C) +constant G5($6E) +constant G5s($70) +constant A5b($70) +constant A5($72) +constant A5s($74) +constant B5b($74) +constant B5($76) + +constant C6($78) +constant C6s($7A) +constant D6b($7A) +constant D6($7C) +constant D6s($7E) +constant E6b($7E) +constant E6($80) +constant F6($82) +constant F6s($84) +constant G6b($84) +constant G6($86) +constant G6s($88) +constant A6b($88) +constant A6($8A) +constant A6s($8C) +constant B6b($8C) +constant B6($8E) + +constant C7($90) +constant C7s($92) +constant D7b($92) +constant D7($94) +constant D7s($96) +constant E7b($96) +constant E7($98) +constant F7($9A) +constant F7s($9C) +constant G7b($9C) +constant G7($9E) +constant G7s($A0) +constant A7b($A0) +constant A7($A2) +constant A7s($A4) +constant B7b($A4) +constant B7($A6) + +constant C8($A8) +constant C8s($AA) +constant D8b($AA) +constant D8($AC) +constant D8s($AE) +constant E8b($AE) +constant E8($B0) +constant F8($B2) +constant F8s($B4) +constant G8b($B4) +constant G8($B6) +constant G8s($B8) +constant A8b($B8) +constant A8($BA) +constant A8s($BC) +constant B8b($BC) +constant B8($BE) + +constant C9($C0) +constant C9s($C2) +constant D9b($C2) +constant D9($C4) +constant D9s($C6) +constant E9b($C6) +constant E9($C8) +constant F9($CA) +constant F9s($CC) +constant G9b($CC) +constant G9($CE) +constant G9s($D0) +constant A9b($D0) +constant A9($D2) +constant A9s($D4) +constant B9b($D4) +constant B9($D6) + +constant SUST($FE) +constant REST($FF) + +macro WritePitchTable(C9Pitch) { // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + variable note(0) + variable octave(0) + + while octave < 10 { + variable pitch({C9Pitch}) + + if note >= 1 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 2 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 3 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 4 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 5 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 6 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 7 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 8 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 9 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note >= 10 { + pitch = ((pitch * 1000000000) / 1059463094) + } + if note == 11 { + pitch = ((pitch * 1000000000) / 1059463094) + } + + pitch = (pitch >> (8-octave)) + + if ! note { + note = 12 + octave = (octave+1) + } + + note = (note-1) + + dw pitch + } +} \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.asm b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.asm new file mode 100644 index 00000000..d8442305 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.asm @@ -0,0 +1,27 @@ +// SNES SPC700 Twinkle Song Demo (CPU Code) by krom (Peter Lemon): +arch snes.cpu +output "Twinkle.sfc", create + +macro seek(variable offset) { + origin ((offset & $7F0000) >> 1) | (offset & $7FFF) + base offset +} + +seek($8000); fill $8000 // Fill Upto $7FFF (Bank 0) With Zero Bytes +include "LIB/SNES.INC" // Include SNES Definitions +include "LIB/SNES_HEADER.ASM" // Include Header & Vector Table +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +seek($8000); Start: + SNES_INIT(SLOWROM) // Run SNES Initialisation Routine + + SPCWaitBoot() // Wait For SPC To Boot + TransferBlockSPC(SPCROM, SPCRAM, SPCROM.size) // Load SPC File To SMP/DSP + SPCExecute(SPCRAM) // Execute SPC At $0200 + +Loop: + jmp Loop + +// SPC Code +// BANK 0 +insert SPCROM, "Twinkle.spc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.sfc b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.sfc new file mode 100644 index 00000000..e781b105 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.sfc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.spc b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.spc new file mode 100644 index 00000000..64c1ad20 Binary files /dev/null and b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle.spc differ diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle_spc.asm b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle_spc.asm new file mode 100644 index 00000000..67bc45a0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/Twinkle_spc.asm @@ -0,0 +1,254 @@ +// SNES SPC700 Twinkle Song Demo (SPC Code) by krom (Peter Lemon): +arch snes.smp +output "Twinkle.spc", create + +macro seek(variable offset) { // Set SPC700 Memory Map + origin (offset - SPCRAM) + base offset +} + +macro ChannelPattern(CHANNEL, VOICE, PITCHTABLE) { // Channel Pattern Calculation + tya // A = Y (Pattern Offset Index) + tax // X = A (Pattern Offset Index) + ldy #{CHANNEL}*2 // Y = CHANNEL * 2 + lda (PATTERNOFS),y // A = Pattern List (LSB) + sta.b PATTERN // Store A To Zero Page RAM + iny // Y++ + lda (PATTERNOFS),y // A = Pattern List (MSB) + sta.b PATTERN+1 // Store A To Zero Page RAM + txa // A = X (Pattern Offset Index) + tay // Y = A (Pattern Offset Index) + + lda (PATTERN),y // A = Pattern Byte + cmp #REST // Compare A To REST Byte ($FE) + beq {#}KEYOFF // IF (A == REST) GOTO Key Off + cmp #SUST // Compare A To SUST Byte ($FD) + beq {#}KEYEND // IF (A == SUST) GOTO Key End + bra {#}KEYON // ELSE GOTO Key On + + {#}KEYOFF: // Key Off + WDSP(DSP_KOFF,1<<{VOICE}) // DSP Register Data = Key Off Flags + bra {#}KEYEND // GOTO Key End + + {#}KEYON: // Key On + tax // X = A (Sample Pitch Table Offset) + str REG_DSPADDR=#DSP_V{VOICE}PITCHL // DSP Register Index = Voice Pitch (LSB) + lda.w {PITCHTABLE},x // A = Voice Pitch (LSB) + sta.b REG_DSPDATA // DSP Register Data = A + + str REG_DSPADDR=#DSP_V{VOICE}PITCHH // DSP Register Index = Voice Pitch (MSB) + inx // X++ (Increment Sample Pitch Table Offset) + lda.w {PITCHTABLE},x // A = Voice Pitch (MSB) + sta.b REG_DSPDATA // DSP Register Data = A + + WDSP(DSP_KOFF,%00000000) // DSP Register Data = Key Off Flags + WDSP(DSP_KON,1<<{VOICE}) // DSP Register Data = Key On Flags + {#}KEYEND: // Key End +} + +include "LIB/SNES_SPC700.INC" // Include SPC700 Definitions & Macros + +// Constants +constant MaxQuant(256) // Maximum Quantization ms +constant PatternSize(8) // Pattern Size (1..256) +constant ChannelCount(7) // Channel Count (1 For Each Sample) + +// Setup Zero Page RAM +constant PATTERN($00) // Pattern Zero Page RAM Address +constant PATTERNOFS($02) // Pattern Offset Zero Page RAM Address + +seek(SPCRAM); Start: + SPC_INIT() // Run SPC700 Initialisation Routine + + WDSP(DSP_DIR,sampleDIR >> 8) // Sample Directory Offset + + WDSP(DSP_KOFF,$00) // Reset Key Off Flags + WDSP(DSP_MVOLL,63) // Master Volume Left + WDSP(DSP_MVOLR,63) // Master Volume Right + + SPCRAMClear($8800,$78) // Clear Echo Buffer RAM + WDSP(DSP_ESA,$88) // Echo Source Address + WDSP(DSP_EDL,15) // Echo Delay + WDSP(DSP_EON,%11111111) // Echo On Flags + WDSP(DSP_FLG,0) // Enable Echo Buffer Writes + WDSP(DSP_EFB,100) // Echo Feedback + WDSP(DSP_FIR0,127) // Echo FIR Filter Coefficient 0 + WDSP(DSP_FIR1,0) // Echo FIR Filter Coefficient 1 + WDSP(DSP_FIR2,0) // Echo FIR Filter Coefficient 2 + WDSP(DSP_FIR3,0) // Echo FIR Filter Coefficient 3 + WDSP(DSP_FIR4,0) // Echo FIR Filter Coefficient 4 + WDSP(DSP_FIR5,0) // Echo FIR Filter Coefficient 5 + WDSP(DSP_FIR6,0) // Echo FIR Filter Coefficient 6 + WDSP(DSP_FIR7,0) // Echo FIR Filter Coefficient 7 + WDSP(DSP_EVOLL,25) // Echo Volume Left + WDSP(DSP_EVOLR,25) // Echo Volume Right + + WDSP(DSP_V0VOLL,25) // Voice 0: Volume Left + WDSP(DSP_V0VOLR,25) // Voice 0: Volume Right + WDSP(DSP_V0SRCN,0) // Voice 0: Harp + WDSP(DSP_V0ADSR1,$FF) // Voice 0: ADSR1 + WDSP(DSP_V0ADSR2,$F0) // Voice 0: ADSR2 + WDSP(DSP_V0GAIN,127) // Voice 0: Gain + + WDSP(DSP_V1VOLL,25) // Voice 1: Volume Left + WDSP(DSP_V1VOLR,25) // Voice 1: Volume Right + WDSP(DSP_V1SRCN,0) // Voice 1: Harp + WDSP(DSP_V1ADSR1,$FF) // Voice 1: ADSR1 + WDSP(DSP_V1ADSR2,$F0) // Voice 1: ADSR2 + WDSP(DSP_V1GAIN,127) // Voice 1: Gain + + WDSP(DSP_V2VOLL,25) // Voice 2: Volume Left + WDSP(DSP_V2VOLR,25) // Voice 2: Volume Right + WDSP(DSP_V2SRCN,0) // Voice 2: Harp + WDSP(DSP_V2ADSR1,$FF) // Voice 2: ADSR1 + WDSP(DSP_V2ADSR2,$F0) // Voice 2: ADSR2 + WDSP(DSP_V2GAIN,127) // Voice 2: Gain + + WDSP(DSP_V3VOLL,25) // Voice 3: Volume Left + WDSP(DSP_V3VOLR,25) // Voice 3: Volume Right + WDSP(DSP_V3SRCN,0) // Voice 3: Harp + WDSP(DSP_V3ADSR1,$FF) // Voice 3: ADSR1 + WDSP(DSP_V3ADSR2,$F0) // Voice 3: ADSR2 + WDSP(DSP_V3GAIN,127) // Voice 3: Gain + + WDSP(DSP_V4VOLL,25) // Voice 4: Volume Left + WDSP(DSP_V4VOLR,25) // Voice 4: Volume Right + WDSP(DSP_V4SRCN,0) // Voice 4: Harp + WDSP(DSP_V4ADSR1,$FF) // Voice 4: ADSR1 + WDSP(DSP_V4ADSR2,$F0) // Voice 4: ADSR2 + WDSP(DSP_V4GAIN,127) // Voice 4: Gain + + WDSP(DSP_V5VOLL,25) // Voice 5: Volume Left + WDSP(DSP_V5VOLR,25) // Voice 5: Volume Right + WDSP(DSP_V5SRCN,0) // Voice 5: Harp + WDSP(DSP_V5ADSR1,$FF) // Voice 5: ADSR1 + WDSP(DSP_V5ADSR2,$F0) // Voice 5: ADSR2 + WDSP(DSP_V5GAIN,127) // Voice 5: Gain + + WDSP(DSP_V6VOLL,25) // Voice 6: Volume Left + WDSP(DSP_V6VOLR,25) // Voice 6: Volume Right + WDSP(DSP_V6SRCN,0) // Voice 6: Harp + WDSP(DSP_V6ADSR1,$FF) // Voice 6: ADSR1 + WDSP(DSP_V6ADSR2,$F0) // Voice 6: ADSR2 + WDSP(DSP_V6GAIN,127) // Voice 6: Gain + +StartSong: + lda #PATTERNLIST // A = Pattern List (LSB) + ldy #PATTERNLIST>>8 // Y = Pattern List (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + ldy #0 // Y = 0 (Pattern Offset Index) + +LoopSong: + ChannelPattern(0, 0, HarpPitchTable) // Channel 1 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(1, 1, HarpPitchTable) // Channel 2 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(2, 2, HarpPitchTable) // Channel 3 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(3, 3, HarpPitchTable) // Channel 4 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(4, 4, HarpPitchTable) // Channel 5 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(5, 5, HarpPitchTable) // Channel 6 Pattern Calculation: Channel, Voice, Pitch Table + ChannelPattern(6, 6, HarpPitchTable) // Channel 7 Pattern Calculation: Channel, Voice, Pitch Table + + // Wait For MilliSecond Amount (8kHz Timer) + lda #MaxQuant // Granularity = 1ms, Max Wait = 256ms + str REG_T0DIV=#8 // 8kHz Clock Divider 8 = 1024 Clock Ticks (1ms) + str REG_CONTROL=#$01 + WaitMS: + bbc REG_T0OUT:0=WaitMS // IF (REG_T0OUT.BIT0 == 0) Wait For Timer + dec // A-- + bne WaitMS // IF (A != 0) Loop Timer Wait + + iny // Increment Pattern Index Offset + cpy #PatternSize // Compare Y To Pattern Size + beq PatternIncrement // IF (Y == Pattern Size) Pattern Increment + jmp PatternEnd // ELSE Pattern End + + PatternIncrement: // Channel 1..8 Pattern Increment + ldy #0 // Y = 0 + lda #ChannelCount * 2 // YA = Channel Count * 2 + adw PATTERNOFS // YA += Pattern Offset + stw PATTERNOFS // Pattern Offset = YA + + // Compare Pattern List End Address + lda #PATTERNLISTEND // A = Pattern List End (LSB) + ldy #PATTERNLISTEND>>8 // Y = Pattern List End (MSB) + cpw PATTERNOFS // Compare YA To Zero Page RAM + bne PatternIncEnd // IF (Pattern Offset != Pattern List End Offset) Pattern Increment End, ELSE Set Pattern Loop Offset + + // Set Pattern Loop Offset + lda #PATTERNLISTLOOP // A = Pattern List Loop (LSB) + ldy #PATTERNLISTLOOP>>8 // Y = Pattern List Loop (MSB) + stw PATTERNOFS // Store YA To Zero Page RAM + + PatternIncEnd: + ldy #0 // Y = 0 (Pattern Index Offset) + + PatternEnd: + jmp LoopSong // GOTO Loop Song + +HarpPitchTable: + WritePitchTable($C900) // Write Sample Pitch Table From C9 Pitch, 9 Octaves: C1..B9 (108 Words) + +PATTERN00: // Pattern 00: Harp (Channel 1) + db C5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN01: // Pattern 01: Harp (Channel 1) + db F5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN02: // Pattern 02: Harp (Channel 1) + db G5, SUST, SUST, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN03: // Pattern 03: Harp (Channel 2) + db SUST, C5, SUST, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN04: // Pattern 04: Harp (Channel 2) + db SUST, F5, SUST, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN05: // Pattern 05: Harp (Channel 2) + db SUST, G5, SUST, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN06: // Pattern 06: Harp (Channel 3) + db SUST, SUST, G5, SUST, SUST, SUST, SUST, SUST // 1 +PATTERN07: // Pattern 07: Harp (Channel 3) + db SUST, SUST, E5, SUST, SUST, SUST, SUST, SUST // 2 +PATTERN08: // Pattern 08: Harp (Channel 3) + db SUST, SUST, F5, SUST, SUST, SUST, SUST, SUST // 3 + +PATTERN09: // Pattern 09: Harp (Channel 4) + db SUST, SUST, SUST, G5, SUST, SUST, SUST, SUST // 1 +PATTERN10: // Pattern 10: Harp (Channel 4) + db SUST, SUST, SUST, E5, SUST, SUST, SUST, SUST // 2 +PATTERN11: // Pattern 11: Harp (Channel 4) + db SUST, SUST, SUST, F5, SUST, SUST, SUST, SUST // 3 + +PATTERN12: // Pattern 12: Harp (Channel 5) + db SUST, SUST, SUST, SUST, A5, SUST, SUST, SUST // 1 +PATTERN13: // Pattern 13: Harp (Channel 5) + db SUST, SUST, SUST, SUST, D5, SUST, SUST, SUST // 2 +PATTERN14: // Pattern 14: Harp (Channel 5) + db SUST, SUST, SUST, SUST, E5, SUST, SUST, SUST // 3 + +PATTERN15: // Pattern 15: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, A5, SUST, SUST // 1 +PATTERN16: // Pattern 16: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, D5, SUST, SUST // 2 +PATTERN17: // Pattern 17: Harp (Channel 6) + db SUST, SUST, SUST, SUST, SUST, E5, SUST, SUST // 3 + +PATTERN18: // Pattern 18: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, G5, SUST // 1 +PATTERN19: // Pattern 19: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, C5, SUST // 2 +PATTERN20: // Pattern 20: Harp (Channel 7) + db SUST, SUST, SUST, SUST, SUST, SUST, D5, SUST // 3 + +PATTERNLIST: +PATTERNLISTLOOP: + dw PATTERN00,PATTERN03,PATTERN06,PATTERN09,PATTERN12,PATTERN15,PATTERN18 // Channel 1..7 Pattern Address List + dw PATTERN01,PATTERN04,PATTERN07,PATTERN10,PATTERN13,PATTERN16,PATTERN19 // Channel 1..7 Pattern Address List + dw PATTERN02,PATTERN05,PATTERN08,PATTERN11,PATTERN14,PATTERN17,PATTERN20 // Channel 1..7 Pattern Address List + dw PATTERN02,PATTERN05,PATTERN08,PATTERN11,PATTERN14,PATTERN17,PATTERN20 // Channel 1..7 Pattern Address List + dw PATTERN00,PATTERN03,PATTERN06,PATTERN09,PATTERN12,PATTERN15,PATTERN18 // Channel 1..7 Pattern Address List + dw PATTERN01,PATTERN04,PATTERN07,PATTERN10,PATTERN13,PATTERN16,PATTERN19 // Channel 1..7 Pattern Address List +PATTERNLISTEND: + +seek($0A00); sampleDIR: + dw Harp, Harp + 927 // 0 + +seek($0B00) // Sample Data + insert Harp, "BRR/034. Harp (Loop=927,AD=$FF,SR=$F0,Echo)(C9Freq=$C900).brr" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/SPC700/Twinkle/make.bat b/roms/snes/peter-lemon-snes/SPC700/Twinkle/make.bat new file mode 100644 index 00000000..405f609b --- /dev/null +++ b/roms/snes/peter-lemon-snes/SPC700/Twinkle/make.bat @@ -0,0 +1,2 @@ +bass Twinkle_spc.asm +bass Twinkle.asm \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.asm b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.asm new file mode 100644 index 00000000..aa50a68f --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.asm @@ -0,0 +1,819 @@ +// SNES "Albert Odyssey" Japanese To English Translation by krom (Peter Lemon): + +output "Albert Odyssey.sfc", create +origin $00000; insert "Albert Odyssey (J).sfc" // Include Japanese Albert Odyssey SNES ROM +origin $007FC0 +db "ALBERT ODYSSEY ENG " // $007FC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +// Char Table 1 +map '0', $00, 10 +map 'A', $0A, 26 +map '?', $24 +map '!', $25 +map '-', $26 +map '/', $27 +map ' ', $28 +map '[', $C1 +map ']', $C2 +map '.', $C3 +map $2C, $C4 // map ',', $C4 +map ':', $D6 +map '$', $F6 + +// Char Table 2 +map '+', $18 +map '>', $31 +map '%', $35 + +// Text Type +constant TextType0(%00000000) +constant TextType1(%00100000) +constant TextType2(%01000000) +constant TextType3(%01100000) +constant TextType4(%10000000) +constant TextType5(%10100000) +constant TextType6(%11000000) +constant TextType7(%11100000) + +macro TextStyle1(OFFSET, TEXT) { + origin {OFFSET} // Offset + variable labeloffset(+) + db labeloffset - {OFFSET} - 2 // Length + db {TEXT} // Text + + +} + +macro TextStyle2(OFFSET, TEXT, TYPE) { + origin {OFFSET} // Offset + variable labeloffset(+) + db ((labeloffset - {OFFSET} - 2) / 2) | {TYPE} // Length (Bits 4:0 = Length, 7:5 = Text Type) + db {TEXT} // Text (2 Bytes Per Character, Byte1 = Text Char, Byte2 = Char Table / Colour) + + +} + +macro TextStyle3(OFFSET, TEXT, TYPE, ASCIIOFFSET, LOWEROFFSET) { + origin {OFFSET} // Upper Offset + variable TEXTCHAR({TEXT} - {ASCIIOFFSET}) + TEXTCHAR = TEXTCHAR + ($10 * (TEXTCHAR / 16)) + db TEXTCHAR // Upper Text + db {TYPE} // Upper Type + + origin {OFFSET} + {LOWEROFFSET} // Lower Offset + db TEXTCHAR + $10 // Lower Text + db {TYPE} // Lower Type +} + +macro TextStyle4(OFFSET, TEXT, TYPE, ASCIIOFFSET) { + origin {OFFSET} // Upper Offset + variable TEXTCHAR({TEXT} - {ASCIIOFFSET}) + TEXTCHAR = TEXTCHAR + ($10 * (TEXTCHAR / 16)) + db TEXTCHAR // Upper Text + db {TYPE} // Upper Type +} + +macro TextStyle5(OFFSET, TEXT) { + origin {OFFSET} // Offset + db {TEXT} // Text +} + +// Intro +TextStyle1($43ABC, " ALBERT - ODYSSEY ") + +TextStyle1($43911, "THE MAGE OSWALD INVADED") +TextStyle1($43D09, "SEEKING THE CRYSTAL KEY,") + +TextStyle1($43D22, "USING HIS POWERS AGAINST") +TextStyle1($43D3B, "THE BRAVE KNIGHTS.") + +TextStyle1($4454F, "KNIGHTS OF GORT - LAST STAND.") + +TextStyle2($41E3A, "K4N4I4G4H4T4:4 0O0H0 0N0O0.0.0.0 0I0M0P0O0S0S0I0B0L0E0!0", TextType7) + +TextStyle1($43929, "KNIGHT1: CAPTAIN SLAY!") + +TextStyle1($43946, "SLAY:WHY ARE YOU ALONE?") + +TextStyle1($43965, "KNIGHT1:ALL OUR FORCES HAVE") +TextStyle1($4398C, "BEEN WIPED OUT!") + +TextStyle1($43F8A, "SLAY: GENERAL!!") + +TextStyle1($4399D, "GENERAL: HAS") +TextStyle1($439AA, "IT COME TO THIS?!") + +TextStyle1($43D4E, "KNIGHT2:GENERAL! LET US GO!") + +TextStyle1($43D73, "KNIGHT3: IN OUR NAME!") + +TextStyle1($439BC, "GENERAL: OK! LETS GO!") + +TextStyle1($439DF, "SOFIA: DADDY...") + +TextStyle1($439F2, "MUM: MY DEAR...") + +TextStyle1($43AA5, "GENERAL: DO NOT WORRY!") +TextStyle1($43A03, "LOOK AFTER SOFIA.") + +TextStyle1($43A15, "SOFIA: NO! PLEASE DONT GO!") +TextStyle1($43A65, " DADDY!") + +TextStyle2($43AD1, "SCLCACYC:C 0H0E0R0E0 0I0 0G0O0!0!0", TextType7) + +TextStyle2($43AF4, "SCLCACYC:C 0W0E0R0E0 0L0O0S0I0N0G0 0T0H0E0 0B0A0T0T0L0E0.0.0.0", TextType7) + +TextStyle2($43B33, "SCLCACYC:CG0E0N0E0R0A0L0!0W0E0 0C0A0N0T0 0G0O0 0O0N0!0", TextType7) + +TextStyle2($43B6A, "G8E8N8E8R8A8L8:8 0Y0O0U0 0O0K0?0!0", TextType7) + +TextStyle2($43B8D, "SCLCACYC:C 0W0E0 0M0U0S0T0 0R0E0T0R0E0A0T0 0N0O0W0!0", TextType7) + +TextStyle2($43BC2, "SCLCACYC:C 0G0E0N0E0R0A0L0!0", TextType7) + +TextStyle2($43BDF, "G8E8N8E8R8A8L8:8 0E0V0A0C0U0A0T0E0 0T0H0E0 0V0I0L0L0A0G0E0!0", TextType7) + +TextStyle2($43C1C, "SCLCACYC:CC0O0M0E0 0B0A0C0K0,0F0O0R0 0S0O0F0I0A0!0", TextType7) + +TextStyle2($43C4F, "SCLCACYC:CC0A0N0T0 0W0I0N0,0L0E0T0S0 0G0O0 0B0A0C0K0.0", TextType7) + +TextStyle2($43C86, "K4N4I4G4H4T4:4M0U0S0T0 0E0V0A0C0U0A0T0E0 0V0I0L0L0A0G0E0R0S0!0", TextType7) + +TextStyle1($43A3E, "SOFIA: WHERES MY DADDY?") + +TextStyle2($43A90, "SCLCACYC:C 0.0.0.0.0", TextType7) + +TextStyle1($43CC5, "SOFIA:WHERE ARE YOU...?") + +TextStyle1($43D9A, "OSWALD:CRYSTAL?") + +TextStyle1($43DB9, "OSWALD:YOU POSSESS MAGIC...") + +TextStyle2($43CE8, "SCOCFCICAC:C 0M0U0M0-0-0-0M0Y0!0", TextType7) + +TextStyle1($43E46, "SOFIA: GIVE BACK MY MUMMY!") + +TextStyle1($438FC, "---10 YEARS LATER---") + + +// Intro Characters Names +TextStyle1($40CE6, "KNIGHT") +TextStyle1($40CF3, "SLAY") +TextStyle1($40F8E, "GN") + +// Playable Characters Names +TextStyle1($40C6B, "ALBERT") +TextStyle1($413BD, "NEUMANN") +TextStyle1($40C82, "SOFIA") + +// Boss Monster Names +TextStyle1($40CBA, "GOLM") +TextStyle1($418D0, "LO.DEMON") +TextStyle1($43A8B, "HARP") + +// Normal Monster Names +TextStyle1($40C9E, "SKELT") +TextStyle1($40CAC, "ROPE") +TextStyle1($40CDB, "GARGO") +TextStyle1($40CE1, "GOBL") +TextStyle1($4189A, "FRUBAT") +TextStyle1($418A6, "LIZMAN") +TextStyle1($418AD, "DRAG") +TextStyle1($47A25, "REDROPE") +TextStyle1($47A33, "SKULLC") + +// Location Names +TextStyle1($41983, "CHIB") +TextStyle1($41988, "GRT") +TextStyle1($41997, "NEURA") + +// Equipment +TextStyle5($40FE5, "H0E0R0O0") +TextStyle5($416FD, "W0I0Z0A0R0D0") +TextStyle5($417B9, "V0I0C0A0R0") +TextStyle5($416E8, "CLOTH") +TextStyle5($416F2, "COPPER") +TextStyle5($4170E, "SPR") +TextStyle5($41716, "CLUB") +TextStyle5($41728, "SHORT ") +TextStyle5($41734, "DAG") +TextStyle5($4173C, "LARGE ") +TextStyle5($41748, "BUCKL") +origin $4174D ; db $49,$00,$01,$76,$77 ; TextStyle5($41752, "CHAIN ") +TextStyle5($4175F, "LARGE") +TextStyle5($4178E, "HLM") +TextStyle5($417C8, "CAP") +TextStyle5($417D0, "LEATH") +TextStyle5($417DA, "RUBBER") +TextStyle5($41861, "LEATH") + +// Items +TextStyle1($4100E, "EGG") +TextStyle1($412EA, "DAYLIGHT") +TextStyle1($416DB, "GRTWARP") +TextStyle1($41764, "GL.HEAD") +TextStyle1($4176C, "LETTR") +TextStyle1($41772, "NEURAWARP") +TextStyle1($417A2, "SHADOW") +TextStyle1($4183D, "HERB") +TextStyle1($41842, "AWAKEN") +TextStyle1($4184A, "CHIBWARP") +TextStyle1($41853, "ODDFRUIT") + +TextStyle1($438A4, "TO:") +TextStyle1($438A8, "SELL?") +TextStyle1($438AE, "BUY?") + + +// Exit Town +TextStyle1($40DE5, "GO OUTSIDE?") +TextStyle2($40DF8, "YCECSC 0-0 0 CAC", TextType7) + + +// Battle Selection: +TextStyle1($410DF, "MOVE") +TextStyle1($40C5C, " HIT") +TextStyle1($40C61, "ENDGO") + +// Albert Battle Selection +TextStyle1($479A7, "PSYK") + +// Neumann & Sofia Battle Selection: +TextStyle1($40CBF, "CAST") + +// Movement Text +TextStyle2($41950, "MOOOVOEO", TextType7) +TextStyle1($4106C, "PROCESSING") +TextStyle3($4E8AF, 'S', $20, $37, $6) ; TextStyle3($4E8BB, 'T', $20, $37, $6) ; TextStyle3($4E8C7, 'P', $20, $37, $6) ; TextStyle3($4E8D3, $D6, $21, $00, $6) + +// Attack Text +TextStyle2($41962, " OHOIOTO", TextType7) +TextStyle1($41098, "NO ONE NEAR") +TextStyle1($413C5, "TO: TARGET") +TextStyle1($4108C, "EMPTY SPACE") + +// Exit Action Text +TextStyle2($41959, "EONODOSO", TextType7) +TextStyle2($41035, "C8A8N8C8E8L8", TextType7) +TextStyle1($40CD0, "TURN ENDED") +TextStyle1($463CE, "ENDOF TURN?") +TextStyle1($40E35, "YES-A NO-B BUTTON") +TextStyle2($410A4, "V0I0E0W0", TextType7) + + +// Albert Transformations +TextStyle2($40C74, "T8A8R8G8", TextType7) +TextStyle2($41077, " 8S8E8T8S0E0L0E0C0T0", TextType7) +TextStyle2($410AD, "E8T8 0E0M0P0T0Y0", TextType7) + +// Neumann Magic +TextStyle2($479C5, "WOMOAOGOIOCO", TextType7) +TextStyle1($479B9, "CURE") +TextStyle1($444E6, "WHO WILL YOU CURE?") +TextStyle1($479BE, "LIF") +TextStyle1($479C2, "HL") +TextStyle1($44693, "WHO?") + +// Sofia Magic +TextStyle2($41347, "BOLO", TextType7) +TextStyle2($4196B, "BOLOCOKO", TextType7) +TextStyle1($479D8, "LIT") +TextStyle1($479DC, "FIRE") +TextStyle1($479E2, "WARP") +TextStyle1($4468E, "TO ?") + + +// Boss Monster Magic +TextStyle1($418E0, "SHOC") // Golem +TextStyle2($418E7, "SOHOOOCO", TextType7) + + +// Battle Messages +TextStyle3($14E62, 'H', $20, $37, $9) ; TextStyle3($14EAF, 'P', $20, $37, $9) ; TextStyle3($14EFC, $D6, $21, $00, $9) +TextStyle3($14DFE, 'A', $20, $37, $9) ; TextStyle3($14E17, 'R', $20, $37, $9) ; TextStyle3($14E30, 'E', $20, $37, $9) ; TextStyle3($14E49, 'A', $20, $37, $9) +TextStyle3($14F5B, 'F', $20, $37, $9) ; TextStyle3($14F74, 'O', $20, $37, $9) ; TextStyle3($14F8D, 'C', $20, $37, $9) ; TextStyle3($14FA6, 'U', $20, $37, $9) ; TextStyle3($14FBF, 'S', $20, $37, $9) + +TextStyle2($444D4, "+1 0$8:0", TextType7) +TextStyle1($444DD, "RECEIVED") +TextStyle1($446B4, " :") +TextStyle1($446B7, "SEIZED!") +TextStyle1($44538, "HAS DIED.") +TextStyle1($446BF, "IS STONE...") +TextStyle1($446CB, "STONE..") +TextStyle1($47B19, "IS STONE") +TextStyle1($47F51, "STONE GONE!") + + +// Map Messages +TextStyle3($4E69E, 'X', $20, $37, $6) +TextStyle3($4E711, 'Y', $20, $37, $6) +TextStyle2($40E20, "M8A8P8 8V8I8E8W8", TextType7) + +// Map Terrain Types +TextStyle4($4E605, 'T', $20, $37) ; TextStyle4($4E612, 'P', $20, $37) ; TextStyle4($4E61F, $D6, $21, $00) + +TextStyle4($00A24, 'L', $24, $37) ; TextStyle4($00A26, 'A', $24, $37) ; TextStyle4($00A28, 'N', $24, $37) ; TextStyle4($00A2A, 'D', $24, $37) +TextStyle4($00A2C, 'W', $24, $37) ; TextStyle4($00A2E, 'O', $24, $37) ; TextStyle4($00A30, 'O', $24, $37) ; TextStyle4($00A32, 'D', $24, $37) +TextStyle4($00A34, 'S', $24, $37) ; TextStyle4($00A36, 'A', $24, $37) ; TextStyle4($00A38, 'N', $24, $37) ; TextStyle4($00A3A, 'D', $24, $37) +TextStyle4($00A44, 'R', $24, $37) ; TextStyle4($00A46, 'O', $24, $37) ; TextStyle4($00A48, 'A', $24, $37) ; TextStyle4($00A4A, 'D', $24, $37) +TextStyle4($00A4C, 'R', $24, $37) ; TextStyle4($00A4E, 'O', $24, $37) ; TextStyle4($00A50, 'C', $24, $37) ; TextStyle4($00A52, 'K', $24, $37) +TextStyle4($00A64, 'S', $24, $37) ; TextStyle4($00A66, 'E', $24, $37) ; TextStyle4($00A68, 'A', $24, $37) + +TextStyle3($4E789, 'R', $28, $37, $6) ; TextStyle3($4E795, 'A', $28, $37, $6) ; TextStyle3($4E7A1, 'T', $28, $37, $6) ; TextStyle3($4E7AD, 'I', $28, $37, $6) ; TextStyle3($4E7B9, 'O', $28, $37, $6) + +// Map Monster Status +TextStyle1($40E47, "ENEMY") + + +// Status - Messages +TextStyle3($27639, 'D', $28, $37, $6) ; TextStyle3($27645, 'E', $28, $37, $6) ; TextStyle3($27651, 'A', $28, $37, $6) ; TextStyle3($2765D, 'T', $28, $37, $6) ; TextStyle3($27669, 'H', $28, $37, $6) +TextStyle3($2767A, 'S', $28, $37, $6) ; TextStyle3($27686, 'T', $28, $37, $6) + +// Status - Item +TextStyle3($4EA49, 'E', $20, $37, $6) ; TextStyle3($4EA55, 'Q', $20, $37, $6) ; TextStyle3($4EA61, $18, $22, $00, $6) + +// Status - Time +TextStyle4($249A5, 'P', $20, $37) +TextStyle4($249BC, 'A', $20, $37) ; TextStyle4($249C9, 'M', $20, $37) ; TextStyle4($249D6, $28, $20, $00) +TextStyle3($24A14, 'H', $20, $37, $6) + + +// Start Screen +TextStyle3($10EBB, $28, $20, $00, $6) ; TextStyle3($10EC7, 'H', $20, $37, $6) ; TextStyle3($10ED3, 'P', $20, $37, $6) +TextStyle3($17A39, 'O', $28, $37, $6) ; TextStyle3($17A45, 'K', $28, $37, $6) +TextStyle1($41699, "EQUI") +TextStyle2($416A0, "RCHC 0:0", TextType7) +TextStyle2($416A9, "LCHC 0:0", TextType7) +TextStyle2($416B2, "ACRCMC:0", TextType7) +TextStyle2($416BB, "LCECGC:0", TextType7) +TextStyle2($416C4, "BCDCYC:0", TextType7) +TextStyle2($416CD, "HCDC 0:0", TextType7) +TextStyle1($40C7D, "ATP:") +TextStyle1($416D6, "DFP:") +TextStyle3($17EA5, 'S', $20, $37, $6) ; TextStyle3($17EB1, 'T', $20, $37, $6) ; TextStyle3($17EBD, 'P', $20, $37, $6) + + +// Chiberus - Start Of Game +TextStyle2($44619, "MCUCMC:CW0A0N0T0 0T0O0 0H0E0A0R0 0T0H0E0 0S0T0O0R0Y0?0", TextType7) +TextStyle1($4379B, " OK") +TextStyle1($4379F, " NO") + +TextStyle1($44674, "SEEKING TO REVIVE GLOBUS.") + +TextStyle1($44650, "TOMORROW YOURE") +TextStyle1($4465F, "16,YOU MUST REST UP.") + +TextStyle1($43E1F, "PRIEST:OH NO!WHOS THIS?") + +TextStyle1($43EA9, "---THE NEXT DAY---") + +TextStyle2($43E65, "MCUCMC:C 0W0A0K0E0 0U0P0.0.0.0", TextType7) + +TextStyle2($41C7B, "MCUCMC:C 0N0O0W0 0Y0O0U0 0A0R0E0 01060", TextType7) + +TextStyle1($41CA4, "YOU INHERIT THE HERO") +TextStyle1($43E99, "SWORD HEIRLOOM.") + +TextStyle2($43DF0, "MCUCMC:C 0H0E0R0E0S0 0$010000000 0I0 0H0A0V0E0", TextType7) +TextStyle1($43E84, "BEEN SAVING FOR YOU.") + +TextStyle1($43EBC, "I THINK YOU WILL") +TextStyle1($43ECD, "MAKE A FINE HERO!") + +TextStyle1($43810, "WARM!!") + +TextStyle1($43EDF, "NEUMANN:GOOD MORNING!ALBERT") +TextStyle1($43F0E, "A BARD IS IN THE PLAZA.") + +TextStyle1($43F26, "WHAT?") +TextStyle1($43F2C, " SEEMS LIKE FUN") +TextStyle1($43F3C, " PASS") + +TextStyle1($43F42, "ALBERT: OK LETS GO NEUMANN") + +TextStyle1($43F63, "NEUMANN:OH ALBERT, COME ON!") + +TextStyle1($41B59, "WAR AGAINST THE MAGE GLOBUS") +TextStyle1($41B76, "WHO RULED THE WORLD") + +TextStyle1($41B8A, "SEEMED TO NEVER END..") + +TextStyle1($41BA0, "GORT BEGAN TO REALIZE") +TextStyle1($41BB6, "A CRYSTAL GAVE HIM POWER") + +TextStyle1($41BCF, "TOOK IT FROM GLOBUS") +TextStyle1($41BE3, "AND DEFEATED HIM") + +TextStyle1($41BF4, "SEALING HIS SPIRIT DEEP") +TextStyle1($41C0C, "UNDERGROUND") + +TextStyle1($45F4A, "PEACE CAME,") +TextStyle1($41C18, "TO THE LAND ONCE MORE") + +TextStyle1($41C2E, "THE PRIEST WANTED") +TextStyle1($41C40, "TO SEE YOU") + +TextStyle1($41C4B, "ALBERT: ALL RIGHT") +TextStyle1($41C62, "NEUMANN: THANKS") + +TextStyle2($41CB9, "PCRCICECSCTC:CP0L0E0A0S0E0 0L0I0S0T0E0N0", TextType7) +TextStyle1($41CE2, "TO MY STORY CLOSELY ALBERT") + +TextStyle2($41F1A, "SCOCFCICAC:C 0I0M0 0A0 0M0A0G0E0 0F0R0O0M0 0G0O0R0T0", TextType7) + +TextStyle1($41F4F, "MONSTERS ARE SPRINGING UP") +TextStyle1($41F69, "ALL OVER THE WORLD.") + +TextStyle1($41F7D, "I WAS ATTACKED COMING HERE") + +TextStyle1($41F98, "OSWALD HAS REVIVED AFTER") +TextStyle1($41FB1, "10 YEARS OF PEACE.") + +TextStyle1($41FC4, "WE MUST TELL THE KING THIS") + +TextStyle1($41FDF, "WILL YOU JOIN ME TO GORT?") +TextStyle1($41CFD, " YES ") +TextStyle1($41D03, " NO ") + +TextStyle1($41FF9, "THANK YOU..") + +TextStyle1($42005, "I WILL NEED YOUR HELP.") + +TextStyle1($442B8, "ONE MORE THING TO SAY,") + +TextStyle1($442CF, "THE LIGHT 10 YEARS AGO,") + +TextStyle1($442E7, "I WITNESSED IT MYSELF.") + +TextStyle1($442FE, "I SUMMONED IT.") + +TextStyle1($4430D, "I LOST THAT STRANGE POWER") + +TextStyle1($44327, "ITS INEVITABLE THAT OSWALD") +TextStyle1($44342, "WILL LOOK FOR ME") + +TextStyle1($44353, "ILL ASK YOU TO KEEP THIS") +TextStyle1($4436C, "AS A SECRET") + +TextStyle2($41DA8, "SCOCFCICAC:C 0I0 0A0M0 0W0E0L0L0 0N0O0W0", TextType7) + +TextStyle2($41DD1, "PCRCICECSCTC:C 0T0A0K0E0 0C0A0R0E0 0O0F0 0S0O0F0I0A0", TextType7) +TextStyle1($41E06, "ALBERT,NEUMANN I THINK YOU") +TextStyle1($41E21, "WILL BECOME A GREAT MONK") + + +// Chiberus - Outside +TextStyle1($41D08, "MONSTERS ARE GETTING") +TextStyle1($41D1D, "TOUGH OUTSIDE.") + +TextStyle1($41D2C, "I AM TAKING WEAPONS TO GORT") + +TextStyle1($41EB5, "IT WAS GOOD TO HEAR THE") +TextStyle1($41ECD, "MUSIC") + +TextStyle1($41D70, "GORT IS NORTHEAST OF HERE") + +TextStyle1($41D8A, "EQUIP YOURSELF IF TRAVELING") + +TextStyle1($41D48, "RECORD YOUR PROGRESS TO") +TextStyle1($41D60, "A SAVE DATA LOG") +TextStyle1($44453, "IF YOU STOP THE ADVENTURE") + +TextStyle1($41E79, "A GHOST COMES OUT AT NIGHT") + +TextStyle1($41E73, "CLUK!") + +TextStyle1($4439A, "I WAS BEATEN BY OSWALD..") + +TextStyle1($41E94, "FIND ME") + +TextStyle1($443B3, "I GOT SICK BEFORE THE GREAT") +TextStyle1($443CF, "BATTLE WITH THE KNIGHTS.") + + +// Chiberus - Inn +TextStyle1($43781, "REST, IF YOU ARE TIRED...") +TextStyle1($47B80, " BED") +TextStyle1($47B85, " SAVE") + +TextStyle1($437A4, "IT WILL BE") +TextStyle1($437AF, "$10 TO STAY.") + +TextStyle1($47B8D, "RECORDING SAVE DATA...") + +TextStyle1($4388D, "STAY") +TextStyle1($43892, "ANYTIME YOU WANT.") + +TextStyle1($4443C, "RECORD A DATA LOG?") +TextStyle1($438E8, "OK") +TextStyle1($4444F, "NO") + +TextStyle1($4407F, "L,R: CHANGES ORDER OF PARTY") + +TextStyle1($4429E, "MY JOURNEY HERE WAS HARD.") + +TextStyle1($440DF, "B: USED TO CANCEL COMMANDS!") + +TextStyle1($4425B, "I WAS WORRIED FOR SOFIA") +TextStyle1($44273, "WHEN SHE CAME FROM GORT") + + +// Chiberus - Item Shop +TextStyle1($4375A, "ITEM SHOP.HOW CAN I HELP") +TextStyle1($43773, " BUY") +TextStyle1($4377A, " SELL") + +TextStyle1($437D9, "WHAT WOULD YOU LIKE") +TextStyle1($437FF, "TO PURCHASE NOW?") + +TextStyle1($437CC, "LETS LOOK AT") +TextStyle1($437ED, "YOUR ITEMS VALUES") + +TextStyle1($4387C, "COME AGAIN SOON.") + +TextStyle1($43FAD, "CHIBWARP TELEPORTS YOU BACK") + +TextStyle1($4428B, "AN EGG IS TWICE AS") +TextStyle1($444AD, "STRONG AS A MEDICINAL HERB!") + +TextStyle1($43FCB, "THE") +TextStyle1($43FCF, "KNIGHTS OF GORT HAD BATTLED") +TextStyle1($43FEB, "COURAGEOUSLY AGAINST") +TextStyle1($44000, "EVIL OSWALD") + +TextStyle1($443E8, "BOO!ALWAYS BE READY.") + + +// Chiberus - Barn Above Inn +TextStyle1($440FD, "BUTTON") +TextStyle1($44104, "X:ZOOM OUT MAP TO SEE AHEAD") + +TextStyle1($44124, "START: WILL SELECT") +TextStyle1($44137, "MEMBERS TO EQUIP!") + + +// Chiberus - Alberts House +TextStyle1($41E9C, "KEEP TRYING YOUR HARDEST") + + +// Chiberus - Middle House +TextStyle1($4409B, "BEAT ENEMIES TO") +TextStyle1($440AB, "OBTAIN CASH AND ITEMS") + +TextStyle1($44199, "TERRAIN TYPES AFFECT DAMAGE") +TextStyle1($441B8, "STRENGTH") + +TextStyle1($44899, "SHOPS BUY AT A FRACTION OF") +TextStyle1($448B4, "THE RETAIL PRICES FOR ITEMS") + +TextStyle1($44149, "CIVILIZATION IMPROVED") +TextStyle1($4415F, "BUT PEOPLE HAD A HARD TIME.") + +TextStyle1($44038, "THE CRYSTAL WAS") +TextStyle1($44048, "KEY TO OUR REVIVAL") +TextStyle1($4405B, "OUR CIVILIZATION IS") +TextStyle1($4406F, "IN AN EVIL GRIP") + +TextStyle1($441E1, "10 YEARS AGO, AT THE BATTLE") +TextStyle1($441FD, "OSWALD WAS BLASTED AWAY") +TextStyle1($44215, "BY BRIGHT LIGHT FROM SOFIA.") +TextStyle1($44231, "SLAY OF GORT HAS TAKEN CARE") +TextStyle1($4424D, "OF HER SINCE.") + + +// Chiberus - Bottom House +TextStyle1($43F9D, "KNOW ODDFRUIT?") + +TextStyle1($44751, "IF USED IN A TOWN IT") +TextStyle1($47A09, "MAKES IT NIGHT TIME") + +TextStyle1($44766, "WHAT A LONG DAY IT IS!") + +TextStyle1($4400C, "WHAT WAS THE LIGHT ABOUT") + +TextStyle1($440C1, "AT NIGHT FOES ARE MORE") +TextStyle1($440D8, "STRONG") + +TextStyle1($44025, "OSWALD HAS REVIVED") + +TextStyle1($4417B, "REAR ATTACKS ARE EFFECTIVE.") + +TextStyle1($44417, "I COULD NOT SLEEP..") +TextStyle1($4442B, "THINKING A LOT..") + + +// Chiberus - Priest +TextStyle1($44378, "HOW MAY I SERVE YOU?") + +TextStyle1($4446D, " HEAL ALL") +TextStyle1($47F21, "MAY YOU EACH BE HEALED...") +TextStyle1($4438D, "I DO MY BEST") + +TextStyle1($44477, " REVIVE ALL PARTY") +TextStyle1($47AAC, "GIVE $300 PLEASE") +TextStyle1($44489, "NOBODY SEEMS TO BE DEAD") + + +// Chiberus - Egg Shop +TextStyle2($41ED3, "HCACYC CGCICRCLC:CH0E0R0E0 0I0S0 0A0N0 0E0G0G0", TextType7) +TextStyle1($41F02, " OK") +TextStyle1($41F06, " NO") + +TextStyle1($41F0C, "IM GLAD,HO HO") + +TextStyle1($4201C, "MY EGGS ARE REALLY") +TextStyle1($44527, "VERY DELICIOUS") + + +// Gort - Outside +TextStyle1($42087, "WELCOME TO THE CITY OF GORT") + +TextStyle1($420EA, "PLEASE VISIT") +TextStyle1($420F7, "CASTLE, TO SEE KING") + +TextStyle1($420A3, "KNOW ABOUT NEURATH TOWN?") + +TextStyle1($4518C, "IT IS BEING") +TextStyle1($420BC, "ATTACKED BY A DEMON NOW") + +TextStyle1($420D4, "ITS IN THE NORTHWEST.") + +TextStyle1($4202F, "MONSTERS APPEARING ALL OVER") + +TextStyle1($4210B, "MONSTERS ARE HARD WORK") + +TextStyle1($4206A, "ITS HARD ENOUGH, PROTECTING") +TextStyle1($4214F, "OUR TOWN") + + +// Gort - Bottom Left House +TextStyle1($44734, "SHOULD NOT CONTEMPLATE LOSS") + + +// Gort - Bottom Middle Left House +TextStyle1($4204D, "WHY WAS I BORN IN THIS ERA.") + +TextStyle1($42122, "MY DAD WAS A KNIGHT.") + +TextStyle1($42137, "WE NEED TO REGAIN POWER") +TextStyle1($42158, "USING SLAYS EXAMPLE.") + +TextStyle1($443FD, "SLEEPY") + + +// Gort - Bottom Middle Right House +TextStyle1($44963, "WOMEN USED TO BE RECRUITED.") + +TextStyle1($441C1, "OSWALD IS BECOMING") +TextStyle1($441D4, "MORE FAMOUS!") + + +// Gort - Bottom Right House +TextStyle1($448FF, "WE NEED TO FIND") +TextStyle1($4490F, "THE CRYSTAL OF GLOBUS") + +TextStyle1($44925, "WE CAN DEPEND ON SLAY") + +TextStyle1($4493B, "WONT STAND A CHANCE") +TextStyle1($4494F, "AGAINST OSWALD NOW.") + + +// Gort - Middle Right House +TextStyle1($4477D, "I CAME TO GORT 8 YEARS AGO.") + +TextStyle1($44799, "WHEN I GROW,I WANT TO BE A") +TextStyle1($447B4, "GORT KNIGHT.") + +TextStyle1($44404, "UP LATE THIS NIGHT") + + +// Gort - Bar +TextStyle1($446D3, "BUSINESS IS GOING SLOW,") +TextStyle1($446EB, "WINES THE BEST CURE.") + +TextStyle1($44700, "AT LEAST I CAN SLEEP SAFE") +TextStyle1($4471A, "THANKS TO THE KNIGHTS AID") + + +// Gort - Middle Left House +TextStyle1($448D0, "GLOBUS IS SEALED IN THE") +TextStyle1($448E8, "GROUND.OSWALD IS THERE") + + +// Gort - Forge +TextStyle1($43817, "HI!I WORK METAL") + +TextStyle1($43827, " BUY GOODS") +TextStyle1($43832, " NO TRADE") + +TextStyle1($4383C, "TAKE YOUR TIME") +TextStyle1($4384B, "SEE MY GOODS") + +TextStyle1($438C1, "WHAT!") +TextStyle1($43858, "I HAVE FINE GOODS") + +TextStyle1($438C7, "COME ANY TIME") + + +// Gort - Shade Shop (Red Cap) +TextStyle2($4482E, "SCHCACDCEC:CD0O0 0Y0O0U0 0W0A0N0T0 0A0 0W0A0R0P0?0", TextType7) + +TextStyle1($44861, "HERES WHAT I HAVE") + +TextStyle1($4487D, "YOU CAN") +TextStyle1($44873, "WARP HERE") + +// Gort - Hebe Shop (Blue Cap) +TextStyle2($447C1, "HCECBCEC:CS0E0E0 0M0Y0 0N0I0C0E08191?0", TextType7) + +TextStyle1($447E8, "SEE MY AMAZINGLY FINE GOODS") + +TextStyle1($44811, "COME AGAIN, IF") +TextStyle1($44804, "YOU WANT IT.") + +TextStyle1($47F3C, "I CAN NOT WEAR THEM.") + + +// Gort - Castle +TextStyle1($4497F, "WERE PROTECTING THE KING.") + +TextStyle2($449AC, "GCUCACRCDCSC:C 0N0E0E0D0 0T0H0E0 0K0I0N0G0?0", TextType7) + +TextStyle1($44999, "SPEAK TO THE KING.") + +TextStyle1($449D9, "DONT NEED TO VISIT,") +TextStyle1($449ED, "YOURE WASTING TIME!") + +TextStyle1($4216D, "KINGS STRONGER THAN") +TextStyle1($42181, "EVER TO RESOLVE PROBLEMS") + +TextStyle1($4219A, "IVE BEEN TOLD OSWALD") +TextStyle1($421AF, "IS REVIVED") + +TextStyle1($421BA, "HIS EVIL GRIP IS TIGHTER") + +TextStyle1($421D3, "WE ARE SITTING DUCKS HERE..") + +TextStyle1($42206, "ARE YOU TO BRING US PEACE?") + +TextStyle1($42221, "SORRY I MISUNDERSTOOD YOU.") + +TextStyle1($4223C, "OH COURAGE!") +TextStyle1($42248, "YOU MUST MEET WITH SLAY.") + +TextStyle1($42261, "HE ALSO FOUGHT OSWALD.") + +TextStyle1($42278, "YOU NEED TO GAIN HIS TRUST") + +TextStyle1($42293, "HE WILL HELP, IF YOU") +TextStyle1($422A8, "BRING ME GOLEMS HEAD.") + +TextStyle1($422BE, "I ALSO NEED THE GOLEM HEAD.") + +TextStyle1($422DC, "MAY I HAVE IT") + +TextStyle1($422EA, "EXCHANGE LETTER FOR HEAD?") + +TextStyle1($42304, "SLAY LIVES IN NEURATH") +TextStyle1($4231A, "HES A GREAT GORT KNIGHT.") + +TextStyle1($42333, "YOU SHOULD GET THE LETTER") +TextStyle1($4234D, "TO SLAY QUICKLY.") + +TextStyle1($44A0E, "SO BE IT.") + +TextStyle1($44A18, "THATS ALL") +TextStyle1($44A22, "I HOPE THAT YOU RETURN SAFE") + +TextStyle1($44A3E, "EXPECT YOU TO SUCCEED!") + + +// Neurath - Outside +TextStyle1($45E68, "KNOW ABOUT SAGE FILO?") + +TextStyle1($45E7E, "I ALSO DONT KNOW.") + +TextStyle1($45E90, "VERY RARE TO MEET HIM") + + +// Neurath - Bottom Left House +TextStyle1($45768, "GOING TO MIKEANA") + +TextStyle1($45779, "SOUTHEAST FROM GORT") + +TextStyle1($46ABD, "PASS IT TO REACH COURT ROAD") + +TextStyle1($44AC5, "CONVERSE WITH ANOBA") + +TextStyle1($44AD9, "PLEASE BEHAVE POLITELY") + +TextStyle1($44AF0, "HMMM") + +TextStyle1($44AF5, "WHERES THE CRYSTAL!") + + +// Neurath - Jennifer Shop (Green Head) +TextStyle2($44A55, "JCECNCYC:CN0E0E0D0 0N0E0U0R0A0T0H0 0W0A0R0P0?0", TextType7) + +TextStyle1($44A84, "YAY,THANK YOU") + +TextStyle1($44AA2, "PLEASE,") +TextStyle1($44A92, "I HAVE CHILDREN") \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.ips b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.ips new file mode 100644 index 00000000..2c4e8fac Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Albert Odyssey.ips differ diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.png b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.png new file mode 100644 index 00000000..b23343d5 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.txt new file mode 100644 index 00000000..a224d77a --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable1.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0|0 1 2 3 4 5 6 7 8 9 A B C D E F +1|G H I J K L M N O P Q R S T U V +2|W X Y Z ? ! - / あ い う え お か き +3|く け こ さ し す せ そ た ち つ て と な に ぬ +4|ね の は ひ ふ へ ほ ま み む め も や ゆ よ ら +5|り る れ ろ わ を ん が ぎ ぐ げ ご ざ じ ず ぜ +6|ぞ だ ぢ づ で ど ば び ぶ べ ぼ ぱ ぴ ぷ ぺ ぽ +7|ぁ っ ゃ ゅ ょ ア イ ウ エ オ カ キ ク ケ コ サ +8|シ ス セ ソ タ チ ツ テ ト ナ ニ ヌ ネ ノ ハ ヒ +9|フ ヘ ホ マ ミ ム メ モ ヤ ユ ヨ ラ リ ル レ ロ +A|ワ ヲ ン ガ ギ グ ゲ ゴ ザ ジ ズ ゼ ゾ ダ ヂ ヅ +B|デ ド バ ビ ブ ベ ボ パ ピ プ ペ ポ ァ ッ ャ ュ +C|ョ 「 」 。 、 武 器 攻 撃 生 早 正 移 動 力 +D|騎 団 長 金 耐 久 : 戦 剣 後 師 守 備 水 晶 地 +E|魔 法 僧 侶 術 導 賢 者 血 補 無 王 祭 気 合 勇 +F|特 弾 行 総 殺 督 $ ー 司 東 西 南 北 方 向 決 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.png b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.png new file mode 100644 index 00000000..3b0dbf8b Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.txt new file mode 100644 index 00000000..f25279aa --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOCharTable2.txt @@ -0,0 +1,10 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0|定 拔 大 図 縦 横 林 形 X X X X X X X X +1|道 路 海 山 平 野 砂 森 + 戻 続 選 命 令 草 +2|士 岳 取 消 終 了 町 村 都 X X X X 様 瞬 効 +3|X X 特 物 果 % X 雷 火 敵 風 名 持 鬼 +4|手 右 左 頭 胴 体 X X X 中 範 囲 ェ 測 X +5|蘇 X 目 上 直 間 接 択 率 標 ぃ ィ ぇ X X +6|装 備 ヴ 両 足 常 薬 X X 城 X X X X X +7|X X X X X X X X X X X X X X X X \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOChars.png b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOChars.png new file mode 100644 index 00000000..6f8631f1 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/CharTables/AOChars.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Battle.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Battle.txt new file mode 100644 index 00000000..3cd736df --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Battle.txt @@ -0,0 +1,116 @@ +----------------- +Battle Messages: +----------------- +耐久力 +Endurance (Top Half) +$14E62 $14EAF $14EFC +A4 21 A5 21 8F 21 | Original Japanese Hex +耐WHITE 久WHITE 力WHITE | Original Japanese Text +HWHITE PWHITE :WHITE | New English Text +21 20 29 20 A6 21 | New English Hex + Endurance (Bottom Half) + $14E6B $14EB8 $14F05 + B4 21 B5 21 9F 21 | Original Japanese Hex + 耐WHITE 久WHITE 力WHITE | Original Japanese Text + HWHITE PWHITE :WHITE | New English Text + 31 20 39 20 B6 21 | New English Hex + +地形効果 +Terrain effect (Top half) +$14DFE $14E17 $14E30 $14E49 +AF 21 07 22 4F 22 64 22 | Original Japanese Hex +地WHITE 形WHITE 効WHITE 果WHITE | Original Japanese Text +AWHITE RWHITE EWHITE AWHITE | New English Text +0A 20 2B 20 0E 20 0A 20 | New English Hex + Terrain effect (Bottom half) + $14E07 $14E20 $14E39 $14E52 + BF 21 17 22 5F 22 74 22 | orig kanji hex + 地WHITE 形WHITE 効WHITE 果WHITE | Original Japanese Text + AWHITE RWHITE EWHITE AWHITE | New English Text + 1A 20 3B 20 1E 20 1A 20 | New English Hex + +向き補正率 +Orientation correction factor (Top Half) +$14F5B $14F74 $14F8D $14FA6 $14FBF +EE 21 4F 20 C9 21 8B 21 A8 22 | Original Japanese Hex +向WHITE きWHITE 補WHITE 正WHITE 率WHITE | Original Japanese Text +FWHITE OWHITE CWHITE UWHITE SWHITE | New English Text +0F 20 28 20 0C 20 2E 20 2C 20 | New English Hex + Orientation correction factor (Bottom Half) + $14F64 $14F7D $14F96 $14FAF $14FC8 + FE 21 5F 20 D9 21 9B 21 B8 22 | Original Japanese Hex + 向WHITE きWHITE 補WHITE 正WHITE 率WHITE | Original Japanese Text + FWHITE OWHITE CWHITE UWHITE SWHITE | New English Text + 1F 20 38 20 1C 20 3E 20 3C 20 | New English Hex + +と +And +$444D4 +E3 3C 00 28 00 F6 08 D6 00 | Original Japanese Hex +LENGTH とWHITE WHITE $GOLD :WHITE | Original Japanese Text +LENGTH +WHITE WHITE $GOLD :WHITE | New English Text +E3 18 01 28 00 F6 08 D6 00 | New English Hex + +を手にいれた! +Got the! +$444DD +26 01 55 40 3E 2A 52 38 25 | Original Japanese Hex +LENGTH LENGTH を 手 に い れ た ! | Original Japanese Text +LENGTH R E C E I V E D | New English Text +07 1B 0E 0C 0E 12 1F 0E 0D | New English Hex + +は、 +The +$446B4 +01 42 C4 | Original Japanese Hex +LENGTH は 、 | Original Japanese Text +LENGTH : | New English Text +01 28 D6 | New English Hex + +を、ひろった! +Picked Up the! +$446B7 +06 55 C4 43 53 71 38 25 | Original Japanese Hex +LENGTH を 、 ひ ろ っ た ! | Original Japanese Text +LENGTH S E I Z E D ! | New English Text +06 1C 0E 12 23 0E 0D 25 | New English Hex + +は、しんでしまった +It died +$44538 +08 42 C4 34 56 64 34 47 71 38 | Original Japanese Hex +LENGTH は 、 し ん で し ま っ た | Original Japanese Text +LENGTH H A S D I E D . | New English Text +08 11 0A 1C 28 0D 12 0E 0D C3 | New English Hex + +は、まひ してしまった +Had paralyzed +$446BF +0A 42 C4 47 43 28 34 3B 34 47 71 38 | Original Japanese Hex +LENGTH は 、 ま ひ し て し ま っ た | Original Japanese Text +LENGTH I S S T O N E . . . | New English Text +0A 12 1C 28 1C 1D 18 17 0E C3 C3 C3 | New English Hex + +まひ している +Has paralysis +$446CB +06 47 43 28 34 3B 2A 51 | Original Japanese Hex +LENGTH ま ひ し て い る | Original Japanese Text +LENGTH S T O N E . . | New English Text +06 1C 1D 18 17 0E C3 C3 | New English Hex + +は、まひ した! +Is paralyzed! +$47B19 +07 42 C4 47 43 28 34 38 25 | Original Japanese Hex +LENGTH は 、 ま ひ し た ! | Original Japanese Text +LENGTH I S S T O N E | New English Text +07 12 1C 28 1C 1D 18 17 0E | New English Hex + +の まひ が とけた! +Paralysis Removed! +$47F51 +0A 41 28 47 43 28 57 28 3C 31 38 25 | Original Japanese Hex +LENGTH の ま ひ が と け た ! | Original Japanese Text +LENGTH S T O N E G O N E ! | New English Text +0A 1C 1D 18 17 0E 28 10 18 17 0E 25 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/BattleSelection.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/BattleSelection.txt new file mode 100644 index 00000000..dc30c2e3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/BattleSelection.txt @@ -0,0 +1,140 @@ +------------------------- +Albert Battle Selection: +------------------------- +移動 | 攻撃 | へんしん | 行動終了 +Movement | Attack | Transformation | Exit action +$410DF | $40C5C | $479A7 | $40C61 +03 28 CD CE 28 | 03 28 C7 C8 28 | 03 45 56 34 56 | 43 02 03 F2 CE 24 25 | Original Japanese Hex +LENGTH 移 動 | LENGTH 攻 撃 | LENGTHへ ん し ん | LENGTHLENGTH LENGTH 行 動 終 了 | Original Japanese Text +LENGTH M O V E | LENGTH H I T | LENGTHP S Y K | LENGTHE N D G O 了 | New English Text +03 16 18 1F 0E | 03 28 11 12 1D | 03 19 1C 22 14 | 04 0E 17 0D 10 18 25 | New English Hex + +---------------------------------- +Neumann & Sofia Battle Selection: +---------------------------------- +移動 | 攻撃 | 魔法 | 行動終了 +Movement | Attack | Magic | Exit action +$410DF | $40C5C | $40CBF | $40C61 +03 28 CD CE 28 | 03 28 C7 C8 28 | 03 28 E0 E1 28 | 43 02 03 F2 CE 24 25 | Original Japanese Hex +LENGTH 移 動 | LENGTH 攻 撃 | LENGTH 魔 法 | LENGTHLENGTH LENGTH 行 動 終 了 | Original Japanese Text +LENGTH M O V E | LENGTH H I T | LENGTHC A S T | LENGTHE N D G O 了 | New English Text +03 16 18 1F 0E | 03 28 11 12 1D | 03 0C 0A 1C 1D | 04 0E 17 0D 10 18 25 | New English Hex + +--------------- +Movement Text: +--------------- +移動 +Movement +$41950 +E3 28 18 CD 18 CE 18 28 18 | Original Japanese Hex +LENGTH WHITE 移WHITE 動WHITE WHITE | Original Japanese Text +LENGTH MWHITE OWHITE VWHITE EWHITE | New English Text +E3 16 18 18 18 1F 18 0E 18 | New English Hex + +移動範囲測定 +Moving range measurement +$4106C +85 02 03 04 05 CD CE 4B 4C 4E 00 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH 移 動 範 囲 測 定 | Original Japanese Text +LENGTH P R O C E S S I N G | New English Text +09 19 1B 18 0C 0E 1C 1C 12 17 10 | New English Hex + +移動力: +Locomotion: (Top Half) +$4E8AF $4E8BB $4E8C7 $4E8D3 +8D 21 8E 21 8F 21 A6 21 | Original Japanese Hex +移WHITE 動WHITE 力WHITE :WHITE | Original Japanese Text +SWHITE TWHITE PWHITE :WHITE | New English Text +2C 20 2D 20 29 20 A6 21 | New English Hex + Locomotion: (Bottom Half) + $4E8B5 $4E8C1 $4E8CD $4E8D9 + 9D 21 9E 21 9F 21 B6 21 | Original Japanese Hex + 移WHITE 動WHITE 力WHITE :WHITE | Original Japanese Text + SWHITE TWHITE PWHITE :WHITE | New English Text + 3C 20 3D 20 39 20 B6 21 | New English Hex + +------------- +Attack Text: +------------- +攻撃 +Attack +$41962 +E3 28 18 C7 18 C8 18 28 18 | Original Japanese Hex +LENGTH 攻 撃 | Original Japanese Text +LENGTH H I T | New English Text +E3 28 18 11 18 12 18 1D 18 | New English Hex + +まわりに敵はいません +No enemies around +$41098 +29 04 47 54 50 3E 39 42 2A 47 36 56 | Original Japanese Hex +LENGTH LENGTH ま わ り に 敵 は い ま せ ん | Original Japanese Text +LENGTH N O O N E N E A R | New English Text +0A 17 18 28 18 17 0E 28 17 0E 0A 1B | New English Hex + +向きを選んでください +Please choose a direction +$413C5 +29 03 FE 2F 55 1C 56 64 30 61 33 2A | Original Japanese Hex +LENGTH LENGTH 向 き を 選 ん で く だ さ い | Original Japanese Text +LENGTH T O : T A R G E T い | New English Text +09 1D 18 D6 28 1D 0A 1B 10 0E 1D 2A | New English Hex + +攻撃は 敵に向って! +Attack towards the enemy! +$4108C (Line 1) +29 04 C7 C8 42 28 39 3E FE 71 3B 25 | Original Japanese Hex +LENGTH LENGTH 攻 撃 は 敵 に 向 っ て ! | Original Japanese Text +LENGTH E M P T Y S P A C E | New English Text +0A 0E 16 19 1D 22 28 1C 19 0A 0C 0E | New English Hex + +------------------ +Exit Action Text: +------------------ +行動終了 +Exit action +$41959 +E3 F2 18 CE 18 24 19 25 19 | Original Japanese Hex +LENGTH 行WHITE 動WHITE 終WHITE 了WHITE | orig kanji text +LENGTH EWHITE NWHITE DWHITE SWHITE | New English Text +E3 0E 18 17 18 0D 18 1C 18 | New English Hex + +移動キャンセル中 +Canceling movement +$41035 +E7 CD 08 CE 08 7B 00 BE 00 A2 00 82 00 9D 00 4A 09 | Original Japanese Hex +LENGTH 移GOLD 動GOLD キWHITE ャWHITE ンWHITE セWHITE ルWHITE 中GOLD | Original Japanese Text +LENGTH CGOLD AGOLD NGOLD CGOLD EGOLD LGOLD ルWHITE 中GOLD | New English Text +E5 0C 08 0A 08 17 08 0C 08 0E 08 15 08 9D 00 4A 09 | New English Hex + +行動終了している +Action has been completed +$40CD0 (Line 1) +47 02 03 F2 CE 24 25 34 3B 2A 51 | Original Japanese Hex +LENGTH LENGTH LENGTH 行 動 終 了 し て い る | Original Japanese Text +LENGTH T U R N E N D E D | New English Text +09 0D 1E 1B 17 28 0E 17 0D 0E 0D | New English Hex + +ターンを終了しますか? +Do you want to end your turn? +$463CE +4A 04 05 84 F7 A2 55 24 25 34 47 35 2E 24 | Original Japanese Hex +LENGTH LENGTH LENGTH タ ー ン を 終 了 し ま す か ? | Original Japanese Text +LENGTH E N D O F T U R N ? か ? | New English Text +0A 0E 17 0D 18 0F 28 1D 1E 1B 17 24 2E 24 | New English Hex + +YES-A ボタン NO-B ボタン +YES-A Button NO-B Button +$40E35 +10 22 0E 1C 26 0A B6 84 A2 28 28 17 18 26 0B B6 84 A2 | Original Japanese Hex +LENGTH Y E S - A ボ タ ン N O - B ボ タ ン | Original Japanese Text +LENGTH Y E S - A N O - B B U T T O N | New English Text +10 22 0E 1C 26 0A 28 17 18 26 0B 28 0B 1E 1D 1D 18 17 | New English Hex + +持後する +After you have +$410A4 +E3 3C 09 D9 08 35 00 51 00 | Original Japanese Hex +LENGTH 持GOLD 後GOLD すWHITE るWHITE | Original Japanese Text +LENGTH VWHITE IWHITE EWHITE WWHITE | New English Text +E3 1F 00 12 00 0E 00 20 00 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterNames.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterNames.txt new file mode 100644 index 00000000..17e1efc3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterNames.txt @@ -0,0 +1,53 @@ +------------------ +Intro Characters: +------------------ +ゴート騎士 +Gothic Knights +$40CE6 +24 04 A7 F7 88 D0 20 | Original Japanese Hex +LENGTH LENGTH ゴ ー ト 騎 士 | Original Japanese Text +LENGTH K N I G H T | New English Text +05 14 17 12 10 11 1D | New English Hex + +スレイ団長 +Slay head +$40CF3 +04 81 9E 76 D1 D2 | Original Japanese Hex +LENGTH ス レ イ 団 長 | Original Japanese Text +LENGTH S L A Y 長 | New English Text +03 1C 15 0A 22 D2 | New English Hex + +総督 +Governor-General +$40F8E +01 F3 F5 | Original Japanese Hex +LENGTH 総 督 | Original Japanese Text +LENGTH G N | New English Text +01 10 17 | New English Hex + +--------------------- +Playable Characters: +--------------------- +勇者 アルバ-ト +Hero Albert +$40C6B +07 EF E7 28 75 9D B2 26 88 | Original Japanese Hex +LENGTH 勇 者 ア ル バ - ト | Original Japanese Text +LENGTH A L B E R T - ト | New English Text +05 0A 15 0B 0E 1B 1D 26 88 | New English Hex + +僧侶 ノイマン +Priest Neumann +$413BD +06 E2 E3 28 8D 76 93 A2 | Original Japanese Hex +LENGTH 僧 侶 ノ イ マ ン | Original Japanese Text +LENGTH N E U M A N N | New English Text +06 17 0E 1E 16 0A 17 17 | New English Hex + +魔術師 ソフィア +Magician Sofia +$40C82 +27 06 E0 E4 DA 28 83 90 5C 75 | Original Japanese Hex +LENGTH LENGTH 魔 術 師 ソ フ ィ ア | Original Japanese Text +LENGTH S O F I A ソ フ ィ ア | New English Text +04 1C 18 0F 12 0A 83 90 5C 75 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterSpells.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterSpells.txt new file mode 100644 index 00000000..7b4d17c9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/CharacterSpells.txt @@ -0,0 +1,130 @@ +------------------------ +Albert Transformations: +------------------------ +PsykeHit (Automatically Generated From "Psyke" & "Hit") + +攻撃目標 +Attack targets +$40C74 +E3 C7 08 C8 08 52 09 59 09 | Original Japanese Hex +LENGTH 攻GOLD 撃GOLD 目GOLD 標GOLD | Original Japanese Text +LENGTH TGOLD AGOLD RGOLD GGOLD | New English Text +E3 1D 08 0A 08 1B 08 10 08 | New English Hex + + (攻撃目標) 向きを選んでください + Please choose a direction + $41077 + E9 FE 08 2F 08 55 00 1C 01 56 00 64 00 30 00 61 00 33 00 2A 00 | Original Japanese Hex + LENGTH 向GOLD きGOLD をWHITE 選WHITE んWHITE でWHITE くWHITE だWHITE さWHITE いWHITE | Original Japanese Text + LENGTH GOLD SGOLD EGOLD TGOLD SWHITE EWHITE LWHITE EWHITE CWHITE TWHITE | New English Text + E9 28 08 1C 08 0E 08 1D 08 1C 00 0E 00 15 00 0E 00 0C 00 1D 00 | New English Hex + + (攻撃目標)に 敵はいません + No enemy targets + $410AD + E7 3E 00 28 00 39 09 42 00 2A 00 47 00 36 00 56 00 | Original Japanese Hex + LENGTH にWHITE WHITE 敵WHITE はWHITE いWHITE まWHITE せWHITE んWHITE | Original Japanese Text + LENGTH EGOLD TGOLD WHITE EWHITE MWHITE PWHITE TWHITE YWHITE | New English Text + E7 0E 08 1D 08 28 00 0E 00 16 00 19 00 1D 00 22 00 | New English Hex + +-------------------- +Neumann Holy Magic: +-------------------- +しんせい魔法 +Holy Magic +$479C5 +E5 34 18 56 18 36 18 2A 18 E0 18 E1 18 | Original Japanese Hex +LENGTH しWHITE んWHITE せWHITE いWHITE 魔WHITE 法WHITE | Original Japanese Text +LENGTH WWHITE MWHITE AWHITE GWHITE IWHITE CWHITE | New English Text +E5 20 18 16 18 0A 18 10 18 12 18 0C 18 | New English Hex + +かいふく +Restoration +$479B9 +03 2E 2A 44 30 | Original Japanese Hex +LENGTH か い ふ く | Original Japanese Text +LENGTH C U R E | New English Text +03 0C 1E 1B 0E | New English Hex + + だれの体力を かいふくさせますか? + Who's strength to restore? + $444E6 + 30 03 61 52 41 45 CF 55 28 2E 2A 44 30 33 36 47 35 2E 24 | Original Japanese Hex + LENGTH LENGTH だ れ の 体 力 を か い ふ く さ せ ま す か ? | Original Japanese Text + LENGTH W H O W I L L Y O U C U R E ? | New English Text + 11 20 11 18 28 20 12 15 15 28 22 18 1E 28 0C 1E 1B 0E 24 | New English Hex + +蘇生 +Revival / Resurrection +$479BE +21 00 50 C9 | Original Japanese Hex +LENGTH LENGTH 蘇 生 | Original Japanese Text +LENGTH L I F | New English Text +02 15 12 0F | New English Hex + +ちゆ +Healing +$479C2 +01 39 4D | Original Japanese Hex +LENGTH ち ゆ | Original Japanese Text +LENGTH H L | New English Text +01 11 15 | New English Hex + + だれを? + Who? + $44693 + 03 61 52 55 24 | Original Japanese Hex + LENGTH だ れ を ? | Original Japanese Text + LENGTH W H O ? | New English Text + 03 20 11 18 24 | New English Hex + +------------- +Sofia Magic: +------------- +魔法 +Magic +$41347 +E1 E0 18 E1 18 | Original Japanese Hex +LENGTH 魔WHITE 法WHITE | Original Japanese Text +LENGTH BWHITE LWHITE | New English Text +E1 0B 18 15 18 | New English Hex + +魔法 +Magic +$4196B (Shows When Doing Multiple Magic) +E3 28 18 E0 18 E1 18 28 18 | Original Japanese Hex +LENGTH WHITE 魔WHITE 法WHITE WHITE | Original Japanese Text +LENGTH BWHITE LWHITE ?WHITE ?WHITE | New English Text +E3 0B 18 15 18 ?? 18 ?? 18 | New English Hex + +雷撃 +Lightning Strike +$479D8 +21 00 37 C8 | Original Japanese Hex +LENGTH LENGTH 雷 撃 | Original Japanese Text +LENGTH L I T | New English Text +02 15 12 1D | New English Hex + +火えん弾 +Fire bullet +$479DC +23 00 38 2C 56 F1 | Original Japanese Hex +LENGTH LENGTH 火 え ん 弾 | Original Japanese Text +LENGTH F I R E 弾 | New English Text +03 0F 12 1B 0E F1 | New English Hex + +瞬間移動 +Teleportation +$479E2 +43 00 01 2E 55 CD CE | Original Japanese Hex +LENGTH LENGTH LENGTH 瞬 間 移 動 | Original Japanese Text +LENGTH W A R P 移 動 | New English Text +03 20 0A 1B 19 CD CE | New English Hex + + どこに? + Where? + $4468E + 03 65 32 3E 24 | Original Japanese Hex + LENGTH ど こ に ? | Original Japanese Text + LENGTH T O ? | New English Text + 03 1D 18 28 24 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Equipment.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Equipment.txt new file mode 100644 index 00000000..f232ed96 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Equipment.txt @@ -0,0 +1,146 @@ +----------- +Equipment: +----------- +勇者の剣 +Brave/Hero Sword +$40FE5 +EF 00 E7 00 41 00 D8 00 | Original Japanese Hex +勇BLACK 者BLACK のBLACK 剣BLACK | Original Japanese Text +HBLACK EBLACK RBLACK OBLACK | New English Text +11 00 0E 00 1B 00 18 00 | New English Hex + +魔術師のつえ +Magician Wand +$416FD +E0 00 E4 00 DA 00 41 00 3A 00 2C 00 | Original Japanese Hex +魔BLACK 術BLACK 師BLACK のBLACK つBLACK えBLACK | Original Japanese Text +WBLACK IBLACK ZBLACK ABLACK RBLACK DBLACK | New English Text +20 00 12 00 23 00 0A 00 1B 00 0D 00 | New English Hex + +僧侶のつえ +Priest Cane/Staff +$417B9 +E2 00 E3 00 41 00 3A 00 2C 00 | Original Japanese Hex +僧BLACK 侶BLACK のBLACK つBLACK えBLACK | Original Japanese Text +VBLACK IBLACK CBLACK ABLACK RBLACK | New English Text +1F 00 12 00 0C 00 0A 00 1B 00 | New English Hex + +ぬののふく +Cloth Clothes +$416E8 +3F 41 41 44 30 | Original Japanese Hex +ぬ の の ふ く | Original Japanese Text +C L O T H | New English Text +0C 15 18 1D 11 | New English Hex + +どうのよろい +Copper Armour +$416F2 +65 2B 41 4E 53 2A | Original Japanese Hex +ど う の よ ろ い | Original Japanese Text +C O P P E R | New English Text +0C 18 19 19 0E 1B | New English Hex + +スピア +Spear +$4170E +81 B8 75 | Original Japanese Hex +ス ピ ア | Original Japanese Text +S P R | New English Text +1C 19 1B | New English Hex + +こんぼう +Club +$41716 +32 56 6A 2B | Original Japanese Hex +こ ん ぼ う | Original Japanese Text +C L U B | New English Text +0C 15 1E 0B | New English Hex + +ショートソード +Short Sword +$41728 +80 C0 F7 88 83 F7 B1 | Original Japanese Hex +シ ョ ー ト ソ ー ド | Original Japanese Text +S H O R T | New English Text +1C 11 18 1B 1D 28 28 | New English Hex + +ダガー +Dagger +$41734 +AD A3 F7 | Original Japanese Hex +ダ ガ ー | Original Japanese Text +D A G | New English Text +0D 0A 10 | New English Hex + +ラージシールド +Large Shield +$4173C +9B F7 A9 80 F7 9D B1 | Original Japanese Hex +ラ ー ジ シ ー ル ド | Original Japanese Text +L A R G E | New English Text +15 0A 1B 10 0E 28 28 | New English Hex + +バックラー +Buckler +$41748 +B2 BD 7C 9B F7 | Original Japanese Hex +バ ッ ク ラ ー | Original Japanese Text +B U C K L | New English Text +0B 1E 0C 14 15 | New English Hex + +チェーンメイル +chain Mail +$4174D $41752 +68 00 01 03 76 77 85 4D F7 A2 96 76 9D | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH MAIL MAIL チ ェ ー ン メ イ ル | Original Japanese Text +LENGTH LENGTH LENGTH MAIL MAIL C H A I N | New English Text +49 00 01 76 77 0C 11 0A 12 17 28 28 28 | New English Hex + +でかいくつ +Big/Huge/Large Shoes +$4175F +64 2E 2A 30 3A | Original Japanese Hex +で か い く つ | Original Japanese Text +L A R G E | New English Text +15 0A 1B 10 0E | New English Hex + +ヘルム +Helm +$4178E +91 9D 95 | Original Japanese Hex +ヘ ル ム | Original Japanese Text +H L M | New English Text +11 15 16 | New English Hex + +ぼうし +Hat/Cap +$417C8 +6A 2B 34 | Original Japanese Hex +ぼ う し | Original Japanese Text +C A P | New English Text +0C 0A 19 | New English Hex + +かわのくつ +Leather/Hide Shoes +$417D0 +2E 54 41 30 3A | Original Japanese Hex +か わ の く つ | Original Japanese Text +L E A T H | New English Text +15 0E 0A 1D 11 | New English Hex + +かわのブーツ +River/Water boots +$417DA +2E 54 41 B4 F7 86 | Original Japanese Hex +か わ の ブ ー ツ | Original Japanese Text +R U B B E R | New English Text +1B 1E 0B 0B 0E 1B | New English Hex + +かわのたて +Shield Skin/Leather +$41861 +2E 54 41 38 3B | Original Japanese Hex +か わ の た て | Original Japanese Text +L E A T H | New English Text +15 0E 0A 1D 11 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/ExitTown.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/ExitTown.txt new file mode 100644 index 00000000..22cc7f59 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/ExitTown.txt @@ -0,0 +1,18 @@ +----------- +Exit Town: +----------- +そと に でます か? +Exit To Outside Location? +$40DE5 +08 37 3C 3E 28 64 47 35 2E 24 02 AC | Original Japanese Hex +LENGTH そ と に で ま す か ? | Original Japanese Text +LENGTH G O O U T S I D E ? | New English Text +0A 10 18 28 18 1E 1D 1C 12 0D 0E 24 | New English Hex + +YES - A ボタン +YES - A Button +$40DF8 +E9 22 0C 0E 0C 1C 0C 28 00 26 00 28 00 0A 0C B6 0C 84 0C A2 0C | Original Japanese Hex +LENGTH YRED ERED SRED BLACK -BLACK BLACK ARED ボRED タRED ンRED | Original Japanese Text +LENGTH YRED ERED SRED BLACK -BLACK BLACK RED ARED タRED ンRED | New English Text +E7 22 0C 0E 0C 1C 0C 28 00 26 00 28 00 28 0C 0A 0C 84 0C A2 0C | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Inns.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Inns.txt new file mode 100644 index 00000000..9af3ea80 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Inns.txt @@ -0,0 +1,84 @@ +-------------- +Chiberus Inn: +-------------- +おつかれさ ま です。ここは やどやですが+++ +You must be tired. +++ Here is the inn +$43781 (Line 1) +75 13 14 15 2D 3A 2E 52 33 47 64 35 C3 32 32 42 28 4C 65 4C 64 35 57 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH お つ か れ さ ま で す 。 こ こ は や ど や で す が + + + | Original Japanese Text +LENGTH R E S T , I F Y O U A R E T I R E D . . . | New English Text +18 1B 0E 1C 1D C4 28 12 0F 28 22 18 1E 28 0A 1B 0E 28 1D 12 1B 0E 0D C3 C3 C3 | New English Hex + + とまる + Stay + $47B80 (Line 2) + 03 28 3C 47 51 | Original Japanese Hex + LENGTH と ま る | Original Japanese Text + LENGTH B E D | New English Text + 03 28 0B 0E 0D | New English Hex + + SAVEする + Save To File + $47B85 (Line 3) + 06 28 1C 0A 1F 0E 35 51 | Original Japanese Hex + LENGTH S A V E す る | Original Japanese Text + LENGTH S A V E | New English Text + 04 28 1C 0A 1F 0E 28 28 | New English Hex + +しゅくはくりょう は $10 と なっております +Price of Room is $10 +$437A4 (Line 1) +09 34 73 30 42 30 50 74 2B 28 42 | Original Japanese Hex +LENGTH し ゅ く は く り ょ う は | Original Japanese Text +LENGTH I T W I L L B E | New English Text +09 12 1D 28 20 12 15 15 28 0B 0E | New English Hex +$437AF (Line 2) +0C F6 01 00 28 3C 28 3D 71 3B 2D 50 47 35 | Original Japanese Hex +LENGTH $ 1 0 と な っ て お り ま す | Original Japanese Text +LENGTH $ 1 0 T O S T A Y . す | New English Text +0B F6 01 00 28 1D 18 28 1C 1D 0A 22 C3 35 | New English Hex + +わかりました。では このノートに+++ +All right. Please Write down you progress in this notebook +$47B8D +72 10 11 12 54 2E 50 47 34 38 C3 64 42 28 32 41 8D F7 88 3E 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH わ か り ま し た 。 で は こ の ノ ー ト に + + + | Original Japanese Text +LENGTH R E C O R D I N G S A V E D A T A . . . | New English Text +15 1B 0E 0C 18 1B 0D 12 17 10 28 1C 0A 1F 0E 28 0D 0A 1D 0A C3 C3 C3 | New English Hex + +このさき お気をつけて いってらっしゃいませ +Take care and have a safe trip on your journey +$4388D (Line 1) +03 32 41 33 2F | Original Japanese Hex +LENGTH こ の さ き | Original Japanese Text +LENGTH S T A Y | New English Text +03 1C 1D 0A 22 | New English Hex +$43892 (Line 2) +10 2D ED 55 3A 31 3B 28 2A 71 3B 4F 71 34 72 2A 47 36 | Original Japanese Hex +LENGTH お 気 を つ け て い っ て ら っ し ゃ い ま せ | Original Japanese Text +LENGTH A N Y T I M E Y O U W A N T . | New English Text +10 0A 17 22 1D 12 16 0E 28 22 18 1E 28 20 0A 17 1D C3 | New English Hex + +ここまでのぼうけんをセーブしますか? +Do you want to save the adventure so far? +$4443C (Line 1) +11 32 32 47 64 41 6A 2B 31 56 55 82 F7 B4 34 47 35 2E 24 | Original Japanese Hex +LENGTH こ こ ま で の ぼ う け ん を セ ー ブ し ま す か ? | Original Japanese Text +LENGTH R E C O R D A D A T A L O G ? | New English Text +11 1B 0E 0C 18 1B 0D 28 0A 28 0D 0A 1D 0A 28 15 18 10 24 | New English Hex + + する + To File + $438E8 (Line 2) + 01 35 51 | Original Japanese Hex + LENGTH す る | Original Japanese Text + LENGTH O K | New English Text + 01 18 14 | New English Hex + + しない + Not + $4444F (Line 3) + 02 34 3D 2A | Original Japanese Hex + LENGTH し な い | Original Japanese Text + LENGTH N O い | New English Text + 01 17 18 2A | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Intro.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Intro.txt new file mode 100644 index 00000000..6d2618c0 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Intro.txt @@ -0,0 +1,361 @@ +------- +Intro: +------- +Title: +アルバート オデッセイ +Albert Odyssey +$43ABC +13 75 28 9D 28 B2 28 F7 28 88 28 28 79 28 B0 28 BD 28 82 28 76 | Original Japanese Hex +LENGTH ア ル バ ー ト オ デ ッ セ イ | Original Japanese Text +LENGTH A L B E R T - O D Y S S E Y | New English Text +13 28 28 0A 15 0B 0E 1B 1D 28 26 28 18 0D 22 1C 1C 0E 22 28 28 | New English Hex + +------------------------------------------------------------------------------------------ +Intro1: +グローバスふっかつの かぎ 「水晶」を もとめ しんりゃくを かいしした 大魔導師オズワルドは +The great mage Oswald began the invasion to seek the Crystal, key to the revival of Globus. +$43911 (Line 1) +16 A5 9F F7 B2 81 44 71 2E 3A 41 28 2E 58 28 C1 DD DE C2 55 28 4B 3C 4A | Original Japanese Hex +LENGTH グ ロ ー バ ス ふ っ か つ の か ぎ 「 水 晶 」 を も と め | Original Japanese Text +LENGTH T H E M A G E O S W A L D I N V A D E D | New English Text +16 1D 11 0E 28 17 0A 10 0E 28 18 1C 20 0A 15 0D 28 12 17 1F 0A 0D 0E 0D | New English Hex +$43D09 (Line 2) +36 0D 34 56 50 72 30 55 28 2E 2A 34 34 38 28 02 E0 E5 DA 79 AA A0 9D B1 42 | Original Japanese Hex +LENGTH LENGTH し ん り ゃ く を か い し し た 大 魔 導 師 オ ズ ワ ル ド は | Original Japanese Text +LENGTH S E E K I N G T H E C R Y S T A L K E Y , | New English Text +17 1C 0E 0E 14 12 17 10 28 1D 11 0E 28 0C 1B 22 1C 1D 0A 15 28 14 0E 22 C4 | New English Hex + +Intro2: +かつて 無敵といわれ ていた 騎士団に たいし あっとうてきな つよさを みせていた +Oswald demonstrated his overwhelming power against the Knights, who were formerly said to be invincible. +$43D22 (Line 1) +55 05 0F 2E 3A 3B 28 EA 39 3C 2A 54 52 3B 2A 38 28 D0 20 D1 3E 28 38 2A 34 | Original Japanese Hex +LENGTH LENGTH LENGTH か つ て 無 敵 と い わ れ て い た 騎 士 団 に た い し | Original Japanese Text +LENGTH U S I N G H I S P O W E R S A G A I N S T | New English Text +17 1E 1C 12 17 10 28 11 12 1C 28 19 18 20 0E 1B 1C 28 0A 10 0A 12 17 1C 1D | New English Hex +$43D3B (Line 2) +11 29 71 3C 2B 3B 2F 3D 28 3A 4E 33 55 28 48 36 3B 2A 38 | Original Japanese Hex +LENGTH あ っ と う て き な つ よ さ を み せ て い た | Original Japanese Text +LENGTH T H E B R A V E K N I G H T S . | New English Text +11 1D 11 0E 28 0B 1B 0A 1F 0E 28 14 17 12 10 11 1D 1C C3 | New English Hex + +------------------------------------------------------------------------------------------ +Top Screen Intro Lines: + +TopScreen1: +ゴート騎士団 さいごの決戦 +Knights of Gort - Last Stand +$4454F +3B 08 A7 28 F7 28 88 28 D0 28 20 28 D1 28 28 28 28 28 28 33 28 2A 28 5B 28 41 28 FF 28 D7 | Original Japanese Hex +LENGTH LENGTH ゴ ー ト 騎 士 団 さ い ご の 決 戦 | Original Japanese Text +LENGTH K N I G H T S O F G O R T - L A S T S T A N D . | New English Text +1C 14 17 12 10 11 1D 1C 28 18 0F 28 10 18 1B 1D 28 26 28 15 0A 1C 1D 28 1C 1D 0A 17 0D C3 | New English Hex + +TopScreen2: +ゴート騎士 「われら 騎士団が+++。 そんな バカなっ!」 +Gort Knight: Our Knights... Impossible! +$41E3A +FB A7 04 F7 04 88 04 D0 04 20 05 C1 00 54 00 52 00 4F 00 28 00 D0 00 20 01 D1 00 57 00 18 01 18 01 18 01 C3 00 37 00 56 00 3D 00 28 00 B2 00 7A 00 3D 00 71 00 25 00 C2 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 「WHITE わWHITE れWHITE らWHITE WHITE 騎WHITE 士WHITE 団WHITE がWHITE +WHITE +WHITE +WHITE 。WHITE そWHITE んWHITE なWHITE WHITE バWHITE カWHITE なWHITE っWHITE !WHITE 」WHITE | Original Japanese Text +LENGTH KBLUE NBLUE IBLUE GBLUE HBLUE TBLUE :BLUE WHITE OWHITE HWHITE WHITE NHITE OWHITE .WHITE .WHITE .WHITE WHITE IWHITE MWHITE PWHITE OWHITE SWHITE SWHITE IWHITE BWHITE LWHITE EWHITE !WHITE | New English Text +FB 14 04 17 04 12 04 10 04 11 04 1D 04 D6 04 28 00 18 00 11 00 28 00 17 00 18 00 C3 00 C3 00 C3 00 28 00 12 00 16 00 18 00 18 00 1C 00 1C 00 12 00 0B 00 15 00 0E 00 25 00 | New English Hex + +------------------------------------------------------------------------------------------ +Intro3: +ゴート騎士1 「スレイ団長!」 +Gort Knight 1: Captain Slay! +$43929 +ED A7 04 F7 04 88 04 D0 04 20 05 01 04 C1 00 81 00 9E 00 76 00 D1 00 D2 00 25 00 C2 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 1BLUE 「BLACK スBLACK レBLACK イBLACK 団BLACK 長BLACK !BLACK 」BLACK | Original Japanese Text +LENGTH K N I G H T 1 : C A P T A I N S L A Y !BLACK 長BLACK !BLACK 」BLACK | New English Text +1B 14 17 12 10 11 1D 01 D6 28 10 1B 0E 0A 1D 28 15 1C 15 0A 22 25 00 D2 00 25 00 C2 00 | New English Hex + +Intro4: +スレイ 「おまえ ひとりか っ!」 +Slay: Are you by yourself?! +$43946 +EE 81 0C 9E 0C 76 0C C1 00 2D 00 47 00 2C 00 28 00 43 00 3C 00 50 00 2E 00 71 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「BLACK おBLACK まBLACK えBLACK BLACK ひBLACK とBLACK りBLACK かBLACK っBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH S L A Y : W H Y A R E Y O U A L O N E ?BLACK っBLACK !BLACK 」BLACK | New English Text +16 1C 15 0A 22 D6 20 11 22 28 0A 1B 0E 28 22 18 1E 28 0A 15 18 17 0E 24 00 71 00 25 00 C2 00 | New English Hex + +Intro5: +ゴート騎士1 「オズワルドの 攻撃により ぶたいは ぜんめつしましたっ!」 +Gort Knight 1: Our forces have been entirely destroyed by Oswald's attacks! +$43965 (Line 1) +F2 A7 04 F7 04 88 04 D0 04 20 05 01 04 C1 00 79 00 AA 00 A0 00 9D 00 B1 00 41 00 28 00 C7 00 C8 00 3E 00 4E 00 50 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 1BLUE 「BLACK オBLACK ズBLACK ワBLACK ルBLACK ドBLACK のBLACK BLACK 攻BLACK 撃BLACK にBLACK よBLACK りBLACK | Original Japanese Text +LENGTH K N I G H T 1 : A L L O U R F O R C E S H A V E 攻BLACK 撃BLACK にBLACK よBLACK りBLACK | New English Text +1A 14 17 12 10 11 1D 01 D6 0A 15 15 28 18 1E 1B 28 0F 18 1B 0C 0E 1C 28 11 0A 1F 0E 00 C7 00 C8 00 3E 00 4E 00 50 00 | New English Hex +$4398C (Line 2) +0F 68 38 2A 42 28 5F 56 4A 3A 34 47 34 38 71 25 C2 | Original Japanese Hex +LENGTH ぶ た い は ぜ ん め つ し ま し た っ ! 」 | Original Japanese Text +LENGTH B E E N W I P E D O U T ! 」 | New English Text +0E 0B 0E 0E 17 28 20 12 19 0E 0D 28 18 1E 1D 25 C2 | New English Hex + +Intro6: +スレイ 「総督!!」 +Slay: General!! +$43F8A +E8 81 0C 9E 0C 76 0C C1 00 F3 00 F5 00 25 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「BLACK 総BLACK 督BLACK !BLACK !BLACK 」BLACK | Original Japanese Text +LENGTH S L A Y : G E N E R A L ! !BLACK 」BLACK | New English Text +0E 1C 15 0A 22 D6 28 10 0E 17 0E 1B 0A 15 25 25 00 C2 28 | New English Hex + +Intro7: +総督 「くそっ もはや これまでかっ+++」 +General: Damn it! Has it come to this already...?! +$4399D (Line 1) +E5 F3 08 F5 08 C1 00 30 00 37 00 71 00 | Original Japanese Hex +LENGTH 総GOLD 督GOLD 「BLACK くBLACK そBLACK っBLACK | Original Japanese Text +LENGTH G E N E R A L : H A S | New English Text +0B 10 0E 17 0E 1B 0A 15 D6 28 11 0A 1C | New English Hex +$439AA (Line 2) +6D 0A 0B 0C 4B 42 4C 28 32 52 47 64 2E 71 18 18 18 C2 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH も は や こ れ ま で か っ + + + 」 | Original Japanese Text +LENGTH I T C O M E T O T H I S ? ! | New English Text +10 12 1D 28 0C 18 16 0E 28 1D 18 28 1D 11 12 1C 24 25 | New English Hex + +Intro8: +ゴート騎士2 「行きましょう! 総督!」 +Gort Knight 2: General! Let us go! +$43D4E +F1 A7 04 F7 04 88 04 D0 04 20 05 02 04 C1 00 F2 00 2F 00 47 00 34 00 74 00 2B 00 25 00 F3 00 F5 00 25 00 C2 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 2BLUE 「BLACK 行BLACK きBLACK まBLACK しBLACK ょBLACK うBLACK !BLACK 総BLACK 督BLACK !BLACK 」BLACK | Original Japanese Text +LENGTH K N I G H T 2 : G E N E R A L ! L E T U S G O !BLACK 総BLACK 督BLACK !BLACK 」BLACK | New English Text +1A 14 17 12 10 11 1D 02 D6 10 0E 17 0E 1B 0A 15 25 28 15 0E 1D 28 1E 1C 28 10 18 25 00 F3 00 F5 00 25 00 C2 00 | New English Hex + +Intro9: +ゴート騎士3 「騎士団の 名にかけて!」 +Gort Knight 3: In the name of the Knights of Gort! +$43D73 +F2 A7 04 F7 04 88 04 D0 04 20 05 03 04 C1 00 D0 00 20 01 D1 00 41 00 28 00 3B 01 3E 00 2E 00 31 00 3B 00 25 00 C2 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 3BLUE 「BLACK 騎BLACK 士BLACK 団BLACK のBLACK BLACK 名BLACK にBLACK かBLACK けBLACK てBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH K N I G H T 3 : I N O U R N A M E !BLACK BLACK 名BLACK にBLACK かBLACK けBLACK てBLACK !BLACK 」BLACK | New English Text +16 14 17 12 10 11 1D 03 D6 28 12 17 28 18 1E 1B 28 17 0A 16 0E 25 00 28 00 3B 01 3E 00 2E 00 31 00 3B 00 25 00 C2 00 | New English Hex + +Intro10: +総督 「わかった みんな! 行こう!」 +General: Understood! Let us go! +$439BC +F0 F3 08 F5 08 C1 00 54 00 2E 00 71 00 38 00 28 00 48 00 56 00 3D 00 25 00 F2 00 32 00 2B 00 25 00 C2 00 | Original Japanese Hex +LENGTH 総GOLD 督GOLD 「BLACK わBLACK かBLACK っBLACK たBLACK BLACK みBLACK んBLACK なBLACK !BLACK 行BLACK こBLACK うBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH G E N E R A L : O K ! L E T S G O !BLACK !BLACK 行BLACK こBLACK うBLACK !BLACK 」BLACK | New English Text +17 10 0E 17 0E 1B 0A 15 D6 28 18 14 25 28 15 0E 1D 1C 28 10 18 25 00 25 00 F2 00 32 00 2B 00 25 00 C2 00 | New English Hex + +Intro11: +ソフィア 「パパァ」 +Sofia: Daddy! +$439DF +E8 83 0C 90 0C 5C 0D 75 0C C1 00 B7 00 B7 00 BC 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK パBLACK パBLACK ァBLACK 」BLACK | Original Japanese Text +LENGTH S O F I A : D A D D Y 。 。 。BLACK 」BLACK | New English Text +0E 1C 18 0F 12 0A D6 28 0D 0A 0D 0D 22 C3 C3 C3 00 C2 00 | New English Hex + +Intro12: +ママ 「あなたっ」 +Mother: Dear! +$439F2 +E7 93 04 93 04 C1 00 29 00 3D 00 38 00 71 00 C2 00 | Original Japanese Hex +LENGTH マBLUE マBLUE 「BLACK あBLACK なBLACK たBLACK っBLACK 」BLACK | Original Japanese Text +LENGTH M U M : M Y D E A R . . .BLACK | New English Text +0E 16 1E 16 D6 28 16 22 28 0D 0E 0A 1B C3 C3 c3 00 | New English Hex + +Intro13: +総督 「しんぱいするなっ ソフィアのことは たのんだぞ」 +General: Don't worry! Look after Sofia for me. +$43AA5 (Line 1) +EA F3 08 F5 08 C1 00 34 00 56 00 6B 00 2A 00 35 00 51 00 3D 00 71 00 | Original Japanese Hex +LENGTH 総GOLD 督GOLD 「BLACK しBLACK んBLACK ぱBLACK いBLACK すBLACK るBLACK なBLACK っBLACK | Original Japanese Text +LENGTH G E N E R A L : D O N O T W O R R Y ! | New English Text +15 10 0E 17 0E 1B 0A 15 D6 28 0D 18 28 17 18 1D 28 20 18 1B 1B 22 25 | New English Hex +$43A03 (Line 2) +2F 03 28 83 90 5C 75 41 32 3C 42 28 38 41 56 61 60 C2 | Original Japanese Hex +LENGTH Length ソ フ ィ ア の こ と は た の ん だ ぞ 」 | Original Japanese Text +LENGTH L O O K A F T E R S O F I A . | New English Text +10 15 18 18 14 28 0A 0F 1D 0E 1B 28 1C 18 0F 12 0A C3 | New English Hex + +Intro14: +ソフィア 「いっちゃ いやだっ いやだよう パパー-ァ」 +Sofia: No! Daddy, don't go! Don't go! +$43A15 (Line 1) +F3 83 0C 90 0C 5C 0D 75 0C C1 00 2A 00 71 00 39 00 72 00 28 00 2A 00 4C 00 61 00 71 00 28 00 2A 00 4C 00 61 00 4E 00 2B 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK いBLACK っBLACK ちBLACK ゃBLACK BLACK いBLACK やBLACK だBLACK っBLACK BLACK いBLACK やBLACK だBLACK よBLACK うBLACK | Original Japanese Text +LENGTH S O F I A : N O ! P L E A S E D O N T G O ! っBLACK BLACK いBLACK やBLACK だBLACK よBLACK うBLACK | New English Text +19 1C 18 0F 12 0A D6 28 17 18 25 28 19 15 0E 0A 1C 0E 28 0D 18 17 1D 28 10 19 25 71 00 28 00 2A 00 4C 00 61 00 4E 00 2B 00 | New English Hex +$43A65 (Line 2) +06 28 B7 B7 F7 26 BC C2 | Original Japanese Hex +LENGTH パ パ ー - ァ 」 | Original Japanese Text +LENGTH D A D D Y ! | New English Text +06 28 0D 0A 0D 0D 22 25 | New English Hex + +------------------------------------------------------------------------------------------ +Top Screen Intro Lines: + +TopScreen3: +スレイ 「団長スレイ 行きます!!」 +Slay: Captain Slay is here! +$43AD1 +F0 81 0C 9E 0C 76 0C C1 00 D1 00 D2 00 81 00 9E 00 76 00 28 00 F2 00 2F 00 47 00 35 00 25 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE 団WHITE 長WHITE スWHITE レWHITE イWHITE WHITE 行WHITE きWHITE まWHITE すWHITE !WHITE !WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE WHITE HWHITE EWHITE RWHITE EWHITE WHITE IWHITE WHITE GWHITE OWHITE !WHITE !WHITE | New English Text +F0 1C 0C 15 0C 0A 0C 22 0C D6 0C 28 00 11 00 0E 00 1B 00 0E 00 28 00 12 00 28 00 10 00 18 00 25 00 25 00 | New English Hex + +TopScreen4: +スレイ 「この戦いは まける。 せかいは オズワルドの手に+++」 +Slay: We're going to lose this battle. The world will fall to Oswald... +$43AF4 +FE 81 0C 9E 0C 76 0C C1 00 32 00 41 00 D7 00 2A 00 42 00 28 00 47 00 31 00 51 00 C3 00 36 00 2E 00 2A 00 42 00 28 00 79 00 AA 00 A0 00 9D 00 B1 00 41 00 40 01 3E 00 18 01 18 01 18 01 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE こWHITE のWHITE 戦WHITE いWHITE はWHITE WHITE まWHITE けWHITE るWHITE 。WHITE せWHITE かWHITE いWHITE はWHITE WHITE オWHITE ズWHITE ワWHITE ルWHITE ドWHITE のWHITE 手WHITE にWHITE +WHITE +WHITE +WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE WHITE WWHITE EWHITE RWHITE EWHITE WHITE LWHITE OWHITE SWHITE IWHITE NWHITE GWHITE WHITE TWHITE HWHITE EWHITE WHITE BWHITE AWHITE TWHITE TWHITE LWHITE EWHITE .WHITE .WHITE .WHITE | New English Text +FE 1C 0C 15 0C 0A 0C 22 0C D6 0C 28 00 20 00 0E 00 1B 00 0E 00 20 00 15 00 18 00 1C 00 12 00 17 00 10 00 28 00 1D 00 11 00 0E 00 28 00 1B 00 0A 00 1D 00 1D 00 15 00 0E 00 C3 00 C3 00 C3 00 | New English Hex + +TopScreen5: +スレイ 「総督! これいじょうの ぎせいは むいみです!」 +Slay: General! It's pointless sacrificing any more men! +$43B33 +FA 81 0C 9E 0C 76 0C C1 00 F3 00 F5 00 25 00 32 00 52 00 2A 00 5D 00 74 00 2B 00 41 00 28 00 58 00 36 00 2A 00 42 00 28 00 49 00 2A 00 48 00 64 00 35 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE 総WHITE 督WHITE !WHITE こWHITE れWHITE いWHITE じWHITE ょWHITE うWHITE のWHITE WHITE ぎWHITE せWHITE いWHITE はWHITE WHITE むWHITE いWHITE みWHITE でWHITE すWHITE !WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE GWHITE EWHITE NWHITE EWHITE RWHITE AWHITE LWHITE !WHITE WWHITE EWHITE WHITE CWHITE AWHITE NWHITE TWHITE WHITE GWHITE OWHITE WHITE OWHITE NWHITE !WHITE | New English Text +FA 1C 0C 15 0C 0A 0C 22 0C D6 0C 1C 00 1E 00 1B 00 1B 00 0E 00 17 00 0D 00 0E 00 1B 00 25 00 28 00 17 00 18 00 17 00 1C 00 0E 00 17 00 1C 00 0E 00 25 00 25 00 C2 00 | New English Hex + +TopScreen6: +総督 「だいじょうぶか? スレイ!!」 +General: Slay! Are you alright?! +$43B6A +F0 F3 08 F5 08 C1 00 61 00 2A 00 5D 00 74 00 2B 00 68 00 2E 00 24 00 81 00 9E 00 76 00 25 00 25 00 C2 00 | Original Japanese Hex +LENGTH 総GOLD 督GOLD 「WHITE だWHITE いWHITE じWHITE ょWHITE うWHITE ぶWHITE かWHITE ?WHITE スWHITE レWHITE イWHITE !WHITE !WHITE 」WHITE | Original Japanese Text +LENGTH GGOLD EGOLD NGOLD EGOLD RGOLD AGOLD LGOLD :GOLD WHITE YWHITE OWHITE UWHITE WHITE OWHITE KWHITE ?WHITE !WHITE | New English Text +F0 10 08 0E 08 17 08 0E 08 1B 08 0A 08 15 08 D6 08 28 00 22 00 18 00 1E 00 28 00 18 00 14 00 24 00 25 00 | New English Hex + +TopScreen7: +スレイ 「は いっ!! それよりはやく 村へ戻りましょう」 +Slay: Yes, sir! Never mind that, let's go to the village, now! +$43B8D +F9 81 0C 9E 0C 76 0C C1 00 42 00 2A 00 71 00 25 00 25 00 37 00 52 00 4E 00 50 00 42 00 4C 00 30 00 28 00 27 01 45 00 1A 01 50 00 47 00 34 00 74 00 2B 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE はWHITE いWHITE っWHITE !WHITE !WHITE そWHITE れWHITE よWHITE りWHITE はWHITE やWHITE くWHITE WHITE 村WHITE へWHITE 戻WHITE りWHITE まWHITE しWHITE ょWHITE うWHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE WHITE WWHITE EWHITE WHITE MWHITE UWHITE SWHITE TWHITE WHITE RWHITE EWHITE TWHITE RWHITE EWHITE AWHITE TWHITE WHITE NWHITE OWHITE WWHITE !WHITE | New English Text +F9 1C 0C 15 0C 0A 0C 22 0C D6 0C 28 00 20 00 0E 00 28 00 16 00 1E 00 1C 00 1D 00 28 00 1B 00 0E 00 1D 00 1B 00 0E 00 0A 00 1D 00 28 00 17 00 18 00 20 00 25 00 | New English Hex + +TopScreen8: +スレイ 「む りです! 総督!!」 +Slay: General! It's hopeless! +$43BC2 +ED 81 0C 9E 0C 76 0C C1 00 49 00 50 00 64 00 35 00 25 00 F3 00 F5 00 25 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE むWHITE りWHITE でWHITE すWHITE !WHITE 総WHITE 督WHITE !WHITE !WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE WHITE GWHITE EWHITE NHITE EWHITE RWHITE AWHITE LWHITE !WHITE | New English Text +ED 1C 0C 15 0C 0A 0C 22 0C D6 0C 28 00 10 00 0E 00 17 00 0E 00 1B 00 0A 00 15 00 25 00 | New English Hex + +TopScreen9: +総督 「オレにかまうな! おまえらは 村び とを ひなんさせろ!」 +General: Don't worry about me! Evacuate the village! +$43BDF +FD F3 08 F5 08 C1 00 79 00 9E 00 3E 00 28 00 2E 00 47 00 2B 00 3D 00 25 00 2D 00 47 00 2C 00 4F 00 42 00 28 00 27 01 67 00 3C 00 55 00 43 00 3D 00 56 00 33 00 36 00 53 00 25 00 C2 00 | Original Japanese Hex +LENGTH 総GOLD 督GOLD 「WHITE オWHITE レWHITE にWHITE WHITE かWHITE まWHITE うWHITE なWHITE !WHITE おWHITE まWHITE えWHITE らWHITE はWHITE WHITE 村WHITE びWHITE とWHITE をWHITE ひWHITE なWHITE んWHITE さWHITE せWHITE ろWHITE !WHITE 」WHITE | Original Japanese Text +LENGTH GGOLD EGOLD NGOLD EGOLD RGOLD AGOLD LGOLD :GOLD WHITE EWHITE VWHITE AWHITE CWHITE UWHITE AWHITE TWHITE EWHITE WHITE TWHITE HWHITE EWHITE WHITE VWHITE IWHITE LWHITE LWHITE AWHITE GWHITE EWHITE !WHITE | New English Text +FD 10 08 0E 08 17 08 0E 08 1B 08 0A 08 15 08 D6 08 28 00 0E 00 1F 00 0A 00 0C 00 1E 00 0A 00 1D 00 0E 00 28 00 1D 00 11 00 0E 00 28 00 1F 00 12 00 15 00 15 00 0A 00 10 00 0E 00 25 00 | New English Hex + +TopScreen10: +スレイ 「戻ってください! むすめさんの ためにも!」 +Slay: Come back! Do it for your daughter! +$43C1C +F8 81 0C 9E 0C 76 0C C1 00 1A 01 71 00 3B 00 30 00 61 00 33 00 2A 00 25 00 49 00 35 00 4A 00 33 00 56 00 41 00 28 00 38 00 4A 00 3E 00 4B 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE 戻WHITE っWHITE てWHITE くWHITE だWHITE さWHITE いWHITE !WHITE むWHITE すWHITE めWHITE さWHITE んWHITE のWHITE WHITE たWHITE めWHITE にWHITE もWHITE !WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE CWHITE OWHITE MWHITE EWHITE WHITE BWHITE AWHITE CWHITE KWHITE ,WHITE FWHITE OWHITE RWHITE WHITE SWHITE OWHITE FWHITE IWHITE AWHITE !WHITE | New English Text +F8 1C 0C 15 0C 0A 0C 22 0C D6 0C 0C 00 18 00 16 00 0E 00 28 00 0B 00 0A 00 0C 00 14 00 C4 00 0F 00 18 00 1B 00 20 00 1C 00 18 00 0F 00 12 00 0A 00 25 00 | New English Hex + +TopScreen11: +スレイ 「戻ろう。 ふたりで たちうちできる敵じゃない!」 +Slay: Let's go back. We can't just beat them with just the two of us! +$43C4F +FA 81 0C 9E 0C 76 0C C1 00 1A 01 53 00 2B 00 C3 00 44 00 38 00 50 00 64 00 28 00 38 00 39 00 2B 00 39 00 64 00 2F 00 51 00 39 01 5D 00 72 00 3D 00 2A 00 25 00 C2 00 | Original Japanese Hex +LENGTH スORANGE レORANGE イORANGE 「WHITE 戻WHITE ろWHITE うWHITE 。WHITE ふWHITE たWHITE りWHITE でWHITE WHITE たWHITE ちWHITE うWHITE ちWHITE でWHITE きWHITE るWHITE 敵WHITE じWHITE ゃWHITE なWHITE いWHITE !WHITE 」WHITE | Original Japanese Text +LENGTH SORANGE LORANGE AORANGE YORANGE :ORANGE CWHITE AWHITE NWHITE TWHITE WHITE WWHITE IWHITE NWHITE ,WHITE LWHITE EWHITE TWHITE SWHITE WHITE GWHITE OWHITE WHITE BWHITE AWHITE CWHITE KWHITE .WHITE | New English Text +FA 1C 0C 15 0C 0A 0C 22 0C D6 0C 0C 00 0A 00 17 00 1D 00 28 00 20 00 12 00 17 00 C4 00 15 00 0E 00 1D 00 1C 00 28 00 10 00 18 00 28 00 0B 00 0A 00 0C 00 14 00 C3 00 | New English Hex + +TopScreen12: +ゴート騎士 「は いっ。 われわれで 村びとを ひなんさせなければ」 +Gort Knight: Yes, sir! We must evacuate the villagers! +$43C86 +FE A7 04 F7 04 88 04 D0 04 20 05 C1 00 42 00 2A 00 71 00 C3 00 54 00 52 00 54 00 52 00 64 00 28 00 27 01 67 00 3C 00 55 00 28 00 43 00 3D 00 56 00 33 00 36 00 3D 00 31 00 52 00 66 00 C2 00 | Original Japanese Hex +LENGTH ゴBLUE ーBLUE トBLUE 騎BLUE 士BLUE 「WHITE はWHITE いWHITE っWHITE 。WHITE わWHITE れWHITE わWHITE れWHITE でWHITE WHITE 村WHITE びWHITE とWHITE をWHITE WHITE ひWHITE なWHITE んWHITE さWHITE せWHITE なWHITE けWHITE れWHITE ばWHITE 」WHITE | Original Japanese Text +LENGTH KBLUE NBLUE IBLUE GBLUE HBLUE TBLUE :BLUE MWHITE UWHITE SWHITE TWHITE WHITE EWHITE VWHITE AWHITE CWHITE UWHITE AWHITE TWHITE EWHITE WHITE VWHITE IWHITE LWHITE LWHITE AWHITE GWHITE EWHITE RWHITE SWHITE !WHITE | New English Text +FE 14 04 17 04 12 04 10 04 11 04 1D 04 D6 04 16 00 1E 00 1C 00 1D 00 28 00 0E 00 1F 00 0A 00 0C 00 1E 00 0A 00 1D 00 0E 00 28 00 1F 00 12 00 15 00 15 00 0A 00 10 00 0E 00 1B 00 1C 00 25 00 | New English Hex + +------------------------------------------------------------------------------------------ +Intro15: +ソフィア 「ねぇ おじちゃん。 パパは?」 +Sophia: Mister, where's Daddy? +$43A3E +F2 83 0C 90 0C 5C 0D 75 0C C1 00 40 00 5D 01 28 00 2D 00 5D 00 39 00 72 00 56 00 C3 00 B7 00 B7 00 42 00 24 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK ねBLACK ぇBLACK BLACK おBLACK じBLACK ちBLACK ゃBLACK んBLACK 。BLACK パBLACK パBLACK はBLACK ?BLACK 」BLACK | Original Japanese Text +LENGTH S O F I A : W H E R E S M Y D A D D Y ?BLACK んBLACK 。BLACK パBLACK パBLACK はBLACK ?BLACK 」BLACK | New English Text +16 1C 18 0F 12 0A D6 28 20 11 0E 1B 0E 1C 28 16 22 28 0D 0A 0D 0D 22 24 00 56 00 C3 00 B7 00 B7 00 42 00 24 00 C2 00 | New English Hex + +Intro16: +スレイ 「+++++」 +Slay: ... +$43A90 +E9 81 0C 9E 0C 76 0C C1 00 18 01 18 01 18 01 18 01 18 01 C2 00 | Original Japanese Hex +LENGTH スRED レRED イRED 「BLACK +BLACK +BLACK +BLACK +BLACK +BLACK 」BLACK | Original Japanese Text +LENGTH SRED LRED ARED YRED :RED BLACK .BLACK .BLACK .BLACK .BLACK | New English Text +E9 1C 0C 15 0C 0A 0C 22 0C D6 0C 28 00 C3 00 C3 00 C3 00 C3 00 | New English Hex + +Intro17: +ソフィア 「パパーーァ どこなのっ? パパー-ァ」 +Sophia: Daddy! Where are you?! Daddy! +$43CC5 (Line 1) +F0 83 0C 90 0C 5C 0D 75 0C C1 00 B7 00 B7 00 F7 00 26 00 BC 00 28 00 65 00 32 00 3D 00 41 00 71 00 24 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK パBLACK パBLACK ーBLACK ーBLACK ァBLACK BLACK どBLACK こBLACK なBLACK のBLACK っBLACK ?BLACK | Original Japanese Text +LENGTH S O F I A : W H E R E A R E Y O U . . . ? こBLACK なBLACK のBLACK っBLACK ?BLACK | New English Text +16 1C 18 0F 12 0A D6 20 11 0E 1B 0E 28 0A 1B 0E 28 22 18 1E C3 C3 C3 24 00 32 00 3D 00 41 00 71 00 24 00 | New English Hex +$43A65 (Line 2) +06 28 B7 B7 F7 26 BC C2 | Original Japanese Hex +LENGTH パ パ ー - ァ 」 | Original Japanese Text +LENGTH D A D D Y ! | New English Text +06 28 0D 0A 0D 0D 22 25 | New English Hex + +Intro18: +オズワルド 「水晶は どこだ!」 +Oswald: Where's the Crystal?! +$43D9A +EE 79 0C AA 0C A0 0C 9D 0C B1 0C C1 00 DD 00 DE 00 42 00 28 00 65 00 32 00 61 00 25 00 C2 00 | Original Japanese Hex +LENGTH オRED ズRED ワRED ルRED ドRED 「BLACK 水BLACK 晶BLACK はBLACK BLACK どBLACK こBLACK だBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH O S W A L D : C R Y S T A L ?BLACK はBLACK BLACK どBLACK こBLACK だBLACK !BLACK 」BLACK | New English Text +0E 18 1C 20 0A 15 0D D6 0C 1B 22 1C 1D 0A 15 24 00 42 00 28 00 65 00 32 00 61 00 25 00 C2 00 | New English Hex + +Intro19: +オズワルド 「おまえ、 魔導の 血を ひいているようだな」 +Oswald: You seem to have magic in your blood... +$43DB9 +FA 79 0C AA 0C A0 0C 9D 0C B1 0C C1 00 2D 00 47 00 2C 00 C4 00 E0 00 E5 00 41 00 28 00 E8 00 55 00 28 00 43 00 2A 00 3B 00 2A 00 51 00 4E 00 2B 00 61 00 3D 00 C2 00 | Original Japanese Hex +LENGTH オRED ズRED ワRED ルRED ドRED 「BLACK おBLACK まBLACK えBLACK 、BLACK 魔BLACK 導BLACK のBLACK BLACK 血BLACK をBLACK BLACK ひBLACK いBLACK てBLACK いBLACK るBLACK よBLACK うBLACK だBLACK なBLACK 」BLACK | Original Japanese Text +LENGTH O S W A L D : Y O U P O S S E S S M A G I C . . . 血BLACK をBLACK BLACK ひBLACK いBLACK てBLACK いBLACK るBLACK よBLACK うBLACK だBLACK なBLACK 」BLACK | New English Text +1A 18 1C 20 0A 15 0D D6 22 18 1E 28 19 18 1C 1C 0E 1C 1C 28 16 0A 10 12 0C C3 C3 C3 00 E8 00 55 00 28 00 43 00 2A 00 3B 00 2A 00 51 00 4E 00 2B 00 61 00 3D 00 C2 00 | New English Hex + +Intro20: +ソフィア 「ママー------ァ」 +Sophia: MUMMY!! +$43CE8 +EF 83 0C 90 0C 5C 0D 75 0C C1 00 93 00 93 00 F7 00 26 00 26 00 26 00 26 00 26 00 26 00 BC 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK マBLACK マBLACK ーBLACK -BLACK -BLACK -BLACK -BLACK -BLACK -BLACK ァBLACK 」BLACK | Original Japanese Text +LENGTH SRED ORED FRED IRED ARED :RED BLACK MBLACK UBLACK MBLACK -BLACK -BLACK -BLACK MBLACK YBLACK !BLACK | New English Text +EF 1C 0C 18 0C 0F 0C 12 0C 0A 0C D6 0C 28 00 16 00 1E 00 16 00 26 00 26 00 26 00 16 00 22 00 25 00 | New English Hex + +Intro21: +ソフィア 「ママを かえ して!」 +Sophia: Give me back my mummy! +$43E46 +EE 83 0C 90 0C 5C 0D 75 0C C1 00 93 00 93 00 55 00 28 00 2E 00 2C 00 34 00 3B 00 25 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK マBLACK マBLACK をBLACK BLACK かBLACK えBLACK しBLACK てBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH S O F I A : G I V E B A C K M Y M U M M Y ! !BLACK 」BLACK | New English Text +19 1C 18 0F 12 0A D6 28 10 12 1F 0E 28 0B 0A 0C 14 28 16 22 28 16 1E 16 16 22 25 25 00 C2 00 | New English Hex + +Intro22: +---10ねんの ときが ながれる--- +---10 years pass--- +$438FC +13 26 26 26 01 00 40 56 41 28 3C 2F 57 28 3D 57 52 51 26 26 26 | Original Japanese Hex +LENGTH - - - 1 0 ね ん の と き が な が れ る - - - | Original Japanese Text +LENGTH - - - 1 0 Y E A R S L A T E R - - - | New English Text +13 26 26 26 01 00 28 22 0E 0A 1B 1C 28 15 0A 1D 0E 1B 26 26 26 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Items.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Items.txt new file mode 100644 index 00000000..95605ba8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Items.txt @@ -0,0 +1,98 @@ +------- +Items: +------- +タマゴ +Egg +$4100E +02 84 93 A7 | Original Japanese Hex +LENGTH タ マ ゴ | Original Japanese Text +LENGTH E G G | New English Text +02 0E 10 10 | New English Hex + +ねがいのともしび +Wish Of Light / There are lights in the root +$412EA +07 40 57 2A 41 3C 4B 34 67 | Original Japanese Hex +LENGTH ね が い の と も し び | Original Japanese Text +LENGTH D A Y L I G H T | New English Text +07 0D 0A 22 15 12 10 11 1D | New English Hex + +ゴートの鬼い +Gort only +$416DB +25 04 A7 F7 88 41 3D 2A | Original Japanese Hex +LENGTH LENGTH ゴ ー ト の 鬼 い | Original Japanese Text +LENGTH G R T W A R P | New English Text +06 10 1B 1D 20 0A 1B 19 | New English Hex + +ゴーレムの頭 +Head of the Golem +$41764 +25 05 A7 F7 9E 95 41 43 | Original Japanese Hex +LENGTH LENGTH ゴ ー レ ム の 頭 | Original Japanese Text +LENGTH G L . H E A D | New English Text +06 10 15 C3 11 0E 0A 0D | New English Hex + +王のてがみ +Letter of the king +$4176C +04 EB 41 3B 57 48 | Original Japanese Hex +LENGTH 王 の て が み | Original Japanese Text +LENGTH L E T T R | New English Text +04 15 0E 1D 1D 1B | New English Hex + +ノイラートの鬼い +Neurath only +$41772 +27 06 8D 76 9B F7 88 41 3D 2A | Original Japanese Hex +LENGTH LENGTH ノ イ ラ ー ト の 鬼 い | Original Japanese Text +LENGTH N E U R A W A R P | New English Text +08 17 0E 1E 1B 0A 20 0A 1B 19 | New English Hex + +かげのゆびわ +Ring shadow +$417A2 +05 2E 5A 41 4D 67 54 | Original Japanese Hex +LENGTH か げ の ゆ び わ | Original Japanese Text +LENGTH S H A D O W | New English Text +05 1C 11 0A 0D 18 20 | New English Hex + +薬草 +Medicinal herb +$4183D +41 00 01 67 1F | Original Japanese Hex +LENGTH LENGTH LENGTH 薬 草 | Original Japanese Text +LENGTH H E R B | New English Text +03 11 0E 1B 0B | New English Hex + +目ざまし草 +Awakening +$41842 +44 00 04 52 5C 47 34 1F | Original Japanese Hex +LENGTH LENGTH LENGTH 目 ざ ま し 草 | Original Japanese Text +LENGTH A W A K E N 草 | New English Text +06 0A 20 0A 14 0E 17 1F | New English Hex + +チベリスの鬼い +Heart of Chiberus +$4184A +26 05 85 B5 9C 81 41 3D 2A | Original Japanese Hex +LENGTH LENGTH チ ベ リ ス の 鬼 い | Original Japanese Text +LENGTH C H I B W A R P | New English Text +07 0C 11 12 0B 20 0A 1B 19 | New English Hex + +ふしぎな果物 +Strange Fruit +$41853 +45 04 05 44 34 58 3D 34 33 | Original Japanese Hex +LENGTH LENGTH LENGTH ふ し ぎ な 果 物 | Original Japanese Text +LENGTH O D D F R U I T | New English Text +07 18 0D 0D 0F 1B 1E 12 1D | New English Hex + +なにを うりますか かいますか +What action, To sell, To buy +$438A4 $438A8 $438AE +02 3D 3E 55 04 2B 50 47 35 2E 04 2E 2A 47 35 2E | Original Japanese Hex +LENGTH な に を LENGTH う り ま す か LENGTH か い ま す か | Original Japanese Text +LENGTH T O : S E L L ? B U Y ? か | New English Text +02 1D 18 D6 04 1C 0E 15 15 24 03 0B 1E 22 24 2E | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/LocationNames.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/LocationNames.txt new file mode 100644 index 00000000..e4498272 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/LocationNames.txt @@ -0,0 +1,26 @@ +------- +Towns: +------- +チベリス +Chiberus / Chiberis +$41983 +03 85 B5 9C 81 | Original Japanese Hex +LENGTH チ ベ リ ス | Original Japanese Text +LENGTH C H I B | New English Text +03 0C 11 12 0B | New English Hex + +ゴート +Gort / Goto +$41988 +02 A7 F7 88 | Original Japanese Hex +LENGTH ゴ ー ト | Original Japanese Text +LENGTH G R T | New English Text +02 10 1B 1D | New English Hex + +ノイラート +Neurath / Noirato +$41997 +04 8D 76 9B F7 88 | Original Japanese Hex +LENGTH ノ イ ラ ー ト | Original Japanese Text +LENGTH N E U R A | New English Text +04 17 0E 1E 1B 0A | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Map.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Map.txt new file mode 100644 index 00000000..b0f33875 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Map.txt @@ -0,0 +1,126 @@ +-------------- +Map Messages: +-------------- +横 +Horizontal (Top Half) +$4E69E +05 22 | Original Japanese Hex +横WHITE | Original Japanese Text +XWHITE | New English Text +41 20 | New English Hex + Horizontal (Bottom Half) + $4E6A4 + 15 22 | Original Japanese Hex + 横WHITE | Original Japanese Text + XWHITE | New English Text + 51 20 | New English Hex + 0x4E6DF changes blue numbers + +縦 +Vertical (Top Half) +$4E711 +04 22 | Original Japanese Hex +縦WHITE | Original Japanese Text +YWHITE | New English Text +42 20 | New English Hex + Vertical (Bottom Half) + $4E717 + 14 22 | Original Japanese Hex + 縦WHITE | Original Japanese Text + YWHITE | New English Text + 52 20 | New English Hex + +拔大マップ +Draw Out Large Map +$40E20 +E8 28 00 01 09 02 09 93 08 BD 08 B9 08 28 00 28 00 28 00 | Original Japanese Hex +LENGTH 拔GOLD 大GOLD マGOLD ッGOLD プGOLD | Original Japanese Text +LENGTH MGOLD AGOLD PGOLD VGOLD IGOLD EGOLD WGOLD | New English Text +E7 16 08 0A 08 19 08 28 00 1F 08 12 08 0E 08 20 08 28 00 | New English Hex + +------------------- +Map Terrain Types: +------------------- +地形: +Terrain: (Uses Only Top Half Of Letters) +$4E605 $4E612 $4E61F +AF 21 07 22 A6 21 | Original Japanese Hex +地WHITE 形WHITE :WHITE | Original Japanese Text +TWHITE PWHITE :WHITE | New English Text +2D 20 29 20 A6 21 | New English Hex + +平野 +Plain / Open Field (Uses Only Top Half Of Letters) +$00A24 $00A26 $00A28 $00A2A +48 24 24 26 48 24 25 26 | Original Japanese Hex +BLUE 平BLUE BLUE 野BLUE | Original Japanese Text +LBLUE ABLUE NBLUE DBLUE | New English Text +25 24 0A 24 27 24 0D 24 | New English Hex + +森林 +Forest / Wood (Uses Only Top Half Of Letters) +$00A2C $00A2E $00A30 $00A32 +48 24 27 26 48 24 06 26 | Original Japanese Hex +BLUE 森BLUE BLUE 林BLUE | Original Japanese Text +WBLUE OBLUE OBLUE DBLUE | New English Text +40 24 28 24 28 24 0D 24 | New English Hex + +砂地 +Sand (Uses Only Top Half Of Letters) +$00A34 $00A36 $00A38 $00A3A +48 24 26 26 48 24 AF 25 | Original Japanese Hex +BLUE 砂BLUE BLUE 地BLUE | Original Japanese Text +SBLUE ABLUE NBLUE DBLUE | New English Text +2C 24 0A 24 27 24 0D 24 | New English Hex + +道路 +Road / Highway (Uses Only Top Half Of Letters) +$00A44 $00A46 $00A48 $00A4A +48 24 20 26 48 24 21 26 | Original Japanese Hex +BLUE 道BLUE BLUE 路BLUE | Original Japanese Text +RBLUE OBLUE ABLUE DBLUE | New English Text +2B 24 28 24 0A 24 0D 24 | New English Hex + +山岳 +Mountains (Uses Only Top Half Of Letters) +$00A4C $00A4E $00A50 $00A52 +48 24 23 26 48 24 41 26 | Original Japanese Hex +BLUE 山BLUE BLUE 岳BLUE | Original Japanese Text +RBLUE OBLUE CBLUE KBLUE | New English Text +2B 24 28 24 0C 24 24 24 | New English Hex + +海 +Sea (Uses Only Top Half Of Letters) +$00A64 $00A66 $00A68 $00A6A +48 24 22 26 48 24 48 24 | Original Japanese Hex +BLUE 海BLUE BLUE BLUE | Original Japanese Text +SBLUE EBLUE ABLUE BLUE | New English Text +2C 24 0E 24 0A 24 48 24 | New English Hex + +地形効果率 +Terrain/Topographic effect factor/ratio (Top Half) +$4E789 $4E795 $4E7A1 $4E7AD $4E7B9 +AF 29 07 2A 4F 2A 64 2A A8 2A | Original Japanese Hex +地GOLD 形GOLD 効GOLD 果GOLD 率GOLD | Original Japanese Text +RGOLD AGOLD TGOLD IGOLD OGOLD | New English Text +2B 28 0A 28 2D 28 22 28 28 28 | New English Hex + Terrain/Topographic effect factor/ratio (Bottom Half) + $4E78F $4E79B $4E7A7 $4E7B3 $4E7BF + BF 29 17 2A 5F 2A 74 2A B8 2A | Original Japanese Hex + 地GOLD 形GOLD 効GOLD 果GOLD 率GOLD | Original Japanese Text + RGOLD AGOLD TGOLD IGOLD OGOLD | New English Text + 3B 28 1A 28 3D 28 32 28 38 28 | New English Hex + + +($4E67B Changes The Space Between The Terrain Explanation) + +-------------------- +Map Monster Status: +-------------------- +敵 です +Enemy +$40E47 +23 00 39 28 64 35 | Original Japanese Hex +LENGTH LENGTH 敵 で す | Original Japanese Text +LENGTH E N E M Y | New English Text +04 0E 17 0E 16 22 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterNames.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterNames.txt new file mode 100644 index 00000000..4f9f2003 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterNames.txt @@ -0,0 +1,101 @@ +--------------- +Boss Monsters: +--------------- +ゴーレム +Golem +$40CBA +03 A7 F7 9E 95 | Original Japanese Hex +LENGTH ゴ ー レ ム | Original Japanese Text +LENGTH G O L M | New English Text +03 10 18 15 16 | New English Hex + +レッサーデーモン +Lesser Demon / Laser Demon +$418D0 +07 9E BD 7F F7 B0 F7 97 A2 | Original Japanese Hex +LENGTH レ ッ サ ー デ ー モ ン | Original Japanese Text +LENGTH L O . D E M O N | New English Text +07 15 18 C3 0D 0E 16 18 17 | New English Hex + +ハーピー +Harpy +$43A8B +03 8E F7 B8 F7 | Original Japanese Hex +LENGTH ハ ー ピ ー | Original Japanese Text +LENGTH H A R P | New English Text +03 11 0A 1B 19 | New English Hex + +----------------- +Normal Monsters: +----------------- +スケルトン +Skeleton +$40C9E +04 81 7D 9D 88 A2 | Original Japanese Hex +LENGTH ス ケ ル ト ン | Original Japanese Text +LENGTH S K E L T | New English Text +04 1C 14 0E 15 1D | New English Hex + +ローパー +Roper +$40CAC +03 9F F7 B7 F7 | Original Japanese Hex +LENGTH ロ ー パ ー | Original Japanese Text +LENGTH R O P E | New English Text +03 1B 18 19 0E | New English Hex + +ガーゴイル +Gargoyle +$40CDB +04 A3 F7 A7 76 9D | Original Japanese Hex +LENGTH ガ ー ゴ イ ル | Original Japanese Text +LENGTH G A R G O | New English Text +04 10 0A 1B 10 18 | New English Hex + +ゴブリン +Goblin +$40CE1 +03 A7 B4 9C A2 | Original Japanese Hex +LENGTH ゴ ブ リ ン | Original Japanese Text +LENGTH G O B L | New English Text +03 10 18 0B 15 | New English Hex + +おおこうもり +Fruit Bat / Flying Fox +$4189A +05 2D 2D 32 2B 4B 50 | Original Japanese Hex +LENGTH お お こ う も り | Original Japanese Text +LENGTH F R U B A T | New English Text +05 0F 1B 1E 0B 0A 1D | New English Hex + +リザード マン +Lizard Man +$418A6 +05 9C A8 26 B1 93 A2 | Original Japanese Hex +LENGTH リ ザ ー ド マ ン | Original Japanese Text +LENGTH L I Z M A N | New English Text +05 15 12 23 16 0A 17 | New English Hex + +ドラゴン +Dragon +$418AD +03 B1 9B A7 A2 | Original Japanese Hex +LENGTH ド ラ ゴ ン | Original Japanese Text +LENGTH D R A G | New English Text +03 0D 1B 0A 10 | New English Hex + +レッドローパー +Red Roper +$47A25 +06 9E BD B1 9F F7 B7 F7 | Original Japanese Hex +LENGTH レ ッ ド ロ ー パ ー | Original Japanese Text +LENGTH R E D R O P E | New English Text +06 1B 0E 0D 1B 18 19 0E | New English Hex + +マントスカル +Skull Cloak +$47A33 +05 93 A2 88 81 7A 9D | Original Japanese Hex +LENGTH マ ン ト ス カ ル | Original Japanese Text +LENGTH S K U L L C | New English Text +05 1C 14 1E 15 15 0C | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterSpells.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterSpells.txt new file mode 100644 index 00000000..8d8d5abb --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/MonsterSpells.txt @@ -0,0 +1,21 @@ +-------------------- +Boss Monster Magic: +-------------------- +------- +Golem: +------- +間接攻撃 +Shock indirect attack +$418E0 +43 00 01 55 56 C7 C8 | Original Japanese Hex +LENGTH LENGTH LENGTH 間 接 攻 撃 | Original Japanese Text +LENGTH S H O C 攻 撃 | New English Text +03 1D 11 18 0C C7 C8 | New English Hex + +間接攻撃 +Shock indirect attack +$418E7 +E3 55 19 56 19 C7 18 C8 18 | Original Japanese Hex +LENGTH 間WHITE 接WHITE 攻WHITE 撃WHITE | Original Japanese Text +LENGTH SWHITE HWHITE OWHITE CWHITE | New English Text +E3 1D 18 11 18 18 18 0C 18 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 01 - Chiberus.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 01 - Chiberus.txt new file mode 100644 index 00000000..d302095e --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 01 - Chiberus.txt @@ -0,0 +1,972 @@ +--------------- +Chiberus Town: +--------------- +-------------------------- +Chiberus - Start Of Game: +-------------------------- +はは 「10ねんまえの はなしを ききたい? アルバート」 +Mother: Albert want to hear the story of 10 years ago? +$44619 (Line 1) +FA 42 0C 42 0C C1 00 01 00 00 00 40 00 56 00 47 00 2C 00 41 00 28 00 42 00 3D 00 34 00 55 00 28 00 2F 00 2F 00 38 00 2A 00 24 00 75 00 9D 00 B2 00 F7 00 88 00 C2 00 | Original Japanese Hex +LENGTH はRED はRED 「BLACK 1BLACK 0BLACK ねBLACK んBLACK まBLACK えBLACK のBLACK BLACK はBLACK なBLACK しBLACK をBLACK BLACK きBLACK きBLACK たBLACK いBLACK ?BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK 」BLACK | Original Japanese Text +LENGTH MRED URED MRED :RED WBLACK ABLACK NBLACK TBLACK BLACK TBLACK OBLACK BLACK HBLACK EBLACK ABLACK RBLACK BLACK TBLACK HBLACK EBLACK BLACK SBLACK TBLACK OBLACK RBLACK YBLACK ?BLACK | New English Text +FA 16 0C 1E 0C 16 0C D6 00 20 00 0A 00 17 00 1D 00 28 00 1D 00 18 00 28 00 11 00 0E 00 0A 00 1B 00 28 00 1D 00 11 00 0E 00 28 00 1C 00 1D 00 18 00 1B 00 22 00 24 00 | New English Hex + + はい + Yes + $4379B (Line 2) + 02 28 42 2A | Original Japanese Hex + LENGTH は い | Original Japanese Text + LENGTH O K | New English Text + 02 28 18 14 | New English Hex + + いいえ + No + $4379F (Line 3) + 03 28 2A 2A 2C | Original Japanese Hex + LENGTH い い え | Original Japanese Text + LENGTH N O え | New English Text + 02 28 17 18 2C | New English Hex + +Yes Selected: +グローバスふっかつの かぎ 「水晶」を もとめ 大魔導師オズワルドは しんりゃくを はじめたのよ +The great mage Oswald began the invasion to seek the Crystal, key to the revival of Globus. +$43911 (Line 1) (Taken From Intro) +16 A5 9F F7 B2 81 44 71 2E 3A 41 28 2E 58 28 C1 DD DE C2 55 28 4B 3C 4A | Original Japanese Hex +LENGTH グ ロ ー バ ス ふ っ か つ の か ぎ 「 水 晶 」 を も と め | Original Japanese Text +LENGTH T H E M A G E O S W A L D I N V A D E D | New English Text +16 1D 11 0E 28 17 0A 10 0E 28 18 1C 20 0A 15 0D 28 12 17 1F 0A 0D 0E 0D | New English Hex +$44674 (Line 2) +37 00 02 E0 E5 DA 79 AA A0 9D B1 42 28 34 56 50 72 30 55 28 42 5D 4A 38 41 4E | Original Japanese Hex +LENGTH LENGTH 大 魔 導 師 オ ズ ワ ル ド は し ん り ゃ く を は じ め た の よ | Original Japanese Text +LENGTH S E E K I N G T O R E V I V E G L O B U S . | New English Text +18 1C 0E 0E 14 12 17 10 28 1D 11 0E 1B 0E 1F 12 1F 0E 28 10 15 18 0B 1E 1C C3 | New English Hex + +No Selected: +あしたで あなたは16さいね きょうはゆっくり 体をやすめるといいわ +Tomorrow you are 16 today is gonna be a good conceptual and rest your body slowly. +$44650 (Line 1) +0D 29 34 38 64 28 29 3D 38 42 01 06 33 2A 40 | Original Japanese Hex +LENGTH あ し た で あ な た は 1 6 さ い ね | Original Japanese Text +LENGTH T O M O R R O W Y O U R E | New English Text +0D 1D 18 16 18 1B 1B 18 20 28 22 18 1E 1B 0E | New English Hex +$4465F (Line 2) +32 09 2F 74 2B 42 4D 71 30 50 28 45 55 4C 35 4A 51 3C 2A 2A 54 | Original Japanese Hex +LENGTH LENGTH き ょ う は ゆ っ く り 体 を や す め る と い い わ | Original Japanese Text +LENGTH 1 6 , Y O U M U S T R E S T U P . | New English Text +13 01 06 C4 22 18 1E 28 16 1E 1C 1D 28 1B 0E 1C 1D 28 1E 19 C3 | New English Hex + +司祭 「どうなされたっ! しっかりせんか」 +Priest: been standing there! Or not good. +$43E1F +F2 F8 0C EC 0C C1 00 65 00 2B 00 3D 00 33 00 52 00 38 00 71 00 25 00 34 00 71 00 2E 00 50 00 36 00 56 00 2E 00 C2 00 | Original Japanese Hex +LENGTH 司RED 祭RED 「BLACK どBLACK うBLACK なBLACK さBLACK れBLACK たBLACK っBLACK !BLACK しBLACK っBLACK かBLACK りBLACK せBLACK んBLACK かBLACK 」BLACK | Original Japanese Text +LENGTH P R I E S T : O H N O ! W H O S T H I S ? っBLACK かBLACK りBLACK せBLACK んBLACK かBLACK 」BLACK | New English Text +16 19 1B 12 0E 1C 1D D6 18 11 28 17 18 25 20 11 18 1C 28 1D 11 12 1C 24 00 71 00 2E 00 50 00 36 00 56 00 2E 00 C2 00 |New English Hex + +---あらし の よる が あけた--- +Storm Night And to dawn/ to grow light +$43EA9 +11 26 26 26 29 4F 34 41 28 4E 51 57 28 29 31 38 26 26 26 | Original Japanese Hex +LENGTH - - - あ ら し の よ る が あ け た - - - | Original Japanese Text +LENGTH - - - T H E N E X T D A Y - - - | New English Text +11 26 26 26 1D 11 0E 28 17 0E 21 1D 28 0D 0A 22 26 26 26 | New English Hex + +はは 「おきなさい アルバート」 +Mother: Wake up Albert +$43E65 +EE 42 0C 42 0C C1 00 2D 00 2F 00 3D 00 33 00 2A 00 28 00 75 00 9D 00 B2 00 F7 00 88 00 C2 00 | Original Japanese Hex +LENGTH はRED はRED 「BLACK おBLACK きBLACK なBLACK さBLACK いBLACK BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK 」BLACK | Original Japanese Text +LENGTH MRED URED MRED :RED BLACK WBLACK ABLACK KBLACK EBLACK BLACK UBLACK PBLACK .BLACK .BLACK .BLACK | New English Text +EB 16 0C 1E 0C 16 0C D6 00 28 00 20 00 0A 00 14 00 0E 00 28 00 1E 00 19 00 C3 00 C3 00 C3 00 | New English Hex + +はは 「アルバート あ なた は もう 16さい」 +Mother: Albert you are already 16 years old +$41C7B +F3 42 0C 42 0C C1 00 75 00 9D 00 B2 00 F7 00 88 00 28 00 29 00 3D 00 38 00 42 00 4B 00 2B 00 01 00 06 00 33 00 2A 00 C2 00 | Original Japanese Hex +LENGTH はRED はRED 「BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK BLACK あBLACK なBLACK たBLACK はBLACK もBLACK うBLACK 1BLACK 6BLACK さBLACK いBLACK 」BLACK | Original Japanese Text +LENGTH MRED URED MRED :RED BLACK NBLACK OBLACK WBLACK BLACK YBLACK OBLACK UBLACK BLACK ABLACK RBLACK EBLACK BLACK 1BLACK 6BLACK 」BLACK | New English Text +F2 16 0C 1E 0C 16 0C D6 0C 28 00 17 00 18 00 20 000 0B 00 22 00 18 00 1E 00 0B 00 0A 00 1B 00 0E 00 28 00 01 00 06 00 C2 00 | New English Hex + +勇者の血を うけつぐ者の ならわしとして ひとりだち せねば なりません +You must not stand alone as the practice of those who inherit the blood of the brave +$41CA4 (Line 1) +13 EF E7 41 E8 55 28 2B 31 3A 59 E7 41 28 3D 4F 54 34 3C 34 3B | Original Japanese Hex +LENGTH 勇 者 の 血 を う け つ ぐ 者 の な ら わ し と し て | Original Japanese Text +LENGTH Y O U I N H E R I T T H E H E R O | New English Text +13 22 18 1E 28 12 17 11 0E 1B 12 1D 28 1D 11 0E 28 11 0E 1B 18 | New English Hex +$43E99 (Line 2) +0E 43 3C 50 61 39 28 36 40 66 28 3D 50 47 36 56 | Original Japanese Hex +LENGTH ひ と り だ ち せ ね ば な り ま せ ん | Original Japanese Text +LENGTH S W O R D H E I R L O O M . | New English Text +0E 1C 20 18 1B 0D 28 11 0E 12 1B 15 18 18 16 C3 | New English Hex + +はは 「これは、このいえの かほう 勇者の剣です それと$1000。特って 行きなさい」 +Mother: This is a specialized $ 1000 I go. with it is the Sword of the Valiant heirloom of the house +$43DF0 (Line 1) +F6 42 0C 42 0C C1 00 32 00 52 00 42 00 C4 00 32 00 41 00 2A 00 2C 00 41 00 28 00 2E 00 46 00 2B 00 28 00 EF 00 E7 00 41 00 D8 00 64 00 35 00 | Original Japanese Hex +LENGTH はRED はRED 「BLACK こBLACK れBLACK はBLACK 、BLACK こBLACK のBLACK いBLACK えBLACK のBLACK BLACK かBLACK ほBLACK うBLACK BLACK 勇BLACK 者BLACK のBLACK 剣BLACK でBLACK すBLACK | Original Japanese Text +LENGTH MRED URED MRED :RED BLACK HBLACK EBLACK RBLACK EBLACK SBLACK BLACK $BLACK 1BLACK 0BLACK 0BLACK 0BLACK BLACK IBLACK BLACK HBLACK ABLACK VBLACK EBLACK | New English Text +F6 16 0C 1E 0C 16 0C D6 0C 28 00 11 00 0E 00 1B 00 0E 00 1C 00 28 00 F6 00 01 00 00 00 00 00 00 00 28 00 12 00 28 00 11 00 0A 00 1F 00 0E 00 | New English Hex +$43E84 (Line 2) +32 09 37 52 3C F6 01 00 00 00 C3 32 71 3B 28 F2 2F 3D 33 2A C2 | Original Japanese Hex +LENGTH LENGTH そ れ と $ 1 0 0 0 。 特 っ て 行 き な さ い 」 | Original Japanese Text +LENGTH B E E N S A V I N G F O R Y O U . | New English Text +13 0B 0E 0E 17 28 1C 0A 1F 12 17 10 28 0F 18 1B 28 22 18 1E C3 | New English Hex + +あなたが りっぱな勇者に なって かえってくるよう しんじていますよ +We believe that you will come back to me such a fine hero +$43EBC (Line 1) +0F 29 3D 38 57 28 50 71 6B 3D EF E7 3E 28 3D 71 3B | Original Japanese Hex +LENGTH あ な た が り っ ぱ な 勇 者 に な っ て | Original Japanese Text +LENGTH I T H I N K Y O U W I L L | New English Text +0F 12 28 1D 11 12 17 14 28 22 18 1E 28 20 12 15 15 | New English Hex +$43ECD (Line 2) +10 2E 2C 71 3B 30 51 4E 2B 28 34 56 5D 3B 2A 47 35 4E | Original Japanese Hex +LENGTH か え っ て く る よ う し ん じ て い ま す よ | Original Japanese Text +LENGTH M A K E A F I N E H E R O ! | New English Text +10 16 0A 14 0E 28 0A 28 0F 12 17 0E 28 11 0E 1B 18 25 | New English Hex + +あったかーい +It was so warm +$43810 +05 29 71 38 2E F7 2A | Original Japanese Hex +LENGTH あ っ た か ー い | Original Japanese Text +LENGTH W A R M ! ! | New English Text +05 20 0A 1B 16 25 25 | New English Hex + +ノばマン 「GOOD MORNING!アルバ-ト ひろばに ぎんゆうしじんが きてるらしいぜ」 +Neumann: Good Morning! Albert Let It looks like a minstrel came Plaza +$43EDF (Line 1) +F6 8D 0C 76 0C 93 0C A2 0C C1 00 10 00 18 00 18 00 0D 00 28 00 16 00 18 00 1B 00 17 00 12 00 17 00 10 00 25 00 75 00 9D 00 B2 00 F7 00 88 00 | Original Japanese Hex +LENGTH ノRED ばRED マRED ンRED 「BLACK GBLACK OBLACK OBLACK DBLACK BLACK MBLACK OBLACK RBLACK NBLACK IBLACK NBLACK GBLACK !BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK | Original Japanese Text +LENGTH N E U M A N N : G O O D M O R N I N G ! A L B E R TBLACK IBLACK NBLACK GBLACK !BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK | New English Text +1A 17 0E 1E 16 0A 17 17 D6 10 18 18 0D 28 16 18 1B 17 12 17 10 25 0A 15 0B 0E 1B 1D 00 12 00 17 00 10 00 25 00 75 00 9D 00 B2 00 F7 00 88 00 | New English Hex +$43F0E (Line 2) +16 28 43 53 66 3E 28 58 56 4D 2B 34 5D 56 57 28 2F 3B 51 4F 34 2A 5F C2 | Original Japanese Hex +LENGTH ひ ろ ば に ぎ ん ゆ う し じ ん が き て る ら し い ぜ 」 | Original Japanese Text +LENGTH A B A R D I S I N T H E P L A Z A . | New English Text +16 0A 28 0B 0A 1B 0D 28 12 1C 28 12 17 28 1D 11 0E 28 19 15 0A 23 0A C3 | New English Hex + +どうする? +What do you want to dO? +$43F26 (Line 1) +04 65 2B 35 51 24 | Original Japanese Hex +LENGTH ど う す る ? | Original Japanese Text +LENGTH W H A T ? | New English Text +04 20 11 0A 1D 24 | New English Hex + + おもしろそうだから みにいく + Go to see it because it sounds interesting + $43F2C (Line 2) + 0E 28 2D 4B 34 53 37 2B 61 2E 4F 28 48 3E 2A 30 | Original Japanese Hex + LENGTH お も し ろ そ う だ か ら み に い く | Original Japanese Text + LENGTH S E E M S L I K E F U N | New English Text + 0E 28 1C 0E 0E 16 1C 28 15 12 14 0E 28 0F 1E 17 | New English Hex + + やめとく + I'll pass + $43F3C (Line 3) + 04 28 4C 4A 3C 30 | Original Japanese Hex + LENGTH や め と く | Original Japanese Text + LENGTH P A S S | New English Text + 04 28 19 0A 1C 1C | New English Hex + +アルバート 「行こうぜ ノイマン」 +Albert: Let's go Neumann +$43F42 +EF 75 0C 9D 0C B2 0C F7 0C 88 0C C1 00 F2 00 32 00 2B 00 5F 00 28 00 8D 00 76 00 93 00 A2 00 C2 00 | Original Japanese Hex +LENGTH アRED ルRED バRED ーRED トRED 「BLACK 行BLACK こBLACK うBLACK ぜBLACK BLACK ノBLACK イBLACK マBLACK ンBLACK 」BLACK | Original Japanese Text +LENGTH A L B E R T : O K L E T S G O N E U M A N N マBLACK ンBLACK 」BLACK | New English Text +19 0A 15 0B 0E 1B 1D D6 28 18 14 28 15 0E 1D 1C 28 10 18 28 17 0E 1E 16 0A 17 17 93 00 A2 00 C2 00 | New English Hex + +ノばマン 「いいから COME ON!」 +Neumann: It will be good, COME ON! +$43F63 +F2 8D 0C 76 0C 93 0C A2 0C C1 00 2A 00 2A 00 2E 00 4F 00 28 00 0C 00 18 00 16 00 0E 00 28 00 18 00 17 00 25 00 C2 00 | Original Japanese Hex +LENGTH ノRED ばRED マRED ンRED 「BLACK いBLACK いBLACK かBLACK らBLACK BLACK CBLACK OBLACK MBLACK EBLACK BLACK OBLACK NBLACK !BLACK 」BLACK | Original Japanese Text +LENGTH N E U M A N N : O H A L B E R T , C O M E O N !BLACK BLACK OBLACK NBLACK !BLACK 」BLACK | New English Text +1A 17 0E 1E 16 0A 17 17 D6 18 11 28 0A 15 0B 0E 1B 1D C4 28 0C 18 16 0E 28 18 17 25 00 28 00 18 00 17 00 25 00 C2 00 | New English Hex + +きょう大な魔力で せい地をしはいしていた グローバスと はがねをまといし勇者、ゴートの 戦いは +Brave heroes of Gort Clad in steel, fought a great war against the high magician Globus who ruled the world +$41B59 (Line 1) +3A 03 2F 74 2B 02 3D E0 CF 64 28 36 2A DF 55 34 42 2A 34 3B 2A 38 28 A5 9F F7 B2 81 3C | Original Japanese Hex +LENGTH LENGTH き ょ う 大 な 魔 力 で せ い 地 を し は い し て い た グ ロ ー バ ス と | Original Japanese Text +LENGTH W A R A G A I N S T T H E M A G E G L O B U S と | New English Text| New English Text +1A 20 0A 1B 28 0A 10 0A 12 17 1C 1D 28 1D 11 0E 28 16 0A 10 0E 28 10 15 18 0B 1E 1C 3C | New English Hex +$41B76 (Line 2) +12 42 57 40 55 47 3C 2A 34 EF E7 C4 A7 F7 88 41 28 D7 2A 42 | Original Japanese Hex +LENGTH は が ね を ま と い し 勇 者 、 ゴ ー ト の 戦 い は | Original Japanese Text +LENGTH W H O R U L E D T H E W O R L D | New English Text| New English Text +12 20 11 18 28 1B 1E 15 0E 0D 28 1D 11 0E 28 20 18 1B 15 0D | New English Hex + +いつまでも 終わりをみせることはなかった +Seemed to never end... +$41B8A +33 06 2A 3A 47 64 4B 28 24 54 50 55 48 36 51 32 3C 42 3D 2E 71 38 | Original Japanese Hex +LENGTH LENGTH い つ ま で も 終 わ り を み せ る こ と は な か っ た | Original Japanese Text +LENGTH S E E M E D T O N E V E R E N D . . | New English Text +14 1C 0E 0E 16 0E 0D 28 1D 18 28 17 0E 1F 0E 1B 28 0E 17 0D C3 C3 | New English Hex + +だが あるとき、むげんの魔力の みなもとが グローバスの特つ 水晶にあるとしった ゴートは +However, Gort came to realize that there was an infinite source of energy within a crystal that Globus had and... +$41BA0 (Line 1) +14 61 57 28 29 51 3C 2F C4 49 5A 56 41 E0 CF 41 28 48 3D 4B 3C 57 | Original Japanese Hex +LENGTH だ が あ る と き 、 む げ ん の 魔 力 の み な も と が | Original Japanese Text +LENGTH G O R T B E G A N T O R E A L I Z E | New English Text| New English Text +14 10 18 1B 1D 28 0B 0E 10 0A 17 28 1D 18 28 1B 0E 0A 15 12 23 0E | New English Hex +$41BB6 (Line 2) +36 06 A5 9F F7 B2 81 41 32 3A 28 DD DE 3E 29 51 3C 34 71 38 28 A7 F7 88 42 | Original Japanese Hex +LENGTH LENGTH グ ロ ー バ ス の 特 つ 水 晶 に あ る と し っ た ゴ ー ト は | Original Japanese Text +LENGTH A C R Y S T A L G A V E H I M P O W E R | New English Text| New English Text +17 0A 28 0C 1B 22 1C 1D 0A 15 28 10 0A 1F 0E 28 11 12 16 28 19 18 20 0E 1B | New English Hex + +それを うばい取ることに せいこうし みごと グローバスを うちたおす +took the crystal away from Globus and defeated him +$41BCF (Line 1) +31 07 37 52 55 28 2B 66 2A 22 51 32 3C 3E 28 36 2A 32 2B 34 | Original Japanese Hex +LENGTH LENGTH そ れ を う ば い 取 る こ と に せ い こ う し | Original Japanese Text +LENGTH T O O K I T F R O M G L O B U S | New English Text +12 1D 18 18 14 28 12 1D 28 0F 1B 18 16 28 10 15 18 0B 1E 1C | New English Hex +$41BE3 (Line 2) +0F 48 5B 3C 28 A5 9F F7 B2 81 55 28 2B 39 38 2D 35 | Original Japanese Hex +LENGTH み ご と グ ロ ー バ ス を う ち た お す | Original Japanese Text +LENGTH A N D D E F E A T E D H I M | New English Text +0F 0A 17 0D 28 0D 0E 0F 0E 0A 1D 0E 0D 28 11 12 16 | New English Hex + +ゴートをのろい続ける グローバスのたましいを 大地にふういんすると +Gort sealed the spirit of Globus under deep earth. +$41BF4 (Line 1) +35 07 A7 F7 88 55 41 53 2A 1B 31 51 28 A5 9F F7 B2 81 41 38 47 34 2A 55 | Original Japanese Hex +LENGTH LENGTH ゴ ー ト を の ろ い 続 け る グ ロ ー バ ス の た ま し い を | Original Japanese Text +LENGTH S E A L I N G H I S S P I R I T D E E P | New English Text +16 1C 0E 0A 15 12 17 10 28 11 12 1C 28 1C 19 12 1B 12 1D 28 0D 0E 0E 19 | New English Hex +$41C0C (Line 2) +29 00 02 DF 3E 44 2B 2A 56 35 51 3C | Original Japanese Hex +LENGTH LENGTH 大 地 に ふ う い ん す る と | Original Japanese Text +LENGTH U N D E R G R O U N D | New English Text +0A 1E 17 0D 0E 1B 10 1B 18 1E 17 0D | New English Hex + +せかいは ひとつとなり ひとびとは ながきへいわを えたのであった +The world lived in peace for a long time. +$45F4A (Line 1) +0A 36 2E 2A 42 28 43 3C 3A 3C 3D 50 | Original Japanese Hex +LENGTH せ か い は ひ と つ と な り | Original Japanese Text +LENGTH P E A C E C A M E , | New English Text +0A 19 0E 0A 0C 0E 28 0C 0A 16 0E C4 | New English Hex +$41C18 (Line 2) +14 43 3C 67 3C 42 28 3D 57 2F 45 2A 54 55 28 2C 38 41 64 29 71 38 | Original Japanese Hex +LENGTH ひ と び と は な が き へ い わ を え た の で あ っ た | Original Japanese Text +LENGTH T O T H E L A N D O N C E M O R E | New English Text +14 1D 18 28 1D 11 0E 28 15 0A 17 0D 28 18 17 0C 0E 28 16 18 1B 0E | New English Hex + +アルバート!司祭さまが よんでるよ ノイマンも こいって +Albert! The Priest is calling you! Neumann you too! +$41C2E (Line 1) +10 75 9D B2 F7 88 25 F8 EC 33 47 57 28 4E 56 64 51 4E | Original Japanese Hex +LENGTH ア ル バ ー ト ! 司 祭 さ ま が よ ん で る よ | Original Japanese Text +LENGTH T H E P R I E S T W A N T E D | New English Text +10 1D 11 0E 28 19 1B 12 0E 1C 1D 28 20 0A 17 1D 0E 0D | New English Hex +$41C40 (Line 2) +09 8D 76 93 A2 4B 28 32 2A 71 3B | Original Japanese Hex +LENGTH ノ イ マ ン も こ い っ て | Original Japanese Text +LENGTH T O S E E Y O U | New English Text +09 1D 18 28 1C 0E 0E 28 22 18 1E | New English Hex + +アルバ-ト「わかった」 ノイマン「THANKS」 +Albert "all right" Neumann "THANKS" +$41C4B (Line 1) +EA 75 0C 9D 0C B2 0C F7 0C 88 0C C1 00 54 00 2E 00 71 00 38 00 C2 00 | Original Japanese Hex +LENGTH アRED ルRED バRED -RED トRED 「BLACK わBLACK かBLACK っBLACK たBLACK 」BLACK | Original Japanese Text +LENGTH A L B E R T : A L L R I G H TBLACK たBLACK 」BLACK | New English Text +10 0A 15 0B 0E 1B 1D D6 28 0A 15 15 28 1B 12 10 11 1D 00 38 00 C2 00 | New English Hex +$41C62 (Line 2) +EB 8D 0C 76 0C 93 0C A2 0C C1 00 1D 00 11 00 0A 00 17 00 14 00 1C 00 C2 00 | Original Japanese Hex +LENGTH ノRED イRED マRED ンRED 「BLACK TBLACK HBLACK ABLACK NBLACK KBLACK SBLACK 」BLACK | Original Japanese Text +LENGTH N E U M A N N : T H A N K SBLACK NBLACK KBLACK SBLACK 」BLACK | New English Text +0E 17 0E 1E 16 0A 17 17 D6 28 1D 11 0A 17 14 1C 00 17 00 14 00 1C 00 C2 00 | New English Hex + +司祭「おお、きたか アルバート。そなたは 勇者の血を ひく者、このこの はなしを きくがよい」 +Priest "Ah you came, Albert. You are the son of a great soldier. Listen to my story" +$41CB9 (Line 1) +F3 F8 0C EC 0C C1 00 2D 00 2D 00 C4 00 2F 00 38 00 2E 00 28 00 75 00 9D 00 B2 00 F7 00 88 00 C3 00 37 00 3D 00 38 00 42 00 | Original Japanese Hex +LENGTH 司RED 祭RED 「BLACK おBLACK おBLACK 、BLACK きBLACK たBLACK かBLACK BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK 。BLACK そBLACK なBLACK たBLACK はBLACK | Original Japanese Text +LENGTH PRED RRED IRED ERED SRED TRED :RED PBLACK LBLACK EBLACK ABLACK SBLACK EBLACK BLACK LBLACK IBLACK SBLACK TBLACK EBLACK NBLACK | New English Text +F3 19 0C 1B 0C 12 0C 0E 0C 1C 0C 1D 0C D6 0C 19 00 15 00 0E 00 0A 00 1C 00 0E 00 28 00 15 00 12 00 1C 00 1D 00 0E 00 17 00 | New English Hex +$41CE2 (Line 2) +19 EF E7 41 E8 55 28 43 30 E7 C4 32 41 32 41 28 42 3D 34 55 28 2F 30 57 4E 2A C2 | Original Japanese Hex +LENGTH 勇 者 の 血 を ひ く 者 、 こ の こ の は な し を き く が よ い 」 | Original Japanese Text +LENGTH T O M Y S T O R Y C L O S E L Y A L B E R T | New English Text +19 1D 18 28 16 22 28 1C 1D 18 1B 22 28 0C 15 18 1C 0E 15 22 28 0A 15 0B 0E 1B 1D | New English Hex + +ソフィア「わたしは ゴートきゅうてい魔術師ソフィア」 +Sofia "I am Sofia, a magician from Gort" +$41F1A +F9 83 0C 90 0C 5C 0D 75 0C C1 00 54 00 38 00 34 00 42 00 28 00 A7 00 F7 00 88 00 2F 00 73 00 2B 00 3B 00 2A 00 E0 00 E4 00 DA 00 83 00 90 00 5C 01 75 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK わBLACK たBLACK しBLACK はBLACK BLACK ゴBLACK ーBLACK トBLACK きBLACK ゅBLACK うBLACK てBLACK いBLACK 魔BLACK 術BLACK 師BLACK ソBLACK フBLACK ィBLACK アBLACK 」BLACK | Original Japanese Text +LENGTH SRED ORED FRED IRED ARED :RED BLACK IBLACK MBLACK BLACK ABLACK BLACK MBLACK ABLACK GBLACK EBLACK BLACK FBLACK RBLACK OBLACK MBLACK BLACK GBLACK OBLACK RBLACK TBLACK | New English Text +F9 1C 0C 18 0C 0F 0C 12 0C 0A 0C D6 0C 28 00 12 00 16 00 28 00 0A 00 28 00 16 00 0A 00 10 00 0E 00 28 00 0F 00 1B 00 18 00 16 00 28 00 10 00 18 00 1B 00 1D 00 | New English Hex + +かく地に とつぜん あらわれた モンスターのことを しらべるために たびをしていたんですが +I was researching about the monsters that have suddenly appeared around the world +$41F4F (Line 1) +18 2E 30 DF 3E 28 3C 3A 5F 56 28 29 4F 54 52 38 28 97 A2 81 84 F7 41 32 3C 55 | Original Japanese Hex +Length か く 地 に と つ ぜ ん あ ら わ れ た モ ン ス タ ー の こ と を | Original Japanese Text +Length M O N S T E R S A R E S P R I N G I N G U P | New English Text +18 16 18 17 1C 1D 0E 1B 1C 28 0A 1B 0E 28 1C 19 1B 12 17 10 12 17 10 28 1E 19 | New English Hex +$41F69 (Line 2) +12 34 4F 69 51 38 4A 3E 28 38 67 55 34 3B 2A 38 56 64 35 57 | Original Japanese Hex +Length し ら べ る た め に た び を し て い た ん で す が | Original Japanese Text +LENGTH A L L O V E R T H E W O R L D . | New English Text +12 0A 15 15 28 18 1F 0E 1B 28 1D 11 0E 28 20 18 1B 15 0D C3 | New English Hex + +きのう、魔物におそわれ この村に にげこみました +Yesterday, I was attacked by a monster & passed out in front of this church. +$41F7D +57 05 0E 2F 41 2B C4 E0 33 3E 2D 37 54 52 28 32 41 27 3E 28 3E 5A 32 48 47 34 38 | Original Japanese Hex +LENGTH LENGTH LENGTH き の う 、 魔 物 に お そ わ れ こ の 村 に に げ こ み ま し た | Original Japanese Text +LENGTH I W A S A T T A C K E D C O M I N G H E R E | New English Text +19 12 28 20 0A 1C 28 0A 1D 1D 0A 0C 14 0E 0D 28 0C 18 16 12 17 10 28 11 0E 1B 0E | New English Hex + +10ねんまえ せかいを きょうふに おとしいれた オズワルドが ふたたび 蘇りました +Oswald who was terrorizing the world 10 years ago has been revived again +$41F98 (Line 1) +17 01 00 40 56 47 2C 28 36 2E 2A 55 28 2F 74 2B 44 3E 28 2D 3C 34 2A 52 38 | Original Japanese Hex +LENGTH 1 0 ね ん ま え せ か い を き ょ う ふ に お と し い れ た | Original Japanese Text +LENGTH O S W A L D H A S R E V I V E D A F T E R | New English Text +17 18 1C 20 0A 15 0D 28 11 0A 1C 28 1B 0E 1F 12 1F 0E 0D 28 0A 0F 1D 0E 1B | New English Hex +$41FB1 (Line 2) +30 0C 79 AA A0 9D B1 57 28 44 38 38 67 28 50 50 47 34 38 | Original Japanese Hex +LENGTH LENGTH オ ズ ワ ル ド が ふ た た び 蘇 り ま し た | Original Japanese Text +LENGTH 1 0 Y E A R S O F P E A C E . | New English Text +11 01 00 28 22 0E 0A 1B 1C 28 18 0F 28 19 0E 0A 0C 0E C3 | New English Hex + +このことを いっこくも早く 王につたえねばなりません +We must tell the king as soon as possible of this +$41FC4 +19 32 41 32 3C 55 28 2A 71 32 30 4B CA 30 28 EB 3E 3A 38 2C 40 66 3D 50 47 36 56 | Original Japanese Hex +LENGTH こ の こ と を い っ こ く も 早 く 王 に つ た え ね ば な り ま せ ん | Original Japanese Text +LENGTH W E M U S T T E L L T H E K I N G T H I S | New English Text +19 20 0E 28 16 1E 1C 1D 28 1D 0E 15 15 28 1D 11 0E 28 14 12 17 10 28 1D 11 12 1C | New English Hex + +どうか いっしょに ゴートまで行ってくれませんか? +Will you please come to Gort with me? +$41FDF (Line 1) +18 65 2B 2E 28 2A 71 34 74 3E 28 A7 F7 88 47 64 F2 71 3B 30 52 47 36 56 2E 24 | Original Japanese Hex +LENGTH ど う か い っ し ょ に ゴ ー ト ま で 行 っ て く れ ま せ ん か ? | Original Japanese Text +LENGTH W I L L Y O U J O I N M E T O G O R T ? | New English Text +18 20 12 15 15 28 22 18 1E 28 13 18 12 17 28 16 0E 28 1D 18 28 10 18 1B 1D 24 | New English Hex + + わかった + all right + $41CFD (Line 2) + 04 28 54 2E 71 38 | Original Japanese Hex + LENGTH わ か っ た | Original Japanese Text + LENGTH Y E S | New English Text + 04 28 22 0E 1C 28 | New English Hex + + いやだ + I refuse + $41D03 (Line 3) + 03 28 2A 4C 61 | Original Japanese Hex + LENGTH い や だ | Original Japanese Text + LENGTH N O | New English Text + 03 28 17 18 28 | New English Hex + +Yes Selected: +ありがとう アルバート +Thank you Albert +$41FF9 +0A 29 50 57 3C 2B 28 75 9D B2 F7 88 | Original Japanese Hex +LENGTH あ り が と う ア ル バ ー ト | Original Japanese Text +LENGTH T H A N K Y O U . . | New English Text +0A 1D 11 0A 17 14 28 22 18 1E C3 C3 | New English Hex + +No Selected: +おねがいします。わたしひとりでは+++ +I need your help. I'm Alone +++ +$42005 +72 10 11 12 2D 40 57 2A 34 47 35 C3 54 38 34 43 3C 50 64 42 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH お ね が い し ま す 。 わ た し ひ と り で は + + + | Original Japanese Text +LENGTH I W I L L N E E D Y O U R H E L P . | New English Text +15 12 28 20 12 15 15 28 17 0E 0E 0D 28 22 18 1E 1B 28 11 0E 15 19 C3 | New English Hex + +それから ひとつ いっておきたいことがあるの +Oh I have one more thing to say +$442B8 +15 37 52 2E 4F 28 43 3C 3A 28 2A 71 3B 2D 2F 38 2A 32 3C 57 29 51 41 | Original Japanese Hex +LENGTH そ れ か ら ひ と つ い っ て お き た い こ と が あ る の | Original Japanese Text +LENGTH O N E M O R E T H I N G T O S A Y , | New English Text +15 18 17 0E 28 16 18 1B 0E 28 1D 11 12 17 10 28 1D 18 28 1C 0A 22 C4 | New English Hex + +10ねんまえの ひかりのことは しってるでしょ +You know that the light from 10 years ago +$442CF +16 01 00 40 56 47 2C 41 28 43 2E 50 41 32 3C 42 28 34 71 3B 51 64 34 74 | Original Japanese Hex +LENGTH 1 0 ね ん ま え の ひ か り の こ と は し っ て る で し ょ | Original Japanese Text +LENGTH T H E L I G H T 1 0 Y E A R S A G O , | New English Text +16 1D 11 0E 28 15 12 10 11 1D 28 01 00 28 22 0E 0A 1B 1C 28 0A 10 18 C4 | New English Hex + +そこにいた おんなのこの ことも+++ +And the girl who was there + + + +$442E7 +72 10 11 12 37 32 3E 2A 38 28 2D 56 3D 41 32 41 28 32 3C 4B 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH そ こ に い た お ん な の こ の こ と も + + + | Original Japanese Text +LENGTH I W I T N E S S E D I T M Y S E L F . | New English Text +15 12 28 20 12 1D 17 0E 1C 1C 0E 0D 28 12 1D 28 16 22 1C 0E 15 0F C3 | New English Hex + +わたしのことなの+++ +It was actually me + + + +$442FE +6A 08 09 0A 54 38 34 41 32 3C 3D 41 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH わ た し の こ と な の + + + | Original Japanese Text +LENGTH I S U M M O N E D I T . | New English Text +0D 12 28 1C 1E 16 16 18 17 0E 0D 28 12 1D C3 | New English Hex + +でも わたしには あのふしぎな力は もう でないし +But I have no such strong power now +$4430D +18 64 4B 28 54 38 34 3E 42 28 29 41 44 34 58 3D CF 42 28 4B 2B 28 64 3D 2A 34 | Original Japanese Hex +LENGTH で も わ た し に は あ の ふ し ぎ な 力 は も う で な い し | Original Japanese Text +LENGTH I L O S T T H A T S T R A N G E P O W E R | New English Text +18 12 28 15 18 1C 1D 28 1D 11 0A 1D 28 1C 1D 1B 0A 17 10 0E 28 19 18 20 0E 1B | New English Hex + +ふっかつしたオズワルドは あのときのことを おそれて ひっしで わたしをさがしているわ +Oswald must be looking for me because of what I did to him back then. +$44327 (Line 1) +19 44 71 2E 3A 34 38 79 AA A0 9D B1 42 28 29 41 3C 2F 41 32 3C 55 28 2D 37 52 3B | Original Japanese Hex +LENGTH ふ っ か つ し た オ ズ ワ ル ド は あ の と き の こ と を お そ れ て | Original Japanese Text +LENGTH I T S I N E V I T A B L E T H A T O S W A L D | New English Text +19 12 1D 1C 28 12 17 0E 1F 12 1D 0A 0B 15 0E 28 1D 11 0B 1D 28 18 1C 20 0A 15 0D | New English Hex +$44342 (Line 2) +0F 43 71 34 64 28 54 38 34 55 33 57 34 3B 2A 51 54 | Original Japanese Hex +LENGTH ひ っ し で わ た し を さ が し て い る わ | Original Japanese Text +LENGTH W I L L L O O K F O R M E | New English Text +0F 20 12 15 15 28 15 18 18 14 28 0F 18 1B 28 16 0E | New English Hex + +だから このことは ないしょにしておいてほしいの おねがいね アルバート +So this is Albert I ask of you to keep it a secret +$44353 (Line 1) +17 61 2E 4F 28 32 41 32 3C 42 28 3D 2A 34 74 3E 34 3B 2D 2A 3B 46 34 2A 41 | Original Japanese Hex +LENGTH だ か ら こ の こ と は な い し ょ に し て お い て ほ し い の | Original Japanese Text +LENGTH I L L A S K Y O U T O K E E P T H I S | New English Text +17 12 15 15 28 0A 1C 14 28 22 18 1E 28 1D 18 28 14 0E 0E 19 28 1D 11 12 1C | New English Hex +$4436C (Line 2) +0A 2D 40 57 2A 40 28 75 9D B2 F7 88 | Original Japanese Hex +LENGTH お ね が い ね ア ル バ ー ト | Original Japanese Text +LENGTH A S A S E C R E T | New English Text +0A 0A 1C 28 0A 28 1C 0E 0C 1B 0E 1D | New English Hex + +ソフィア「司祭さま おせわになりました」 +Now priest take care +$41DA8 +F3 83 0C 90 0C 5C 0D 75 0C C1 00 F8 00 EC 00 33 00 47 00 28 00 2D 00 36 00 54 00 3E 00 3D 00 50 00 47 00 34 00 38 00 C2 00 | Original Japanese Hex +LENGTH ソRED フRED ィRED アRED 「BLACK 司BLACK 祭BLACK さBLACK まBLACK BLACK おBLACK せBLACK わBLACK にBLACK なBLACK りBLACK まBLACK しBLACK たBLACK 」BLACK | Original Japanese Text +LENGTH SRED ORED FRED IRED ARED :RED BLACK IBLACK BLACK ABLACK MBLACK BLACK WBLACK EBLACK LBLACK LBLACK BLACK NBLACK OBLACK WBLACK | New English Text +F3 1C 0C 18 0C 0F 0C 12 0C 0A 0C D6 0C 28 00 12 00 28 00 0A 00 16 00 28 00 20 00 0E 00 15 00 15 00 28 00 17 00 18 00 20 00 | New English Hex + +司祭「気をつけてな。ソフィアをたのんだぞ アルバート それから ノイマン、わしは おまえが いちにんまえの 僧侶になるのを きたいしておる。がんばるんだぞ」 +Priest "Be careful out there. Please take care of her Albert. Neumann I look forward to seeing you as a fine monk. Don't disappoint me" +$41DD1 (Line 1) +F9 F8 0C EC 0C C1 00 ED 00 55 00 3A 00 31 00 3B 00 3D 00 C3 00 83 00 90 00 5C 01 75 00 55 00 38 00 41 00 56 00 61 00 60 00 28 00 75 00 9D 00 B2 00 F7 00 88 00 | Original Japanese Hex +LENGTH 司RED 祭RED 「BLACK 気BLACK をBLACK つBLACK けBLACK てBLACK なBLACK 。BLACK ソBLACK フBLACK ィBLACK アBLACK をBLACK たBLACK のBLACK んBLACK だBLACK ぞBLACK BLACK アBLACK ルBLACK バBLACK ーBLACK トBLACK | Original Japanese Text +LENGTH PRED RRED IRED ERED SRED TRED :RED BLACK TBLACK ABLACK KBLACK EBLACK BLACK CBLACK ABLACK RBLACK EBLACK BLACK OBLACK FBLACK BLACK SBLACK OBLACK FBLACK IBLACK ABLACK | New English Text +F9 19 0C 1B 0C 12 0C 0E 0C 1C 0C 1D 0C D6 0C 28 00 1D 00 0A 00 14 00 0E 00 28 00 0C 00 0A 00 1B 00 0E 00 28 00 18 00 0F 00 28 00 1C 00 18 00 0F 00 12 00 0A 00 | New English Hex +$41E06 (Line 2) +19 37 52 2E 4F 28 8D 76 93 A2 C4 54 34 42 28 2D 47 2C 57 28 2A 39 3E 56 47 2C 41 | Original Japanese Hex +LENGTH そ れ か ら ノ イ マ ン 、 わ し は お ま え が い ち に ん ま え の | Original Japanese Text +LENGTH A L B E R T , N E U M A N N I T H I N K Y O U | New English Text +19 0A 15 0B 0E 1B 1D C4 17 0E 1E 16 0A 17 17 28 12 28 1D 11 12 17 14 28 22 18 1E | New English Hex +$41E21 (Line 3) +17 E2 E3 3E 3D 51 41 55 28 2F 38 2A 34 3B 2D 51 C3 57 56 66 51 56 61 60 C2 | Original Japanese Hex +LENGTH 僧 侶 に な る の を き た い し て お る 。 が ん ば る ん だ ぞ 」 | Original Japanese Text +LENGTH W I L L B E C O M E A G R E A T M O N K | New English Text +17 20 12 15 15 28 0B 0E 0C 18 16 0E 28 0A 28 10 1B 0E 0A 1D 28 16 18 17 14 | New English Hex + +-------------------- +Chiberus - Outside: +-------------------- +Green Hair Tube Head Man On Church Front: +ちかごろ かくちで モンスターがあらわれ 村が おそわれているらしい +Villages seems to have been recently attacked monster will appear in various locations +$41D08 (Line 1) +13 39 2E 5B 53 28 2E 30 39 64 28 97 A2 81 84 F7 57 29 4F 54 52 | Original Japanese Hex +LENGTH ち か ご ろ か く ち で モ ン ス タ ー が あ ら わ れ | Original Japanese Text +LENGTH M O N S T E R S A R E G E T T I N G | New English Text +13 16 18 17 1C 1D 0E 1B 1C 28 0A 1B 0E 28 10 0E 1D 1D 12 17 10 | New English Hex +$41D1D (Line 2) +2C 00 27 57 28 2D 37 54 52 3B 2A 51 4F 34 2A | Original Japanese Hex +LENGTH LENGTH 村 が お そ わ れ て い る ら し い | Original Japanese Text +LENGTH T O U G H O U T S I D E . | New English Text +0D 1D 18 1E 10 11 28 18 1E 1D 1C 12 0D 0E C3 | New English Hex + +Brown Hair Boy On Plaza: +武器は ゴートまで行かないと いいものが かえないなぁ +Good thing is I do not have to go up and change weapons Gort +$41D2C +1A C5 C6 42 28 A7 F7 88 47 64 F2 2E 3D 2A 3C 28 2A 2A 4B 41 57 28 2E 2C 3D 2A 3D 70 | Original Japanese Hex +LENGTH 武 器 は ゴ ー ト ま で 行 か な い と い い も の が か え な い な ぁ | Original Japanese Text +LENGTH I A M T A K I N G W E A P O N S T O G O R T | New English Text +1A 12 28 0A 16 28 1D 0A 14 12 17 10 28 20 0E 0A 19 18 17 1C 28 1D 18 28 10 18 1B 1D | New English Hex + +Purple Hair Girl On Plaza: +ぎんゆうしじんは 風のふくまま 気の向くまま すてきねっ +Bard ne nice fancy still remains windy +$41EB5 (Line 1) +35 09 58 56 4D 2B 34 5D 56 42 28 3A 41 44 30 47 47 28 ED 41 FE 30 47 47 | Original Japanese Hex +LENGTH LENGTH ぎ ん ゆ う し じ ん は 風 の ふ く ま ま 気 の 向 く ま ま | Original Japanese Text +LENGTH I T W A S G O O D T O H E A R T H E | New English Text +16 12 1D 28 20 0A 1C 28 10 18 18 0D 28 1D 18 28 11 0E 0A 1B 28 1D 11 0E | New English Hex +$41ECD (Line 2) +04 35 3B 2F 40 71 | Original Japanese Hex +LENGTH す て き ね っ | Original Japanese Text +LENGTH M U S I C | New English Text +04 16 1E 1C 12 0C | New English Hex + +Brown Hair Girl: +東にむかい ハシをわたったところに ゴートがあるわ +If you go over the bridge in the east, you can get to Gort +$41D70 +18 F9 3E 49 2E 2A 28 8E 80 55 54 38 71 38 3C 32 53 3E 28 A7 F7 88 57 29 51 54 | Original Japanese Hex +LENGTH 東 に む か い ハ シ を わ た っ た と こ ろ に ゴ ー ト が あ る わ | Original Japanese Text +LENGTH G O R T I S N O R T H E A S T O F H E R E | New English Text +18 10 18 1B 1D 28 12 1C 28 17 18 1B 1D 11 0E 0A 1C 1D 28 18 0F 28 11 0E 1B 0E | New English Hex + +Old Man On Church Front: +武器は特っているだけでなく ちゃんと装備しないとダメだ +It's a useless to have arms that are not equipped properly not only have specialized っ +$41D8A +5A 03 12 C5 C6 42 32 71 3B 2A 51 61 31 64 3D 30 28 39 72 56 3C 60 DC 34 3D 2A 3C AD 96 61 | Original Japanese Hex +LENGTH LENGTH LENGTH 武 器 は 特 っ て い る だ け で な く ち ゃ ん と 装 備 し な い と ダ メ だ | Original Japanese Text +LENGTH E Q U I P Y O U R S E L F I F T R A V E L I N G メ だ | New English Text +1A 0E 1A 1E 12 19 28 22 18 1E 1B 1D 0E 15 0F 28 12 0F 28 1D 1B 0A 1F 0E 15 12 17 10 96 61 | New English Hex + +Old Man Near Inn: +よいか 取りかえしのつかぬことに なるまえに こまめに セーブしておくんじゃ +Before you will be good or not irreparable Maybe you have to save frequently +$41D48 (Line 1) +35 04 4E 2A 2E 28 22 50 2E 2C 34 41 3A 2E 3F 32 3C 3E 28 3D 51 47 2C 3E | Original Japanese Hex +LENGTH LENGTH よ い か 取 り か え し の つ か ぬ こ と に な る ま え に | Original Japanese Text +LENGTH R E C O R D Y O U R P R O G R E S S T O | New English Text +16 1B 0E 0C 18 1B 0D 28 22 18 1E 1B 28 19 1B 18 10 1B 0E 1C 1C 28 1D 18 | New English Hex +$41D60 (Line 2) +0E 32 47 4A 3E 28 82 F7 B4 34 3B 2D 30 56 5D 72 | Original Japanese Hex +LENGTH こ ま め に セ ー ブ し て お く ん じ ゃ | Original Japanese Text +LENGTH A S A V E D A T A L O G | New English Text +0E 0A 28 1C 0A 1F 0E 28 0D 0A 1D 0A 28 15 18 10 | New English Hex +とまるさきざきで このぼうけんを きろくするがいい +I will log this adventure that stops +$44453 (Line 3) +18 3C 47 51 33 2F 5C 2F 64 28 32 41 6A 2B 31 56 55 28 2F 53 30 35 51 57 2A 2A | Original Japanese Hex +LENGTH と ま る さ き ざ き で こ の ぼ う け ん を き ろ く す る が い い | Original Japanese Text +LENGTH I F Y O U S T O P T H E A D V E N T U R E | New English Text +18 12 0F 28 22 18 1E 28 1C 1D 18 19 28 1D 11 0E 28 0A 0D 1F 0E 17 1D 1E 1B 0E | New English Hex + +Red Hair Tube Head Man South East: +この村 よるになると オバケがでるって うわさだぜ +They say a ghost is out at night in this village +$41E79 +38 02 32 41 27 28 4E 51 3E 3D 51 3C 28 79 B2 7D 57 64 51 71 3B 28 2B 54 33 61 5F | Original Japanese Hex +LENGTH LENGTH こ の 村 よ る に な る と オ バ ケ が で る っ て う わ さ だ ぜ | Original Japanese Text +LENGTH A G H O S T C O M E S O U T A T N I G H T | New English Text +19 0A 28 10 11 18 1C 1D 28 0C 18 16 0E 1C 28 18 1E 1D 28 0A 1D 28 17 12 10 11 1D | New English Hex + +Chicken: +コケッ!! +cock-A-Doodle-Doo!! +$41E73 +04 7E 7D BD 25 25 | Original Japanese Hex +LENGTH コ ケ ッ ! ! | Original Japanese Text +LENGTH C L U K ! | New English Text +04 0C 15 1E 14 25 | New English Hex + +Ghost On Church Front (Night): +10ねんまえ オズワルドにやられたんだ。しくしく +I was beaten 10 years ago by Oswald. Weeping +$4439A +17 01 00 40 56 47 2C 28 79 AA A0 9D B1 3E 4C 4F 52 38 56 61 C3 34 30 34 30 | Original Japanese Hex +LENGTH 1 0 ね ん ま え オ ズ ワ ル ド に や ら れ た ん だ 。 し く し く | Original Japanese Text +LENGTH I W A S B E A T E N B Y O S W A L D . . | New English Text +17 12 28 20 0A 1C 28 0B 0E 0A 1D 0E 17 28 0B 22 28 18 1C 20 0A 15 0D C3 C3 | New English Hex + +Ghost Bottom Right (Night): +なっ でただろ +Would have not become / It is only infiltration +$41E94 +06 3D 71 28 64 38 61 53 | Original Japanese Hex +LENGTH な っ で た だ ろ | Original Japanese Text +LENGTH F I N D M E | New English Text +06 0F 12 17 0D 28 16 0E | New English Hex + +Ghost In Plaza (Night): +オレはゴート騎士団に いたんだが いまはこのとうりさ スレイ団長に もうしわけがたたなくて+++ +I became sick Gort Knights but without other was sorry this is Tori is now led by Sleigh + + + +$443B3 (Line 1) +39 07 79 9E 42 A7 F7 88 D0 20 D1 3E 28 2A 38 56 61 57 28 2A 47 42 32 41 3C 2B 50 33 | Original Japanese Hex +LENGTH LENGTH オ レ は ゴ ー ト 騎 士 団 に い た ん だ が い ま は こ の と う り さ | Original Japanese Text +LENGTH I G O T S I C K B E F O R E T H E G R E A T | New English Text +1A 12 28 10 18 1D 28 1C 12 0C 14 28 0B 0E 0F 18 1B 0E 28 1D 11 0E 28 10 1B 0E 0A 1D | New English Hex +$443CF (Line 2) +74 12 13 14 81 9E 76 D1 D2 3E 28 4B 2B 34 54 31 57 38 38 3D 30 3B 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH ス レ イ 団 長 に も う し わ け が た た な く て + + + | Original Japanese Text +LENGTH B A T T L E W I T H T H E K N I G H T S . | New English Text +17 0B 0A 1D 1D 15 0E 28 20 12 1D 11 28 1D 11 0E 28 14 17 12 10 11 1D 1C C3 | New English Hex + +---------------- +Chiberus - Inn: +---------------- +Green Hair Boy: +L+R ボタンで パーティのじゅんばんが かえれます +Order of the party with L + R buttons going back +$4407F +58 01 0B 15 18 1B B6 84 A2 64 28 B7 F7 87 5C 41 5D 73 56 66 56 57 28 2E 2C 52 47 35 | Original Japanese Hex +LENGTH LENGTH LENGTH L + R ボ タ ン で パ ー テ ィ の じ ゅ ん ば ん が か え れ ま す | Original Japanese Text +LENGTH L , R : C H A N G E S O R D E R O F P A R T Y | New English Text +1A 15 C4 1B D6 28 0C 11 0A 17 10 0E 1C 28 18 1B 0D 0E 1B 28 18 0F 28 19 0A 1B 1D 22 | New English Hex + +Red Hair Boy: +さいきんは 魔物どものせいで たびが しにくいぜ +Recently, the journey is hard because of the many evils +$4429E +37 07 33 2A 2F 56 42 28 E0 33 65 4B 41 36 2A 64 28 38 67 57 28 34 3E 30 2A 5F | Original Japanese Hex +LENGTH LENGTH さ い き ん は 魔 物 ど も の せ い で た び が し に く い ぜ | Original Japanese Text +LENGTH M Y J O U R N E Y H E R E W A S H A R D . | New English Text +18 16 22 28 13 18 1E 1B 17 0E 22 28 11 0E 1B 0E 28 20 0A 1C 28 11 0A 1B 0D C3 | New English Hex + +Brown Hair Girl: +ボタンは夬定 Bボタンは取り消し これ きほん!! +Button B button is basically 夬定 cancel this!! +$440DF +79 06 0D 0F 0A B6 84 A2 42 FF 00 28 0B B6 84 A2 42 22 50 23 34 28 32 52 28 2F 46 56 25 25 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH A ボ タ ン は 夬 定 B ボ タ ン は 取 り 消 し こ れ き ほ ん ! ! | Original Japanese Text +LENGTH B : U S E D T O C A N C E L C O M M A N D S ! ! ! | New English Text +1A 0B D6 28 1E 1C 0E 0D 28 1D 18 28 0C 0A 17 0C 0E 15 28 0C 18 16 16 0A 17 0D 1C 25 25 25 | New English Hex + +Purple Hair Tube Head Man: +おれはゴートからきたんだが 騎士団のスレイが すごく ソフィアのことを しんぱいしていたぜ +Slay the Knights I was even worried about that, but I'm very Sophia came from Gort +$4425B (Line 1) +35 0F 2D 52 42 A7 F7 88 2E 4F 2F 38 56 61 57 28 D0 20 D1 41 81 9E 76 57 | Original Japanese Hex +LENGTH LENGTH お れ は ゴ ー ト か ら き た ん だ が 騎 士 団 の ス レ イ が | Original Japanese Text +LENGTH I W A S W O R R I E D F O R S O F I A | New English Text +16 12 28 20 0A 1C 28 20 18 1B 1B 12 0E 0D 28 0F 18 1B 28 1C 18 0F 12 0A | New English Hex +$44273 (Line 2) +35 06 35 5B 30 28 83 90 5C 75 41 32 3C 55 28 34 56 6B 2A 34 3B 2A 38 5F | Original Japanese Hex +LENGTH LENGTH す ご く ソ フ ィ ア の こ と を し ん ぱ い し て い た ぜ | Original Japanese Text +LENGTH W H E N S H E C A M E F R O M G O R T | New English Text +16 20 11 0E 17 28 1C 11 0E 28 0C 0A 16 0E 28 0F 1B 18 16 28 10 18 1B 1D | New English Hex + +---------------------- +Chiberus - Item Shop: +---------------------- +Old Man: +チベリスの鬼いで いつでも この村に 戻れるんじゃよ +So what I always go back to the village of Chiberus +$43FAD +79 05 10 13 85 B5 9C 81 41 3D 2A 64 28 2A 3A 64 4B 28 32 41 27 3E 28 1A 52 51 56 5D 72 4E | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH チ ベ リ ス の 鬼 い で い つ で も こ の 村 に 戻 れ る ん じ ゃ よ | Original Japanese Text +LENGTH C H I B W A R P T E L E P O R T S Y O U B A C K ゃ よ | New English Text +1A 0C 11 12 0B 20 0A 1B 19 28 1D 0E 15 0E 19 18 1B 1D 1C 28 22 18 1E 28 0B 0A 0C 14 72 4E | New English Hex + +Green Hair Boy: +体力がへったら 薬草かタマゴ! タマゴは ねだんも 効き目も 薬草の2ばい なんだ +Eggs! eggs'm a double strength herbal medicinal plants also effect the prices have been reduced or +$4428B (Line 1) +6E 00 08 09 45 CF 57 45 71 38 4F 28 67 1F 2E 84 93 A7 25 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH 体 力 が へ っ た ら 薬 草 か タ マ ゴ ! | Original Japanese Text +LENGTH A N E G G I S T W I C E A S | New English Text +11 11 0E 15 19 28 0B 18 18 1C 1D 28 1C 1D 0A 16 12 17 0A | New English Hex +$444AD (Line 2) +98 0A 0C 0F 10 84 93 A7 42 28 40 61 56 4B 28 2F 2F 52 4B 28 67 1F 41 02 66 2A 28 3D 56 61 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH タ マ ゴ は ね だ ん も 効 き 目 も 薬 草 の 2 ば い な ん だ | Original Japanese Text +LENGTH S T R O N G A S A M E D I C I N A L H E R B ! ん だ | New English Text +1A 0B 22 28 1D 0A 14 12 17 10 28 0A 28 16 0E 0D 12 0C 12 17 0A 15 28 11 0E 1B 0B 25 56 61 | New English Hex + +Red Hair Boy: +むかし ゴート騎士団っていう すごいれんちゅうが いたんだよ でも 10ねんまえのオズワルドとの戦いで いまは ズタズタらしい +Now seems to devastating in the battle against Oswald of 10 years ago even though I've just called the Knights of Gort stomach amazing guys a long time ago +$43FCB (Line 1) +02 49 2E 34 | Original Japanese Hex +LENGTH む か し | Original Japanese Text +LENGTH T H E | New English Text +02 1D 11 0E | New English Hex +$43FCF (Line 2) +39 04 A7 F7 88 D0 20 D1 71 3B 2A 2B 28 35 5B 2A 52 56 39 73 2B 57 28 2A 38 56 61 4E | Original Japanese Hex +LENGTH LENGTH ゴ ー ト 騎 士 団 っ て い う す ご い れ ん ち ゅ う が い た ん だ よ | Original Japanese Text +LENGTH K N I G H T S O F G O R T H A D B A T T L E D | New English Text +1A 14 17 12 10 11 1D 1C 28 18 0F 28 10 18 1B 1D 28 11 0A 0D 28 0B 0A 1D 1D 15 0E 0D | New English Hex +$43FEB (Line 3) +13 64 4B 28 01 00 40 56 47 2C 41 79 AA A0 9D B1 3C 41 D7 2A 64 | Original Japanese Hex +LENGTH で も 1 0 ね ん ま え の オ ズ ワ ル ド と の 戦 い で | Original Japanese Text +LENGTH C O U R A G E O U S L Y A G A I N S T | New English Text +13 0C 18 1E 1B 0A 10 0E 18 1E 1C 15 22 28 0A 10 0A 12 17 1C 1D | New English Hex +$44000 (Line 4) +0A 2A 47 42 28 AA 84 AA 84 4F 34 2A | Original Japanese Hex +LENGTH い ま は ズ タ ズ タ ら し い | Original Japanese Text +LENGTH E V I L O S W A L D | New English Text +0A 0E 1F 12 15 28 18 1C 20 0A 15 0D | New English Hex + +Red Hair Boy (Night): ++++わっ、びっくりするじゃないか ++++Boo!, Try not to be surprised +$443E8 +70 00 01 02 18 18 18 54 71 C4 67 71 30 50 35 51 5D 72 3D 2A 2E | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH + + + わ っ 、 び っ く り す る じ ゃ な い か | Original Japanese Text +LENGTH B O O ! A L W A Y S B E R E A D Y . | New English Text +13 0B 18 18 25 0A 15 20 0B 22 1C 28 0B 0E 28 1B 0E 0A 0D 22 C3 | New English Hex + +--------------------------- +Chiberus - Barn Above Inn: +--------------------------- +Old Man: +そとにでたら Xボタンの拔大図で さきの地形をみながら すすむんじゃ +Maybe go looking at the terrain ahead using the X button map zoom out +$440FD (Line 1) +05 37 3C 3E 64 38 4F | Original Japanese Hex +LENGTH そ と に で た ら | Original Japanese Text +LENGTH B U T T O N | New English Text +05 0B 1E 1D 1D 18 17 | New English Hex +$44104 (Line 2) +9A 05 06 07 0E 21 B6 84 A2 41 01 02 03 64 28 33 2F 41 DF 07 55 48 3D 57 4F 28 35 35 49 56 5D 72 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH X ボ タ ン の 拔 大 図 で さ き の 地 形 を み な が ら す す む ん じ ゃ | Original Japanese Text +LENGTH X : Z O O M O U T M A P T O S E E A H E A D む ん じ ゃ | New English Text +1A 21 D6 23 18 18 16 28 18 1E 1D 28 16 0A 19 28 1D 18 28 1C 0E 0E 28 0A 11 0E 0A 0D 49 56 5D 72 | New English Hex + +Brown Hair Girl: +STARTボタンで メンバー選択 装備+ITEMも このボタン! +Member Selection button in the START This button is also equipment + ITEM! +$44124 (Line 1) +4F 0E 0F 1C 1D 0A 1B 1D B6 84 A2 64 28 96 A2 B2 F7 1C 57 | Original Japanese Hex +LENGTH LENGTH LENGTH S T A R T ボ タ ン で メ ン バ ー 選 択 | Original Japanese Text +LENGTH S T A R T : W I L L S E L E C T | New English Text +11 1C 1D 0A 1B 1D D6 28 20 12 15 15 28 1C 0E 15 0E 0C 1D | New English Hex +$44137 (Line 2) +4E 00 02 60 DC 18 12 1D 0E 16 4B 28 32 41 B6 84 A2 25 | Original Japanese Hex +LENGTH LENGTH LENGTH 装 備 + I T E M も こ の ボ タ ン ! | Original Japanese Text +LENGTH M E M B E R S T O E Q U I P ! | New English Text +10 16 0E 16 0B 0E 1B 1C 28 1D 18 28 0E 1A 1E 12 19 25 | New English Hex + +-------------------------- +Chiberus - Alberts House: +-------------------------- +Mum: +がんばりなさい。あなたは選ばれた者なんですから +Try to hold on. Because you are the person, who has been chosen +$41E9C +36 0C 57 56 66 50 3D 33 2A C3 29 3D 38 42 1C 66 52 38 E7 3D 56 64 35 2E 4F | Original Japanese Hex +LENGTH LENGTH が ん ば り な さ い 。 あ な た は 選 ば れ た 者 な ん で す か ら | Original Japanese Text +LENGTH K E E P T R Y I N G Y O U R H A R D E S T | New English Text +17 14 0E 0E 19 28 1D 1B 22 12 17 10 28 22 18 1E 1B 28 11 0A 1B 0D 0E 1C 1D | New English Hex + A L W A Y S T R Y T O K E E P G O I N G + +------------------------- +Chiberus - Middle House: +------------------------- +Brown Hair Girl (Downstairs): +敵をたおし お金をためなさい そのお金で 装備をととのえていくといいわ +Please defeat the enemy and save money. I hope will prepare the equipment with the money +$4409B (Line 1) +2D 00 39 55 38 2D 34 28 2D D3 55 38 4A 3D 33 2A | Original Japanese Hex +LENGTH LENGTH 敵 を た お し お 金 を た め な さ い | Original Japanese Text +LENGTH B E A T E N E M I E S T O | New English Text +0E 0B 0E 0A 1D 28 0E 17 0E 16 12 0E 1C 28 1D 18 | New English Hex +$440AB (Line 2) +33 06 37 41 2D D3 64 28 60 DC 55 3C 3C 41 2C 3B 2A 30 3C 2A 2A 54 | Original Japanese Hex +LENGTH LENGTH そ の お 金 で 装 備 を と と の え て い く と い い わ | Original Japanese Text +LENGTH O B T A I N C A S H A N D I T E M S | New English Text +14 18 0B 1D 0A 12 17 28 0C 0A 1C 11 28 0A 17 0D 28 12 1D 0E 16 1C | New English Hex + +Brown Hair Boy (Downstairs): +地形によって ダメージはかわる。これを地形効果という おぼえましたか? +Damage will vary depending on terrain. Did you remember that the topographic effect this? +$44199 (Line 1) +99 01 14 15 16 DF 07 3E 4E 71 3B 28 AD 96 F7 A9 42 2E 54 51 C3 32 52 55 DF 07 2F 34 3C 2A 2B | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH 地 形 に よ っ て ダ メ ー ジ は か わ る 。 こ れ を 地 形 効 果 と い う | Original Japanese Text +LENGTH T E R R A I N T Y P E S A F F E C T D A M A G E と い う | New English Text +1A 1D 0E 1B 1B 0A 12 17 28 1D 22 19 0E 1C 28 0A 0F 0F 0E 0C 1D 28 0D 0A 16 0A 10 0E 3C 2A 2B | New English Hex +$441B8 (Line 2) +07 2D 6A 2C 47 34 38 2E 24 | Original Japanese Hex +LENGTH お ぼ え ま し た か ? | Original Japanese Text +LENGTH S T R E N G T H | New English Text +07 1C 1D 1B 0E 17 10 1D 11 | New English Hex + +Green Hair Girl (Downstairs): +物は かったときの 7わり5ぶ にしか ならないの だから かうまえに いちど セーブしておくと いいわよ +Do not you be only 5 to 70% of the hump when you buy the things. It 's good idea to save before you buy +$44899 (Line 1) +38 00 33 42 28 2E 71 38 3C 2F 41 28 07 54 50 05 68 28 3E 34 2E 28 3D 4F 3D 2A 41 | Original Japanese Hex +LENGTH LENGTH 物 は か っ た と き の 7 わ り 5 ぶ に し か な ら な い の | Original Japanese Text +LENGTH S H O P S B U Y A T A F R A C T I O N O F | New English Text +19 1C 11 18 19 1C 28 0B 1E 22 28 0A 1D 28 0A 28 0F 1B 0A 0C 1D 12 18 17 28 18 0F | New English Hex +$448B4 (Line 2) +1A 61 2E 4F 28 2E 2B 47 2C 3E 28 2A 39 65 28 82 F7 B4 34 3B 2D 30 3C 28 2A 2A 54 4E | Original Japanese Hex +LENGTH だ か ら か う ま え に い ち ど セ ー ブ し て お く と い い わ よ | Original Japanese Text +LENGTH T H E R E T A I L P R I C E S F O R I T E M S | New English Text +1A 1D 11 0E 28 1B 0E 1D 0A 12 15 28 19 1B 12 0C 0E 1C 28 0F 18 1B 28 12 1D 0E 16 1C | New English Hex + +Brown Hair Girl (Upstairs): +グローバスのぶんめいは すばらしかったのに ひとびとは ぎゃくに くるしいせいかつを おくったのよ +civilization of Globus was great even though people lived a hard life on the contrary +$44149 (Line 1) +14 A5 9F F7 B2 81 41 68 56 4A 2A 42 28 35 66 4F 34 2E 71 38 41 3E | Original Japanese Hex +LENGTH グ ロ ー バ ス の ぶ ん め い は す ば ら し か っ た の に | Original Japanese Text +LENGTH C I V I L I Z A T I O N I M P R O V E D | New English Text +14 0C 12 1F 12 15 12 23 0A 1D 12 18 17 28 12 16 19 1B 18 1F 0E 0D | New English Hex +$4415F (Line 2) +1A 43 3C 67 3C 42 28 58 72 30 3E 28 30 51 34 2A 36 2A 2E 3A 55 28 2D 30 71 38 41 4E | Original Japanese Hex +LENGTH ひ と び と は ぎ ゃ く に く る し い せ い か つ を お く っ た の よ | Original Japanese Text +LENGTH B U T P E O P L E H A D A H A R D T I M E . | New English Text +1A 0B 1E 1D 28 19 0E 18 19 15 0E 28 11 0A 0D 28 0A 28 11 0A 1B 0D 28 0D 12 16 0E C3 | New English Hex + +Old Man Purple (Upstairs): +グローバスは こだいのぶんめい 「水晶」は ぶんめいふっかつの かぎ +Golbus ancient civilization. "Crystal" is the key to revival civilization +$44038 (Line 1) +0E A5 9F F7 B2 81 42 28 32 61 2A 41 68 56 4A 2A | Original Japanese Hex +LENGTH グ ロ ー バ ス は こ だ い の ぶ ん め い | Original Japanese Text +LENGTH T H E C R Y S T A L W A S | New English Text +0E 1D 11 0E 28 0C 1B 22 1C 1D 0A 15 28 20 0A 1C | New English Hex +$44048 (Line 2) +11 C1 DD DE C2 42 28 68 56 4A 2A 44 71 2E 3A 41 28 2E 58 | Original Japanese Hex +LENGTH 「 水 晶 」 は ぶ ん め い ふ っ か つ の か ぎ | Original Japanese Text +LENGTH K E Y T O O U R R E V I V A L | New English Text +11 14 0E 22 28 1D 18 28 18 1E 1B 28 1B 0E 1F 12 1F 0A 15 | New English Hex + +大魔導師グローバスは このぶんめいを ー手に にぎっていたようじゃ +This civilization the Archmage Golbus single-handed gripped +$4405B (Line 2) +31 00 02 E0 E5 DA A5 9F F7 B2 81 42 28 32 41 68 56 4A 2A 55 | Original Japanese Hex +LENGTH LENGTH 大 魔 導 師 グ ロ ー バ ス は こ の ぶ ん め い を | Original Japanese Text +LENGTH O U R C I V I L I Z A T I O N I S | New English Text +12 18 1E 1B 28 0C 12 1F 12 15 12 23 0A 1D 12 18 17 28 12 1C | New English Hex +$4406F (Line 3) +2D 01 F7 40 3E 28 3E 58 71 3B 2A 38 4E 2B 5D 72 | Original Japanese Hex +LENGTH LENGTH ー 手 に に ぎ っ て い た よ う じ ゃ | Original Japanese Text +LENGTH I N A N E V I L G R I P | New English Text +0E 12 17 28 0A 17 28 0E 1F 12 15 28 10 1B 12 19 | New English Hex + +Old Man Red (Upstairs): +わしは 10ねんまえ あのひかりの中に いたんじゃよ +I 10 Years ago He In the hunt Faith +$441E1 (Line 1) +39 11 54 34 42 28 01 00 40 56 47 2C 28 29 41 43 2E 50 41 4A 3E 28 2A 38 56 5D 72 4E | Original Japanese Hex +LENGTH LENGTH わ し は 1 0 ね ん ま え あ の ひ か り の 中 に い た ん じ ゃ よ | Original Japanese Text +LENGTH 1 0 Y E A R S A G O , A T T H E B A T T L E | New English Text +1A 01 00 28 22 0E 0A 1B 1C 28 0A 10 18 C4 28 0A 1D 28 1D 11 0E 28 0B 0A 1D 1D 15 0E | New English Hex + +ひとりの おんなのこが はっした あのひかりは またたくまに ひろがり オズワルドを のみこんだんじゃ +Light that the girl was alone originated the Maybe Oswald swallowed the wildfire spread +$441FD (Line 2) +16 43 3C 50 41 28 2D 56 3D 41 32 57 28 42 71 34 38 28 29 41 43 2E 50 42 | Original Japanese Hex +LENGTH ひ と り の お ん な の こ が は っ し た あ の ひ か り は | Original Japanese Text +LENGTH O S W A L D W A S B L A S T E D A W A Y | New English Text +16 18 1C 20 0A 15 0D 28 20 0A 1C 28 0B 15 0A 1C 1D 0E 0D 28 0A 20 0A 22 | New English Hex +$44215 (Line 3) +1A 47 38 38 30 47 3E 28 43 53 57 50 28 79 AA A0 9D B1 55 28 41 48 32 56 61 56 5D 72 | Original Japanese Hex +LENGTH ま た た く ま に ひ ろ が り オ ズ ワ ル ド を の み こ ん だ ん じ ゃ | Original Japanese Text +LENGTH B Y B R I G H T L I G H T F R O M S O F I A . | New English Text +1A 0B 22 28 0B 1B 12 10 11 1D 28 15 12 10 11 1D 28 0F 1B 18 16 28 1C 18 0F 12 0A C3 | New English Hex + +ゴート騎士団の スレイは みなしごになった そのこを ひきとっていかれたんじゃよ +Slay the Knight of gort took custody of and its children orphaned +$44231 (Line 4) +39 04 A7 F7 88 D0 20 D1 41 28 81 9E 76 42 28 48 3D 34 5B 3E 3D 71 38 28 37 41 32 55 | Original Japanese Hex +LENGTH LENGTH ゴ ー ト 騎 士 団 の ス レ イ は み な し ご に な っ た そ の こ を | Original Japanese Text +LENGTH S L A Y O F G O R T H A S T A K E N C A R E | New English Text +1A 1C 15 0A 22 28 18 0F 28 10 18 1B 1D 28 11 0A 1C 28 1D 0A 14 0E 17 28 0C 0A 1B 0E | New English Hex +$4424D (Line 5) +0C 43 2F 3C 71 3B 2A 2E 52 38 56 5D 72 4E | Original Japanese Hex +LENGTH ひ き と っ て い か れ た ん じ ゃ よ | Original Japanese Text +LENGTH O F H E R S I N C E . | New English Text +0C 18 0F 28 11 0E 1B 28 1C 12 17 0C 0E C3 | New English Hex + +------------------------- +Chiberus - Bottom House: +------------------------- +Brown Hair Boy: +10ねんまえの あのひかりは なんだったんだろう +What was that light 10 years ago, I wonder +$4400C +17 01 00 40 56 47 2C 41 28 29 41 43 2E 50 42 28 3D 56 61 71 38 56 61 53 2B | Original Japanese Hex +LENGTH 1 0 ね ん ま え の あ の ひ か り は な ん だ っ た ん だ ろ う | Original Japanese Text +LENGTH W H A T W A S T H E L I G H T A B O U T | New English Text +17 20 11 0A 1D 28 20 0A 1C 28 1D 11 0E 28 15 12 10 11 1D 28 0A 0B 18 1E 1D | New English Hex + +Old Man: +よるになると 魔物どもが つよくなるんじゃ 気をつけろよ +Maybe many evils have become strong at night. Be careful +$440C1 (Line 1) +34 08 4E 51 3E 3D 51 3C 28 E0 33 65 4B 57 28 3A 4E 30 3D 51 56 5D 72 | Original Japanese Hex +LENGTH LENGTH よ る に な る と 魔 物 ど も が つ よ く な る ん じ ゃ | Original Japanese Text +LENGTH A T N I G H T F O E S A R E M O R E | New English Text +15 0A 1D 28 17 12 10 11 1D 28 0F 18 0E 1C 28 0A 1B 0E 28 16 18 1B 0E | New English Hex +$440D8 (Line 2) +05 ED 55 3A 31 53 4E | Original Japanese Hex +LENGTH 気 を つ け ろ よ | Original Japanese Text +LENGTH S T R O N G | New English Text +05 1C 1D 1B 18 17 10 | New English Hex + +Red Hair Boy: +また オズワルドが 蘇ったらしいよ +Oswald also seems to have revived +$44025 +30 0A 47 38 28 79 AA A0 9D B1 57 28 50 71 38 4F 34 2A 4E | Original Japanese Hex +LENGTH LENGTH ま た オ ズ ワ ル ド が 蘇 っ た ら し い よ | Original Japanese Text +LENGTH O S W A L D H A S R E V I V E D | New English Text +11 18 1C 20 0A 15 0D 28 11 0A 1C 28 1B 0E 1F 12 1F 0E 0D | New English Hex + +Green Hair Tube Head Man: +攻撃は まえからより うしろからのほうが 効果があるぞ +An attack from behind is more effective than from the front +$4417B +5A 15 16 C7 C8 42 28 47 2C 2E 4F 4E 50 28 2B 34 53 2E 4F 41 46 2B 57 28 2F 34 57 29 51 60 | Original Japanese Hex +LENGTH LENGTH LENGTH 攻 撃 は ま え か ら よ り う し ろ か ら の ほ う が 効 果 が あ る ぞ | Original Japanese Text +LENGTH R E A R A T T A C K S A R E E F F E C T I V E . る ぞ | New English Text +1A 1B 0E 0A 1B 28 0A 1D 1D 0A 0C 14 1C 28 0A 1B 0E 28 0E 0F 0F 0E 0C 1D 12 1F 0E C3 51 60 | New English Hex + +Purple Hair Girl: +ふしぎな果物を特ってる? +I specialize Ru strange fruit? +$43F9D +6B 04 05 07 44 34 58 3D 34 33 55 32 71 3B 51 24 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH ふ し ぎ な 果 物 を 特 っ て る ? | Original Japanese Text +LENGTH K N O W O D D F R U I T ? ? | New English Text +0E 14 17 18 20 28 18 0D 0D 0F 1B 1E 12 1D 24 24 | New English Hex + +Yes Selected: +ひると よるを かえる力を 特ってるの くらい町なんかで つかうと いいわよ +Sure enough, when used in town have something Tsu and especially the power to change depending noon +$44751 (Line 1) +32 0E 43 51 3C 28 4E 51 55 28 2E 2C 51 CF 55 28 32 71 3B 51 41 | Original Japanese Hex +LENGTH LENGTH ひ る と よ る を か え る 力 を 特 っ て る の | Original Japanese Text +LENGTH I F U S E D I N A T O W N I T | New English Text +13 12 0F 28 1E 1C 0E 0D 28 12 17 28 0A 28 1D 18 20 17 28 12 1D | New English Hex +$47A09 (Line 2) +31 03 30 4F 2A 26 3D 56 2E 64 28 3A 2E 2B 3C 28 2A 2A 54 4E | Original Japanese Hex +LENGTH LENGTH く ら い 町 な ん か で つ か う と い い わ よ | Original Japanese Text +LENGTH M A K E S I T N I G H T T I M E | New English Text +12 16 0A 14 0E 1C 28 12 1D 28 17 12 10 11 1D 28 1D 12 16 0E | New English Hex + +No Selected: +ひとつくらい 特ってた方がいいと 鬼うわ +Wow What a demon who was especially nice and long one +$44766 (Line 1) +53 07 11 43 3C 3A 30 4F 2A 28 32 71 3B 38 FD 57 2A 2A 3C 28 3D 2B 54 | Original Japanese Hex +LENGTH LENGTH LENGTH ひ と つ く ら い 特 っ て た 方 が い い と 鬼 う わ | Original Japanese Text +LENGTH W H A T A L O N G D A Y I T I S ! | New English Text +15 20 11 0A 1D 28 0A 28 15 18 17 10 28 0D 0A 22 28 12 1D 28 12 1C 25 | New English Hex + +Purple Hair Girl (Night): +ぎんゆうしじんさまの ことを おもうと よるもねむれなくって+++ +And I could not sleep at night when I think that the bard customers + + + +$44417 (Line 1) +12 58 56 4D 2B 34 5D 56 33 47 41 28 32 3C 55 28 2D 4B 2B 3C | Original Japanese Hex +LENGTH ぎ ん ゆ う し じ ん さ ま の こ と を お も う と | Original Japanese Text +LENGTH I C O U L D N O T S L E E P . . | New English Text +12 12 28 0C 18 1E 15 0D 28 17 18 1D 28 1C 15 0E 0E 19 C3 C3 | New English Hex +$4442B (Line 2) +6C 0A 0B 0C 4E 51 4B 40 49 52 3D 30 71 3B 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH よ る も ね む れ な く っ て + + + | Original Japanese Text +LENGTH T H I N K I N G A L O T . . | New English Text +0F 1D 11 12 17 14 12 17 10 28 0A 28 15 18 1D C3 C3 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 02 - Gort.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 02 - Gort.txt new file mode 100644 index 00000000..07377703 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 02 - Gort.txt @@ -0,0 +1,524 @@ +----------- +Gort City: +----------- +---------------- +Gort - Outside: +---------------- +Knight - Bottom Right: +ここはゴートの都です。きっと いい物が かえますよ +This is the the City of Gort. The change is a good thing surely +$42087 +58 07 11 32 32 42 A7 F7 88 41 28 64 35 C3 2F 71 3C 28 2A 2A 33 57 28 2E 2C 47 35 4E | Original Japanese Hex +LENGTH LENGTH LENGTH こ こ は ゴ ー ト の 都 で す 。 き っ と い い 物 が か え ま す よ | Original Japanese Text +LENGTH W E L C O M E T O T H E C I T Y O F G O R T | New English Text +1A 20 0E 15 0C 18 16 0E 28 1D 18 28 1D 11 0E 28 0C 12 1D 22 28 18 0F 28 10 18 1B 1D | New English Hex + +Knight - Bottom Middle: +王様に おあいください このさきの お城に いらっしゃいます +You come to the castle earlier this please love your king +$420EA (Line 1) +2A 01 EB 2D 3E 28 2D 29 2A 30 61 33 2A | Original Japanese Hex +LENGTH LENGTH 王 様 に お あ い く だ さ い | Original Japanese Text +LENGTH P L E A S E V I S I T | New English Text +0B 19 15 0E 0A 1C 0E 28 1F 12 1C 12 1D | New English Hex +$420F7 (Line 2) +31 07 32 41 33 2F 41 28 2D 6A 3E 28 2A 4F 71 34 72 2A 47 35 | Original Japanese Hex +LENGTH LENGTH こ の さ き の お 城 に い ら っ し ゃ い ま す | Original Japanese Text +LENGTH C A S T L E , T O S E E K I N G | New English Text +13 0C 0A 1C 1D 15 0E C4 28 1D 18 28 1C 0E 0E 28 14 12 17 10 | New English Hex + +Knight - Bottom Left: +ノイラートの村が どこにあるか しってますか? +Do you know where to find the village of Neurath? +$420A3 +36 06 8D 76 9B F7 88 41 27 57 28 65 32 3E 29 51 2E 28 34 71 3B 47 35 2E 24 | Original Japanese Hex +LENGTH LENGTH ノ イ ラ ー ト の 村 が ど こ に あ る か し っ て ま す か ? | Original Japanese Text +LENGTH K N O W A B O U T N E U R A T H T O W N ? | New English Text +17 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 24 | New English Hex + +Yes Selected: +かげのゆびわを 特つ レッサーデーモンに おそわれているらしいですよ +Is apparently being attacked by Tokutsu Lesser daemon ring shadow +$4518C (Line 1) +29 08 2E 5A 41 4D 67 54 55 28 32 3A | Original Japanese Hex +LENGTH LENGTH か げ の ゆ び わ を 特 つ | Original Japanese Text +LENGTH I T I S B E I N G | New English Text +0A 12 1D 28 12 1C 28 0B 0E 12 17 10 | New English Hex +$420BC (Line 2) +16 9E BD 7F F7 B0 F7 97 A2 3E 28 2D 37 54 52 3B 2A 51 4F 34 2A 64 35 4E | Original Japanese Hex +LENGTH レ ッ サ ー デ ー モ ン に お そ わ れ て い る ら し い で す よ | Original Japanese Text +LENGTH A T T A C K E D B Y A D E M O N N O W | New English Text +16 0A 1D 1D 0A 0D 14 0E 0D 28 0B 22 28 0A 28 0D 0E 16 18 17 28 17 18 20 | New English Hex + +No Selected: +この町からみて 北西の方向に ありますよ +It is in the direction of northwest viewed from this town +$420D4 +33 02 32 41 26 2E 4F 48 3B 28 FC FA 41 FD FE 3E 28 29 50 47 35 4E | Original Japanese Hex +LENGTH LENGTH こ の 町 か ら み て 北 西 の 方 向 に あ り ま す よ | Original Japanese Text +LENGTH I T S I N T H E N O R T H W E S T . | New English Text +14 12 1D 1C 28 12 17 28 1D 11 0E 28 17 18 1B 1D 11 20 0E 1C 1D C3 | New English Hex + +Knight - Middle Right: +かくちのモンスターさわぎで 町中が あわただしいんです +The whole town I busy monster commotion around the country +$4202F +5A 0E 0F 2E 30 39 41 97 A2 81 84 F7 33 54 58 64 28 26 4A 57 28 29 54 38 61 34 2A 56 64 35 | Original Japanese Hex +LENGTH LENGTH LENGTH か く ち の モ ン ス タ ー さ わ ぎ で 町 中 が あ わ た だ し い ん で す | Original Japanese Text +LENGTH M O N S T E R S A P P E A R I N G A L L O V E R で す | New English Text +1A 16 18 17 1C 1D 0E 1B 1C 28 0A 19 19 0E 0A 1B 12 17 10 28 0A 15 15 28 18 1F 0E 1B 64 35 | New English Hex + +Knight - Top Right: +魔物どもを みはるのも きつい しごとです +It's amazing monsters us it is also hard work +$4210B +34 01 E0 33 65 4B 55 28 48 42 51 41 4B 28 2F 3A 2A 28 34 5B 3C 64 35 | Original Japanese Hex +LENGTH LENGTH 魔 物 ど も を み は る の も き つ い し ご と で す | Original Japanese Text +LENGTH M O N S T E R S A R E H A R D W O R K | New English Text +15 16 18 17 1C 1D 0E 1B 1C 28 0A 1B 0E 28 11 0A 1B 0D 28 20 18 1B 14 | New English Hex + +Knight - Bottom Left: +われら 騎士団は 町の中を守るだけで せいいっぱい かなしいことです +Our Knights is sad as hard as possible just to protect the town in the +$4206A (Line 1) +78 05 09 0B 54 52 4F 28 D0 20 D1 42 28 26 41 4A 55 DB 51 61 31 64 28 36 2A 2A 71 6B 2A | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH わ れ ら 騎 士 団 は 町 の 中 を 守 る だ け で せ い い っ ぱ い | Original Japanese Text +LENGTH I T S H A R D E N O U G H , P R O T E C T I N G い | New English Text +1A 12 1D 1C 28 11 0A 1B 0D 28 0E 17 18 1E 10 11 C4 28 19 1B 18 1D 0E 0C 1D 12 17 10 2A | New English Hex +$4214F (Line 2) +07 2E 3D 34 2A 32 3C 64 35 | Original Japanese Hex +LENGTH か な し い こ と で す | Original Japanese Text +LENGTH O U R T O W N | New English Text +07 18 1E 1B 28 1D 18 20 17 | New English Hex + +-------------------------- +Gort - Bottom Left House: +-------------------------- +Old Man: +王様も わしとおなじで もう むりはできん おとしじゃ +Impossible the other 's losing banishment in the same King and I +$44734 +3A 01 EB 2D 4B 28 54 34 3C 2D 3D 5D 64 28 4B 2B 28 49 50 42 64 2F 56 28 2D 3C 34 5D 72 | Original Japanese Hex +LENGTH LENGTH 王 様 も わ し と お な じ で も う む り は で き ん お と し じ ゃ | Original Japanese Text +LENGTH S H O U L D N O T C O N T E M P L A T E L O S S ゃ | New English Text +1A 1D 11 18 1E 15 0D 28 17 18 1D 28 0C 18 17 1D 0E 16 19 15 0A 1D 0E 28 15 18 1C 1C 72 | New English Hex + +--------------------------------- +Gort - Bottom Middle Left House: +--------------------------------- +Knight - Left: +いつから こんなじだいに なってしまったんですかねぇ +Since when fame did you ended up with this era +$4204D +3A 1A 2A 3A 2E 4F 28 32 56 3D 28 5D 61 2A 3E 28 3D 71 3B 34 47 71 38 56 64 35 2E 40 5D | Original Japanese Hex +LENGTH LENGTH い つ か ら こ ん な じ だ い に な っ て し ま っ た ん で す か ね ぇ | Original Japanese Text +LENGTH W H Y W A S I B O R N I N T H I S E R A . ぇ | New English Text +1A 20 11 22 28 20 0A 1C 28 12 28 0B 18 1B 17 28 12 17 28 1D 11 12 1C 28 0E 1B 0A C3 5D | New English Hex + +Knight - Left: +わたしのちちも ゴートの 騎士 でした +My father was also a Knight of Gort +$42122 (Line 1) +32 0E 54 38 34 41 39 39 4B 28 A7 F7 88 41 28 D0 20 28 64 34 38 | Original Japanese Hex +LENGTH LENGTH わ た し の ち ち も ゴ ー ト の 騎 士 で し た | Original Japanese Text +LENGTH M Y D A D W A S A K N I G H T . | New English Text +13 16 22 28 0D 0A 0D 28 20 0A 1C 28 0A 28 14 17 12 10 11 1D C3 | New English Hex + +ゴート騎士団は きっと スレイ団長の もとに むかしの力を取り戻すと 鬼いますよ +There are demon and regain the power of the past on the basis of Sleigh Grandmaster surely Gort Knights +$42137 (Line 2) +35 04 A7 F7 88 D0 20 D1 42 28 2F 71 3C 28 81 9E 76 D1 D2 41 28 4B 3C 3E | Original Japanese Hex +LENGTH LENGTH ゴ ー ト 騎 士 団 は き っ と ス レ イ 団 長 の も と に | Original Japanese Text +LENGTH W E N E E D T O R E G A I N P O W E R | New English Text +16 20 0E 28 17 0E 0E 0D 28 1D 18 28 1B 0E 10 0A 12 17 28 19 18 20 0E 1B | New English Hex +$42158 (Line 3) +70 06 08 0C 49 2E 34 41 CF 55 22 50 1A 35 3C 28 3D 2A 47 35 4E | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH む か し の 力 を 取 り 戻 す と 鬼 い ま す よ | Original Japanese Text +LENGTH U S I N G S L A Y S E X A M P L E . | New English Text +13 1E 1D 12 17 10 28 1C 15 0A 22 1D 28 0E 21 0A 16 19 15 0E C3 | New English Hex + +Knight (Night): +ああ ねむい +Is sleepy Oh +$443FD +05 29 29 28 40 49 2A | Original Japanese Hex +LENGTH あ あ ね む い | Original Japanese Text +LENGTH S L E E P Y | New English Text +05 1C 15 0E 0E 19 22 | New English Hex + +---------------------------------- +Gort - Bottom Middle Right House: +---------------------------------- +Old Man: +むかしは 王様も いせいのいい おひとだったんじゃよ +King also Ja did was contact person of the opposite sex good old days +$44963 +39 06 49 2E 34 42 28 EB 2D 4B 28 2A 36 2A 41 2A 2A 28 2D 43 3C 61 71 38 56 5D 72 4E | Original Japanese Hex +LENGTH LENGTH む か し は 王 様 も い せ い の い い お ひ と だ っ た ん じ ゃ よ | Original Japanese Text +LENGTH W O M E N U S E D T O B E R E C R U I T E D . | New English Text +1A 20 18 16 0E 17 28 1E 1C 0E 0D 28 1D 18 28 0B 0E 28 1B 0E 0C 1B 1E 12 1D 0E 0D C3 | New English Hex + +Girl: +オズワルドなんかに こだいぶんめいを わたしては いけないわ! +Do not pass the ancient literary fame to something Oswald! +$441C1 (Line 1) +11 79 AA A0 9D B1 3D 56 2E 3E 28 32 61 2A 68 56 4A 2A 55 | Original Japanese Hex +LENGTH オ ズ ワ ル ド な ん か に こ だ い ぶ ん め い を | Original Japanese Text +LENGTH O S W A L D I S B E C O M I N G | New English Text +11 18 1C 20 0A 15 0D 28 12 1C 28 0B 0E 0C 18 16 12 17 10 | New English Hex +$441D4 (Line 2) +0B 54 38 34 3B 42 28 2A 31 3D 2A 54 25 | Original Japanese Hex +LENGTH わ た し て は い け な い わ ! | Original Japanese Text +LENGTH M O R E F A M O U S ! | New English Text +0B 16 18 1B 0E 28 0F 0A 16 18 1E 1C 25 | New English Hex + +--------------------------- +Gort - Bottom Right House: +--------------------------- +Man: +グローバスの水晶を さがすには 「水晶の行方」って物が ひつようらしいよ +Thing seems to need What is it, "The Future of the crystal" to find a crystal of Globus +$448FF (Line 1) +0E A5 9F F7 B2 81 41 DD DE 55 28 33 57 35 3E 42 | Original Japanese Hex +LENGTH グ ロ ー バ ス の 水 晶 を さ が す に は | Original Japanese Text +LENGTH W E N E E D T O F I N D | New English Text +0E 20 0E 28 17 0E 0E 0D 28 1D 18 28 0F 12 17 0D | New English Hex +$4490F (Line 2) +33 09 C1 DD DE 41 F2 FD C2 71 3B 33 57 28 43 3A 4E 2B 4F 34 2A 4E | Original Japanese Hex +LENGTH LENGTH 「 水 晶 の 行 方 」 っ て 物 が ひ つ よ う ら し い よ | Original Japanese Text +LENGTH T H E C R Y S T A L O F G L O B U S | New English Text +14 1D 11 0E 28 0C 1B 22 1C 1D 0A 15 28 18 0F 28 10 15 18 0B 1E 1C | New English Hex + +Old Man: +王様は スレイ団長だけが たよりなんじゃ +Only Slay Grandmaster is not you depend on ... on king +$44925 (Line 1) +33 01 EB 2D 42 28 81 9E 76 D1 D2 61 31 57 28 38 4E 50 3D 56 5D 72 | Original Japanese Hex +LENGTH LENGTH 王 様 は ス レ イ 団 長 だ け が た よ り な ん じ ゃ | Original Japanese Text +LENGTH W E C A N D E P E N D O N S L A Y | New English Text +14 20 0E 28 0C 0A 17 28 0D 0E 19 0E 17 0D 28 18 17 28 1C 15 0A 22 | New English Hex + +いま オズワルドに 攻められでもしたら このせかいは ひとたまりもないからのう +Because not stand a chance in this world When you have even been attacked Oswald now +$4493B (Line 2) +12 2A 47 28 79 AA A0 9D B1 3E 28 C7 4A 4F 52 64 4B 34 38 4F | Original Japanese Hex +LENGTH い ま オ ズ ワ ル ド に 攻 め ら れ で も し た ら | Original Japanese Text +LENGTH W O N T S T A N D A C H A N C E | New English Text +12 20 18 17 1D 28 1C 1D 0A 17 0D 28 0A 28 0C 11 0A 17 0C 0E | New English Hex +$4494F (Line 3) +12 32 41 36 2E 2A 42 28 43 3C 38 47 50 4B 3D 2A 2E 4F 41 2B | Original Japanese Hex +LENGTH こ の せ か い は ひ と た ま り も な い か ら の う | Original Japanese Text +LENGTH A G A I N S T O S W A L D N O W . | New English Text +12 0A 10 0A 12 17 1C 1D 28 18 1C 20 0A 15 0D 28 17 18 20 C3 | New English Hex + +--------------------------- +Gort - Middle Right House: +--------------------------- +Girl: +ゴート8せいが いま このせかいを おさめてるんですよ +8 due to Gort is I've been met with this world today +$4477D +1A A7 F7 88 08 36 2A 57 28 2A 47 28 32 41 36 2E 2A 55 28 2D 33 4A 3B 51 56 64 35 4E | Original Japanese Hex +LENGTH ゴ ー ト 8 せ い が い ま こ の せ か い を お さ め て る ん で す よ | Original Japanese Text +LENGTH I C A M E T O G O R T 8 Y E A R S A G O . | New English Text +1A 12 28 0C 0A 16 0E 28 1D 18 28 10 18 1B 1D 28 08 28 22 0E 0A 1B 1C 28 0A 10 18 C3 | New English Hex + +Boy: +ぼく 大きくなったら ゴート騎士団に はいるんだ だって かっこいいだろー +Low's cool to me I'm entering the Gort Knights when you grow up I +$44799 (Line 1) +57 03 0F 6A 30 28 02 2F 30 3D 71 38 4F 28 A7 F7 88 D0 20 D1 3E 28 42 2A 51 56 61 | Original Japanese Hex +LENGTH LENGTH LENGTH ぼ く 大 き く な っ た ら ゴ ー ト 騎 士 団 に は い る ん だ | Original Japanese Text +LENGTH W H E N I G R O W , I W A N T T O B E A | New English Text +19 20 11 0E 17 28 12 28 10 1B 18 20 C4 12 28 20 0A 17 1D 28 1D 18 28 0B 0E 28 0A | New English Hex +$447B4 (Line 2) +0B 61 71 3B 28 2E 71 32 2A 2A 61 53 F7 | Original Japanese Hex +LENGTH だ っ て か っ こ い い だ ろ ー | Original Japanese Text +LENGTH G O R T K N I G H T . | New English Text +0B 10 18 1B 1D 28 14 17 12 10 11 1D C3 | New English Hex + +Girl (Night): +こんな よるおそくまで げんきなのね +It's the spirit until late this evening +$44404 +11 32 56 3D 28 4E 51 2D 37 30 47 64 28 5A 56 2F 3D 41 40 | Original Japanese Hex +LENGTH こ ん な よ る お そ く ま で げ ん き な の ね | Original Japanese Text +LENGTH U P L A T E T H I S N I G H T | New English Text +11 1E 19 28 15 0A 1D 0E 28 1D 11 12 1C 28 17 12 10 11 1D | New English Hex + +------------ +Gort - Bar: +------------ +Barmaid: +さいきんは しょうばい あがったり+++ あなたも さけは のみそうにないしねぇ +Business go bankrupt + + + sake is the best of all medicines Hey not likely to be your only recently +$446D3 (Line 1) +73 11 12 13 33 2A 2F 56 42 28 34 74 2B 66 2A 28 29 57 71 38 50 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH さ い き ん は し ょ う ば い あ が っ た り + + + | Original Japanese Text +LENGTH B U S I N E S S I S G O I N G S L O W , | New English Text +16 0B 1E 1C 12 17 0E 1C 1C 28 12 1C 28 10 18 12 17 10 28 1C 15 18 20 C4 | New English Hex +$446EB (Line 2) +32 12 29 3D 38 4B 28 33 31 42 28 41 48 37 2B 3E 3D 2A 34 40 5D | Original Japanese Hex +LENGTH LENGTH あ な た も さ け は の み そ う に な い し ね ぇ | Original Japanese Text +LENGTH W I N E S T H E B E S T C U R E . | New English Text +13 20 12 17 0E 1C 28 1D 11 0E 28 0B 0E 1C 1D 28 0C 1E 1B 0E C3 | New English Hex + +でも こうして わたしが グダググねていられるのも スレイ団長率いる ゴート騎士団の おかげなのよ +But this way I have is sleeping exhausted also is it a Gort thanks to the Knights, led by Slay Grandmaster +$44700 (Line 3) +18 64 4B 28 32 2B 34 3B 28 54 38 34 57 28 A5 AD A5 AD 40 3B 2A 4F 52 51 41 4B | Original Japanese Hex +LENGTH で も こ う し て わ た し が グ ダ グ グ ね て い ら れ る の も | Original Japanese Text +LENGTH A T L E A S T I C A N S L E E P S A F E | New English Text +18 0A 1D 28 15 0E 0A 1C 1D 28 12 28 0C 0A 17 28 1C 15 0E 0E 19 28 1C 0A 0F 0E | New English Hex +$4471A (Line 4) +56 05 0D 81 9E 76 D1 D2 58 2A 51 28 A7 F7 88 D0 20 D1 41 28 2D 2E 5A 3D 41 4E | Original Japanese Hex +LENGTH LENGTH LENGTH ス レ イ 団 長 率 い る ゴ ー ト 騎 士 団 の お か げ な の よ | Original Japanese Text +LENGTH T H A N K S T O T H E K N I G H T S A I D | New English Text +18 1D 11 0A 17 14 1C 28 1D 18 28 1D 11 0E 28 14 17 12 10 11 1D 1C 28 0A 12 0D | New English Hex + +-------------------------- +Gort - Middle Left House: +-------------------------- +Girl: +大地にふういんされた グローバスのおんねんが オズワルドを よびおこしたっていう うわさよ +Rumor grudge of Globus, which is sealed in the earth called aroused Oswald +$448D0 (Line 1) +35 00 02 DF 3E 44 2B 2A 56 33 52 38 28 A5 9F F7 B2 81 41 2D 56 40 56 57 | Original Japanese Hex +LENGTH LENGTH 大 地 に ふ う い ん さ れ た グ ロ ー バ ス の お ん ね ん が | Original Japanese Text +LENGTH G L O B U S I S S E A L E D I N T H E | New English Text +16 10 15 18 0B 1E 1C 28 12 1C 28 1C 0E 0A 15 0E 0D 28 12 17 28 1D 11 0E | New English Hex +$448E8 (Line 2) +15 79 AA A0 9D B1 55 28 4E 67 2D 32 34 38 71 3B 2A 2B 28 2B 54 33 4E | Original Japanese Hex +LENGTH オ ズ ワ ル ド を よ び お こ し た っ て い う う わ さ よ | Original Japanese Text +LENGTH G R O U N D . O S W A L D I S T H E R E | New English Text +15 10 1B 18 1E 17 0D C3 18 1C 20 0A 15 0D 28 12 1C 28 1D 11 0E 1B 0E | New English Hex + +--------------- +Gort - Castle: +--------------- +Guards: +わたしたちで 王様をお守りしなくては+++ +Not have to observe the king with we +$4497F +94 08 12 13 14 54 38 34 38 39 64 28 EB 2D 55 2D DB 50 34 3D 30 3B 42 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH わ た し た ち で 王 様 を お 守 り し な く て は + + + | Original Japanese Text +LENGTH W E R E P R O T E C T I N G T H E K I N G . | New English Text +18 20 0E 1B 0E 28 19 1B 18 1D 0E 0C 1D 12 17 10 28 1D 11 0E 28 14 12 17 10 C3 | New English Hex + +King Guards: +このえへい「王様に なにか ごようですか?」 +Guards "Do you need something to our king?" +$449AC +F5 32 0C 41 0C 2C 0C 45 0C 2A 0C C1 00 EB 00 2D 01 3E 00 28 00 3D 00 3E 00 2E 00 28 00 5B 00 4E 00 2B 00 64 00 35 00 2E 00 24 00 C2 00 | Original Japanese Hex +LENGTH こRED のRED えRED へRED いRED 「BLACK 王BLACK 様BLACK にBLACK BLACK なBLACK にBLACK かBLACK BLACK ごBLACK よBLACK うBLACK でBLACK すBLACK かBLACK ?BLACK 」BLACK | Original Japanese Text +LENGTH GRED URED ARED RRED DRED SRED :RED BLACK NBLACK EBLACK EBLACK DBLACK BLACK TBLACK HBLACK EBLACK BLACK KBLACK IBLACK NBLACK GBLACK ?BLACK | New English Text +F5 10 0C 1E 0C 0A 0C 1B 0C 0D 0C 1C 0C D6 0C 28 00 17 00 0E 00 0E 00 0D 00 28 00 1D 00 11 00 0E 00 28 00 14 00 12 00 17 00 10 00 24 00 | New English Hex + +OK Selected: +ごぶれいのない様 おはなしください +Please tell as there is no Goburei +$44999 +30 07 5B 68 52 2A 41 3D 2A 2D 28 2D 42 3D 34 30 61 33 2A | Original Japanese Hex +LENGTH LENGTH ご ぶ れ い の な い 様 お は な し く だ さ い | Original Japanese Text +LENGTH S P E A K T O T H E K I N G . | New English Text +11 1C 19 0E 0A 14 28 1D 18 28 1D 11 0E 28 14 12 17 10 C3 | New English Hex + +No Selected: +ならば わたくし 王様を守る者として ここを とおすわけには まいりません! +If it does not visit To not pass here as those who protect the private affairs king! +$449D9 (Line 1) +31 0A 3D 4F 66 28 54 38 30 34 28 EB 2D 55 DB 51 E7 3C 34 3B | Original Japanese Hex +LENGTH LENGTH な ら ば わ た く し 王 様 を 守 る 者 と し て | Original Japanese Text +LENGTH D O N T N E E D T O V I S I T , | New English Text +12 0D 18 17 1D 28 17 0E 0E 0D 28 1D 18 28 1F 12 1C 12 1D C4 | New English Hex +????????? +$449ED (Line 2) +12 32 32 55 28 3C 2D 35 54 31 3E 42 28 47 2A 50 47 36 56 25 | Original Japanese Hex +LENGTH こ こ を と お す わ け に は ま い り ま せ ん ! | Original Japanese Text +LENGTH Y O U R E W A S T I N G T I M E ! | New English Text +12 22 18 1E 1B 0E 28 20 0A 1C 1D 12 17 10 28 1D 12 16 0E 25 | New English Hex + +Queen: +ゴート王も さいきんでは くろうばかり すっかり体の方も よわってしまって+++ +Gort King even if I weakened even better body completely just struggling in recent years +++ +$4216D (Line 1) +12 A7 F7 88 EB 4B 28 33 2A 2F 56 64 42 28 30 53 2B 66 2E 50 | Original Japanese Hex +LENGTH ゴ ー ト 王 も さ い き ん で は く ろ う ば か り | Original Japanese Text +LENGTH K I N G S S T R O N G E R T H A N | New English Text +12 14 12 17 10 1C 28 1C 1D 1B 18 17 10 0E 1B 28 1D 11 0A 17 | New English Hex +$42181 (Line 2) +93 04 11 12 13 35 71 2E 50 45 41 FD 4B 28 4E 54 71 3B 34 47 71 3B 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH す っ か り 体 の 方 も よ わ っ て し ま っ て + + + | Original Japanese Text +LENGTH E V E R T O R E S O L V E P R O B L E M S | New English Text +17 0E 1F 0E 1B 28 1D 18 28 1B 0E 1C 18 15 1F 0E 28 19 1B 18 0B 15 0E 16 1C | New English Hex + +King: +そうか やはりオズワルドが 蘇ったのか よく しらせてくれた +It made ​​me well-known Oswald Did revived still so? +$4219A (Line 1) +32 0E 37 2B 2E 28 4C 42 50 79 AA A0 9D B1 57 28 50 71 38 41 2E | Original Japanese Hex +LENGTH LENGTH そ う か や は り オ ズ ワ ル ド が 蘇 っ た の か | Original Japanese Text +LENGTH I V E B E E N T O L D O S W A L D | New English Text +13 12 1F 0E 28 0B 0E 0E 17 28 1D 18 15 0D 28 18 1D 20 0A 15 0D | New English Hex +$421AF (Line 2) +09 4E 30 28 34 4F 36 3B 30 52 38 | Original Japanese Hex +LENGTH よ く し ら せ て く れ た | Original Japanese Text +LENGTH I S R E V I V E D | New English Text +09 12 1C 28 1B 0E 1F 12 1F 0E 0D | New English Hex + +だが わしには うつ手が のこされてないんじゃ +Depression hand is not you not left the Dagawashi +$421BA +36 0A 61 57 28 54 34 3E 42 28 2B 3A 40 57 28 41 32 33 52 3B 3D 2A 56 5D 72 | Original Japanese Hex +LENGTH LENGTH だ が わ し に は う つ 手 が の こ さ れ て な い ん じ ゃ | Original Japanese Text +LENGTH H I S E V I L G R I P I S T I G H T E R | New English Text +17 11 12 1C 28 0E 1F 12 15 28 10 1B 12 19 28 12 1C 28 1D 12 10 11 1D 0E 1B | New English Hex + +わしのないちがいかも しれんが+++ そなた+++ +That Way + + + I was in the middle of the field as usual + + + but I was a sitting duck, it was an ordeal +$421D3 +F8 54 00 34 00 41 00 3D 00 2A 00 39 00 57 00 2A 00 2E 00 4B 00 28 00 34 00 52 00 56 00 57 00 18 01 18 01 18 01 28 00 37 00 3D 00 38 00 18 01 18 01 18 01 | Original Japanese Hex +LENGTH わBLACK しBLACK のBLACK なBLACK いBLACK ちBLACK がBLACK いBLACK かBLACK もBLACK BLACK しBLACK れBLACK んBLACK がBLACK +BLACK +BLACK +BLACK BLACK そBLACK なBLACK たBLACK +BLACK +BLACK +BLACK | Original Japanese Text +LENGTH W E A R E S I T T I N G D U C K S H E R E . .BLACK がBLACK +BLACK +BLACK +BLACK BLACK そBLACK なBLACK たBLACK +BLACK +BLACK +BLACK | New English Text +1A 20 0E 28 0A 1B 0E 28 1C 12 1D 1D 12 17 10 28 0D 1E 0C 14 1C 28 11 0E 1B 0E C3 C3 00 57 00 18 01 18 01 18 01 28 00 37 00 3D 00 38 00 18 01 18 01 18 01 | New English Hex + +このせかいを へいわに導こうとしてるんじゃないのか? +Is it not you are going to lead to peace this world? +$42206 +19 32 41 36 2E 2A 55 28 45 2A 54 3E E5 32 2B 3C 34 3B 51 56 5D 72 3D 2A 41 2E 24 | Original Japanese Hex +LENGTH こ の せ か い を へ い わ に 導 こ う と し て る ん じ ゃ な い の か ? | Original Japanese Text +LENGTH A R E Y O U T O B R I N G U S P E A C E ? | New English Text +19 0A 1B 0E 28 22 18 1E 28 1D 18 28 0B 1B 12 17 10 28 1E 1C 28 19 0E 0A 0C 0E 24 | New English Hex + +No Selected: +すまん かんちがいじゃ だれだって命はおしいからな +Everyone life because I'm regrettable misunderstanding sorry +$42221 +38 11 35 47 56 28 2E 56 39 57 2A 5D 72 28 61 52 61 71 3B 1D 42 2D 34 2A 2E 4F 3D | Original Japanese Hex +LENGTH LENGTH す ま ん か ん ち が い じ ゃ だ れ だ っ て 命 は お し い か ら な | Original Japanese Text +LENGTH S O R R Y I M I S U N D E R S T O O D Y O U . | New English Text +19 1C 18 1B 1B 22 28 12 28 16 12 1C 1E 17 0D 0E 1B 1C 1D 18 18 0D 28 22 18 1E C3 | New English Hex + +OK Selected: +おお!なんというゆうき ならば スレイにあうといい ゴートの騎士団長だ +It is a good knight head of the gort when meet the sleigh if What a courage! Oh +$4223C (Line 1) +0A 2D 2D 25 3D 56 3C 2A 2B 4D 2B 2F | Original Japanese Hex +LENGTH お お ! な ん と い う ゆ う き | Original Japanese Text +LENGTH O H C O U R A G E ! | New English Text +0A 18 11 28 0C 18 1E 1B 0A 10 0E 25 | New English Hex +$42248 (Line 2) +36 13 3D 4F 66 28 81 9E 76 3E 29 2B 3C 2A 2A 28 A7 F7 88 41 D0 20 D1 D2 61 | Original Japanese Hex +LENGTH LENGTH な ら ば ス レ イ に あ う と い い ゴ ー ト の 騎 士 団 長 だ | Original Japanese Text +LENGTH Y O U M U S T M E E T W I T H S L A Y . | New English Text +17 22 18 1E 28 16 1E 1C 1D 28 16 0E 0E 1D 28 20 12 1D 11 28 1C 15 0A 22 C3 | New English Hex + +かれも またオズワルドに命をねらわれておる +I Nikki Neraware life to Oswald he also +$42261 +34 0C 2E 52 4B 28 47 38 79 AA A0 9D B1 3E 1D 55 40 4F 54 52 3B 2D 51 | Original Japanese Hex +LENGTH LENGTH か れ も ま た オ ズ ワ ル ド に 命 を ね ら わ れ て お る | Original Japanese Text +LENGTH H E A L S O F O U G H T O S W A L D . | New English Text +15 11 0E 28 0A 15 1C 18 28 0F 18 1E 10 11 1D 28 18 1C 20 0A 15 0D C3 | New English Hex + +そなたを しんようせんわけじゃないのだが+++ +Although he does not mean you do not trust your company + + + +$42278 +76 14 15 16 37 3D 38 55 28 34 56 4E 2B 36 56 54 31 5D 72 3D 2A 41 61 57 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH そ な た を し ん よ う せ ん わ け じ ゃ な い の だ が + + + | Original Japanese Text +LENGTH Y O U N E E D T O G A I N H I S T R U S T | New English Text +17 22 18 1E 28 17 0E 0E 0D 28 1D 18 28 10 0A 12 17 28 11 12 1C 28 1D 1B 1E 1C 1D | New English Hex + +そうじゃ ゴーレムの頭を特ってまいれ すれば スレイのいばしょを おしえてやろう +I'll tell me the whereabouts of Slay if Maile I solve the head of the Golem 's so +$42293 (Line 1) +51 0A 0C 37 2B 5D 72 28 A7 F7 9E 95 41 43 55 32 71 3B 47 2A 52 | Original Japanese Hex +LENGTH LENGTH LENGTH そ う じ ゃ ゴ ー レ ム の 頭 を 特 っ て ま い れ | Original Japanese Text +LENGTH H E W I L L H E L P , I F Y O U | New English Text +13 11 0E 28 20 12 15 15 28 11 0E 15 19 C4 28 12 0F 28 22 18 1E | New English Hex +$422A8 (Line 2) +14 35 52 66 28 81 9E 76 41 2A 66 34 74 55 28 2D 34 2C 3B 4C 53 2B | Original Japanese Hex +LENGTH す れ ば ス レ イ の い ば し ょ を お し え て や ろ う | Original Japanese Text +LENGTH B R I N G M E G O L E M S H E A D . | New English Text +14 0B 1B 12 17 10 28 16 0E 28 10 18 15 0E 16 1C 28 11 0E 0A 0D C3 | New English Hex + +それに おまえはゴーレムの頭も特っておるし+++ +And to dwell especially I also head of the golem you, + + + +$422BE +B7 0D 0F 15 16 17 37 52 3E 28 2D 47 2C 42 A7 F7 9E 95 41 43 4B 32 71 3B 2D 51 34 18 18 18 | Original Japanese Hex +LENGTH LENGTH LENGTH LENGTH LENGTH LENGTH そ れ に お ま え は ゴ ー レ ム の 頭 も 特 っ て お る し + + + | Original Japanese Text +LENGTH I A L S O N E E D T H E G O L E M H E A D . + + | New English Text +1A 12 28 0A 15 1C 18 28 17 0E 0E 0D 28 1D 11 0E 28 10 18 15 0E 16 28 11 0E 0A 0D C3 18 18 | New English Hex + +そなたなら しんようできる +I trust you can accomplish this +$422DC +0C 37 3D 38 3D 4F 28 34 56 4E 2B 64 2F 51 | Original Japanese Hex +LENGTH そ な た な ら し ん よ う で き る | Original Japanese Text +LENGTH M A Y I H A V E I T | New English Text +0C 16 0A 22 28 12 28 11 0A 1F 0E 28 12 1D | New English Hex + +その頭とひきかえに このてがみを特っていかれよ +The Ikareyo Te Toku~tsu this letter in exchange for his head +$422EA +56 02 10 37 41 43 3C 43 2F 2E 2C 3E 28 32 41 3B 57 48 55 32 71 3B 2A 2E 52 4E | Original Japanese Hex +LENGTH LENGTH LENGTH そ の 頭 と ひ き か え に こ の て が み を 特 っ て い か れ よ | Original Japanese Text +LENGTH E X C H A N G E L E T T E R F O R H E A D ? | New English Text +18 0E 21 0C 11 0A 17 10 0E 28 15 0E 1D 1D 0E 1B 28 0F 18 1B 28 11 0E 0A 0D 24 | New English Hex + +OK Selected: +スレイは ゴート騎士団に ふさわしい者が ノイラートにおるときいて たびだっていったんじゃ +Slay not you went traveled to hear that dwell in Neurath is a person who is worthy of goat Knights +$42304 (Line 1) +33 09 81 9E 76 42 28 A7 F7 88 D0 20 D1 3E 28 44 33 54 34 2A E7 57 | Original Japanese Hex +LENGTH LENGTH ス レ イ は ゴ ー ト 騎 士 団 に ふ さ わ し い 者 が | Original Japanese Text +LENGTH S L A Y L I V E S I N N E U R A T H | New English Text +14 1C 15 0A 22 28 15 12 1F 0E 1C 28 12 17 28 17 0E 1E 1B 0A 1D 11 | New English Hex +$4231A (Line 2) +17 8D 76 9B F7 88 3E 2D 51 3C 2F 2A 3B 28 38 67 61 71 3B 2A 71 38 56 5D 72 | Original Japanese Hex +LENGTH ノ イ ラ ー ト に お る と き い て た び だ っ て い っ た ん じ ゃ | Original Japanese Text +LENGTH H E S A G R E A T G O R T K N I G H T . | New English Text +17 11 0E 1C 28 0A 28 10 1B 0E 0A 1D 28 10 18 1B 1D 28 14 17 12 10 11 1D C3 | New English Hex + +さぁ早く このてがみを特って スレイをおうのじゃ きっと そなたの力になるであろう +It will be the force of the sonata I'm sure 'll king slay Te Toku~tsu this letter soon Now +$42333 (Line 1) +37 0B 33 70 CA 30 28 32 41 3B 57 48 55 32 71 3B 28 81 9E 76 55 2D 2B 41 5D 72 | Original Japanese Hex +LENGTH LENGTH さ ぁ 早 く こ の て が み を 特 っ て ス レ イ を お う の じ ゃ | Original Japanese Text +LENGTH Y O U S H O U L D G E T T H E L E T T E R | New English Text +18 22 18 1E 28 1C 11 18 1E 15 0D 28 10 0E 1D 28 1D 11 0E 28 15 0E 1D 1D 0E 1B | New English Hex +$4234D (Line 2) +0F 2F 71 3C 28 37 3D 38 41 CF 3E 3D 51 64 29 53 2B | Original Japanese Hex +LENGTH き っ と そ な た の 力 に な る で あ ろ う | Original Japanese Text +LENGTH T O S L A Y Q U I C K L Y . | New English Text +0F 1D 18 28 1C 15 0A 22 28 1A 1E 12 0C 14 15 22 c3 | New English Hex + +No Selected: +そうか しかたない +There is no way that so? +$44A0E +08 37 2B 2E 28 34 2E 38 3D 2A | Original Japanese Hex +LENGTH そ う か し か た な い | Original Japanese Text +LENGTH S O B E I T . | New English Text +08 1C 18 28 0B 0E 28 12 1D C3 | New English Hex + +よく戻ってきたな だが わしには なにもしてやれることがない すまんのう +I'm sorry that they do not do better with anything to Dagawashi Na came back well +$44A18 (Line 1) +27 02 4E 30 1A 71 3B 2F 38 3D | Original Japanese Hex +LENGTH LENGTH よ く 戻 っ て き た な | Original Japanese Text +LENGTH T H A T S A L L | New English Text +08 1D 11 0A 1D 1C 28 0A 15 15 | New English Hex +$44A22 (Line 2) +1A 61 57 28 54 34 3E 42 28 3D 3E 4B 34 3B 4C 52 51 32 3C 57 3D 2A 28 35 47 56 41 2B | Original Japanese Hex +LENGTH だ が わ し に は な に も し て や れ る こ と が な い す ま ん の う | Original Japanese Text +LENGTH I H O P E T H A T Y O U R E T U R N S A F E | New English Text +1A 12 28 11 18 19 0E 28 1D 11 0A 1D 28 22 18 1E 28 1B 0E 1D 1E 1B 17 28 1C 0A 0F 0E | New English Hex + +おまえの かつやくを きたいしておるからな! +I from Nikki expect success of you! +$44A3E +15 2D 47 2C 41 28 2E 3A 4C 30 55 28 2F 38 2A 34 3B 2D 51 2E 4F 3D 25 | Original Japanese Hex +LENGTH お ま え の か つ や く を き た い し て お る か ら な ! | Original Japanese Text +LENGTH E X P E C T Y O U T O S U C C E E D ! | New English Text +15 0E 21 19 0E 0C 1D 28 22 18 1E 28 1D 18 28 1C 1E 0C 0C 0E 0E 0D 25 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 03 - Neurath.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 03 - Neurath.txt new file mode 100644 index 00000000..ff645785 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/NPCS - 03 - Neurath.txt @@ -0,0 +1,117 @@ +-------------- +Neurath Town: +-------------- +------------------- +Neurath - Outside: +------------------- +Girl - Bottom Left: +ほうろうの大賢者 フィロを しってる? +Do you know a large sage Philo of wandering? +$45E68 (Line 1) +52 05 0A 46 2B 53 2B 41 02 E6 E7 28 90 5C 9F 55 28 34 71 3B 51 24 | Original Japanese Hex +LENGTH LENGTH LENGTH ほ う ろ う の 大 賢 者 フ ィ ロ を し っ て る ? | Original Japanese Text +LENGTH K N O W A B O U T S A G E F I L O ? | New English Text +14 14 17 18 20 28 0A 0B 18 1E 1D 28 1C 0A 10 0E 28 0F 12 15 18 24 | New English Hex + +No Selected: +ごめんなさい。わたしも しらないの +I am sorry. I am also not a known +$45E7E +10 5B 4A 56 3D 33 2A C3 54 38 34 4B 28 34 4F 3D 2A 41 | Original Japanese Hex +LENGTH ご め ん な さ い 。 わ た し も し ら な い の | Original Japanese Text +LENGTH I A L S O D O N T K N O W . | New English Text +10 12 28 0A 15 1C 18 28 0D 18 17 1D 28 14 17 18 20 C3 | New English Hex + +OK Selected: +すごいわ。かれとは めったに あえないのよ +Is amazing. Not a rarely met with him +$45E90 +14 35 5B 2A 54 C3 2E 52 3C 42 28 4A 71 38 3E 28 29 2C 3D 2A 41 4E | Original Japanese Hex +LENGTH す ご い わ 。 か れ と は め っ た に あ え な い の よ | Original Japanese Text +LENGTH V E R Y R A R E T O M E E T H I M | New English Text +14 1F 0E 1B 22 28 1B 0A 1B 0E 28 1D 18 28 16 0E 0E 1D 28 11 12 16 | New English Hex + +----------------------------- +Neurath - Bottom Left House: +----------------------------- +Old Man: +ミケアナには もう 行かれたか? +Were you going anymore Mikeana? +$45768 +0F 94 7D 75 89 3E 42 28 4B 2B 28 F2 2E 52 38 2E 24 | Original Japanese Hex +LENGTH ミ ケ ア ナ に は も う 行 か れ た か ? | Original Japanese Text +LENGTH G O I N G T O M I K E A N A | New English Text +0F 10 18 12 17 10 28 1D 18 28 16 12 14 0E 0A 17 0A | New English Hex + +No Selected: +ゴートから南東に向かえば いいんじゃよ +The Ja should I celebrating southeast of Gort +$45779 +12 A7 F7 88 2E 4F FB F9 3E FE 2E 2C 66 28 2A 2A 56 5D 72 4E | Original Japanese Hex +LENGTH ゴ ー ト か ら 南 東 に 向 か え ば い い ん じ ゃ よ | Original Japanese Text +LENGTH S O U T H E A S T F R O M G O R T | New English Text +12 1C 18 1E 1D 11 0E 0A 1C 1D 28 0F 1B 18 16 28 10 18 1B 1D | New English Hex + +OK Selected: +そうか。コートロードへ行くのに あそこを とおるからな +That's good. I from passing through over there to go to Court Road +$46ABD +1A 37 2B 2E C3 7E F7 88 9F F7 B1 45 F2 30 41 3E 28 29 37 32 55 28 3C 2D 51 2E 4F 3D | Original Japanese Hex +LENGTH そ う か 。 コ ー ト ロ ー ド へ 行 く の に あ そ こ を と お る か ら な | Original Japanese Text +LENGTH P A S S I T T O R E A C H C O U R T R O A D | New English Text +1A 19 0A 1C 1C 28 12 1D 28 1D 18 28 1B 0E 0A 0C 11 28 0C 18 1E 1B 1D 28 1B 18 0A 0D | New English Hex + +Man: +あの ばーちゃんたちと はなすのかい? +Do you speak with Anoba and her friends? +$44AC5 +12 29 41 28 66 F7 39 72 56 38 39 3C 28 42 3D 35 41 2E 2A 24 | Original Japanese Hex +LENGTH あ の ば ー ち ゃ ん た ち と は な す の か い ? | Original Japanese Text +LENGTH C O N V E R S E W I T H A N O B A | New English Text +12 0C 18 17 1F 0E 1B 1C 0E 28 20 12 1D 11 28 0A 17 18 0B 0A | New English Hex + +OK Selected: +なんかへん なんだよなー。あのばーちゃんたち +I'm behaving badly. Anoba and her friends +$44AD9 +15 3D 56 2E 45 56 28 3D 56 61 4E 3D F7 C3 29 41 66 F7 39 72 56 38 39 | Original Japanese Hex +LENGTH な ん か へ ん な ん だ よ な ー 。 あ の ば ー ち ゃ ん た ち | Original Japanese Text +LENGTH P L E A S E B E H A V E P O L I T E L Y | New English Text +15 19 15 0E 0A 1C 0E 28 0B 0E 11 0A 1F 0E 28 19 18 15 12 1D 0E 15 22 | New English Hex + +No Selected: +ふー-ん +Hmm +$44AF0 +03 44 F7 26 56 | Original Japanese Hex +LENGTH ふ ー - ん | Original Japanese Text +LENGTH H M M M | New English Text +03 11 16 16 16 | New English Hex + +Anoba: +「水晶」のありか なんて しらないよ! +I do not know What or there "crystal"! +$44AF5 +12 C1 DD DE C2 41 29 50 2E 28 3D 56 3B 28 34 4F 3D 2A 4E 25 | Original Japanese Hex +LENGTH 「 水 晶 」 の あ り か な ん て し ら な い よ ! | Original Japanese Text +LENGTH W H E R E S T H E C R Y S T A L ! | New English Text +12 20 11 0E 1B 0E 1C 28 1D 11 0E 28 0C 1B 22 1C 1D 0A 15 25 | New English Hex + +--------------------------- +Neurath - Top Right House: +--------------------------- +Knight: +????????? +???????????????????????????? +$????? +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? | Original Japanese Hex +? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | Original Japanese Text +? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? | New English Text +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? | New English Hex + + + + + + + diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Priest.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Priest.txt new file mode 100644 index 00000000..44e15c19 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Priest.txt @@ -0,0 +1,58 @@ +------------------- +Chiberus - Priest: +------------------- +そなたらの 力になれることはないかのう? +Thou and followers to get Help thing well won't you take gift? +$44378 +13 37 3D 38 4F 41 28 CF 3E 3D 52 51 32 3C 42 3D 2A 2E 41 2B 24 | Original Japanese Hex +LENGTH そ な た ら の 力 に な れ る こ と は な い か の う ? | Original Japanese Text +LENGTH H O W M A Y I S E R V E Y O U ? | New English Text +13 11 18 20 28 16 0A 22 28 12 28 1C 0E 1B 1F 0E 28 22 18 1E 24 | New English Hex + +いのって ほしい +I want to pray +$4446D +08 28 2A 41 71 3B 28 46 34 2A | Original Japanese Hex +LENGTH い の っ て ほ し い | Original Japanese Text +LENGTH H E A L A L L | New English Text +08 28 11 0E 0A 15 28 0A 15 15 | New English Hex + + そなたの たびが ぶじで ありますように+++ + Thou and followers wanderer Peace so existence take care+++ + $47F21 + 76 14 15 16 37 3D 38 41 28 38 67 57 28 68 5D 64 28 29 50 47 35 4E 2B 3E 18 18 18 | Original Japanese Hex + LENGTH LENGTH LENGTH LENGTH そ な た の た び が ぶ じ で あ り ま す よ う に + + + | Original Japanese Text + LENGTH M A Y Y O U E A C H B E H E A L E D . . . + | New English Text + 18 16 0A 22 28 22 18 1E 28 0E 0A 0C 11 28 0B 0E 28 11 0E 0A 15 0E 0D C3 C3 C3 18 | New English Hex + + くじけず がんばるんだぞ + Undaunted I'll do my best + $4438D + 0B 30 5D 31 5E 28 57 56 66 51 56 61 60 | Original Japanese Hex + LENGTH く じ け ず が ん ば る ん だ ぞ | Original Japanese Text + LENGTH I D O M Y B E S T | New English Text + 0B 12 28 0D 18 28 16 22 28 0B 0E 1C 1D | New English Hex + +しにん を いきかえら して ほしい +I want you to come and revive the dead +$44477 +10 28 34 3E 56 55 28 2A 2F 2E 2C 4F 34 3B 28 46 34 2A | Original Japanese Hex +LENGTH し に ん を い き か え ら し て ほ し い | Original Japanese Text +LENGTH R E V I V E A L L P A R T Y | New English Text +10 28 1B 0E 1F 12 1F 0E 28 0A 15 15 28 19 0A 1B 1D 22 | New English Hex + + きふ 金 $300 おねがいします + $300 donation, please + $47AAC + 0F 2F 44 D3 28 F6 03 00 00 28 2D 40 57 2A 34 47 35 | Original Japanese Hex + LENGTH き ふ 金 $ 3 0 0 お ね が い し ま す | Original Japanese Text + LENGTH G I V E $ 3 0 0 P L E A S E | New English Text + 0F 10 12 1F 0E 28 F6 03 00 00 28 19 15 0E 0A 1C 0E | New English Hex + + おや っ だれも しんどらんようだが+++ + Oh? Nobody seems to be dead+++ + $44489 + 73 11 12 13 2D 4C 71 28 61 52 4B 28 34 56 65 4F 56 4E 2B 61 57 18 18 18 | Original Japanese Hex + LENGTH LENGTH LENGTH LENGTH お や っ だ れ も し ん ど ら ん よ う だ が + + + | Original Japanese Text + LENGTH N O B O D Y S E E M S T O B E D E A D | New English Text + 16 17 18 0B 18 0D 22 28 1C 0E 0E 16 1C 28 1D 18 28 0B 0E 28 0D 0E 0A 0D | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Shops.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Shops.txt new file mode 100644 index 00000000..3332ebf5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Shops.txt @@ -0,0 +1,293 @@ +---------- +Chiberus: +---------- +---------------------- +Chiberus - Item Shop: +---------------------- +ここは どうぐやです。どんな ごようでしょうか? +This is an item shop. How can I help you? +$4375A (Line 1) +17 32 32 42 28 65 2B 59 4C 64 35 C3 65 56 3D 28 5B 4E 2B 64 34 74 2B 2E 24 | Original Japanese Hex +LENGTH こ こ は ど う ぐ や で す 。 ど ん な ご よ う で し ょ う か ? | Original Japanese Text +LENGTH I T E M S H O P . H O W C A N I H E L P | New English Text +17 12 1D 0E 16 28 1C 11 18 19 C3 11 18 20 28 0C 0A 17 28 12 28 11 0E 15 19 | New English Hex + + かいにきた + I came to buy + $43773 (Line 2) + 05 28 2E 2A 3E 2F 38 | Original Japanese Hex + LENGTH か い に き た | Original Japanese Text + LENGTH B U Y き た | New English Text + 03 28 0B 1E 22 2F 38 | New English Hex + + うりにきた + I came to sell + $4377A (Line 3) + 05 28 2B 50 3E 2F 38 | Original Japanese Hex + LENGTH う り に き た | Original Japanese Text + LENGTH S E L L た | New English Text + 04 28 1C 0E 15 15 38 | New English Hex + +Buy Selected: +おきゃくさん。 サービスさせてもらうわね なにを かってくださるのかしら? +I will get you a discount. What can I get you? +$437D9 (Line 1) +12 2D 2F 72 30 33 56 C3 7F F7 B3 81 33 36 3B 4B 4F 2B 54 40 | Original Japanese Hex +LENGTH お き ゃ く さ ん 。 サ ー ビ ス さ せ て も ら う わ ね | Original Japanese Text +LENGTH W H A T W O U L D Y O U L I K E | New English Text +12 20 11 0A 1D 28 20 18 1E 15 0D 28 22 18 1E 28 15 12 14 0E | New English Hex +$437FF (Line 2) +0F 3D 3E 55 28 2E 71 3B 30 61 33 51 41 2E 34 4F 24 | Original Japanese Hex +LENGTH な に を か っ て く だ さ る の か し ら ? | Original Japanese Text +LENGTH T O P U R C H A S E N O W ? | New English Text +0F 1D 18 28 19 1E 1B 0C 11 0A 1C 0E 28 17 18 20 24 | New English Hex + +Sell Selected: +おたかく かいとりますわ さぁ しなものを みせてちょうだい +Come in and show me a thing Now +$437CC (Line 1) +0B 2D 38 2E 30 28 2E 2A 3C 50 47 35 54 | Original Japanese Hex +LENGTH お た か く か い と り ま す わ | Original Japanese Text +LENGTH L E T S L O O K A T | New English Text +0B 15 0E 1D 1C 28 15 18 18 14 28 0A 1D | New English Hex +$437ED (Line 2) +10 33 70 28 34 3D 4B 41 55 28 48 36 3B 39 74 2B 61 2A | Original Japanese Hex +LENGTH さ ぁ し な も の を み せ て ち ょ う だ い | Original Japanese Text +LENGTH Y O U R I T E M S V A L U E S | New English Text +10 22 18 1E 1B 28 12 1D 0E 16 1C 28 1F 0A 15 1E 0E 1C | New English Hex + +またの おこしを おまちしてます +I look forward to welcoming you again +$4387C +0F 47 38 41 28 2D 32 34 55 28 2D 47 39 34 3B 47 35 | Original Japanese Hex +LENGTH ま た の お こ し を お ま ち し て ま す | Original Japanese Text +LENGTH C O M E A G A I N S O O N . | New English Text +0F 0C 18 16 0E 28 0A 10 0A 12 17 28 1C 18 18 17 C3 | New English Hex + +--------------------- +Chiberus - Egg Shop: +--------------------- +おーちゃん「ここのタマゴは おいしいですわよ」 +Hay Girl: I'm here, eggs are delicious +$41ED3 (Line 1) +F6 2D 0C F7 0C 39 0C 72 0C 56 0C C1 00 32 00 32 00 41 00 84 00 93 00 A7 00 42 00 28 00 2D 00 2A 00 34 00 2A 00 64 00 35 00 54 00 4E 00 C2 00 | Original Japanese Hex +LENGTH おRED ーRED ちRED ゃRED んRED 「BLACK こBLACK こBLACK のBLACK タBLACK マBLACK ゴBLACK はBLACK BLACK おBLACK いBLACK しBLACK いBLACK でBLACK すBLACK わBLACK よBLACK 」BLACK | Original Japanese Text +LENGTH HRED ARED YRED RED GRED IRED RRED LRED :RED HBLACK EBLACK RBLACK EBLACK BLACK IBLACK SBLACK BLACK ABLACK NBLACK BLACK EBLACK GBLACK GBLACK | New English Text +F6 11 0C 0A 0C 22 0C 28 0C 10 0C 12 0C 1B 0C 15 0C D6 0C 11 00 0E 00 1B 00 0E 00 28 00 12 00 1C 00 28 00 0A 00 17 00 28 00 0E 00 10 00 10 00 | New English Hex + + かう + To buy + $41F02 (Line 2) + 02 28 2E 2B | Original Japanese Hex + LENGTH か う | Original Japanese Text + LENGTH O K | New English Text + 02 28 18 14 | New English Hex + + いらない + I do not need + $41F06 (Line 3) + 04 28 2A 4F 3D 2A | Original Japanese Hex + LENGTH い ら な い | Original Japanese Text + LENGTH N O な い | New English Text + 02 28 17 18 3D 2A | New English Hex + +OK Selected: +うれしいですわ。 おほほほほ +I'm happy. Ho ho ho ho +$41F0C +0C 2B 52 34 2A 64 35 54 C3 2D 46 46 46 46 | Original Japanese Hex +LENGTH う れ し い で す わ 。 お ほ ほ ほ ほ | Original Japanese Text +LENGTH I M G L A D , H O H O | New English Text +0C 12 16 28 10 15 0A 0D C4 11 18 28 11 18 | New English Hex + +No Selected: +ざんねんですわ おいしいタマゴなのに また いらしてくださいですわ +Please come Though I also delicious eggs I'm sorry +$4201C (Line 1) +11 5C 56 40 56 64 35 54 28 2D 2A 34 2A 84 93 A7 3D 41 3E | Original Japanese Hex +LENGTH ざ ん ね ん で す わ お い し い タ マ ゴ な の に | Original Japanese Text +LENGTH M Y E G G S A R E R E A L L Y | New English Text +11 16 22 28 0E 10 10 1C 28 0A 1B 0E 28 1B 0E 0A 15 15 22 | New English Hex +$44527 (Line 2) +0D 47 38 28 2A 4F 34 3B 30 61 33 2A 64 35 54 | Original Japanese Hex +LENGTH ま た い ら し て く だ さ い で す わ | Original Japanese Text +LENGTH V E R Y D E L I C I O U S | New English Text +0D 1F 0E 1B 22 28 0D 0E 15 12 0C 12 18 1E 1C | New English Hex + +-------------- +Gort - Forge: +-------------- +Blacksmith: +なんだ!オレに なんかようか? +The softening in melting! Me What? +$43817 (Line 1) +0E 3D 56 61 25 79 9E 3E 28 3D 56 2E 4E 2B 2E 24 | Original Japanese Hex +LENGTH な ん だ ! オ レ に な ん か よ う か ? | Original Japanese Text +LENGTH H I ! I W O R K M E T A L | New English Text +0E 11 12 25 12 28 20 18 1B 14 28 16 0E 1D 0A 15 | New English Hex + + 武器を かいにきた + I came to buy the weapon + $43827 (Line 2) + 09 28 C5 C6 55 28 2E 2A 3E 2F 38 | Original Japanese Hex + LENGTH 武 器 を か い に き た | Original Japanese Text + LENGTH B U Y G O O D S | New English Text + 09 28 0B 1E 22 28 10 18 18 0D 1C | New English Hex + + ただ よんでみた + I just tried calling + $43832 (Line 3) + 08 28 38 61 28 4E 56 64 48 38 | Original Japanese Hex + LENGTH た だ よ ん で み た | Original Japanese Text + LENGTH N O T R A D E | New English Text + 08 28 17 18 28 1D 1B 0A 0D 0E | New English Hex + +Buy Goods Selected: +どれも いっきゅうひんだぜっ じっくり選んでいきなっ +It became Ki have chosen carefully Ikkyu Hindaze~tsu any +$4383C (Line 1) +0D 65 52 4B 28 2A 71 2F 73 2B 43 56 61 5F 71 | Original Japanese Hex +LENGTH ど れ も い っ き ゅ う ひ ん だ ぜ っ | Original Japanese Text +LENGTH T A K E Y O U R T I M E | New English Text +0D 1D 0A 14 0E 28 22 18 1E 1B 28 1D 12 16 0E | New English Hex +$4384B (Line 2) +2A 04 5D 71 30 50 1C 56 64 2A 2F 3D 71 | Original Japanese Hex +LENGTH LENGTH じ っ く り 選 ん で い き な っ | Original Japanese Text +LENGTH S E E M Y G O O D S | New English Text +0B 1D 0E 0E 28 16 22 28 10 18 18 0D 1C | New English Hex + +No Trade Selected: +てめぇ! ようもねぇのに よぶんじゃねぇ +Hey! Is not it call to not be imported goods +$438C1 (Line 1) +23 02 3B 4A 5D 25 | Original Japanese Hex +LENGTH LENGTH て め ぇ ! | Original Japanese Text +LENGTH W H A T ! | New English Text +04 20 11 0A 1D 25 | New English Hex +$43858 (Line 2) +4E 04 0E 4E 2B 4B 40 5D 41 3E 28 4E 68 56 5D 72 40 5D | Original Japanese Hex +LENGTH LENGTH LENGTH よ う も ね ぇ の に よ ぶ ん じ ゃ ね ぇ | Original Japanese Text +LENGTH I H A V E F I N E G O O D S | New English Text +10 12 28 11 0A 1F 0E 28 0F 12 17 0E 28 10 18 18 0D 1C | New English Hex + +いつでも 持ってるからな +Because I have at any time +$438C7 +2B 05 2A 3A 64 4B 28 3C 71 3B 51 2E 4F 3D | Original Japanese Hex +LENGTH LENGTH い つ で も 持 っ て る か ら な | Original Japanese Text +LENGTH C O M E A N Y T I M E | New English Text +0C 0C 18 16 0E 28 0A 17 22 28 1D 12 16 0E | New English Hex + +----------------------------- +Gort - Shade Shop (Red Cap): +----------------------------- +Shade: +すけざえもん「ゴートの鬼いは いかがでござるか?」 +Sukezaemon "Oni-i of Gort or a bamboo basket How?" +$4482E +F8 35 0C 31 0C 5C 0C 2C 0C 4B 0C 56 0C C1 00 A7 00 F7 00 88 00 41 00 3D 01 2A 00 42 00 28 00 2A 00 2E 00 57 00 64 00 5B 00 5C 00 51 00 2E 00 24 00 C2 00 | Original Japanese Hex +LENGTH すRED けRED ざRED えRED もRED んRED 「BLACK ゴBLACK ーBLACK トBLACK のBLACK 鬼BLACK いBLACK はBLACK BLACK いBLACK かBLACK がBLACK でBLACK ごBLACK ざBLACK るBLACK かBLACK ?BLACK 」BLACK | Original Japanese Text +LENGTH SRED HRED ARED DRED ERED :RED DBLACK OBLACK BLACK YBLACK OBLACK UBLACK BLACK WBLACK ABLACK NBLACK TBLACK BLACK ABLACK BLACK WBLACK ABLACK RBLACK PBLACK ?BLACK | New English Text +F8 1C 0C 11 0C 0A 0C 0D 0C 0E 0C D6 0C 0D 00 18 00 28 00 22 00 18 00 1E 00 28 00 20 00 0A 00 17 00 1D 00 28 00 0A 00 28 00 20 00 0A 00 1B 00 19 00 24 00 | New English Hex + +OK Selected: +きゃくじん さーびすしてしんぜよう +Let Shinzeyo with guests service +$44861 +10 2F 72 30 5D 56 28 33 F7 67 35 34 3B 34 56 5F 4E 2B | Original Japanese Hex +LENGTH き ゃ く じ ん さ ー び す し て し ん ぜ よ う | Original Japanese Text +LENGTH H E R E S W H A T I H A V E | New English Text +10 11 0E 1B 0E 1C 28 20 11 0A 1D 28 12 28 11 0A 1F 0E | New English Hex + +No Selected: +そうでござるか また くるでござる +The bamboo basket comes again or bamboo basket so +$4487D (Line 1) +06 37 2B 64 5B 5C 51 2E | Original Japanese Hex +LENGTH そ う で ご ざ る か | Original Japanese Text +LENGTH Y O U C A N | New English Text +06 22 18 1E 28 0C 0A 17 | New English Hex +$44873 (Line 2) +08 47 38 28 30 51 64 5B 5C 51 | Original Japanese Hex +LENGTH ま た く る で ご ざ る | Original Japanese Text +LENGTH W A R P H E R E | New English Text +08 20 0A 1B 19 28 11 0E 1B 0E | New English Hex + +----------------------------- +Gort - Hebe Shop (Blue Cap): +----------------------------- +Hebereke: +へべ「**でかいくつ かうかぴょー?」 +Hebe "Some strapping boots?" +$447C1 +F2 45 0C 69 0C C1 00 08 01 09 01 64 00 2E 00 2A 00 30 00 3A 00 28 00 2E 00 2B 00 2E 00 6C 00 74 00 F7 00 24 00 C2 00 | Original Japanese Hex +LENGTH へRED べRED 「BLACK *BLACK *BLACK でBLACK かBLACK いBLACK くBLACK つBLACK BLACK かBLACK うBLACK かBLACK ぴBLACK ょBLACK ーBLACK ?BLACK 」BLACK | Original Japanese Text +LENGTH HRED ERED BRED ERED :RED SBLACK EBLACK EBLACK BLACK MBLACK YBLACK BLACK NBLACK IBLACK CBLACK EBLACK *BLACK *BLACK ?BLACK | New English Text +F2 11 0C 0E 0C 0B 0C 0E 0C D6 0C 1C 00 0E 00 0E 00 28 00 16 00 22 00 28 00 17 00 12 00 0C 00 0E 00 08 01 09 01 24 00 | New English Hex + +OK Selected: +らっきーだにょーう。うれなくて こまってたでげしょぱぴ +U Lucky Danyoー. The Papi Gesho in was in trouble, rather than ripe +$447E8 +1A 4F 71 2F F7 61 3E 74 F7 2B C3 2B 52 3D 30 3B 28 32 47 71 3B 38 64 5A 34 74 6B 6C | Original Japanese Hex +LENGTH ら っ き ー だ に ょ ー う 。 う れ な く て こ ま っ て た で げ し ょ ぱ ぴ | Original Japanese Text +LENGTH S E E M Y A M A Z I N G L Y F I N E G O O D S | New English Text +1A 1C 0E 0E 28 16 22 28 0A 16 0A 23 12 17 10 15 22 28 0F 12 17 0E 28 10 18 18 0D 1C | New English Hex + +No Selected: +やっぱり うれないひょろぷー また きてくれだにょーう +The U Nyoー that I come again Hyoro Pooh not sell after all +$44811 (Line 1) +0D 4C 71 6B 50 28 2B 52 3D 2A 43 74 53 6D F7 | Original Japanese Hex +LENGTH や っ ぱ り う れ な い ひ ょ ろ ぷ ー | Original Japanese Text +LENGTH C O M E A G A I N , I F | New English Text +0D 0C 18 16 0E 28 0A 10 0A 12 17 C4 28 12 0F | New English Hex +$44804 (Line 2) +0B 47 38 28 2F 3B 30 52 61 3E 74 F7 2B | Original Japanese Hex +LENGTH ま た き て く れ だ に ょ ー う | Original Japanese Text +LENGTH Y O U W A N T I T . | New English Text +0B 22 18 1E 28 20 0A 17 1D 28 12 1D C3 | New English Hex + +足に はくんじゃないんだひょろぴぷーん +Hyoropipun I do not Hakunja feet +$47F3C +32 00 64 3E 28 42 30 56 5D 72 3D 2A 56 61 43 74 53 6C 6D F7 56 | Original Japanese Hex +LENGTH LENGTH 足 に は く ん じ ゃ な い ん だ ひ ょ ろ ぴ ぷ ー ん | Original Japanese Text +LENGTH I C A N N O T W E A R T H E M . | New English Text +13 12 28 0C 0A 17 28 17 18 1D 28 20 0E 0A 1B 28 1D 11 0E 16 C3 | New English Hex + +-------------------------------------- +Neurath - Jennifer Shop (Green Head): +-------------------------------------- + +Frog: +ぢぇにふぁー「ノイラートの鬼いは どうだい?」 +Jennifer "Demon physician Neurath to university?" +$44A55 +F6 62 0C 5D 0D 3E 0C 44 0C 70 0C F7 0C C1 00 8D 00 76 00 9B 00 F7 00 88 00 41 00 3D 01 2A 00 42 00 28 00 65 00 2B 00 61 00 2A 00 24 00 C2 00 | Original Japanese Hex +LENGTH ぢRED ぇRED にRED ふRED ぁRED ーRED 「BLACK ノBLACK イBLACK ラBLACK ーBLACK トBLACK のBLACK 鬼BLACK いBLACK はBLACK BLACK どBLACK うBLACK だBLACK いBLACK ?BLACK 」BLACK | Original Japanese Text +LENGTH JRED ERED NRED YRED :BLACK NBLACK EBLACK EBLACK DBLACK BLACK NBLACK EBLACK UBLACK RBLACK ABLACK TBLACK HBLACK BLACK WBLACK ABLACK RBLACK PBLACK ?BLACK | New English Text +F6 13 0C 0E 0C 17 0C 22 0C D6 00 17 00 0E 00 0E 00 0D 00 28 00 17 00 0E 00 1E 00 1B 00 0A 00 1D 00 11 00 28 00 20 00 0A 00 1B 00 19 00 24 00 | New English Hex + +OK Selected: +かんしゃするぜっいぇーい +Yay Thanks +$44A84 +2B 09 2E 56 34 72 35 51 5F 71 2A 5D F7 2A | Original Japanese Hex +LENGTH LENGTH か ん し ゃ す る ぜ っ い ぇ ー い | Original Japanese Text +LENGTH Y A Y , T H A N K Y O U | New English Text +0C 22 0A 22 C4 1D 11 0A 17 14 28 22 18 1E | New English Hex + +No Selected: +いらねーのかっ いつでも持っているぜベイビー +Ll do the Irane Baby ze you have at any time +$44AA2 (Line 1) +06 2A 4F 40 F7 41 2E 71 | Original Japanese Hex +LENGTH い ら ね ー の か っ | Original Japanese Text +LENGTH P L E A S E , | New English Text +06 19 15 0E 0A 1C 0E C4 | New English Hex +$44A92 (Line 2) +2D 04 2A 3A 64 4B 3C 71 3B 2A 51 5F B5 76 B3 F7 | Original Japanese Hex +LENGTH LENGTH い つ で も 持 っ て い る ぜ ベ イ ビ ー | Original Japanese Text +LENGTH I H A V E C H I L D R E N | New English Text +0E 12 28 11 0A 1F 0E 28 0C 11 12 15 0D 1B 0E 17 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/StartScreen.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/StartScreen.txt new file mode 100644 index 00000000..e8cbc66d --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/StartScreen.txt @@ -0,0 +1,136 @@ +-------------- +Start Screen: +-------------- +------------------------------------------- +BG Edit to make stuff fit (Does not work): + +$41595 +2A 11 36 | Original BG Hex +47 11 2A | New BG Hex + +$415F4 +5F 11 | Original BG Hex +28 00 | New BG Hex + +EXP.: +$415CB +0E 0C 21 0C 19 0C 30 0D | Original BG Hex +E X P . | Original BG Text + E X P | New BG Text +5E 11 0E 0C 21 0C 19 0C | New BG Hex + +------------------------------------------- + +耐久力 +Endurance/Stamina (Top Half) +$10EBB $10EC7 $10ED3 +A4 21 A5 21 8F 21 | Original Japanese Hex +耐BLACK 久BLACK 力BLACK | Original Japanese Text +BLACK HBLACK PBLACK | New English Text +48 20 21 20 29 20 | New English Hex + Endurance/Stamina (Bottom Half) + $10EC1 $10ECD $10ED9 + B4 21 B5 21 9F 21 | Original Japanese Hex + 耐BLACK 久BLACK 力BLACK | Original Japanese Text + BLACK HBLACK PBLACK | New English Text + 58 20 31 20 39 20 | New English Hex + +正常 +Normal (Top half) +$17A39 $17A45 +8B 29 C6 2A | Original Japanese Hex +正GOLD 常GOLD | Original Japanese Text +OGOLD KGOLD | New English Text +28 28 24 28 | New English Hex + Normal (Bottom half) + $17A3F $17A4B + 9B 29 D6 2A | Original Japanese Hex + 正GOLD 常GOLD | Original Japanese Text + OGOLD KGOLD | New English Text + 38 28 34 28 | New English Hex + +装備 +Equipment +$41699 +43 00 01 60 61 28 28 | Original Japanese Hex +LENGTH LENGTH LENGTH 装 備 | Original Japanese Text +LENGTH E Q U I | New English Text +03 0E 1A 1E 12 28 28 | New English Hex + +右手 +Right Hand +$416A0 +E3 41 0D 40 0D 28 00 D6 00 | Original Japanese Hex +LENGTH 右RED 手RED BLACK :BLACK | Original Japanese Text +LENGTH RRED HRED BLACK :BLACK | New English Text +E3 1B 0C 11 0C 28 00 D6 00 | New English Hex + +左手 +Left Hand +$416A9 +E3 42 0D 40 0D 28 00 D6 00 | Original Japanese Hex +LENGTH 左RED 手RED BLACK :BLACK | Original Japanese Text +LENGTH LRED HRED BLACK :BLACK | New English Text +E3 15 0C 11 0C 28 00 D6 00 | New English Hex + +両うで +Arms +$416B2 +E3 63 0D 2B 0C 64 0C D6 00 | Original Japanese Hex +LENGTH 両RED うRED でRED :BLACK | Original Japanese Text +LENGTH ARED RRED MRED :BLACK | New English Text +E3 0A 0C 1B 0C 16 0C D6 00 | New English Hex + +両足 +Feet/Legs +$416BB +E3 63 0D 64 0D 28 00 D6 00 | Original Japanese Hex +LENGTH 両RED 足RED BLACK :BLACK | Original Japanese Text +LENGTH LRED ERED GRED :BLACK | New English Text +E3 15 0C 0E 0C 10 0C D6 00 | New English Hex + +胴体 +Body +$416C4 +E3 44 0D 45 0D 28 00 D6 00 | Original Japanese Hex +LENGTH 胴RED 体RED BLACK :BLACK | Original Japanese Text +LENGTH BRED DRED YRED :BLACK | New English Text +E3 0B 0C 0D 0C 22 0C D6 00 | New English Hex + +頭 +Head +$416CD +E3 43 0D 28 00 28 00 D6 00 | Original Japanese Hex +LENGTH 頭RED BLACK : | Original Japanese Text +LENGTH HRED DRED : | New English Text +E3 11 0C 0D 0C 28 00 D6 00 | New English Hex + +攻撃力: +Attack/Offensive Power +$40C7D +03 C7 C8 CF D6 | Original Japanese Hex +LENGTH 攻 撃 力 : | Original Japanese Text +LENGTH A T P : | New English Text +03 0A 1D 19 D6 | New English Hex + +守備力: +Defensive Power: +$416D6 +03 DB DC CF D6 | Original Japanese Hex +LENGTH 守 備 力 : | Original Japanese Text +LENGTH D F P : | New English Text +03 0D 0F 19 D6 | New English Hex + +移動力 +Locomotion (Top Half) +$17EA5 $17EB1 $17EBD +8D 21 8E 21 8F 21 | Original Japanese Hex +移BLACK 動BLACK 力BLACK | Original Japanese Text +SBLACK TBLACK PBLACK | New English Text +2C 20 2D 20 29 20 | New English Hex + Locomotion (Bottom Half) + $17EAB $17EB7 $17EC3 + 9D 21 9E 21 9F 21 | Original Japanese Hex + 移BLACK 動BLACK 力BLACK | Original Japanese Text + SBLACK TBLACK PBLACK | New English Text + 3C 20 3D 20 39 20 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Status.txt b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Status.txt new file mode 100644 index 00000000..1b351495 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/Text/Status.txt @@ -0,0 +1,80 @@ +------------------- +Status - Messages: +------------------- +しんでいる +Is dead (Top Half) +$27639 $27645 $27651 $2765D $27669 +64 28 A6 28 C4 28 4A 28 A1 28 | Original Japanese Hex +しGOLD んGOLD でGOLD いGOLD るGOLD | Original Japanese Text +DGOLD EGOLD AGOLD TGOLD HGOLD | New English Text +0D 28 0E 28 0A 28 2D 28 21 28 | New English Hex + Is dead (Bottom Half) + $2763F $2764B $27657 $27663 $2766F + 74 28 B6 28 D4 28 5A 28 B1 28 | Original Japanese Hex + しGOLD んGOLD でGOLD いGOLD るGOLD | Original Japanese Text + DGOLD EGOLD AGOLD TGOLD HGOLD | New English Text + 1D 28 1E 28 1A 28 3D 28 31 28 | New English Hex + +まひ +Paralysis (Top Half) +$2767A $27686 +87 28 83 28 | Original Japanese Hex +まGOLD ひGOLD | Original Japanese Text +SGOLD TGOLD | New English Text +2C 28 2D 28 | New English Hex + Paralysis (Bottom Half) + $27680 $2768C + 97 28 93 28 | Original Japanese Hex + まGOLD ひGOLD | Original Japanese Text + SGOLD TGOLD | New English Text + 3C 28 3D 28 | New English Hex + +--------------- +Status - Item: +--------------- +装備+ +Equipment+ (Top Half) +$4EA49 $4EA55 $4EA61 +C0 22 C1 22 28 22 | Original Japanese Hex +装WHITE 備WHITE +WHITE | Original Japanese Text +EWHITE QWHITE +WHITE | New English Text +0E 20 2A 20 28 22 | New English Hex + Equipment+ (Bottom Half) + $4EA4F $4EA5B $4EA67 + D0 22 D1 22 38 22 | Original Japanese Hex + 装WHITE 備WHITE +WHITE | Original Japanese Text + EWHITE QWHITE +WHITE | New English Text + 1E 20 3A 20 38 22 | New English Hex + +--------------- +Status - Time: +--------------- +ごご +P.M. (Uses Only Top Half Of Letters) +$249A5 $249A5 +AB 20 AB 20 | Original Japanese Hex +ごWHITE ごWHITE | Original Japanese Text +PWHITE PWHITE | New English Text +29 20 29 20 | New English Hex + +ごぜん +A.M. (Uses Only Top Half Of Letters) +$249BC $249C9 $249D6 +AB 20 AF 20 A6 20 | Original Japanese Hex +ごWHITE ぜWHITE んWHITE | Original Japanese Text +AWHITE MWHITE WHITE | New English Text +0A 20 26 20 48 20 | New English Hex + +じ +Hour (Top Half) +$24A14 +AD 20 | Original Japanese Hex +じWHITE | Original Japanese Text +HWHITE | New English Text +21 20 | New English Hex + Hour (Bottom Half) + $24A1A + BD 20 | Original Japanese Hex + じWHITE | Original Japanese Text + HWHITE | New English Text + 31 20 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/make.bat b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/make.bat new file mode 100644 index 00000000..2c3accd4 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Albert Odyssey/make.bat @@ -0,0 +1,2 @@ +bass "Albert Odyssey.asm" +ucon64 --nbak --chk "Albert Odyssey.sfc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/README.md b/roms/snes/peter-lemon-snes/Translate/README.md new file mode 100644 index 00000000..d2bfdb45 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/README.md @@ -0,0 +1,23 @@ +SNES Japanese To English Translation +===================================== +
    +Translation by krom (Peter Lemon).
    +
    +All code compiles out of box with the bass assembler:
    +http://byuu.org/tool/bass
    +I have also included an IPS file of the translation as a patch.
    +
    +Please check out RomHacking & their forum, a great resource for translation work:
    +http://www.romhacking.net
    +
    +Howto Compile:
    +You will need the original Japanese ROM in .sfc (Little-Endian) Format, without a header, in the root directory of this patch
    +All the code compiles into a single binary (ROMNAME.sfc) file.
    +Using bass Run: make.bat
    +Or you can patch the original Japanese ROM using the IPS file.
    +
    +Howto Run:
    +I only test with a real SNES using a SD2SNES Cartridge by ikari:
    +http://sd2snes.de
    +
    +You can also use SNES emulators like higan & the MESS SNES Driver. diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.png b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.png new file mode 100644 index 00000000..9487efa0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.txt new file mode 100644 index 00000000..a917afb3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/CharTables/CharTable.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0| 0 1 2 3 4 5 6 7 8 9 あ い う え お +1|か き く け こ さ し す せ そ た ち つ て と な +2|に ぬ ね の は ひ ふ へ ほ ま み む め も や ゆ +3|よ ら り る れ ろ わ を ん ア イ ウ エ オ カ キ +4|ク ケ コ サ シ ス セ ソ タ チ ツ テ ト ナ ニ ヌ +5|ネ ノ ハ ヒ フ ヘ ホ マ ミ ム メ モ ヤ ユ ヨ ラ +6|リ ル レ ロ ワ ヲ ン ぁ っ ゃ ゅ ょ ッ ャ ュ ョ +7|、 。 ・ ー一 ! ? X 「 」 両 U P が ぎ ぐ げ +8|ご ざ じ ず ぜ ぞ だ ぢ づ で ど ば び ぶ べ ぼ +9|ガ ギ グ ゲ ゴ ザ ジ ズ ゼ ゾ ダ ヂ ヅ デ ド バ +A|ビ ブ ベ ボ ぱ ぴ ぷ ぺ ぽ パ ピ プ ペ ポ +B| +C| +D| +E| +F| NEWPAGE NEWLINE ENDTEXT \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/ConvertFontRLE.py b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/ConvertFontRLE.py new file mode 100644 index 00000000..06ddc21d --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/ConvertFontRLE.py @@ -0,0 +1,100 @@ +# Konami SNES RLE Compress +BLOCKRAW = 0x80 # BLOCK: RAW Copy 5-Bit "0x80 + LENGTH (0..31), DATA.." +BLOCKRLEZERO4 = 0xE0 # BLOCK: RLE Zero 4-Bit "0xE0 + LENGTH-2 (2..17)" +BLOCKRLEZERO8 = 0xFF # BLOCK: RLE Zero 8-Bit "0xFF, LENGTH-2 (2..257)" + +RAWRLELENGTH = [] +# 1st PASS: Get RAW & Zero Run Data Lengths From File in Order +with open("Font2BPPENG.pic", "rb") as fin: + bytein = fin.read(1) + rawcount = 0 + zerocount = 0 + while bytein: + if bytein != b'\x00': # RAW Copy Block + rawcount += 1 + if zerocount >= 2: + if zerocount >= 258: # RLE Data > MAX LENGTH + while zerocount >= 258: + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(0xFF) + zerocount -= 257 + + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(zerocount-2) + else: + rawcount += zerocount + zerocount = 0 + else: # RLE Zero Block (bytein == b'\x00') + zerocount += 1 + if zerocount == 2: + if rawcount != 0: + RAWRLELENGTH.append(BLOCKRAW+rawcount) + rawcount = 0 + + if rawcount >= 31: # MAX RAW Copy Length Check + RAWRLELENGTH.append(BLOCKRAW+31) + rawcount -= 31 + zerocount = 0 + bytein = fin.read(1) +fin.close() + +# Get Last Remaing Block (IF Any) After File Has Been Read +# RLE Zero Block +if zerocount >= 2: + if zerocount >= 258: # RLE Data > MAX LENGTH + while zerocount >= 258: + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(0xFF) + zerocount -= 257 + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(zerocount-2) +else: + rawcount += zerocount +# RAW Copy Block +if rawcount >= 31: # MAX RAW Copy Length Check + RAWRLELENGTH.append(BLOCKRAW+31) + rawcount -= 31 +if rawcount != 0: + RAWRLELENGTH.append(BLOCKRAW+rawcount) + +# 2nd PASS: Save Lengths & RAW Data To File +fout = open("Font2BPPENG.rle", "wb") +i = 0 +bytelength = 2 +fout.write(b"%c" %0x00) # 2 Byte Pad For Byte Length +fout.write(b"%c" %0x00) +with open("Font2BPPENG.pic", "rb") as fin: + while i < len(RAWRLELENGTH): + if RAWRLELENGTH[i] != 255: # RAW Copy Bytes + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + rawcount = RAWRLELENGTH[i] - BLOCKRAW + while rawcount != 0: + bytein = fin.read(1) + fout.write(bytein) + bytelength += 1 + rawcount -= 1 + i += 1 + + else: # RLE Zero Bytes + if RAWRLELENGTH[i+1] >= 16: + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + i += 1 + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + else: + i += 1 + fout.write(b"%c" %(BLOCKRLEZERO4+RAWRLELENGTH[i])) + bytelength += 1 + rlecount = RAWRLELENGTH[i] + 2 + while rlecount != 0: + bytein = fin.read(1) + rlecount -= 1 + i += 1 +fout.seek(0) # Seek To The Start Of The Output File +fout.write(b"%c" %(bytelength & 0xFF)) +fout.write(b"%c" %(bytelength >> 8)) +fin.close() +fout.close() +print("Compressed Byte Length = %d" %bytelength) diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.pic b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.pic new file mode 100644 index 00000000..a0384ec3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.pic differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.png b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.png new file mode 100644 index 00000000..cc388f42 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.rle b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.rle new file mode 100644 index 00000000..f9be6181 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPENG.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPJPN.png b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPJPN.png new file mode 100644 index 00000000..9487efa0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font/Font2BPPJPN.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font2BPPENG.rle b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font2BPPENG.rle new file mode 100644 index 00000000..f9be6181 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Font2BPPENG.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/README.md b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/README.md new file mode 100644 index 00000000..98a9d2d9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/README.md @@ -0,0 +1,6 @@ +SNES Japanese To English Translation +===================================== +
    +** This translation is now discontinued **
    +Please go to: https://www.romhacking.net/translations/5666/
    +For a full 100% complete translation. diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.asm b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.asm new file mode 100644 index 00000000..4ea17f0e --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.asm @@ -0,0 +1,376 @@ +// SNES "Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!" Japanese To English Translation by krom (Peter Lemon): + +output "Ebisumaru Puzzle Maze - Goemon is Missing!!.sfc", create +origin $00000; insert "Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!! (J).sfc" // Include Japanese Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!! SNES ROM +origin $007FC0 +db "SOREYUKE EBISUMARU EN" // $007FC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +macro TextNormal(OFFSET, TEXT) { + origin {OFFSET} + db {TEXT} +} + +macro TextTitleScreenUpper(OFFSET, TEXT) { + // Char Table (Title Screen Top) + map ' ', $00 + map 'A', $00, 16 + map 'Q', $20, 10 + + map '<', $8C + map '>', $8D + map '!', $8E + + map 'b', $22 // Blue Font color + map 'y', $26 // Yellow Font color + + origin {OFFSET} + db {TEXT} +} + +macro TextTitleScreenLower(OFFSET, TEXT) { + // Char Table (Title Screen Bottom) + map ' ', $00 + map 'A', $10, 16 + map 'Q', $30, 10 + + map '<', $9C + map '>', $9D + map '!', $9E + + map 'b', $22 // Blue Font color + map 'y', $26 // Yellow Font color + + origin {OFFSET} + db {TEXT} +} + +// Include English Font +origin $A46DE; insert "Font2BPPENG.rle" // 128x128 2BPP Konami RLE + +// Include English Title Screen Font +origin $A502E; insert "TitleScreenFont4BPPENG.rle" // 128x88 4BPP Konami RLE + + +// TITLE SCREEN (Blue) +TextTitleScreenUpper($0C629, "SbTbObRbYb MbObDbEb ") +TextTitleScreenLower($0C669, "SbTbObRbYb MbObDbEb ") + +TextTitleScreenUpper($0C689, "MbUbLbTbIb PbLbAbYbEbRb ") +TextTitleScreenLower($0C6C9, "MbUbLbTbIb PbLbAbYbEbRb ") + +TextTitleScreenUpper($0C6E9, "PbAbSbSbWbObRbDb IbNbPbUbTb ") +TextTitleScreenLower($0C729, "PbAbSbSbWbObRbDb IbNbPbUbTb ") + +TextTitleScreenUpper($0C749, "CbObNbFbIbGbUbRbAbTbIbObNb ") +TextTitleScreenLower($0C789, "CbObNbFbIbGbUbRbAbTbIbObNb ") + +// TITLE SCREEN (Yellow) +TextTitleScreenUpper($0C7A9, "SyTyOyRyYy MyOyDyEy ") +TextTitleScreenLower($0C7E9, "SyTyOyRyYy MyOyDyEy ") + +TextTitleScreenUpper($0C809, "MyUyLyTyIy PyLyAyYyEyRy ") +TextTitleScreenLower($0C849, "MyUyLyTyIy PyLyAyYyEyRy ") + +TextTitleScreenUpper($0C869, "PyAySySyWyOyRyDy IyNyPyUyTy ") +TextTitleScreenLower($0C8A9, "PyAySySyWyOyRyDy IyNyPyUyTy ") + +TextTitleScreenUpper($0C8C9, "CyOyNyFyIyGyUyRyAyTyIyOyNy ") +TextTitleScreenLower($0C909, "CyOyNyFyIyGyUyRyAyTyIyOyNy ") + + +// MULTI PLAYER +// Char Table (Multi Player) + map 'A', $00, 16 + map 'Q', $20, 10 + map ' ', $2A + + map '<', $8C + map '>', $8D + map '!', $8E + +TextNormal($0A6A4, "START!") +TextNormal($0A6B5, "EXIT!!") +TextNormal($0A6CE, "COURSE") +TextNormal($0A6D7, "SCORE TO WIN") +TextNormal($0A6EE, "CONFIGURATION ") + + +// NPC +// Char Table (NPC) +map ' ', $00 +map '0', $01, 10 +map 'A', $0B, 26 +map 'a', $25, 20 +map 'u', $67 +map 'v', $39, 5 +map '\s', $3E // Single Quote +map '<', $3F // Double Quote Left +map '>', $40 // Double Quote Right + +map $2C, $70 // Comma "," +map '.', $71 +map '_', $72 +map '-', $73 +map '!', $74 +map '?', $75 +map '$', $79 +map '\n', $FE // newline + +constant NEWPAGE($FD) // New Page Character +constant ENDTEXT($FF) // End Text Character + +// NPC SHOP +TextNormal($0C9D6, "Welcome.\n") + db "How may I help?", NEWPAGE + db "You can hold 1 item", ENDTEXT + +TextNormal($0CA03, "Armor. Price $300.\n") + db "Takes 1 enemy hit.", ENDTEXT + +TextNormal($0CA29, "Clock. Price $500.\n") + db "Gives extra time.", ENDTEXT + +TextNormal($0CA51, ". Price $800.\n") + db "Add extra life.", ENDTEXT + +TextNormal($0CA6F, "Is this OK?\n") + db " Yes No ", ENDTEXT + +TextNormal($0CA8C, "Thank you. ") ; db ENDTEXT + +TextNormal($0CA99, "Need more gold!") ; db ENDTEXT + +TextNormal($0CAA9, "Visit anytime.") ; db ENDTEXT + + +TextNormal($0CC38, "Welcome. Slot machine\n") + db "1 play $5.", NEWPAGE + db "Rules are simple. Push\n" + db "button stops drum.", NEWPAGE + db "Match symbols to win.", NEWPAGE + db "Play?\n" + db " Play Quit", ENDTEXT + +TextNormal($0CCB1, "No Win") ; db ENDTEXT + +TextNormal($0CCB8, "777!! You win $500.") ; db ENDTEXT + +TextNormal($0CCCD, "Cherries! Win $10.") ; db ENDTEXT + +TextNormal($0CCE0, "Bells! Win $15.") ; db ENDTEXT + +TextNormal($0CCF0, "Cats!! Win $50.") ; db ENDTEXT + +TextNormal($0CD00, "Orange! Win $15.") ; db ENDTEXT + +TextNormal($0CD11, "Play again?\n") + db " Yes No ", ENDTEXT + +TextNormal($0CD2F, "Please come again. ") ; db ENDTEXT + +// NPC +TextNormal($0CE93, "Huh, who are you?\n") + db "Why are you on", NEWPAGE + db "?\n" + db "A guy in red clothes", NEWPAGE + db "came by, but I was in\n" + db "such a rush...", ENDTEXT + +TextNormal($0CF01, "Eat a meal to keep\n") + db "your energy high.", ENDTEXT + +TextNormal($0CF26, "What? Goemon?!\n") + db "Was that his name?!", NEWPAGE + db "Asking me questions.\n" + db "I hope he's OK?", ENDTEXT + +TextNormal($0CF6E, "This island is nice.\n") + db "It's all a maze.", ENDTEXT + +TextNormal($0CF94, "To go a long way\n") + db "use to jump.", NEWPAGE + db "You need a \n" + db "to make use of one.", ENDTEXT + +TextNormal($0CFE3, "To change direction\n") + db "press on the red floor.", ENDTEXT + +TextNormal($0D00F, "Aim the \n") + db "using timing on your", NEWPAGE + db "button press!!", ENDTEXT + +TextNormal($0D04A, "When entering a\n") + db "", NEWPAGE + db "you can warp... Me? I\n" + db "have not tried myself.", ENDTEXT + +TextNormal($0D094, "Watchout for the bad\n") + db "robot in the maze.", ENDTEXT + +TextNormal($0D0BC, "I am 40 years old.\n") + db "I have great .", NEWPAGE + db "How are you?\n" + db "______________________", NEWPAGE + db "Ah, there's a problem?\n" + db "You need help? ", NEWPAGE + db "______________________\n" + db "______________________", NEWPAGE + db "How come? Are you\n" + db "already lost?", NEWPAGE + db "______________________\n" + db "______________________", NEWPAGE + db "How is this? You need\n" + db "to look harder!", NEWPAGE + db "______________________\n" + db "______________________", NEWPAGE + db "How is this so?\n" + db "Such a pity.", NEWPAGE + db "______________________\n" + db "______________________", NEWPAGE + db "Do you think I'm\n" + db "strange?", ENDTEXT + +TextNormal($0D265, "Use the spring to\n") + db "defeat enemies.", NEWPAGE + db "However, it\n" + db "accelerates your speed", NEWPAGE + db "dangerously!\n" + db "Take care with it!", ENDTEXT + +TextNormal($0D2CA, "You're a real person!?\n") + db "This is no place", NEWPAGE + db "for you.\n" + db "Why visit here?", ENDTEXT + +TextNormal($0D30B, "What?? I'm hungry!?\n") + db "I don't have food.", NEWPAGE + db "There might be a shop.\n" + db "But in ", NEWPAGE + db "I've not seen any food.\n" + db "I wonder why??", ENDTEXT + +TextNormal($0D382, "The shop next door has\n") + db "a big slot machine.", NEWPAGE + db "I don't know myself,\n" + db "but I heard you win", NEWPAGE + db "money by matching the\n" + db "symbols. The jackpot", NEWPAGE + db "can be won with 777.\n" + db "Will you get lucky?...", ENDTEXT + +TextNormal($0D432, "If you have any money,\n") + db "try to go next door.", NEWPAGE + db "He is now back after a\n" + db "long time away.", ENDTEXT + +TextNormal($0D485, "Hey. Have you heard?\n") + db "A became", NEWPAGE + db "available, in the day.\n" + db "I hear you can collect", NEWPAGE + db "a lot of gold.\n" + db "Are you interested?", NEWPAGE + db "Good luck...", ENDTEXT + +TextNormal($0D50F, "Bad robots in the maze\n") + db "can step on switches,", NEWPAGE + db "if you time it well.\n" + db "That's right! If it is", NEWPAGE + db "in a dangerous place,\n" + db "use a robot!!", ENDTEXT + +TextNormal($0D58C, "Recently at night, a\n") + db "bad robot has shown up", NEWPAGE + db "in town. You'll find\n" + db "it hard on your own.", NEWPAGE + db "What? You can handle\n" + db "it!? Are you lucky?", NEWPAGE + db "Try to dodge the arrows\n" + db "to win.", ENDTEXT + +TextNormal($0D62B, "Ahead is !!\n") + db "Stop it with .", NEWPAGE + db "Try not to step on it\n" + db "yourself!", ENDTEXT + +// NPC TREASURE +TextNormal($0E307, "Long ago on \n") + db "I hid a treasure.", NEWPAGE + db "Do you want to get\n" + db "rich?", NEWPAGE + db "I'm the only one that\n" + db "knows the short-cut.", NEWPAGE + db "I'll need $500 to take\n" + db "you...", NEWPAGE + db "Do you want to go?\n" + db " Yes No ", ENDTEXT + + +TextNormal($0E677, "Collect the treasure!\n") + db "Take care!", ENDTEXT + +TextNormal($0E698, "You'll need to bring\n") + db "more gold than that.", ENDTEXT + +TextNormal($0E6C2, "Did you find treasure?\n") + db "I know it's hard.", ENDTEXT + + +TextNormal($0E6FF, "OK. Sad you don't want\n") + db "to go! Maybe later...", ENDTEXT + +// INTRO +// Char Table (INTRO) +map ' ', $00 +map '0', $01, 10 +map '$', $0B +map $2C, $0E // Comma "," +map '.', $0F +map 'A', $20, 16 +map 'Q', $40, 10 +map 'a', $4A, 6 +map 'g', $60, 15 +map 'v', $80, 5 +map '\s', $85 // Single Quote +map '<', $86 // Double Quote Left +map '>', $87 // Double Quote Right + +map '_', $EC +map '-', $ED +map '!', $EE +map '?', $EF + +TextNormal($F0000, "Hi Goemon. Are you in? ") ; db $00 + +TextNormal($F0019, "Huh? Where did you go? ") ; db $00 + +TextNormal($F0032, "Well, I guess I'll have ") ; db $00 + db "to eat this food alone!?", $00 + +TextNormal($F0065, "???????????????????????") ; db $00 + +TextNormal($F007D, "What is this letter...? ") ; db $00 + db "Hmm? What??? ", $00 + +TextNormal($F00AE, "I'm going to take care_Goemon", $00 + +TextNormal($F00E0, "Do not worry Goemon... ") ; db $00 + db "What am I going to do? ", $00 + +TextNormal($F0112, "Well, yeah. I could play ") ; db $00 + db "a game to kill time. ", $00 + +TextNormal($F0147, "At any rate, Goemon. ") ; db $00 + db "I still feel hungry. ", $00 + +TextNormal($F0178, "Are you in any trouble?") ; db $00 + +TextNormal($F0190, "After all, this does not ") ; db $00 + db "seem good for Goemon. ", $00 + +TextNormal($F01C2, "I hope he is all right. ") ; db $00 + +TextNormal($F01DD, "What if he is missing...") ; db $00 + db "Why didn't you say hi!!!", $00 + +TextNormal($F020E, "Now I'm the lead role... ") ; db $00 \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.ips b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.ips new file mode 100644 index 00000000..e3a29378 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.ips differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/INTRO.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/INTRO.txt new file mode 100644 index 00000000..2e5bc6ab --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/INTRO.txt @@ -0,0 +1,146 @@ +ゴエモンはーん。いてまっか? +Hi Goemon. Are you in? +$F0000 +00 1C 89 83 C2 CD 49 ED 6D 0F 00 21 42 4E E3 25 EF 00 00 00 00 00 00 00 00 | Original Japanese Hex + " ゴ エ モ ン は ー ん 。 い て ま っ か ? END | Original Japanese Text +H i G o e m o n . A r e y o u i n ? END | New English Text + +あれ? どこいったんや? +Huh? Where did you go? +$F0019 +00 20 69 EF 00 1C 43 29 21 E3 2F 6D 63 EF 00 00 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + あ れ ? " ど こ い っ た ん や ? END | Original Japanese Text +H u h ? W h e r e d i d y o u g o ? END | New English Text + +さては れてにないしょで ひとりで +Well then, I guess I'll be eating +$F0032 (Line 1) +00 2A 42 49 00 6B 42 45 44 21 2B E2 1C 42 00 4A 43 67 1C 42 00 00 00 00 00 00 | Original Japanese Hex + さ て は れ て に な い し ょ " で ひ と り " で END | Original Japanese Text +W e l l , I g u e s s I ' l l h a v e END | New English Text +うまいもん たべに いったんちゃいまっか!? +this delicious meal alone!? +$F004C (Line 2) +00 22 4E 21 62 6D 00 2F 1C 4C 45 00 21 E3 2F 6D 40 E0 21 4E E3 25 EE EF 00 | Original Japanese Hex + う ま い も ん た " べ に い っ た ん ち ゃ い ま っ か ! ? END | Original Japanese Text +t o e a t t h i s f o o d a l o n e ! ? END | New English Text + +?????????????????????? +?????????????????????? +$F0065 +00 EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF EF 00 | Original Japanese Hex + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? END | Original Japanese Text +? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? END | New English Text + +ん??? なんや このてがみは・・・??? +Hmm??? What is this letter...??? +$F007D (Line 1) +00 6D EF EF EF 00 44 6D 63 00 29 48 42 1C 25 4F 49 EC EC EC EF EF EF 00 00 | Original Japanese Hex + ん ? ? ? な ん や こ の て " が み は ・ ・ ・ ? ? ? END | Original Japanese Text +W h a t i s t h i s l e t t e r . . . ? END | New English Text +なに? なに??? +Huh? What??? +$F0096 (Line 2) +00 44 45 EF 00 44 45 EF EF EF 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + な に ? な に ? ? ? END | Original Japanese Text +H m m ? W h a t ? ? ? END | New English Text + +「からくりアイランド」に いってくる。 +I'm going to "Karakuri Island". +$F00AE (Line 1) +00 EA 25 66 27 67 80 81 C6 CD 1C A3 EB 45 00 21 E3 42 27 68 0F 00 00 00 00 | Original Japanese Hex + 「 か ら く り ア イ ラ ン " ド 」 に い っ て く る 。 END | Original Japanese Text +I ' m g o i n g t o " K a r a k u r i END | New English Text +るすをたのむ。 ゴエモン。 +Take care of the house. Goemon. +$F00C7 (Line 2) +00 68 2C 6C 2F 48 60 0F 00 1C 89 83 C2 CD 0F 00 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + る す を た の む 。 " ゴ エ モ ン 。 END | Original Japanese Text +I s l a n d " t a k e c a r e ・ G o e m o n END | New English Text + +あんなぶっそうなしまに ゴエモンはん +Do not worry Goemon, +$F00E0 (Line 1) +00 20 6D 44 1C 4B E3 2E 22 44 2B 4E 45 00 1C 89 83 C2 CD 49 6D 00 00 00 00 00 | Original Japanese Hex + あ ん な " ぶ っ そ う な し ま に " ゴ エ モ ン は ん END | Original Japanese Text +D o n o t w o r r y G o e m o n . . . END | New English Text +いったい なにしに いきはったんやろか? +what on earth am I going to do? +$F00FA (Line 2) +00 21 E3 2F 21 00 44 45 2B 45 00 21 26 49 E3 2F 6D 63 6A 25 EF 00 00 00 | Original Japanese Hex + い っ た い な に し に い き は っ た ん や ろ か ? END | Original Japanese Text +W h a t a m I g o i n g t o d o ? END | New English Text + +ま、ええわ。 ひまつぶしに グームでもして +Well, yeah. I could play +$F0112 (Line 1) +00 4E 0E 23 23 6B 0F 00 4A 4E 41 1C 4B 2B 45 00 1C 88 ED C0 1C 42 62 2B 42 00 00 | Original Japanese Hex + ま 、 え え わ 。 ひ ま つ " ぶ し に " グ ー ム " で も し て END | Original Japanese Text +W e l l , y e a h . I c o u l d p l a y END | New English Text +るすばんでも しといたりまひょか。 +a game to kill time. +$F012D (Line 2) +00 68 2C 1C 49 6D 1C 42 62 00 2B 43 21 2F 67 4E 4A E2 25 0F 00 00 00 00 00 00 | Original Japanese Hex + る す " ば ん " で も し と い た り ま ひ ょ か 。 END | Original Japanese Text +a g a m e t o k i l l t i m e . END | New English Text + +それにしても ゴエモンはん。 +At any rate, Goemon. +$F0147 (Line 1) +00 2E 69 45 2B 42 62 00 1C 89 83 C2 CD 49 6D 0F 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + そ れ に し て も " ゴ エ モ ン は ん 。 END | Original Japanese Text +A t a n y r a t e , G o e m o n . END | New English Text +かえりおそいなぁ。 +I still feel hungry. +$F0160 (Line 2) +00 25 23 67 24 2E 21 44 6E 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + か え り お そ い な ぁ 。 END | Original Japanese Text +I s t i l l f e e l h u n g r y . END | New English Text + +なんか あったんと ちゃうやろか?! +Are you in any trouble?! +$F0178 +00 44 6D 25 00 20 E3 2F 6D 43 00 40 E0 22 63 6A 25 EF EE 00 00 00 00 00 | Original Japanese Hex + な ん か あ っ た ん と ち ゃ う や ろ か ? ! END | Original Japanese Text +A r e y o u i n a n y t r o u b l e ? END | New English Text + +やはり ゴエモンはんには、わてがついてな +After all, this does not +$F0190 (Line 1) +00 63 49 67 00 1C 89 83 C2 CD 49 6D 45 49 0E 6B 42 1C 25 41 21 42 44 00 00 00 | Original Japanese Hex + や は り " ゴ エ モ ン は ん に は 、 わ て " が つ い て な END | Original Japanese Text +A f t e r a l l , t h i s d o e s n o t END | New English Text +あかんようやな。 +seem good for Goemon. +$F01AA (Line 2) +00 20 25 6D 65 22 63 44 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 | Original Japanese Hex + あ か ん よ う や な 。 END | Original Japanese Text +s e e m g o o d f o r G o e m o n . END | New English Text + +どうせ まいごにでも なったんやろ。 +I hope he is all right. +$F01C2 +00 1C 43 22 2D 00 4E 21 1C 29 45 1C 42 62 00 44 E3 2F 6D 63 6A 0F 00 00 00 00 00 | Original Japanese Hex + " ど う せ ま い " ご に " で も な っ た ん や ろ 。 END | Original Japanese Text +I h o p e h e i s a l l r i g h t . END | New English Text + +たベものも なくなった ことやし・・・・・・ +What if he has gone missing...... +$F01DD (Line 1) +00 2F 1C 4C 62 48 62 00 44 27 44 E3 2F 00 29 43 63 2B EC EC EC EC EC EC 00 | Original Japanese Hex + た " ベ も の も な く な っ た こ と や し ・ ・ ・ ・ ・ ・ END | Original Japanese Text +W h a t i f h e i s m i s s i n g . . . END | New English Text +いっちよ、たすけに いったりまひょか!!! +Wait a minute, why did you not say hi!!! +$F01F6 (Line 2) +00 21 E3 40 E2 0E 2F 2C 28 45 00 21 E3 2F 67 4E 4A E2 25 EE EE EE 00 00 00 | Original Japanese Hex + い っ ち よ 、 た す け に い っ た り ま ひ ょ か ! ! ! END | Original Japanese Text +W h y d i d n ' t y o u s a y h i ! ! ! END | New English Text + +ついに わてが しゅやくでんな・・・フフフ +Finally I am in the lead role... +At last I am the main character... +$F020E +00 41 21 45 00 6B 42 1C 25 00 2B E1 63 27 1C 42 6D 44 EC EC EC AB AB AB 00 00 | Original Japanese Hex + つ い に わ て " が し ゅ や く " で ん な ・ ・ ・ フ フ フ END | Original Japanese Text +N o w I ' m t h e l e a d r o l e . . . END | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/MULTIPLAYER.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/MULTIPLAYER.txt new file mode 100644 index 00000000..ec4d1984 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/MULTIPLAYER.txt @@ -0,0 +1,34 @@ +いざ!! +ALRIGHT!! / START!! +$0A6A4 +00 01 02 03 8E 8E | Original Japanese Hex +い ざ ! ! | Original Japanese Text +S T A R T ! | New English Text + +やめる +QUIT / EXIT +$0A6B5 +04 05 06 07 08 09 | Original Japanese Hex +や め る | Original Japanese Text +Q U I T ! ! | New English Text + +ばこょ +COURSE / STAGES / LEVELS +$0A6CE +0A 0B 0C 0D 0E 0F | Original Japanese Hex +ば こ ょ | Original Japanese Text +C O U R S E | New English Text + +か ちポイひト +PEOPLE VALUE / # OF CHARACTERS / SCORE TO WIN / POINTS TO WIN +$0A6D7 (Top Half) +20 21 22 23 24 25 26 27 28 29 2A 2B | Original Japanese Hex +か ち ポ イ ひ ト | Original Japanese Text +S C O R E T O W I N | New English Text + +そ らさ せってい +OPTIONS / SETTINGS / CONFIGURATION +$0A6EE +2C 2D 2E 2F 40 41 42 43 44 45 46 47 00 01 | Original Japanese Hex +そ ら さ せ っ て い | Original Japanese Text +C O N F I G U R A T I O N | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPC.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPC.txt new file mode 100644 index 00000000..3baaf239 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPC.txt @@ -0,0 +1,673 @@ +にいちゃん あんたいったい なにものだい? +Who the hell are you, huh? +$0CE93 (Line 1) +20 0C 1B 69 38 00 0B 38 1A 0C 68 1A 0C 00 1F 20 2D 23 86 0C 75 FE | Original Japanese Hex +に い ち ゃ ん あ ん た い っ た い な に も の だ い ? NEWLINE | Original Japanese Text +H u h , w h o a r e y o u ? NEWLINE W h y | New English Text +わざわざ この「からくりアイランド」に +Why have you bothered to come +$0CEA9 (Line 2) +36 81 36 81 00 14 23 77 10 31 12 32 39 3A 5F 66 9E 78 20 FD | Original Japanese Hex +わ ざ わ ざ こ の 「 か ら く り ア イ ラ ン ド 」 に NEWPAGE | Original Japanese Text +a r e y o u o n NEWPAGE " K a r a k u r i | New English Text +なにしに きたんだ? +to "Karakuri Island"? +$0CEBD (Line 3) +1F 20 16 20 00 11 1A 38 86 75 FE | Original Japanese Hex +な に し に き た ん だ ? NEWLINE | Original Japanese Text + I s l a n d " ? NEWLINE A | New English Text +そういえば あかいふくでイガグリあたまの +A guy in red clothes came by +$0CEC8 (Line 4) +19 0D 0C 0E 8B 00 0B 10 0C 26 12 89 3A 90 92 60 0B 1A 29 23 FD | Original Japanese Hex +そ う い え ば あ か い ふ く で イ ガ グ リ あ た ま の NEWPAGE | Original Japanese Text + g u y i n r e d c l o t h e s NEWPAGE c | New English Text +にいちゃんも なにしに きたのかなぁ? +I wonder what he was doing? +$0CEDD (Line 5) +20 0C 1B 69 38 2D 00 1F 20 16 20 00 11 1A 23 10 1F 67 75 FE | Original Japanese Hex +に い ち ゃ ん も な に し に き た の か な ぁ ? NEWLINE | Original Japanese Text +a m e b y , b u t I w a s i n | New English Text +すごく あわててたけど・・・・ +but I was in such a hurry... +$0CEF1 (Line 6) +17 80 12 00 0B 36 1D 1D 1A 13 8A 72 72 72 72 FF | Original Japanese Hex +す ご く あ わ て て た け ど ・ ・ ・ ・ ENDTEXT | Original Japanese Text +NEWLINE s u c h a r u s h . . . ENDTEXT | New English Text + + +めいろでまよって じかんがなくなれば +Please stay as long as you like +$0CF01 (Line 1) +2C 0C 35 89 29 30 68 1D 00 82 10 38 7C 1F 12 1F 34 8B FE | Original Japanese Hex +め い ろ で ま よ っ て じ か ん が な く な れ ば NEWLINE | Original Japanese Text +E a t a m e a l t o k e e p NEWLINE | New English Text +はしらないと しんでしまいますヨ。 +I do not mind if you are in a rush. +$0CF14 (Line 2) +24 16 31 1F 0C 1E 00 16 38 89 16 29 0C 29 17 5E 71 FF | Original Japanese Hex +は し ら な い と し ん で し ま い ま す ヨ 。 ENDTEXT | Original Japanese Text +y o u r e n e r g y h i g h . ENDTEXT | New English Text + + +なに? ゴエモン?! +What? Goemon?! +$0CF26 (Line 1) +1F 20 75 00 94 3C 5B 66 75 74 FE | Original Japanese Hex +な に ? ゴ エ モ ン ? ! NEWLINE | Original Japanese Text +W h a t ? G o e m o | New English Text +そんななまえじゃったかのお?! +I wonder if it was such a name?! +$0CF31 (Line 2) +19 38 1F 1F 29 0E 82 69 68 1A 10 23 0F 75 74 FD | Original Japanese Hex +そ ん な な ま え じ ゃ っ た か の お ? ! NEWPAGE | Original Japanese Text +n ? ! NEWLINE W a s t h a t h i s | New English Text +「からくりじょう」は どこにあるか? って +Where is "Karakuri Island"? +$0CF41 (Line 3) +77 10 31 12 32 82 6B 0D 78 24 00 8A 14 20 0B 33 10 75 00 68 1D FE | Original Japanese Hex +「 か ら く り じ ょ う 」 は ど こ に あ る か ? っ て NEWLINE | Original Japanese Text + n a m e ? ! NEWPAGE A s k i n g m e q u e s | New English Text +たずねられたが・・・いや ちがったかな??? +I was asked... I wonder what is wrong??? +$0CF57 (Line 4) +1A 83 22 31 34 1A 7C 72 72 72 0C 2E 00 1B 7C 68 1A 10 1F 75 75 75 FF | Original Japanese Hex +た ず ね ら れ た が ・ ・ ・ い や ち が っ た か な ? ? ? ENDTEXT | Original Japanese Text +t i o n s . NEWLINE I h o p e h e ' s O K ? ENDTEXT | New English Text + + +このしまは めいろ。 すべてがめいろ。 +This island is nice. It's all a maze. +$0CF6E (Line 1) +14 23 16 29 24 00 2C 0C 35 71 00 17 8E 1D 7C 00 2C 0C 35 71 FE | Original Japanese Hex +こ の し ま は め い ろ 。 す べ て が め い ろ 。 NEWLINE | Original Japanese Text +T h i s i s l a n d i s n i c e . NEWLINE | New English Text +あんた いきて かえれるかねえ? +I wonder if you can get home? +$0CF83 (Line 2) +0B 38 1A 00 0C 11 1D 00 10 0E 34 33 10 22 0E 75 FF | Original Japanese Hex +あ ん た い き て か え れ る か ね え ? ENDTEXT | Original Japanese Text +I t ' s a l l a m a z e . ENDTEXT | New English Text + + +たかいとさろに いきたいときは +If you want to go a long distance, +$0CF94 (Line 1) +1A 10 0C 1E 14 35 20 00 0C 11 1A 0C 1E 11 24 FE | Original Japanese Hex +た か い と さ ろ に い き た い と き は NEWLINE | Original Japanese Text +T o g o a l o n g w a y | New English Text +「シーソー」をつかって ジャンプすればいい。 +use "Seesaw" to jump. +$0CFA4 (Line 2) +77 44 73 47 73 78 37 1C 10 68 1D 00 96 6D 66 AB 17 34 8B 0C 0C 71 FD | Original Japanese Hex +「 シ ー ソ ー 」 を つ か っ て ジ ャ ン プ す れ ば い い 。 NEWPAGE | Original Japanese Text +NEWLINE u s e " S e e s a w " t o j u m p . NEWPAGE | New English Text +ただす、「おもり」をもっていかないと +If you do not have a "Weight" +$0CFBB (Line 3) +1A 86 16 70 77 0F 2D 32 78 37 2D 68 1D 0C 10 1F 0C 1E FE | Original Japanese Hex +た だ す 、 「 お も り 」 を も っ て い か な い と NEWLINE | Original Japanese Text +Y o u n e e d a " W e i g h t " | New English Text +「シーソー」にのっても いみは ないぞ。 +there is no point in getting on the "Seesaw". +$0CFCE (Line 4) +77 44 73 47 73 78 20 23 68 1D 2D 00 0C 2A 24 00 1F 0C 85 71 FF | Original Japanese Hex +「 シ ー ソ ー 」 に の っ て も い み は な い ぞ 。 ENDTEXT | Original Japanese Text +NEWLINE t o m a k e u s e o f o n e . ENDTEXT | New English Text + + +やじるしのむきをかえるには あかいざぶとんに +In order to change the direction of the arrow, +$0CFE3 (Line 1) +2E 82 33 16 23 2B 11 37 10 0E 33 20 24 00 0B 10 0C 81 8D 1E 38 20 FE | Original Japanese Hex +や じ る し の む き を か え る に は あ か い ざ ぶ と ん に NEWLINE | Original Japanese Text +T o c h a n g e d i r e c t i o n NEWLINE p r e | New English Text +カーソルをあわせて ボタンを おすのヨ。 +move the cursor to the red floor cushion and press the button. +$0CFFA (Line 2) +3E 73 47 61 37 0B 36 18 1D 00 A3 48 66 37 00 0F 17 23 5E 71 FF | Original Japanese Hex +カ ー ソ ル を あ わ せ て ボ タ ン を お す の ヨ 。 ENDTEXT | Original Japanese Text +s s o n t h e r e d f l o o r . ENDTEXT | New English Text + + +エジモンがつくった「にんげんたいほう」は +You can fire the "Human Cannon" created by Egymont +$0D00F (Line 1) +3C 96 5B 66 7C 1C 12 68 1A 77 20 38 7F 38 1A 0C 28 0D 78 24 FE | Original Japanese Hex +エ ジ モ ン が つ く っ た 「 に ん げ ん た い ほ う 」 は NEWLINE | Original Japanese Text +A i m t h e " H u m a n C a n n o n | New English Text +ボタンをおすタイミングによって ひきょりを +early according to the +$0D024 (Line 2) +A3 48 66 37 0F 17 48 3A 58 66 92 20 30 68 1D 00 25 11 6B 32 37 FD | Original Japanese Hex +ボ タ ン を お す タ イ ミ ン グ に よ っ て ひ き ょ り を NEWPAGE | Original Japanese Text +" NEWLINE u s i n g t i m i n g o n y o u r | New English Text +かえることが できるのじゃ!! +timing of buttons!! +$0D03A (Line 3) +10 0E 33 14 1E 7C 00 89 11 33 23 82 69 74 74 FF | Original Japanese Hex +か え る こ と が で き る の じ ゃ ! ! ENDTEXT | Original Japanese Text +NEWLINE b u t t o n p r e s s ! ! ENDTEXT | New English Text + + +エジモンがつくった「ひかりあな」に はいると +When entering a "Light Hole" created by Egymont +$0D04A (Line 1) +3C 96 5B 66 7C 1C 12 68 1A 77 25 10 32 0B 1F 78 20 00 24 0C 33 1E FE | Original Japanese Hex +エ ジ モ ン が つ く っ た 「 ひ か り あ な 」 に は い る と NEWLINE | Original Japanese Text +W h e n e n t e r i n g a " L i g h t | New English Text +ワープできるって・・・ +you can warp... +$0D061 (Line 2) +64 73 AB 89 11 33 68 1D 72 72 72 FD | Original Japanese Hex +ワ ー プ で き る っ て ・ ・ ・ NEWPAGE | Original Japanese Text +H o l e " y o u c a | New English Text +エッ? よくわからない・・・? +Me? I don't know much about it...? +$0D06D (Line 3) +3C 6C 75 00 30 12 36 10 31 1F 0C 72 72 72 75 FE | Original Japanese Hex +エ ッ ? よ く わ か ら な い ・ ・ ・ ? NEWLINE | Original Japanese Text +n w a r p . . . M e ? I | New English Text +とにかく そのあなにはいったら わかります。 +Anyway, you'll find out if you enter that hole. +$0D07D (Line 4) +1E 20 10 12 00 19 23 0B 1F 20 24 0C 68 1A 31 00 36 10 32 29 17 71 FF | Original Japanese Hex +と に か く そ の あ な に は い っ た ら わ か り ま す 。 ENDTEXT | Original Japanese Text +h a v e n o t t r i e d m y s e l f . ENDTEXT | New English Text + + +めいろのなかには わるいからくりロボが +In the maze there is a bad scolding robot, +$0D094 (Line 1) +2C 0C 35 23 1F 10 20 24 00 36 33 0C 10 31 12 32 63 A3 7C FE | Original Japanese Hex +め い ろ の な か に は わ る い か ら く り ロ ボ が NEWLINE | Original Japanese Text +W a t c h o u t f o r t h e b a d | New English Text +うろうろしているから ちゅういしろよ。 +be careful as you are wandering around. +$0D0A8 (Line 2) +0D 35 0D 35 16 1D 0C 33 10 31 00 1B 6A 0D 0C 16 35 30 71 FF | Original Japanese Hex +う ろ う ろ し て い る か ら ち ゅ う い し ろ よ 。 ENDTEXT | Original Japanese Text +NEWLINE r o b o t i n t h e m a z e . ENDTEXT | New English Text + + +わたし 「だじゃれ」ひとすじ40ねん。 +I am 40 years old "Pay attention". +$0D0BC (Line 1) +36 1A 16 00 77 86 82 69 34 78 25 1E 17 82 05 01 22 38 71 FE | Original Japanese Hex +わ た し 「 だ じ ゃ れ 」 ひ と す じ 4 0 ね ん 。 NEWLINE | Original Japanese Text +I a m 4 0 y e a r s o l d . NEWLINE I | New English Text +おもしろい「だじゃれ」かんがえたあるね。 +I have an interesting "Way" of thinking. +$0D0D0 (Line 2) +0F 2D 16 35 0C 77 86 82 69 34 78 10 38 7C 0E 1A 0B 33 22 71 FD | Original Japanese Hex +お も し ろ い 「 だ じ ゃ れ 」 か ん が え た あ る ね 。 NEWPAGE | Original Japanese Text + h a v e g r e a t " i d e a s " . NEWPAGE | New English Text +どうじょうへ どうじょ。 +How about you? +$0D0E5 (Line 3) +8A 0D 82 6B 0D 27 00 8A 0D 82 6B 71 FE | Original Japanese Hex +ど う じ ょ う へ ど う じ ょ 。 NEWLINE | Original Japanese Text +H o w a r e y o u ? NEWLINE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D0F2 (Line 4) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FD | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | New English Text +うむ、うこないあるか。 これならどうあるか? +Ah, there is a problem. How is this? +$0D109 (Line 5) +0D 2B 70 0D 13 1F 0C 0B 33 10 71 00 14 34 1F 31 8A 0D 0B 33 10 75 FE | Original Japanese Hex +う む 、 う こ な い あ る か 。 こ れ な ら ど う あ る か ? NEWLINE | Original Japanese Text +A h , t h e r e ' s a p r o b l e m ? NEWLINE | New English Text +でんわをかけても だれもでんわ +Even if you make a phone call, no one will help. +$0D120 (Line 6) +89 38 36 37 10 13 1D 2D 00 86 34 2D 89 38 36 FD | Original Japanese Hex +で ん わ を か け て も だ れ も で ん わ NEWPAGE | Original Japanese Text +Y o u n e e d h e l p ? NEWPAGE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D130 (Line 7) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FE | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D147 (Line 8) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FD | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | New English Text +うむ、だめあるか。 これはどうあるか? +Well, are you useless? How is this? +$0D15E (Line 9) +0D 2B 70 86 2C 0B 33 10 71 00 14 34 24 8A 0D 0B 33 10 75 FE | Original Japanese Hex +う む 、 だ め あ る か 。 こ れ は ど う あ る か ? NEWLINE | Original Japanese Text +H o w c o m e ? A r e y o u NEWLINE a l | New English Text +ふとんが ふっとんだー +Are you stuck? +$0D172 (Line 10) +26 1E 38 7C 00 26 68 1E 38 86 73 FD | Original Japanese Hex +ふ と ん が ふ っ と ん だ ー NEWPAGE | Original Japanese Text +r e a d y l o s t ? NEWPAGE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D17E (Line 11) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FE | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D195 (Line 12) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FD | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | New English Text +うむ、うけないあるか。 これならどうあるか? +Well, that is not right? How is this? +$0D1AC (Line 13) +0D 2B 70 0D 13 1F 0C 0B 33 10 71 00 14 34 1F 31 8A 0D 0B 33 10 75 FE | Original Japanese Hex +う む 、 う け な い あ る か 。 こ れ な ら ど う あ る か ? NEWLINE | Original Japanese Text +H o w i s t h i s ? Y o u n e e d NEWLINE t | New English Text +メガネをとったら めがねー! +You might need glasses! +$0D1C3 (Line 14) +5A 90 50 37 1E 68 1A 31 00 2C 7C 22 73 74 FD | Original Japanese Hex +メ ガ ネ を と っ た ら め が ね ー ! NEWPAGE | Original Japanese Text +o l o o k h a r d e r ! NEWPAGE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D1D2 (Line 15) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FE | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D1E9 (Line 16) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FD | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | New English Text +うむ、では これならどうあるか? +Well, then how is this possible? +$0D200 (Line 17) +0D 2B 70 89 24 00 14 34 1F 31 8A 0D 0B 33 10 75 FE | Original Japanese Hex +う む 、 で は こ れ な ら ど う あ る か ? NEWLINE | Original Japanese Text +H o w i s t h i s s o ? NEWLINE S | New English Text +そのステッキ、すてき。 +A nice guy like you, in a sticky situation. +$0D211 (Line 18) +19 23 45 4B 6C 3F 70 17 1D 11 71 FD | Original Japanese Hex +そ の ス テ ッ キ 、 す て き 。 NEWPAGE | Original Japanese Text +u c h a p i t y . NEWPAGE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D21D (Line 19) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FE | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWLINE | New English Text +・・・・・・・・・・・・・・・・・・・・・・ +...................... +$0D234 (Line 20) +72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 72 FD | Original Japanese Hex +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ ・ NEWPAGE | New English Text +そんなつまんない だじゃれをいったのは +Is not it such a boring funny thing +$0D24B (Line 21) +19 38 1F 1C 29 38 1F 0C 00 86 82 69 34 37 0C 68 1A 23 24 FE | Original Japanese Hex +そ ん な つ ま ん な い だ じ ゃ れ を い っ た の は NEWLINE | Original Japanese Text +D o y o u t h i n k I ' m NEWLINE s t r | New English Text +だじゃれ? +to say? +$0D25F (Line 22) +86 82 69 34 75 FF | Original Japanese Hex +だ じ ゃ れ ? ENDTEXT | Original Japanese Text +a n g e ? ENDTEXT | New English Text + + +てきを いっきにたおすには +To defeat all enemies at once +$0D265 (Line 1) +1D 11 37 00 0C 68 11 20 1A 0F 17 20 24 FE | Original Japanese Hex +て き を い っ き に た お す に は NEWLINE | Original Japanese Text +U s e t h e s p r i n g | New English Text +バネのちからを りようしろよ。 +use the power of the spring. +$0D273 (Line 2) +9F 50 23 1B 10 31 37 00 32 30 0D 16 35 30 71 FD | Original Japanese Hex +バ ネ の ち か ら を り よ う し ろ よ 。 NEWPAGE | Original Japanese Text + t o NEWLINE d e f e a t e n e m i | New English Text +ただし、 かそくがつくから、 +However, because the stick is accelerating, +$0D283 (Line 3) +1A 86 16 70 00 10 19 12 7C 1C 12 10 31 70 FE | Original Japanese Hex +た だ し 、 か そ く が つ く か ら 、 NEWLINE | Original Japanese Text +e s . NEWPAGE H o w e v e r , i t | New English Text +じぶんの いきさきを さだめていないと +I must say do not forget that +$0D292 (Line 4) +82 8D 38 23 00 0C 11 15 11 37 00 15 86 2C 1D 0C 1F 0C 1E FD | Original Japanese Hex +じ ぶ ん の い き さ き を さ だ め て い な い と NEWPAGE | Original Japanese Text +NEWLINE a c c e l e r a t e s y o u r s p | New English Text +あぶないぞ! ちゅういがひつようだ!! +it is dangerous! Take your time!! +$0D2A6 (Line 5) +0B 8D 1F 0C 85 74 00 1B 6A 0D 0C 7C 25 1C 30 0D 86 74 74 FE | Original Japanese Hex +あ ぶ な い ぞ ! ち ゅ う い が ひ つ よ う だ ! ! NEWLINE | Original Japanese Text +e e d NEWPAGE d a n g e r o u s l y ! NEWLINE T a k | New English Text +よくかんがえて つかえよ!!! +Take care when using it!!! +$0D2BA (Line 6) +30 12 10 38 7C 0E 1D 00 1C 10 0E 30 74 74 74 FF | Original Japanese Hex +よ く か ん が え て つ か え よ ! ! ! ENDTEXT | Original Japanese Text +e c a r e w i t h i t ! ENDTEXT | New English Text + + +あんた ほんものの にんげんだね?! +You're a real person, aren't you?! +$0D2CA (Line 1) +0B 38 1A 00 28 38 2D 23 23 00 20 38 7F 38 86 22 75 74 FE | Original Japanese Hex +あ ん た ほ ん も の の に ん げ ん だ ね ? ! NEWLINE | Original Japanese Text +Y o u ' r e a r e a l p e r s o | New English Text +ここは あんたのようなにんげんの +This is not the place to come for +$0D2DD (Line 2) +14 14 24 00 0B 38 1A 23 30 0D 1F 20 38 7F 38 23 FD | Original Japanese Hex +こ こ は あ ん た の よ う な に ん げ ん の NEWPAGE | Original Japanese Text +n ? ! NEWLINE T h i s i s n o p l | New English Text +くるところじゃないよ。 +people like you. +$0D2EE (Line 3) +12 33 1E 14 35 82 69 1F 0C 30 71 FE | Original Japanese Hex +く る と こ ろ じ ゃ な い よ 。 NEWLINE | Original Japanese Text +a c e f o r NEWPAGE y o u . | New English Text +いったい なにしに きたんだい? +What do you want to do? +$0D2FA (Line 4) +0C 68 1A 0C 00 1F 20 16 20 00 11 1A 38 86 0C 75 FF | Original Japanese Hex +い っ た い な に し に き た ん だ い ? ENDTEXT | Original Japanese Text +NEWLINE W h y v i s i t h e r e ? ENDTEXT | New English Text + + +エッ なんですって?? おなかすいたって!? +What is it?? I am hungry!? +$0D30B (Line 1) +3C 6C 00 1F 38 89 17 68 1D 75 75 00 0F 1F 10 17 0C 1A 68 1D 74 75 FE | Original Japanese Hex +エ ッ な ん で す っ て ? ? お な か す い た っ て ! ? NEWLINE | Original Japanese Text +W h a t ? ? I ' m h u n g r y ! ? NEWLINE I d | New English Text +ここには たべものなんて うってないわよ。 +I do not sell any food here. +$0D322 (Line 2) +14 14 20 24 00 1A 8E 2D 23 1F 38 1D 00 0D 68 1D 1F 0C 36 30 71 FD | Original Japanese Hex +こ こ に は た べ も の な ん て う っ て な い わ よ 。 NEWPAGE | Original Japanese Text +o n ' t h a v e f o o d . NEWPAGE T h e r e | New English Text +よろずやにいけば なにかうってるかもネ。 +There might be some if you go to a shop. +$0D338 (Line 3) +30 35 83 2E 20 0C 13 8B 00 1F 20 10 0D 68 1D 33 10 2D 50 71 FE | Original Japanese Hex +よ ろ ず や に い け ば な に か う っ て る か も ネ 。 NEWLINE | Original Japanese Text +m i g h t b e a s h o p . NEWLINE B u t | New English Text +でも 「からくりじょう」に たべものを +However, in "Karakuri" +$0D34D (Line 4) +89 2D 00 77 10 31 12 32 82 6B 0D 78 20 00 1A 8E 2D 23 37 FD | Original Japanese Hex +で も 「 か ら く り じ ょ う 」 に た べ も の を NEWPAGE | Original Japanese Text +i n " K a r a k u r i " NEWPAGE I ' v e n | New English Text +はこびこんでるのを みたことあるわ。 +I have not seen any food. +$0D361 (Line 5) +24 14 8C 14 38 89 33 23 37 00 2A 1A 14 1E 0B 33 36 71 FE | Original Japanese Hex +は こ び こ ん で る の を み た こ と あ る わ 。 NEWLINE | Original Japanese Text +o t s e e n a n y f o o d . NEWLINE I | New English Text +にんげんが いるのかなぁ? +I wonder if there is a reason? +$0D374 (Line 6) +20 38 7F 38 7C 00 0C 33 23 10 1F 67 75 FF | Original Japanese Hex +に ん げ ん が い る の か な ぁ ? ENDTEXT | Original Japanese Text + w o n d e r w h y ? ? ENDTEXT | New English Text + + +このさきのみせには エジモンがつくった +The shop next door +$0D382 (Line 1) +14 23 15 11 23 2A 18 20 24 00 3C 96 5B 66 7C 1C 12 68 1A FE | Original Japanese Hex +こ の さ き の み せ に は エ ジ モ ン が つ く っ た NEWLINE | Original Japanese Text +T h e s h o p n e x t d o o r h | New English Text +スロットマシーンとかいう きかいがある。 +has a slot machine made by Ejimon. +$0D396 (Line 2) +45 63 6C 4C 57 44 73 66 1E 10 0C 0D 00 11 10 0C 7C 0B 33 71 FD | Original Japanese Hex +ス ロ ッ ト マ シ ー ン と か い う き か い が あ る 。 NEWPAGE | Original Japanese Text +a s NEWLINE a b i g s l o t m a c h i n e | New English Text +わしには よくわからんが、 +I do not know myself, +$0D3AB (Line 3) +36 16 20 24 00 30 12 36 10 31 38 7C 70 FE | Original Japanese Hex +わ し に は よ く わ か ら ん が 、 NEWLINE | Original Japanese Text +. NEWPAGE I d o n ' t k n o w | New English Text +なにやら えがらを ねらってとめると +but I think you can win +$0D3B9 (Line 4) +1F 20 2E 31 00 0E 7C 31 37 00 22 31 68 1D 1E 2C 33 1E FD | Original Japanese Hex +な に や ら え が ら を ね ら っ て と め る と NEWPAGE | Original Japanese Text + m y s e l f , NEWLINE b u t I h e a r | New English Text +おかねが もうかるそうじゃ。 +money if you get a pattern. +$0D3CC (Line 5) +0F 10 22 7C 00 2D 0D 10 33 19 0D 82 69 71 FE | Original Japanese Hex +お か ね が も う か る そ う じ ゃ 。 NEWLINE | Original Japanese Text +d y o u w i n NEWPAGE m o n e y | New English Text +わしのしっとるおとこは 777がそろって +I heard the jackpot +$0D3DB (Line 6) +36 16 23 16 68 1E 33 0F 1E 14 24 00 08 08 08 7C 19 35 68 1D FD | Original Japanese Hex +わ し の し っ と る お と こ は 7 7 7 が そ ろ っ て NEWPAGE | Original Japanese Text + b y m a t c h i n g t h e s y m b | New English Text +こしを ぬかしおった。 +can be won with 777. +$0D3F0 (Line 7) +14 16 37 00 21 10 16 0F 68 1A 71 FE | Original Japanese Hex +こ し を ぬ か し お っ た 。 NEWLINE | Original Japanese Text +o l s . NEWLINE A l s o t h | New English Text +うんがよかったのか わるかったのか・・・・・ +Will you get lucky?..... +$0D3FC (Line 8) +0D 38 7C 30 10 68 1A 23 10 00 36 33 10 68 1A 23 10 72 72 72 72 72 FD | Original Japanese Hex +う ん が よ か っ た の か わ る か っ た の か ・ ・ ・ ・ ・ NEWPAGE | Original Japanese Text +e j a c k p o t NEWPAGE c a n b e w o n w i | New English Text +なんなら おわかいの、うんだめしに +Anyway it's stupid, I'd rather +$0D413 (Line 9) +1F 38 1F 31 00 0F 36 10 0C 23 70 0D 38 86 2C 16 20 FE | Original Japanese Hex +な ん な ら お わ か い の 、 う ん だ め し に NEWLINE | Original Japanese Text +t h 7 7 7 . NEWLINE W i l l y o u g | New English Text +いってみたらどうじゃな。 +have a bowl of fish. +$0D425 (Line 10) +0C 68 1D 2A 1A 31 8A 0D 82 69 1F 71 FF | Original Japanese Hex +い っ て み た ら ど う じ ゃ な 。 ENDTEXT | Original Japanese Text +e t l u c k y ? . . . ENDTEXT | New English Text + + +おかねがあったら とせんやで ふねにのって +If you have money, please +$0D432 (Line 1) +0F 10 22 7C 0B 68 1A 31 00 1E 18 38 2E 89 00 26 22 20 23 68 1D FE | Original Japanese Hex +お か ね が あ っ た ら と せ ん や で ふ ね に の っ て NEWLINE | Original Japanese Text +I f y o u h a v e a n y m o n e y , | New English Text +はなれこじまに いってみな。 +try to go next door. +$0D448 (Line 2) +24 1F 34 14 82 29 20 00 0C 68 1D 2A 1F 71 FD | Original Japanese Hex +は な れ こ じ ま に い っ て み な 。 NEWPAGE | Original Japanese Text +NEWLINE t r y t o g o n e x t | New English Text +うわさによると、むかし「からくりいちぞく」が +According to the rumor, it seems that he is back +$0D457 (Line 3) +0D 36 15 20 30 33 1E 70 2B 10 16 77 10 31 12 32 0C 1B 85 12 78 7C FE | Original Japanese Hex +う わ さ に よ る と 、 む か し 「 か ら く り い ち ぞ く 」 が NEWLINE | Original Japanese Text + d o o r . NEWPAGE H e i s n o w b a c k a | New English Text +かくした ざいほうが ねむっているらしいぞ。 +after a long absence from "Karakuri Island". +$0D46E (Line 4) +10 12 16 1A 00 81 0C 28 0D 7C 00 22 2B 68 1D 0C 33 31 16 0C 85 71 FF | Original Japanese Hex +か く し た ざ い ほ う が ね む っ て い る ら し い ぞ 。 ENDTEXT | Original Japanese Text +f t e r a NEWLINE l o n g t i m e a w a y . ENDTEXT | New English Text + + +ちょっとちょっと にいさん。 きいた? +Hey brother. Have you heard? +$0D485 (Line 1) +1B 6B 68 1E 1B 6B 68 1E 00 20 0C 15 38 71 00 11 0C 1A 75 FE | Original Japanese Hex +ち ょ っ と ち ょ っ と に い さ ん 。 き い た ? NEWLINE | Original Japanese Text +H e y . H a v e y o u h e a r d ? | New English Text +さのさきには 「ボーナスステージ」があって、 +There is a "bonus stage" in the morning, +$0D499 (Line 2) +14 23 15 11 20 24 00 77 A3 73 4D 45 45 4B 73 96 78 7C 0B 68 1D 70 FD | Original Japanese Hex +さ の さ き に は 「 ボ ー ナ ス ス テ ー ジ 」 が あ っ て 、 NEWPAGE | Original Japanese Text +NEWLINE A " B o n u s S t a g e " b e c a m e | New English Text +おかねをたくさんあつめられるそうよ。 +I hear that you can collect a lot of money. +$0D4B0 (Line 3) +0F 10 22 37 1A 12 15 38 0B 1C 2C 31 34 33 19 0D 30 71 FE | Original Japanese Hex +お か ね を た く さ ん あ つ め ら れ る そ う よ 。 NEWLINE | Original Japanese Text +NEWPAGE a v a i l a b l e , i n t h e | New English Text +いいもうけばなしと おもわない? +Do you think that it is a good story? +$0D4C3 (Line 4) +0C 0C 2D 0D 13 8B 1F 16 1E 00 0F 2D 36 1F 0C 75 FD | Original Japanese Hex +い い も う け ば な し と お も わ な い ? NEWPAGE | Original Japanese Text +d a y . NEWLINE I h e a r y o u c | New English Text +ただし、せいげんじかんが あるらしいから +However, it appeared a few days ago, +$0D4D4 (Line 5) +1A 86 16 70 18 0C 7F 38 82 10 38 7C 00 0B 33 31 16 0C 10 31 FE | Original Japanese Hex +た だ し 、 せ い げ ん じ か ん が あ る ら し い か ら NEWLINE | Original Japanese Text +a n c o l l e c t NEWPAGE a l o t o f g | New English Text +どれだけあつめられるかは、にいさんの +so how much can be gathered depends +$0D4E9 (Line 6) +8A 34 86 13 0B 1C 2C 31 34 33 10 24 70 20 0C 15 38 23 FD | Original Japanese Hex +ど れ だ け あ つ め ら れ る か は 、 に い さ ん の NEWPAGE | Original Japanese Text +o l d . NEWLINE A r e y o u i n t e r e | New English Text +うでしだいだネ。がんばっといで・・・ +on how many people have been there already. Good luck... +$0D4FC (Line 7) +0D 89 16 86 0C 86 50 71 7C 38 8B 68 1E 0C 89 72 72 72 FF | Original Japanese Hex +う で し だ い だ ネ 。 が ん ば っ と い で ・ ・ ・ ENDTEXT | Original Japanese Text +s t e d ? NEWPAGE G o o d l u c k . . . ENDTEXT | New English Text + + +めいろのなかにいる わるいからくりロボは +The bad robots in the maze +$0D50F (Line 1) +2C 0C 35 23 1F 10 20 0C 33 00 36 33 0C 10 31 12 32 63 A3 24 FE | Original Japanese Hex +め い ろ の な か に い る わ る い か ら く り ロ ボ は NEWLINE | Original Japanese Text +B a d r o b o t s i n t h e m a z | New English Text +じぶんで スイッチをふんで しかけを +can step on switches +$0D524 (Line 2) +82 8D 38 89 00 45 3A 6C 49 37 26 38 89 00 16 10 13 37 FD | Original Japanese Hex +じ ぶ ん で ス イ ッ チ を ふ ん で し か け を NEWPAGE | Original Japanese Text +e NEWLINE c a n s t e p o n s w i t c | New English Text +さどうさせるから ちゅういがひつようじゃ。 +if you time it right. +$0D537 (Line 3) +15 8A 0D 15 18 33 10 31 00 1B 6A 0D 0C 7C 25 1C 30 0D 82 69 71 FE | Original Japanese Hex +さ ど う さ せ る か ら ち ゅ う い が ひ つ よ う じ ゃ 。 NEWLINE | Original Japanese Text +h e s , NEWLINE i f y o u t i m e i t w e | New English Text +そうじゃ! あぶないところにある スイッチを +That's right! If a switch is in a dangerous place +$0D54D (Line 4) +19 0D 82 69 74 00 0B 8D 1F 0C 1E 14 35 20 0B 33 00 45 3A 6C 49 37 FD | Original Japanese Hex +そ う じ ゃ ! あ ぶ な い と こ ろ に あ る ス イ ッ チ を NEWPAGE | Original Japanese Text +l l . NEWLINE T h a t ' s r i g h t ! I f i t | New English Text +ふみたいときは ぎゃくに あいつらに +you can use the robot +$0D564 (Line 5) +26 2A 1A 0C 1E 11 24 00 7D 69 12 20 00 0B 0C 1C 31 20 FE | Original Japanese Hex +ふ み た い と き は ぎ ゃ く に あ い つ ら に NEWLINE | Original Japanese Text + i s NEWPAGE i n a d a n g e r o u s | New English Text +ふみに いかせれば あんぜんじゃのう!! +to press it!! +$0D577 (Line 6) +26 2A 20 00 0C 10 18 34 8B 00 0B 38 84 38 82 69 23 0D 74 74 FF | Original Japanese Hex +ふ み に い か せ れ ば あ ん ぜ ん じ ゃ の う ! ! ENDTEXT | Original Japanese Text +p l a c e , NEWLINE u s e a r o b o t ! ! ENDTEXT | New English Text + + +さいきん よるになると このあたりに +Recently at night around here +$0D58C (Line 1) +15 0C 11 38 00 30 33 20 1F 33 1E 00 14 23 0B 1A 32 20 FE | Original Japanese Hex +さ い き ん よ る に な る と こ の あ た り に NEWLINE | Original Japanese Text +R e c e n t l y a t n i g h t , | New English Text +きょだいな すもうとりの からくりロボが +a bad robot appears, +$0D59F (Line 2) +11 6B 86 0C 1F 00 17 2D 0D 1E 32 23 00 10 31 12 32 63 A3 7C FD | Original Japanese Hex +き ょ だ い な す も う と り の か ら く り ロ ボ が NEWPAGE | Original Japanese Text +a NEWLINE b a d r o b o t h a s s h o w n | New English Text +あらわれて まちを あらしてこまってるの。 +and it shows up in the town. +$0D5B4 (Line 3) +0B 31 36 34 1D 00 29 1B 37 00 0B 31 16 1D 14 29 68 1D 33 23 71 FE | Original Japanese Hex +あ ら わ れ て ま ち を あ ら し て こ ま っ て る の 。 NEWLINE | Original Japanese Text + u p NEWPAGE i n t o w n . Y o u ' l l f i | New English Text +おにいさんも きをつけたほうが いいですよ。 +You will get into trouble by yourself. +You'll find it hard on your own. +$0D5CA (Line 4) +0F 20 0C 15 38 2D 00 11 37 1C 13 1A 28 0D 7C 00 0C 0C 89 17 30 71 FD | Original Japanese Hex +お に い さ ん も き を つ け た ほ う が い い で す よ 。 NEWPAGE | Original Japanese Text +n d NEWLINE i t h a r d o n y o u r o w n . | New English Text +エッ? たいじしてくれるって!? +What? You say you can handle it!? +$0D5E1 (Line 5) +3C 6C 75 00 1A 0C 82 16 1D 12 34 33 68 1D 74 75 FE | Original Japanese Hex +エ ッ ? た い じ し て く れ る っ て ! ? NEWLINE | Original Japanese Text +NEWPAGE W h a t ? Y o u c a n h a | New English Text +それは うれしいけど おにいさん ほんとうに +I am happy you think so +$0D5F2 (Line 6) +19 34 24 00 0D 34 16 0C 13 8A 00 0F 20 0C 15 38 00 28 38 1E 0D 20 FD | Original Japanese Hex +そ れ は う れ し い け ど お に い さ ん ほ ん と う に NEWPAGE | Original Japanese Text +n d l e NEWLINE i t ! ? A r e y o u l u c k y | New English Text +だいじょうぶですか? +but are you really lucky? +$0D609 (Line 7) +86 0C 82 6B 0D 8D 89 17 10 75 FE | Original Japanese Hex +だ い じ ょ う ぶ で す か ? NEWLINE | Original Japanese Text +? NEWPAGE T r y t o d o | New English Text +あいては やじるしを むしして すすむのよ。 +Just ignore the arrows to win. +$0D614 (Line 8) +0B 0C 1D 24 00 2E 82 33 16 37 00 2B 16 16 1D 00 17 17 2B 23 30 71 FF | Original Japanese Hex +あ い て は や じ る し を む し し て す す む の よ 。 ENDTEXT | Original Japanese Text +d g e t h e a r r o w s NEWLINE t o w i n . ENDTEXT | New English Text + + +ほんとうに はらのたつ「すもうロボ」だ!! +Coming up is a "Sumo Robo"!! +$0D62B (Line 1) +28 38 1E 0D 20 00 24 31 23 1A 1C 77 17 2D 0D 63 A3 78 86 74 74 FE | Original Japanese Hex +ほ ん と う に は ら の た つ 「 す も う ロ ボ 」 だ ! ! NEWLINE | Original Japanese Text +A h e a d i s " S u m o R o b o " ! ! | New English Text +イヌの「うんち」でもふんで こわれてしまえ。 +Stop it with a dog's "Poop" to break it. +$0D641 (Line 2) +3A 4F 23 77 0D 38 1B 78 89 2D 26 38 89 00 14 36 34 1D 16 29 0E 71 FD | Original Japanese Hex +イ ヌ の 「 う ん ち 」 で も ふ ん で こ わ れ て し ま え 。 NEWPAGE | Original Japanese Text +NEWLINE S t o p i t w i t h " D o g P o o " . | New English Text +にいさんも イヌの「うんち」を +Be careful not to tread in +$0D658 (Line 3) +20 0C 15 38 2D 00 3A 4F 23 77 0D 38 1B 78 37 FE | Original Japanese Hex +に い さ ん も イ ヌ の 「 う ん ち 」 を NEWLINE | Original Japanese Text +NEWPAGE T r y n o t t o s t e p | New English Text +ふまないように きをつけろよ!! +the dog's "Poop" yourself!! +$0D668 (Line 4) +26 29 1F 0C 30 0D 20 00 11 37 1C 13 35 30 74 74 FF | Original Japanese Hex +ふ ま な い よ う に き を つ け ろ よ ! ! ENDTEXT | Original Japanese Text + o n i t NEWLINE y o u r s e l f ! ENDTEXT | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCSHOP.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCSHOP.txt new file mode 100644 index 00000000..8d7e0350 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCSHOP.txt @@ -0,0 +1,214 @@ +いらっしゃいませ。 +Welcome. +$0C9D6 (Line 1) +0C 31 68 16 69 0C 29 18 71 FE | Original Japanese Hex +い ら っ し ゃ い ま せ 。 NEWLINE | Original Japanese Text +W e l c o m e . NEWLINE H | New English Text +なにか おもとめですか? +What do you seek? / How may I help? / Are you looking for something? +$0C9E0 (Line 2) +1F 20 10 00 0F 2D 1E 2C 89 17 10 75 FD | Original Japanese Hex +な に か お も と め で す か ? NEWPAGE | Original Japanese Text +o w m a y I h e l p | New English Text +ただし、アイテムは 1つしか もてません。 +However, you can only hold 1 item. +$0C9ED (Line 3) +1A 86 16 70 39 3A 4B 59 24 00 02 1C 16 10 00 2D 1D 29 18 38 71 FF | Original Japanese Hex +た だ し 、 ア イ テ ム は 1 つ し か も て ま せ ん 。 ENDTEXT | Original Japanese Text +? NEWPAGE Y o u c a n h o l d 1 i t e m ENDTEXT | New English Text + + +よろいです。300両になります。 +This is armor. It will be $300. +$0CA03 (Line 1) +30 35 0C 89 17 71 04 01 01 79 20 1F 32 29 17 71 FE | Original Japanese Hex +よ ろ い で す 。 3 0 0 両 に な り ま す 。 NEWLINE | Original Japanese Text +A r m o r . P r i c e $ 3 0 0 | New English Text +てきに あたっても だいじょうぶですよ。 +It is safe to hit the enemy. +$0CA14 (Line 2) +1D 11 20 00 0B 1A 68 1D 2D 00 86 0C 82 6B 0D 8D 89 17 30 71 FF | Original Japanese Hex +て き に あ た っ て も だ い じ ょ う ぶ で す よ 。 ENDTEXT | Original Japanese Text +. NEWLINE T a k e s 1 e n e m y h i t . ENDTEXT | New English Text + + +とけいです。500両になります。 +This is a clock. It will be $500. +$0CA29 (Line 1) +1E 13 0C 89 17 71 06 01 01 79 20 1F 32 29 17 71 FE | Original Japanese Hex +と け い で す 。 5 0 0 両 に な り ま す 。 NEWLINE | Original Japanese Text +C l o c k . P r i c e $ 5 0 0 | New English Text +タイムがなくなっても たすかりますよ。 +Survive even if you run out of time. +$0CA3A (Line 2) +48 3A 59 7C 1F 12 1F 68 1D 2D 00 1A 17 10 32 29 17 30 71 FF | Original Japanese Hex +タ イ ム が な く な っ て も た す か り ま す よ 。 ENDTEXT | Original Japanese Text +. NEWLINE G i v e s e x t r a t i m e . ENDTEXT | New English Text + + +1UPです。800両になります。 +This is a 1UP. It will be $800. +$0CA4E (Line 1) +02 7A 7B 89 17 71 09 01 01 79 20 1F 32 29 17 71 FE | Original Japanese Hex +1 U P で す 。 8 0 0 両 に な り ま す 。 NEWLINE | Original Japanese Text +1 U P . P r i c e $ 8 0 0 . NEWLINE | New English Text +プレイヤーが ひとりふえます。 +There will be more players. +$0CA5F (Line 2) +AB 62 3A 5C 73 7C 00 25 1E 32 26 0E 29 17 71 FF | Original Japanese Hex +プ レ イ ヤ ー が ひ と り ふ え ま す 。 ENDTEXT | Original Japanese Text +A d d e x t r a l i f e . ENDTEXT | New English Text + + +おかいに なりますか? +Would you mind making it? +$0CA6F (Line 1) +0F 10 0C 20 00 1F 32 29 17 10 75 FE | Original Japanese Hex +お か い に な り ま す か ? NEWLINE | Original Japanese Text +I s t h i s O K ? NEWLINE | New English Text +はい いいえ +Yes No +$0CA7B (Line 2) +00 00 00 00 00 00 24 0C 00 00 00 00 00 0C 0C 0E FF | Original Japanese Hex + は い い い え ENDTEXT | Original Japanese Text + Y e s N o ENDTEXT | New English Text + + +ありがとうございました。 +Thank you very much. +$0CA8C +0B 32 7C 1E 0D 80 81 0C 29 16 1A 71 FF | Original Japanese Hex +あ り が と う ご ざ い ま し た 。 ENDTEXT | Original Japanese Text +T h a n k y o u . ENDTEXT | New English Text + + +あんた おかねが たりないよ! +You do not have enough money! / Can not afford! / Need more gold! +$0CA99 +0B 38 1A 00 0F 10 22 7C 00 1A 32 1F 0C 30 74 FF | Original Japanese Hex +あ ん た お か ね が た り な い よ ! ENDTEXT | Original Japanese Text +N e e d m o r e g o l d ! ENDTEXT | New English Text + + +ひやかしは おことわりです。 +A truly memorable service. +$0CAA9 +25 2E 10 16 24 00 0F 14 1E 36 32 89 17 71 FF | Original Japanese Hex +ひ や か し は お こ と わ り で す 。 ENDTEXT | Original Japanese Text +V i s i t a n y t i m e . ENDTEXT | New English Text + + + + +ようこそ いらっしゃいました。 +Welcome. +$0CC38 (Line 1) +30 0D 14 19 00 0C 31 68 16 69 0C 29 16 1A 71 FE | Original Japanese Hex +よ う こ そ い ら っ し ゃ い ま し た 。 NEWLINE | Original Japanese Text +W e l c o m e . S l o t m a | New English Text +スロットマシーン 1プレイ 5両です。 +Slot machine 1 play is $5. +$0CC48 (Line 2) +45 63 6C 4C 57 44 73 66 00 02 AB 62 3A 00 06 79 89 17 71 FD | Original Japanese Hex +ス ロ ッ ト マ シ ー ン 1 プ レ イ 5 両 で す 。 NEWPAGE | Original Japanese Text +c h i n e NEWLINE 1 p l a y $ 5 . NEWPAGE R u l | New English Text +なぁに ルールは かんたんですよ。 +Hey, the rules are simple. +$0CC5C (Line 3) +1F 67 20 00 61 73 61 24 00 10 38 1A 38 89 17 30 71 FE | Original Japanese Hex +な ぁ に ル ー ル は か ん た ん で す よ 。 NEWLINE | Original Japanese Text +e s a r e s i m p l e . P u s | New English Text +ボタンをおして ドラムをとめるだけです。 +Just push the button to stop the drum. +$0CC6E (Line 4) +A3 48 66 37 0F 16 1D 00 9E 5F 59 37 1E 2C 33 86 13 89 17 71 FD | Original Japanese Hex +ボ タ ン を お し て ド ラ ム を と め る だ け で す 。 NEWPAGE | Original Japanese Text +h NEWLINE b u t t o n s t o p s d r u m . NEWPAGE | New English Text +えがらがそろえば コバンがもらえます。 +If the pattern is aligned, you get a prize. +$0CC83 (Line 5) +0E 7C 31 7C 19 35 0E 8B 00 42 9F 66 7C 2D 31 0E 29 17 71 FD | Original Japanese Hex +え が ら が そ ろ え ば コ バ ン が も ら え ま す 。 NEWPAGE | Original Japanese Text +M a t c h s y m b o l s t o w i n | New English Text +どうなさいます? +What would you like todo? +$0CC97 (Line 6) +8A 0D 1F 15 0C 29 17 75 FE | Original Japanese Hex +ど う な さ い ま す ? NEWLINE | Original Japanese Text +. NEWPAGE P l a y ? NEWLINE | New English Text +やる やめる +Play Quit +$0CCA0 (Line 7) +00 00 00 00 00 00 2E 33 00 00 00 00 00 2E 2C 33 FF | Original Japanese Hex + や る や め る ENDTEXT | Original Japanese Text + P l a y Q u i t ENDTEXT | New English Text + + +ハズレです。 +You lost. +$0CCB1 +52 97 62 89 17 71 FF | Original Japanese Hex +ハ ズ レ で す 。 ENDTEXT | Original Japanese Text +N o W i n ENDTEXT | New English Text + + +スリーセブン!! コバン 500まい。 +Three Seven!! It's 500 coins. +$0CCB8 +45 60 73 46 A1 66 74 74 00 00 42 9F 66 00 06 01 01 29 0C 71 FF | Original Japanese Hex +ス リ ー セ ブ ン ! ! コ バ ン 5 0 0 ま い 。 ENDTEXT | Original Japanese Text +7 7 7 ! ! Y o u w i n $ 5 0 0 . ENDTEXT | New English Text + + +さくらんぼ!! コバン 10まい。 +Cherries!! It's 10 coins. +$0CCCD +15 12 31 38 8F 74 74 00 00 42 9F 66 00 02 01 29 0C 71 FF | Original Japanese Hex +さ く ら ん ぼ ! ! コ バ ン 1 0 ま い 。 ENDTEXT | Original Japanese Text +C h e r r i e s ! W i n $ 1 0 . ENDTEXT | New English Text + + +すず!! コバン 15まい。 +Bells!! It's 15 coins. +$0CCE0 +17 83 74 74 00 00 42 9F 66 00 02 06 29 0C 71 FF | Original Japanese Hex +す ず ! ! コ バ ン 1 5 ま い 。 ENDTEXT | Original Japanese Text +B e l l s ! W i n $ 1 5 . ENDTEXT | New English Text + + +ネコ!! コバン 50まい。 +Cats!! It's 50 coins. +$0CCF0 +50 42 74 74 00 00 42 9F 66 00 06 01 29 0C 71 FF | Original Japanese Hex +ネ コ ! ! コ バ ン 5 0 ま い 。 ENDTEXT | Original Japanese Text +C a t s ! ! W i n $ 5 0 . ENDTEXT | New English Text + + +みかん!! コバン 15まい。 +Mandarin oranges!! It's 15 coins. +$0CD00 +2A 10 38 74 74 00 00 42 9F 66 00 02 06 29 0C 71 FF | Original Japanese Hex +み か ん ! ! コ バ ン 1 5 ま い 。 ENDTEXT | Original Japanese Text +O r a n g e ! W i n $ 1 5 . ENDTEXT | New English Text + + +まだチャレンジしますか? +Do you still want to play? +$0CD11 (Line 1) +29 86 49 6D 62 66 96 16 29 17 10 75 FE | Original Japanese Hex +ま だ チ ャ レ ン ジ し ま す か ? NEWLINE | Original Japanese Text +P l a y a g a i n ? NEWLINE | New English Text +はい いいえ +Yes No +$0CD1E (Line 2) +00 00 00 00 00 00 24 0C 00 00 00 00 00 0C 0C 0E FF | Original Japanese Hex + は い い い え ENDTEXT | Original Japanese Text + Y e s N o ENDTEXT | New English Text + + +そうですか。また おたちよりください。 +Is that so. Please come again. +$0CD2F +19 0D 89 17 10 71 29 1A 00 0F 1A 1B 30 32 12 86 15 0C 71 FF | Original Japanese Hex +そ う で す か 。 ま た お た ち よ り く だ さ い 。 ENDTEXT | Original Japanese Text +P l e a s e c o m e a g a i n . ENDTEXT | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCTREASURE.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCTREASURE.txt new file mode 100644 index 00000000..bb6047d8 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/NPCTREASURE.txt @@ -0,0 +1,120 @@ +にいちゃん むかし「からくりいちぞく」が +Long ago on "Karakuri Island" +$0E307 (Line 1) +20 0C 1B 69 38 00 2B 10 16 77 10 31 12 32 0C 1B 85 12 78 7C FE | Original Japanese Hex +に い ち ゃ ん む か し 「 か ら く り い ち ぞ く 」 が NEWLINE | Original Japanese Text +L o n g a g o o n " K a r a k u r i | New English Text +ざいほうをかくした しままで つれていくぜ。 +I hid a treasure, I can take you there. +$0E31C (Line 2) +81 0C 28 0D 37 10 12 16 1A 00 16 29 29 89 00 1C 34 1D 0C 12 84 71 FD | Original Japanese Hex +ざ い ほ う を か く し た し ま ま で つ れ て い く ぜ 。 NEWPAGE | Original Japanese Text +" NEWLINE I h i d a t r e a s u r e . NEWPAGE D o | New English Text +どうだい ひとざいさん きずいてみる +Do you feel like increasing +$0E333 (Line 3) +8A 0D 86 0C 00 25 1E 81 0C 15 38 00 11 83 0C 1D 2A 33 FE | Original Japanese Hex +ど う だ い ひ と ざ い さ ん き ず い て み る NEWLINE | Original Japanese Text +y o u w a n t t o g e t NEWLINE r i c | New English Text +きはないかい? +your wealth? +$0E346 (Line 4) +11 24 1F 0C 10 0C 75 FD | Original Japanese Hex +き は な い か い ? NEWPAGE | Original Japanese Text +h ? NEWPAGE I ' m t | New English Text +ただし、あっしは おくりむかえを するだけ。 +However, I am the only one that +$0E34E (Line 5) +1A 86 16 70 0B 68 16 24 00 0F 12 32 2B 10 0E 37 00 17 33 86 13 71 FE | Original Japanese Hex +た だ し 、 あ っ し は お く り む か え を す る だ け 。 NEWLINE | Original Japanese Text +h e o n l y o n e t h a t NEWLINE k n o w s | New English Text +いのちの ほしょうまで しませんぜ。 +knows the short-cut. +$0E365 (Line 6) +0C 23 1B 23 00 28 16 6B 0D 29 89 00 16 29 18 38 84 71 FD | Original Japanese Hex +い の ち の ほ し ょ う ま で し ま せ ん ぜ 。 NEWPAGE | Original Japanese Text +t h e s h o r t - c u t . NEWPAGE I ' l l | New English Text +わたしちんは 500両いただくけど・・・・・ +I will require $500, but... +$0E378 (Line 7) +36 1A 16 1B 38 24 00 06 01 01 79 0C 1A 86 12 13 8A 72 72 72 72 72 FE | Original Japanese Hex +わ た し ち ん は 5 0 0 両 い た だ く け ど ・ ・ ・ ・ ・ NEWLINE | Original Japanese Text + n e e d $ 5 0 0 t o t a k e NEWLINE y o u . | New English Text +うまくいけば、かせげるぜ。 +Hopefully you will win it back. +$0E38F (Line 8) +0D 29 12 0C 13 8B 70 10 18 7F 33 84 71 FD | Original Japanese Hex +う ま く い け ば 、 か せ げ る ぜ 。 NEWPAGE | Original Japanese Text +. . NEWPAGE D o y o u w a n t | New English Text +いってみるかい? +Do you want to go? +$0E39D (Line 9) +0C 68 1D 2A 33 10 0C 75 FE | Original Japanese Hex +い っ て み る か い ? NEWLINE | Original Japanese Text + t o g o ? NEWLINE | New English Text +はい いいえ +Yes No +$0E3A6 (Line 10) +00 00 00 00 00 00 24 0C 00 00 00 00 00 0C 0C 0E FF | Original Japanese Hex + は い い い え ENDTEXT | Original Japanese Text + Y e s N o ENDTEXT | New English Text + + + + +しっかり ざいほうを あつめてきなよ! +Please collect the treasure! +$0E677 (Line 1) +16 68 10 32 00 81 0C 28 0D 37 00 0B 1C 2C 1D 11 1F 30 74 FE | Original Japanese Hex +し っ か り ざ い ほ う を あ つ め て き な よ ! NEWLINE | Original Japanese Text +C o l l e c t t h e t r e a s u r e | New English Text +ただし きをつけてな!! +However, please be careful! +$0E68B (Line 2) +1A 86 16 00 11 37 1C 13 1D 1F 74 74 FF | Original Japanese Hex +た だ し き を つ け て な ! ! ENDTEXT | Original Japanese Text +! NEWLINE T a k e c a r e ! ENDTEXT | New English Text + + +にいちゃん それだけしか おかねがなきゃ +You will need to be able to +$0E698 (Line 1) +20 0C 1B 69 38 00 19 34 86 13 16 10 00 0F 10 22 7C 1F 11 69 FE | Original Japanese Hex +に い ち ゃ ん そ れ だ け し か お か ね が な き ゃ NEWLINE | Original Japanese Text +Y o u ' l l n e e d t o b r i n g NEWLINE | New English Text +いまどき さんずのかわも わたれねえよ。 +pay me more gold than that. +$0E6AD (Line 2) +0C 29 8A 11 00 15 38 83 23 10 36 2D 00 36 1A 34 22 0E 30 71 FF | Original Japanese Hex +い ま ど き さ ん ず の か わ も わ た れ ね え よ 。 ENDTEXT | Original Japanese Text +m o r e g o l d t h a n t h a t . ENDTEXT | New English Text + + +ざいほうは みつかったかね・・・・・? +Did you find treasure...? +$0E6C2 (Line 1) +81 0C 28 0D 24 00 2A 1C 10 68 1A 10 22 72 72 72 72 72 75 FE | Original Japanese Hex +ざ い ほ う は み つ か っ た か ね ・ ・ ・ ・ ・ ? NEWLINE | Original Japanese Text +D i d y o u f i n d t r e a s u r | New English Text +ま、あっしには かんけいねえ ことさね。 +Well, I hope you did not find it too hard. +$0E6D6 (Line 2) +29 70 0B 68 16 20 24 00 10 38 13 0C 22 0E 00 14 1E 15 22 71 FF | Original Japanese Hex +ま 、 あ っ し に は か ん け い ね え こ と さ ね 。 ENDTEXT | Original Japanese Text +e ? NEWLINE I k n o w i t ' s h a r d . ENDTEXT | New English Text + + + + +そうかい。 あっしのふねには「のれねえ」と +OK. In the meantime, "I'm sorry" +$0E6FF (Line 1) +19 0D 10 0C 71 00 0B 68 16 23 26 22 20 24 77 23 34 22 0E 78 1E FE | Original Japanese Hex +そ う か い 。 あ っ し の ふ ね に は 「 の れ ね え 」 と NEWLINE | Original Japanese Text +O K . S a d y o u d o n ' t w a n t | New English Text +いうんだね! どきょうのねえ やろうだ・・・ +you do not want to do it! Maybe some other time... +$0E715 (Line 2) +0C 0D 38 86 22 74 00 8A 11 6B 0D 23 22 0E 00 2E 35 0D 86 72 72 72 FF | Original Japanese Hex +い う ん だ ね ! ど き ょ う の ね え や ろ う だ ・ ・ ・ ENDTEXT | Original Japanese Text +NEWLINE t o g o ! M a y b e l a t e r . . . ENDTEXT | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/TITLESCREEN.txt b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/TITLESCREEN.txt new file mode 100644 index 00000000..e61d3a3c --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/Text/TITLESCREEN.txt @@ -0,0 +1,90 @@ +// Blue Text +ひとりであそぶ +PLAYALONE / 1PLAYER / STORYMODE +$0C629 (Top Half) +$2260 $2261 $2262 $2263 $2264 $2265 $2266 $2267 $2268 $2269 $222C $222D $226A $226B $0000 $0000 | Original Japanese Hex +ひ と り で あ そ ぶ | Original Japanese Text +S T O R Y M O D E | New English Text +$0C669 (Bottom Half) +$2270 $2271 $2272 $2273 $2274 $2275 $2276 $2277 $2278 $2279 $223C $223D $227A $227B $0000 $0000 | Original Japanese Hex +ひ と り で あ そ ぶ | Original Japanese Text +S T O R Y M O D E | New English Text + +ふれりで れいせん +EXHIBITION / 2PLAYER / MULTIPLAYER +$0C689 (Top Half) +$226C $226D $226E $226F $2264 $2265 $2266 $2267 $226E $226F $2200 $2201 $2242 $2243 $2280 $2281 | Original Japanese Hex +ふ れ り で れ い せ ん | Original Japanese Text +M U L T I P L A Y E R | New English Text +$0C6C9 (Bottom Half) +$227C $227D $227E $227F $2274 $2275 $2276 $2277 $227E $227F $2210 $2211 $2252 $2253 $2290 $2291 | Original Japanese Hex +ふ れ り で れ い せ ん | Original Japanese Text +M U L T I P L A Y E R | New English Text + +パスワード +PASSWORD +$0C6E9 (Top Half) +$2282 $2283 $2284 $2285 $2286 $2287 $2288 $2289 $228A $228B $0000 $0000 $0000 $0000 $0000 $0000 | Original Japanese Hex +パ ス ワ ー ド | Original Japanese Text +P A S S W O R D I N P U T | New English Text +$0C729 (Bottom Half) +$2292 $2293 $2294 $2295 $2296 $2297 $2298 $2299 $229A $229B $0000 $0000 $0000 $0000 $0000 $0000 | Original Japanese Hex +パ ス ワ ー ド | Original Japanese Text +P A S S W O R D I N P U T | New English Text + +そらさ せってい +SETTINGS / OPTIONS +$0C749 (Top Half) +$222C $222D $222E $222F $2240 $2241 $2242 $2243 $2244 $2245 $2246 $2647 $2200 $2201 $0000 $0000 | Original Japanese Hex +そ ら さ せ っ て い | Original Japanese Text +C O N F I G U R A T I O N | New English Text +$0C789 (Bottom Half) +$223C $223D $223E $223F $2250 $2251 $2252 $2253 $2254 $2255 $2256 $2657 $2210 $2211 $0000 $0000 | Original Japanese Hex +そ ら さ せ っ て い | Original Japanese Text +C O N F I G U R A T I O N | New English Text + + +// Yellow Text +ひとりであそぶ +PLAYALONE / 1PLAYER / STORYMODE +$0C7A9 (Top Half) +$2660 $2661 $2662 $2663 $2664 $2665 $2666 $2667 $2668 $2669 $262C $262D $266A $266B $0000 $0000 | Original Japanese Hex +ひ と り で あ そ ぶ | Original Japanese Text +S T O R Y M O D E | New English Text +$0C7E9 (Bottom Half) +$2670 $2671 $2672 $2673 $2674 $2675 $2676 $2677 $2678 $2679 $263C $263D $267A $267B $0000 $0000 | Original Japanese Hex +ひ と り で あ そ ぶ | Original Japanese Text +S T O R Y M O D E | New English Text + +ふれりで れいせん +EXHIBITION / 2PLAYER / MULTIPLAYER +$0C809 (Top Half) +$266C $266D $266E $266F $2664 $2665 $2666 $2667 $266E $266F $2600 $2601 $2642 $2643 $2680 $2681 | Original Japanese Hex +ふ れ り で れ い せ ん | Original Japanese Text +M U L T I P L A Y E R | New English Text +$0C849 (Bottom Half) +$267C $267D $267E $267F $2674 $2675 $2676 $2677 $267E $267F $2610 $2611 $2652 $2653 $2690 $2691 | Original Japanese Hex +ふ れ り で れ い せ ん | Original Japanese Text +M U L T I P L A Y E R | New English Text + +パスワード +PASSWORD +$0C869 (Top Half) +$2682 $2683 $2684 $2685 $2686 $2687 $2688 $2689 $268A $268B $0000 $0000 $0000 $0000 $0000 $0000 | Original Japanese Hex +パ ス ワ ー ド | Original Japanese Text +P A S S W O R D I N P U T | New English Text +$0C8A9 (Bottom Half) +$2692 $2693 $2694 $2695 $2696 $2697 $2698 $2699 $269A $269B $0000 $0000 $0000 $0000 $0000 $0000 | Original Japanese Hex +パ ス ワ ー ド | Original Japanese Text +P A S S W O R D I N P U T | New English Text + +そらさ せってい +SETTINGS / OPTIONS +$0C8C9 (Top Half) +$262C $262D $262E $262F $2640 $2641 $2642 $2643 $2644 $2645 $2646 $2647 $2600 $2601 $0000 $0000 | Original Japanese Hex +そ ら さ せ っ て い | Original Japanese Text +C O N F I G U R A T I O N | New English Text +$0C909 (Bottom Half) +$263C $263D $263E $263F $2650 $2651 $2652 $2653 $2654 $2655 $2656 $2657 $2610 $2611 $0000 $0000 | Original Japanese Hex +そ ら さ せ っ て い | Original Japanese Text +C O N F I G U R A T I O N | New English Text \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/ConvertTitleScreenFontRLE.py b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/ConvertTitleScreenFontRLE.py new file mode 100644 index 00000000..2cdff8fd --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/ConvertTitleScreenFontRLE.py @@ -0,0 +1,100 @@ +# Konami SNES RLE Compress +BLOCKRAW = 0x80 # BLOCK: RAW Copy 5-Bit "0x80 + LENGTH (0..31), DATA.." +BLOCKRLEZERO4 = 0xE0 # BLOCK: RLE Zero 4-Bit "0xE0 + LENGTH-2 (2..17)" +BLOCKRLEZERO8 = 0xFF # BLOCK: RLE Zero 8-Bit "0xFF, LENGTH-2 (2..257)" + +RAWRLELENGTH = [] +# 1st PASS: Get RAW & Zero Run Data Lengths From File in Order +with open("TitleScreenFont4BPPENG.pic", "rb") as fin: + bytein = fin.read(1) + rawcount = 0 + zerocount = 0 + while bytein: + if bytein != b'\x00': # RAW Copy Block + rawcount += 1 + if zerocount >= 2: + if zerocount >= 258: # RLE Data > MAX LENGTH + while zerocount >= 258: + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(0xFF) + zerocount -= 257 + + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(zerocount-2) + else: + rawcount += zerocount + zerocount = 0 + else: # RLE Zero Block (bytein == b'\x00') + zerocount += 1 + if zerocount == 2: + if rawcount != 0: + RAWRLELENGTH.append(BLOCKRAW+rawcount) + rawcount = 0 + + if rawcount >= 31: # MAX RAW Copy Length Check + RAWRLELENGTH.append(BLOCKRAW+31) + rawcount -= 31 + zerocount = 0 + bytein = fin.read(1) +fin.close() + +# Get Last Remaing Block (IF Any) After File Has Been Read +# RLE Zero Block +if zerocount >= 2: + if zerocount >= 258: # RLE Data > MAX LENGTH + while zerocount >= 258: + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(0xFF) + zerocount -= 257 + RAWRLELENGTH.append(BLOCKRLEZERO8) + RAWRLELENGTH.append(zerocount-2) +else: + rawcount += zerocount +# RAW Copy Block +if rawcount >= 31: # MAX RAW Copy Length Check + RAWRLELENGTH.append(BLOCKRAW+31) + rawcount -= 31 +if rawcount != 0: + RAWRLELENGTH.append(BLOCKRAW+rawcount) + +# 2nd PASS: Save Lengths & RAW Data To File +fout = open("TitleScreenFont4BPPENG.rle", "wb") +i = 0 +bytelength = 2 +fout.write(b"%c" %0x00) # 2 Byte Pad For Byte Length +fout.write(b"%c" %0x00) +with open("TitleScreenFont4BPPENG.pic", "rb") as fin: + while i < len(RAWRLELENGTH): + if RAWRLELENGTH[i] != 255: # RAW Copy Bytes + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + rawcount = RAWRLELENGTH[i] - BLOCKRAW + while rawcount != 0: + bytein = fin.read(1) + fout.write(bytein) + bytelength += 1 + rawcount -= 1 + i += 1 + + else: # RLE Zero Bytes + if RAWRLELENGTH[i+1] >= 16: + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + i += 1 + fout.write(b"%c" %RAWRLELENGTH[i]) + bytelength += 1 + else: + i += 1 + fout.write(b"%c" %(BLOCKRLEZERO4+RAWRLELENGTH[i])) + bytelength += 1 + rlecount = RAWRLELENGTH[i] + 2 + while rlecount != 0: + bytein = fin.read(1) + rlecount -= 1 + i += 1 +fout.seek(0) # Seek To The Start Of The Output File +fout.write(b"%c" %(bytelength & 0xFF)) +fout.write(b"%c" %(bytelength >> 8)) +fin.close() +fout.close() +print("Compressed Byte Length = %d" %bytelength) diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.pic b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.pic new file mode 100644 index 00000000..f61a0945 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.pic differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.png b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.png new file mode 100644 index 00000000..2a59046f Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.rle b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.rle new file mode 100644 index 00000000..fed626ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPENG.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPJPN.png b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPJPN.png new file mode 100644 index 00000000..ba078c82 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreen/TitleScreenFont4BPPJPN.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreenFont4BPPENG.rle b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreenFont4BPPENG.rle new file mode 100644 index 00000000..fed626ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/TitleScreenFont4BPPENG.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/make.bat b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/make.bat new file mode 100644 index 00000000..bdc30179 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!/make.bat @@ -0,0 +1,2 @@ +bass "Soreyuke Ebisumaru Karakuri Meiro - Kieta Goemon no Nazo!!.asm" +ucon64 --nbak --chk "Ebisumaru Puzzle Maze - Goemon is Missing!!.sfc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.png b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.png new file mode 100644 index 00000000..4ccc7fec Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.txt new file mode 100644 index 00000000..bf0ba4bf --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable1.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0| 0 1 2 3 4 5 6 7 8 9 A B C D E +1|F G H I J K L M N O P Q R S T U +2|V W X Y Z あ い う え お な に ぬ ね の ま +3|み む め も や ゆ よ ら り る れ ろ わ を ん ア +4|イ ウ エ オ ナ ニ ヌ ネ ノ マ ミ ム メ モ ヤ ユ +5|ヨ ラ リ ル レ ロ ワ ヲ ン か き く け こ さ し +6|す せ そ た ち つ て と カ キ ク ケ コ サ シ ス +7|セ ソ タ チ ツ テ ト は ひ ふ へ ほ ハ ヒ フ ヘ +8|ホ + ー ゃ ゅ ょ っ ャ ュ ョ ッ " 。 X X X +9|X X X X X X X X X X X X X X X X +A|X X X X X X X X X X X X X X X X +B| 0 1 2 3 4 5 6 7 8 9 A B C D E // Top Half +C|F G H I J K L M N O P Q R S T U // Top Half +D|V W X Y Z あ い う え お な に ぬ ね の ま // Top Half +E|み む め も や ゆ よ ら り る れ ろ わ を ん ア // Top Half +F|イ ウ エ オ ナ ニ ヌ ネ ノ マ ミ ム メ モ ヤ ユ // Top Half \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.png b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.png new file mode 100644 index 00000000..5df747ac Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.txt new file mode 100644 index 00000000..055af679 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfCharTable2.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0|ヨ ラ リ ル レ ロ ワ ヲ ン か き く け こ さ し // Top Half +1|す せ そ た ち つ て と カ キ ク ケ コ サ シ ス // Top Half +2|セ ソ タ チ ツ テ ト は ひ ふ へ ほ ハ ヒ フ ヘ // Top Half +3|ホ + - X X ! ? / X X X X X X // Top Half +4| +5| +6| +7| 0 1 2 3 4 5 6 7 8 9 A B C D E // Bottom Half +8|F G H I J K L M N O P Q R S T U // Bottom Half +9|V W X Y Z あ い う え お な に ぬ ね の ま // Bottom Half +A|み む め も や ゆ よ ら り る れ ろ わ を ん ア // Bottom Half +B|イ ウ エ オ ナ ニ ヌ ネ ノ マ ミ ム メ モ ヤ ユ // Bottom Half +C|ヨ ラ リ ル レ ロ ワ ヲ ン か き く け こ さ し // Bottom Half +D|す せ そ た ち つ て と カ キ ク ケ コ サ シ ス // Bottom Half +E|セ ソ タ チ ツ テ ト は ひ ふ へ ほ ハ ヒ フ ヘ // Bottom Half +F|ホ + - X X ! ? / X X X X X X // Bottom Half \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfChars.png b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfChars.png new file mode 100644 index 00000000..5e31f883 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfChars.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.png b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.png new file mode 100644 index 00000000..00aaebd7 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.txt new file mode 100644 index 00000000..4dfaa253 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/CharTables/SuperNaxatOpenGolfLargeCharTable.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0| 0 1 2 3 4 5 6 7 8 9 A B C D E +1|F G H I J K L M N O P Q R S T U +2|V W X Y Z あ い う え お な に ぬ ね の ま +3|み む め も や ゆ よ ら り る れ ろ わ を ん ア +4|イ ウ エ オ ナ ニ ヌ ネ ノ マ ミ ム メ モ ヤ ユ +5|ヨ ラ リ ル レ ロ ワ ヲ ン か き く け こ さ し +6|す せ そ た ち つ て と カ キ ク ケ コ サ シ ス +7|セ ソ タ チ ツ テ ト は ひ ふ へ ほ ハ ヒ フ ヘ +8|ホ + ー < > ! ? / . X X X X X が ぎ +9|ぐ げ ご ざ じ ず ぜ ぞ だ ぢ づ で ど ガ ギ グ +A|ゲ ゴ ザ ジ ズ ゼ ゾ ダ ヂ ヅ デ ド ば び ぶ べ +B|ぼ バ ビ ブ ベ ボ ぱ ぴ ぷ ぺ ぽ パ ピ プ ペ ポ +C|ぁ ぃ ぅ ぇ ぉ ゃ ゅ ょ っ ァ ィ ゥ ェ ォ ャ ュ +D|ョ ッ +E| +F| \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/README.md b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/README.md new file mode 100644 index 00000000..939a8c22 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/README.md @@ -0,0 +1,6 @@ +SNES Japanese To English Translation +===================================== +
    +** This translation is now discontinued **
    +Please go to: https://www.romhacking.net/translations/4096/
    +For a full 100% complete translation. diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.asm b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.asm new file mode 100644 index 00000000..ab629d9d --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.asm @@ -0,0 +1,344 @@ +// SNES "Super Naxat Open - Golf de Shoubu da! Dorabocchan" Japanese To English Translation by krom (Peter Lemon): + +output "Super Naxat Open - Golf Challenge!.sfc", create +origin $00000; insert "Super Naxat Open - Golf de Shoubu da! Dorabocchan (J).sfc" // Include Japanese Super Naxat Open - Golf de Shoubu da! Dorabocchan SNES ROM +origin $007FC0 +db "SUPER NAXAT OPEN GOLF" // $007FC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +// Char Table 1 +map ' ', $00 +map '0', $01, 10 +map 'A', $0B, 26 +map '+', $81 +map '-', $82 +map '<', $83 +map '>', $84 +map '!', $85 +map '?', $86 +map '/', $87 +map '.', $88 + +macro TextStyle1(OFFSET, TEXT) { + origin {OFFSET} + db {TEXT} +} + +// Hi Score +TextStyle1($0CBA2, "BASSX") +TextStyle1($0CBAA, "YOROI") +TextStyle1($0CBB2, "MGORA") +TextStyle1($0CBBA, "YETI ") +TextStyle1($0CBC2, "TIANA") +TextStyle1($0CBCA, "YUSAF") +TextStyle1($0CBD2, "SKULL") +TextStyle1($0CBDA, "GETOR") +TextStyle1($0CBE2, "YANDU") +TextStyle1($0CBEA, "CDASS") +TextStyle1($0CC10, "MDORA") +TextStyle1($0CC18, "REPEL") +TextStyle1($0CC20, "TOYOU") +TextStyle1($0CC28, "YUKIR") +TextStyle1($0CC30, "RGORA") +TextStyle1($0CC38, "KARIN") +TextStyle1($0CC40, "TOSHI") +TextStyle1($0CC48, "AZUSA") +TextStyle1($0CC50, "GOUDO") +TextStyle1($0CC58, "NIKKI") + +// Title Screen +TextStyle1($7EDC4, "MASTERS OPEN") +TextStyle1($7ED46, "1994 RED 2013 KROM") + +// Config +TextStyle1($7E8F4, "CONFIGURE CONTROL PAD") + +// Continue +TextStyle1($7EB01, "CHOOSE SLOT TO LOAD ") + +TextStyle1($7EC1C, "THERE") +TextStyle1($7EC24, "IS NO DATA") + +TextStyle1($7F995, "STROK") +TextStyle1($7F99B, "MATCH") + +TextStyle1($7EBD8, "TEXT") +TextStyle1($7EBDF, " SPD") +TextStyle1($7F9A7, "FST") +TextStyle1($7F9AB, "NOR") +TextStyle1($7F9AF, "SLW") + +// Naxat/Masters Open Stroke/Match Play +TextStyle1($7FBC3, "MASTERS OPEN") + +TextStyle1($7E804, "PLAYERS?") +TextStyle1($7B3E8, "SETS UP PLAYERS!...") +TextStyle1($7B3FF, "MATCHPLAY IS 2PLAYER") + +TextStyle1($7E81D, "NO.HOLES?") +TextStyle1($7B416, "PICK HOLES TO PLAY") + +TextStyle1($7E835, "SET") +TextStyle1($7F946, "AMATEUR") +TextStyle1($7B42B, "SET GAME MODE!") +TextStyle1($7B43D, "TRY PRO CHALLENGE!") + +TextStyle1($7E83D, "TEXTS?") +TextStyle1($7F95C, "FAST ") +TextStyle1($7F962, "NORM ") +TextStyle1($7F968, "SLOW ") +TextStyle1($7B452, "SET MESSAGE SPEED") + +TextStyle1($7E848, "BGM.SET") +TextStyle1($7F972, "STEREO ") +TextStyle1($7F97A, "MONO ") +TextStyle1($7B466, "SOUND OUTPUT!") + +// Player Select +TextStyle1($7F3E9, "SPIKE ") +TextStyle1($7F3F1, "CAMELIA") +TextStyle1($7F3F9, "HYDRA ") +TextStyle1($7F401, "K.CLOVE") +TextStyle1($7F409, "P.STEAM") +TextStyle1($7F411, "FELINA ") + +TextStyle1($7E5EE, "HIT") +TextStyle1($7E601, "SKILL") +TextStyle1($7E614, "POSE") +TextStyle1($7E627, "SPN") +TextStyle1($7E63C, "POWER") + +TextStyle1($7F7DD, "GRASS DRIVES") +TextStyle1($7B477, "HE IS EVENLY SKILLED") +TextStyle1($7B48F, "BEGINNERS CHOICE!") + +TextStyle1($7F7A9, "ROUGH SHOTS ") +TextStyle1($7B4A3, "NOT TOO MUCH POWER") +TextStyle1($7B4B9, "BUT PLENTY OF SKILL") + +TextStyle1($7F79C, "NONE SPECIAL") +TextStyle1($7B4CF, "HAS THE STRONGEST HIT") +TextStyle1($7B4E8, "CAN BE A BIT CLUMSY!!") + +TextStyle1($7F7C3, "WEDGE STRIKE") +TextStyle1($7B500, "SMALL IN STATURE BUT") +TextStyle1($7B518, "HAS A GOOD STANCE") + +TextStyle1($7F7B6, "BUNKER SHOTS") +TextStyle1($7B52C, "SPINS THE BALL WHEN") +TextStyle1($7B543, "OUT OF A BUNKER") + +TextStyle1($7F7D0, "WINDY STRIKE") +TextStyle1($7B555, "MANIPULATES A WINDY") +TextStyle1($7B56C, "SHOT VERY WELL") + +// Caddy Select +TextStyle1($7E66B, "CADDYSELECT") + +TextStyle1($7F429, "VHESLER") +TextStyle1($7F431, "CLARENC") +TextStyle1($7F439, "ENDORA ") +TextStyle1($7F441, "YUNI ") +TextStyle1($7F449, "FREEZER") +TextStyle1($7F451, "CROC ") + +TextStyle1($7E709, "CARD") + +TextStyle1($7F8EA, ".HEIGHT") +TextStyle1($7B57D, "CADDY POSSESS A CLUB") +TextStyle1($7B595, "THAT HAS ATTACK POWER") + +TextStyle1($7F92A, ".OKAY ") +TextStyle1($7B5AD, "HIS GREAT GRANDFATHER") +TextStyle1($7B5C6, "WAS THE CLUBS FOUNDER") + +TextStyle1($7F90A, ".DASH ") +TextStyle1($7B5DE, "THIS CADDY HAS A") +TextStyle1($7B5F2, "TECHNICAL CLUB") + +TextStyle1($7F91A, ".HOMING") +TextStyle1($7B603, "HAS DECENT CLUBS AND") +TextStyle1($7B61B, "GIVES FRIENDLY ADVICE") + +TextStyle1($7F8E2, "TOPSPIN") +TextStyle1($7B633, "MAKES STEADY CHOICES") +TextStyle1($7B64B, "FOR SHOTS") + +TextStyle1($7F912, "REPLACE") +TextStyle1($7B657, "EXPERIENCED BRINGS") +TextStyle1($7B66D, "A STRONG SET OF CLUBS") + +// Stroke Play Rules +TextStyle1($7EE42, "GAME RULES") + +TextStyle1($7D008, ".STROKE PLAY MODE") +TextStyle1($7D01D, "LEAST NUMBER OF SHOTS WILL") +TextStyle1($7D03B, "WIN THE GAME") + +TextStyle1($7D051, ".PRO MODE - DIFFERENCES") +TextStyle1($7D06C, "BETWEEN AMATEUR MODE..") +TextStyle1($7D086, "WIND DIRECTION/SPEED MUCH") +TextStyle1($7D0A3, "MORE SEVERE THAN NORMAL..") +TextStyle1($7D0C0, "IF YOU LIKE THRILLS THERE") +TextStyle1($7D0DD, "IS PLENTY IN THIS MODE!") + +// Match Play Rules +TextStyle1($7D0F8, ".MATCH PLAY MODE") +TextStyle1($7D10C, "2 PLAYERS EARN POINTS FOR") +TextStyle1($7D129, "EVERY HOLE WON A HIGH SCORE") +TextStyle1($7D148, "WINS THE GAME") + +TextStyle1($7D15A, ".PRO MODE - DIFFERENCES") +TextStyle1($7D175, "BETWEEN AMATEUR MODE..") +TextStyle1($7D18F, "WIND DIRECTION/SPEED MUCH") +TextStyle1($7D1AC, "MORE SEVERE THAN NORMAL..") +TextStyle1($7D1C9, "IF YOU LIKE THRILLS THERE") +TextStyle1($7D1E6, "IS PLENTY IN THIS MODE!") + +// Course Select +TextStyle1($7BBA9, "CHOOSE A COURSE TYPE!") +TextStyle1($7BBC2, "SIX HOLES PER COURSE") + +TextStyle1($7B758, "DESERT COURSE. TRY") +TextStyle1($7B76E, "NOT TO GET STUCK!") + +TextStyle1($7B782, "JUNGLE COURSE.ITS") +TextStyle1($7B797, "EASY TO LAND IN ROUGH") + +TextStyle1($7B7AF, "LAKE COURSE.TAKE CARE") +TextStyle1($7B7C8, "NOT TO LAND IN WATER!") + + + + + + + + +// Player Text +TextStyle1($78007, "TRY TODO MY") +TextStyle1($78016, "BEST!") + +TextStyle1($7801F, "I TRY MUCH") +TextStyle1($7802D, "MORE!") + +TextStyle1($78036, "WONT GIVE UP!") + +TextStyle1($78061, "BECOME STRONG!") +TextStyle1($78073, "I AIM TO BE A PRO!!") + +TextStyle1($7808A, "TRY FOR A NEW RECORD!") + +TextStyle1($780A3, "TRY MY LUCK! THIS") +TextStyle1($780B8, "HOLE IS MINE") + +TextStyle1($780E4, "SEE GENIUS AS I PLAY") +TextStyle1($780FC, "PROFESSIONAL GOLF!") + +TextStyle1($78112, "HA...MY TURN...") + +TextStyle1($78125, "HERE I COME... I WILL") +TextStyle1($7813E, "SHOW REAL POWER!") + +TextStyle1($7818A, "LOOKIE!") + +TextStyle1($78195, "LOOK ON!") + +TextStyle1($781A1, "SEE ME!") + +TextStyle1($781BF, "COULD IT BE AN EAGLE?") + +TextStyle1($781D8, "ITS TIME FOR THE TRUE") +TextStyle1($781F1, "POWER OF THE EAGLE") + +TextStyle1($78207, "I THINK I CAN CONVERT") +TextStyle1($78220, "IT INTO AN EAGLE!") + +TextStyle1($78251, "I THINK IVE") +TextStyle1($78260, "GOT HANG OF IT!!") + +TextStyle1($78274, "CAN I MANAGE") +TextStyle1($78284, "A GREAT SCORE?") + +TextStyle1($78296, "I AM GONNA") +TextStyle1($782A4, "SHOW YOU MY POWER") + +// Caddy Text +TextStyle1($78340, "I AM THE EVIL EMPEROR") +TextStyle1($78359, "ILL GIVE ADVICE!") +TextStyle1($7836E, "NOT MUCH TO SAY FOR") +TextStyle1($78385, "THIS HOLE... I SHOOT") +TextStyle1($7839E, "BLIND AT FULL POWER!") + +TextStyle1($78E3D, "LISTEN UP...") +TextStyle1($78E4D, "FOR THIS HOLE YOU") +TextStyle1($78E63, "CAN SLICE TO KEEP") +TextStyle1($78E78, "ON THE FAIRWAY. NEED") +TextStyle1($78E91, "BACKSPIN TO HELP TO") +TextStyle1($78EA8, "AVOID ENDING IN") +TextStyle1($78EBC, "THE BUNKER.") + +TextStyle1($7A258, "YOU CALLED? YES") +TextStyle1($7A26B, "IT IS A LONG DRIVE ON") +TextStyle1($7A285, "THIS HOLE TRY TO STAY") +TextStyle1($7A29E, "IN THE CENTER OF") +TextStyle1($7A2B3, "A NARROW FAIRWAY") + +// Start Hole +TextStyle1($7DC57, "PTS") + +// Ball Control +TextStyle1($7FB59, "TOP SPIN") +TextStyle1($7FB62, "NORMAL ") +TextStyle1($7FB6B, "BACKSPIN") + +TextStyle1($7FB7A, "STRIKE ") +TextStyle1($7FB82, "HOOK ") +TextStyle1($7FB8A, "SLICE ") + +// Card Select +TextStyle1($7D8EC, "TO USE ") +TextStyle1($7D8FB, " PRESS Y") +TextStyle1($7D90B, "TO SKIP") +TextStyle1($7D91A, " PRESS A") + +TextStyle1($7D92A, "LEFT") +TextStyle1($7D936, "+ RIGHT") +TextStyle1($7D945, " SELECT") + +TextStyle1($7FB0D, "GLUETUBE") +TextStyle1($7BC7E, ".GLUE BALL TO") +TextStyle1($7BC8F, "THE GROUND.") + +TextStyle1($7FB16, "PSYCHO") +TextStyle1($7BCA2, ".USE DPAD TO") +TextStyle1($7BCB2, "CONTROL BALL.") + +TextStyle1($7FB1D, "DASHING") +TextStyle1($7BCC7, ".2XPOWER AIR") +TextStyle1($7BCD7, "DISTANCE++") + +TextStyle1($7FB2C, "HOMING") +TextStyle1($7BD0A, ". ATTRACTION") +TextStyle1($7BD1A, "TO THE HOLE.") + +TextStyle1($7FB45, "STRAIGHT") +TextStyle1($7BEFF, ".AS AN ARROW") +TextStyle1($7BF0F, "BALL HIT.") + +// End Hole +TextStyle1($7DB7B, "OVERALL") +TextStyle1($7DB8F, "PRIZE") +TextStyle1($7DB9D, "PTS") +TextStyle1($7F67D, " BOGEY") +TextStyle1($7F686, "DOUBLE BOGEY") +TextStyle1($7F693, "TRIPLE BOGEY") + +// Select Screen +TextStyle1($7E3BA, "SCR") +TextStyle1($7E303, "PRIZE") + +TextStyle1($78B5E, "THE BATTLE HAS NOW") +TextStyle1($78B74, "STARTED!AIM FOR TOP!") + +TextStyle1($7A65D, "THIS IS THE START OF") +TextStyle1($7A675, "THE ROUND.GOOD LUCK!") \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.ips b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.ips new file mode 100644 index 00000000..e9b6483a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Super Naxat Open - Golf de Shoubu da! Dorabocchan.ips differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/BallControl.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/BallControl.txt new file mode 100644 index 00000000..5b59b30a --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/BallControl.txt @@ -0,0 +1,47 @@ +トップスピン +Top Spin +$7FB59 +76 D1 BD 6F BC 58 00 00 | Original Japanese Hex +ト ッ プ ス ピ ン | Original Japanese Text +T O P S P I N | New English Text +1E 19 1A 00 1D 1A 13 18 | New English Hex +| +ノーマルショット +Normal Shot +$7FB62 +48 82 49 53 6E D0 D1 76 | Original Japanese Hex +ノ ー マ ル シ ョ ッ ト | Original Japanese Text +N O R M A L | New English Text +18 19 1C 17 0B 16 00 00 | New English Hex +| +バックスピン +Backspin +$7FB6B +B1 D1 6A 6F BC 58 00 00 | Original Japanese Hex +バ ッ ク ス ピ ン | Original Japanese Text +B A C K S P I N | New English Text +0C 0B 0D 15 1D 1A 13 18 | New English Hex + +ストレート +Straight +$7FB7A +6F 76 54 82 76 00 00 | Original Japanese Hex +ス ト レ ー ト | Original Japanese Text +S T R I K E | New English Text +1D 1E 1C 13 15 0F 00 | New English Hex +| +ドローボール +Draw ball +$7FB82 +AB 55 82 B5 82 53 00 | Original Japanese Hex +ド ロ ー ボ ー ル | Original Japanese Text +H O O K | New English Text +12 19 19 15 00 00 00 | New English Hex +| +フェードボール +Fade ball +$7FB8A +7E CC 82 AB B5 82 53 | Original Japanese Hex +フ ェ ー ド ボ ー ル | Original Japanese Text +S L I C E | New English Text +1D 16 13 0D 0F 00 00 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddySelect.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddySelect.txt new file mode 100644 index 00000000..aa0ac7c3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddySelect.txt @@ -0,0 +1,195 @@ +CADY SELECT +CADDYSELECT +$7E66B +0D 0B 0E 23 00 1D 0F 16 0F 0D 1E | Original Japanese Hex +C A D Y S E L E C T | Original Japanese Text +C A D D Y S E L E C T | New English Text +0D 0B 0E 0E 23 1D 0F 16 0F 0D 1E | New English Hex + +オオワルサー +General Von Hesler +$7F429 +43 43 56 53 6D 82 00 | Original Japanese Hex +オ オ ワ ル サ ー | Original Japanese Text +V H E S L E R | New English Text +20 12 0F 1D 16 0F 1C | New English Hex + +だいちょうろう +Clarence or Master Ching Cao Qiang +$7F431 +98 26 64 C7 27 3B 27 | Original Japanese Hex +だ い ち ょ う ろ う | Original Japanese Text +C L A R E N C | New English Text +0D 16 0B 1C 0F 18 0D | New English Hex + +エンドラ +Endora (might be Vampra from u.s) +$7F439 +42 58 AB 51 00 00 00 | Original Japanese Hex +エ ン ド ラ | Original Japanese Text +E N D O R A | New English Text +0F 18 0E 19 1C 0B 00 | New English Hex + +ユーニ +Yuni +$7F441 +4F 82 45 00 00 00 00 | Original Japanese Hex +ユ ー ニ | Original Japanese Text +Y U N I | New English Text +23 1F 18 13 00 00 00 | New English Hex + +アイスゴン +The Freezer / Ice Gun +$7F449 +3F 40 6F A1 58 00 00 | Original Japanese Hex +ア イ ス ゴ ン | Original Japanese Text +F R E E Z E R | New English Text +10 1C 0F 0F 24 0F 1C | New English Hex + +わにどじーん +Croc +$7F451 +3C 2B 9C 94 82 3E 00 | Original Japanese Hex +わ に ど じ ー ん | Original Japanese Text +C R O C | New English Text +0D 1C 19 0D 00 00 00 | New English Hex + +カード. +Card. +$7E709 +68 82 AB 88 | Original Japanese Hex +カ ー ド . | Original Japanese Text +C A R D | New English Text +0D 0B 1C 0E | New English Hex + +わんきょくんR +Curvature height +$7F8EA +3C 3E 5A C7 5B 3E 1C | Original Japanese Hex +わ ん き ょ く ん R | Original Japanese Text +. H E I G H T | New English Text +88 12 0F 13 11 12 1E | New English Hex +| +こうげきりょくのある クラブをもっている +It 's Intermediate beast shrine's caddy has a club with attack power +$7B57D (Line 1) +5D 27 91 5A 38 C7 5B 2E 25 39 00 6A 51 B3 3D 33 C8 66 26 39 | Original Japanese Hex +こ う げ き り ょ く の あ る ク ラ ブ を も っ て い る | Original Japanese Text +C A D D Y P O S S E S S A C L U B | New English Text +0D 0B 0E 0E 23 00 1A 19 1D 1D 0F 1D 1D 00 0B 00 0D 16 1F 0C | New English Hex +キャディさんだよ ちゅうきゅうしゃむけだね +$7B595 (Line 2) +69 CE AA CA 5E 3E 98 36 00 64 C6 27 5A C6 27 5F C5 31 5C 98 2D | Original Japanese Hex +キ ャ デ ィ さ ん だ よ ち ゅ う き ゅ う し ゃ む け だ ね | Original Japanese Text +T H A T H A S A T T A C K P O W E R | New English Text +1E 12 0B 1E 00 12 0B 1D 00 0B 1E 1E 0B 0D 15 00 1A 19 21 0F 1C | New English Hex + +おーけーデス +Is okay +$7F92A +29 82 5C 82 AA 6F 00 | Original Japanese Hex +お ー け ー デ ス | Original Japanese Text +. O K A Y | New English Text +88 19 15 0B 23 00 00 | New English Hex +| +しぶめのクラブをそろえている じいさまだわ +I guess it can not only have I been called a city that truly it 's grandfather align the club the second branch +$7B5AD (Line 1) +5F AE 32 2E 6A 51 B3 3D 62 3B 28 66 26 39 00 94 26 5E 2F 98 3C | Original Japanese Hex +し ぶ め の ク ラ ブ を そ ろ え て い る じ い さ ま だ わ | Original Japanese Text +H I S G R E A T G R A N D F A T H E R | New English Text +12 13 1D 00 11 1C 0F 0B 1E 00 11 1C 0B 18 0E 10 0B 1E 12 0F 1C | New English Hex +さすが としをめされているだけでわないわね +$7B5C6 (Line 2) +5E 60 8E 00 67 5F 3D 32 5E 3A 66 26 39 98 5C 9B 3C 2A 26 3C 2D | Original Japanese Hex +さ す が と し を め さ れ て い る だ け で わ な い わ ね | Original Japanese Text +W A S T H E C L U B S F O U N D E R | New English Text +21 0B 1D 00 1E 12 0F 00 0D 16 1F 0C 1D 00 10 19 1F 18 0E 0F 1C | New English Hex + +ねっけつカード +Dashing / Passionate / Hot Blood +$7F90A +2D C8 5C 65 68 82 AB | Original Japanese Hex +ね っ け つ カ ー ド | Original Japanese Text +. D A S H | New English Text +88 0E 0B 1D 12 00 00 | New English Hex +| +テクニカルなクラブをそろえている +The club offers a large selection of technical It 's sister .. aunt which burns +$7B5DE (Line 1) +75 6A 45 68 53 2A 6A 51 B3 3D 62 3B 28 66 26 39 | Original Japanese Hex +テ ク ニ カ ル な ク ラ ブ を そ ろ え て い る | Original Japanese Text +T H I S C A D D Y H A S A | New English Text +1E 12 13 1D 00 0D 0B 0E 0E 23 00 12 0B 1D 00 0B | New English Hex +もえるおば..おねえさんだわ +$7B5F2 (Line 2) +33 28 39 29 AC 88 88 29 2D 28 5E 3E 98 3C | Original Japanese Hex +も え る お ば . . お ね え さ ん だ わ | Original Japanese Text +T E C H N I C A L C L U B | New English Text +1E 0F 0D 12 18 13 0D 0B 16 00 0D 16 1F 0C | New English Hex + +ホーミンくん +Homing ok +$7F91A +80 82 4A 58 5B 3E 00 | Original Japanese Hex +ホ ー ミ ン く ん | Original Japanese Text +. H O M I N G | New English Text +88 12 19 17 13 18 11 | New English Hex +| +もってるクラブはまともだし アドバイスも +Club you have is decent then also advice I'm able to play with confidence from friendly +$7B603 (Line 1) +33 C8 66 39 6A 51 B3 77 2F 67 33 98 5F 00 3F AB B1 40 6F 33 | Original Japanese Hex +も っ て る ク ラ ブ は ま と も だ し ア ド バ イ ス も | Original Japanese Text +H A S D E C E N T C L U B S A N D | New English Text +12 0B 1D 00 0E 0F 0D 0F 18 1E 00 0D 16 1F 0C 1D 00 0B 18 0E | New English Hex +やさしいから あんしんしてプレイできるわよ +$7B61B (Line 2) +34 5E 5F 26 59 37 00 25 3E 5F 3E 5F 66 BD 54 40 9B 5A 39 3C 36 | Original Japanese Hex +や さ し い か ら あ ん し ん し て プ レ イ で き る わ よ | Original Japanese Text +G I V E S F R I E N D L Y A D V I C E | New English Text +11 13 20 0F 1D 00 10 1C 13 0F 18 0E 16 23 00 0A 0E 20 13 0D 0F | New English Hex + +TOPぅカード +TOP~U Card +$7F8E2 +1E 19 1A C2 68 82 AB | Original Japanese Hex +T O P ぅ カ ー ド | Original Japanese Text +T O P S P I N | New English Text +1E 19 1A 1D 1A 13 18 | New English Hex +| +ひつようなクラブは てがたくおさえている +Necessary club is kept on a steady basis I'm Caddy's +$7B633 (Line 1) +78 65 36 27 2A 6A 51 B3 77 00 66 8E 63 5B 29 5E 28 66 26 39 | Original Japanese Hex +ひ つ よ う な ク ラ ブ は て が た く お さ え て い る | Original Japanese Text +M A K E S S T E A D Y C H O I C E S | New English Text +17 0B 15 0F 1D 00 1D 1E 0F 0B 0E 23 00 0D 12 19 13 0D 0F 1D | New English Hex +キャディーさんだよ +$7B64B (Line 2) +69 CE AA CA 82 5E 3E 98 36 | Original Japanese Hex +キ ャ デ ィ ー さ ん だ よ | Original Japanese Text +F O R S H O T S | New English Text +10 19 1C 00 1D 12 19 1E 1D | New English Hex + +ボールルイス +Ballroom Position +$7F912 +B5 82 53 53 40 6F 00 | Original Japanese Hex +ボ ー ル ル イ ス | Original Japanese Text +R E P L A C E | New English Text +1C 0F 1A 16 0B 0D 0F | New English Hex +| +きょうりょくな クラブしか もたない +It does not have only a strong club It 's experienced person for'm caddy's +$7B657 (Line 1) +5A C7 27 38 C7 5B 2A 00 6A 51 B3 5F 59 00 33 63 2A 26 | Original Japanese Hex +き ょ う り ょ く な ク ラ ブ し か も た な い | Original Japanese Text +E X P E R I E N C E D B R I N G S | New English Text +0F 22 1A 0F 1C 13 0F 18 0D 0F 0E 00 0C 1C 13 18 11 1D | New English Hex +キャディさんだよ じょうきゅうしゃむけだね +$7B66D (Line 2) +69 CE AA CA 5E 3E 98 36 00 94 C7 27 5A C6 27 5F C5 31 5C 98 2D | Original Japanese Hex +キ ャ デ ィ さ ん だ よ じ ょ う き ゅ う し ゃ む け だ ね | Original Japanese Text +A S T R O N G S E T O F C L U B S | New English Text +0B 00 1D 1E 1C 19 18 11 00 1D 0F 1E 00 19 10 00 0D 16 1F 0C 1D | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddyText.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddyText.txt new file mode 100644 index 00000000..df4f9f00 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CaddyText.txt @@ -0,0 +1,121 @@ +フッフッフッ ちょうぜつムテキで すてきな +The nice in Fuffuffu~tsu transcendence Muteki +While Walther emperor of evil +Hear it in ... I'll give advice! +Not able to speak well this bloody hole... +I shoot at full power and without thinking! +$78340 (Line 1) +7E D1 7E D1 7E D1 00 64 C7 27 96 65 4B 75 69 9B 00 60 66 5A 2A | Original Japanese Hex +フ ッ フ ッ フ ッ ち ょ う ぜ つ ム テ キ で す て き な | Original Japanese Text +I A M T H E E V I L E M P E R O R | New English Text +13 00 0B 17 00 1E 12 0F 00 0F 20 13 16 00 0F 17 1A 0F 1C 19 1C | New English Hex +あくのていおうオオワルサーさまが +$78359 (Line 2) +25 5B 2E 66 26 29 27 43 43 56 53 6D 82 5E 2F 8E | Original Japanese Hex +あ く の て い お う オ オ ワ ル サ ー さ ま が | Original Japanese Text +I L L G I V E A D V I C E ! | New English Text +13 16 16 00 11 13 20 0F 00 0B 0E 20 13 0D 0F 85 | New English Hex +アドバイスをしてやろう..では きけ! +$7836E (Line 3) +3F AB B1 40 6F 3D 5F 66 34 3B 27 88 88 9B 77 00 5A 5C 85 | Original Japanese Hex +ア ド バ イ ス を し て や ろ う . . で は き け ! | Original Japanese Text +N O T M U C H T O S A Y F O R | New English Text +18 19 1E 00 17 1F 0D 12 00 1E 19 00 1D 0B 23 00 10 19 1C | New English Hex +このホールで ちゅういすることはない.. +$78385 (Line 4) +5D 2E 80 82 53 9B 00 64 C6 27 26 60 39 5D 67 77 2A 26 88 88 | Original Japanese Hex +こ の ホ ー ル で ち ゅ う い す る こ と は な い . . | Original Japanese Text +T H I S H O L E . . . I S H O O T | New English Text +1E 12 13 1D 00 12 19 16 0F 88 88 88 00 13 00 1D 12 19 19 1E | New English Hex +なにもかんがえず フルパワーでうつのだ! +$7839E (Line 5) +2A 2B 33 59 3E 8E 28 95 00 7E 53 BB 56 82 9B 27 65 2E 98 85 | Original Japanese Hex +な に も か ん が え ず フ ル パ ワ ー で う つ の だ ! | Original Japanese Text +B L I N D A T F U L L P O W E R ! | New English Text +0C 16 13 18 0E 00 0B 1E 00 10 1F 16 16 00 1A 19 21 0E 1C 85 | New English Hex + +ふぉっふぉっふぉっ... +'Ll folder Tsu Tsu Fo Fo ... +When it should be noted in this Hole +Dji cut-to judge around the fairway +Ball is too rolling as hard accused +The back spin to avoid falling in bunker +Prudently the fairway over +Na 's Causeway that I aimed at? +$78E3D (Line 1) +79 C4 C8 79 C4 C8 79 C4 C8 88 88 88 | Original Japanese Hex +ふ ぉ っ ふ ぉ っ ふ ぉ っ . . . | Original Japanese Text +L I S T E N U P . . . | New English Text +16 13 1D 1E 0F 18 00 1F 1A 88 88 88 | New English Hex +このホールでちゅういすべきところは +$78E4D (Line 2) +5D 2E 80 82 53 9B 64 C6 27 26 60 AF 5A 67 5D 3B 77 | Original Japanese Hex +こ の ホ ー ル で ち ゅ う い す べ き と こ ろ は | Original Japanese Text +F O R T H I S H O L E Y O U | New English Text +10 19 1C 00 1E 12 13 1D 00 12 19 16 0F 00 23 19 1F | New English Hex +フェアウェイの まわりのさばくぢゃ +$78E63 (Line 3) +7E CC 3F 41 CC 40 2E 00 2F 3C 38 2E 5E AC 5B 99 C5 | Original Japanese Hex +フ ェ ア ウ ェ イ の ま わ り の さ ば く ぢ ゃ | Original Japanese Text +C A N S L I C E T O K E E P | New English Text +0D 0B 18 00 1D 16 13 0D 0F 00 1E 19 00 15 0F 0F 1A | New English Hex +せめかたとしては ボールがころがりすぎて +$78E78 (Line 4) +61 32 59 63 67 5F 66 77 00 B5 82 53 8E 5D 3B 8E 38 60 8F 66 | Original Japanese Hex +せ め か た と し て は ボ ー ル が こ ろ が り す ぎ て | Original Japanese Text +O N T H E F A I R W A Y . N E E D | New English Text +19 18 00 1E 12 0F 00 10 0B 13 1C 21 0B 23 88 00 18 0F 0F 0E | New English Hex +バンカーにおちないようにバックスピンを +$78E91 (Line 5) +B1 58 68 82 2B 29 64 2A 26 36 27 2B B1 D1 6A 6F BC 58 3D | Original Japanese Hex +バ ン カ ー に お ち な い よ う に バ ッ ク ス ピ ン を | Original Japanese Text +B A C K S P I N T O H E L P T O | New English Text +0C 0B 0D 15 1D 1A 13 18 00 1E 19 00 12 0F 16 1A 00 1E 19 | New English Hex +かけて てがたくフェアウェイを +$78EA8 (Line 6) +59 5C 66 00 66 8E 63 5B 7E CC 3F 41 CC 40 3D | Original Japanese Hex +か け て て が た く フ ェ ア ウ ェ イ を | Original Japanese Text +A V O I D E N D I N G I N | New English Text +0B 20 19 13 0E 00 0F 18 0E 13 18 11 00 13 18 | New English Hex +ねらったらどうじゃな? +$78EBC (Line 7) +2D 37 C8 63 37 9C 27 94 C5 2A 86 | Original Japanese Hex +ね ら っ た ら ど う じ ゃ な ? | Original Japanese Text +T H E B U N K E R . | New English Text +1E 12 0F 00 0C 1F 18 15 0F 1C 88 | New English Hex + +はーい? わたしをよぶからには +And now that call me? Yesss +Things very much You're a must have happened... +I speak is at stake to long drive contest in this hole +Central course because narrow +Anymore under the fairway! +$7A258 (Line 1) +77 82 26 86 00 3C 63 5F 3D 36 AE 59 37 2B 77 | Original Japanese Hex +は ー い ? わ た し を よ ぶ か ら に は | Original Japanese Text +Y O U C A L L E D ? Y E S | New English Text +23 19 1F 00 0D 0B 16 16 0F 0E 86 00 23 0F 1D | New English Hex +よほどのことがおきたにちがいないわね... +$7A26B (Line 2) +36 7B 9C 2E 5D 67 8E 29 5A 63 2B 64 8E 26 2A 26 3C 2D 88 88 88 | Original Japanese Hex +よ ほ ど の こ と が お き た に ち が い な い わ ね . . . | Original Japanese Text +I T I S A L O N G D R I V E O N | New English Text +13 1E 00 13 1D 00 0B 00 16 19 18 11 00 0E 1C 13 20 0F 00 19 18 | New English Hex +このホールにはドラコンしょうがかかってるわ +$7A285 (Line 3) +5D 2E 80 82 53 2B 77 AB 51 6C 58 5F C7 27 8E 59 59 C8 66 39 3C | Original Japanese Hex +こ の ホ ー ル に は ド ラ コ ン し ょ う が か か っ て る わ | Original Japanese Text +T H I S H O L E T R Y T O S T A Y | New English Text +1E 12 13 1D 00 12 19 16 0F 00 1E 1C 23 00 1E 19 00 1D 1E 0B 23 | New English Hex +コースがせまいから ちゅうおうの +$7A29E (Line 4) +6C 82 6F 8E 61 2F 26 59 37 00 64 C6 27 29 27 2E | Original Japanese Hex +コ ー ス が せ ま い か ら ち ゅ う お う の | Original Japanese Text +I N T H E C E N T E R O F | New English Text +13 18 00 1E 12 0F 00 0D 0F 18 1E 0F 1C 00 19 10 | New English Hex +フェアウェイキープに はげもう! +$7A2B3 (Line 5) +7E CC 3F 41 CC 40 69 82 BD 2B 00 77 91 33 27 85 | Original Japanese Hex +フ ェ ア ウ ェ イ キ ー プ に は げ も う ! | Original Japanese Text +A N A R R O W F A I R W A Y | New English Text +0B 00 18 0B 1C 1C 19 21 00 10 0B 13 1C 21 0B 23 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CardSelect.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CardSelect.txt new file mode 100644 index 00000000..8d8d1636 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CardSelect.txt @@ -0,0 +1,137 @@ +" +$7D8EC +00 00 00 00 00 00 8B | Original Japanese Hex + " | Original Japanese Text +T O U S E | New English Text +1E 19 00 1F 1D 0F 00 | New English Hex +| +つかう Yボタン +To Use Y Push-Buttons +$7D8FB +65 59 27 00 23 80 72 58 | Original Japanese Hex +つ か う Y ボ タ ン | Original Japanese Text + P R E S S Y | New English Text +00 1A 1C 0F 1D 1D 00 23 | New English Hex +| +. " +$7D90B +00 8C 00 00 00 00 8B | Original Japanese Hex + . " | Original Japanese Text +T O S K I P | New English Text +1E 19 00 1D 15 13 1A | New English Hex +| +パス Aボタン +Pass/Skipping a move A Push-Buttons +$7D91A +7C 6F 00 00 0B 80 72 58 | Original Japanese Hex +パ ス A ボ タ ン | Original Japanese Text + P R E S S A | New English Text +00 1A 1C 0F 1D 1D 00 0B | New English Hex +| +" +$7D92A +00 00 00 8B | Original Japanese Hex + " | Original Japanese Text +L E F T | New English Text +16 0F 10 1E | New English Hex +| +えらぶ さゆう +to choose; to select; left and right +$7D936 +28 37 79 00 5E 35 27 | Original Japanese Hex +え ら ぶ さ ゆ う | Original Japanese Text ++ R I G H T | New English Text +81 00 1C 13 11 12 1E | New English Hex +| +キー +Key +$7D945 +00 00 00 00 00 69 82 | Original Japanese Hex + キ ー | Original Japanese Text + S E L E C T | New English Text +00 1D 0F 16 0F 0D 1E | New English Hex + +くっつくんカード +.ボールがちゃくちしたとき +Card does stick +.When the ball landed +No longer bound +$7FB0D (Line 1) $7BC7E +5B C8 65 5B 3E 68 82 AB 88 B5 82 53 8E 64 C5 5B 64 5F 63 67 5A | Original Japanese Hex +く っ つ く ん カ ー ド . ボ ー ル が ち ゃ く ち し た と き | Original Japanese Text +G L U E T U B E . G L U E B A L L T O | New English Text +11 16 1F 0F 1E 1F 0C 0F 88 11 16 1F 0F 00 0C 0B 16 16 00 1E 19 | New English Hex +バウンドしなくなります +$7BC8F (Line 2) +B1 41 58 AB 5F 2A 5B 2A 38 2F 60 | Original Japanese Hex +バ ウ ン ド し な く な り ま す | Original Japanese Text +T H E G R O U N D . | New English Text +1E 12 0F 00 11 1C 19 1F 18 0E 88 | New English Hex + +サイコカード +.いどうちゅうのボールを +Psycho card +.I will take and is a four-way +controller ball on the move +$7FB16 (Line 1) $7BCA2 +6D 40 6C 68 82 AB 88 26 9C 27 64 C6 27 2E B5 82 53 3D | Original Japanese Hex +サ イ コ カ ー ド . い ど う ち ゅ う の ボ ー ル を | Original Japanese Text +P S Y C H O . U S E D P A D T O | New English Text +1A 1D 23 1D 12 19 88 1F 1D 0F 00 0E 1A 0B 0E 00 1E 19 | New English Hex +じゅうじキーであやつれます +$7BCB2 (Line 2) +94 C6 27 94 69 82 9B 25 34 65 3A 2F 60 | Original Japanese Hex +じ ゅ う じ キ ー で あ や つ れ ま す | Original Japanese Text +C O N T R O L B A L L . | New English Text +0D 19 18 1E 1C 19 16 00 0C 0B 16 16 88 | New English Hex + +ねっけつカード +.パワーが2ばいになって +Dashing card +.Power is double +Flying distance is extended +$7FB1D (Line 1) $7BCC7 +2D C8 5C 65 68 82 AB 88 BB 56 82 8E 03 AC 26 2B 2A C8 66 | Original Japanese Hex +ね っ け つ カ ー ド . パ ワ ー が 2 ば い に な っ て | Original Japanese Text +D A S H I N G . 2 X P O W E R A I R | New English Text +0E 0B 1D 12 13 18 11 88 03 22 1A 19 21 0F 1C 00 0B 13 1C | New English Hex +ひきょりが のびます +$7BCD7 (Line 2) +78 5A C7 38 8E 00 2E AD 2F 60 | Original Japanese Hex +ひ き ょ り が の び ま す | Original Japanese Text +D I S T A N C E + + | New English Text +0E 13 1D 1E 0B 18 0D 0F 81 81 | New English Hex + +ホーミンくん +.カップのあるほうこうへ +Homing card +.The direction of cup +Ball will be attracted +$7FB2C (Line 1) $7BD0A +80 82 4A 58 5B 3E 88 68 D1 BD 2E 25 39 7B 27 5D 27 7A | Original Japanese Hex +ホ ー ミ ン く ん . カ ッ プ の あ る ほ う こ う へ | Original Japanese Text +H O M I N G . A T T R A C T I O N | New English Text +12 19 17 13 18 11 88 00 0B 1E 1E 1C 0B 0D 1E 13 19 18 | New English He +ボールがひきよせられます +$7BD1A (Line 2) +B5 82 53 8E 78 5A 36 61 37 3A 2F 60 | Original Japanese Hex +ボ ー ル が ひ き よ せ ら れ ま す | Original Japanese Text +T O T H E H O L E . | New English Text +1E 19 00 1E 12 0F 00 12 19 16 0F 88 | New English Hex + +まっすぐショット +.ナニガアロウト ボール +Shot straight +.Arrows ball +Straight ahead +$7FB45 (Line 1) $7BEFF +2F C8 60 90 6E D0 D1 76 88 44 45 9D 3F 55 41 76 00 B5 82 53 | Original Japanese Hex +ま っ す ぐ シ ョ ッ ト . ナ ニ ガ ア ロ ウ ト ボ ー ル | Original Japanese Text +S T R A I G H T . A S A N A R R O W | New English Text +1D 1E 1C 0B 13 11 12 1E 88 0B 1D 00 0B 18 00 0B 1C 1C 19 21 | New English Hex +マッスグススム.. +$7BF0F (Line 2) +49 D1 6F 9F 6F 6F 4B 88 88 | Original Japanese Hex +マ ッ ス グ ス ス ム . . | Original Japanese Text +B A L L H I T . | New English Text +0C 0B 16 16 00 12 13 1E 88 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Config.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Config.txt new file mode 100644 index 00000000..500aeaf2 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Config.txt @@ -0,0 +1,8 @@ +コントロールパットのわりふりをしてください +Please allocation control pad +$7E8F4 +6C 58 76 55 82 53 BB D1 76 2E 3C 38 79 38 3D 5F 66 5B 98 56 26 | Original Japanese Hex +コ ン ト ロ ー ル パ ッ ト の わ り ふ り を し て く だ さ い | Original Japanese Text +C O N F I G U R E C O N T R O L P A D | New English Text +0D 19 18 10 13 11 1F 1C 0F 00 0D 19 18 1E 1C 19 16 00 1A 0B 0E | New English Hex + diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Continue.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Continue.txt new file mode 100644 index 00000000..43956b27 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/Continue.txt @@ -0,0 +1,76 @@ +ロードする スロットを えらんでください +Please select a slot to load +$7EB01 +55 82 AB 60 39 00 6F 55 D1 76 3D 00 28 37 3E 9B 5B 98 5E 26 | Original Japanese Hex +ロ ー ド す る ス ロ ッ ト を え ら ん で く だ さ い | Original Japanese Text +C H O O S E S L O T T O L O A D | New English Text +0D 12 19 19 1D 0F 00 1D 16 19 1E 00 1E 19 00 16 19 0B 0E 00 | New English Hex + + +" " +There is no data +$7EC1C (Line 1) +00 8B 00 00 8B | Original Japanese Hex + " " | Original Japanese Text +T H E R E | New English Text +1E 12 0F 1C 0F | New English Hex +データが ありません +$7EC24 (Line 2) +75 82 72 59 00 25 38 2F 61 3E | Original Japanese Hex +デ ー タ が あ り ま せ ん | Original Japanese Text +I S N O D A T A | New English Text +13 1D 00 18 19 00 0E 0B 1E 0B | New English Hex + +すとろーく +Stroke +$7F995 +60 67 3B 82 5B | Original Japanese Hex +す と ろ ー く | Original Japanese Text +S T R O K | New English Text +1D 1E 1C 19 15 | New English Hex +| +マッチ +Match +$7F99B +00 49 8A 73 00 | Original Japanese Hex + マ ッ チ | Original Japanese Text +M A T C H | New English Text +17 0B 1E 0D 12 | New English Hex + +。 " +Speed +$7EBD8 (Line 1) +00 8C 00 8B | Original Japanese Hex + 。 " | Original Japanese Text +T E X T | New English Text +1E 0F 22 1E | New English Hex +すぴーど +$7EBDF (Line 2) +60 78 82 67 | Original Japanese Hex +す ひ ー と | Original Japanese Text + S P D | New English Text +00 1D 1A 0E | New English Hex +| +はやい +Fast +$7F8A7 +77 34 26 | Original Japanese Hex +は や い | Original Japanese Text +F S T | New English Text +10 1D 1E | New English Hex +| +ふつう +Normal +$7F9AB +79 65 27 | Original Japanese Hex +ふ つ う | Original Japanese Text +N O R | New English Text +18 19 1C | New English Hex +| +おそい +Slow +$7F9AF +29 62 26 | Original Japanese Hex +お そ い | Original Japanese Text +S L W | New English Text +1D 16 21 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CourseSelect.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CourseSelect.txt new file mode 100644 index 00000000..0e477de9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/CourseSelect.txt @@ -0,0 +1,59 @@ +さいしょに プレイするコースをえらんでね! +It choose the course to play to specification! +By the way, one course has become a six-hole +$7BBA9 (Line 1) +5E 26 5F C7 2B 00 BD 54 40 60 39 6C 82 6F 3D 28 37 3E 9B 2D 85 | Original Japanese Hex +さ い し ょ に プ レ イ す る コ ー ス を え ら ん で ね ! | Original Japanese Text +C H O O S E A C O U R S E T Y P E ! | New English Text +0D 12 19 19 1D 0E 00 0B 00 0D 19 1F 1C 1D 0F 00 1E 23 1A 0F 85 | New English Hex +ちなみに 1コースは6ホールになってます +$7BBC2 (Line 2) +64 2A 30 2B 00 02 6C 82 6F 77 07 80 82 53 2B 2A C8 66 2F 60 | Original Japanese Hex +ち な み に 1 コ ー ス は 6 ホ ー ル に な っ て ま す | Original Japanese Text +S I X H O L E S P E R C O U R S E | New English Text +1D 13 22 00 12 19 16 0F 1D 00 1A 0F 1C 00 0D 19 1F 1C 1D 0F | New English Hex + +このコースは さばくのおおいところよ +This course is placed in a large desert +Take care not to get your leg stuck in the sand! +$7B758 (Line 1) +5D 2E 6C 82 6F 77 00 5E AC 5B 2E 29 29 26 67 5D 3B 36 | Original Japanese Hex +こ の コ ー ス は さ ば く の お お い と こ ろ よ | Original Japanese Text +D E S E R T C O U R S E . T R Y | New English Text +0E 0F 1D 0F 1C 1E 00 0D 19 1F 1C 1D 0F 88 00 1E 1C 23 | New English Hex +すなにあしをとられないようにねっ! +$7B76E (Line 2) +60 2A 2B 25 5F 3D 67 37 3A 2A 26 36 27 2B 2D C8 85 | Original Japanese Hex +す な に あ し を と ら れ な い よ う に ね っ ! | Original Japanese Text +N O T T O G E T S T U C K ! | New English Text +18 19 1E 00 1E 19 00 11 0F 1E 00 1D 1E 1F 0D 15 85 | New English Hex + +このコースはジャングルコースですわ +This course is a jungle course I +It'll have you addicted to rough If you do not care +$7B782 (Line 1) +5D 2E 6C 82 6F 77 A3 CE 58 9F 53 6C 82 6F 9B 60 3C | Original Japanese Hex +こ の コ ー ス は ジ ャ ン グ ル コ ー ス で す わ | Original Japanese Text +J U N G L E C O U R S E . I T S | New English Text +14 1F 18 11 16 0F 00 0D 19 1F 1C 1D 0F 88 13 1E 1D | New English Hex +きをつけてないと ラフにはまっちゃいますわ +$7B797 (Line 2) +5A 3D 65 5C 66 2A 26 67 00 51 7E 2B 77 2F C8 64 C5 26 2F 60 3C | Original Japanese Hex +き を つ け て な い と ラ フ に は ま っ ち ゃ い ま す わ | Original Japanese Text +E A S Y T O L A N D I N R O U G H | New English Text +0F 0B 1D 23 00 1E 19 00 16 0B 18 0E 00 13 18 00 1C 19 1F 11 12 | New English Hex + +このコースはでっかいみずうみのあるコースよ +This course is by a huge lake +It's a water hazard if you do not care! +$7B7AF (Line 1) +5D 2E 6C 82 6F 77 9B C8 59 26 30 95 27 30 2E 25 39 6C 82 6F 36 | Original Japanese Hex +こ の コ ー ス は で っ か い み ず う み の あ る コ ー ス よ | Original Japanese Text +L A K E C O U R S E . T A K E C A R E | New English Text +16 0B 15 0F 00 0D 19 1F 1C 1D 0F 88 1E 0B 15 0F 00 0D 0B 1C 0F | New English Hex +きをつけないと ウォーターハザードですわ! +$7B7C8 (Line 2) +5A 3D 65 5C 2A 26 67 00 41 CD 82 72 82 7C A2 82 AB 9B 60 3C 85 | Original Japanese Hex +き を つ け な い と ウ ォ ー タ ー ハ ザ ー ド で す わ ! | Original Japanese Text +N O T T O L A N D I N W A T E R ! | New English Text +18 19 1E 00 1E 19 00 16 0B 18 0E 00 13 18 00 21 0B 1E 0F 1C 85 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/EndHole.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/EndHole.txt new file mode 100644 index 00000000..aee293e3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/EndHole.txt @@ -0,0 +1,47 @@ +とーたるすこあ +Total Score +$7DB7B +67 82 63 39 60 5D 25 | Original Japanese Hex +と ー た る す こ あ | Original Japanese Text +O V E R A L L | New English Text +19 20 0F 1C 0B 16 16 | New English Hex + +しょうきん +Prize +$7DB8F +5F C7 27 5A 3E | Original Japanese Hex +し ょ う き ん | Original Japanese Text +P R I Z E | New English Text +1A 1C 13 24 0F | New English Hex + +じゃら +Score +$7DB9D +94 C5 37 | Original Japanese Hex +じ ゃ ら | Original Japanese Text +P T S | New English Text +1A 1E 1D | New English Hex + +BOGGY +BOGEY +$7F67D +00 00 00 0C 19 11 11 23 | Original Japanese Hex + B O G G Y | Original Japanese Text + B O G E Y | New English Text +00 00 00 0C 19 11 0F 23 | New English Hex + +DOUBLE BOGGY +DOUBLE BOGEY +$7F686 +0E 19 1F 0C 16 0F 00 0C 19 11 11 23 | Original Japanese Hex +D O U B L E B O G G Y | Original Japanese Text +D O U B L E B O G E Y | New English Text +0E 19 1F 0C 16 0F 00 0C 19 11 0F 23 | New English Hex + +TRIPLE BOGGY +TRIPLE BOGEY +$7F693 +1E 1C 13 1A 16 0F 00 0C 19 11 11 23 | Original Japanese Hex +T R I P L E B O G G Y | Original Japanese Text +T R I P L E B O G E Y | New English Text +1E 1C 13 1A 16 0F 00 0C 19 11 0F 23 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/HiScore.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/HiScore.txt new file mode 100644 index 00000000..17f96133 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/HiScore.txt @@ -0,0 +1,159 @@ +おおわるさ +Badass, multiply +$0CBA2 +29 29 3C 39 5E | Original Japanese Hex +お お わ る さ | Original Japanese Text +B A S S X | New English Text +0C 0B 1D 1D 22 | New English Hex + +ヨロヨロイ +Yoroyoroi +$0CBAA +50 55 50 55 40 | Original Japanese Hex +ヨ ロ ヨ ロ イ | Original Japanese Text +Y O R O I | New English Text +23 19 1C 19 13 | New English Hex + +マドラゴラ +Madoragora +$0CBB2 +49 AB 51 A1 51 | Original Japanese Hex +マ ド ラ ゴ ラ | Original Japanese Text +M G O R A | New English Text +17 11 19 1C 0B | New English Hex + +いえてぃ +Yeti +$0CBBA +26 28 66 C1 00 | Original Japanese Hex +い え て ぃ | Original Japanese Text +Y E T I | New English Text +23 0F 1E 13 00 | New English Hex + +てぃあな! +Tiana! +$0CBC2 +66 C1 25 2A 85 | Original Japanese Hex +て ぃ あ な ! | Original Japanese Text +T I A N A | New English Text +1E 13 0B 18 0B | New English Hex + +ゆきんこ +Yu safe +$0CBCA +35 5A 3E 5D 00 | Original Japanese Hex +ゆ き ん こ | Original Japanese Text +Y U S A F | New English Text +23 1F 1D 0B 10 | New English Hex + +すかるまん +Skull Man +$0CBD2 +60 59 39 2F 3E | Original Japanese Hex +す か る ま ん | Original Japanese Text +S K U L L | New English Text +1D 15 1F 16 16 | New English Hex + +かにお +Get to or +$0CBDA +59 2B 29 00 00 | Original Japanese Hex +か に お | Original Japanese Text +G E T O R | New English Text +11 0F 1E 19 1C | New English Hex + +ダミやん +Yan dummy +$0CBE2 +A7 4A 34 3E 00 | Original Japanese Hex +ダ ミ や ん | Original Japanese Text +Y A N D U | New English Text +23 0B 18 0E 1F | New English Hex + +カードだす +Carddass +$0CBEA +68 82 AB 98 60 | Original Japanese Hex +カ ー ド だ す | Original Japanese Text +C D A S S | New English Text +0D 0E 0B 1D 1D | New English Hex + +マンドラー +Mandora +$0CC10 +49 58 AB 51 82 | Original Japanese Hex +マ ン ド ラ ー | Original Japanese Text +M D O R A | New English Text +17 0E 19 1C 0B | New English Hex + +さばちーの +Repellent over the +$0CC18 +5E AC 64 82 2E | Original Japanese Hex +さ ば ち ー の | Original Japanese Text +R E P E L | New English Text +1C 0F 19 0F 16 | New English Hex + +ゆーに! +To You! +$0CC20 +35 82 2B 85 00 | Original Japanese Hex +ゆ ー に ! | Original Japanese Text +T O Y O U | New English Text +1E 19 23 19 1F | New English Hex + +ゆきうさめ +Yuki rabbit order +$0CC28 +35 5A 27 5E 32 | Original Japanese Hex +ゆ き う さ め | Original Japanese Text +Y U K I R | New English Text +23 1F 15 13 1C | New English Hex + +らごら +Ragora +$0CC30 +37 92 37 00 00 | Original Japanese Hex +ら ご ら | Original Japanese Text +R G O R A | New English Text +1C 11 19 1C 0B | New English Hex + +かりんこ +Come Karin +$0CC38 +59 38 3E 5D 00 | Original Japanese Hex +か り ん こ | Original Japanese Text +K A R I N | New English Text +15 0B 1C 13 18 | New English Hex + +ひさこ +Toshiko +$0CC40 +78 5E 5D 00 00 | Original Japanese Hex +ひ さ こ | Original Japanese Text +T O S H I | New English Text +1E 19 1D 12 13 | New English Hex + +あずさ +Azusa +$0CC48 +25 95 5E 00 00 | Original Japanese Hex +あ ず さ | Original Japanese Text +A Z U S A | New English Text +0B 24 1F 1D 0B | New English Hex + +GOごん +GO you do +$0CC50 +11 19 92 3E 00 | Original Japanese Hex +G O ご ん | Original Japanese Text +G O U D O | New English Text +11 19 1F 0E 19 | New English Hex + +のっとるだ +Nikki's ride +$0CC58 +2E C8 67 39 98 | Original Japanese Hex +の っ と る だ | Original Japanese Text +N I K K I | New English Text +18 13 15 15 13 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/MatchPlayRules.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/MatchPlayRules.txt new file mode 100644 index 00000000..31863783 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/MatchPlayRules.txt @@ -0,0 +1,81 @@ +ルール の せつめい +Rule Description +$7EE42 +53 82 53 00 2E 00 61 65 32 26 | Original Japanese Hex +ル ー ル の せ つ め い | Original Japanese Text +G A M E R U L E S | New English Text +11 0B 17 0F 00 1C 1F 16 0F 1D | New English Hex + +.マッチプレイモード +Match Play Mode +$7D0F8 +00 00 00 00 00 00 88 49 D1 73 BD 54 40 4D 82 AB | Original Japanese Hex + . マ ッ チ プ レ イ モ ー ド | Original Japanese Text +. M A T C H P L A Y M O D E | New English Text +88 17 0B 1E 0D 12 00 1A 16 0B 23 00 17 19 0E 0F | New English Hex + +2PLAYたいせんモードで ホールごとの だすうで +Will be the value of the player were to win the final number of strokes per hole decided the game in battle mode 2PLAY +$7D10C (Line 1) +03 1A 16 0B 23 63 26 61 3E 4D 82 AB 9B 00 80 82 53 92 67 2E 00 98 60 27 9B | Original Japanese Hex +2 P L A Y た い せ ん モ ー ド で ホ ー ル ご と の だ す う で | Original Japanese Text +2 P L A Y E R S E A R N P O I N T S F O R | New English Text +03 00 1A 16 0B 23 0F 1C 1D 00 0F 0B 1C 18 00 1A 19 13 18 1E 1D 00 10 19 1C | New English Hex +しょうぶをきめ さいしゅうてきに かちすうがおおかった +$7D129 (Line 2) +5F C7 27 AE 3D 5A 32 00 5E 26 5F C6 27 66 5A 2B 00 59 64 60 27 8E 29 29 59 C8 63 | Original Japanese Hex +し ょ う ぶ を き め さ い し ゅ う て き に か ち す う が お お か っ た | Original Japanese Text +E V E R Y H O L E W O N A H I G H S C O R E | New English Text +0F 20 0F 1C 23 00 12 19 16 0F 00 21 19 18 00 0B 00 12 13 11 12 00 1D 0D 19 1C 0F | New English Hex +プレイヤーのかちになります +$7D148 (Line 3) +BD 54 40 4E 82 2E 59 64 2B 2A 38 2F 60 | Original Japanese Hex +プ レ イ ヤ ー の か ち に な り ま す | Original Japanese Text +W I N S T H E G A M E | New English Text +21 13 18 1D 00 1E 12 0F 00 11 0B 17 0F | New English Hex + +.PROモード.ノーマルモードのちがいについて +. For the difference in PRO mode . Normal mode +$7D15A +88 1A 1C 19 4D 82 AB 88 48 82 49 53 4D 82 AB 2E 64 8E 26 2B 65 26 66 | Original Japanese Hex +. P R O モ ー ド . ノ ー マ ル モ ー ド の ち が い に つ い て | Original Japanese Text +. P R O M O D E - D I F F E R E N C E S | New English Text +88 1A 1C 19 00 17 19 0E 0F 00 82 00 0E 13 10 10 0F 1C 0F 18 0D 0F 1D | New English Hex + +PROモードはノーマルモードと くらべて.. +Compared with the normal mode .. PRO mode +$7D175 +1A 1C 19 4D 82 AB 77 48 82 49 53 4D 82 AB 67 00 5B 37 AF 66 88 88 | Original Japanese Hex +P R O モ ー ド は ノ ー マ ル モ ー ド と く ら べ て . . | Original Japanese Text +B E T W E E N A M A T E U R M O D E . . | New English Text +0C 0F 1E 21 0F 0F 18 00 0B 17 0B 1E 0F 1F 1C 00 17 19 0E 0F 88 88 | New English Hex + +かぜのむきと そのちからのあたいが かなりシビアに +The value of quite severe and their direction of the wind power +$7D18F (Line 1) +59 96 2E 31 5A 67 00 62 2E 64 59 37 2E 25 63 26 8E 00 59 2A 38 6E B2 3F 2B | Original Japanese Hex +か ぜ の む き と そ の ち か ら の あ た い が か な り シ ビ ア に | Original Japanese Text +W I N D D I R E C T I O N / S P E E D M U C H | New English Text +21 13 18 0E 00 0E 13 1C 0F 0D 1E 13 19 18 87 1D 1A 0F 0F 0E 00 17 1F 0D 12 | New English Hex +なっています ノーマルモードでは ものたりない.. +In normal mode has become unsatisfactory is .. +$7D1AC (Line 2) +2A C8 66 26 2F 60 00 48 82 49 53 4D 82 AB 9B 77 00 33 2E 63 38 2A 26 88 88 | Original Japanese Hex +な っ て い ま す ノ ー マ ル モ ー ド で は も の た り な い . . | Original Japanese Text +M O R E S E V E R E T H A N N O R M A L . . | New English Text +17 19 1C 0F 00 1D 0F 20 0F 1C 0F 00 1E 12 0B 18 00 18 19 1C 17 0B 16 88 88 | New English Hex + +というかた よりスリリングなプレイをおのぞみのかた +Those who want to play more thrilling than that +$7D1C9 (Line 1) +67 26 27 59 63 00 36 38 6F 52 52 58 9F 2A BD 54 40 3D 29 2E 97 30 2E 59 63 | Original Japanese Hex +と い う か た よ り ス リ リ ン グ な プ レ イ を お の ぞ み の か た | Original Japanese Text +I F Y O U L I K E T H R I L L S T H E R E | New English Text +13 10 00 23 19 1F 00 16 13 15 0F 00 1E 12 1C 13 16 16 1D 00 1E 12 0F 1C 0F | New English Hex +などでも じゅうぶんに たのしめるモードです! +This mode is also plenty to enjoy, such as! +$7D1E6 (Line 2) +2A 9C 9B 33 00 94 C6 27 AE 3E 2B 00 63 2E 5F 32 39 4D 82 AB 9B 60 85 | Original Japanese Hex +な ど で も じ ゅ う ぶ ん に た の し め る モ ー ド で す ! | Original Japanese Text +I S P L E N T Y I N T H I S M O D E ! | New English Text +13 1D 00 1A 16 0F 18 1E 23 00 13 18 00 1E 12 13 1D 00 17 19 0E 0F 85 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/OpenPlay.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/OpenPlay.txt new file mode 100644 index 00000000..beebbb13 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/OpenPlay.txt @@ -0,0 +1,149 @@ +どらぼっちゃん OPEN +young master Open +$7FBC3 +9C 37 B0 C8 64 C5 3E 00 19 1A 0F 18 | Original Japanese Hex +ど ら ぼ っ ち ゃ ん O P E N | Original Japanese Text +M A S T E R S O P E N | New English Text +17 0B 1D 1E 0F 1C 1D 00 19 1A 0F 18 | New English Hex + +PLAYにんずう +Number of Players +$7E804 +1A 16 0B 23 2B 3E 95 27 | Original Japanese Hex +P L A Y に ん ず う | Original Japanese Text +P L A Y E R S ? | New English Text +1A 16 0B 23 0F 1C 1D 86 | New English Hex +|| +ゲームプレイにんずうをきめてね!... +Decide the number of people playing games!... +$7B3E8 (Line 1) +A0 82 4B BD 54 40 2B 3E 95 27 3D 5A 32 66 2D 85 88 88 88 | Original Japanese Hex +ゲ ー ム プ レ イ に ん ず う を き め て ね ! . . . | Original Japanese Text +S E T S U P P L A Y E R S ! . . . | New English Text +1D 0F 1E 1D 00 1F 1A 00 1A 16 0B 23 0F 1C 1D 85 88 88 88 | New English Hex +だけどマッチプレイは 2PLAYのみです +But match play is only 2 Player +$7B3FF (Line 2) +98 5C 9C 49 D1 73 BD 54 40 77 00 03 1A 16 0B 23 2E 30 9B 60 | Original Japanese Hex +だ け ど マ ッ チ プ レ イ は 2 P L A Y の み で す | Original Japanese Text +M A T C H P L A Y I S 2 P L A Y E R | New English Text +17 0B 1E 0D 12 1A 16 0B 23 00 13 1D 00 03 1A 16 0B 23 0F 1C | New English Hex + +プレイHOLEすう +Number of holes? +$7E81D +BD 54 40 12 19 16 0F 60 27 | Original Japanese Hex +プ レ イ H O L E す う | Original Japanese Text +N O . H O L E S ? | New English Text +18 19 88 12 19 16 0F 1D 86 | New English Hex +|| +プレイするホールのかずを えらんでね +Select the number of holes to play +$7B416 +BD 54 40 60 39 80 82 53 2E 59 95 3D 00 28 37 3E 9B 2D | Original Japanese Hex +プ レ イ す る ホ ー ル の か ず を え ら ん で ね | Original Japanese Text +P I C K H O L E S T O P L A Y | New English Text +1A 13 0D 15 00 12 19 16 0F 1D 00 1E 19 00 1A 16 0B 23 | New English Hex + +モード +Mode +$7E835 +4D 82 AB | Original Japanese Hex +モ ー ド | Original Japanese Text +S E T | New English Text +1D 0F 1E | New English Hex +| +ノーマル +Normal +$7F946 +48 00 82 00 49 00 53 | Original Japanese Hex +ノ ー マ ル | Original Japanese Text +A M A T E U R | New English Text +0B 17 0B 1E 0F 1F 1C | New English Hex +|| +ゲームモードを えらんでね! +Select game mode! +$7B42B (Line 1) +A0 82 4B 4D 82 AB 3D 00 28 37 3E 9B 2D 85 | Original Japanese Hex +ゲ ー ム モ ー ド を え ら ん で ね ! | Original Japanese Text +S E T G A M E M O D E ! | New English Text +1D 0F 1E 00 11 0B 17 0F 00 17 19 0E 0F 85 | New English Hex +いっておくけど PROはむずいぞぁ! +PRO HAMUZU and keep going, but I'll go outside. or However you say, as for PRO the [mu] [zu] to be, the [a]! +$7B43D (Line 2) +26 C8 66 29 5B 5C 9C 00 1A 1C 19 77 31 95 26 97 C4 85 | Original Japanese Hex +い っ て お く け ど P R O は む ず い ぞ ぁ ! | Original Japanese Text +T R Y P R O C H A L L E N G E ! | New English Text +1E 1C 23 00 1A 1C 19 00 0D 12 0B 16 16 0F 18 11 0F 85 | New English Hex + +もじスピード +Text Speed +$7E83D +33 94 6F BC 82 AB | Original Japanese Hex +も じ ス ピ ー ド | Original Japanese Text +T E X T S ? | New English Text +1E 0F 22 1E 1D 86 | New English Hex +| +はやい +Fast +$7F95C +77 00 34 00 26 | Original Japanese Hex +は や い | Original Japanese Text +F A S T | New English Text +10 0B 1D 1E 00 | New English Hex +| +ふつう +Normal +$7F962 +79 00 65 00 27 | Original Japanese Hex +ふ つ う | Original Japanese Text +N O R M | New English Text +18 19 1C 17 00 | New English Hex +| +おそい +Slow +$7F968 +29 00 62 00 26 | Original Japanese Hex +お そ い | Original Japanese Text +S L O W | New English Text +1D 16 19 21 00 | New English Hex +|| +もじの ひょうじスピードをきめてね +Set text display speed +$7B452 +33 94 2E 00 78 C7 27 94 6F BC 82 AB 3D 5A 32 66 2D | Original Japanese Hex +も じ の ひ ょ う じ ス ピ ー ド を き め て ね | Original Japanese Text +S E T M E S S A G E S P E E D | New English Text +1D 0F 1E 00 17 0F 1D 1D 0B 11 0F 00 1D 1A 0F 0F 0E | New English Hex + +BGM.モード +BGM.Mode +$7E848 +0C 11 17 88 4D 82 AB | Original Japanese Hex +B G M . モ ー ド | Original Japanese Text +B G M . S E T | New English Text +0C 11 17 88 1D 0F 1E | New English Hex +| +ステレオ +Stereo +$7F972 +6F 00 75 00 54 00 43 | Original Japanese Hex +ス テ レ オ | Original Japanese Text +S T E R E O | New English Text +1D 1E 0F 1C 0F 19 00 | New English Hex +| +モノラル +Monaural +$7F97A +4D 00 48 00 51 00 53 | Original Japanese Hex +モ ノ ラ ル | Original Japanese Text + M O N O | New English Text +00 17 19 18 19 00 00 | New English Hex +|| +サウンドモードをきめてね! +Decide the sound mode! +$7B466 +6D 41 58 AB 4D 82 AB 3D 5A 32 66 2D 85 | Original Japanese Hex +サ ウ ン ド モ ー ド を き め て ね ! | Original Japanese Text +S O U N D O U T P U T ! | New English Text +1D 19 1F 18 0E 00 19 1F 1E 1A 1F 1E 85 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerSelect.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerSelect.txt new file mode 100644 index 00000000..f43971a5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerSelect.txt @@ -0,0 +1,219 @@ +どらぼっちゃん +Spike +$7F3E9 +9C 37 B0 C8 64 C5 3E | Original Japanese Hex +ど ら ぼ っ ち ゃ ん | Original Japanese Text +S P I K E | New English Text +1D 1A 13 15 0F 00 00 | New English Hex +| +カミーラ +Camilla or Camelia (from twisted tales) +$7F3F1 +68 4A 82 51 00 00 00 | Original Japanese Hex +カ ミ ー ラ | Original Japanese Text +C A M E L I A | New English Text +0D 0B 17 0F 16 13 0B | New English Hex +| +コワル +Kowal or Hydra (from twisted tales) +$7F3F9 +6C 56 53 00 00 00 00 | Original Japanese Hex +コ ワ ル | Original Japanese Text +H Y D R A | New English Text +12 23 0E 1C 0B 00 00 | New English Hex +| +にんにくん +Garlic or Killer Clove (from twisted tales) +$7F401 +2B 3E 2B 5B 3E 00 00 | Original Japanese Hex +に ん に く ん | Original Japanese Text +K . C L O V E | New English Text +15 88 0D 16 19 20 0F | New English Hex +| +しつじちょう +Professor Steam +$7F409 +5F 65 94 64 C7 27 00 | Original Japanese Hex +し つ じ ち ょ う | Original Japanese Text +P . S T E A M | New English Text +1A 88 1D 1E 0F 0B 17 | New English Hex +| +ひょうひょう +Felina +$7F411 +78 C7 27 78 C7 27 00 | Original Japanese Hex +ひ ょ う ひ ょ う | Original Japanese Text +F E L I N A | New English Text +10 0F 16 13 18 0B 00 | New English Hex + +パワー +Power +$7E5EE +BB 56 82 | Original Japanese Hex +パ ワ ー | Original Japanese Text +H I T | New English Text +12 13 1E | New English Hex +| +テクニック +Technique +$7E601 +75 6A 45 D1 6A | Original Japanese Hex +テ ク ニ ッ ク | Original Japanese Text +S K I L L | New English Text +1D 15 13 16 16 | New English Hex +| +スタンス +Stance +$7E614 +6F 72 58 6F | Original Japanese Hex +ス タ ン ス | Original Japanese Text +P O S E | New English Text +1A 19 1D 0F | New English Hex +| +スピン +Spin +$7E627 +6F BC 58 | Original Japanese Hex +ス ピ ン | Original Japanese Text +S P N | New English Text +1D 1A 18 | New English Hex +| +すペしゃる +Special +$7E63C +60 B9 5F C5 39 | Original Japanese Hex +す ペ し ゃ る | Original Japanese Text +P O W E R | New English Text +1A 19 21 0F 1C | New English Hex + +しばめのききめがはんぶん +Turf eye/sprout Field Efficiancy half +$7F7DD +5F AC 32 2E 5A 5A 32 8E 77 3E AE 3E | Original Japanese Hex +し ば め の き き め が は ん ぶ ん | Original Japanese Text +G R A S S D R I V E S | New English Text +11 1C 0B 1D 1D 00 0E 1C 13 20 0F 1D | New English Hex +| +ヘいきんてきなちからをもったプレイヤーよ +Player with a well of strength that I come onto Oh... Will do for beginners! +$7B477 (Line 1) +7A 26 5A 3E 66 5A 2A 64 59 37 3D 33 C8 63 BD 54 40 4E 82 36 | Original Japanese Hex +ヘ い き ん て き な ち か ら を も っ た プ レ イ ヤ ー よ | Original Japanese Text +H E I S E V E N L Y S K I L L E D | New English Text +12 0F 00 13 1D 00 0F 20 0F 18 16 23 00 1D 15 13 16 16 0F 0E | New English Hex +まあ。。。しょしんしゃむけかなっ! +$7B48F (Line 2) +2F 25 88 88 88 5F C7 5F 3E 5F C5 31 5C 59 2A C8 85 | Original Japanese Hex +ま あ 。 。 。 し ょ し ん し ゃ む け か な っ ! | Original Japanese Text +B E G I N N E R S C H O I C E ! | New English Text +0C 0F 11 13 18 18 0F 1C 1D 00 0D 12 19 13 0D 0F 85 | New English Hex + +ラフでのショットがとくい +Is good at shots in the rough +$7F7A9 +51 7E 9B 2E 6E D0 D1 76 8E 67 5B 26 | Original Japanese Hex +ラ フ で の シ ョ ッ ト が と く い | Original Japanese Text +R O U G H S H O T S | New English Text +1C 19 1F 11 12 00 1D 12 19 1E 1D 00 | New English Hex +| +パワーはないけど そのぶんを わざで +In any portion I do not have power skills I had enough Game to cover +$7B4A3 (Line 1) +BB 56 82 77 2A 26 5C 9C 00 62 2E AE 3E 3D 00 3C 93 9B | Original Japanese Hex +パ ワ ー は な い け ど そ の ぶ ん を わ ざ で | Original Japanese Text +N O T T O O M U C H P O W E R | New English Text +18 19 1E 00 1E 19 19 00 17 1F 0D 12 00 1A 19 21 0F 1C | New English Hex +じゅうぶんにカバーしてる プレイヤーよ +$7B4B9 (Line 2) +94 C6 27 AE 3E 2B 68 B1 82 5F 66 39 00 BD 54 40 4E 82 36 | Original Japanese Hex +じ ゅ う ぶ ん に カ バ ー し て る プ レ イ ヤ ー よ | Original Japanese Text +B U T P L E N T Y O F S K I L L | New English Text +0C 1F 1E 00 1A 16 0F 18 1E 23 00 19 10 00 1D 15 13 16 16 | New English Hex + +とくになし +None in particular +$7F79C +67 5B 2B 2A 5F 00 00 00 00 00 00 00 | Original Japanese Hex +と く に な し | Original Japanese Text +N O N E S P E C I A L | New English Text +18 19 18 0F 00 1D 1A 0F 0D 13 0B 16 | New English Hex +| +ちょっとぶきようだけど パワーさいきょうの +It is the strongest power but a little clumsy Best player to knock out please! +$7B4CF (Line 1) +64 C7 C8 67 AE 5A 36 27 98 5C 9C 00 BB 56 82 5E 26 5A c7 27 2E | Original Japanese Hex +ち ょ っ と ぶ き よ う だ け ど パ ワ ー さ い き ょ う の | Original Japanese Text +H A S T H E S T R O N G E S T H I T | New English Text +12 0B 1D 00 1E 12 0F 00 1D 1E 1C 29 18 11 0F 1D 1E 00 12 13 1E | New English Hex +プレイヤーよ かっとばしたいひとはどうぞ! +$7B4E8 (Line 2) +BD 54 40 4E 82 36 00 59 C8 67 AC 5F 63 26 78 67 77 9C 27 97 85 | Original Japanese Hex +プ レ イ ヤ ー よ か っ と ば し た い ひ と は ど う ぞ ! | Original Japanese Text +C A N B E A B I T C L U M S Y ! ! | New English Text +0D 0B 18 00 0C 0F 00 0B 00 0C 13 1E 00 0C 16 1F 17 1D 23 85 85 | New English Hex + +スーパーショットがうてる +Super shot strike/wedge +$7F7C3 +6F 82 BB 82 6E D0 D1 76 8E 27 66 39 | Original Japanese Hex +ス ー パ ー シ ョ ッ ト が う て る | Original Japanese Text +W E D G E S T R I K E | New English Text +21 0F 0E 11 0F 00 1D 1E 1C 13 15 0F | New English Hex +| +パワーはひくいけど うちにひめたちからを +While the small from his power, but lower in If you should lose to anyone +$7B500 (Line 1) +BB 56 82 77 78 5B 26 5C 9C 00 27 64 2B 78 32 63 64 59 37 3D | Original Japanese Hex +パ ワ ー は ひ く い け ど う ち に ひ め た ち か ら を | Original Japanese Text +S M A L L I N S T A T U R E B U T | New English Text +1D 17 0A 16 16 00 13 18 00 1D 1E 0B 1E 1F 1C 0F 00 0C 1F 1E | New English Hex +かいほうすれば だれにもまけないわ +$7B518 (Line 2) +59 26 7B 27 60 3A AC 00 98 3A 2B 33 2F 5C 2A 26 3C | Original Japanese Hex +か い ほ う す れ ば だ れ に も ま け な い わ | Original Japanese Text +H A S A G O O D S T A N C E | New English Text +12 0B 1D 00 0B 00 11 19 19 0E 00 1D 1E 0B 18 0D 0F | New English Hex + +バンカーショットがとくい +Is good at bunker shots +$7F7B6 +B1 58 68 82 6E D0 D1 76 8E 67 5B 26 | Original Japanese Hex +バ ン カ ー シ ョ ッ ト が と く い | Original Japanese Text +B U N K E R S H O T S | New English Text +0C 1F 18 15 0F 1C 00 1D 12 19 1E 1D | New English Hex +| +スピンにかけては まかいいち..しかも +A master of spin between bunker shots Dust it over the bunker +$7B52C (Line 1) +6F BC 58 2B 59 5C 66 77 00 2F 59 26 26 64 88 88 5F 59 33 | Original Japanese Hex +ス ピ ン に か け て は ま か い い ち . . し か も | Original Japanese Text +S P I N S T H E B A L L W H E N | New English Text +1D 1A 13 18 1D 00 1E 12 0F 00 0C 0B 16 16 00 21 12 0F 18 | New English Hex +バンカーショットの たつじんよ +$7B543 (Line 2) +B1 58 68 82 6E D0 D1 76 2E 00 63 65 94 3E 36 | Original Japanese Hex +バ ン カ ー シ ョ ッ ト の た つ じ ん よ | Original Japanese Text +O U T O F A B U N K E R | New English Text +19 1F 1E 00 19 10 00 0B 00 0C 1F 18 15 0F 1C | New English Hex + +かぜをあやつる +Manipulate the wind +$7F7D0 +59 96 3D 25 34 65 39 00 00 00 00 00 | Original Japanese Hex +か ぜ を あ や つ る | Original Japanese Text +W I N D Y S T R I K E | New English Text +21 13 18 0E 23 00 1D 1E 1C 13 15 0F | New English Hex +| +のうりょくは そんなに めだたないけど +Capacity is so obvious but Can manipulate the wind +$7B555 (Line 1) +2E 27 38 C7 5B 77 00 62 3E 2A 2B 00 32 98 63 2A 26 5C 9C | Original Japanese Hex +の う り ょ く は そ ん な に め だ た な い け ど | Original Japanese Text +M A N I P U L A T E S A W I N D Y | New English Text +17 0B 18 13 1A 1F 16 0B 1E 0F 1D 00 0B 00 21 13 18 0E 23 | New English Hex +かぜをあやつることができるわ +$7B56C (Line 2) +59 96 3D 25 34 65 39 5D 67 8E 9B 5A 39 3C | Original Japanese Hex +か ぜ を あ や つ る こ と が で き る わ | Original Japanese Text +S H O T V E R Y W E L L | New English Text +1D 12 19 1E 00 20 0F 1C 23 00 21 0F 16 16 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerText.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerText.txt new file mode 100644 index 00000000..cb7acf26 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/PlayerText.txt @@ -0,0 +1,220 @@ +ぼっくんに おまかせで +In leave it to Mr. offs +Offs do more! +$78007 (Line 1) +B0 C8 5B 3E 2B 00 29 2F 59 61 9B | Original Japanese Hex +ぼ っ く ん に お ま か せ で | Original Japanese Text +T R Y T O D O M Y | New English Text +1E 1C 23 00 1E 19 0E 19 00 17 23 | New English Hex +ぼっくん! +$78016 (Line 2) +B0 C8 5B 3E 85 | Original Japanese Hex +ぼ っ く ん ! | Original Japanese Text +B E S T ! | New English Text +0C 0F 1D 1E 85 | New English Hex + +ぼっくんの でばんで +In turn do more of offs +Offs do more! +$7801F (Line 1) +B0 C8 5B 3E 2E 00 9B AC 3E 9B | Original Japanese Hex +ぼ っ く ん の で ば ん で | Original Japanese Text +I T R Y M U C H | New English Text +13 00 1E 1C 23 00 17 1F 0D 12 | New English Hex +ぼっくん! +$7802D (Line 2) +B0 C8 5B 3E 85 | Original Japanese Hex +ぼ っ く ん ! | Original Japanese Text +M O R E ! | New English Text +17 19 1C 0F 85 | New English Hex + +まけないで ぼっくんよー! +I will try as much as possible not to give up! +$78036 +2F 5C 2A 26 9B 00 B0 C8 5B 3E 36 82 85 | Original Japanese Hex +ま け な い で ぼ っ く ん よ ー ! | Original Japanese Text +W O N T G I V E U P ! | New English Text +21 19 18 1E 00 11 13 20 0F 00 1F 1A 85 | New English Hex + +もっと もっと つよくなって +Become more strong +I 'll aim to be a pro golfer! +$78061 (Line 1) +33 C8 67 00 33 C8 67 00 65 36 5B 2A C8 66 | Original Japanese Hex +も っ と も っ と つ よ く な っ て | Original Japanese Text +B E C O M E S T R O N G ! | New English Text +0C 0F 0D 19 17 0F 00 1D 1E 1C 19 18 11 85 | New English Hex +わたし プロゴルファーをめざすわっ!! +$78073 (Line 2) +3C 63 5F 00 BD 55 A1 53 7E C9 82 3D 32 93 60 3C C8 85 85 | Original Japanese Hex +わ た し プ ロ ゴ ル フ ァ ー を め ざ す わ っ ! ! | Original Japanese Text +I A I M T O B E A P R O ! ! | New English Text +13 00 0A 13 17 00 1E 19 00 0C 0F 00 0B 00 1A 1C 19 85 85 | New English Hex + +わたし ぜえーったい きろくをのこすわっ! +Wow want to keep a record Tsu er ze me! +$7808A +3C 63 5F 00 96 28 82 C8 63 26 00 5A 3B 5B 3D 2E 5D 60 3C C8 85 | Original Japanese Hex +わ た し ぜ え ー っ た い き ろ く を の こ す わ っ ! | Original Japanese Text +T R Y F O R A N E W R E C O R D ! | New English Text +1E 1C 23 00 10 19 1C 00 0B 00 18 0F 21 00 1C 0F 0D 19 1C 0E 85 | New English Hex + +よーし ちょうしが のってきたわ! +Luck-pusher is Alright I've been riding! +It's got this hole! +$780A3 (Line 1) +36 82 5F 00 64 C7 27 5F 8E 00 2E C8 66 5A 63 3C 85 | Original Japanese Hex +よ ー し ち ょ う し が の っ て き た わ ! | Original Japanese Text +T R Y M Y L U C K ! T H I S | New English Text +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? | New English Hex +このホール もらったわ! +$780B8 (Line 2) +5D 2E 80 82 53 00 33 37 C8 63 3C 85 | Original Japanese Hex +こ の ホ ー ル も ら っ た わ ! | Original Japanese Text +H O L E I S M I N E | New English Text +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 85 | New English Hex + +このてんさいプロゴルファー コワルさまの +The genius or a professional golfer Kowal is this +Do not be skip the waist looking at the ability! +$780E4 (Line 1) +5D 2E 66 3E 5E 26 BD 55 A1 53 7E C9 82 00 6C 56 53 5E 2F 2E | Original Japanese Hex +こ の て ん さ い プ ロ ゴ ル フ ァ ー コ ワ ル さ ま の | Original Japanese Text +S E E G E N I U S A S I P L A Y | New English Text +1D 0F 0F 00 11 0F 18 13 1F 1D 00 0B 1D 00 13 00 1A 16 0B 23 | New English Hex +じつりょくをみて こしをぬかすなよ! +$780FC (Line 2) +94 65 38 C7 5B 3D 30 66 00 5D 5F 3D 2C 59 60 2A 36 85 | Original Japanese Hex +じ つ り ょ く を み て こ し を ぬ か す な よ ! | Original Japanese Text +P R O F E S S I O N A L G O L F ! | New English Text +1A 1C 19 10 0F 1D 1D 13 19 18 0B 16 00 11 19 16 10 85 | New English Hex + +フッ...オレのでばんか... +hah... Now it's my turn... +$78112 +7E D1 88 88 88 43 54 2E 9B AC 3E 59 88 88 88 | Original Japanese Hex +フ ッ . . . オ レ の で ば ん か . . . | Original Japanese Text +H A . . . M Y T U R N . . . | New English Text +12 0B 88 88 88 17 23 00 1E 1F 1C 18 88 88 88 | New English Hex + +はっはっはっ..やっときたな コワルさまの +Kowal of various Na came finally Tsu .. ha ha ha +I'll show the real power! +$78125 (Line 1) +77 C8 77 C8 77 C8 88 88 34 C8 67 5A 63 2A 00 6C 56 53 5E 2F 2E | Original Japanese Hex +は っ は っ は っ . . や っ と き た な コ ワ ル さ ま の | Original Japanese Text +H E R E I C O M E . . . I W I L L | New English Text +12 0F 1C 0F 00 13 00 1D 19 17 0F 88 88 88 00 13 00 21 13 16 16 | New English Hex +しんのじつりょくをみせてやろう! +$7813E (Line 2) +5F 3E 2E 94 65 38 C7 5B 3D 30 61 66 34 3B 27 85 | Original Japanese Hex +し ん の じ つ り ょ く を み せ て や ろ う ! | Original Japanese Text +S H O W R E A L P O W E R ! | New English Text +1D 12 19 21 00 1C 0F 0B 16 00 1A 19 21 0F 1C 85 | New English Hex + +みー! みー! +Look over! See over! +$7818A +30 82 85 00 30 82 85 | Original Japanese Hex +み ー ! み ー ! | Original Japanese Text +L O O K I E ! | New English Text +16 19 19 15 13 0F 85 | New English Hex + +み..みいーっ! +See .. see I~tsu! +$78195 +30 88 88 30 26 82 C8 85 | Original Japanese Hex +み . . み い ー っ ! | Original Japanese Text +L O O K O N ! | New English Text +16 19 19 15 00 19 18 85 | New English Hex + +みみみいーっ! +The Yaa it has seen only look! +$781A1 +30 30 30 26 82 C8 85 | Original Japanese Hex +み み み い ー っ ! | Original Japanese Text +S E E M E ! | New English Text +1D 0F 0F 00 17 0F 85 | New English Hex + +どっこいしょっ..もお わしのでばんかね? +Heigh-Ho.. I guess turn your eagle also? +$781BF +9C C8 5D 26 5F C7 C8 88 88 33 29 00 3C 5F 2E 9B AC 3E 59 2D 86 | Original Japanese Hex +ど っ こ い し ょ っ . . も お わ し の で ば ん か ね ? | Original Japanese Text +C O U L D I T B E A N E A G L E ? | New English Text +0D 19 1F 16 0E 00 13 1E 00 0C 0F 00 0A 18 00 0F 0B 11 16 0F 86 | New English Hex + +やれやれ わしのしんのちからをみせなくては +Not show the true power of the an eagle is well +The Wow Wow uncertainties which stem of .. seems there or not .. +$781D8 (Line 1) +34 3A 34 3A 00 3C 5F 2E 5F 3E 2E 64 59 37 3D 30 61 2A 5B 66 77 | Original Japanese Hex +や れ や れ わ し の し ん の ち か ら を み せ な く て は | Original Japanese Text +I T S T I M E F O R T H E T R U E | New English Text +13 1E 1D 00 1E 13 17 0F 00 10 19 1C 00 1E 12 0E 00 1E 1C 1F 0F | New English Hex +いかんらしいのお..ふぉっふぉっ.. +$781F1 (Line 2) +26 59 3E 37 5F 26 2E 29 88 88 79 C4 C8 79 C4 C8 88 88 | Original Japanese Hex +い か ん ら し い の お . . ふ ぉ っ ふ ぉ っ . . | Original Japanese Text +P O W E R O F T H E E A G L E | New English Text +1A 19 21 0F 1C 00 1C 10 00 1E 12 0F 00 0F 0B 11 16 0F | New English Hex + +クラブふり ボールとびこむ みずのおと.. +The sound of not only non-come flying club swing ball.. +And a cut-comes into play that same feeling of well.. an eagle transfer +$78207 (Line 1) +6A 51 B3 79 38 00 B5 82 53 67 AD 5D 31 00 30 95 2E 29 67 88 88 | Original Japanese Hex +ク ラ ブ ふ り ボ ー ル と び こ む み ず の お と . . | Original Japanese Text +I T H I N K I C A N C O N V E R T | New English Text +13 00 1E 12 13 18 15 00 13 00 0D 0B 18 00 0D 19 18 20 0F 1C 1E | New English Hex +いかんいかん..わしのでばんじゃな +$78220 (Line 2) +26 59 3E 26 59 3E 88 88 3C 5F 2E 9B AC 3E 94 C5 2A | Original Japanese Hex +い か ん い か ん . . わ し の で ば ん じ ゃ な | Original Japanese Text +I T I N T O A N E A G L E ! | New English Text +13 1E 00 13 18 13 19 00 0B 18 00 0F 0B 11 16 0F 85 | New English Hex + +ひょっひょっひょーっ! +Tsu Hyo~tsu Hyo~tsu Hyo! +It would have got this game! +$78251 (Line 1) +78 C7 C8 78 C7 C8 78 C7 82 C8 85 | Original Japanese Hex +ひ ょ っ ひ ょ っ ひ ょ ー っ ! | Original Japanese Text +I T H I N K I V E | New English Text +13 00 1E 12 13 18 15 00 13 20 0F | New English Hex +このしょうぶ もらったでひょう! +$78260 (Line 2) +5D 2E 5F C7 27 AE 00 33 37 C8 63 9B 78 C7 27 85 | Original Japanese Hex +こ の し ょ う ぶ も ら っ た で ひ ょ う ! | Original Japanese Text +G O T H A N G O F I T ! ! | New English Text +11 19 1E 00 12 0B 18 11 00 19 10 00 13 1E 85 85 | New English Hex + +キャハハハハハ...え? +For example calibration lol lol ...? +Van will I get? There? +$78274 (Line 1) +69 CE 7C 7C 7C 7C 7C 88 88 88 28 86 | Original Japanese Hex +キ ャ ハ ハ ハ ハ ハ . . . え ? | Original Japanese Text +C A N I M A N A G E | New English Text +0D 0B 18 00 13 00 17 0B 18 0B 11 0F | New English Hex +あっ? もお あたしのばん? +$78284 (Line 2) +25 C8 86 00 33 29 00 25 63 5F 2E AC 3E 86 | Original Japanese Hex +あ っ ? も お あ た し の ば ん ? | Original Japanese Text +A G R E A T S C O R E ? | New English Text +0B 00 11 1C 0F 0B 1D 00 1C 0D 19 1C 0F 86 | New English Hex + +キャハハハハハ... +Calibration lol lol ... +I'll show you my power! +$78296 (Line 1) +69 CE 7C 7C 7C 7C 7C 88 88 88 | Original Japanese Hex +キ ャ ハ ハ ハ ハ ハ . . . | Original Japanese Text +I A M G O N N A | New English Text +13 00 0B 17 00 11 19 18 18 0B | New English Hex +あたしのちからをみせてあげるわね! +$782A4 (Line 2) +25 63 5F 2E 64 59 37 3D 30 61 66 25 91 39 3C 2D 85 | Original Japanese Hex +あ た し の ち か ら を み せ て あ げ る わ ね ! | Original Japanese Text +S H O W Y O U M Y P O W E R | New English Text +1D 12 19 21 00 23 19 1F 00 17 23 00 1A 19 21 0F 1C | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/SelectScreen.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/SelectScreen.txt new file mode 100644 index 00000000..d592c6f1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/SelectScreen.txt @@ -0,0 +1,45 @@ +すこあ +Score +$7E3BA +60 5D 25 | Original Japanese Hex +す こ あ | Original Japanese Text +S C R | New English Text +1D 0D 1C | New English Hex + +しょうきん +Prize +$7E303 +5F 85 27 5A 3E | Original Japanese Hex +し ょ う き ん | Original Japanese Text +P R I Z E | New English Text +1A 1C 13 24 0F | New English Hex + +フッフッフッ たたかいは はじまった +Fuffuffu~tsu battle began +Aim: accept a gift or top good! I aim at! +$78B5E (Line 1) +7E D1 7E D1 7E D1 00 63 63 59 26 77 00 77 94 2F C8 63 | Original Japanese Hex +フ ッ フ ッ フ ッ た た か い は は じ ま っ た | Original Japanese Text +T H E B A T T L E H A S N O W | New English Text +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? | New English Hex +よいか! トップをねらえ! ねらうのだ! +$78B74 (Line 2) +36 26 59 85 00 76 D1 BD 3D 2D 37 28 85 00 2D 37 27 2E 98 85 | Original Japanese Hex +よ い か ! ト ッ プ を ね ら え ! ね ら う の だ ! | Original Japanese Text +S T A R T E D ! A I M F O R T O P ! | New English Text +?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? 85 | New English Hex + +まだ たたかいは はじまったばかりですわ +It is still only just began +With it, and I do my best to please you. +$7A65D (Line 1) +2F 98 00 63 63 59 26 77 00 77 94 2F C8 63 AC 59 38 9B 60 3C | Original Japanese Hex +ま だ た た か い は は じ ま っ た ば か り で す わ | Original Japanese Text +T H I S I S T H E S T A R T O F | New English Text +1E 12 13 1D 00 13 1D 00 1E 12 0F 00 1D 1E 0B 1C 1E 00 19 10 | New English Hex +おうえんしてますわ がんばってくださいね +$7A675 (Line 2) +29 27 28 3E 5F 66 2F 60 3C 00 8E 3E AC C8 66 5B 98 5E 26 2D | Original Japanese Hex +お う え ん し て ま す わ が ん ば っ て く だ さ い ね | Original Japanese Text +T H E R O U N D . G O O D L U C K ! | New English Text +1E 12 0F 00 1C 19 1F 18 0E 88 11 19 19 0E 00 16 1F 0D 15 85 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StartHole.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StartHole.txt new file mode 100644 index 00000000..f418e6e5 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StartHole.txt @@ -0,0 +1,7 @@ +じゃら +Clink +$7DC57 +94 C5 37 | Original Japanese Hex +じ ゃ ら | Original Japanese Text +P T S | New English Text +1A 1E 1D | New English Hex diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StrokePlayRules.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StrokePlayRules.txt new file mode 100644 index 00000000..90daf5b9 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/StrokePlayRules.txt @@ -0,0 +1,75 @@ +ルール の せつめい +Rule Description +$7EE42 +53 82 53 00 2E 00 61 65 32 26 | Original Japanese Hex +ル ー ル の せ つ め い | Original Japanese Text +G A M E R U L E S | New English Text +11 0B 17 0F 00 1C 1F 16 0F 1D | New English Hex + +.ストロークプレイモード +Stroke Play Mode +$7D008 +00 00 00 00 00 88 6F 76 55 82 6A BD 54 40 4D 82 AB | Original Japanese Hex + . ス ト ロ ー ク プ レ イ モ ー ド | Original Japanese Text +. S T R O K E P L A Y M O D E | New English Text +88 1D 1E 1C 19 15 0F 00 1A 16 0B 23 00 17 19 0E 0F | New English Hex + +1コースをプレイして それまでの スコアのごうけいを +Is a game mode for up to compete with the sum of the score to play a course that +$7D01D (Line 1) +02 6C 82 6F 3D BD 54 40 5F 66 00 62 3A 2F 9B 2E 00 6F 6C 3F 2E 92 27 5C 26 3D | Original Japanese Hex +1 コ ー ス を プ レ イ し て そ れ ま で の ス コ ア の ご う け い を | Original Japanese Text +L E A S T N U M B E R O F S H O T S W I L L | New English Text +16 0F 0B 1D 1E 00 18 1F 17 0C 0F 1C 00 19 10 00 1D 12 19 1E 1D 00 21 13 16 16 | New English Hex +きそう ゲームモードです +$7D03B (Line 2) +5A 62 27 00 A0 82 4B 4D 82 AB 9B 60 | Original Japanese Hex +き そ う ゲ ー ム モ ー ド で す | Original Japanese Text +W I N T H E G A M E | New English Text +21 13 18 00 1E 12 0F 00 11 0B 17 0F | New English Hex + +.PROモード.ノーマルモードのちがいについて +. For the difference in PRO mode . Normal mode +$7D051 +88 1A 1C 19 4D 82 AB 88 48 82 49 53 4D 82 AB 2E 64 8E 26 2B 65 26 66 | Original Japanese Hex +. P R O モ ー ド . ノ ー マ ル モ ー ド の ち が い に つ い て | Original Japanese Text +. P R O M O D E - D I F F E R E N C E S | New English Text +88 1A 1C 19 00 17 19 0E 0F 00 82 00 0E 13 10 10 0F 1C 0F 18 0D 0F 1D | New English Hex + +PROモードはノーマルモードと くらべて.. +Compared with the normal mode .. PRO mode +$7D06C +1A 1C 19 4D 82 AB 77 48 82 49 53 4D 82 AB 67 00 5B 37 AF 66 88 88 | Original Japanese Hex +P R O モ ー ド は ノ ー マ ル モ ー ド と く ら べ て . . | Original Japanese Text +B E T W E E N A M A T E U R M O D E . . | New English Text +0C 0F 1E 21 0F 0F 18 00 0B 17 0B 1E 0F 1F 1C 00 17 19 0E 0F 88 88 | New English Hex + +かぜのむきと そのちからのあたいが かなりシビアに +The value of quite severe and their direction of the wind power +$7D086 (Line 1) +59 96 2E 31 5A 67 00 62 2E 64 59 37 2E 25 63 26 8E 00 59 2A 38 6E B2 3F 2B | Original Japanese Hex +か ぜ の む き と そ の ち か ら の あ た い が か な り シ ビ ア に | Original Japanese Text +W I N D D I R E C T I O N / S P E E D M U C H | New English Text +21 13 18 0E 00 0E 13 1C 0F 0D 1E 13 19 18 87 1D 1A 0F 0F 0E 00 17 1F 0D 12 | New English Hex +なっています ノーマルモードでは ものたりない.. +In normal mode has become unsatisfactory is .. +$7D0A3 (Line 2) +2A C8 66 26 2F 60 00 48 82 49 53 4D 82 AB 9B 77 00 33 2E 63 38 2A 26 88 88 | Original Japanese Hex +な っ て い ま す ノ ー マ ル モ ー ド で は も の た り な い . . | Original Japanese Text +M O R E S E V E R E T H A N N O R M A L . . | New English Text +17 19 1C 0F 00 1D 0F 20 0F 1C 0F 00 1E 12 0B 18 00 18 19 1C 17 0B 16 88 88 | New English Hex + +というかた よりスリリングなプレイをおのぞみのかた +Those who want to play more thrilling than that +$7D0C0 (Line 1) +67 26 27 59 63 00 36 38 6F 52 52 58 9F 2A BD 54 40 3D 29 2E 97 30 2E 59 63 | Original Japanese Hex +と い う か た よ り ス リ リ ン グ な プ レ イ を お の ぞ み の か た | Original Japanese Text +I F Y O U L I K E T H R I L L S T H E R E | New English Text +13 10 00 23 19 1F 00 16 13 15 0F 00 1E 12 1C 13 16 16 1D 00 1E 12 0F 1C 0F | New English Hex +などでも じゅうぶんに たのしめるモードです! +This mode is also plenty to enjoy, such as! +$7D0DD (Line 2) +2A 9C 9B 33 00 94 C6 27 AE 3E 2B 00 63 2E 5F 32 39 4D 82 AB 9B 60 85 | Original Japanese Hex +な ど で も じ ゅ う ぶ ん に た の し め る モ ー ド で す ! | Original Japanese Text +I S P L E N T Y I N T H I S M O D E ! | New English Text +13 1D 00 1A 16 0F 18 1E 23 00 13 18 00 1E 12 13 1D 00 17 19 0E 0F 85 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/TitleScreen.txt b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/TitleScreen.txt new file mode 100644 index 00000000..cff68799 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/Text/TitleScreen.txt @@ -0,0 +1,14 @@ +どらぼっちゃん OPEN +young master OPEN +$7EDC4 +9C 37 B0 C8 64 C5 3E 00 19 1A 0F 18 | Original Japanese Hex +ど ら ぼ っ ち ゃ ん O P E N | Original Japanese Text +M A S T E R S O P E N | New English Text +17 0B 1D 1E 0F 1C 1D 00 19 1A 0F 18 | New English Hex + +1990 1993 1995 RED +$7ED46 +02 0A 0A 01 00 02 0A 0A 04 00 02 0A 0A 05 00 1C 0F 0E | Original Japanese Hex +1 9 9 0 1 9 9 3 1 9 9 4 R E D | Original Japanese Text +1 9 9 4 R E D 2 0 1 3 K R O M | New English Text +02 0A 0A 05 00 1C 0F 0E 00 03 01 02 04 00 15 1C 19 17 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/make.bat b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/make.bat new file mode 100644 index 00000000..01d30351 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Naxat Open/make.bat @@ -0,0 +1,2 @@ +bass "Super Naxat Open - Golf de Shoubu da! Dorabocchan.asm" +ucon64 --nbak --chk "Super Naxat Open - Golf Challenge!.sfc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable1Player.png b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable1Player.png new file mode 100644 index 00000000..ef40f470 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable1Player.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable2Player.png b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable2Player.png new file mode 100644 index 00000000..c20573c4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTable2Player.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.png b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.png new file mode 100644 index 00000000..80e1053a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.txt b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.txt new file mode 100644 index 00000000..347c96cb --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableEditor.txt @@ -0,0 +1,18 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0|X X X X X X X X X X X X X X X X +1|S T A G E T E P L I M I T X X // Letters here have alpha +2| ! X X X X X X ( ) X X X - . / +3|0 1 2 3 4 5 6 7 8 9 : X < = > ? // Numbers here have no alpha +4|@ A B C D E F G H I J K L M N O +5|P Q R S T U V W X Y Z [ v ] X X +6|0 1 2 3 4 5 6 7 8 9 面 - ぱ コ - ス // Numbers here have alpha +7| ち ょう な ん か い ー ミ ン グ +8|X 。 「 」 、 ど さ ぁ ぃ ぅ ぇ ぉ ゃ ゅ ょ っ +9|ー あ い う え お か き く け こ さ し す せ そ +A|た ち つ て と な に ぬ ね の は ひ ふ へ ほ ま +B|み む め も や ゆ よ ら リ る れ ろ わ ん ゛ ゜ +C|X X X X X X ヲ ァ ィ ゥ ェ ォ ャ ュ ョ ッ +D|X ア イ ウ エ オ カ キ ク ケ コ サ シ ス セ ソ +E|タ チ ツ テ ト ナ ニ ヌ ネ ノ ハ ヒ フ ヘ ホ マ +F|ミ ム メ モ ヤ ユ ヨ ラ リ ル レ ロ ワ ン ク X \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableStartScreen.png b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableStartScreen.png new file mode 100644 index 00000000..06e4f1ce Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/CharTable/SokuCharTableStartScreen.png differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/README.md b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/README.md new file mode 100644 index 00000000..56663565 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/README.md @@ -0,0 +1,6 @@ +SNES Japanese To English Translation +===================================== +
    +** This translation is now discontinued **
    +Please go to: https://www.romhacking.net/translations/3313/
    +For a full 100% complete translation. diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.asm b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.asm new file mode 100644 index 00000000..1de07c6a --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.asm @@ -0,0 +1,72 @@ +// SNES "Super Soukoban" Japanese To English Translation by krom (Peter Lemon): + +output "Super Soukoban.sfc", create +origin $00000; insert "Super Soukoban (J).sfc" // Include Japanese Super Soukoban SNES ROM +origin $007FC0 +db "SUPER SOUKOBAN ENG " // $007FC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +macro TextStyle1(OFFSET, TEXT) { + origin {OFFSET} + db {TEXT} +} + +// Char Table 1 +map ' ', $20 +map '!', $21 +map '(', $28 +map ')', $29 +map '-', $2D +map '.', $2E +map '/', $2F +map '0', $30, 10 +map ':', $3A +map '<', $3C +map '=', $3D +map '>', $3E +map '?', $3F +map '@', $40 +map 'A', $41, 26 + +// Editor +TextStyle1($01C65, "MAP EDIT") +TextStyle1($01CC5, " SET TILE ") + +TextStyle1($01C6F, "PLAY MAP") +TextStyle1($01D61, "NO MAP TO PLAY.") + +TextStyle1($01C79, "MAP LOAD") +TextStyle1($01D02, "LOAD LEVEL:") +TextStyle1($018D4, "TRIAL SET") +TextStyle1($018DD, "WARM SET") +TextStyle1($018E6, "SUMO SET") +TextStyle1($018EF, "EPIC SET") +TextStyle1($018F8, "GRAND SET") +TextStyle1($01901, "TOUGH SET") +TextStyle1($01D36, "MAP:01 ") + +TextStyle1($01C83, "DELETE") +TextStyle1($01D8E, "ERASE ALL") +TextStyle1($01D99, "MAP DATA?") +TextStyle1($01DA4, " YES/NO ") + +TextStyle1($01C8D, "EXIT") + +// Char Table 2 +map '*', $19 + +map '0', $55, 10 +map ' ', $A0 +map 'A', $A1, 26 +map '[', $B1 +map '$', $B2 +map ']', $B3 +map '/', $B4 +map '.', $B5 +map $2C, $B6 // map ',', $B6 +map '-', $B8 + +// Start Screen +TextStyle1($01085, " *1*P* *S*O*K*O*B*A*N* *") +TextStyle1($010A1, " *2*P* *S*O*K*O*B*A*N* *") +TextStyle1($010BD, " * * * * * * * * * * * *") +TextStyle1($010D9, " *M*A*P* *E*D*I*T*O*R* *") \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.ips b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.ips new file mode 100644 index 00000000..d97ed4d4 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Super Soukoban.ips differ diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/1Player.txt b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/1Player.txt new file mode 100644 index 00000000..35107532 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/1Player.txt @@ -0,0 +1,97 @@ +こてしらベ コース +Preliminary test or trial; tryout Course +$4DE08 +9A 00 A3 00 9C 00 B7 00 F7 AD 00 BE B9 C2 DA 00 90 00 77 DD 00 | Original Japanese Hex +こ て し ら ベ コ ー ス | Original Japanese Text +T R I A L S E T | New English Text +74 00 72 00 69 00 61 00 F7 6C 00 00 B9 C2 73 00 65 00 77 74 00 | New English Hex +| +ウォーミング +Warming/up Course +$4DE20 +D3 00 CB 65 00 9F F0 00 FD 00 D8 5D | Original Japanese Hex +ウ ォ ー ミ ン グ | Original Japanese Text +W A R M | New English Text +77 00 61 65 00 9F 6D 00 00 00 00 5D | New English Hex +| +ひっかけ +Grappling/Sumo Course +$4DE2F +AB 3F 00 8F 00 96 00 99 B5 | Original Japanese Hex +ひ っ か け | Original Japanese Text +S U M O | New English Text +73 3F 00 75 00 6D 00 6F B5 | New English Hex +| +たいさく +Wants to spend/epic Course +$4DE2E +A0 00 92 00 9B 00 98 DB | Original Japanese Hex +た い さ く | Original Japanese Text +E P I C | New English Text +65 00 70 00 69 00 63 DB | New English Hex +| +エレガント +Elegant Course +$4DE46 +D4 00 FA 00 D6 5D 00 FD 00 5D E4 5F | Original Japanese Hex +エ レ ガ ン ト | Original Japanese Text +G R A N D | New English Text +67 00 72 00 61 5D 00 6E 00 5D 64 5F | New English Hex +| +なんかい +Difficult Course +$4DE53 +A5 00 BD D7 00 92 DB | Original Japanese Hex +な ん か い | Original Japanese Text +T O U G | New English Text +74 00 6F D7 00 67 DB | New English Hex +T O U G H +74 00 6F 00 75 00 67 00 68 DB | New English Hex + +こてしらベ コース +Preliminary test or trial; tryout Course +$16A1 +9A A3 9C B7 ED BE 00 00 DA 90 DD | Original Japanese Hex +こ て し ら ベ コ ー ス | Original Japanese Text +T R I A L S E T | New English Text +54 52 49 41 4C 00 00 00 53 45 54 | New English Hex +| +ウォーミング コース +Warming/up Course +$16AC +D3 CB 90 F0 FD D8 BE 00 DA 90 DD | Original Japanese Hex +ウ ォ ー ミ ン グ コ ー ス | Original Japanese Text +W A R M S E T | New English Text +57 41 52 4D 00 00 00 00 53 45 54 | New English Hex +| +ひっかけ コース +Grappling/Sumo Course +$16B7 +AB 8F 96 99 00 00 00 00 DA 90 DD | Original Japanese Hex +ひ っ か け コ ー ス | Original Japanese Text +S U M O S E T | New English Text +53 55 4D 4F 00 00 00 00 53 45 54 | New English Hex +| +たいさく コース +Wants to spend/epic Course +$16C2 +A0 92 9B 98 00 00 00 00 DA 90 DD | Original Japanese Hex +た い さ く コ ー ス | Original Japanese Text +E P I C S E T | New English Text +45 50 49 43 00 00 00 00 53 45 54 | New English Hex +| +エレガント コース +Elegant Course +$16CD +D4 FA D6 BE FD E4 00 00 DA 90 DD | Original Japanese Hex +エ レ ガ ン ト コ ー ス | Original Japanese Text +G R A N D S E T | New English Text +47 52 41 4E 44 00 00 00 53 45 54 | New English Hex +| +なんかい コース +Difficult Course +$16D8 +A5 BD 96 92 00 00 00 00 DA 90 DD | Original Japanese Hex +な ん か い コ ー ス | Original Japanese Text +T O U G H S E T | New English Text +54 4F 55 47 48 00 00 00 53 45 54 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/2Player.txt b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/2Player.txt new file mode 100644 index 00000000..dd0a3c47 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/2Player.txt @@ -0,0 +1,7 @@ +?????? +???????????? +$59D72 +9D 24 97 24 A5 24 00 34 | Original Japanese Hex +す き な | Original Japanese Text +? ? ? ? ? ? ? ? | New English Text +?? ?? ?? ?? ?? ?? ?? ?? | New English Hex diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/Editor.txt b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/Editor.txt new file mode 100644 index 00000000..079133ab --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/Editor.txt @@ -0,0 +1,141 @@ +面さつくる +Making surface +$01C65 +6A 86 A2 98 B9 20 20 20 | Original Japanese Hex +面 さ つ く る | Original Japanese Text +M A P E D I T | New English Text +4D 41 50 20 45 44 49 54 | New English Hex + | + キャラクターへんこう + Change Character + $01CC5 + D7 CC F7 D8 E0 90 AD BD 9A 93 | Original Japanese Hex + キ ャ ラ ク タ ー へ ん こ う | Original Japanese Text + S E T T I L E | New English Text + 20 53 45 54 20 54 49 4C 45 20 | New English Hex + +あそんでみる +Try playing +$01C6F +91 9F BD A3 BE B0 B9 20 | Original Japanese Hex +あ そ ん で み る | Original Japanese Text +P L A Y M A P | New English Text +50 4C 41 59 20 4D 41 50 | New English Hex + | + 面さ みなおして くだ さい。 + Please Reconsider the surface. + $01D61 + 6A 86 20 B0 A5 95 9C A3 20 98 A0 BE 9B 92 81 | Original Japanese Hex + 面 さ み な お し て く だ さ い 。 | Original Japanese Text + N O M A P T O P L A Y . | New English Text + 4E 4F 20 4D 41 50 20 54 4F 20 50 4C 41 59 2E | New English Hex + +ゲーム面さよぶ +We call the game surfaces +$01C79 +D9 6B F1 6A 86 B6 AC BE | Original Japanese Hex +ゲ ー ム 面 さ よ ぶ | Original Japanese Text +M A P L O A D | New English Text +4D 41 50 20 4C 4F 41 44 | New English Hex + | + ゲーム面さよびます。 + The surfaces called a game. + $01D02 + D9 6B F1 6A 86 B6 AB BE AF 9D 81 | Original Japanese Hex + ゲ ー ム 面 さ よ び ま す 。 | Original Japanese Text + L O A D L E V E L : | New English Text + 4C 4F 41 44 20 4C 45 56 45 4C 3A | New English Hex + | + こてしらベ コース + Preliminary test or trial; tryout Course + $018D4 + 9A A3 9C B7 AD BE 6D 6E 6F | Original Japanese Hex + こ て し ら ベ コ ー ス | Original Japanese Text + T R I A L S E T | New English Text + 54 52 49 41 4C 20 53 45 54 | New English Hex + | + ウォーミング コース + Warming/up Course + $018DD + D3 CB 7C 7D 7E 7F 6D 6E 6F | Original Japanese Hex + ウ ォ ー ミ ン グ コ ー ス | Original Japanese Text + W A R M S E T | New English Text + 57 41 52 4D 20 20 53 45 54 | New English Hex + | + ひっかけ コース + Grappling/Sumo Course + $018E6 + AB 8F 96 99 20 20 6D 6E 6F | Original Japanese Hex + ひ っ か け コ ー ス | Original Japanese Text + S U M O S E T | New English Text + 53 55 4D 4F 20 20 53 45 54 | New English Hex + | + たいさく コース + Wants to spend/epic Course + $018EF + A0 92 9B 98 20 20 6D 6E 6F | Original Japanese Hex + た い さ く コ ー ス | Original Japanese Text + E P I C S E T | New English Text + 45 50 49 43 20 20 53 45 54 | New English Hex + | + エレガント コース + Elegant Course + $018F8 + D4 FA D6 BE FD E4 6D 6E 6F | Original Japanese Hex + エ レ ガ ン ト コ ー ス | Original Japanese Text + G R A N D S E T | New English Text + 47 52 41 4E 44 20 53 45 54 | New English Hex + | + なんかい コース + Difficult Course + $01901 + A5 BD 96 92 20 20 6D 6E 6F | Original Japanese Hex + な ん か い コ ー ス | Original Japanese Text + T O U G H S E T | New English Text + 54 4F 55 47 48 20 53 45 54 | New English Hex + | + num 面 + Surface + $01D36 + 20 20 20 20 30 31 6A | Original Japanese Hex + num 面 | Original Japanese Text + M A P : num | New English Text + 4D 41 50 3A 30 31 20 | New English Hex + +面さけす +Surface Disappear +$01C83 +6A 86 99 9D 20 20 | Original Japanese Hex +面 さ け す | Original Japanese Text +D E L E T E | New English Text +44 45 4C 45 54 45 | New English Hex + | + 面さ けしますか? + The け it does? + $01D8E + 6A 86 20 99 9C AF 9D 96 3F | Original Japanese Hex + 面 さ け し ま す か ? | Original Japanese Text + E R A S E A L L | New English Text + 45 52 41 53 45 20 41 4C 4C | New English Hex + | + $01D99 + 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + M A P D A T A ? | New English Text + 4D 41 50 20 44 41 54 41 3F | New English Hex + | + はい / いいえ + Yes / No + $01DA4 + 20 AA 20 92 2F 92 92 94 20 | Original Japanese Hex + は い / い い え | Original Japanese Text + Y E S / N O | New English Text + 20 59 45 53 2F 4E 4F 20 20 | New English Hex + +もどる +Back / Return +$01C8D +B3 85 B9 20 | Original Japanese Hex +も ど る | Original Japanese Text +E X I T | New English Text +45 58 49 54 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/StartScreen.txt b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/StartScreen.txt new file mode 100644 index 00000000..73946768 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/Text/StartScreen.txt @@ -0,0 +1,46 @@ +スーパー そうこばん +Super Sokoban (Top Half) +$4DB79 +9B 08 9C 37 00 9D FE 37 00 9E 08 9F 08 A0 08 A1 EE 37 00 A2 08 29 75 80 2A 09 2B EE 75 80 2C 09 2D 75 80 2E 09 2F EE 75 80 30 09 31 B3 | Original Japanese Hex +ス ー パ ー そ う こ ば ん | Original Japanese Text +S U P E R S O K O B A N | New English Text +B3 09 00 37 ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? ?? B3 ?? ?? ?? AF ?? ?? ?? AB ?? ?? ?? AF ?? ?? ?? A2 ?? A1 ?? A0 09 AE B3 | New English Hex +| +????????? (Bottom Half) +$????? + + 155, 156, 000, 157, 000, 158 +009B,009C,0000,009D,0000,009E + + +スーパー そうこばん +Super Sokoban +$01085 +50 19 1D 1A D0 19 47 1A 48 1A 49 1A DF 19 D3 19 DA 19 EA 19 45 1A 46 1A | Original Japanese Hex + ス ー パ ー そ う こ ば ん | Original Japanese Text + 1 P S O K O B A N | New English Text +A0 19 56 19 B0 19 A0 19 B3 19 AF 19 AB 19 AF 19 A2 19 A1 19 AE 19 A0 19 | New English Hex + +たいせん そうこばん +Sokoban Game (Top Half) +$010A1 +50 19 50 1A 51 1A 52 1A 53 1A 50 19 54 1A 55 1A 56 1A 57 1A 58 1A 50 19 | Original Japanese Hex + た い せ ん そ う こ ば ん | Original Japanese Text + 2 P S O K O B A N | New English Text +A0 19 57 19 B0 19 A0 19 B3 19 AF 19 AB 19 AF 19 A2 19 A1 19 AE 19 A0 19 | New English Hex +| +たいせん うこばん +Koban game (Bottom Half) +$010BD +50 19 60 1A 61 1A 62 1A 63 1A 50 19 64 1A 65 1A 66 1A 67 1A 68 1A 69 1A | Original Japanese Hex + た い せ ん う こ ば ん | Original Japanese Text + | New English Text +A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 A0 19 | New English Hex + +そうこばん エディット +Edit Sokoban +$010D9 +50 19 DF 19 D3 19 DA 19 EA 19 45 1A 46 1A 14 1A 23 1A 4A 1A 4B 1A 4C 1A | Original Japanese Hex + そ う こ ば ん エ デ ィ ッ ト | Original Japanese Text + M A P E D I T O R | New English Text +A0 19 AD 19 A1 19 B0 19 A0 19 A5 19 A4 19 A9 19 B4 19 AF 19 B2 19 A0 19 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Super Soukoban/make.bat b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/make.bat new file mode 100644 index 00000000..3909f782 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Super Soukoban/make.bat @@ -0,0 +1,2 @@ +bass "Super Soukoban.asm" +ucon64 --nbak --chk "Super Soukoban.sfc" \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable1.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable1.txt new file mode 100644 index 00000000..636d74ec --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable1.txt @@ -0,0 +1,20 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________ +0| +1| +2| ! " # $ % & ' ( ) * + , - . / +3|0 1 2 3 4 5 6 7 8 9 : ; < > ? +4|© A B C D E F G H I J K L M N O +5|P Q R S T U V W X Y Z [ ] v _ +6|© A B C D E F G H I J K L M N O +7|P Q R S T U V W X Y Z +8| +9| +A| 。 「 」 、 ・ ヲ ァ ィ ゥ ェ ォ ャ ュ ョ ッ $23 (Index Pre-Byte) +B|ー ア イ ウ エ オ カ キ ク ケ コ サ シ ス セ ソ $DE " (Post-Byte) +C|タ チ ツ テ ト ナ ニ ヌ ネ ノ ハ ヒ フ ヘ ホ マ $DF o (Post-Byte) +D|ミ ム メ モ ヤ ユ ヨ ラ リ ル レ ロ ワ ン " o +A| 。 「 」 、 ・ を ぁ ぃ ぅ ぇ ぉ ゃ ゅ ょ っ $24 (Index Pre-Byte) +B|ー あ い う え お か き く け こ さ し す せ そ $DE " (Post-Byte) +C|た ち つ て と な に ぬ ね の は ひ ふ へ ほ ま $DF o (Post-Byte) +D|み む め も や ゆ よ ら り る れ ろ わ ん " o \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable2.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable2.txt new file mode 100644 index 00000000..30b43848 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharTables/TetrisBattleGaidenCharTable2.txt @@ -0,0 +1,90 @@ + 0 1 2 3 4 5 6 7 8 9 A B C D E F + _______________________________________________________________________________________________________________________$24 (MAP HI BYTE) +0| 。 「 」 、 ・ を ぁ ぃ ぅ ぇ ぉ ゃ ゅ ょ っ Top Half +1| 。 「 」 、 ・ を ぁ ぃ ぅ ぇ ぉ ゃ ゅ ょ っ Bottom Half + | +2|ー あ い う え お か き く け こ さ し す せ そ Top Half +3|ー あ い う え お か き く け こ さ し す せ そ Bottom Half + | +4|た ち つ て と な に ぬ ね の は ひ ふ へ ほ ま Top Half +5|た ち つ て と な に ぬ ね の は ひ ふ へ ほ ま Bottom Half + | +6|み む め も や ゆ よ ら り る れ ろ わ ん " o Top Half +7|み む め も や ゆ よ ら り る れ ろ わ ん " o Bottom Half + | +8| 。 「 」 、 ・ ヲ ァ ィ ゥ ェ ォ ャ ュ ョ ッ Top Half +9| 。 「 」 、 ・ ヲ ァ ィ ゥ ェ ォ ャ ュ ョ ッ Bottom Half + | +A|ー ア イ ウ エ オ カ キ ク ケ コ サ シ ス セ ソ Top Half +B|ー ア イ ウ エ オ カ キ ク ケ コ サ シ ス セ ソ Bottom Half + | +C|タ チ ツ テ ト ナ ニ ヌ ネ ノ ハ ヒ フ ヘ ホ マ Top Half +D|タ チ ツ テ ト ナ ニ ヌ ネ ノ ハ ヒ フ ヘ ホ マ Bottom Half + | +E|ミ ム メ モ ヤ ユ ヨ ラ リ ル レ ロ ワ ン " o Top Half +F|ミ ム メ モ ヤ ユ ヨ ラ リ ル レ ロ ワ ン " o Bottom Half + + _______________________________________________________________________________________________________________________$25 (MAP HI BYTE) +0| +1| + | +2| が ぎ ぐ げ ご ざ じ ず ぜ ぞ Top Half +3| が ぎ ぐ げ ご ざ じ ず ぜ ぞ Bottom Half + | +4|だ ぢ づ で ど ば び ぶ べ ぼ ま" Top Half +5|だ ぢ づ で ど ば び ぶ べ ぼ ま" Bottom Half + | +6| +7| + | +8| +9| + | +A| ガ ギ グ ゲ ゴ ザ ジ ズ ゼ ゾ Top Half +B| ガ ギ グ ゲ ゴ ザ ジ ズ ゼ ゾ Bottom Half + | +C|ダ ヂ ヅ デ ド バ ビ ブ ベ ボ マ" Top Half +D|ダ ヂ ヅ デ ド バ ビ ブ ベ ボ マ" Bottom Half + | +E| +F| + + _______________________________________________________________________________________________________________________$26 (MAP HI BYTE) +0| +1| + | +2| +3| + | +4| ぱ ぴ ぷ ぺ ぽ Top Half +5| ぱ ぴ ぷ ぺ ぽ Bottom Half + | +6| +7| + | +8| +9| + | +A| +B| + | +C| パ ピ プ ペ ポ Top Half +D| パ ピ プ ペ ポ Bottom Half + | +E| +F| + + _______________________________________________________________________________________________________________________$27 (MAP HI BYTE) +0| ! " # $ % & ' ( ) * + , - . / Top Half +1| ! " # $ % & ' ( ) * + , - . / Bottom Half + | +2|0 1 2 3 4 5 6 7 8 9 : ; < > ? Top Half +3|0 1 2 3 4 5 6 7 8 9 : ; < > ? Bottom Half + | +4|© A B C D E F G H I J K L M N O Top Half +5|© A B C D E F G H I J K L M N O Bottom Half + | +6|P Q R S T U V W X Y Z [ ] v _ Top Half +7|P Q R S T U V W X Y Z [ ] v _ Bottom Half + + diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect.rle new file mode 100644 index 00000000..82e4ab3a Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/BPSRLEEncode.py new file mode 100644 index 00000000..1f88b4c6 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('CharacterSelectMAPENGVRAM$F000..$F7FF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('CharacterSelectMAP.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/CharacterSelectMAPENGVRAM$F000..$F7FF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/CharacterSelectMAPENGVRAM$F000..$F7FF.bin new file mode 100644 index 00000000..7e4e0494 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/MAP/CharacterSelectMAPENGVRAM$F000..$F7FF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/BPSRLEEncode.py new file mode 100644 index 00000000..542b5843 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('CharacterSelectPageMAPENGVRAM$F000..$FFFF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('CharacterSelectPageMAP.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/CharacterSelectPageMAPENGVRAM$F000..$FFFF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/CharacterSelectPageMAPENGVRAM$F000..$FFFF.bin new file mode 100644 index 00000000..20d41386 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/PageMAP/CharacterSelectPageMAPENGVRAM$F000..$FFFF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/BPSRLEEncode.py new file mode 100644 index 00000000..f8635faa --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('CharacterSelectENGVRAM$0000..$3FFF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('CharacterSelect.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/CharacterSelectENGVRAM$0000..$3FFF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/CharacterSelectENGVRAM$0000..$3FFF.bin new file mode 100644 index 00000000..4fa600bd Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelect/TILES/CharacterSelectENGVRAM$0000..$3FFF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectMAP.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectMAP.rle new file mode 100644 index 00000000..9f221761 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectMAP.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectPageMAP.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectPageMAP.rle new file mode 100644 index 00000000..451c8c8e Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/CharacterSelectPageMAP.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro.rle new file mode 100644 index 00000000..e89ea8aa Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/BPSRLEEncode.py new file mode 100644 index 00000000..31e7a1e1 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('IntroENGVRAM$C000..$DFFF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('Intro.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/IntroENGVRAM$C000..$DFFF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/IntroENGVRAM$C000..$DFFF.bin new file mode 100644 index 00000000..060314e9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Intro/IntroENGVRAM$C000..$DFFF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen.rle new file mode 100644 index 00000000..2f8aade6 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/BPSRLEEncode.py new file mode 100644 index 00000000..dbc5a201 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('OptionScreenMAPENGVRAM$C000..$C7FF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('OptionScreenMAP.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/OptionScreenMAPENGVRAM$C000..$C7FF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/OptionScreenMAPENGVRAM$C000..$C7FF.bin new file mode 100644 index 00000000..323668aa Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/MAP/OptionScreenMAPENGVRAM$C000..$C7FF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/BPSRLEEncode.py new file mode 100644 index 00000000..b9ebf992 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('OptionScreenENGVRAM$0000..$2000.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('OptionScreen.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/OptionScreenENGVRAM$0000..$2000.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/OptionScreenENGVRAM$0000..$2000.bin new file mode 100644 index 00000000..ecf199c9 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreen/TILES/OptionScreenENGVRAM$0000..$2000.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreenMAP.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreenMAP.rle new file mode 100644 index 00000000..a53360ae Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/OptionScreenMAP.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/README.md b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/README.md new file mode 100644 index 00000000..01f722a3 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/README.md @@ -0,0 +1,6 @@ +SNES Japanese To English Translation +===================================== +
    +** This translation is now discontinued **
    +Please go to: https://www.romhacking.net/translations/5737/
    +For a full 100% complete translation. diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.asm b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.asm new file mode 100644 index 00000000..3930aa05 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.asm @@ -0,0 +1,1188 @@ +// SNES "Tetris Battle Gaiden" Japanese To English Translation by krom (Peter Lemon): + +output "Tetris Battle Gaiden.sfc", create +origin $00000; insert "Tetris Battle Gaiden (J).sfc" // Include Japanese Tetris Battle Gaiden SNES ROM +origin $007FC0 +db "TETRIS BATTLE GAIDENG" // $007FC0 - PROGRAM TITLE (21 Byte ASCII String, Use Spaces For Unused Bytes) + +macro PC2LoROM(SIZE, OFFSET) { + variable lorom({OFFSET} & $FFFF) + if lorom < $8000 { + lorom = lorom + $8000 + } + variable bank({OFFSET} >> 15) + bank = bank + $80 + lorom = lorom + (bank << 16) + {SIZE} lorom +} + +macro TextMapINTRO(TEXT) { + // Map Font HI + map ' ', $00 + map 'A', $C0, 16 + map 'Q', $E0, 10 + db {TEXT} + + // Map Font LO + map ' ', $00 + map 'A', $D0, 16 + map 'Q', $F0, 10 + db {TEXT} +} + +macro TextMapCHARACTERSELECTNAME(TEXT) { + // Map Font HI + map ' ', $01DE + map 'A', $01B0, 16 + map 'Q', $01D0, 10 + dw {TEXT} + + // Map Font LO + map ' ', $01DE + map 'A', $01C0, 16 + map 'Q', $01E0, 10 + dw {TEXT} +} + +macro TextMapCHARACTERSELECT(TEXT) { + // Map Font + map ' ', $A5 + map 'A', $A6, 26 + dw {TEXT} +} + +macro TextMapLO(OFFSET, TEXT) { + // Map Font HI + map ' ', $00, 16 + map '0', $20, 16 + map '@', $40, 16 + map 'P', $60, 16 + + origin {OFFSET} // Offset + variable labeloffset(+) + variable length(labeloffset - {OFFSET} - 1) + db length, {TEXT} + + + db $94 + ($C - length), $00 + + // Map Font LO + map ' ', $10, 16 + map '0', $30, 16 + map '@', $50, 16 + map 'P', $70, 16 + + db length, {TEXT} + db $94 + ($C - length), $00 +} + +macro TextMapHI(OFFSET, LENGTH) { + origin {OFFSET} // Offset + db $80 + {LENGTH}, $27 + db $94 + ($C - {LENGTH}), $00 + + db $80 + {LENGTH}, $27 + db $94 + ($C - {LENGTH}), $00 +} + +macro TextMapASCII() { + map 0, 0, 256 // Map ASCII Font +} + +macro TextMapPause() { + // Map Pause Font + map '\n', $25 + map '0', $30, 10 + map '!', $3A + map '?', $3B + map 'A', $41, 26 + map '.', $A1 + map '\s', $A2 // map "'", $A2 + map $2C, $A4 // map ',', $A4 + map '-', $B0 +} + +TextMapASCII() // Map ASCII Font + +// SETTING +origin $00C87 +PC2LoROM(dw, SETTINGBACKGROUND) + +origin $00CA0 +PC2LoROM(dw, SETTINGSTEREOMONO) + +// BACK GROUND +origin $01950 +SETTINGBACKGROUND: + PC2LoROM(dw, TWOPLAYERBGSetting) + PC2LoROM(dw, HALLOWEENSetting) + PC2LoROM(dw, MIRURUNSetting) + PC2LoROM(dw, SHAMANSetting) + PC2LoROM(dw, ALADDINSetting) + PC2LoROM(dw, PRINCESSSetting) + PC2LoROM(dw, BITSetting) + PC2LoROM(dw, NINJASetting) + PC2LoROM(dw, WOLFMANSetting) + PC2LoROM(dw, DRAGONSetting) + PC2LoROM(dw, QUEENSetting) +TWOPLAYERBGSetting: + db "2PLAYERBG", $FF +HALLOWEENSetting: + db "HALLOWEEN", $FF +MIRURUNSetting: + db "MIRURUN ", $FF +SHAMANSetting: + db "SHAMAN ", $FF +ALADDINSetting: + db "ALADDIN ", $FF +PRINCESSSetting: + db "PRINCESS ", $FF +BITSetting: + db "BIT ", $FF +NINJASetting: + db "NINJA ", $FF +WOLFMANSetting: + db "WOLFMAN ", $FF +DRAGONSetting: + db "DRAGON ", $FF +QUEENSetting: + db "QUEEN ", $FF + +// STEREO/MONO +SETTINGSTEREOMONO: + PC2LoROM(dw, STEREOSetting) + PC2LoROM(dw, MONOSetting) +STEREOSetting: + db "STEREO", $FF +MONOSetting: + db "MONO ", $FF + +TextMapPause() // Map Pause Font + +// PAUSE SCREEN +origin $117DC + PC2LoROM(dw, HALLOWEENPauseName) + PC2LoROM(dw, MIRURUNPauseName) + PC2LoROM(dw, SHAMANPauseName) + PC2LoROM(dw, ALADDINPauseName) + PC2LoROM(dw, PRINCESSPauseName) + PC2LoROM(dw, BITPauseName) + PC2LoROM(dw, NINJAPauseName) + PC2LoROM(dw, WOLFMANPauseName) + PC2LoROM(dw, DRAGONPauseName) + PC2LoROM(dw, QUEENPauseName) +HALLOWEENPauseName: + db "HALLOWEN", $FF +MIRURUNPauseName: + db "MIRURUN", $FF +SHAMANPauseName: + db "SHAMAN", $FF +ALADDINPauseName: + db "ALADDIN", $FF +PRINCESSPauseName: + db "PRINCESS", $FF +BITPauseName: + db " BIT", $FF +NINJAPauseName: + db " NINJA", $FF +WOLFMANPauseName: + db "WOLFMAN", $FF +DRAGONPauseName: + db "DRAGON", $FF +QUEENPauseName: + db " QUEEN", $FF + +// PAUSE SCREEN MAGIC DESCRIPTION +origin $11A95 + PC2LoROM(dw, PAUSEMAGIC01) // Level 1 Mirurun + PC2LoROM(dw, PAUSEMAGIC02) // Level 4 Princess + PC2LoROM(dw, PAUSEMAGIC03) // Level 4 Ninja + PC2LoROM(dw, PAUSEMAGIC04) // Level 4 Halloween + PC2LoROM(dw, PAUSEMAGIC05) // Level 2 Ninja + PC2LoROM(dw, PAUSEMAGIC06) // Level 3 Mirurun + PC2LoROM(dw, PAUSEMAGIC07) // Level 3 Ninja + PC2LoROM(dw, PAUSEMAGIC08) // Level 1 Halloween + PC2LoROM(dw, PAUSEMAGIC09) // Level 3 Shaman + PC2LoROM(dw, PAUSEMAGIC10) // Level 3 Halloween + PC2LoROM(dw, PAUSEMAGIC11) // Level 4 Queen + PC2LoROM(dw, PAUSEMAGIC12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGIC12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGIC12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGIC13) // Level 1 Wolfman + PC2LoROM(dw, PAUSEMAGIC14) // Level 1 Shaman + PC2LoROM(dw, PAUSEMAGIC15) // Level 4 Bit + PC2LoROM(dw, PAUSEMAGIC16) // Level 1 Bit + PC2LoROM(dw, PAUSEMAGIC17) // Level 2 Queen + PC2LoROM(dw, PAUSEMAGIC18) // Level 3 Princess + PC2LoROM(dw, PAUSEMAGIC19) // Level 2 Shaman + PC2LoROM(dw, PAUSEMAGIC20) // Level 1 Ninja + PC2LoROM(dw, PAUSEMAGIC21) // Level 3 Bit + PC2LoROM(dw, PAUSEMAGIC22) // Level 4 Wolfman + PC2LoROM(dw, PAUSEMAGIC23) // Level 1 Dragon + PC2LoROM(dw, PAUSEMAGIC24) // Level 1 Princess + PC2LoROM(dw, PAUSEMAGIC25) // Level 4 Mirurun + PC2LoROM(dw, PAUSEMAGIC26) // Level 3 Aladdin + PC2LoROM(dw, PAUSEMAGIC27) // Level 2 Aladdin + PC2LoROM(dw, PAUSEMAGIC28) // Level 2 Princess + PC2LoROM(dw, PAUSEMAGIC29) // Level ? ???? + PC2LoROM(dw, PAUSEMAGIC30) // Level 2 Dragon + PC2LoROM(dw, PAUSEMAGIC31) // Level 2 Wolfman + PC2LoROM(dw, PAUSEMAGIC32) // Level 4 Aladdin + PC2LoROM(dw, PAUSEMAGIC33) // Level 2 Mirurun + PC2LoROM(dw, PAUSEMAGIC34) // Level 3 Wolfman + PC2LoROM(dw, PAUSEMAGIC35) // Level 4 Shaman + PC2LoROM(dw, PAUSEMAGIC36) // Level 3 Dragon + PC2LoROM(dw, PAUSEMAGIC37) // Level 2 Bit + PC2LoROM(dw, PAUSEMAGIC38) // Level 4 Dragon + PC2LoROM(dw, PAUSEMAGIC39) // Level 3 Queen + PC2LoROM(dw, PAUSEMAGIC40) // Level 2 Halloween + PC2LoROM(dw, PAUSEMAGIC41) // Level 1 Queen + +origin $11B01 +PAUSEMAGIC01: + db "LOWER THE BLOCKS\n" + db "IN MY FIELD BY 4\n" + db "LINES!", $FF +PAUSEMAGIC02: + db "MAKE MY FIELD THE\n" + db "SAME AS ON THE\n" + db "OPPONENT SIDE.", $FF +PAUSEMAGIC03: + db "THIS WILL TURN ALL" + db "THE OPPONENT\n" + db "BLOCKS INTO STONE!", $FF +PAUSEMAGIC04: + db "LAYS DOWN BOMBS TO" + db "BLOW-UP OPPONENT\n" + db "FIELD M-WAH-HA-HA!", $FF +PAUSEMAGIC05: + db "FAKES NEXT BLOCKS\n" + db "OF MY OPPONENT!", $FF +PAUSEMAGIC06: + db "I WILL ADD 5 LINES" + db "TO MY OPPONENT.", $FF +PAUSEMAGIC07: + db "MY SPIDER WEB WILL" + db "HOLD BLOCKS UP\n" + db "AFTER LINES CLEAR!", $FF +PAUSEMAGIC08: + db "BURNS 3 LINES IN\n" + db "MY FIELD! THEY\n" + db "WILL DISINTEGRATE!", $FF +PAUSEMAGIC09: + db "I WILL ADD BLOCKS\n" + db "OF STONE WITH THIS" + db "CURSE.", $FF +PAUSEMAGIC10: + db "SUCK CRYSTAL POWER" + db "FROM MY OPPONENT.", $FF +PAUSEMAGIC11: + db "ALL THE BLOCKS IN\n" + db "MY FIELD WILL GO!\n" + db "HOW WONDERFUL!", $FF +PAUSEMAGIC12: + db "SENDS 2 LINES FROM" + db "FROM MY FIELD TO\n" + db "THE OPPONENT SIDE.", $FF +PAUSEMAGIC13: + db "I WILL CUT OFF 4\n" + db "LINES OF BLOCKS\n" + db "FROM THE TOP.", $FF +PAUSEMAGIC14: + db "THIS WILL SPLIT\n" + db "MY BLOCKS DOWN THE" + db "MIDDLE.", $FF +PAUSEMAGIC15: + db "MAKES THE OPPONENT" + db "BLOCKS DANCE AND\n" + db "BECOME MESSY.", $FF +PAUSEMAGIC16: + db "SHOOTING STARS\n" + db "RAIN DOWN LOWERING" + db "THE BLOCKS.", $FF +PAUSEMAGIC17: + db "REVERSES CONTROLS\n" + db "OF MY OPPONENT!\n" + db "HO-HO-HO!", $FF +PAUSEMAGIC18: + db "STOPS THE BLOCKS\n" + db "OF MY OPPONENT\n" + db "FROM MOVING.", $FF +PAUSEMAGIC19: + db "THIS WILL SPEED UP" + db "THE BLOCK ROTATION" + db "OF MY OPPONENT.", $FF +PAUSEMAGIC20: + db "THIS WILL PUSH ALL" + db "MY BLOCKS TO ONE\n" + db "SIDE WITH WIND!", $FF +PAUSEMAGIC21: + db "A GANG WILL STEAL\n" + db "CRYSTALS FROM THE\n" + db "OPPONENT FIELD.", $FF +PAUSEMAGIC22: + db "MY FIELD WILL USE\n" + db "RENSA RULES FOR\n" + db "THE NEXT 4 BLOCKS.", $FF +PAUSEMAGIC23: + db "I WILL CRUSH THE\n" + db "BLOCKS IN MY FIELD" + db "USING GREAT POWER!", $FF +PAUSEMAGIC24: + db "DESTROYS 3 COLUMNS" + db "OF ALL MY BLOCKS.\n" + db "AIM FOR BEST SHOT!", $FF +PAUSEMAGIC25: + db "SWITCHES ALL HOLES" + db "WITH BLOCKS AND\n" + db "BLOCKS WITH HOLES.", $FF +PAUSEMAGIC26: + db "MAKES THE FIELD OF" + db "MY OPPONENT THE\n" + db "SAME AS MINE.", $FF +PAUSEMAGIC27: + db "WHEN MY OPPONENT\n" + db "CLEARS A LINE, IT\n" + db "WILL NOT HURT ME.", $FF +PAUSEMAGIC28: + db "REFLECTS THE MAGIC" + db "OF MY OPPONENT, AS" + db "IF I HAVE CAST IT.", $FF +PAUSEMAGIC29: + db "I KNOW HOW LONG IT" + db "WILL TAKE A SECRET" + db "BLOCK TO FALL.", $FF +PAUSEMAGIC30: + db "I CAN CHANGE THE\n" + db "NEXT 4 BLOCKS INTO" + db "ANY, WITH L AND R!", $FF +PAUSEMAGIC31: + db "A GIANT WILL STOP\n" + db "THE OPPONENT FROM\n" + db "DROPPING BLOCKS.", $FF +PAUSEMAGIC32: + db "I WILL CONTROL THE" + db "NEXT 2 BLOCKS OF\n" + db "MY OPPONENT.", $FF +PAUSEMAGIC33: + db "INVERT THE CONTROL" + db "OF MY OPPONENT FOR" + db "THE NEXT 3 BLOCKS.", $FF +PAUSEMAGIC34: + db "LINES CLEARED BY\n" + db "MY OPPONENT MAKE\n" + db "MY FIELD GO DOWN.", $FF +PAUSEMAGIC35: + db "CHOOSES A RANDOM\n" + db "LEVEL 4 CRYSTAL\n" + db "POWER TO USE...", $FF +PAUSEMAGIC36: + db "RANDOMLY SCRAMBLES" + db "THE CONTROLS OF MY" + db "OPPONENT!", $FF +PAUSEMAGIC37: + db "REPEATS THE SAME\n" + db "BLOCK 10 TIMES FOR" + db "BOTH PLAYERS.", $FF +PAUSEMAGIC38: + db "IT SWAPS MY FIELD\n" + db "WITH MY OPPONENT!\n" + db "G-WAH-HA-HA!", $FF +PAUSEMAGIC39: + db "MY CLEARED LINES\n" + db "ATTACK DOUBLES!\n" + db "HO-HO-HO!", $FF +PAUSEMAGIC40: + db "MAKES THE FIELD OF" + db "MY OPPONENT DARK\n" + db "FOR 3 BLOCKS.", $FF +PAUSEMAGIC41: + db "BURNS 4 LINES IN\n" + db "MY FIELD! THEY\n" + db "WILL DISINTEGRATE!", $FF + +// PAUSE SCREEN PLAYER +origin $12A9B +ALLPausePlayer: + db "-HOW TO USE MAGIC- ", $FF + +origin $11AED + PC2LoROM(dw, HALLOWEENPausePlayer) + PC2LoROM(dw, MIRURUNPausePlayer) + PC2LoROM(dw, SHAMANPausePlayer) + PC2LoROM(dw, ALADDINPausePlayer) + PC2LoROM(dw, PRINCESSPausePlayer) + PC2LoROM(dw, BITPausePlayer) + PC2LoROM(dw, NINJAPausePlayer) + PC2LoROM(dw, WOLFMANPausePlayer) + PC2LoROM(dw, DRAGONPausePlayer) + PC2LoROM(dw, QUEENPausePlayer) + +origin $1231D +HALLOWEENPausePlayer: + db "GET SOME CRYSTALS\n" + db "TO USE MY SPELLS!\n" + db "PRESS UP ON D-PAD.", $FF +MIRURUNPausePlayer: + db "HI! GET CRYSTALS\n" + db "TO CAST MY MAGIC!\n" + db "PRESS UP ON D-PAD.", $FF +SHAMANPausePlayer: + db "GET CRYSTALS FOR\n" + db "MY SHAMAN MAGIC.\n" + db "D-PAD UP TO CAST.", $FF +ALADDINPausePlayer: + db "GATHER CRYSTALS TO" + db "USE MY GREAT MAGIC" + db "D-PAD UP TO CAST!", $FF +PRINCESSPausePlayer: + db "GATHER CRYSTALS TO" + db "USE MY SPELLS. UP\n" + db "ON D-PAD TO CAST!", $FF +BITPausePlayer: + db "WE NEED CRYSTALS\n" + db "FOR OUR FUN MAGIC!" + db "D-PAD UP TO CAST!", $FF +NINJAPausePlayer: + db "MY NINJUTSU NEEDS\n" + db "CRYSTALS FOR POWER" + db "D-PAD UP TO USE IT", $FF +WOLFMANPausePlayer: + db "MY TRUE STRENGTH\n" + db "REQUIRES CRYSTALS." + db "PRESS UP ON D-PAD.", $FF +DRAGONPausePlayer: + db "HUFF-PUFF! BRING\n" + db "ME CRYSTALS. PRESS" + db "UP ON THE D-PAD!", $FF +QUEENPausePlayer: + db "GIVE ME CRYSTALS\n" + db "NOW FOR MY SPELLS!" + db "THEN USE D-PAD UP!", $FF + +// PAUSE SCREEN MAGIC NAME +origin $12588 + PC2LoROM(dw, PAUSEMAGICNAME01) // Level 1 Mirurun + PC2LoROM(dw, PAUSEMAGICNAME02) // Level 4 Princess + PC2LoROM(dw, PAUSEMAGICNAME03) // Level 4 Ninja + PC2LoROM(dw, PAUSEMAGICNAME04) // Level 4 Halloween + PC2LoROM(dw, PAUSEMAGICNAME05) // Level 2 Ninja + PC2LoROM(dw, PAUSEMAGICNAME06) // Level 3 Mirurun + PC2LoROM(dw, PAUSEMAGICNAME07) // Level 3 Ninja + PC2LoROM(dw, PAUSEMAGICNAME08) // Level 1 Halloween + PC2LoROM(dw, PAUSEMAGICNAME09) // Level 3 Shaman + PC2LoROM(dw, PAUSEMAGICNAME10) // Level 3 Halloween + PC2LoROM(dw, PAUSEMAGICNAME11) // Level 4 Queen + PC2LoROM(dw, PAUSEMAGICNAME12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME12) // Level 1 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME13) // Level 1 Wolfman + PC2LoROM(dw, PAUSEMAGICNAME14) // Level 1 Shaman + PC2LoROM(dw, PAUSEMAGICNAME15) // Level 4 Bit + PC2LoROM(dw, PAUSEMAGICNAME16) // Level 1 Bit + PC2LoROM(dw, PAUSEMAGICNAME17) // Level 2 Queen + PC2LoROM(dw, PAUSEMAGICNAME18) // Level 3 Princess + PC2LoROM(dw, PAUSEMAGICNAME19) // Level 2 Shaman + PC2LoROM(dw, PAUSEMAGICNAME20) // Level 1 Ninja + PC2LoROM(dw, PAUSEMAGICNAME21) // Level 3 Bit + PC2LoROM(dw, PAUSEMAGICNAME22) // Level 4 Wolfman + PC2LoROM(dw, PAUSEMAGICNAME23) // Level 1 Dragon + PC2LoROM(dw, PAUSEMAGICNAME24) // Level 1 Princess + PC2LoROM(dw, PAUSEMAGICNAME25) // Level 4 Mirurun + PC2LoROM(dw, PAUSEMAGICNAME26) // Level 3 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME27) // Level 2 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME28) // Level 2 Princess + PC2LoROM(dw, PAUSEMAGICNAME29) // Level ? ???? + PC2LoROM(dw, PAUSEMAGICNAME30) // Level 2 Dragon + PC2LoROM(dw, PAUSEMAGICNAME31) // Level 2 Wolfman + PC2LoROM(dw, PAUSEMAGICNAME32) // Level 4 Aladdin + PC2LoROM(dw, PAUSEMAGICNAME33) // Level 2 Mirurun + PC2LoROM(dw, PAUSEMAGICNAME34) // Level 3 Wolfman + PC2LoROM(dw, PAUSEMAGICNAME35) // Level 4 Shaman + PC2LoROM(dw, PAUSEMAGICNAME36) // Level 3 Dragon + PC2LoROM(dw, PAUSEMAGICNAME37) // Level 2 Bit + PC2LoROM(dw, PAUSEMAGICNAME38) // Level 4 Dragon + PC2LoROM(dw, PAUSEMAGICNAME39) // Level 3 Queen + PC2LoROM(dw, PAUSEMAGICNAME40) // Level 2 Halloween + PC2LoROM(dw, PAUSEMAGICNAME41) // Level 1 Queen + +origin $125DE +PAUSEMAGICNAME01: + db "MIRURUN ", $FF +PAUSEMAGICNAME02: + db " COPY ", $FF +PAUSEMAGICNAME03: + db " MEDUSA ", $FF +PAUSEMAGICNAME04: + db " BOMB ", $FF +PAUSEMAGICNAME05: + db " FAKE ", $FF +PAUSEMAGICNAME06: + db "PENTRIS ", $FF +PAUSEMAGICNAME07: + db "SHAMBLE ", $FF +PAUSEMAGICNAME08: + db " FRY ", $FF +PAUSEMAGICNAME09: + db " CURSE ", $FF +PAUSEMAGICNAME10: + db "VAMPIRE ", $FF +PAUSEMAGICNAME11: + db " CLEAR ", $FF +PAUSEMAGICNAME12: + db " SEESAW ", $FF +PAUSEMAGICNAME13: + db " SLICE ", $FF +PAUSEMAGICNAME14: + db " MOSES ", $FF +PAUSEMAGICNAME15: + db " MAMBO ", $FF +PAUSEMAGICNAME16: + db "STARDUST", $FF +PAUSEMAGICNAME17: + db "REVERSE ", $FF +PAUSEMAGICNAME18: + db "PARALYZE", $FF +PAUSEMAGICNAME19: + db "ROTATION", $FF +PAUSEMAGICNAME20: + db " GATHER ", $FF +PAUSEMAGICNAME21: + db " GANG ", $FF +PAUSEMAGICNAME22: + db " RENSA ", $FF +PAUSEMAGICNAME23: + db " PRESS ", $FF +PAUSEMAGICNAME24: + db " SOUL ", $FF +PAUSEMAGICNAME25: + db " SIRTET ", $FF +PAUSEMAGICNAME26: + db " FAX ", $FF +PAUSEMAGICNAME27: + db " SHIELD ", $FF +PAUSEMAGICNAME28: + db " MIRROR ", $FF +PAUSEMAGICNAME29: + db " HEAVY ", $FF +PAUSEMAGICNAME30: + db " SELECT ", $FF +PAUSEMAGICNAME31: + db "SLOWDOWN", $FF +PAUSEMAGICNAME32: + db " REMOTE ", $FF +PAUSEMAGICNAME33: + db " INVERT ", $FF +PAUSEMAGICNAME34: + db "BUDDIES ", $FF +PAUSEMAGICNAME35: + db " PRAYER ", $FF +PAUSEMAGICNAME36: + db "ROULETTE", $FF +PAUSEMAGICNAME37: + db " FEVER ", $FF +PAUSEMAGICNAME38: + db " CHANGE ", $FF +PAUSEMAGICNAME39: + db " DOUBLE ", $FF +PAUSEMAGICNAME40: + db " DARK ", $FF +PAUSEMAGICNAME41: + db "HYPERFRY", $FF + +// PAUSE SCREEN COMPUTER +origin $12A4A + PC2LoROM(dw, HALLOWEENPauseComputer1) + PC2LoROM(dw, HALLOWEENPauseComputer2) + PC2LoROM(dw, HALLOWEENPauseComputer3) + PC2LoROM(dw, MIRURUNPauseComputer1) + PC2LoROM(dw, MIRURUNPauseComputer2) + PC2LoROM(dw, MIRURUNPauseComputer3) + PC2LoROM(dw, SHAMANPauseComputer1) + PC2LoROM(dw, SHAMANPauseComputer2) + PC2LoROM(dw, SHAMANPauseComputer3) + PC2LoROM(dw, ALADDINPauseComputer1) + PC2LoROM(dw, ALADDINPauseComputer2) + PC2LoROM(dw, ALADDINPauseComputer3) + PC2LoROM(dw, PRINCESSPauseComputer1) + PC2LoROM(dw, PRINCESSPauseComputer2) + PC2LoROM(dw, PRINCESSPauseComputer3) + PC2LoROM(dw, BITPauseComputer1) + PC2LoROM(dw, BITPauseComputer2) + PC2LoROM(dw, BITPauseComputer3) + PC2LoROM(dw, NINJAPauseComputer1) + PC2LoROM(dw, NINJAPauseComputer2) + PC2LoROM(dw, NINJAPauseComputer3) + PC2LoROM(dw, WOLFMANPauseComputer1) + PC2LoROM(dw, WOLFMANPauseComputer2) + PC2LoROM(dw, WOLFMANPauseComputer3) + PC2LoROM(dw, DRAGONPauseComputer1) + PC2LoROM(dw, DRAGONPauseComputer2) + PC2LoROM(dw, DRAGONPauseComputer3) + PC2LoROM(dw, QUEENPauseComputer1) + PC2LoROM(dw, QUEENPauseComputer2) + PC2LoROM(dw, QUEENPauseComputer3) + +origin $12AB0 +HALLOWEENPauseComputer1: + db "M-WAH-HA!\n" + db "WE WILL HAVE FUN.\n" + db "COME ON!", $FF +HALLOWEENPauseComputer2: + db "M-WAH-HA!\n" + db "KEEP TRYING!\n" + db "I WILL DEFEAT YOU\n" + db "SOON!", $FF +HALLOWEENPauseComputer3: + db "SO MANY BLOCKS\n" + db "I MUST NOT PANIC!\n" + db "I WILL USE THEM!", $FF + +MIRURUNPauseComputer1: + db "HI!\n" + db "I WILL DO MY BEST!", $FF +MIRURUNPauseComputer2: + db "NOT TOO BAD!\n" + db "I CAN NOT LOSE!", $FF +MIRURUNPauseComputer3: + db "VERY BAD!\n" + db "I WILL DO MY BEST!" + db "BUT I TRIED THAT!!", $FF + +SHAMANPauseComputer1: + db "I PRAY TO THE GOD\n" + db "OF TETRIS FOR MY\n" + db "STRENGTH.", $FF +SHAMANPauseComputer2: + db "I AM OBSESSED WITH" + db "TETRIS.\n" + db "I WILL NOT LOSE.", $FF +SHAMANPauseComputer3: + db "MAYBE THIS IS A\n" + db "SIGN.\n" + db "I MUST WIN!", $FF + +ALADDINPauseComputer1: + db "HA-HA!\n" + db "A VICTORY WILL\n" + db "SURELY BE MINE.", $FF +ALADDINPauseComputer2: + db "HA-HA!\n" + db "A LITTLE TROUBLE.\n" + db "I WILL STILL WIN!", $FF +ALADDINPauseComputer3: + db "I CAN NOT LOSE.\n" + db "I WILL TRY TO\n" + db "RECOVER QUICKLY!", $FF + +PRINCESSPauseComputer1: + db "I WILL DO MY BEST!" + db "BE GENTLE!", $FF +PRINCESSPauseComputer2: + db "A LITTLE DANGER.\n" + db "I WILL TRY HARDER!", $FF +PRINCESSPauseComputer3: + db "AH!\n" + db "I WILL LOSE IF I\n" + db "PLAY LIKE THIS!\n" + db "I MUST DO BETTER!", $FF + +BITPauseComputer1: + db "HOORAY!\n" + db "THERE IS NO BLOCKS" + db "WOW, YO!", $FF +BITPauseComputer2: + db "HOORAY!\n" + db "SOME MORE BLOCKS\n" + db "HOORAY!", $FF +BITPauseComputer3: + db "WAH! WAH!\n" + db "BLOCKS TO THE TOP\n" + db "WAH! WAH!", $FF + +NINJAPauseComputer1: + db "I HAVE GOT THIS.\n" + db "I WILL WIN WITH MY" + db "NINJUTSU, I CAN DO" + db "IT!", $FF +NINJAPauseComputer2: + db "DO NOT DO IT!\n" + db "IT IS NOT POSSIBLE" + db "TO BREAK NINJUTSU\n" + db "TO THIS DEGREE!", $FF +NINJAPauseComputer3: + db "GROWTH!\n" + db "I MUST REVERSE IT!" + db "PLEASE WAIT!", $FF + +WOLFMANPauseComputer1: + db "SEE MY TRUE\n" + db "STRENGTH\n" + db "I WILL BEAT YOU.", $FF +WOLFMANPauseComputer2: + db "SADLY THIS ROUND\n" + db "IS AWKWARD FOR ME." + db "IT IS A PLEASURE\n" + db "TO FIGHT YOU.", $FF +WOLFMANPauseComputer3: + db "I MUST NOT THROW\n" + db "THIS AWAY!\n" + db "I CAN FEEL MY\n" + db "POWER RETURNING!", $FF + +DRAGONPauseComputer1: + db "HUFF-PUFF\n" + db "THINK YOU CAN WIN?" + db "GIVE UP NOW, RUN\n" + db "AWAY!", $FF +DRAGONPauseComputer2: + db "IF YOU THINK YOU\n" + db "CAN WIN, YOU ARE\n" + db "WRONG!\n" + db "I WILL BEAT YOU!", $FF +DRAGONPauseComputer3: + db "YOU!\n" + db "HMM WHAT TO DO!\n" + db "BUT I STILL WILL\n" + db "NOT LOSE!!", $FF + +QUEENPauseComputer1: + db "HO-HO!\n" + db "PLEASE APPOLOGIZE!" + db "THEN I WILL\n" + db "FORGIVE YOU!", $FF +QUEENPauseComputer2: + db "HO-HO!\n" + db "IT IS QUITE EASY!\n" + db "BUT I AM STILL NOT" + db "TRYING HARD!", $FF +QUEENPauseComputer3: + db "HO-HO!\n" + db "YOU MADE ME ANGRY!" + db "COME ON! KNEEL\n" + db "DOWN BEFORE ME!", $FF + +// INTRO +origin $1B26F +TextMapINTRO("HALLOWEEN ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db " CHOCOLATE" +db " CAKE" +db "HATES: " +db "PUMPKINPIE" +db "BORN IN: " +db " A PUMPKIN" +db " FIELD" +db " ", $00, $00, $00 + +origin $1B2D9 +TextMapINTRO(" MIRURUN ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db " FRIENDS" +db "HATES: " +db " HALLOWEEN" +db " " +db "BORN IN: " +db " BANBOO" +db " GARDENS" +db " ", $00, $00 + +origin $1B341 +TextMapINTRO(" SHAMAN ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db " DANCING" +db "HATES: " +db " THUNDER" +db " " +db "BORN IN: " +db " YANBOO" +db " FOREST" +db " ", $00, $00 + +origin $1B3A7 +TextMapINTRO(" ALADDIN ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db " DREAMS," +db " ADVENTURE" +db "HATES: " +db " REAL LIFE" +db " " +db "BORN IN: " +db " NAKADAT" +db " ", $00, $00 + +origin $1B411 +TextMapINTRO(" PRINCESS ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db "CHEESECAKE" +db " DOGS" +db "HATES: " +db "EARTHWORMS" +db " SLUGS" +db "BORN IN: " +db " L-SHIP" +db " ", $00, $00, $00 + +origin $1B47D +TextMapINTRO(" BIT ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db "FUN, JOKES" +db "HATES: " +db " SILENCE" +db " " +db "BORN IN: " +db " SUNHOUSE" +db " HILLS" +db " ", $00, $00 + +origin $1B4E3 +TextMapINTRO(" NINJA ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db " CHOCOLATE" +db " " +db "HATES: " +db " COCKROACH" +db " " +db "BORN IN: " +db " GEKKO" +db " ", $00 + +origin $1B54B +TextMapINTRO(" WOLFMAN ") // Map Intro Font +TextMapASCII() // Map ASCII Font +db "LIKES: " +db "ONION SOUP" +db "HATES: " +db " TOMATOES" +db " " +db "BORN IN: " +db " DOWNTOWN," +db " TOKYO" +db " " + +// CHARACTER DESCRIPTION +origin $27222 + PC2LoROM(dl, HALLOWEENCharacterDescription) + PC2LoROM(dl, MIRURUNCharacterDescription) + PC2LoROM(dl, SHAMANCharacterDescription) + PC2LoROM(dl, ALADDINCharacterDescription) + PC2LoROM(dl, PRINCESSCharacterDescription) + PC2LoROM(dl, BITCharacterDescription) + PC2LoROM(dl, NINJACharacterDescription) + PC2LoROM(dl, WOLFMANCharacterDescription) + +origin $2FA1B +PRINCESSCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "PRINCESS WAS") // Line 1: Origin, Text + TextMapLO(origin(), "IN L-SHIP") // Line 2: Origin, Text + TextMapLO(origin(), "CASTLE WHEN") // Line 3: Origin, Text + TextMapLO(origin(), "HER SISTER") // Line 4: Origin, Text + TextMapLO(origin(), "IS KIDNAPPED") // Line 5: Origin, Text + TextMapLO(origin(), "BY A DRAGON.") // Line 6: Origin, Text + TextMapLO(origin(), "SHE SETS OUT") // Line 7: Origin, Text + TextMapLO(origin(), "TO FIND HER.") // Line 8: Origin, Text + TextMapLO(origin(), "\dHOLD ON SIS") // Line 9: Origin, Text + TextMapLO(origin(), " I WILL NOT") // Line 10: Origin, Text + TextMapLO(origin(), " FAIL YOU!!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $C) // Line 1: Origin, Length + TextMapHI(origin(), $9) // Line 2: Origin, Length + TextMapHI(origin(), $B) // Line 3: Origin, Length + TextMapHI(origin(), $A) // Line 4: Origin, Length + TextMapHI(origin(), $C) // Line 5: Origin, Length + TextMapHI(origin(), $C) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $C) // Line 8: Origin, Length + TextMapHI(origin(), $C) // Line 9: Origin, Length + TextMapHI(origin(), $B) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $3FB9C +ALADDINCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "ALADDIN IS") // Line 1: Origin, Text + TextMapLO(origin(), "DREAMING OF") // Line 2: Origin, Text + TextMapLO(origin(), "ADVENTURE...") // Line 3: Origin, Text + TextMapLO(origin(), "FLYING ON A") // Line 4: Origin, Text + TextMapLO(origin(), "MAGIC CARPET") // Line 5: Origin, Text + TextMapLO(origin(), "HE SPOTS AN") // Line 6: Origin, Text + TextMapLO(origin(), "ISLAND...") // Line 7: Origin, Text + TextMapLO(origin(), "\dTHERE IS A") // Line 8: Origin, Text + TextMapLO(origin(), " DRAGON DOWN") // Line 9: Origin, Text + TextMapLO(origin(), " THERE! I'LL") // Line 10: Origin, Text + TextMapLO(origin(), " LAND HERE!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $A) // Line 1: Origin, Length + TextMapHI(origin(), $B) // Line 2: Origin, Length + TextMapHI(origin(), $C) // Line 3: Origin, Length + TextMapHI(origin(), $B) // Line 4: Origin, Length + TextMapHI(origin(), $C) // Line 5: Origin, Length + TextMapHI(origin(), $B) // Line 6: Origin, Length + TextMapHI(origin(), $9) // Line 7: Origin, Length + TextMapHI(origin(), $B) // Line 8: Origin, Length + TextMapHI(origin(), $C) // Line 9: Origin, Length + TextMapHI(origin(), $C) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $84800 +BITCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "A GROUP OF 5") // Line 1: Origin, Text + TextMapLO(origin(), "LADS WHO ARE") // Line 2: Origin, Text + TextMapLO(origin(), "THE BEST OF") // Line 3: Origin, Text + TextMapLO(origin(), "CHUMS, & ARE") // Line 4: Origin, Text + TextMapLO(origin(), "ALWAYS HAPPY") // Line 5: Origin, Text + TextMapLO(origin(), "WHEREVER") // Line 6: Origin, Text + TextMapLO(origin(), "THEY ROAM...") // Line 7: Origin, Text + TextMapLO(origin(), "LOVE DANCING") // Line 8: Origin, Text + TextMapLO(origin(), "\dYIPPEE!!") // Line 9: Origin, Text + TextMapLO(origin(), " WE HAVE SO") // Line 10: Origin, Text + TextMapLO(origin(), " MUCH FUN!!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $C) // Line 1: Origin, Length + TextMapHI(origin(), $C) // Line 2: Origin, Length + TextMapHI(origin(), $B) // Line 3: Origin, Length + TextMapHI(origin(), $C) // Line 4: Origin, Length + TextMapHI(origin(), $C) // Line 5: Origin, Length + TextMapHI(origin(), $8) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $C) // Line 8: Origin, Length + TextMapHI(origin(), $9) // Line 9: Origin, Length + TextMapHI(origin(), $B) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $849F0 +HALLOWEENCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "HALLOWEEN") // Line 1: Origin, Text + TextMapLO(origin(), "LOVES SWEETS") // Line 2: Origin, Text + TextMapLO(origin(), "& MISCHIEF.") // Line 3: Origin, Text + TextMapLO(origin(), "HE IS ALWAYS") // Line 4: Origin, Text + TextMapLO(origin(), "THINKING OF") // Line 5: Origin, Text + TextMapLO(origin(), "EATING CANDY") // Line 6: Origin, Text + TextMapLO(origin(), "& WANTS THE") // Line 7: Origin, Text + TextMapLO(origin(), "DRAGON'S OWN") // Line 8: Origin, Text + TextMapLO(origin(), "SWEETS FOR") // Line 9: Origin, Text + TextMapLO(origin(), "HIMSELF...") // Line 10: Origin, Text + TextMapLO(origin(), "\dYUM YUM!!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $9) // Line 1: Origin, Length + TextMapHI(origin(), $C) // Line 2: Origin, Length + TextMapHI(origin(), $B) // Line 3: Origin, Length + TextMapHI(origin(), $C) // Line 4: Origin, Length + TextMapHI(origin(), $B) // Line 5: Origin, Length + TextMapHI(origin(), $C) // Line 6: Origin, Length + TextMapHI(origin(), $B) // Line 7: Origin, Length + TextMapHI(origin(), $C) // Line 8: Origin, Length + TextMapHI(origin(), $A) // Line 9: Origin, Length + TextMapHI(origin(), $A) // Line 10: Origin, Length + TextMapHI(origin(), $B) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $84BDE +SHAMANCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "SHAMAN IS IN") // Line 1: Origin, Text + TextMapLO(origin(), "SEARCH OF A") // Line 2: Origin, Text + TextMapLO(origin(), "LEGENDARY") // Line 3: Origin, Text + TextMapLO(origin(), "POTION THAT") // Line 4: Origin, Text + TextMapLO(origin(), "CAN CURE ANY") // Line 5: Origin, Text + TextMapLO(origin(), "ILLNESS...") // Line 6: Origin, Text + TextMapLO(origin(), "HE WILL NEED") // Line 7: Origin, Text + TextMapLO(origin(), "TO FIND THE") // Line 8: Origin, Text + TextMapLO(origin(), "DRAGON SCALE") // Line 9: Origin, Text + TextMapLO(origin(), "TO SUCCEED.") // Line 10: Origin, Text + TextMapLO(origin(), "\dHU-WA-YE!!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $C) // Line 1: Origin, Length + TextMapHI(origin(), $B) // Line 2: Origin, Length + TextMapHI(origin(), $9) // Line 3: Origin, Length + TextMapHI(origin(), $B) // Line 4: Origin, Length + TextMapHI(origin(), $C) // Line 5: Origin, Length + TextMapHI(origin(), $A) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $B) // Line 8: Origin, Length + TextMapHI(origin(), $C) // Line 9: Origin, Length + TextMapHI(origin(), $B) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $855C7 +NINJACharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "AS NINJA WAS") // Line 1: Origin, Text + TextMapLO(origin(), "TRAINING, HE") // Line 2: Origin, Text + TextMapLO(origin(), "HEARD THAT") // Line 3: Origin, Text + TextMapLO(origin(), "HIS FIANCEE") // Line 4: Origin, Text + TextMapLO(origin(), "KYOUKO HAD") // Line 5: Origin, Text + TextMapLO(origin(), "BEEN TURNED") // Line 6: Origin, Text + TextMapLO(origin(), "INTO A FROG,") // Line 7: Origin, Text + TextMapLO(origin(), "BY THE HAND") // Line 8: Origin, Text + TextMapLO(origin(), "OF AN EVIL") // Line 9: Origin, Text + TextMapLO(origin(), "SORCERER...") // Line 10: Origin, Text + TextMapLO(origin(), "\dSAVE HER!!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $C) // Line 1: Origin, Length + TextMapHI(origin(), $C) // Line 2: Origin, Length + TextMapHI(origin(), $A) // Line 3: Origin, Length + TextMapHI(origin(), $B) // Line 4: Origin, Length + TextMapHI(origin(), $A) // Line 5: Origin, Length + TextMapHI(origin(), $B) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $B) // Line 8: Origin, Length + TextMapHI(origin(), $A) // Line 9: Origin, Length + TextMapHI(origin(), $B) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $85913 +MIRURUNCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "MIRURUN IS A") // Line 1: Origin, Text + TextMapLO(origin(), "CREATURE WHO") // Line 2: Origin, Text + TextMapLO(origin(), "HAS A HEART") // Line 3: Origin, Text + TextMapLO(origin(), "OF GOLD.") // Line 4: Origin, Text + TextMapLO(origin(), "HE HAS BEEN") // Line 5: Origin, Text + TextMapLO(origin(), "ON A JOURNEY") // Line 6: Origin, Text + TextMapLO(origin(), "TO FIND SOME") // Line 7: Origin, Text + TextMapLO(origin(), "FRIENDS.") // Line 8: Origin, Text + TextMapLO(origin(), "\dWILL YOU") // Line 9: Origin, Text + TextMapLO(origin(), " BE MY") // Line 10: Origin, Text + TextMapLO(origin(), " FRIEND?\d...") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $C) // Line 1: Origin, Length + TextMapHI(origin(), $C) // Line 2: Origin, Length + TextMapHI(origin(), $B) // Line 3: Origin, Length + TextMapHI(origin(), $8) // Line 4: Origin, Length + TextMapHI(origin(), $B) // Line 5: Origin, Length + TextMapHI(origin(), $C) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $8) // Line 8: Origin, Length + TextMapHI(origin(), $9) // Line 9: Origin, Length + TextMapHI(origin(), $6) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +origin $D7E13 +WOLFMANCharacterDescription: + db $C3, $00 // Low Bytes + TextMapLO(origin(), "WOLFMAN") // Line 1: Origin, Text + TextMapLO(origin(), "WENT BACK TO") // Line 2: Origin, Text + TextMapLO(origin(), "HIS HOMELAND") // Line 3: Origin, Text + TextMapLO(origin(), "AFTER MANY") // Line 4: Origin, Text + TextMapLO(origin(), "YEARS AWAY &") // Line 5: Origin, Text + TextMapLO(origin(), "FOUND IT WAS") // Line 6: Origin, Text + TextMapLO(origin(), "IN UPROAR!..") // Line 7: Origin, Text + TextMapLO(origin(), "THE PRINCESS") // Line 8: Origin, Text + TextMapLO(origin(), "IS KIDNAPPED") // Line 9: Origin, Text + TextMapLO(origin(), "\dI'LL FIGHT") // Line 10: Origin, Text + TextMapLO(origin(), "WITH HONOR!\d") // Line 11: Origin, Text + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End Low Bytes + db $C3, $00 // High Bytes + TextMapHI(origin(), $7) // Line 1: Origin, Length + TextMapHI(origin(), $C) // Line 2: Origin, Length + TextMapHI(origin(), $C) // Line 3: Origin, Length + TextMapHI(origin(), $A) // Line 4: Origin, Length + TextMapHI(origin(), $C) // Line 5: Origin, Length + TextMapHI(origin(), $C) // Line 6: Origin, Length + TextMapHI(origin(), $C) // Line 7: Origin, Length + TextMapHI(origin(), $C) // Line 8: Origin, Length + TextMapHI(origin(), $C) // Line 9: Origin, Length + TextMapHI(origin(), $B) // Line 10: Origin, Length + TextMapHI(origin(), $C) // Line 11: Origin, Length + db $FF, $00, $FF, $00, $B3, $00, $00, $FF // End High Bytes + +// CHARACTER SELECT MAGIC +origin $05442 +TextMapCHARACTERSELECT("MIRURUN ") // Level 1 Mirurun +TextMapCHARACTERSELECT("COPY ") // Level 4 Princess +TextMapCHARACTERSELECT("MEDUSA ") // Level 4 Ninja +TextMapCHARACTERSELECT("BOMB ") // Level 4 Halloween +TextMapCHARACTERSELECT("FAKE ") // Level 2 Ninja +TextMapCHARACTERSELECT("PENTRIS ") // Level 3 Mirurun +TextMapCHARACTERSELECT("SHAMBLE ") // Level 3 Ninja +TextMapCHARACTERSELECT("FRY ") // Level 1 Halloween +TextMapCHARACTERSELECT("CURSE ") // Level 3 Shaman +TextMapCHARACTERSELECT("VAMPIRE ") // Level 3 Halloween +TextMapCHARACTERSELECT("CLEAR ") // Level 4 Queen +TextMapCHARACTERSELECT("SEESAW ") // Level 1 Aladdin +TextMapCHARACTERSELECT("SEESAW ") // Level 1 Aladdin +TextMapCHARACTERSELECT("SEESAW ") // Level 1 Aladdin +TextMapCHARACTERSELECT("SLICE ") // Level 1 Wolfman +TextMapCHARACTERSELECT("MOSES ") // Level 1 Shaman +TextMapCHARACTERSELECT("MAMBO ") // Level 4 Bit +TextMapCHARACTERSELECT("STARDUST") // Level 1 Bit +TextMapCHARACTERSELECT("REVERSE ") // Level 2 Queen +TextMapCHARACTERSELECT("PARALYZE") // Level 3 Princess +TextMapCHARACTERSELECT("ROTATION") // Level 2 Shaman +TextMapCHARACTERSELECT("GATHER ") // Level 1 Ninja +TextMapCHARACTERSELECT("GANG ") // Level 3 Bit +TextMapCHARACTERSELECT("RENSA ") // Level 4 Wolfman +TextMapCHARACTERSELECT("PRESS ") // Level 1 Dragon +TextMapCHARACTERSELECT("SOUL ") // Level 1 Princess +TextMapCHARACTERSELECT("SIRTET ") // Level 4 Mirurun +TextMapCHARACTERSELECT("FAX ") // Level 3 Aladdin +TextMapCHARACTERSELECT("SHIELD ") // Level 2 Aladdin +TextMapCHARACTERSELECT("MIRROR ") // Level 2 Princess +TextMapCHARACTERSELECT("HEAVY ") // Level ? ???? +TextMapCHARACTERSELECT("SELECT ") // Level 2 Dragon +TextMapCHARACTERSELECT("SLOWDOWN") // Level 2 Wolfman +TextMapCHARACTERSELECT("REMOTE ") // Level 4 Aladdin +TextMapCHARACTERSELECT("INVERT ") // Level 2 Mirurun +TextMapCHARACTERSELECT("BUDDIES ") // Level 3 Wolfman +TextMapCHARACTERSELECT("PRAYER ") // Level 4 Shaman +TextMapCHARACTERSELECT("ROULETTE") // Level 3 Dragon +TextMapCHARACTERSELECT("FEVER ") // Level 2 Bit +TextMapCHARACTERSELECT("CHANGE ") // Level 4 Dragon +TextMapCHARACTERSELECT("DOUBLE ") // Level 3 Queen +TextMapCHARACTERSELECT("DARK ") // Level 2 Halloween +TextMapCHARACTERSELECT("HYPERFRY") // Level 1 Queen + +// CHARACTER SELECT NAME +origin $1A313 +TextMapCHARACTERSELECTNAME("HALLOWE") +TextMapCHARACTERSELECTNAME("MIRURUN") +TextMapCHARACTERSELECTNAME(" SHAMAN") +TextMapCHARACTERSELECTNAME("ALADDIN") +TextMapCHARACTERSELECTNAME("PRINCES") +TextMapCHARACTERSELECTNAME(" BIT ") +TextMapCHARACTERSELECTNAME(" NINJA ") +TextMapCHARACTERSELECTNAME("WOLFMAN") + +// Include Character Select Tile MAP +origin $3D1D2; insert "CharacterSelectMAP.rle" // VRAM $F000..$F7FF MAP Character Select RLE (1224 Bytes) +// Include Character Select Tiles +origin $95112; insert "CharacterSelect.rle" // VRAM $0000..$3FFF 4BPP Character Select RLE (9064 Bytes) +// Include Character Select Page Tile MAP +origin $FD2B2; insert "CharacterSelectPageMAP.rle" // VRAM $F000..$F7FF MAP Character Select Page RLE (2307 Bytes) + +// Include Title Screen Book Tiles +origin $9D06F; insert "TitleScreenBookMode7.rle" // VRAM $0001..$7FFF 8BPP Title Screen Book Mode7 RLE (10149 Bytes) +origin $ACAB5; insert "TitleScreenBook.rle" // VRAM $C400..$D400 4BPP Title Screen Book RLE (7923 Bytes) +// Include Title Screen Tiles +origin $D6125; insert "TitleScreen.rle" // VRAM $C000..$FFFF 4BPP Title Screen RLE (7248 Bytes) + +// Include Option Screen Tile MAP +origin $85416; insert "OptionScreenMAP.rle" // VRAM $C000..$C7FF MAP Option Screen RLE (424 Bytes) +// Include Option Screen Tiles +origin $E655A; insert "OptionScreen.rle" // VRAM $0000..$1FFF 2BPP Option Screen RLE (2744 Bytes) + +// Include Intro Tiles +origin $EB3A1; insert "Intro.rle" // VRAM $C000..$DFFF 4BPP Intro RLE (4107 Bytes) \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.ips b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.ips new file mode 100644 index 00000000..98f792fd Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Tetris Battle Gaiden.ips differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERDESCRIPTION.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERDESCRIPTION.txt new file mode 100644 index 00000000..3692b577 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERDESCRIPTION.txt @@ -0,0 +1,1072 @@ +CHARACTER DESCRIPTION: + NINJA: + シュギョウちゅうのかれの + As he was + $2FA1B (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C AC 8D A7 8E A3 41 0D 23 49 26 6A 49 | Original Japanese Hex + $2FA2A (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C BC 9D B7 9E B3 51 1D 33 59 36 7A 59 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN シ ュ ギ ョ ウ ち ゅ う の か れ の | Original Japanese Text + $2FB4B (Line 1) (Top Half: MAP HI Bytes) + E3 00 82 24 ..01 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + $2FB53 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..01 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. .. | Original Japanese Text + + もとに、いいなづけのキョ + training, word came + $2FA39 (Line 2) (Top Half: MAP LO Bytes) + 94 00 0C 63 44 46 04 22 22 45 42 29 49 A7 8E | Original Japanese Hex + $2FA48 (Line 2) (Bottom Half: MAP LO Bytes) + 94 00 0C 73 54 56 14 32 32 55 52 39 59 B7 9E | Original Japanese Hex + RLELEN RLEBYTE RAWLEN も と に 、 い い な づ け の キ ョ | Original Japanese Text + $2FB5B (Line 2) (Top Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + $2FB63 (Line 2) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. | Original Japanese Text + + ウコさんが、ワルいまほう + to him, that his fiancee + $2FA57 (Line 3) (Top Half: MAP LO Bytes) + 94 00 0C A3 AA 2B 6D 26 04 EC E9 22 4F 4E 23 | Original Japanese Hex + $2FA66 (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C B3 BA 3B 7D 36 14 FC F9 32 5F 5E 33 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ウ コ さ ん が 、 ワ ル い ま ほ う | Original Japanese Text + $2FB6B (Line 3) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + $2FB73 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + つかいに、まほうでカエル + Kyouko, had been turned + $2FA75 (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C 42 26 22 46 04 4F 4E 23 43 A6 A4 E9 | Original Japanese Hex + $2FA84 (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C 52 36 32 56 14 5F 5E 33 53 B6 B4 F9 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN つ か い に 、 ま ほ う で カ エ ル | Original Japanese Text + $2FB7B (Line 4) (Top Half: MAP HI Bytes) + 94 00 88 24 .. .. .. .. .. .. ..01 25 83 24 .. .. | Original Japanese Hex + $2FB83 (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 88 24 .. .. .. .. .. .. ..01 25 83 24 .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. | Original Japanese Text + + にされたとのしらせがとど + into a frog by an evil + $2FA93 (Line 5) (Top Half: MAP LO Bytes) + 94 00 0C 46 2B 6A 40 44 49 2C 67 2E 26 44 44 | Original Japanese Hex + $2FAA2 (Line 5) (Bottom Half: MAP LO Bytes) + 94 00 0C 56 3B 7A 50 54 59 3C 77 3E 36 54 54 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN に さ れ た と の し ら せ が と ど | Original Japanese Text + $2FB8B (Line 5) (Top Half: MAP HI Bytes) + 94 00 89 24 03 25 24 25 | Original Japanese Hex + $2FB93 (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 89 24 .. .. .. .. .. .. .. ..03 25 24 25 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. .. .. | Original Japanese Text + + いた。もとにもどるには、 + sorcerer. It seems a potion + $2FAB1 (Line 6) (Top Half: MAP LO Bytes) + 94 00 0C 22 40 01 63 44 46 63 44 69 46 4A 04 | Original Japanese Hex + $2FAC0 (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 32 50 11 73 54 56 73 54 79 56 5A 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い た 。 も と に も ど る に は 、 | Original Japanese Text + $2FB9B (Line 6) (Top Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + $2FBA3 (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. | Original Japanese Text + + ドラゴンのしっているクス + is needed to change her back to normal + $2FACF (Line 7) (Top Half: MAP LO Bytes) + 94 00 0C C4 E7 AA ED 49 2C 0F 43 22 69 A8 AD | Original Japanese Hex + $2FADE (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C D4 F7 BA FD 59 3C 1F 53 32 79 B8 BD | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ド ラ ゴ ン の し っ て い る ク ス | Original Japanese Text + $2FBAB (Line 7) (Top Half: MAP HI Bytes) + 94 00 03 25 24 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + $2FBB3 (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 03 25 24 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. .. RLELEN RLEBYTE .. .. .. .. .. .. .. .. | Original Japanese Text + + リがひつようらしい・・・ + and the dragon knows of it... + $2FAED (Line 8) (Top Half: MAP LO Bytes) + 94 00 09 E8 26 4B 42 66 23 67 2C 22 83 05 .. .. | Original Japanese Hex + $2FAFB (Line 8) (Bottom Half: MAP LO Bytes) + 94 00 09 F8 36 5B 52 76 33 77 3C 32 83 15 .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN リ が ひ つ よ う ら し い ・ ・ ・ | Original Japanese Text + $2FBBB (Line 8) (Top Half: MAP HI Bytes) + 94 00 02 24 25 8A 24 .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $2FBC2 (Line 8) (Bottom Half: MAP HI Bytes) + 94 00 02 24 25 8A 24 .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. | Original Japanese Text + + 「かならずもとのすがたに + "I promise I'll change you + $2FB09 (Line 9) (Top Half: MAP LO Bytes) + 94 00 0C 02 26 45 67 2D 63 44 49 2D 26 40 46 | Original Japanese Hex + $2FB18 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 36 55 77 3D 73 54 59 3D 36 50 56 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 か な ら ず も と の す が た に | Original Japanese Text + $2FBC9 (Line 9) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 84 24 .. .. ..03 25 24 24 | Original Japanese Hex + $2FBD5 (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 84 24 .. .. ..03 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN RLELEN RLEBYTE .. .. RAWLEN .. .. .. | Original Japanese Text + + もどしてやるからな。」 + back to normal." + $2FB27 (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B 63 44 2C 43 64 69 26 67 45 01 03 | Original Japanese Hex + $2FB35 (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B 73 54 3C 53 74 79 36 77 55 11 13 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN も ど し て や る か ら な 。 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $2FBE1 (Line 10) (Top Half: MAP HI Bytes) + 95 00 02 24 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + $2FBE8 (Line 10) (Bottom Half: MAP HI Bytes) + 95 00 02 24 25 89 24 .. .. .. .. .. .. .. .. FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. .. .. .. .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27234 + 1B FA 85 | Memory Address + + ALADDIN: + ぼうけんとユメは、ぼくの + Dreams and adventure + $3FB9C (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C 4E 23 29 6D 44 E5 E2 4A 04 4E 28 49 | Original Japanese Hex + $3FBAB (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C 5E 33 39 7D 54 F5 F2 5A 14 5E 38 59 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ぼ う け ん と ユ メ は 、 ぼ く の | Original Japanese Text + $3FCBC (Line 1) (Top Half: MAP HI Bytes) + E3 00 01 25 88 24 .. .. .. .. .. .. ..03 25 24 24 | Original Japanese Hex + $3FCC6 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 01 25 88 24 .. .. .. .. .. .. ..03 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. RAWLEN .. .. .. | Original Japanese Text + + たからもの。きょうも、そ + are what I treasure! + $3FBBA (Line 2) (Top Half: MAP LO Bytes) + 94 00 0C 40 26 67 63 49 01 27 0E 23 63 04 2F | Original Japanese Hex + $3FBC9 (Line 2) (Bottom Half: MAP LO Bytes) + 94 00 0C 50 36 77 73 59 11 37 1E 33 73 14 3F | Original Japanese Hex + RLELEN RLEBYTE RAWLEN た か ら も の 。 き ょ う も 、 そ | Original Japanese Text + $3FCD0 (Line 2) (Top Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $3FCD4 (Line 2) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + らとぶジュウタンにのり、 + Once again I will take to the skies + $3FBD8 (Line 3) (Top Half: MAP LO Bytes) + 94 00 0C 67 44 4C AC 8D A3 C0 ED 46 49 68 04 | Original Japanese Hex + $3FBE7 (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 77 54 5C BC 9D B3 D0 FD 56 59 78 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ら と ぶ ジ ュ ウ タ ン に の り 、 | Original Japanese Text + $3FCD8 (Line 3) (Top Half: MAP HI Bytes) + 94 00 82 24 ..82 25 ..88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $3FCE0 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..82 25 ..88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + おおぞらをゆく! + on my flying carpet! + $3FBF6 (Line 4) (Top Half: MAP LO Bytes) + 94 00 82 25 06 2F 67 06 65 28 01 | Original Japanese Hex + $3FC01 (Line 4) (Bottom Half: MAP LO Bytes) + 98 00 82 35 ..06 3F 77 16 75 38 11 | Original Japanese Hex + RLELEN RLEBYTE RLELEN お おRAWLEN ぞ ら を ゆ く ! | Original Japanese Text + $3FCE8 (Line 4) (Top Half: MAP HI Bytes) + 94 00 82 24 ..01 25 84 24 .. .. ..01 27 | Original Japanese Hex + $3FCF2 (Line 4) (Bottom Half: MAP HI Bytes) + 98 00 82 24 ..01 25 84 24 .. .. ..01 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. RAWLEN .. | Original Japanese Text + + 「おや?たしかここは・・ + "Huh? I'm sure this is... + $3FC0C (Line 5) (Top Half: MAP LO Bytes) + 98 00 0C 02 25 64 2F 40 2C 26 2A 2A 4A 05 05 | Original Japanese Hex + $3FC1B (Line 5) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 35 74 3F 50 3C 36 3A 3A 5A 15 15 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 お や ? た し か こ こ は ・ ・ | Original Japanese Text + $3FCFC (Line 5) (Top Half: MAP HI Bytes) + 98 00 83 24 .. ..01 27 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $3FD04 (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 83 24 .. ..01 27 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + そうだ!ドラゴンがいる + Yes! This is the + $3FC2A (Line 6) (Top Half: MAP LO Bytes) + 95 00 0B 2F 23 40 01 C4 E7 AA ED 26 22 69 | Original Japanese Hex + $3F3C8 (Line 6) (Bottom Half: MAP LO Bytes) + 95 00 0B 3F 33 50 11 D4 F7 BA FD 36 32 79 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN そ う だ ! ド ラ ゴ ン が い る | Original Japanese Text + $3FD0C (Line 6) (Top Half: MAP HI Bytes) + 95 00 82 24 09 25 27 25 24 25 24 25 24 24 | Original Japanese Hex + $3FD1A (Line 6) (Bottom Half: MAP HI Bytes) + 95 00 82 24 ..09 25 27 25 24 25 24 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. .. .. .. .. .. .. .. | Original Japanese Text + + というシマだ!マホウの + island the dragon is on! + $3FC46 (Line 7) (Top Half: MAP LO Bytes) + 95 00 0B 44 22 23 AC CF 40 01 CF CE A3 49 | Original Japanese Hex + $3FC54 (Line 7) (Bottom Half: MAP LO Bytes) + 95 00 0B 54 32 33 BC DF 50 11 DF DE B3 59 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN と い う シ マ だ ! マ ホ ウ の | Original Japanese Text + $3FD28 (Line 7) (Top Half: MAP HI Bytes) + 95 00 85 24 .. .. .. ..02 25 27 84 24 .. .. .. | Original Japanese Hex + $3FD31 (Line 7) (Bottom Half: MAP HI Bytes) + 95 00 85 24 .. .. .. ..02 25 27 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. RAWLEN .. RLELEN RLEBYTE .. .. .. | Original Japanese Text + + ランプよ、きょうもちか + Magic lamp! Lend me your strength + $3FC62 (Line 8) (Top Half: MAP LO Bytes) + 95 00 0B E7 ED CC 66 04 27 0E 23 63 41 26 | Original Japanese Hex + $3FC70 (Line 8) (Bottom Half: MAP LO Bytes) + 95 00 0B F7 FD DC 76 14 37 1E 33 73 51 36 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ラ ン プ よ 、 き ょ う も ち か | Original Japanese Text + $3FD3A (Line 8) (Top Half: MAP HI Bytes) + 95 00 82 24 ..01 26 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $3FD42 (Line 8) (Bottom Half: MAP HI Bytes) + 95 00 82 24 ..01 26 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + らをかしてくれ!さあ! + as you have before! + $3FC7E (Line 9) (Top Half: MAP LO Bytes) + 95 00 0B 67 06 26 2C 43 28 6A 01 2B 21 01 | Original Japanese Hex + $3FC8C (Line 9) (Bottom Half: MAP LO Bytes) + 95 00 0B 77 16 36 3C 53 38 7A 11 3B 31 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ら を か し て く れ ! さ あ ! | Original Japanese Text + $3FD4A (Line 9) (Top Half: MAP HI Bytes) + 95 00 87 24 .. .. .. .. .. ..04 27 24 24 27 | Original Japanese Hex + $3FD53 (Line 9) (Bottom Half: MAP HI Bytes) + 95 00 87 24 .. .. .. .. .. ..04 27 24 24 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN .. .. .. .. | Original Japanese Text + + ぼうけんのせかいへ」 + Let us journey into a world of adventure!" + $3FC9A (Line 10) (Top Half: MAP LO Bytes) + 95 00 0A 4E 23 29 6D 49 2E 26 22 4D 03 | Original Japanese Hex + $3FCA7 (Line 10) (Bottom Half: MAP LO Bytes) + 96 00 0A 5E 33 39 7D 59 3E 36 32 5D 13 FF 00 FF 00 B4 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ぼ う け ん の せ か い へ 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $3FD5C (Line 10) (Top Half: MAP HI Bytes) + 95 00 01 25 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + $3FD62 (Line 10) (Bottom Half: MAP HI Bytes) + 96 00 01 25 89 24 .. .. .. .. .. .. .. .. FF 00 FF 00 B4 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $2722B + 9C FB 87 | Memory Address + + BIT: + いつでも、どこにいても、 + A group of five lads who are best of chums, + $84800 (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C 22 42 43 63 04 44 2A 46 22 43 63 04 | Original Japanese Hex + $8480F (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C 32 52 53 73 14 54 3A 56 32 53 73 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い つ で も 、 ど こ に い て も 、 | Original Japanese Text + $84926 (Line 1) (Top Half: MAP HI Bytes) + E3 00 82 24 ..04 25 24 24 25 86 24 .. .. .. .. .. | Original Japanese Hex + $84931 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..04 25 24 24 25 86 24 .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. .. RLELEN RLEBYTE .. .. .. .. .. | Original Japanese Text + + なかよしゴニングミ。 + whenever and wherever. + $8481E (Line 2) (Top Half: MAP LO Bytes) + 94 00 0A 45 26 66 2C AA C6 ED A8 E0 01 | Original Japanese Hex + $8482B (Line 2) (Bottom Half: MAP LO Bytes) + 96 00 0A 55 36 76 3C BA D6 FD B8 F0 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN な か よ し ゴ ニ ン グ ミ 。 | Original Japanese Text + $8493C (Line 2) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..06 25 24 24 25 24 24 | Original Japanese Hex + $84947 (Line 2) (Bottom Half: MAP HI Bytes) + 96 00 84 24 .. .. ..06 25 24 24 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN .. .. .. .. .. .. | Original Japanese Text + + いつでも、どこにいても、 + A group of five lads who are cheerful, + $84838 (Line 3) (Top Half: MAP LO Bytes) + 96 00 0C 22 42 43 63 04 44 2A 46 22 43 63 04 | Original Japanese Hex + $84847 (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 32 52 53 73 14 54 3A 56 32 53 73 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い つ で も 、 ど こ に い て も 、 | Original Japanese Text + $84952 (Line 3) (Top Half: MAP HI Bytes) + 96 00 82 24 ..04 25 24 24 25 86 24 .. .. .. .. .. | Original Japanese Hex + $8495D (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..04 25 24 24 25 86 24 .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. .. RLELEN .. .. .. .. .. .. | Original Japanese Text + + ヨウキなゴニングミ。 + whenever and wherever. + $84856 (Line 4) (Top Half: MAP LO Bytes) + 94 00 0A E6 A3 A7 45 AA C6 ED A8 E0 01 | Original Japanese Hex + $84863 (Line 4) (Bottom Half: MAP LO Bytes) + 96 00 0A F6 B3 B7 55 BA D6 FD B8 F0 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ヨ ウ キ な ゴ ニ ン グ ミ 。 | Original Japanese Text + $84968 (Line 4) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..06 25 24 24 25 24 24 | Original Japanese Hex + $84973 (Line 4) (Bottom Half: MAP HI Bytes) + 96 00 84 24 .. .. ..06 25 24 24 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN .. .. .. .. .. .. | Original Japanese Text + + きょうもみんなで、たのし + As always, they wander the world + $84870 (Line 5) (Top Half: MAP LO Bytes) + 96 00 0C 27 0E 23 63 60 6D 45 43 04 40 49 2C | Original Japanese Hex + $8487F (Line 5) (Bottom Half: MAP LO Bytes) + 94 00 0C 37 1E 33 73 70 7D 55 53 14 50 59 3C | Original Japanese Hex + RLELEN RLEBYTE RAWLEN き ょ う も み ん な で 、 た の し | Original Japanese Text + $8497E (Line 5) (Top Half: MAP HI Bytes) + 96 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + $84986 (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. | Original Japanese Text + + いたびの、そらのした。 + together, on a fun-filled journey. + $8488E (Line 6) (Top Half: MAP LO Bytes) + 94 00 0B 22 40 4B 49 04 2F 67 49 2C 40 01 | Original Japanese Hex + $8489C (Line 6) (Bottom Half: MAP LO Bytes) + 95 00 0B 32 50 5B 59 14 3F 77 59 3C 50 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い た び の 、 そ ら の し た 。 | Original Japanese Text + $8498E (Line 6) (Top Half: MAP HI Bytes) + 94 00 82 24 01 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $84996 (Line 6) (Bottom Half: MAP HI Bytes) + 95 00 82 24 ..01 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + だれとでも、ドラゴンとで + They want to dance with everyone, including + $848AA (Line 7) (Top Half: MAP LO Bytes) + 95 00 0C 40 6A 44 43 63 04 C4 E7 AA ED 44 43 | Original Japanese Hex + $848B9 (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C 50 7A 54 53 73 14 D4 F7 BA FD 54 53 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN だ れ と で も 、 ド ラ ゴ ン と で | Original Japanese Text + $8499E (Line 7) (Top Half: MAP HI Bytes) + 95 00 0C 25 24 24 25 24 24 25 24 25 24 24 25 | Original Japanese Hex + $849AD (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 0C 25 24 24 25 24 24 25 24 25 24 24 25 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + もヨウキにおどりたい! + the dragon! + $848C8 (Line 8) (Top Half: MAP LO Bytes) + 94 00 0B 63 E6 A3 A7 46 25 44 68 40 22 01 | Original Japanese Hex + $848D6 (Line 8) (Bottom Half: MAP LO Bytes) + 95 00 0B 73 F6 B3 B7 56 35 54 78 50 32 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN も ヨ ウ キ に お ど り た い ! | Original Japanese Text + $849BC (Line 8) (Top Half: MAP HI Bytes) + 94 00 86 24 .. .. .. .. ..01 25 83 24 .. ..01 27 | Original Japanese Hex + $849C6 (Line 8) (Bottom Half: MAP HI Bytes) + 95 00 86 24 .. .. .. .. ..01 25 83 24 .. ..01 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. RAWLEN RLELEN RLEBYTE .. RAWLEN .. | Original Japanese Text + + 「ワーイワーイ!たのしい + "Yippee! We'll have + $848E4 (Line 9) (Top Half: MAP LO Bytes) + 95 00 0C 02 EC A0 A2 EC A0 A2 01 40 49 2C 22 | Original Japanese Hex + $848F3 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 FC B0 B2 FC B0 B2 11 50 59 3C 32 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 ワ ー イ ワ ー イ ! た の し い | Original Japanese Text + $849D0 (Line 9) (Top Half: MAP HI Bytes) + 95 00 87 24 .. .. .. .. .. ..01 27 84 24 .. .. .. | Original Japanese Hex + $849D8 (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 27 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. | Original Japanese Text + + なったら、たのしいな」 + fun, fun, fun!" + $84902 (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B 45 0F 40 67 04 40 49 2C 22 45 03 | Original Japanese Hex + $84910 (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B 55 1F 50 77 14 50 59 3C 32 55 13 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN な っ た ら 、 た の し い な 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $849E0 (Line 10) (Top Half: MAP HI Bytes) + 95 00 8B 24 .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $849E4 (Line 10) (Bottom Half: MAP HI Bytes) + 95 00 8B 24 .. .. .. .. .. .. .. .. .. .. FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27231 + 00 C8 90 | Memory Address + + HALLOWEEN: + おかしとイタズラが、だい + Halloween loves candy + $849F0 (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C 25 26 2C 44 A2 C0 AD E7 26 04 40 22 | Original Japanese Hex + $849FF (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C 35 36 3C 54 B2 D0 BD F7 36 14 50 32 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN お か し と イ タ ズ ラ が 、 だ い | Original Japanese Text + $84B18 (Line 1) (Top Half: MAP HI Bytes) + E3 00 86 24 .. .. .. .. ..06 25 24 25 24 25 24 | Original Japanese Hex + $84B23 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 86 24 .. .. .. .. ..06 25 24 25 24 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. RAWLEN .. .. .. .. .. .. | Original Japanese Text + + スキなハロウィン。 + and mischief. + $84A0E (Line 2) (Top Half: MAP LO Bytes) + 94 00 09 AD A7 45 CA EB A3 88 ED 01 | Original Japanese Hex + $84A1A (Line 2) (Bottom Half: MAP LO Bytes) + 97 00 09 BD B7 55 DA FB B3 98 FD 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ス キ な ハ ロ ウ ィ ン 。 | Original Japanese Text + $84B2E (Line 2) (Top Half: MAP HI Bytes) + 94 00 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + $84B32 (Line 2) (Bottom Half: MAP HI Bytes) + 97 00 89 24 .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. | Original Japanese Text + + いつもおかしのことで、あ + His head is constantly filled + $84A26 (Line 3) (Top Half: MAP LO Bytes) + 97 00 0C 22 42 63 25 26 2C 49 2A 44 43 04 21 | Original Japanese Hex + $84A35 (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 32 52 73 35 36 3C 59 3A 54 53 14 31 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い つ も お か し の こ と で 、 あ | Original Japanese Text + $84B36 (Line 3) (Top Half: MAP HI Bytes) + 97 00 89 24 .. .. .. .. .. .. .. ..03 25 24 24 | Original Japanese Hex + $84B3E (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 89 24 .. .. .. .. .. .. .. ..03 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. .. .. | Original Japanese Text + + たまのなかはいっぱいなん + with thoughts of + $84A44 (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C 40 4F 49 45 26 4A 22 0F 4A 22 45 6D | Original Japanese Hex + $84A53 (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C 50 5F 59 55 36 5A 32 1F 5A 32 55 7D | Original Japanese Hex + RLELEN RLEBYTE RAWLEN た ま の な か は い っ ぱ い な ん | Original Japanese Text + $84B46 (Line 4) (Top Half: MAP HI Bytes) + 94 00 88 24 .. .. .. .. .. .. ..01 26 83 24 .. .. | Original Japanese Hex + $84B4E (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 88 24 .. .. .. .. .. .. ..01 26 83 24 .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. | Original Japanese Text + + だ。このせかいにすんでい + sweets. Naturally, + $84A62 (Line 5) (Top Half: MAP LO Bytes) + 94 00 0C 40 01 2A 49 2E 26 22 46 2D 6D 43 22 | Original Japanese Hex + $84A71 (Line 5) (Bottom Half: MAP LO Bytes) + 94 00 0C 50 11 3A 59 3E 36 32 56 3D 7D 53 32 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN だ 。 こ の せ か い に す ん で い | Original Japanese Text + $84B56 (Line 5) (Top Half: MAP HI Bytes) + 94 00 01 25 89 24 .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + $84B5F (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 01 25 89 24 .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. .. | Original Japanese Text + + る、ドラゴンのひみつのお + he wants nothing more + $84A80 (Line 6) (Top Half: MAP LO Bytes) + 94 00 0C 69 04 C4 E7 AA ED 49 4B 60 42 49 25 | Original Japanese Hex + $84A8F (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 79 14 D4 F7 BA FD 59 5B 70 52 59 35 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN る 、 ド ラ ゴ ン の ひ み つ の お | Original Japanese Text + $84B68 (Line 6) (Top Half: MAP HI Bytes) + 94 00 82 24 ..03 25 24 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + $84B72 (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..03 25 24 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + かしが、たべたくて、たべ + than to eat the Secret Candy of the dragon, that + $84A9E (Line 7) (Top Half: MAP LO Bytes) + 94 00 0C 26 2C 26 04 40 4D 40 28 43 04 40 4D | Original Japanese Hex + $84AAD (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C 36 3C 36 14 50 5D 50 38 53 14 50 5D | Original Japanese Hex + RLELEN RLEBYTE RAWLEN か し が 、 た べ た く て 、 た べ | Original Japanese Text + $84B7C (Line 7) (Top Half: MAP HI Bytes) + 94 00 82 24 ..04 25 24 24 25 85 24 .. .. .. ..01 25 | Original Japanese Hex + $84B89 (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..04 25 24 24 25 85 24 .. .. .. ..01 25 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. .. RLELEN RLEBYTE .. .. .. RAWLEN .. | Original Japanese Text + + たくてしかたがない。 + inhabits this world. + $84ABC (Line 8) (Top Half: MAP LO Bytes) + 94 00 0A 40 28 43 2C 26 40 26 45 22 01 | Original Japanese Hex + $84AC9 (Line 8) (Bottom Half: MAP LO Bytes) + 96 00 0A 50 38 53 3C 36 50 36 55 32 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN た く て し か た が な い 。 | Original Japanese Text + $84B96 (Line 8) (Top Half: MAP HI Bytes) + 94 00 86 24 .. .. .. .. ..01 25 83 24 .. .. | Original Japanese Hex + $84B9E (Line 8) (Bottom Half: MAP HI Bytes) + 96 00 86 24 .. .. .. .. ..01 25 83 24 .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. | Original Japanese Text + + 「どーすればドラゴンのお + "Gee, I wonder how I can get + $84AD6 (Line 9) (Top Half: MAP LO Bytes) + 96 00 0C 02 44 20 2D 6A 4A C4 E7 AA ED 49 25 | Original Japanese Hex + $84AE5 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 54 30 3D 7A 5A D4 F7 BA FD 59 35 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 ど ー す れ ば ド ラ ゴ ン の お | Original Japanese Text + $84BA6 (Line 9) (Top Half: MAP HI Bytes) + 96 00 02 24 25 83 24 .. ..82 25 ..02 24 25 83 24 .. .. | Original Japanese Hex + $84BB4 (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 02 24 25 83 24 .. ..82 25 ..02 24 25 83 24 .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. | Original Japanese Text + + かしがたべれるのかな」 + the dragon's candy?" + $84AF4 (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B 26 2C 26 40 4D 6A 69 49 26 45 03 | Original Japanese Hex + $84B02 (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B 36 3C 36 50 5D 7A 79 59 36 55 13 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN か し が た べ れ る の か な 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $84BC2 (Line 10) (Top Half: MAP HI Bytes) + 95 00 82 24 ..03 25 24 25 86 24 .. .. .. .. .. | Original Japanese Hex + $84BCC (Line 10) (Bottom Half: MAP HI Bytes) + 95 00 82 24 ..03 25 24 25 86 24 .. .. .. .. .. FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. .. RLELEN RLEBYTE .. .. .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27222 + F0 C9 90 | Memory Address + + SHAMAN: + シャーマンいちぞくにつた + The tale of a legendary potion + $84BDE (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C AC 8C A0 CF ED 22 41 2F 28 46 42 40 | Original Japanese Hex + $84BED (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C BC 9C B0 DF FD 32 51 3F 38 56 52 50 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN シ ャ ー マ ン い ち ぞ く に つ た | Original Japanese Text + $84D08 (Line 1) (Top Half: MAP HI Bytes) + E3 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + $84D10 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..01 25 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. | Original Japanese Text + + わる、でんせつのクスリ。 + has been passed down + $84BFC (Line 2) (Top Half: MAP LO Bytes) + 94 00 0C 6C 69 04 43 6D 2E 42 49 A8 AD E8 01 | Original Japanese Hex + $84C0B (Line 2) (Bottom Half: MAP LO Bytes) + 94 00 0C 7C 79 14 53 7D 3E 52 59 B8 BD F8 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN わ る 、 で ん せ つ の ク ス リ 。 | Original Japanese Text + $84D18 (Line 2) (Top Half: MAP HI Bytes) + 94 00 83 24 .. ..01 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $84D20 (Line 2) (Bottom Half: MAP HI Bytes) + 94 00 83 24 .. ..01 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + そのクスリは、どんなビョ + through a family of Shamans + $84C1A (Line 3) (Top Half: MAP LO Bytes) + 94 00 0C 2F 49 A8 AD E8 4A 04 44 6D 45 CB 8E | Original Japanese Hex + $84C29 (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 3F 59 B8 BD F8 5A 14 54 7D 55 DB 9E | Original Japanese Hex + RLELEN RLEBYTE RAWLEN そ の ク ス リ は 、 ど ん な ビ ョ | Original Japanese Text + $84D28 (Line 3) (Top Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..05 25 24 24 25 24 | Original Japanese Hex + $84D32 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. ..05 25 24 24 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. RAWLEN .. .. .. .. .. | Original Japanese Text + + ウキも、なおしてしまうと + a mysterious potion + $84C38 (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C A3 A7 63 04 45 25 2C 43 2C 4F 23 44 | Original Japanese Hex + $84C47 (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C B3 B7 73 14 55 35 3C 53 3C 5F 33 54 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ウ キ も 、 な お し て し ま う と | Original Japanese Text + $84D3C (Line 4) (Top Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $84D40 (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + いうフシギなクスリ。 + which can cure any illness. + $84C56 (Line 5) (Top Half: MAP LO Bytes) + 94 00 0A 22 23 CC AC A7 45 A8 AD E8 01 | Original Japanese Hex + $84C63 (Line 5) (Bottom Half: MAP LO Bytes) + 96 00 0A 32 33 DC BC B7 55 B8 BD F8 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN い う フ シ ギ な ク ス リ 。 | Original Japanese Text + $84D44 (Line 5) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + $84D4C (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + それにはドラゴンのウロコ + What's more, this potion seems to require + $84C70 (Line 6) (Top Half: MAP LO Bytes) + 96 00 0C 2F 6A 46 4A C4 E7 AA ED 49 A3 EB AA | Original Japanese Hex + $84C7F (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 3F 7A 56 5A D4 F7 BA FD 59 B3 FB BA | Original Japanese Hex + RLELEN RLEBYTE RAWLEN そ れ に は ド ラ ゴ ン の ウ ロ コ | Original Japanese Text + $84D54 (Line 6) (Top Half: MAP HI Bytes) + 94 00 84 24 .. .. ..03 25 24 25 85 24 .. .. .. .. | Original Japanese Hex + $84D5E (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..03 25 24 25 85 24 .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN RAWBYTE .. .. RAWLEN .. .. RLELEN RLEBYTE .. .. .. .. | Original Japanese Text + + がひつようらしい・・・・ + a dragon's scale.... + $84C8E (Line 7) (Top Half: MAP LO Bytes) + 94 00 08 26 4B 42 66 23 67 2C 22 84 05 .. .. .. | Original Japanese Hex + $84C9B (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 08 36 5B 52 76 33 77 3C 32 84 15 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN が ひ つ よ う ら し いRLELEN ・ ・ ・ ・ | Original Japanese Text + $84D68 (Line 7) (Top Half: MAP HI Bytes) + 94 00 01 25 8B 24 .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $84D6E (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 01 25 8B 24 .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + 「ンバボボ!ンバボボ!」 + "I shall fetch that dragon's scale!" + $84CA8 (Line 8) (Top Half: MAP LO Bytes) + 94 00 0C 02 ED CA CE CE 01 ED CA CE CE 01 03 | Original Japanese Hex + $84CB7 (Line 8) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 FD DA DE DE 11 FD DA DE DE 11 13 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 ン バ ボ ボ ! ン バ ボ ボ ! 」 | Original Japanese Text + $84D74 (Line 8) (Top Half: MAP HI Bytes) + 94 00 82 24 ..83 25 .. ..02 27 24 83 25 .. ..02 27 24 | Original Japanese Hex + $84D82 (Line 8) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..83 25 .. ..02 27 24 83 25 .. ..02 27 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE .. RAWLEN .. RLELEN RLEBYTE .. RAWLEN .. .. | Original Japanese Text + + (おらが、そのドラゴンの + (I will take that + $84CC6 (Line 9) (Top Half: MAP LO Bytes) + 94 00 0C 08 25 67 26 04 2F 49 C4 E7 AA ED 49 | Original Japanese Hex + $84CD5 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 18 35 77 36 14 3F 59 D4 F7 BA FD 59 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ( お ら が 、 そ の ド ラ ゴ ン の | Original Japanese Text + $84D90 (Line 9) (Top Half: MAP HI Bytes) + 94 00 04 27 24 24 25 83 24 05 25 24 25 24 24 | Original Japanese Hex + $84D9F (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 04 27 24 24 25 83 24 .. ..05 25 24 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. .. .. RLELEN RLEBYTE .. RAWLEN .. .. .. .. .. | Original Japanese Text + + ウロコをとってくるだ) + dragon 's scales) + $84CE4 (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B A3 EB AA 06 44 0F 43 28 69 40 09 | Original Japanese Hex + $84CF2 (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B B3 FB BA 16 54 1F 53 38 79 50 19 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ウ ロ コ を と っ て く る だ ) RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $84DAE (Line 10) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. ..02 25 27 | Original Japanese Hex + $84DB5 (Line 10) (Bottom Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. ..02 25 27 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27228 + DE CB 90 | Memory Address + + PRINCESS: + エルシップジョウにすむ、 + Two princesses, + $855C7 (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C A4 E9 AC 8F CC AC 8E A3 46 2D 61 04 | Original Japanese Hex + $855D6 (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C B4 F9 BC 9F DC BC 9E B3 56 3D 71 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN エ ル シ ッ プ ジ ョ ウ に す む 、 | Original Japanese Text + $856E9 (Line 1) (Top Half: MAP HI Bytes) + E3 00 84 24 .. .. ..02 26 25 86 24 .. .. .. .. .. | Original Japanese Hex + $856F2 (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..02 26 25 86 24 .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN .. RLELEN RLEBYTE .. .. .. .. .. | Original Japanese Text + + ふたりのおひめさま。 + live in L-Ship Castle. + $855E5 (Line 2) (Top Half: MAP LO Bytes) + 94 00 0A 4C 40 68 49 25 4B 62 2B 4F 01 | Original Japanese Hex + $855F2 (Line 2) (Bottom Half: MAP LO Bytes) + 96 00 0A 5C 50 78 59 35 5B 72 3B 5F 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ふ た り の お ひ め さ ま 。 | Original Japanese Text + $856FB (Line 2) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $856FF (Line 2) (Bottom Half: MAP HI Bytes) + 96 00 8A 24 .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. | Original Japanese Text + + あるひ、うえのおひめさま + One day, though + $855FF (Line 3) (Top Half: MAP LO Bytes) + 96 00 0C 21 69 4B 04 23 24 49 25 4B 62 2B 4F | Original Japanese Hex + $8560E (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 31 79 5B 14 33 34 59 35 5B 72 3B 5F | Original Japanese Hex + RLELEN RLEBYTE RAWLEN あ る ひ 、 う え の お ひ め さ ま | Original Japanese Text + $85703 (Line 3) (Top Half: MAP HI Bytes) + 96 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $85707 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + が、ドラゴンにさらわれて + , the elder one was + $8561D (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C 26 04 C4 E7 AA ED 46 2B 67 6C 6A 43 | Original Japanese Hex + $8562C (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C 36 14 D4 F7 BA FD 56 3B 77 7C 7A 53 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN が 、 ド ラ ゴ ン に さ ら わ れ て | Original Japanese Text + $8570B (Line 4) (Top Half: MAP HI Bytes) + 94 00 05 25 24 25 24 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + $85715 (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 05 25 24 25 24 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. .. .. .. RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + しまいました。 + kidnapped by a dragon. + $8563B (Line 5) (Top Half: MAP LO Bytes) + 94 00 07 2C 4F 22 4F 2C 40 01 | Original Japanese Hex + $85645 (Line 5) (Bottom Half: MAP LO Bytes) + 99 00 07 3C 5F 32 5F 3C 50 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN し ま い ま し た 。 | Original Japanese Text + $8571F (Line 5) (Top Half: MAP HI Bytes) + 94 00 87 24 .. .. .. .. .. .. | Original Japanese Hex + $85723 (Line 5) (Bottom Half: MAP HI Bytes) + 99 00 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + ちせいと、ゆうきにあふれ + The younger one, a girl of + $8564F (Line 6) (Top Half: MAP LO Bytes) + 99 00 0C 41 2E 22 44 04 65 23 27 46 21 4C 6A | Original Japanese Hex + $8565E (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 51 3E 32 54 14 75 33 37 56 31 5C 7A | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ち せ い と 、 ゆ う き に あ ふ れ | Original Japanese Text + $85727 (Line 6) (Top Half: MAP HI Bytes) + 99 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $8572B (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + るおひめさまは、あねをた + much intellect, and courage + $8566D (Line 7) (Top Half: MAP LO Bytes) + 94 00 0C 69 25 4B 62 2B 4F 4A 04 21 48 06 40 | Original Japanese Hex + $8567C (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C 79 35 5B 72 3B 5F 5A 14 31 58 16 50 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN る お ひ め さ ま は 、 あ ね を た | Original Japanese Text + $8572F (Line 7) (Top Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $85733 (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + すけに、たびだちます。 + set out on a journey to save her sister. + $8568B (Line 8) (Top Half: MAP LO Bytes) + 94 00 0B 2D 29 46 04 40 4B 40 41 4F 2D 01 | Original Japanese Hex + $85699 (Line 8) (Bottom Half: MAP LO Bytes) + 95 00 0B 3D 39 56 14 50 5B 50 51 5F 3D 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN す け に 、 た び だ ち ま す 。 | Original Japanese Text + $85737 (Line 8) (Top Half: MAP HI Bytes) + 94 00 85 24 .. .. .. ..82 25 ..84 24 .. .. .. | Original Japanese Hex + $8573F (Line 8) (Bottom Half: MAP HI Bytes) + 95 00 85 24 .. .. .. ..82 25 ..84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. | Original Japanese Text + + 「ねえさま、まっててね! + "Hold on, Sister! + $856A7 (Line 9) (Top Half: MAP LO Bytes) + 95 00 0C 02 48 24 2B 4F 04 4F 0F 43 43 48 01 | Original Japanese Hex + $856B6 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 58 34 3B 5F 14 5F 1F 53 53 58 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 ね え さ ま 、 ま っ て て ね ! | Original Japanese Text + $85747 (Line 9) (Top Half: MAP HI Bytes) + 95 00 8B 24 .. .. .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + $8574D (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 8B 24 .. .. .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. RAWLEN .. | Original Japanese Text + + わたし・・まけない!」 + I-I won't fail!" + $856C5 (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B 6C 40 2C 05 05 4F 29 45 22 01 03 | Original Japanese Hex + $856D3 (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B 7C 50 3C 15 15 5F 39 55 32 11 13 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN わ た し ・ ・ ま け な い ! 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $85753 (Line 10) (Top Half: MAP HI Bytes) + 95 00 89 24 .. .. .. .. .. .. .. ..02 27 24 | Original Japanese Hex + $8575A (Line 10) (Bottom Half: MAP HI Bytes) + 95 00 89 24 .. .. .. .. .. .. .. ..02 27 24 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $2722E + C7 D5 90 | Memory Address + + MIRURUN: + こころやさしいミルルン。 + A creature with a heart of gold. + $85913 (Line 1) (Top Half: MAP LO Bytes) + E3 00 82 2A 0A 6B 64 2B 2C 22 E0 E9 E9 ED 01 | Original Japanese Hex + $85922 (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 82 3A 0A 7B 74 3B 3C 32 F0 F9 F9 FD 11 | Original Japanese Hex + RLELEN RLEBYTE RLELEN こ こRAWLEN ろ や さ し い ミ ル ル ン 。 | Original Japanese Text + $85A1B (Line 1) (Top Half: MAP HI Bytes) + E3 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $85A1F (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + きょうも、あしたも、その + Mirurun will continue + $85931 (Line 2) (Top Half: MAP LO Bytes) + 94 00 0C 27 0E 23 63 04 21 2C 40 63 04 2F 49 | Original Japanese Hex + $85940 (Line 2) (Bottom Half: MAP LO Bytes) + 94 00 0C 37 1E 33 73 14 31 3C 50 73 14 3F 59 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN き ょ う も 、 あ し た も 、 そ の | Original Japanese Text + $85A23 (Line 2) (Top Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $85A27 (Line 2) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + またつぎのひも、トモダチ + its journey to find friends + $8594F (Line 3) (Top Half: MAP LO Bytes) + 94 00 0C 4F 40 42 27 49 4B 63 04 C4 E3 C0 C1 | Original Japanese Hex + $8595E (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 5F 50 52 37 59 5B 73 14 D4 F3 D0 D1 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ま た つ ぎ の ひ も 、 ト モ ダ チ | Original Japanese Text + $85A2B (Line 3) (Top Half: MAP HI Bytes) + 94 00 83 24 .. ..01 25 86 24 .. .. .. .. ..02 25 24 | Original Japanese Hex + $85A36 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 83 24 .. ..01 25 86 24 .. .. .. .. ..02 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. RAWLEN RLELEN RLEBYTE .. .. .. .. RAWLEN .. .. | Original Japanese Text + + もとめてミルルンのたびは + today, tomorrow, and the day + $8596D (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C 63 44 62 43 E0 E9 E9 ED 49 40 4B 4A | Original Japanese Hex + $8597C (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C 73 54 72 53 F0 F9 F9 FD 59 50 5B 5A | Original Japanese Hex + RLELEN RLEBYTE RAWLEN も と め て ミ ル ル ン の た び は | Original Japanese Text + $85A41 (Line 4) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + $85A48 (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. RAWLEN .. .. | Original Japanese Text + + つづきます。 + after that. + $8598B (Line 5) (Top Half: MAP LO Bytes) + 94 00 82 42 ..04 27 4F 2D 01 | Original Japanese Hex + $85994 (Line 5) (Bottom Half: MAP LO Bytes) + 9A 00 82 52 ..04 37 5F 3D 11 | Original Japanese Hex + RLELEN RLEBYTE RLELEN つ づRAWLEN き ま す 。 | Original Japanese Text + $85A4F (Line 5) (Top Half: MAP HI Bytes) + 94 00 02 24 25 84 24 .. .. .. | Original Japanese Hex + $85A56 (Line 5) (Bottom Half: MAP HI Bytes) + 9A 00 02 24 25 84 24 .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. .. | Original Japanese Text + + さあ、きょうもあたらしい + And so, as always, Mirurun + $8599D (Line 6) (Top Half: MAP LO Bytes) + 9A 00 0C 2B 21 04 27 0E 23 63 21 40 67 2C 22 | Original Japanese Hex + $859AC (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 3B 31 14 37 1E 33 73 31 50 77 3C 32 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN さ あ 、 き ょ う も あ た ら し い | Original Japanese Text + $85A5D (Line 6) (Top Half: MAP HI Bytes) + 9A 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + $85A61 (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 8C 24 .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. .. .. .. | Original Japanese Text + + であいが、ミルルンをまっ + is waiting, to meet someone + $859BB (Line 7) (Top Half: MAP LO Bytes) + 94 00 0C 43 21 22 26 04 E0 E9 E9 ED 06 4F 0F | Original Japanese Hex + $859CA (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C 53 31 32 36 14 F0 F9 F9 FD 16 5F 1F | Original Japanese Hex + RLELEN RLEBYTE RAWLEN で あ い が 、 ミ ル ル ン を ま っ | Original Japanese Text + $85A65 (Line 7) (Top Half: MAP HI Bytes) + 94 00 04 25 24 24 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + $85A6E (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 04 25 24 24 25 88 24 .. .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. .. .. RLELEN RLEBYTE .. .. .. .. .. .. .. | Original Japanese Text + + ています。 + new. + $859D9 (Line 8) (Top Half: MAP LO Bytes) + 94 00 05 43 22 4F 2D 01 | Original Japanese Hex + $859E1 (Line 8) (Bottom Half: MAP LO Bytes) + 9B 00 05 53 32 5F 3D 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN て い ま す 。 | Original Japanese Text + $85A77 (Line 8) (Top Half: MAP HI Bytes) + 94 00 85 24 .. .. .. .. | Original Japanese Hex + $85A7B (Line 8) (Bottom Half: MAP HI Bytes) + 9B 00 85 24 .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. | Original Japanese Text + + 「ぼくとトモダチになって + "Will you be my + $859E9 (Line 9) (Top Half: MAP LO Bytes) + 9B 00 0C 02 4E 28 44 C4 E3 C0 C1 46 45 0F 43 | Original Japanese Hex + $859F8 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 5E 38 54 D4 F3 D0 D1 56 55 1F 53 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 ぼ く と ト モ ダ チ に な っ て | Original Japanese Text + $85A7F (Line 9) (Top Half: MAP HI Bytes) + 9B 00 02 24 25 84 24 .. .. ..01 25 85 24 .. .. .. .. | Original Japanese Hex + $85A8A (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 02 24 25 84 24 .. .. ..01 25 85 24 .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. RAWLEN RLELEN RLEBYTE .. .. .. .. | Original Japanese Text + + ね!」 + friend!" + $85A07 (Line 10) (Top Half: MAP LO Bytes) + 95 00 03 48 01 03 | Original Japanese Hex + $85A0D (Line 10) (Bottom Half: MAP LO Bytes) + 9D 00 03 58 11 13 FF 00 FF 00 BB 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ね ! 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $85A95 (Line 10) (Top Half: MAP HI Bytes) + 95 00 03 24 27 24 | Original Japanese Hex + $85A9B (Line 10) (Bottom Half: MAP HI Bytes) + 9D 00 03 24 27 24 FF 00 FF 00 BB 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN .. .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27225 + 13 D9 90 | Memory Address + + WOLFMAN: + ひさかたぶりに、こきょう + I returned to my homeland, after + $D7E13 (Line 1) (Top Half: MAP LO Bytes) + E3 00 0C 4B 2B 26 40 4C 68 46 04 2A 27 0E 23 | Original Japanese Hex + $D7E22 (Line 1) (Bottom Half: MAP LO Bytes) + 94 00 0C 5B 3B 36 50 5C 78 56 14 3A 37 1E 33 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN ひ さ か た ぶ り に 、 こ き ょ う | Original Japanese Text + $D7F43 (Line 1) (Top Half: MAP HI Bytes) + E3 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + $D7F4B (Line 1) (Bottom Half: MAP HI Bytes) + 94 00 84 24 .. .. ..01 25 87 24 .. .. .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. RAWLEN RLELEN RLEBYTE .. .. .. .. .. .. | Original Japanese Text + + のクニにかえってみれば、 + a great many years, + $D7E31 (Line 2) (Top Half: MAP LO Bytes) + 94 00 0C 49 A8 C6 46 26 24 0F 43 60 6A 4A 04 | Original Japanese Hex + $D7E40 (Line 2) (Bottom Half: MAP LO Bytes) + 94 00 0C 59 B8 D6 56 36 34 1F 53 70 7A 5A 14 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN の ク ニ に か え っ て み れ ば 、 | Original Japanese Text + $D7F53 (Line 2) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + $D7F5A (Line 2) (Bottom Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. RAWLEN .. .. | Original Japanese Text + + なんとクニはおおさわぎ! + only to find it in an uproar! + $D7E4F (Line 3) (Top Half: MAP LO Bytes) + 94 00 0C 45 6D 44 A8 C6 4A 25 25 2B 6C 27 01 | Original Japanese Hex + $D7E5E (Line 3) (Bottom Half: MAP LO Bytes) + 94 00 0C 55 7D 54 B8 D6 5A 35 35 3B 7C 37 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN な ん と ク ニ は お お さ わ ぎ ! | Original Japanese Text + $D7F61 (Line 3) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 27 | Original Japanese Hex + $D7F68 (Line 3) (Bottom Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..02 25 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. RAWLEN .. .. | Original Japanese Text + + おひめさまが、ドラゴンに + The princess, has been + $D7E6D (Line 4) (Top Half: MAP LO Bytes) + 94 00 0C 25 4B 62 2B 4F 26 04 C4 E7 AA ED 46 | Original Japanese Hex + $D7E7C (Line 4) (Bottom Half: MAP LO Bytes) + 94 00 0C 35 5B 72 3B 5F 36 14 D4 F7 BA FD 56 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN お ひ め さ ま が 、 ド ラ ゴ ン に | Original Japanese Text + $D7F6F (Line 4) (Top Half: MAP HI Bytes) + 94 00 85 24 .. .. .. ..07 25 24 25 24 25 24 24 | Original Japanese Hex + $D7F7B (Line 4) (Bottom Half: MAP HI Bytes) + 94 00 85 24 .. .. .. ..07 25 24 25 24 25 24 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. RAWLEN .. .. .. .. .. .. .. | Original Japanese Text + + かどわかされてしまった! + kidnapped by a dragon! + $D7E8B (Line 5) (Top Half: MAP LO Bytes) + 94 00 0C 26 44 6C 26 2B 6A 43 2C 4F 0F 40 01 | Original Japanese Hex + $D7E9A (Line 5) (Bottom Half: MAP LO Bytes) + 94 00 0C 36 54 7C 36 3B 7A 53 3C 5F 1F 50 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN か ど わ か さ れ て し ま っ た ! | Original Japanese Text + $D7F87 (Line 5) (Top Half: MAP HI Bytes) + 94 00 02 24 25 89 24 .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + $D7F90 (Line 5) (Bottom Half: MAP HI Bytes) + 94 00 02 24 25 89 24 .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. .. .. .. .. .. RAWLEN .. | Original Japanese Text + + このままみすごす、わけに + I can't stand by, and + $D7EA9 (Line 6) (Top Half: MAP LO Bytes) + 94 00 0C 2A 49 4F 4F 60 2D 2A 2D 04 6C 29 46 | Original Japanese Hex + $D7EB8 (Line 6) (Bottom Half: MAP LO Bytes) + 94 00 0C 3A 59 5F 5F 70 3D 3A 3D 14 7C 39 56 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN こ の ま ま み す ご す 、 わ け に | Original Japanese Text + $D7F99 (Line 6) (Top Half: MAP HI Bytes) + 94 00 86 24 .. .. .. .. ..01 25 85 24 .. .. .. .. | Original Japanese Hex + $D7FA1 (Line 6) (Bottom Half: MAP HI Bytes) + 94 00 86 24 .. .. .. .. ..01 25 85 24 .. .. .. .. | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. .. | Original Japanese Text + + はいかねえ!おとこいっぴ + do nothing! A real + $D7EC7 (Line 7) (Top Half: MAP LO Bytes) + 94 00 0C 4A 22 26 48 24 01 25 44 2A 22 0F 4B | Original Japanese Hex + $D7ED6 (Line 7) (Bottom Half: MAP LO Bytes) + 94 00 0C 5A 32 36 58 34 11 35 54 3A 32 1F 5B | Original Japanese Hex + RLELEN RLEBYTE RAWLEN は い か ね え ! お と こ い っ ぴ | Original Japanese Text + $D7FA9 (Line 7) (Top Half: MAP HI Bytes) + 94 00 85 24 .. .. .. ..01 27 85 24 .. .. .. ..01 26 | Original Japanese Hex + $D7FB3 (Line 7) (Bottom Half: MAP HI Bytes) + 94 00 85 24 .. .. .. ..01 27 85 24 .. .. .. ..01 26 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. RAWLEN RLELEN RLEBYTE .. .. .. RAWLEN .. | Original Japanese Text + + き、あとにはひかねえ! + man, does not back down! + $D7EE5 (Line 8) (Top Half: MAP LO Bytes) + 94 00 0B 27 04 21 44 46 4A 4B 26 48 24 01 | Original Japanese Hex + $D7EF3 (Line 8) (Bottom Half: MAP LO Bytes) + 95 00 0B 37 14 31 54 56 5A 5B 36 58 34 11 | Original Japanese Hex + RLELEN RLEBYTE RAWLEN き 、 あ と に は ひ か ね え ! | Original Japanese Text + $D7FBD (Line 8) (Top Half: MAP HI Bytes) + 94 00 8A 24 .. .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + $D7FC3 (Line 8) (Bottom Half: MAP HI Bytes) + 95 00 8A 24 .. .. .. .. .. .. .. .. ..01 27 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE .. .. .. .. .. .. .. .. RAWLEN .. | Original Japanese Text + + 「いざ!せっしゃと、じん + "Come, fight me + $D7F01 (Line 9) (Top Half: MAP LO Bytes) + 95 00 0C 02 22 2B 01 2E 0F 2C 0C 44 04 2C 6D | Original Japanese Hex + $D7F10 (Line 9) (Bottom Half: MAP LO Bytes) + 94 00 0C 12 32 3B 11 3E 1F 3C 1C 54 14 3C 7D | Original Japanese Hex + RLELEN RLEBYTE RAWLEN 「 い ざ ! せ っ し ゃ と 、 じ ん | Original Japanese Text + $D7FC9 (Line 9) (Top Half: MAP HI Bytes) + 95 00 82 24 ..02 25 27 86 24 .. .. .. .. ..02 25 24 | Original Japanese Hex + $D7FD5 (Line 9) (Bottom Half: MAP HI Bytes) + 94 00 82 24 ..02 25 27 86 24 .. .. .. .. ..02 25 24 | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLEBYTE RAWLEN .. RLELEN RLEBYTE .. .. .. .. RAWLEN .. .. | Original Japanese Text + + じょうにしょうぶだ!」 + with honor!" + $D7F1F (Line 10) (Top Half: MAP LO Bytes) + 95 00 0B 2C 0E 23 46 2C 0E 23 4C 40 01 03 | Original Japanese Hex + $D7F2D (Line 10) (Bottom Half: MAP LO Bytes) + 95 00 0B 3C 1E 33 56 3C 1E 33 5C 50 11 13 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RAWLEN じ ょ う に し ょ う ぶ だ ! 」 RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + $D7FE1 (Line 10) (Top Half: MAP HI Bytes) + 95 00 01 25 86 24 .. .. .. .. ..82 25 ..02 27 24 | Original Japanese Hex + $D7FEC (Line 10) (Bottom Half: MAP HI Bytes) + 95 00 01 25 86 24 .. .. .. .. ..82 25 ..02 27 24 FF 00 FF 00 B3 00 00 FF | Original Japanese Hex + RLELEN RLEBYTE RLELEN RLELEN RLEBYTE .. .. .. .. RLELEN RLEBYTE RAWLEN .. .. RLELEN RLEBYTE RLELEN RLEBYTE RLELEN RLEBYTE RLEEND # | Original Japanese Text + + $27237 + 13 FE 9A | Memory Address \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERSELECT.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERSELECT.txt new file mode 100644 index 00000000..a93de835 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/CHARACTERSELECT.txt @@ -0,0 +1,442 @@ +CHARACTER SELECT MAGIC: + MAGIC01: + ミルルン + Mirurun + $5442 + D0 00 D9 00 D9 00 DD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ミ # ル # ル # ン # # # # # | Original Japanese Text + + MAGIC02: + コピー + Copy + $5452 + BA 00 CB 00 DF 00 B0 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + コ # ヒ # o # ー # # # # # | Original Japanese Text + + MAGIC03: + メデューサ + Medusa + $5462 + D2 00 C3 00 DE 00 AD 00 B0 00 BB 00 A5 00 A5 00 | Original Japanese Hex + メ # テ # " # ュ # ー # サ # # # | Original Japanese Text + + MAGIC04: + ボム + Bomb + $5472 + CE 00 DE 00 D1 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ホ # " # ム # # # # # # | Original Japanese Text + + MAGIC05: + マヤカシ + Deception/Fake/Make-Believe/Fake/Counterfeit/Phony + $5482 + CF 00 D4 00 B6 00 BC 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + マ # ヤ # カ # シ # # # # # | Original Japanese Text + + MAGIC06: + ペンタリス + Pentris + $5492 + CD 00 DF 00 DD 00 C0 00 D8 00 BD 00 A5 00 A5 00 | Original Japanese Hex + ヘ # o # ン # タ # リ # ス # # # | Original Japanese Text + + MAGIC07: + ダイナシ + Spoil/Shamble/Destroy + $54A2 + C0 00 DE 00 B2 00 C5 00 BC 00 A5 00 A5 00 A5 00 | Original Japanese Hex + タ # " # イ # ナ # シ # # # # | Original Japanese Text + + MAGIC08: + フライ + Fry + $54B2 + CC 00 D7 00 B2 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + フ # ラ # イ # # # # # # | Original Japanese Text + + MAGIC09: + ノロイ + Curse + $54C2 + C9 00 DB 00 B2 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ノ # ロ # イ # # # # # # | Original Japanese Text + + MAGIC10: + バンパイア + Vampire + $54D2 + CA 00 DE 00 DD 00 CA 00 DF 00 B2 00 B1 00 A5 00 | Original Japanese Hex + ハ # " # ン # ハ # o # イ # ア # # | Original Japanese Text + + MAGIC11: + クリアー + Clear + $54E2 + B8 00 D8 00 B1 00 B0 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ク # リ # ア # ー # # # # # | Original Japanese Text + + MAGIC12: + シーソー + Seesaw + $54F2 + BC 00 B0 00 BF 00 B0 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + シ # ー # ソ # ー # # # # # | Original Japanese Text + + MAGIC12: + シーソー + Seesaw + $5502 + A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + # # # # # # # # | Original Japanese Text + + MAGIC12: + シーソー + Seesaw + $5512 + A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + # # # # # # # # | Original Japanese Text + + MAGIC13: + カット + Cut / Slice + $5522 + B6 00 AF 00 C4 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + カ # ッ # ト # # # # # # | Original Japanese Text + + MAGIC14: + モーゼ + Moses + $5532 + D3 00 B0 00 BE 00 DE 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + モ # ー # セ # " # # # # # | Original Japanese Text + + MAGIC15: + マンボ + Mambo + $5542 + CF 00 DD 00 CE 00 DE 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + マ # ン # ホ # " # # # # # | Original Japanese Text + + MAGIC16: + スターダスト + Stardust + $5552 + BD 00 C0 00 B0 00 C0 00 DE 00 BD 00 C4 00 A5 00 | Original Japanese Hex + ス # タ # ー # タ # " # ス # ト # # | Original Japanese Text + + MAGIC17: + リバース + Reverse + $5562 + D8 00 CA 00 DE 00 B0 00 BD 00 A5 00 A5 00 A5 00 | Original Japanese Hex + リ # ハ # " # ー # ス # # # # | Original Japanese Text + + MAGIC18: + マヒ + Paralyze + $5572 + CF 00 CB 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + マ # ヒ # # # # # # # | Original Japanese Text + + MAGIC19: + カイテン + Rotate/Rotation + $5582 + B6 00 B2 00 C3 00 DD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + カ # イ # テ # ン # # # # # | Original Japanese Text + + MAGIC20: + ヨセ + Yose / Gather + $5592 + D6 00 BE 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ヨ # セ # # # # # # # | Original Japanese Text + + MAGIC21: + ギャング + Gang + $55A2 + B7 00 DE 00 AC 00 DD 00 B8 00 DE 00 A5 00 A5 00 | Original Japanese Hex + キ # " # ャ # ン # ク # " # # # | Original Japanese Text + + MAGIC22: + ドトン + Earth Release/Rensa + $55B2 + C4 00 DE 00 C4 00 DD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ト # " # ト # ン # # # # # | Original Japanese Text + + MAGIC23: + プレス + Press / Crush / Stomp + $55C2 + CC 00 DF 00 DA 00 BD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + フ # o # レ # ス # # # # # | Original Japanese Text + + MAGIC24: + ソル + Soul + $55D2 + BF 00 D9 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ソ # ル # # # # # # # | Original Japanese Text + + MAGIC25: + スリトテ + Sirtet + $55E2 + BD 00 D8 00 C4 00 C3 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ス # リ # ト # テ # # # # # | Original Japanese Text + + MAGIC26: + ファックス + Fax + $55F2 + CC 00 A7 00 AF 00 B8 00 BD 00 A5 00 A5 00 A5 00 | Original Japanese Hex + フ # ァ # ッ # ク # ス # # # # | Original Japanese Text + + MAGIC27: + シールド + Shield + $5602 + BC 00 B0 00 D9 00 C4 00 DE 00 A5 00 A5 00 A5 00 | Original Japanese Hex + シ # ー # ル # ト # " # # # # | Original Japanese Text + + MAGIC28: + ミラー + Mirror + $5612 + D0 00 D7 00 B0 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ミ # ラ # ー # # # # # # | Original Japanese Text + + MAGIC29: + ヘビー + Heavy + $5622 + CD 00 CB 00 DE 00 B0 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ヘ # ヒ # " # ー # # # # # | Original Japanese Text + + MAGIC30: + セレクト + Select + $5632 + BE 00 DA 00 B8 00 C4 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + セ # レ # ク # ト # # # # # | Original Japanese Text + + MAGIC31: + ヌー + Slow Down/Gnu/Wildebeest/Nu/New/Noose + $5642 + C7 00 B0 00 A5 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ヌ # ー # # # # # # # | Original Japanese Text + + MAGIC32: + リモコン + Remote Control + $5652 + D8 00 D3 00 BA 00 DD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + リ # モ # コ # ン # # # # # | Original Japanese Text + + MAGIC33: + ハンテン + Reversal/Reverse/Invert/Flip + $5662 + CA 00 DD 00 C3 00 DD 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ハ # ン # テ # ン # # # # # | Original Japanese Text + + MAGIC34: + ナカヨシ + Chum / Buddy / Buddies / Friend / Heal + $5672 + C5 00 B6 00 D6 00 BC 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ナ # カ # ヨ # シ # # # # # | Original Japanese Text + + MAGIC35: + イノリ + Pray/Prayer + $5682 + B2 00 C9 00 D8 00 A5 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + イ # ノ # リ # # # # # # | Original Japanese Text + + MAGIC36: + ルーレット + Roulette + $5692 + D9 00 B0 00 DA 00 AF 00 C4 00 A5 00 A5 00 A5 00 | Original Japanese Hex + ル # ー # レ # ッ # ト # # # # | Original Japanese Text + + MAGIC37: + フィーバー + Fever + $56A2 + CC 00 A8 00 B0 00 CA 00 DE 00 B0 00 A5 00 A5 00 | Original Japanese Hex + フ # ィ # ー # ハ # " # ー # # # | Original Japanese Text + + MAGIC38: + チェンジ + Change + $56B2 + C1 00 AA 00 DD 00 BC 00 DE 00 A5 00 A5 00 A5 00 | Original Japanese Hex + チ # ェ # ン # シ # " # # # # | Original Japanese Text + + MAGIC39: + ダブルス + Doubles + $56C2 + C0 00 DE 00 CC 00 DE 00 D9 00 BD 00 A5 00 A5 00 | Original Japanese Hex + タ # " # フ # " # ル # ス # # # | Original Japanese Text + + MAGIC40: + ダーク + Dark + $56D2 + C0 00 DE 00 B0 00 B8 00 A5 00 A5 00 A5 00 A5 00 | Original Japanese Hex + タ # " # ー # ク # # # # # | Original Japanese Text + + MAGIC41: + ハイパーフライ + HyperFry + $56E2 + CA 00 B2 00 CA 00 DF 00 B0 00 CC 00 D7 00 B2 00 | Original Japanese Hex + ハ # イ # ハ # o # ー # フ # ラ # イ # | Original Japanese Text + +CHARACTER SELECT NAME: + ハロウィン + Halloween + $1A313 (Top Half) + DE 01 B0 01 B1 01 B2 01 B3 01 B4 01 DE 01 | Original Japanese Hex + # ハ # ロ # ウ # ィ # ン # # | Original Japanese Text + H # A # L # L # O # W # E # | New English Text + B7 01 B0 01 BB 01 BB 01 BE 01 D6 01 B4 01 | New English Hex + $1A321 (Bottom Half) + DE 01 C0 01 C1 01 C2 01 C3 01 C4 01 DE 01 | Original Japanese Hex + # ハ # ロ # ウ # ィ # ン # # | Original Japanese Text + H # A # L # L # O # W # E # | New English Text + C7 01 C0 01 CB 01 CB 01 CE 01 E6 01 C4 01 | New English Hex + $1A303 + 13 A3 | Memory Address + + ミルルン + Mirurun + $1A32F (Top Half) + DE 01 DE 01 BF 01 D0 01 D0 01 B4 01 DE 01 | Original Japanese Hex + # # ミ # ル # ル # ン # # | Original Japanese Text + M # I # R # U # R # U # N # | New English Text + BC 01 B8 01 D1 01 D4 01 D1 01 D4 01 BD 01 | New English Hex + $1A33D (Bottom Half) + DE 01 DE 01 CF 01 E0 01 E0 01 C4 01 DE 01 | Original Japanese Hex + # # ミ # ル # ル # ン # # | Original Japanese Text + M # I # R # U # R # U # N # | New English Text + CC 01 C8 01 E1 01 E4 01 E1 01 E4 01 CD 01 | New English Hex + $1A305 + 2F A3 | Memory Address + + シャーマン + Shaman + $1A34B (Top Half) + DE 01 B5 01 B6 01 B7 01 B8 01 B4 01 DE 01 | Original Japanese Hex + # シ # ャ # ー # マ # ン # # | Original Japanese Text + # S # H # A # M # A # N # | New English Text + DE 01 D2 01 B7 01 B0 01 BC 01 B0 01 BD 01 | New English Hex + $1A359 (Bottom Half) + DE 01 C5 01 C6 01 C7 01 C8 01 C4 01 DE 01 | Original Japanese Hex + # シ # ャ # ー # マ # ン # # | Original Japanese Text + # S # H # A # M # A # N # | New English Text + DE 01 E2 01 C7 01 C0 01 CC 01 C0 01 CD 01 | New English Hex + $1A307 + 4B A3 | Memory Address + + アラジン + Aladdin + $1A367 (Top Half) + DE 01 B9 01 BA 01 B5 01 BB 01 B4 01 DE 01 | Original Japanese Hex + # ア # ラ # シ # " # ン # # | Original Japanese Text + A # L # A # D # D # I # N # | New English Text + B0 01 BB 01 B0 01 B3 01 B3 01 B8 01 BD 01 | New English Hex + $1A375 (Bottom Half) + DE 01 C9 01 CA 01 C5 01 CB 01 C4 01 DE 01 | Original Japanese Hex + # ア # ラ # シ # " # ン # # | Original Japanese Text + A # L # A # D # D # I # N # | New English Text + C0 01 CB 01 C0 01 C3 01 C3 01 C8 01 CD 01 | New English Hex + $1A309 + 67 A3 | Memory Address + + プリンセス + Princess + $1A383 (Top Half) + DE 01 D1 01 D2 01 D3 01 B4 01 D4 01 D5 01 | Original Japanese Hex + # フ # o # リ # ン # セ # ス # | Original Japanese Text + P # R # I # N # C # E # S # | New English Text + BF 01 D1 01 B8 01 BD 01 B2 01 B4 01 D2 01 | New English Hex + $1A391 (Bottom Half) + DE 01 E1 01 E2 01 E3 01 C4 01 E4 01 E5 01 | Original Japanese Hex + # フ # o # リ # ン # セ # ス # | Original Japanese Text + P # R # I # N # C # E # S # | New English Text + CF 01 E1 01 C8 01 CD 01 C2 01 C4 01 E2 01 | New English Hex + $1A30B + 83 A3 | Memory Address + + ビット + Bit + $1A39F (Top Half) + DE 01 DE 01 BC 01 BB 01 BD 01 BE 01 DE 01 | Original Japanese Hex + # # ヒ # " # ッ # ト # # | Original Japanese Text + # # B # I # T # # # | New English Text + DE 01 DE 01 B1 01 B8 01 D3 01 DE 01 DE 01 | New English Hex + $1A3AD (Bottom Half) + DE 01 DE 01 CC 01 CB 01 CD 01 CE 01 DE 01 | Original Japanese Hex + # # ヒ # " # ッ # ト # # | Original Japanese Text + # # B # I # T # # # | New English Text + DE 01 DE 01 C1 01 C8 01 E3 01 DE 01 DE 01 | New English Hex + $1A30D + 9F A3 | Memory Address + + ニンジャ + Ninja + $1A3BB (Top Half) + DE 01 D7 01 B4 01 B5 01 BB 01 B6 01 DE 01 | Original Japanese Hex + # ニ # ン # シ # " # ャ # # | Original Japanese Text + # N # I # N # J # A # # | New English Text + DE 01 BD 01 B8 01 BD 01 B9 01 B0 01 DE 01 | New English Hex + $1A3C9 (Bottom Half) + DE 01 E7 01 C4 01 C5 01 CB 01 C6 01 DE 01 | Original Japanese Hex + # ニ # ン # シ # " # ャ # # | Original Japanese Text + # N # I # N # J # A # # | New English Text + DE 01 CD 01 C8 01 CD 01 C9 01 C0 01 DE 01 | New English Hex + $1A30F + BB A3 | Memory Address + + オオカミオトコ + Wolfman + $1A3D7 (Top Half) + DB 01 DB 01 DC 01 BF 01 DB 01 BE 01 DD 01 | Original Japanese Hex + オ # オ # カ # ミ # オ # ト # コ # | Original Japanese Text + W # O # L # F # M # A # N # | New English Text + D6 01 BE 01 BB 01 B5 01 BC 01 B0 01 BD 01 | New English Hex + $1A3E5 (Bottom Half) + EB 01 EB 01 EC 01 CF 01 EB 01 CE 01 ED 01 | Original Japanese Hex + オ # オ # カ # ミ # オ # ト # コ # | Original Japanese Text + W # O # L # F # M # A # N # | New English Text + E6 01 CE 01 CB 01 C5 01 CC 01 C0 01 CD 01 | New English Hex + $1A311 + D7 A3 | Memory Address + +CHARACTER SELECTION: + もくじ + Table of Contents + $3D271 (Top Half: MAP LO Bytes) + 05 DC 12 DD 12 DE | Original Japanese Hex + RAW も く じ | Original Japanese Text + RAW T O C | New English Text + 05 D3 12 BE 12 B2 | New English Hex + $3D4EB (Top Half: MAP HI Bytes) + 08 28 08 28 08 | Original Japanese Hex + 29 28 29 28 29 | New English Hex + $3D28B (Bottom Half: MAP LO Bytes) + 05 EC 12 ED 12 EE | Original Japanese Hex + RAW も く じ | Original Japanese Text + RAW T O C | New English Text + 05 E3 12 CE 12 C2 | New English Hex + $3D505 (Bottom Half: MAP HI Bytes) + 08 28 08 28 08 | Original Japanese Hex + 29 28 29 28 29 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/INTRO.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/INTRO.txt new file mode 100644 index 00000000..d43b041e --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/INTRO.txt @@ -0,0 +1,536 @@ +HALLOWEEN: + ハロウィン + Halloween + $1B26F (Top Half) + 00 00 C0 C1 C2 C3 C4 00 00 00 | Original Japanese Hex + ハ ロ ウ ィ ン | Original Japanese Text + H A L L O W E E N | New English Text + C7 C0 CB CB CE E6 C4 C4 CD 00 | New English Hex + $1B279 (Bottom Half) + 00 00 D0 D1 D2 D3 D4 00 00 00 | Original Japanese Hex + ハ ロ ウ ィ ン | Original Japanese Text + H A L L O W E E N | New English Text + D7 D0 DB DB DE F6 D4 D4 DD 00 | New English Hex + + すきなもの + Favorite Things: + $1B283 (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + チョコレートケーキ + Chocolate Cake + $1B28D (Line 2) + 5B C1 AE BA DA B0 C4 B9 B0 B7 5D 20 | Original Japanese Hex + [ チ ョ コ レ ー ト ケ ー キ ] | Original Japanese Text + C H O C O L A T E | New English Text + 20 43 48 4F 43 4F 4C 41 54 45 20 20 | New English Hex + $1B299 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + C A K E H A | New English Text + 20 20 20 20 43 41 4B 45 48 41 | New English Hex + きらいなもの + Things I Hate: + $1B2A3 (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + T E S : P U | New English Text + 54 45 53 3A 20 20 20 20 50 55 | New English Hex + カボチャのにつけ + Pumpkin Pie + $1B2AD (Line 5) + 5B B6 CE DE C1 AC 5D C9 C6 C2 B9 20 | Original Japanese Hex + [ カ ホ " チ ャ ] の に つ け | Original Japanese Text + M P K I N P I E B O R N | New English Text + 4D 50 4B 49 4E 50 49 45 42 4F 52 4E | New English Hex + $1B2B9 (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + I N : A P | New English Text + 20 49 4E 3A 20 20 20 41 20 50 | New English Hex + うまれ + Born In: + $1B2C3 (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + U M P K I N | New English Text + 55 4D 50 4B 49 4E 20 20 20 20 | New English Hex + カボチャばだけ + A Pumpkin Field + $1B2CD (Line 8) + 5B B6 CE DE C1 AC 5D CA DE C0 B9 20 00 00 00 | Original Japanese Hex + [ カ ホ " チ ャ ] ば " た け # # # | Original Japanese Text + F I E L D # # # | New English Text + 20 46 49 45 4C 44 20 20 20 20 20 20 00 00 00 | New English Hex + +MIRURUN: + ミルルン + Mirurun + $1B2D9 (Top Half) + 00 00 00 CF E0 E0 C4 00 00 00 | Original Japanese Hex + ミ ル ル ン | Original Japanese Text + M I R U R U N | New English Text + 00 CC C8 E1 E4 E1 E4 CD 00 00 | New English Hex + $1B2E3 (Bottom Half) + 00 00 00 DF F0 F0 D4 00 00 00 | Original Japanese Hex + ミ ル ル ン | Original Japanese Text + M I R U R U N | New English Text + 00 DC D8 F1 F4 F1 F4 DD 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B2ED (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + ともだち + Friends + $1B2F7 (Line 2) + C4 D3 C0 DE C1 20 20 20 20 20 | Original Japanese Hex + と も た " ち | Original Japanese Text + F R I E N D S | New English Text + 20 20 20 46 52 49 45 4E 44 53 | New English Hex + $1B301 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + H A T E S : | New English Text + 48 41 54 45 53 3A 20 20 20 20 | New English Hex + きらいなもの + Things I Hate: + $1B30B (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + H A L L O W E E N | New English Text + 20 48 41 4C 4C 4F 57 45 45 4E | New English Hex + ハロウィン + Halloween + $1B315 (Line 5) + 5B CA DB B3 A8 DD 5D 20 20 20 20 20 | Original Japanese Hex + [ ハ ロ ウ ィ ン ] | Original Japanese Text + B O | New English Text + 20 20 20 20 20 20 20 20 20 20 42 4F | New English Hex + $1B321 (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + R N I N : | New English Text + 52 4E 20 49 4E 3A 20 20 20 20 | New English Hex + うまれ + Born In: + $1B32B (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + B A N B O O | New English Text + 20 20 42 41 4E 42 4F 4F 20 20 | New English Hex + バンブーヤード + Bamboo Garden + $1B335 (Line 8) + 5B CA DE DD CC DE B0 D4 B0 C4 DE 5D 00 00 | Original Japanese Hex + [ ハ " ン フ " ー ヤ ー ト " ] # # | Original Japanese Text + G A R D E N S # # | New English Text + 20 47 41 52 44 45 4E 53 20 20 20 20 00 00 | New English Hex + +SHAMAN: + シャーマン + Shaman + $1B341 (Top Half) + 00 00 C5 C6 C7 C8 C4 00 00 00 | Original Japanese Hex + シ ャ ー マ ン | Original Japanese Text + S H A M A N | New English Text + 00 00 E2 C7 C0 CC C0 CD 00 00 | New English Hex + $1B34B (Bottom Half) + 00 00 D5 D6 D7 D8 D4 00 00 00 | Original Japanese Hex + シ ャ ー マ ン | Original Japanese Text + S H A M A N | New English Text + 00 00 F2 D7 D0 DC D0 DD 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B355 (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + おどり + Dancing + $1B35F (Line 2) + B5 C4 DE D8 20 20 20 20 20 20 | Original Japanese Hex + お と " り | Original Japanese Text + D A N C I N G | New English Text + 20 20 20 44 41 4E 43 49 4E 47 | New English Hex + $1B369 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + H A T E S : | New English Text + 48 41 54 45 53 3A 20 20 20 20 | New English Hex + きらいなもの + Things I Hate: + $1B373 (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + T H U N D E R | New English Text + 20 20 20 54 48 55 4E 44 45 52 | New English Hex + かみなり + Thunder/Lightning/Storms + $1B37D (Line 5) + B6 D0 C5 D8 20 20 20 20 20 20 | Original Japanese Hex + か み な り | Original Japanese Text + | New English Text + 20 20 20 20 20 20 20 20 20 20 | New English Hex + $1B387 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + B O R N I N : | New English Text + 42 4F 52 4E 20 49 4E 3A 20 20 | New English Hex + うまれ + Born In: + $1B391 (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + Y A N B O O | New English Text + 20 20 20 20 59 41 4E 42 4F 4F | New English Hex + ヤンブーフォレスト + Yanboo Forest + $1B39B (Line 8) + 5B D4 DD CC DE B0 CC AB DA BD C4 5D 00 00 | Original Japanese Hex + [ ヤ ン フ " ー フ ォ レ ス ト ] # # | Original Japanese Text + F O R E S T # # | New English Text + 20 20 20 20 46 4F 52 45 53 54 20 20 00 00 | New English Hex + +ALADDIN: + アラジン + Aladdin + $1B3A7 (Top Half) + 00 00 C9 CA C5 CB C4 00 00 00 | Original Japanese Hex + ア ラ シ " ン | Original Japanese Text + A L A D D I N | New English Text + 00 C0 CB C0 C3 C3 C8 CD 00 00 | New English Hex + $1B3B1 (Bottom Half) + 00 00 D9 DA D5 DB D4 00 00 00 | Original Japanese Hex + ア ラ シ " ン | Original Japanese Text + A L A D D I N | New English Text + 00 D0 DB D0 D3 D3 D8 DD 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B3BB (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + ユメ,ボウケン + Dreams, Adventure + $1B3C5 (Line 2) + 5B D5 D2 5D 2C 5B CE DE B3 B9 DD 5D 20 20 | Original Japanese Hex + [ ユ メ ] , [ ホ " ウ ケ ン ] | Original Japanese Text + D R E A M S , A D V | New English Text + 20 20 20 44 52 45 41 4D 53 2C 20 41 44 56 | New English Hex + $1B3D3 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + E N T U R E H A T E | New English Text + 45 4E 54 55 52 45 48 41 54 45 | New English Hex + きらいなもの + Things I Hate: + $1B3DD (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + S : R E A | New English Text + 53 3A 20 20 20 20 20 52 45 41 | New English Hex + こんじょう + Real Life/Temper/Nature + $1B3E7 (Line 5) + BA DD BC DE AE B3 20 20 20 20 | Original Japanese Hex + こ ん し " ょ う | Original Japanese Text + L L I F E | New English Text + 4C 20 4C 49 46 45 20 20 20 20 | New English Hex + $1B3F1 (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + B O R N | New English Text + 20 20 20 20 20 20 42 4F 52 4E | New English Hex + うまれ + Born In: + $1B3FB (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + I N : N | New English Text + 20 49 4E 3A 20 20 20 20 20 4E | New English Hex + ナカダット + Nakadat + $1B405 (Line 8) + 5B C5 B6 C0 DE AF C4 5D 20 20 20 20 00 00 | Original Japanese Hex + [ ナ カ タ " ッ ト ] # # | Original Japanese Text + A K A D A T # # | New English Text + 41 4B 41 44 41 54 20 20 20 20 20 20 00 00 | New English Hex + +PRINCESS: + プリンセス + Princess + $1B411 (Top Half) + 00 00 E1 E2 E3 C4 E4 E5 00 00 | Original Japanese Hex + フ o リ ン セ ス | Original Japanese Text + P R I N C E S S | New English Text + 00 CF E1 C8 CD C2 C4 E2 E2 00 | New English Hex + $1B41B (Bottom Half) + 00 00 F1 F2 F3 D4 F4 F5 00 00 | Original Japanese Hex + フ o リ ン セ ス | Original Japanese Text + P R I N C E S S | New English Text + 00 DF F1 D8 DD D2 D4 F2 F2 00 | New English Hex + + すきなもの + Favorite Things: + $1B425 (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + チーズケーキ,いぬ + Cheese Cake, Dogs + $1B42F (Line 2) + 5B C1 B0 BD DE B9 B0 B7 5D 2C B2 C7 | Original Japanese Hex + [ チ ー ス " ケ ー キ ] , い ぬ | Original Japanese Text + C H E E S E C A K E | New English Text + 43 48 45 45 53 45 43 41 4B 45 20 20 | New English Hex + $1B43B (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + D O G S H A | New English Text + 20 20 20 20 44 4F 47 53 48 41 | New English Hex + きらいなもの + Things I Hate: + $1B445 (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + T E S : E A | New English Text + 54 45 53 3A 20 20 20 20 45 41 | New English Hex + ミミズ,ナメクジ + Earthworms, Slugs + $1B44F (Line 5) + 5B D0 D0 BD DE 5D 2C 5B C5 D2 B8 BC DE 5D | Original Japanese Hex + [ ? ? ? ? ] , [ ? ? ? ? ? ] | Original Japanese Text + R T H W O R M S S | New English Text + 52 54 48 57 4F 52 4D 53 20 20 20 20 20 53 | New English Hex + $1B45D (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + L U G S B O R N I | New English Text + 4C 55 47 53 42 4F 52 4E 20 49 | New English Hex + うまれ + Born In: + $1B467 (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + N : L - | New English Text + 4E 3A 20 20 20 20 20 20 4C 2D | New English Hex + エルシップおうこく + L-Ship Kingdom + $1B471 (Line 8) + 5B B4 D9 BC AF CC DF 5D B5 B3 BA B8 00 00 00 | Original Japanese Hex + [ エ ル シ ッ フ o ] お う こ く # # # | Original Japanese Text + S H I P # # # | New English Text + 53 48 49 50 20 20 20 20 20 20 20 20 00 00 00 | New English Hex + +BIT: + ビット + Bit + $1B47D (Top Half) + 00 00 00 CC CB CD CE 00 00 00 | Original Japanese Hex + ヒ " ッ ト | Original Japanese Text + B I T | New English Text + 00 00 00 C1 C8 E3 00 00 00 00 | New English Hex + $1B487 (Bottom Half) + 00 00 00 DC DB DD DE 00 00 00 | Original Japanese Hex + ヒ " ッ ト | Original Japanese Text + B I T | New English Text + 00 00 00 D1 D8 F3 00 00 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B491 (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + ゆかいなこと + Funny/Amusing/Joyful Things/Entertaining + $1B49B (Line 2) + D5 B6 B2 C5 BA C4 20 20 20 20 | Original Japanese Hex + ゆ か い な こ と | Original Japanese Text + F U N , J O K E S | New English Text + 46 55 4E 2C 20 4A 4F 4B 45 53 | New English Hex + $1B4A5 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + H A T E S : | New English Text + 48 41 54 45 53 3A 20 20 20 20 | New English Hex + きらいなもの + Things I Hate: + $1B4AF (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + S I L E N C E | New English Text + 20 20 20 53 49 4C 45 4E 43 45 | New English Hex + ちんもく + Silence + $1B4B9 (Line 5) + C1 DD D3 B8 20 20 20 20 20 20 | Original Japanese Hex + ち ん も く | Original Japanese Text + | New English Text + 20 20 20 20 20 20 20 20 20 20 | New English Hex + $1B4C3 (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + B O R N I N : | New English Text + 42 4F 52 4E 20 49 4E 3A 20 20 | New English Hex + うまれ + Born In: + $1B4CD (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + S U N H O U S E | New English Text + 20 20 53 55 4E 48 4F 55 53 45 | New English Hex + サンハウスヒルズ + SunHouse Hills + $1B4D7 (Line 8) + 5B BB DD CA B3 BD CB D9 BD DE 5D 20 00 00 | Original Japanese Hex + [ サ ン ハ ウ ス ヒ ル ス " ] # # | Original Japanese Text + H I L L S # # | New English Text + 20 20 20 20 20 48 49 4C 4C 53 20 20 00 00 | New English Hex + +NINJA: + ニンジャ + Ninja + $1B4E3 (Top Half) + 00 00 E7 C4 C5 CB C6 00 00 00 | Original Japanese Hex + ニ ン シ " ャ | Original Japanese Text + N I N J A | New English Text + 00 00 CD C8 CD C9 C0 00 00 00 | New English Hex + $1B4ED (Bottom Half) + 00 00 F7 D4 D5 DB D6 00 00 00 | Original Japanese Hex + ニ ン シ " ャ | Original Japanese Text + N I N J A | New English Text + 00 00 DD D8 DD D9 D0 00 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B4F7 (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + チョコレート + Chocolate + $1B501 (Line 2) + 5B C1 AE BA DA B0 C4 5D 20 20 20 20 | Original Japanese Hex + [ チ ョ コ レ ー ト ] | Original Japanese Text + C H O C O L A T E | New English Text + 20 43 48 4F 43 4F 4C 41 54 45 20 20 | New English Hex + $1B50D (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + H A | New English Text + 20 20 20 20 20 20 20 20 48 41 | New English Hex + きらいなもの + Things I Hate: + $1B517 (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + T E S : C | New English Text + 54 45 53 3A 20 20 20 20 20 43 | New English Hex + ゴキブリ + Cockroach + $1B521 (Line 5) + 5B BA DE B7 CC DE D8 5D 20 20 20 20 | Original Japanese Hex + [ コ " キ フ " リ ] | Original Japanese Text + O C K R O A C H | New English Text + 4F 43 4B 52 4F 41 43 48 20 20 20 20 | New English Hex + $1B52D (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + B O R N | New English Text + 20 20 20 20 20 20 42 4F 52 4E | New English Hex + うまれ + Born In: + $1B537 (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + I N : | New English Text + 20 49 4E 3A 20 20 20 20 20 20 | New English Hex + げっこうえどむら + Gekko Edo-mura + $1B541 (Line 8) + B9 DE AF BA B3 B4 C4 DE D1 D7 00 | Original Japanese Hex + け " っ こ う え と " む ら # | Original Japanese Text + G E K K O # | New English Text + 20 47 45 4B 4B 4F 20 20 20 20 00 | New English Hex + +WOLFMAN: + オオカミオトコ + Wolfman + $1B54B (Top Half) + 00 EB EB EC CF EB CE ED 00 00 | Original Japanese Hex + オ オ カ ミ オ ト コ | Original Japanese Text + W O L F M A N | New English Text + 00 E6 CE CB C5 CC C0 CD 00 00 | New English Hex + $1B555 (Bottom Half) + 00 FB FB FC DF FB DE FD 00 00 | Original Japanese Hex + オ オ カ ミ オ ト コ | Original Japanese Text + W O L F M A N | New English Text + 00 F6 DE DB D5 DC D0 DD 00 00 | New English Hex + + すきなもの + Favorite Things: + $1B55F (Line 1) + BD B7 C5 D3 C9 20 20 20 20 20 | Original Japanese Hex + す き な も の | Original Japanese Text + L I K E S : | New English Text + 4C 49 4B 45 53 3A 20 20 20 20 | New English Hex + オニオンスープ + Onion Soup + $1B569 (Line 2) + 5B B5 C6 B5 DD BD B0 CC DF 5D 20 20 | Original Japanese Hex + [ オ ニ オ ン ス ー フ o ] | Original Japanese Text + O N I O N S O U P H A | New English Text + 4F 4E 49 4F 4E 20 53 4F 55 50 48 41 | New English Hex + $1B575 (Line 3) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + T E S : | New English Text + 54 45 53 3A 20 20 20 20 20 20 | New English Hex + きらいなもの + Things I Hate: + $1B57F (Line 4) + B7 D7 B2 C5 D3 C9 20 20 20 20 | Original Japanese Hex + き ら い な も の | Original Japanese Text + T O M A T O E S | New English Text + 54 4F 4D 41 54 4F 45 53 20 20 | New English Hex + トマト + Tomatoes + $1B589 (Line 5) + 5B C4 CF C4 5D 20 20 20 20 20 20 20 | Original Japanese Hex + [ ト マ ト ] | Original Japanese Text + B O R N | New English Text + 20 20 20 20 20 20 20 20 42 4F 52 4E | New English Hex + $1B595 (Line 6) + 20 20 20 20 20 20 20 20 20 20 | Original Japanese Hex + | Original Japanese Text + I N : D O W | New English Text + 20 49 4E 3A 20 20 20 44 4F 57 | New English Hex + うまれ + Born In: + $1B59F (Line 7) + B3 CF DA 20 20 20 20 20 20 20 | Original Japanese Hex + う ま れ | Original Japanese Text + N T O W N , | New English Text + 4E 54 4F 57 4E 2C 20 20 20 20 | New English Hex + + とうきょうしたまち + Tokyo, Downtown + $1B5A9 (Line 8) + C4 B3 B7 AE B3 BC C0 CF C1 20 | Original Japanese Hex + と う き ょ う し た ま ち | Original Japanese Text + T O K Y O | New English Text + 20 54 4F 4B 59 4F 20 20 20 20 | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/PAUSE.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/PAUSE.txt new file mode 100644 index 00000000..779f845a --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/PAUSE.txt @@ -0,0 +1,1924 @@ +PAUSE SCREEN NAMES: + ハロウィン + Halloween + $117F0 + 20 CA DB B3 A8 DD FF | Original Japanese Hex + ハ ロ ウ ィ ン # | Original Japanese Text + H A L L O W # | New English Text + 48 41 4C 4C 4F 57 FF | New English Hex + $117DC + F0 97 | Memory Address + + ミルルン + Mirurun + $117F7 + 20 20 D0 D9 D9 DD FF | Original Japanese Hex + ミ ル ル ン # | Original Japanese Text + M I R U R U # | New English Text + 4D 49 52 55 52 55 FF | New English Hex + $117DE + F7 97 | Memory Address + + シャーマン + Shaman + $117FE + 20 BC AC B0 CF DD FF | Original Japanese Hex + シ ャ ー マ ン # | Original Japanese Text + S H A M A N # | New English Text + 53 48 41 4D 41 4E FF | New English Hex + $117E0 + FE 97 | Memory Address + + アラジン + Aladdin + $11805 + 20 20 B1 D7 BC DE DD FF | Original Japanese Hex + ア ラ シ " ン # | Original Japanese Text + A L A D D I N # | New English Text + 41 4C 41 44 44 49 4E FF | New English Hex + $117E2 + 05 98 | Memory Address + + プリンセス + Princess + $1180D + 20 CC DF D8 DD BE BD FF | Original Japanese Hex + フ o リ ン セ ス # | Original Japanese Text + P R I N C E S # | New English Text + 50 52 49 4E 43 45 53 FF | New English Hex + $117E4 + 0D 98 | Memory Address + + ビット + Bit + $11815 + 20 20 20 CB DE AF C4 FF | Original Japanese Hex + ヒ " ッ ト # | Original Japanese Text + B I T # | New English Text + 42 49 54 20 20 20 20 FF | New English Hex + $117E6 + 15 98 | Memory Address + + ニンジャ + Ninja + $1181D + 20 20 C6 DD BC DE AC FF | Original Japanese Hex + ニ ン シ " ャ # | Original Japanese Text + N I N J A # | New English Text + 4E 49 4E 4A 41 20 20 FF | New English Hex + $117E8 + 1D 98 | Memory Address + + オオカミオトコ + Wolfman + $11825 + B5 B5 B6 D0 B5 C4 BA FF | Original Japanese Hex + オ オ カ ミ オ ト コ # | Original Japanese Text + W O L F M A N # | New English Text + 57 4F 4C 46 4D 41 4E FF | New English Hex + $117EA + 25 98 | Memory Address + + ドラゴン + Dragon + $1182D + 20 20 C4 DE D7 BA DE DD FF | Original Japanese Hex + ト " ラ コ " ン # | Original Japanese Text + D R A G O N # | New English Text + 44 52 41 47 4F 4E 20 20 FF | New English Hex + $117EC + 2D 98 | Memory Address + + グラプリ + Grand Princess (Queen) Empress + $11836 + 20 20 B8 DE D7 CC DF D8 FF | Original Japanese Hex + ? " ラ フ o リ # | Original Japanese Text + Q U E E N # | New English Text + 51 55 45 45 4E 20 20 20 FF | New English Hex + $117EE + 36 98 | Memory Address + +// PAUSE SCREEN MAGIC DESCRIPTION + MAGIC01: + ぼくのフィールドにあるブロックを + Lower the blocks in my field/wall + $11B01 (Line 1) + 24CEDE B8 C9 23CC A8 B0 D9 C4DE 24C6 B1 D9 23CCDE DB AF B8 24A6 25 | Original Japanese Hex + # ほ " く の # フ ィ ー ル ト " # に あ る # フ " ロ ッ ク # を NL | Original Japanese Text + 4ラインさげるんだ! + by 4 lines! + $11B1A (Line 2) + 2334 D7 B2 DD 24BB B9DE D9 DD C0DE 3A FF | Original Japanese Hex + # 4 ラ イ ン # さ け " る ん た " ! # | Original Japanese Text + $11A95 + 01 9B | Memory Address + + MAGIC02: + わたしのフィールドを、あいての + Make my field the same as + $11B29 (Line 1) + 24DC C0 BC C9 23CC A8 B0 D9 C4DE 24A6 A4 B1 B2 C3 C9 25 | Original Japanese Hex + # わ た し の # フ ィ ー ル ト " # を 、 あ い て の NL | Original Japanese Text + フィールドとおなじものにするのよ。 + the opponent 's field. + $11B3D (Line 2) + 23CC A8 B0 D9 C4DE 24C4 B5 C5 BCDE D3 C9 C6 BD D9 C9 D6 A1 FF | Original Japanese Hex + # フ ィ ー ル ト " # と お な し " も の に す る の よ 。 # | Original Japanese Text + $11A97 + 29 9B | Memory Address + + MAGIC03: + バテレンようじゅつイシガタメ! + Veteran Ishigatame! + $11B53 (Line 1) + 23CADE C3 DA DD 24D6 B3 BCDE AD C2 23B2 BC B6DE C0 D2 3A 2425 | Original Japanese Hex + # ハ " テ レ ン # よ う し " ゅ つ # イ シ カ " タ メ ! # NL | Original Japanese Text + これであいてのブロックはすベてイシに + This will turn all the opponent's blocks + $11B6A (Line 2) + BA DA C3DE B1 B2 C3 C9 23CCDE DB AF B8 24CA BD CDDE C3 23B2 BC 24C6 | Original Japanese Hex + こ れ て " あ い て の # フ " ロ ッ ク # は す へ " て # イ シ # に | Original Japanese Text + してやるゼ! + into stone! + $11B83 (Line 3) + BC C3 D4 D9 23BEDE 3A FF | Original Japanese Hex + し て や る # セ " ! # | Original Japanese Text + $11A99 + 53 9B | Memory Address + + MAGIC04: + ヒッサツのバクダンをなげこんで、あい + Lay down a bunch of bombs and + $11B8C (Line 1) + 23CB AF BB C2 24C9 23CADE B8 C0DE DD 24A6 C5 B9DE BA DD C3DE A4 B1 B2 | Original Japanese Hex + # ヒ ッ サ ツ # の # ハ " ク タ " ン # を な け " こ ん て " 、 あ い | Original Japanese Text + てのフィールドをあなだらけにするんだ + blow up the opponent's field + $11BA6 (Line 2) + C3 C9 23CC A8 B0 D9 C4DE 24A6 B1 C5 C0DE D7 B9 C6 BD D9 DD C0DE | Original Japanese Hex + て の # フ ィ ー ル ト " # を あ な た " ら け に す る ん た " | Original Japanese Text + キャハハハッ! + Cahahahaha! + $11BBD (Line 3) + 23B7 AC CA CA CA AF 3A FF | Original Japanese Hex + # キ ャ ハ ハ ハ ッ ! # | Original Japanese Text + $11A9B + 8C 9B | Memory Address + + MAGIC05: + Fakes the opponent's + にんぽうマヤカシのジュツであいての + $11BC6 (Line 1) + 24C6 DD CEDF B3 23CF D4 B6 BC 24C9 23BCDE AD C2 24C3DE B1 B2 C3 C9 25 | Original Japanese Hex + # に ん ほ o う # マ ヤ カ シ # の # シ " ュ ツ # て " あ い て の NL | Original Japanese Text + ネクストブロックをマヤカすゼ! + next blocks! + $11BE0 (Line 2) + 23C8 B8 BD C4 CCDE DB AF B8 24A6 23CF D4 B6 24BD 23BEDE 3A FF | Original Japanese Hex + # ネ ク ス ト フ " ロ ッ ク # を # マ ヤ カ # す # セ " ! # | Original Japanese Text + $11A9D + C6 9B | Memory Address + + MAGIC06: + あいてのフィールドを5ライン + I can add 5 lines to + $11BF7 (Line 1) + 24B1 B2 C3 C9 23CC A8 B0 D9 C4DE 24A6 2335 D7 B2 DD 2425 | Original Japanese Hex + # あ い て の # フ ィ ー ル ト " # を # 5 ラ イ ン # NL | Original Japanese Text + あげちゃうことができるんだ。 + the opponent's field. + $11C0C (Line 2) + B1 B9DE C1 AC B3 BA C4 B6DE C3DE B7 D9 DD C0DE A1 FF | Original Japanese Hex + あ け " ち ゃ う こ と か " て " き る ん た " 。 # | Original Japanese Text + $11A9F + F7 9B | Memory Address + + MAGIC07: + オレのにんぽうクモのイトはあいてが + My spider web will hold + $11C1F (Line 1) + 23B5 DA 24C9 C6 DD CEDF B3 23B8 D3 24C9 23B2 C4 24CA B1 B2 C3 B6DE 25 | Original Japanese Hex + # オ レ # の に ん ほ o う # ク モ # の # イ ト # は あ い て か " NL | Original Japanese Text + ラインをそろえてもブロックが + up your enemies blocks even + $11C39 (Line 2) + 23D7 B2 DD 24A6 BF DB B4 C3 D3 23CCDE DB AF B8 24B6DE 25 | Original Japanese Hex + # ラ イ ン # を そ ろ え て も # フ " ロ ッ ク # か " NL | Original Japanese Text + おとせなくなるゼ + after they have cleared lines below! + $11C4E (Line 3) + B5 C4 BE C5 B8 C5 D9 23BEDE 3A FF | Original Japanese Hex + お と せ な く な る # セ " ! # | Original Japanese Text + $11AA1 + 1F 9C | Memory Address + + MAGIC08: + オイラのフィールドのした3ラインの + I will cook/burn 3 lines + $11C5A (Line 1) + 23B5 B2 D7 24C9 23CC A8 B0 D9 C4DE 24C9 BC C0 2333 D7 B2 DD 24C9 25 | Original Japanese Hex + # オ イ ラ # の # フ ィ ー ル ト " # の し た # 3 ラ イ ン # の NL | Original Japanese Text + アナがうまるんだ! + on the field! + $11C73 (Line 2) + 23B1 C5 24B6DE B3 CF D9 DD C0DE 3A 25 | Original Japanese Hex + # ア ナ # か " う ま る ん た " ! NL | Original Japanese Text + ないときはむりやりうめるぞ! + Add some weight to see them go! + $11C81 (Line 3) + C5 B2 C4 B7 CA D1 D8 D4 D8 B3 D2 D9 BFDE 3A FF | Original Japanese Hex + な い と き は む り や り う め る そ " ! # | Original Japanese Text + $11AA3 + 5A 9C | Memory Address + + MAGIC09: + ドロドロガォー + Doro doro ga-o + $11C91 (Line 1) + 23C4DE DB C4DE DB B6DE AB B0 2425 | Original Japanese Hex + # ト " ロ ト " ロ カ " ォ ー # NL | Original Japanese Text + いみ、あいてにノロイをかけ + I will add blocks of stone + $11C9E (Line 2) + B2 D0 A4 B1 B2 C3 C6 23C9 DB B2 24A6 B6 B9 25 | Original Japanese Hex + い み 、 あ い て に # ノ ロ イ # を か け NL | Original Japanese Text + せきかブロックをおくります。 + as soon as possible. + $11CAE (Line 3) + BE B7 B6 23CCDE DB AF B8 24A6 B5 B8 D8 CF BD A1 FF | Original Japanese Hex + せ き か # フ " ロ ッ ク # を お く り ま す 。 # | Original Japanese Text + $11AA5 + 91 9C | Memory Address + + MAGIC10: + あいてのクリスタルパワーをオイラのも + Steal/Suck crystal power + $11CC0 (Line 1) + 24B1 B2 C3 C9 23B8 D8 BD C0 D9 CADF DC B0 24A6 23B5 B2 D7 24C9 D3 | Original Japanese Hex + # あ い て の # ク リ ス タ ル ハ o ワ ー # を # オ イ ラ # の も | Original Japanese Text + のにするんだ。 + from your enemy. + $11CD8 (Line 2) + C9 C6 BD D9 DD C0DE A1 FF | Original Japanese Hex + の に す る ん た " 。 # | Original Japanese Text + $11AA7 + C0 9C | Memory Address + + MAGIC11: + これでわたくしのフィールドのブロック + With this, all the blocks + $11CE1 (Line 1) + 24BA DA C3DE DC C0 B8 BC C9 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 | Original Japanese Hex + # こ れ て " わ た く し の # フ ィ ー ル ト " # の # フ " ロ ッ ク | Original Japanese Text + はすべてきえさるのよ! + of my field are gone! + $11CFA (Line 2) + 24CA BD CDDE C3 B7 B4 BB D9 C9 D6 3A 25 | Original Japanese Hex + # は す へ " て き え さ る の よ ! NL | Original Japanese Text + なぁーんてすばらしいんでしょう! + What a wonderful thing! + $11D08 (Line 3) + C5 A7 B0 DD C3 BD CADE D7 BC B2 DD C3DE BC AE B3 3A FF | Original Japanese Hex + な ぁ ー ん て す は " ら し い ん て " し ょ う ! # | Original Japanese Text + $11AA9 + E1 9C | Memory Address + + MAGIC12: + ボクのフィールドのした2ラインを + I'm going to give a present + $11D1B (Line 1) + 23CEDE B8 24C9 23CC A8 B0 D9 C4DE 24C9 BC C0 2332 D7 B2 DD 24A6 25 | Original Japanese Hex + # ホ " ク # の # フ ィ ー ル ト " # の し た # 2 ラ イ ン # を NL | Original Japanese Text + あいてにフoレゼントしてしまうのだ。 + of 2 lines from my field. + $11D34 (Line 2) + B1 B2 C3 C6 23CCDF DA BEDE DD C4 24BC C3 BC CF B3 C9 C0DE A1 FF | Original Japanese Hex + あ い て に # フ o レ セ " ン ト # し て し ま う の た " 。 # | Original Japanese Text + $11AAB + 1B 9D | Memory Address + $11AAD + 1B 9D | Memory Address + $11AAF + 1B 9D | Memory Address + + MAGIC13: + あっしのイアイぎりでじぶんの + I cut off 4 lines of blocks + $11D4B (Line 1) + 24B1 AF BC C9 23B2 B1 B2 24B7DE D8 C3DE BCDE CCDE DD C9 25 | Original Japanese Hex + # あ っ し の # イ ア イ # き " り て " し " ふ " ん の NL | Original Japanese Text + フィールドのブロックうえ4ラインを + at the end of my current + $11D61 (Line 2) + 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 24B3 B4 2334 D7 B2 DD 24A6 25 | Original Japanese Hex + # フ ィ ー ル ト " # の # フ " ロ ッ ク # う え # 4 ラ イ ン # を NL | Original Japanese Text + きるでござる。 + field. + $11D7B (Line 3) + B7 D9 C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + き る て " こ " さ " る 。 # | Original Japanese Text + $11AB1 + 4B 9D | Memory Address + + MAGIC14: + ンボビババフン + Nbobi baba fun + $11D86 (Line 1) + 23DD CEDE CBDE CADE CADE CC DD 25 | Original Japanese Hex + # ン ホ " ヒ " ハ " ハ " フ ン NL | Original Japanese Text + いみ、じぶんのフィールドのブロックを + This will split the blocks + $11D93 (Line 2) + 24B2 D0 A4 24BCDE CCDE DD C9 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 24A6 | Original Japanese Hex + # い み 、 # し " ふ " ん の # フ ィ ー ル ト " # の # フ " ロ ッ ク # を | Original Japanese Text + サユウによせます。 + down the middle of my field. + $11DAF (Line 3) + 23BB D5 B3 24C6 D6 BE CF BD A1 FF | Original Japanese Hex + # サ ユ ウ # に よ せ ま す 。 # | Original Japanese Text + $11AB3 + 86 9D | Memory Address + + MAGIC15: + あいてフィールドのブロックたちが + With this, the blocks in the field + $11DBB (Line 1) + 24B1 B2 C3 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 24C0 C1 B6DE 25 | Original Japanese Hex + # あ い て # フ ィ ー ル ト " # の # フ " ロ ッ ク # た ち か " NL | Original Japanese Text + おどってメチャクチャになるんだー + dance and become messy + $11DD4 (Line 2) + B5 C4DE AF C3 23D2 C1 AC B8 C1 AC 24C6 C5 D9 DD C0DE B0 FF | Original Japanese Hex + お と " っ て # メ チ ャ ク チ ャ # に な る ん た " ー # | Original Japanese Text + $11AB5 + BB 9D | Memory Address + + MAGIC16: + おほしさまがふってきてブロックを + Shooting stars rain down + $11DE9 (Line 1) + 24B5 CE BC BB CF B6DE CC AF C3 B7 C3 23CCDE DB AF B8 24A6 25 | Original Japanese Hex + # お ほ し さ ま か " ふ っ て き て # フ " ロ ッ ク # を NL | Original Japanese Text + さげてくれるんだー + lowering the blocks. + $11DFF (Line 2) + BB B9DE C3 B8 DA D9 DD C0DE B0 FF | Original Japanese Hex + さ け " て く れ る ん た " ー # | Original Japanese Text + $11AB7 + E9 9D | Memory Address + + MAGIC17: + これであいてのサユウいどうサユウかい + This will reverse the controls + $11E0B (Line 1) + 24BA DA C3DE B1 B2 C3 C9 23BB D5 B3 24B2 C4DE B3 23BB D5 B3 24B6 B2 | Original Japanese Hex + # こ れ て " あ い て の # サ ユ ウ # い と " う # サ ユ ウ # か い | Original Japanese Text + てんがさかさになるのよ! + of your opponent! + $11E24 (Line 2) + C3 DD B6DE BB B6 BB C6 C5 D9 C9 D6 3A 25 | Original Japanese Hex + て ん か " さ か さ に な る の よ ! NL | Original Japanese Text + ホーホッホッ! + Ho Ho! + $11E32 (Line 3) + 23CE B0 CE AF CE AF 3A FF | Original Japanese Hex + # ホ ー ホ ッ ホ ッ ! # | Original Japanese Text + $11AB9 + 0B 9E | Memory Address + + MAGIC18: + わたしのまほうであいてのらっか + With my wish I will hold the blocks + $11E3B (Line 1) + 24DC C0 BC C9 CF CE B3 C3DE B1 B2 C3 C9 D7 AF B6 25 | Original Japanese Hex + # わ た し の ま ほ う て " あ い て の ら っ か NL | Original Japanese Text + ブロックのかいてんをとめてしまうのよ + on the field of the opponent. + $11E4D (Line 2) + 23CCDE DB AF B8 24C9 B6 B2 C3 DD A6 C4 D2 C3 BC CF B3 C9 D6 FF | Original Japanese Hex + # フ " ロ ッ ク # の か い て ん を と め て し ま う の よ # | Original Japanese Text + $11ABB + 3B 9E | Memory Address + + MAGIC19: + ビビロンツイツイ + Bi-bi Ron tsui-tsui + $11E63 (Line 1) + 23CBDE CBDE DB DD C2 B2 C2 B2 25 | Original Japanese Hex + # ヒ " ヒ " ロ ン ツ イ ツ イ NL | Original Japanese Text + いみ、あいてのカイテンがおもう + This will speed up the block rotation + $11E6F (Line 2) + 24B2 D0 A4 24B1 B2 C3 C9 23B6 B2 C3 DD 24B6DE B5 D3 B3 25 | Original Japanese Hex + # い み 、 # あ い て の # カ イ テ ン # か " お も う NL | Original Japanese Text + ようにできなくなります。 + of my opponent. + $11E84 (Line 3) + D6 B3 C6 C3DE B7 C5 B8 C5 D8 CF BD A1 FF | Original Japanese Hex + よ う に て " き な く な り ま す 。 # | Original Japanese Text + $11ABD + 63 9E | Memory Address + + MAGIC20: + オレのにんほoうツムジカゼでフィールド + This will push all my blocks to one side + $11E92 (Line 1) + 23B5 DA 24C9 C6 DD CEDF B3 23C2 D1 BCDE B6 BEDE 24C3DE 23CC A8 B0 D9 C4DE | Original Japanese Hex + # オ レ # の に ん ほ o う # ツ ム シ " カ セ " # て " # フ ィ ー ル ト " | Original Japanese Text + のブロックをハジによせるゼ! + with the wind! + $11EAE (Line 2) + 24C9 23CCDE DB AF B8 24A6 23CA BCDE 24C6 D6 BE D9 23BEDE 3A FF | Original Japanese Hex + # の # フ " ロ ッ ク # を # ハ シ " # に よ せ る # セ " ! # | Original Japanese Text + $11ABF + 92 9E | Memory Address + + MAGIC21: + ギャングさんたちがあいてフィールドの + A gang will come and steal the crystals + $11EC6 (Line 1) + 23B7DE AC DD B8DE 24BB DD C0 C1 B6DE B1 B2 C3 23CC A8 B0 D9 C4DE 24C9 | Original Japanese Hex + # キ " ャ ン ク " # さ ん た ち か " あ い て # フ ィ ー ル ト " # の | Original Japanese Text + クリスタルをとってきてくれるんだー + from the opponent's field. + $11EE0 (Line 2) + 23B8 D8 BD C0 D9 24A6 C4 AF C3 B7 C3 B8 DA D9 DD C0DE B0 FF | Original Japanese Hex + # ク リ ス タ ル # を と っ て き て く れ る ん た " ー # | Original Japanese Text + $11AC1 + C6 9E | Memory Address + + MAGIC22: + あっしのカタナでブロックをきりつけ + I cut off the block with a katana + $11EF5 (Line 1) + 24B1 AF BC C9 23B6 C0 C5 24C3DE 23CCDE DB AF B8 24A6 B7 D8 C2 B9 25 | Original Japanese Hex + # あ っ し の # カ タ ナ # て " # フ " ロ ッ ク # を き り つ け NL | Original Japanese Text + ブロックをトクシュレンサじょうたいに + of the day and I will make the + $11F0E (Line 2) + 23CCDE DB AF B8 24A6 23C4 B8 BC AD DA DD BB 24BCDE AE B3 C0 B2 C6 | Original Japanese Hex + # フ " ロ ッ ク # を # ト ク シ ュ レ ン サ # し " ょ う た い に | Original Japanese Text + するでござる。 + blocks into rensa mode. + $11F26 (Line 3) + BD D9 C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + す る て " こ " さ " る 。 # | Original Japanese Text + $11AC3 + F5 9E | Memory Address + + MAGIC23: + オレさまのキョウリョクなチカラで + I will crush the field blocks + $11F31 (Line 1) + 23B5 DA 24BB CF C9 23B7 AE B3 D8 AE B8 24C5 23C1 B6 D7 24C3DE 25 | Original Japanese Hex + # オ レ # さ ま の # キ ョ ウ リ ョ ク # な # チ カ ラ # て " NL | Original Japanese Text + フィールドのブロックをつぶすのだ! + with my mighty power! + $11F49 (Line 2) + 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 24A6 C2 CCDE BD C9 C0DE 3A FF | Original Japanese Hex + # フ ィ ー ル ト " # の # フ " ロ ッ ク # を つ ふ " す の た " ! # | Original Japanese Text + $11AC5 + 31 9F | Memory Address + + MAGIC24: + わたしのまほうでフィールドのたて + I will destroy 3 columns of my field + $11F63 (Line 1) + 24DC C0 BC C9 CF CE B3 C3DE 23CC A8 B0 D9 C4DE 24C9 C0 C3 25 | Original Japanese Hex + # わ た し の ま ほ う て " # フ ィ ー ル ト " # の た て NL | Original Japanese Text + 3ラインをけしてしまうの。 + with my magic. + $11F79 (Line 2) + 2333 D7 B2 DD 24A6 B9 BC C3 BC CF B3 C9 A1 25 | Original Japanese Hex + # 3 ラ イ ン # を け し て し ま う の 。 NL | Original Japanese Text + すきなところをけせるのよ! + Put it on your favorite place! + $11F89 (Line 3) + BD B7 C5 C4 BA DB A6 B9 BE D9 C9 D6 3A FF | Original Japanese Hex + す き な と こ ろ を け せ る の よ ! # | Original Japanese Text + $11AC7 + 63 9F | Memory Address + + MAGIC25: + あいてのフィールドのブロックの + I will replace the place where there is a block + $11F97 (Line 1) + 24B1 B2 C3 C9 23CC A8 B0 D9 C4DE 24C9 23CCDE DB AF B8 24C9 25 | Original Japanese Hex + # あ い て の # フ ィ ー ル ト " # の # フ " ロ ッ ク # の NL | Original Japanese Text + あるところとないところをいれかえちゃ + of the field with the place where there is + $11FAE (Line 2) + B1 D9 C4 BA DB C4 C5 B2 C4 BA DB A6 B2 DA B6 B4 C1 AC | Original Japanese Hex + あ る と こ ろ と な い と こ ろ を い れ か え ち ゃ | Original Japanese Text + うんだ。 + no block. + $11FC0 (Line 3) + B3 DD C0DE A1 FF | Original Japanese Hex + う ん た " 。 # | Original Japanese Text + $11AC9 + 97 9F | Memory Address + + MAGIC26: + あいてのフィールドをボクのフィールド + It makes the field of the opponent + $11FC6 (Line 1) + 24B1 B2 C3 C9 23CC A8 B0 D9 C4DE 24A6 23CEDE B8 24C9 23CC A8 B0 D9 C4DE | Original Japanese Hex + # あ い て の # フ ィ ー ル ト " # を # ホ " ク # の # フ ィ ー ル ト " | Original Japanese Text + とおなじにしてしまうのだ。 + the same as my field. + $11FE1 (Line 2) + 24C4 B5 C5 BCDE C6 BC C3 BC CF B3 C9 C0DE A1 FF | Original Japanese Hex + # と お な し " に し て し ま う の た " 。 # | Original Japanese Text + $11ACB + C6 9F | Memory Address + + MAGIC27: + これさえあればあいてがラインを + Even if the other party erases a line, + $11FF2 (Line 1) + 24BA DA BB B4 B1 DA CADE B1 B2 C3 B6DE 23D7 B2 DD 24A6 25 | Original Japanese Hex + # こ れ さ え あ れ は " あ い て か " # ラ イ ン # を NL | Original Japanese Text + けしてもしばらくはふせげるのだ。 + it can be prevented for a while if using this. + $12007 (Line 2) + B9 BC C3 D3 BC CADE D7 B8 CA CC BE B9DE D9 C9 C0DE A1 FF | Original Japanese Hex + け し て も し は " ら く は ふ せ け " る の た " 。 # | Original Japanese Text + $11ACD + F2 9F | Memory Address + + MAGIC28: + まほうのかがみであいてのかけたワザの + Make sure to put a lot of trouble overworking + $1201B (Line 1) + 24CF CE B3 C9 B6 B6DE D0 C3DE B1 B2 C3 C9 B6 B9 C0 23DC BBDE 24C9 | Original Japanese Hex + # ま ほ う の か か " み て " あ い て の か け た # ワ サ " # の | Original Japanese Text + たいしょうをさかさにするのよ。 + with magical reflection. + $12033 (Line 2) + C0 B2 BC AE B3 A6 BB B6 BB C6 BD D9 C9 D6 A1 FF | Original Japanese Hex + た い し ょ う を さ か さ に す る の よ 。 # | Original Japanese Text + $11ACF + 1B A0 | Memory Address + + MAGIC29: + じぶんのらっかするブロックがおいた + I will be confident about the time + $12043 (Line 1) + 24BCDE CCDE DD C9 D7 AF B6 BD D9 23CCDE DB AF B8 24B6DE B5 B2 C0 25 | Original Japanese Hex + # し " ふ " ん の ら っ か す る # フ " ロ ッ ク # か " お い た NL | Original Japanese Text + しゅんかんにじしんをおこす。 + it takes a secret block to fall. + $1205C (Line 2) + BC AD DD B6 DD C6 BCDE BC DD A6 B5 BA BD A1 FF | Original Japanese Hex + し ゅ ん か ん に し " し ん を お こ す 。 # | Original Japanese Text + $11AD1 + 43 A0 | Memory Address + + MAGIC30: + オレさまのマリョクでじぶんの + Using L,R buttons + $1206C (Line 1) + 23B5 DA 24BB CF C9 23CF D8 AE B8 24C3DE BCDE CCDE DD C9 25 | Original Japanese Hex + # オ レ # さ ま の # マ リ ョ ク # て " し " ふ " ん の NL | Original Japanese Text + らっかブロックをすきなものにかえて + I can change the next 4 blocks + $12082 (Line 2) + D7 AF B6 23CCDE DB AF B8 24A6 BD B7 C5 D3 C9 C6 B6 B4 C3 25 | Original Japanese Hex + ら っ か # フ " ロ ッ ク # を す き な も の に か え て NL | Original Japanese Text + しまうのだ! + into my favorite one! + $12097 (Line 3) + BC CF B3 C9 C0DE 3A FF | Original Japanese Hex + し ま う の た " ! # | Original Japanese Text + $11AD3 + 6C A0 | Memory Address + + MAGIC31: + あっしのキョウダイブンであるヌーが + A giant will + $1209F (Line 1) + 24B1 AF BC C9 23B7 AE B3 C0DE B2 CCDE DD 24C3DE B1 D9 23C7 B0 24B6DE 25 | Original Japanese Hex + # あ っ し の # キ ョ ウ タ " イ フ " ン # て " あ る # ヌ ー # か " NL | Original Japanese Text + あいてのらっかブロックのドロップを + stop the opponent + $120BA (Line 2) + 24B1 B2 C3 C9 D7 AF B6 23CCDE DB AF B8 24C9 23C4DE DB AF CCDF 24A6 25 | Original Japanese Hex + # あ い て の ら っ か # フ " ロ ッ ク # の # ト " ロ ッ フ o # を NL | Original Japanese Text + うけとめるでござる。 + from dropping blocks. + $120D4 (Line 3) + B3 B9 C4 D2 D9 C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + う け と め る て " こ " さ " る 。 # | Original Japanese Text + $11AD5 + 9F A0 | Memory Address + + MAGIC32: + あいてのらっかブロックをボクがそうさ + I will control the next 2 blocks + $120E2 (Line 1) + 24B1 B2 C3 C9 D7 AF B6 23CCDE DB AF B8 24A6 23CEDE B8 24B6DE BF B3 BB | Original Japanese Hex + # あ い て の ら っ か # フ " ロ ッ ク # を # ホ " ク # か " そ う さ | Original Japanese Text + できるのだ。 + of my opponent. + $120FC (Line 2) + C3DE B7 D9 C9 C0DE A1 FF | Original Japanese Hex + て " き る の た " 。 # | Original Japanese Text + $11AD7 + E2 A0 | Memory Address + + MAGIC33: + あいてのコントローラをさかさまに + I will turn the opponent's controller + $12105 (Line 1) + 24B1 B2 C3 C9 23BA DD C4 DB B0 D7 24A6 BB B6 BB CF C6 25 | Original Japanese Hex + # あ い て の # コ ン ト ロ ー ラ # を さ か さ ま に NL | Original Japanese Text + しちゃうんだ。つまり、ボタンでほうこ + upside down. In other words, it is inverted + $12119 (Line 2) + BC C1 AC B3 DD C0DE A1 C2 CF D8 A4 23CEDE C0 DD 24C3DE CE B3 BA | Original Japanese Hex + し ち ゃ う ん た " 。 つ ま り 、 # ホ " タ ン # て " ほ う こ | Original Japanese Text + う、ジュウジキーでカイテンだよ。 + for the next 3 blocks. + $12130 (Line 3) + B3 A4 23BCDE AD B3 BCDE B7 B0 24C3DE 23B6 B2 C3 DD 24C0DE D6 A1 FF | Original Japanese Hex + う 、 # シ " ュ ウ シ " キ ー # て " # カ イ テ ン # た " よ 。 # | Original Japanese Text + $11AD9 + 05 A1 | Memory Address + + MAGIC34: + あいてがラインをそろえてさがると + As a result, lines that are cleared + $12149 (Line 1) + 24B1 B2 C3 B6DE 23D7 B2 DD 24A6 BF DB B4 C3 BB B6DE D9 C4 25 | Original Japanese Hex + # あ い て か " # ラ イ ン # を そ ろ え て さ か " る と NL | Original Japanese Text + あっしのフィールドもさがるでござる + by my opponent will make my field go down. + $1215F (Line 2) + B1 AF BC C9 23CC A8 B0 D9 C4DE 24D3 BB B6DE D9 C3DE BADE BBDE D9 FF | Original Japanese Hex + あ っ し の # フ ィ ー ル ト " # も さ か " る て " こ " さ " る # | Original Japanese Text + $11ADB + 49 A1 | Memory Address + + MAGIC35: + ンババメラメラ + Namba Bamera + $12178 (Line 1) + 23DD CADE CADE D2 D7 D2 D7 25 | Original Japanese Hex + # ン ハ " ハ " メ ラ メ ラ NL | Original Japanese Text + いみ、4レベルのワザがランダムにかか + Meanwhile, it takes 4 levels of random + $12183 (Line 2) + 24B2 D0 A4 34 23DA CDDE D9 24C9 23DC BBDE 24B6DE 23D7 DD C0DE D1 24C6 B6 B6 | Original Japanese Hex + # い み 、 4 # レ ヘ " ル # の # ワ サ " # か " # ラ ン タ " ム # に か か | Original Japanese Text + ります。たまに、しっぱいも・・・ + play. Occasionally, I also have to do something... + $121A0 (Line 3) + D8 CF BD A1 C0 CF C6 A4 BC AF CADF B2 D3 A5 A5 A5 FF | Original Japanese Hex + り ま す 。 た ま に 、 し っ は o い も ・ ・ ・ # | Original Japanese Text + $11ADD + 78 A1 | Memory Address + + MAGIC36: + オレさまのマリョクであいての + Make my opponent's + $121B2 (Line 1) + 23B5 DA 24BB CF C9 23CF D8 AE B8 24C3DE B1 B2 C3 C9 25 | Original Japanese Hex + # オ レ # さ ま の # マ リ ョ ク # て " あ い て の NL | Original Japanese Text + コントローラーのそうさをメチャクチャ + controller buttons + $121C6 (Line 2) + 23BA DD C4 DB B0 D7 B0 24C9 BF B3 BB A6 23D2 C1 AC B8 C1 AC | Original Japanese Hex + # コ ン ト ロ ー ラ ー # の そ う さ を # メ チ ャ ク チ ャ | Original Japanese Text + にするのだ! + become randomly scrambled! + $121DB (Line 3) + 24C6 BD D9 C9 C0DE 3A FF | Original Japanese Hex + # に す る の た " ! # | Original Japanese Text + $11ADF + B2 A1 | Memory Address + + MAGIC37: + おんなじブロックが10コれんぞくして + Repeats the same block 10 times + $121E4 (Line 1) + 24B5 DD C5 BCDE 23CCDE DB AF B8 24B6DE 2331 30 BA 24DA DD BFDE B8 BC C3 | Original Japanese Hex + # お ん な し " # フ " ロ ッ ク # か " # 1 0 コ # れ ん そ " く し て | Original Japanese Text + おちてくるんだー + between both players. + $121FF (Line 2) + B5 C1 C3 B8 D9 DD C0DE B0 FF | Original Japanese Hex + お ち て く る ん た " ー # | Original Japanese Text + $11AE1 + E4 A1 | Memory Address + + MAGIC38: + オレさまのフィールドとあいての + This will swap my field + $12209 (Line 1) + 23B5 DA 24BB CF C9 23CC A8 B0 D9 C4DE 24C4 B1 B2 C3 C9 25 | Original Japanese Hex + # オ レ # さ ま の # フ ィ ー ル ト " # と あ い て の NL | Original Japanese Text + フィールドをいれかえてしまうのだ! + with my opponent! + $1221E (Line 2) + 23CC A8 B0 D9 C4DE 24A6 B2 DA B6 B4 C3 BC CF B3 C9 C0DE 3A 25 | Original Japanese Hex + # フ ィ ー ル ト " # を い れ か え て し ま う の た " ! NL | Original Japanese Text + がっはっは! + Gwah ha ha! + $12234 (Line 3) + B6DE AF CA AF CA 3A FF | Original Japanese Hex + か " っ は っ は ! # | Original Japanese Text + $11AE3 + 09 A2 | Memory Address + + MAGIC39: + わたくしのけしたラインすうが2バイに + The number of my erased lines doubles + $1223C (Line 1) + 24DC C0 B8 BC C9 B9 BC C0 23D7 B2 DD 24BD B3 B6DE 2332 CADE B2 24C6 | Original Japanese Hex + # わ た く し の け し た # ラ イ ン # す う か " # 2 ハ " イ # に | Original Japanese Text + なってあいてにおくられるのよ! + and is sent to my opponent! + $12255 (Line 2) + C5 AF C3 B1 B2 C3 C6 B5 B8 D7 DA D9 C9 D6 3A 25 | Original Japanese Hex + な っ て あ い て に お く ら れ る の よ ! NL | Original Japanese Text + ホーホッホッホ! + Ho ho ho! + $12265 (Line 3) + 23CE B0 CE AF CE AF CE 3A FF | Original Japanese Hex + # ホ ー ホ ッ ホ ッ ホ ! # | Original Japanese Text + $11AE5 + 3C A2 | Memory Address + + MAGIC40: + あいてのフィールドがまっくらになる。 + The opponent's field goes dark for 3 blocks. + $1226F (Line 1) + 24B1 B2 C3 C9 23CC A8 B0 D9 C4DE 24B6DE CF AF B8 D7 C6 C5 D9 A1 | Original Japanese Hex + # あ い て の # フ ィ ー ル ト " # か " ま っ く ら に な る 。 | Original Japanese Text + でもブロックからのライトでみえちゃう + But they can see with a light + $12286 (Line 2) + C3DE D3 23CCDE DB AF B8 24B6 D7 C9 23D7 B2 C4 24C3DE D0 B4 C1 AC B3 | Original Japanese Hex + て " も # フ " ロ ッ ク # か ら の # ラ イ ト # て " み え ち ゃ う | Original Japanese Text + んだなこれが。 + from the block. + $1229F (Line 3) + DD C0DE C5 BA DA B6DE A1 FF | Original Japanese Hex + ん た " な こ れ か " 。 # | Original Japanese Text + $11AE7 + 6F A2 | Memory Address + + MAGIC41: + わたくしのはハイパーだからクリスタル + With my hyper crystal, + $122A9 (Line 1) + 24DC C0 B8 BC C9 CA 23CA B2 CADF B0 24C0DE B6 D7 23B8 D8 BD C0 D9 | Original Japanese Hex + # わ た く し の は # ハ イ ハ o ー # た " か ら # ク リ ス タ ル | Original Japanese Text + ブロックいがいのした4ラインを + I will burn 4 lines + $122C1 (Line 2) + CCDE DB AF B8 24B2 B6DE B2 C9 BC C0 2334 D7 B2 DD 24A6 25 | Original Japanese Hex + フ " ロ ッ ク # い か " い の し た # 4 ラ イ ン # を NL | Original Japanese Text + ブロックにかえますのよ! + of blocks! + $122D6 (Line 3) + 23CCDE DB AF B8 24C6 B6 B4 CF BD C9 D6 3A FF | Original Japanese Hex + # フ " ロ ッ ク # に か え ま す の よ ! # | Original Japanese Text + $11AE9 + A9 A2 | Memory Address + +PAUSE SCREEN PLAYER: + ALL: + 「ワザのつかいかた」 + "How to use the service" + $12A9B (Line 1) + A2 23DC BBDE 24C9 C2 B6 B2 B6 C0 A3 20 20 20 20 20 20 20 FF | Original Japanese Hex + 「 # ワ サ " # の つ か い か た 」 # | Original Japanese Text + - H O W T O U S E - # | New English Text + B0 484F 5720 544F 20 55 53 45 B0 20 20 20 20 20 20 20 20 FF | New English Hex + + HALLOWEEN: + クリスタルをけすとワザがつかえるのだ + You can use it if you hit a crystal/You need crystals to use magic + $1231D (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C4 23DC BBDE 24B6DE C2 B6 B4 D9 C9 C0DE | Original Japanese Hex + # ク リ ス タ ル # を け す と # ワ サ " # か " つ か え る の た " | Original Japanese Text + ジュウジボタンのウエをおしてあいてを + Press UP on the D-Pad + $12336 (Line 2) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24A6 B5 BC C3 B1 B2 C3 A6 | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # を お し て あ い て を | Original Japanese Text + こまらせるんだな。 + to use it. + $1234F (Line 3) + BA CF D7 BE D9 DD C0DE C5 A1 FF | Original Japanese Hex + こ ま ら せ る ん た " な 。 # | Original Japanese Text + $11AED + 1D A3 | Memory Address + + MIRURUN: + クリスタルをけすとワザがつかえるよ。 + You can use a crystal when you hit a crystal. + $1235A (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C4 23DC BBDE 24B6DE C2 B6 B4 D9 D6 A1 | Original Japanese Hex + # ク リ ス タ ル # を け す と # ワ サ " # か " つ か え る よ 。 | Original Japanese Text + つかいかたはジュウジボタンのウエをお + Press UP on the D-Pad + $12372 (Line 2) + C2 B6 B2 B6 C0 CA 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24A6 B5 | Original Japanese Hex + つ か い か た は # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # を お | Original Japanese Text + すんだ。 + to use it. + $1238B (Line 3) + BD DD C0DE A1 FF | Original Japanese Hex + す ん た " 。 # | Original Japanese Text + $11AEF + 5A A3 | Memory Address + + SHAMAN: + んんーばばばばばん! + Nn-babababan! / Good Morning! + $12391 (Line 1) + 24DD DD B0 CADE CADE CADE CADE CADE DD 3A 25 | Original Japanese Hex + # ん ん ー は " は " は " は " は " ん ! NL | Original Japanese Text + いみ、クリスタルをけすとワザがつかえ + I do not mind if I miss the crystal. + $123A2 (Line 2) + 24B2 D0 A4 23B8 D8 BD C0 D9 24A6 B9 BD C4 23DC BBDE 24B6DE C2 B6 B4 | Original Japanese Hex + # い み 、 # ク リ ス タ ル # を け す と # ワ サ " # か " つ か え | Original Japanese Text + ます。ジュウジボタンのウエをおします + Press UP on the D-Pad to use it. + $123BB (Line 3) + CF BD A1 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24A6 B5 BC CF BD FF | Original Japanese Hex + ま す 。 # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # を お し ま す # | Original Japanese Text + $11AF1 + 91 A3 | Memory Address + + ALADDIN: + クリスタルをけすとボクのすばらしい + You can use my wonderful spells by turning off + $123D5 (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C4 23CEDE B8 24C9 BD CADE D7 BC B2 25 | Original Japanese Hex + # ク リ ス タ ル # を け す と # ホ " ク # の す は " ら し い NL | Original Japanese Text + ジュモンがつかえるぞ。 + the crystals. + $123ED (Line 2) + 23BCDE AD D3 DD 24B6DE C2 B6 B4 D9 BFDE A1 25 | Original Japanese Hex + # シ " ュ モ ン # か " つ か え る そ " 。 NL | Original Japanese Text + つかいかたはジュウジボタンのウエだぞ + Press UP on the D-Pad to use it. + $123FE (Line 3) + C2 B6 B2 B6 C0 CA 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24C0DE BFDE FF | Original Japanese Hex + つ か い か た は # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # た " そ " # | Original Japanese Text + $11AF3 + D5 A3 | Memory Address + + PRINCESS: + クリスタルをけすとマホウがつかえるの + I can use a magic with crushing a crystal. + $1241A (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C4 23CF CE B3 24B6DE C2 B6 B4 D9 C9 | Original Japanese Hex + # ク リ ス タ ル # を け す と # マ ホ ウ # か " つ か え る の | Original Japanese Text + マホウはジュウジボタンのウエよ。 + Press UP on the D-Pad to use it. + $12431 (Line 2) + 23CF CE B3 24CA 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24D6 A1 FF | Original Japanese Hex + # マ ホ ウ # は # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # よ 。 # | Original Japanese Text + $11AF5 + 1A A4 | Memory Address + + BIT: + クリスタルをけすとたのしいことがおこ + If you break the crystal, something fun + $1244B (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C4 C0 C9 BC B2 BA C4 B6DE B5 BA | Original Japanese Hex + # ク リ ス タ ル # を け す と た の し い こ と か " お こ | Original Japanese Text + るんだよ! + will happen! + $12460 (Line 2) + D9 DD C0DE D6 3A 25 | Original Japanese Hex + る ん た " よ ! NL | Original Japanese Text + ジュウジボタンのウエをおすんだー! + We are waiting for the D-Pad Up button! + $12467 (Line 3) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24A6 B5 BD DD C0DE B0 3A FF | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # を お す ん た " ー ! # | Original Japanese Text + $11AF7 + 4B A4 | Memory Address + + NINJA: + クリスタルをけしてニンポウをつかえ! + Please remove the crystal and use Ninjutsu power! + $12481 (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BC C3 23C6 DD CEDF B3 24A6 C2 B6 B4 3A | Original Japanese Hex + # ク リ ス タ ル # を け し て # ニ ン ホ o ウ # を つ か え ! | Original Japanese Text + ジュウジボタンのウエでオレのニンポウ + Press UP on the D-Pad + $12498 (Line 2) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24C3DE 23B5 DA 24C9 23C6 DD CEDF B3 | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # て " # オ レ # の # ニ ン ホ o ウ | Original Japanese Text + がサクレツするぜ! + to use it! + $124B6 (Line 3) + 24B6DE 23BB B8 DA C2 24BD D9 BEDE 3A FF | Original Japanese Hex + # か " # サ ク レ ツ # す る せ " ! # | Original Japanese Text + $11AF9 + 81 A4 | Memory Address + + WOLFMAN: + くりすたるをけしてキアイをためよ! + Stop crushing and give up Kia! + $124C5 (Line 1) + 24B8 D8 BD C0 D9 A6 B9 BC C3 23B7 B1 B2 24A6 C0 D2 D6 3A 25 | Original Japanese Hex + # く り す た る を け し て # キ ア イ # を た め よ ! NL | Original Japanese Text + ジュウジボタンのうえでせっしゃのケン + Push the UP button + $124DA (Line 2) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 B3 B4 C3DE BE AF BC AC C9 23B9 DD | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の う え て " せ っ し ゃ の # ケ ン | Original Japanese Text + がうなるでござる! + to use it! + $124F3 (Line 3) + 24B6DE B3 C5 D9 C3DE BADE BBDE D9 3A FF | Original Japanese Hex + # か " う な る て " こ " さ " る ! # | Original Japanese Text + $11AFB + C5 A4 | Memory Address + + DRAGON: + クリスタルをけしてパワーをためるのだ + Get crystals and save them for power + $12502 (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BC C3 23CADF DC B0 24A6 C0 D2 D9 C9 C0DE | Original Japanese Hex + # ク リ ス タ ル # を け し て # ハ o ワ ー # を た め る の た " | Original Japanese Text + ジュウジボタンのウエでオレのマリョク + Press UP on the D-Pad + $1251A (Line 2) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24C3DE 23B5 DA 24C9 23CF D8 AE B8 | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # て " # オ レ # の # マ リ ョ ク | Original Japanese Text + がサクレツだゼ! + to use it! + $12537 (Line 3) + 24B6DE 23BB B8 DA C2 24C0DE 23BEDE 3A FF | Original Japanese Hex + # か " # サ ク レ ツ # た " # セ " ! # | Original Japanese Text + $11AFD + 02 A5 | Memory Address + + QUEEN: + クリスタルをけすのはキホンよ! + It is basic knowledge to use crystals! + $12547 (Line 1) + 23B8 D8 BD C0 D9 24A6 B9 BD C9 CA 23B7 CE DD 24D6 3A 25 | Original Japanese Hex + # ク リ ス タ ル # を け す の は # キ ホ ン # よ ! NL | Original Japanese Text + ジュウジボタンのウエでわたくしのかれ + Use UP on D-Pad for my + $1255B (Line 2) + 23BCDE AD B3 BCDE CEDE C0 DD 24C9 23B3 B4 24C3DE DC C0 B8 BC C9 B6 DA | Original Japanese Hex + # シ " ュ ウ シ " ホ " タ ン # の # ウ エ # て " わ た く し の か れ | Original Japanese Text + いなワザがおがめましてよ! + beautiful magic! + $12575 (Line 3) + B2 C5 23DC BBDE 24B6DE B5 B6DE D2 CF BC C3 D6 3A FF | Original Japanese Hex + い な # ワ サ " # か " お か " め ま し て よ ! # | Original Japanese Text + $11AFF + 47 A5 | Memory Address + +PAUSE SCREEN MAGIC: + MAGIC01: + ミルルン + Mirurun + $125DE + 20 20 D0 D9 D9 DD 20 20 FF | Original Japanese Hex + ミ ル ル ン # | Original Japanese Text + $12588 + DE A5 | Memory Address + + MAGIC02: + コピー + Copy + $125E7 + 20 20 20 BA CBDF B0 20 20 FF | Original Japanese Hex + コ ヒ o ー # | Original Japanese Text + $1258A + E7 A5 | Memory Address + + MAGIC03: + メデューサ + Medusa + $125F1 + 20 20 D2 C3DE AD B0 BB 20 FF | Original Japanese Hex + メ テ " ュ ー サ # | Original Japanese Text + $1258C + F1 A5 | Memory Address + + MAGIC04: + ボム + Bomb + $125FB + 20 20 20 CEDE D1 20 20 20 FF | Original Japanese Hex + ホ " ム # | Original Japanese Text + $1258E + FB A5 | Memory Address + + MAGIC05: + マヤカシ + Deception/Make-Believe/Fake/Counterfeit/Phony + $12605 + 20 20 CF D4 B6 BC 20 20 FF | Original Japanese Hex + マ ヤ カ シ # | Original Japanese Text + $12590 + 05 A6 | Memory Address + + MAGIC06: + ペンタリス + Pentris + $1260E + 20 20 CDDF DD C0 D8 BD 20 FF | Original Japanese Hex + ヘ o ン タ リ ス # | Original Japanese Text + $12592 + 0E A6 | Memory Address + + MAGIC07: + ダイナシ + Spoil/Shamble/Destroy + $12618 + 20 20 C0DE B2 C5 BC 20 20 FF | Original Japanese Hex + タ " イ ナ シ # | Original Japanese Text + $12594 + 18 A6 | Memory Address + + MAGIC08: + フライ + Fry + $12622 + 20 20 20 CC D7 B2 20 20 FF | Original Japanese Hex + フ ラ イ # | Original Japanese Text + $12596 + 22 A6 | Memory Address + + MAGIC09: + ノロイ + Curse + $1262B + 20 20 20 C9 DB B2 20 20 FF | Original Japanese Hex + ノ ロ イ # | Original Japanese Text + $12598 + 2B A6 | Memory Address + + MAGIC10: + バンパイア + Vampire + $12634 + 20 20 CADE DD CADF B2 B1 20 FF | Original Japanese Hex + ハ " ン ハ o イ ア # | Original Japanese Text + $1259A + 34 A6 | Memory Address + + MAGIC11: + クリアー + Clear + $1263F + 20 20 B8 D8 B1 B0 20 20 FF | Original Japanese Hex + ク リ ア ー # | Original Japanese Text + $1259C + 3F A6 | Memory Address + + MAGIC12: + シーソー + Seesaw + $12648 + 20 20 BC B0 BF B0 20 20 FF | Original Japanese Hex + シ ー ソ ー # | Original Japanese Text + $1259E + 48 A6 | Memory Address + $125A0 + 48 A6 | Memory Address + $125A2 + 48 A6 | Memory Address + + MAGIC13: + カット + Cut / Slice + $12651 + 20 20 20 B6 AF C4 20 20 FF | Original Japanese Hex + カ ッ ト # | Original Japanese Text + $125A4 + 51 A6 | Memory Address + + MAGIC14: + モーゼ + Moses + $1265A + 20 20 20 D3 B0 BEDE 20 20 FF | Original Japanese Hex + モ ー セ " # | Original Japanese Text + $125A6 + 5A A6 | Memory Address + + MAGIC15: + マンボ + Mambo + $12664 + 20 20 20 CF DD CEDE 20 20 FF | Original Japanese Hex + マ ン ホ " # | Original Japanese Text + $125A8 + 64 A6 | Memory Address + + MAGIC16: + スターダスト + Stardust + $1266E + 20 BD C0 B0 C0DE BD C4 20 FF | Original Japanese Hex + ス タ ー タ " ス ト # | Original Japanese Text + $125AA + 6E A6 | Memory Address + + MAGIC17: + リバース + Reverse + $12678 + 20 20 D8 CADE B0 BD 20 20 FF | Original Japanese Hex + リ ハ " ー ス # | Original Japanese Text + $125AC + 78 A6 | Memory Address + + MAGIC18: + マヒ + Paralyze + $12682 + 20 20 20 CF CB 20 20 20 FF | Original Japanese Hex + マ ヒ # | Original Japanese Text + $125AE + 82 A6 | Memory Address + + MAGIC19: + カイテン + Rotate/Rotation + $1268B + 20 20 B6 B2 C3 DD 20 20 FF | Original Japanese Hex + カ イ テ ン # | Original Japanese Text + $125B0 + 8B A6 | Memory Address + + MAGIC20: + ヨセ + Yose / Gather + $12694 + 20 20 20 D6 BE 20 20 20 FF | Original Japanese Hex + ヨ セ # | Original Japanese Text + $125B2 + 94 A6 | Memory Address + + MAGIC21: + ギャング + Gang + $1269D + 20 20 B7DE AC DD B8DE 20 20 FF | Original Japanese Hex + キ " ャ ン ク " # | Original Japanese Text + $125B4 + 9D A6 | Memory Address + + MAGIC22: + ドトン + Earth Release/Rensa + $126A8 + 20 20 20 C4DE C4 DD 20 20 FF | Original Japanese Hex + ト " ト ン # | Original Japanese Text + $125B6 + A8 A6 | Memory Address + + MAGIC23: + プレス + Press / Crush / Stomp + $126B2 + 20 20 20 CCDF DA BD 20 20 FF | Original Japanese Hex + フ o レ ス # | Original Japanese Text + $125B8 + B2 A6 | Memory Address + + MAGIC24: + ソル + Soul + $126BC + 20 20 20 BF D9 20 20 20 FF | Original Japanese Hex + ソ ル # | Original Japanese Text + $125BA + BC A6 | Memory Address + + MAGIC25: + スリトテ + Sirtet + $126C5 + 20 20 BD D8 C4 C3 20 20 FF | Original Japanese Hex + ス リ ト テ # | Original Japanese Text + $125BC + C5 A6 | Memory Address + + MAGIC26: + ファックス + Fax + $126CE + 20 20 CC A7 AF B8 BD 20 FF | Original Japanese Hex + フ ァ ッ ク ス # | Original Japanese Text + $125BE + CE A6 | Memory Address + + MAGIC27: + シールド + Shield + $126D7 + 20 20 BC B0 D9 C4DE 20 20 FF | Original Japanese Hex + シ ー ル ト " # | Original Japanese Text + $125C0 + D7 A6 | Memory Address + + MAGIC28: + ミラー + Mirror + $126E1 + 20 20 20 D0 D7 B0 20 20 FF | Original Japanese Hex + ミ ラ ー # | Original Japanese Text + $125C2 + E1 A6 | Memory Address + + MAGIC29: + ヘビー + Heavy + $126EA + 20 20 20 CD CBDE B0 20 20 FF | Original Japanese Hex + ヘ ヒ " ー # | Original Japanese Text + $125C4 + EA A6 | Memory Address + + MAGIC30: + セレクト + Select + $126F4 + 20 20 BE DA B8 C4 20 20 FF | Original Japanese Hex + セ レ ク ト # | Original Japanese Text + $125C6 + F4 A6 | Memory Address + + MAGIC31: + ヌー + Slow Down/Gnu/Wildebeest/Nu/New/Noose + $126FD + 20 20 20 C7 B0 20 20 20 FF | Original Japanese Hex + ヌ ー # | Original Japanese Text + $125C8 + FD A6 | Memory Address + + MAGIC32: + リモコン + Remote Control + $12706 + 20 20 D8 D3 BA DD 20 20 FF | Original Japanese Hex + リ モ コ ン # | Original Japanese Text + $125CA + 06 A7 | Memory Address + + MAGIC33: + ハンテン + Reversal/Reverse/Invert/Flip + $1270F + 20 20 CA DD C3 DD 20 20 FF | Original Japanese Hex + ハ ン テ ン # | Original Japanese Text + $125CC + 0F A7 | Memory Address + + MAGIC34: + ナカヨシ + Chum / Buddy / Buddies / Friend / Heal + $12718 + 20 20 C5 B6 D6 BC 20 20 FF | Original Japanese Hex + ナ カ ヨ シ # | Original Japanese Text + $125CE + 18 A7 | Memory Address + + MAGIC35: + イノリ + Pray/Prayer + $12721 + 20 20 20 B2 C9 D8 20 20 FF | Original Japanese Hex + イ ノ リ # | Original Japanese Text + $125D0 + 21 A7 | Memory Address + + MAGIC36: + ルーレット + Roulette + $1272A + 20 20 D9 B0 DA AF C4 20 FF | Original Japanese Hex + ル ー レ ッ ト # | Original Japanese Text + $125D2 + 2A A7 | Memory Address + + MAGIC37: + フィーバー + Fever + $12733 + 20 20 CC A8 B0 CADE B0 20 FF | Original Japanese Hex + フ ィ ー ハ " ー # | Original Japanese Text + $125D4 + 33 A7 | Memory Address + + MAGIC38: + チェンジ + Change + $1273D + 20 20 C1 AA DD BCDE 20 20 FF | Original Japanese Hex + チ ェ ン シ " # | Original Japanese Text + $125D6 + 3D A7 | Memory Address + + MAGIC39: + ダブルス + Doubles + $12747 + 20 20 C0DE CCDE D9 BD 20 20 FF | Original Japanese Hex + タ " フ " ル ス # | Original Japanese Text + $125D8 + 47 A7 | Memory Address + + MAGIC40: + ダーク + Dark + $12752 + 20 20 20 C0DE B0 B8 20 20 FF | Original Japanese Hex + タ " ー ク # | Original Japanese Text + $125DA + 52 A7 | Memory Address + + MAGIC41: + ハイパーフライ + HyperFry + $1275C + CA B2 CADF B0 CC D7 B2 20 FF | Original Japanese Hex + ハ イ ハ o ー フ ラ イ # | Original Japanese Text + $125DC + 5C A7 | Memory Address + +PAUSE SCREEN COMPUTER: + HALLOWEEN1: + キャハハハ! + Kyahahaha! + $12AB0 (Line 1) + 23B7 AC CA CA CA 3A 25 | Original Japanese Hex + # キ ャ ハ ハ ハ ! NL | Original Japanese Text + さあコテンパンにしてやるぞ。 + Let's have fun. + $12AB8 (Line 2) + 24BB B1 23BA C3 DD CADF DD 24C6 BC C3 D4 D9 BFDE A1 25 | Original Japanese Hex + # さ あ # コ テ ン ハ o ン # に し て や る そ " 。 NL | Original Japanese Text + カモーン! + Come on! + $12ACC (Line 3) + 23B6 D3 B0 DD 3A FF | Original Japanese Hex + # カ モ ー ン ! # | Original Japanese Text + $12A4A + B0 AA | Memory Address + + HALLOWEEN2: + キャハハハ! + Kyahahaha! + $12AD3 (Line 1) + 23B7 AC CA CA CA 3A 25 | Original Japanese Hex + # キ ャ ハ ハ ハ ! NL | Original Japanese Text + ちょっとできるからってチョウシに + Because I can do it for a while + $12ADB (Line 2) + 24C1 AE AF C4 C3DE B7 D9 B6 D7 AF C3 23C1 AE B3 BC 24C6 25 | Original Japanese Hex + # ち ょ っ と て " き る か ら っ て # チ ョ ウ シ # に NL | Original Japanese Text + のるなよ! + Do not settle! + $12AF0 (Line 3) + C9 D9 C5 D6 3A 25 | Original Japanese Hex + の る な よ ! NL | Original Japanese Text + すぐになかしちゃるからな! + It will be an outrage soon! + $12AF6 (Line 4) + BD B8DE C6 C5 B6 BC C1 AC D9 B6 D7 C5 3A FF | Original Japanese Hex + す く " に な か し ち ゃ る か ら な ! # | Original Japanese Text + $12A4C + D3 AA | Memory Address + + HALLOWEEN3: + オッ、オイラをここまでおいつめるとは + Oh, to put up with us so far/Oh, to put it all together so far + $12B05 (Line 1) + 23B5 AF A4 B5 B2 D7 24A6 BA BA CF C3DE B5 B2 C2 D2 D9 C4 CA | Original Japanese Hex + # オ ッ 、 オ イ ラ # を こ こ ま て " お い つ め る と は | Original Japanese Text + ナカナカやるな! + Do not panic! + $12B1A (Line 2) + 23C5 B6 C5 B6 24D4 D9 C5 3A 25 | Original Japanese Hex + # ナ カ ナ カ # や る な ! NL | Original Japanese Text + でもすぐになかしちゃるからな! + But it will be used soon! + $12B25 (Line 3) + C3DE D3 BD B8DE C6 C5 B6 BC C1 AC D9 B6 D7 C5 3A FF | Original Japanese Hex + て " も す く " に な か し ち ゃ る か ら な ! # | Original Japanese Text + $12A4E + 05 AB | Memory Address + + MIRURUN1: + ミルルンがんばるもーん! + Mirurun I will do my best! + $12B37 (Line 1) + 23D0 D9 D9 DD 24B6DE DD CADE D9 D3 B0 DD 3A 25 | Original Japanese Hex + # ミ ル ル ン # が " ん ば " る も ー ん ! NL | Original Japanese Text + よろしく! + Nice to meet you! + $12B48 (Line 2) + D6 DB BC B8 3A FF | Original Japanese Hex + よ ろ し く ! # | Original Japanese Text + $12A50 + 37 AB | Memory Address + + MIRURUN2: + ミルルンちょっとピンチ。 + Mirurun a little pinch. + $12B4E (Line 1) + 23D0 D9 D9 DD 24C1 AE AF C4 23CBDF DD C1 A1 25 | Original Japanese Hex + # ミ ル ル ン # ち ょ っ と # ヒ o ン チ 。 NL | Original Japanese Text + でもまけないんだもーん! + But I can not lose! + $12B5F (Line 2) + 24C3DE D3 CF B9 C5 B2 DD C0DE D3 B0 DD 3A FF | Original Japanese Hex + # て " も ま け な い ん た " も ー ん ! # | Original Japanese Text + $12A52 + 4E AB | Memory Address + + MIRURUN3: + ミルルンすごくピンチ! + Mirurun is really pinch! + $12B6F (Line 1) + 23D0 D9 D9 DD 24BD BADE B8 23CBDF DD C1 3A 25 | Original Japanese Hex + # ミ ル ル ン # す こ " く # ヒ o ン チ ! NL | Original Japanese Text + でもがんばっちゃうんだもーん! + But I will do my best! + $12B80 (Line 2) + 24C3DE D3 B6DE DD CADE AF C1 AC B3 DD C0DE D3 B0 DD 3A 25 | Original Japanese Hex + # て " も か " ん は " っ ち ゃ う ん た " も ー ん ! NL | Original Japanese Text + すごくがんばっちゃうんだもーん!! + I'm doing my best!! + $12B95 (Line 3) + BD BADE B8 B6DE DD CADE AF C1 AC B3 DD C0DE D3 B0 DD 3A 3A FF | Original Japanese Hex + す こ " く か " ん は " っ ち ゃ う ん た " も ー ん ! ! # | Original Japanese Text + $12A54 + 6F AB | Memory Address + + SHAMAN1: + ンンダーウンダバ + I'll go easy on you + $12BAB (Line 1) + 23DD DD C0DE B0 B3 DD C0DE CADE 25 | Original Japanese Hex + # ン ン タ " ー ウ ン タ " ハ " NL | Original Japanese Text + いみ、おれはテトリスのカミにつかえて + I worship the god of tetris, + $12BB8 (Line 2) + 24B2 D0 A4 B5 DA CA 23C3 C4 D8 BD 24C9 23B6 D0 24C6 C2 B6 B4 C3 | Original Japanese Hex + # い み 、 お れ は # テ ト リ ス # の # カ ミ # に つ か え て | Original Japanese Text + いるからつよい。 + who gives me strength. + $12BCF (Line 3) + B2 D9 B6 D7 C2 D6 B2 A1 FF | Original Japanese Hex + い る か ら つ よ い 。 # | Original Japanese Text + $12A56 + AB AB | Memory Address + + SHAMAN2: + ンダダバオバオ + Da Da Bao Bao + $12BD8 (Line 1) + 23DD C0DE C0DE CADE B5 CADE B5 25 | Original Japanese Hex + # ン タ " タ " ハ " オ ハ " オ NL | Original Japanese Text + いみ、テトリスのカミはいつもおれを + Ok, Tetris game always makes me + $12BE5 (Line 2) + 24B2 D0 A4 23C3 C4 D8 BD 24C9 23B6 D0 24CA B2 C2 D3 B5 DA A6 25 | Original Japanese Hex + # い み 、 # テ ト リ ス # の # カ ミ # は い つ も お れ を NL | Original Japanese Text + みまもっている。 + I'm obsessed. + $12BFC (Line 3) + D0 CF D3 AF C3 B2 D9 A1 25 | Original Japanese Hex + み ま も っ て い る 。 NL | Original Japanese Text + だからまけない。 + So I will not lose. + $12C05 (Line 4) + C0DE B6 D7 CF B9 C5 B2 A1 FF | Original Japanese Hex + た " か ら ま け な い 。 # | Original Japanese Text + $12A58 + D8 AB | Memory Address + + SHAMAN3: + ンガーンガーオーオー + Nga-Nga-Oh-Oh/Singer + $12C0F (Line 1) + 23DD B6DE B0 DD B6DE B0 B5 B0 B5 B0 25 | Original Japanese Hex + # ン カ " ー ン カ " ー オ ー オ ー NL | Original Japanese Text + いみ、これはテトリスのカミにあたえら + Maybe this is a sign from the god of tetris. + $12C1D (Line 2) + 24B2 D0 A4 BA DA CA 23C3 C4 D8 BD 24C9 23B6 D0 24C6 B1 C0 B4 D7 | Original Japanese Hex + # い み 、 こ れ は # テ ト リ ス # の # カ ミ # に あ た え ら | Original Japanese Text + れたシレンである。 + It was a siren. + $12C34 (Line 3) + DA C0 23BC DA DD 24C3DE B1 D9 A1 25 | Original Japanese Hex + れ た # シ レ ン # て " あ る 。 NL | Original Japanese Text + だからかならずシレンをコクフクする! + So always make sure to shrink Siren! + $12C41 (Line 4) + C0DE B6 D7 B6 C5 D7 BDDE 23BC DA DD 24A6 23BA B8 CC B8 24BD D9 3A FF | Original Japanese Hex + た " か ら か な ら す " # シ レ ン # を # コ ク フ ク # す る ! # | Original Japanese Text + $12A5A + 0F AC | Memory Address + + ALADDIN1: + はっはっは! + Ha ha ha! + $12C5A (Line 1) + 24CA AF CA AF CA 3A 25 | Original Japanese Hex + # は っ は っ は ! NL | Original Japanese Text + このショウブ、ぼくのかちはきまった + A Victory will + $12C62 (Line 2) + BA C9 23BC AE B3 CCDE A4 24CEDE B8 C9 B6 C1 CA B7 CF AF C0 25 | Original Japanese Hex + こ の # シ ョ ウ フ " 、 # ほ " く の か ち は き ま っ た NL | Original Japanese Text + ようなものですね。 + surely be mine. + $12C78 (Line 3) + D6 B3 C5 D3 C9 C3DE BD C8 A1 FF | Original Japanese Hex + よ う な も の て " す ね 。 # | Original Japanese Text + $12A5C + 5A AC | Memory Address + + ALADDIN2: + はっはっは! + Ha ha ha! + $12C83 (Line 1) + 24CA AF CA AF CA 3A 25 | Original Japanese Hex + # は っ は っ は ! NL | Original Japanese Text + なかなかやりますね。 + It is quite easy. + $12C8B (Line 2) + C5 B6 C5 B6 D4 D8 CF BD C8 A1 25 | Original Japanese Hex + な か な か や り ま す ね 。 NL | Original Japanese Text + でも、ぼくのかちはかわりませんね。 + But I will not change my win. + $12C96 (Line 3) + C3DE D3 A4 CEDE B8 C9 B6 C1 CA B6 DC D8 CF BE DD C8 A1 FF | Original Japanese Hex + て " も 、 ほ " く の か ち は か わ り ま せ ん ね 。 # | Original Japanese Text + $12A5E + 83 AC | Memory Address + + ALADDIN3: + ぼっ、ぼくがまけるはずないんだ。 + But, I can not lose. + $12CAA (Line 1) + 24CEDE AF A4 CEDE B8 B6DE CF B9 D9 CA BDDE C5 B2 DD C0DE A1 25 | Original Japanese Hex + # ほ " っ 、 ほ " く か " ま け る は す " な い ん た " 。 NL | Original Japanese Text + すっ、すぐにかいふくしてやるからな! + Well, I will recover quickly! + $12CC1 (Line 2) + BD AF A4 BD B8DE C6 B6 B2 CC B8 BC C3 D4 D9 B6 D7 C5 3A FF | Original Japanese Hex + す っ 、 す く " に か い ふ く し て や る か ら な ! # | Original Japanese Text + $12A60 + AA AC | Memory Address + + PRINCESS1: + わたし、いっしょうけんめい + I'll do my + $12CD5 (Line 1) + 24DC C0 BC A4 B2 AF BC AE B3 B9 DD D2 B2 25 | Original Japanese Hex + # わ た し 、 い っ し ょ う け ん め い NL | Original Japanese Text + がんばります! + best! + $12CE4 (Line 2) + B6DE DD CADE D8 CF BD 3A 25 | Original Japanese Hex + か " ん は " り ま す ! NL | Original Japanese Text + おてやわらかに! + Try to be gentle! + $12CEE (Line 3) + B5 C3 D4 DC D7 B6 C6 3A FF | Original Japanese Hex + お て や わ ら か に ! # | Original Japanese Text + $12A62 + D5 AC | Memory Address + + PRINCESS2: + ちょっとキケンだわ。 + I am in a bit of a danger./It is a little dangerous. + $12CF7 (Line 1) + 24C1 AE AF C4 23B7 B9 DD 24C0DE DC A1 25 | Original Japanese Hex + # ち ょ っ と # キ ケ ン # た " わ 。 NL | Original Japanese Text + でも、まだまだがんばれるわ! + But I will do my best! + $12D06 (Line 2) + C3DE D3 A4 CF C0DE CF C0DE B6DE DD CADE DA D9 DC 3A FF | Original Japanese Hex + て " も 、 ま た " ま た " か " ん は " れ る わ ! # | Original Japanese Text + $12A64 + F7 AC | Memory Address + + PRINCESS3: + あーん! + Ah! + $12D1A (Line 1) + 24B1 B0 DD 3A 25 | Original Japanese Hex + # あ ー ん ! NL | Original Japanese Text + このままじゃまけちゃう! + I will lose just like this! + $12D20 (Line 2) + BA C9 CF CF BCDE AC CF B9 C1 AC B3 3A 25 | Original Japanese Hex + こ の ま ま し " ゃ ま け ち ゃ う ! NL | Original Japanese Text + でもすぐにギャクテンしちゃうからね! + But I will soon have a big block! + $12D2E (Line 3) + C3DE D3 BD B8DE C6 23B7DE AC B8 C3 DD 24BC C1 AC B3 B6 D7 C8 3A FF | Original Japanese Hex + て " も す く " に # キ " ャ ク テ ン # し ち ゃ う か ら ね ! # | Original Japanese Text + $12A66 + 1A AD | Memory Address + + BIT1: + わーい! + Hooray! + $12D46 (Line 1) + 24DC B0 B2 3A 25 | Original Japanese Hex + # わ ー い ! NL | Original Japanese Text + ブロックがほとんどないぞー + There is almost no blocks + $12D4C (Line 2) + 23CCDE DB AF B8 24B6DE CE C4 DD C4DE C5 B2 BFDE B0 25 | Original Japanese Hex + # フ " ロ ッ ク # か " ほ と ん と " な い そ " ー NL | Original Japanese Text + わーい、わーい! + Yo, Yo! + $12D60 (Line 3) + DC B0 B2 A4 DC B0 B2 3A FF | Original Japanese Hex + わ ー い 、 わ ー い ! # | Original Japanese Text + $12A68 + 46 AD | Memory Address + + BIT2: + わーい! + Hooray! + $12D69 (Line 1) + 24DC B0 B2 3A 25 | Original Japanese Hex + # わ ー い ! NL | Original Japanese Text + ブロックがたくさんあるぞー + There are lots of blocks + $12D6F (Line 2) + 23CCDE DB AF B8 24B6DE C0 B8 BB DD B1 D9 BFDE B0 25 | Original Japanese Hex + # フ " ロ ッ ク # か " た く さ ん あ る そ " ー NL | Original Japanese Text + わーい! + Hooray! + $12D82 (Line 3) + DC B0 B2 3A FF | Original Japanese Hex + わ ー い ! # | Original Japanese Text + $12A6A + 69 AD | Memory Address + + BIT3: + アワワ!アワワ! + Awawa! Awa! + $12D87 (Line 1) + 23B1 DC DC 3A B1 DC DC 3A 25 | Original Japanese Hex + # ア ワ ワ ! ア ワ ワ ! NL | Original Japanese Text + ブロックがウエまであるぞー + There are blocks upto the top + $12D91 (Line 2) + CCDE DB AF B8 24B6DE 23B3 B4 24CF C3DE B1 D9 BFDE B0 2325 | Original Japanese Hex + フ " ロ ッ ク # か " # ウ エ # ま て " あ る そ " ー # NL | Original Japanese Text + アワワ!アワワ! + Awawa! Awa! + $12DA7 (Line 3) + B1 DC DC 3A B1 DC DC 3A FF | Original Japanese Hex + ア ワ ワ ! ア ワ ワ ! # | Original Japanese Text + $12A6C + 87 AD | Memory Address + + NINJA1: + このショウブ、もらったな。 + I have got this game. + $12DB0 (Line 1) + 24BA C9 23BC AE B3 CCDE A4 24D3 D7 AF C0 C5 A1 25 | Original Japanese Hex + # こ の # シ ョ ウ フ " 、 # も ら っ た な 。 NL | Original Japanese Text + オレのニンジュツでいっきにショウブを + I will win this game at once with my ninjutsu + $12DC2 (Line 2) + 23B5 DA 24C9 23C6 DD BCDE AD C2 24C3DE B2 AF B7 C6 23BC AE B3 CCDE 24A6 | Original Japanese Hex + # オ レ # の # ニ ン シ " ュ ツ # て " い っ き に # シ ョ ウ フ " # を | Original Japanese Text + つけてやるぜ! + I'll do it! + $12DDD (Line 3) + C2 B9 C3 D4 D9 BEDE 3A FF | Original Japanese Hex + つ け て や る せ " ! # | Original Japanese Text + $12A6E + B0 AD | Memory Address + + NINJA2: + むむっ!やるな! + Do not do it! + $12DE6 (Line 1) + 24D1 D1 AF 3A D4 D9 C5 3A 25 | Original Japanese Hex + # む む っ ! や る な ! NL | Original Japanese Text + だがこのテイドではおれのニンジュツを + It is not possible to break my ninjutsu + $12DF0 (Line 2) + C0DE B6DE BA C9 23C3 B2 C4DE 24C3DE CA B5 DA C9 23C6 DD BCDE AD C2 24A6 | Original Japanese Hex + た " か " こ の # テ イ ト " # て " は お れ の # ニ ン シ " ュ ツ # を | Original Japanese Text + やぶることはできないぞ! + to this degree! + $12E0B (Line 3) + D4 CCDE D9 BA C4 CA C3DE B7 C5 B2 BFDE 3A FF | Original Japanese Hex + や ふ " る こ と は て " き な い そ " ! # | Original Japanese Text + $12A70 + E6 AD | Memory Address + + NINJA3: + キョウコ! + Growth! + $12E1B (Line 1) + 23B7 AE B3 BA 3A 25 | Original Japanese Hex + # キ ョ ウ コ ! NL | Original Japanese Text + かならずギャクテンしてやるからな! + I will always be going to play a game!/Always it because I'll reversed! + $12E22 (Line 2) + 24B6 C5 D7 BDDE 23B7DE AC B8 C3 DD 24BC C3 D4 D9 B6 D7 C5 3A 25 | Original Japanese Hex + # か な ら す " # キ " ャ ク テ ン # し て や る か ら な ! NL | Original Japanese Text + まっていろよ! + Please wait! + $12E39 (Line 3) + CF AF C3 B2 DB D6 3A FF | Original Japanese Hex + ま っ て い ろ よ ! # | Original Japanese Text + $12A72 + 1B AE | Memory Address + + WOLFMAN1: + せっしゃ、ショウブにシジョウは + I will show you my strength + $12E41 (Line 1) + 24BE AF BC AC A4 23BC AE B3 CCDE 24C6 23BC BCDE AE B3 24CA 25 | Original Japanese Hex + # せ っ し ゃ 、 # シ ョ ウ フ " # に # シ シ " ョ ウ # は NL | Original Japanese Text + もちこまないでござる。 + I do not mind bothering you. + $12E58 (Line 2) + D3 C1 BA CF C5 B2 C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + も ち こ ま な い て " こ " さ " る 。 # | Original Japanese Text + $12A74 + 41 AE | Memory Address + + WOLFMAN2: + せっしゃ、このテイドではびくともしな + Sadly, this round is awkward + $12E67 (Line 1) + 24BE AF BC AC A4 BA C9 23C3 B2 C4DE 24C3DE CA CBDE B8 C4 D3 BC C5 | Original Japanese Hex + # せ っ し ゃ 、 こ の # テ イ ト " # て " は ひ " く と も し な | Original Japanese Text + いでござる。 + It is bad. + $12E7F (Line 2) + B2 C3DE BADE BBDE D9 A1 25 | Original Japanese Hex + い て " こ " さ " る 。 NL | Original Japanese Text + すぐにハンゲキするでござる。 + It is a pleasure to fight you. + $12E89 (Line 3) + BD B8DE C6 23CA DD B9DE B7 24BD D9 C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + す く " に # ハ ン ケ " キ # す る て " こ " さ " る 。 # | Original Japanese Text + $12A76 + 67 AE | Memory Address + + WOLFMAN3: + せっしゃ、キュウチにおいてもキボウは + Well, even in cucumbers + $12E9F (Line 1) + 24BE AF BC AC A4 23B7 AD B3 C1 24C6 B5 B2 C3 D3 23B7 CEDE B3 24CA | Original Japanese Hex + # せ っ し ゃ 、 # キ ュ ウ チ # に お い て も # キ ホ " ウ # は | Original Japanese Text + すてないでござる! + I will not throw it away! + $12EB7 (Line 2) + BD C3 C5 B2 C3DE BADE BBDE D9 3A 25 | Original Japanese Hex + す て な い て " こ " さ " る ! NL | Original Japanese Text + かならずカリはかえすでござる。 + Kari is always returning. + $12EC4 (Line 3) + B6 C5 D7 BDDE 23B6 D8 24CA B6 B4 BD C3DE BADE BBDE D9 A1 FF | Original Japanese Hex + か な ら す " # カ リ # は か え す て " こ " さ " る 。 # | Original Japanese Text + $12A78 + 9F AE | Memory Address + + DRAGON1: + フッフッフ + Fuf fuf fu + $12EDA (Line 1) + 23CC AF CC AF CC 25 | Original Japanese Hex + # フ ッ フ ッ フ NL | Original Japanese Text + このオレさまにかてるとおもうのか? + Do you think you can beat me? + $12EE1 (Line 2) + 24BA C9 23B5 DA 24BB CF C6 B6 C3 D9 C4 B5 D3 B3 C9 B6 3B 25 | Original Japanese Hex + # こ の # オ レ # さ ま に か て る と お も う の か ? NL | Original Japanese Text + にげだすならいまのうちだぞ! + Give up now, run away! + $12EF6 (Line 3) + C6 B9DE C0DE BD C5 D7 B2 CF C9 B3 C1 C0DE BFDE 3A FF | Original Japanese Hex + に け " た " す な ら い ま の う ち た " そ " ! # | Original Japanese Text + $12A7A + DA AE | Memory Address + + DRAGON2: + このテイドでかったとおもったら + If you think that you can win this round + $12F09 (Line 1) + 24BA C9 23C3 B2 C4DE 24C3DE B6 AF C0 C4 B5 D3 AF C0 D7 25 | Original Japanese Hex + # こ の # テ イ ト " # て " か っ た と お も っ た ら NL | Original Japanese Text + おおまちがいだぞ。 + you will lose. + $12F1E (Line 2) + B5 B5 CF C1 B6DE B2 C0DE BFDE A1 25 | Original Japanese Hex + お お ま ち か " い た " そ " 。 NL | Original Japanese Text + すぐにジゴクをみせてやろう。 + I will show you defeat soon. + $12F2B (Line 3) + BD B8DE C6 23BCDE BADE B8 24A6 D0 BE C3 D4 DB B3 A1 FF | Original Japanese Hex + す く " に # シ " コ " ク # を み せ て や ろ う 。 # | Original Japanese Text + $12A7C + 09 AF | Memory Address + + DRAGON3: + おのれ! + You! + $12F3F (Line 1) + 24B5 C9 DA 3A 25 | Original Japanese Hex + # お の れ ! NL | Original Japanese Text + よもやここまでやるとは! + Wonder what to do here! + $12F45 (Line 2) + D6 D3 D4 BA BA CF C3DE D4 D9 C4 CA 3A 25 | Original Japanese Hex + よ も や こ こ ま て " や る と は ! NL | Original Japanese Text + だがオレはマダまけんぞ!! + But I still will not lose!! + $12F53 (Line 3) + C0DE B6DE 23B5 DA 24CA 23CF C0DE 24CF B9 DD BFDE 3A 3A FF | Original Japanese Hex + た " か " # オ レ # は # マ タ " # ま け ん そ " ! ! # | Original Japanese Text + $12A7E + 3F AF | Memory Address + + QUEEN1: + ホーッホホホ! + Ho ho ho! + $12F69 (Line 1) + 23CE B0 AF CE CE CE 3A 25 | Original Japanese Hex + # ホ ー ッ ホ ホ ホ ! NL | Original Japanese Text + さあ、いまのうちにあやまりなさい! + Come now, please apologize! + $12F72 (Line 2) + 24BB B1 A4 B2 CF C9 B3 C1 C6 B1 D4 CF D8 C5 BB B2 3A 25 | Original Japanese Hex + # さ あ 、 い ま の う ち に あ や ま り な さ い ! NL | Original Japanese Text + そうすればゆるしてあげるわよ! + Then I will forgive you! + $12F85 (Line 3) + BF B3 BD DA CADE D5 D9 BC C3 B1 B9DE D9 DC D6 3A FF | Original Japanese Hex + そ う す れ は " ゆ る し て あ け " る わ よ ! # | Original Japanese Text + $12A80 + 69 AF | Memory Address + + QUEEN2: + ホーッホホホ! + Ho ho ho! + $12F97 (Line 1) + 23CE B0 AF CE CE CE 3A 25 | Original Japanese Hex + # ホ ー ッ ホ ホ ホ ! NL | Original Japanese Text + なかなかやるわね! + It's quite easy! + $12FA0 (Line 2) + 24C5 B6 C5 B6 D4 D9 DC C8 3A 25 | Original Japanese Hex + # な か な か や る わ ね ! NL | Original Japanese Text + でもわたくしはまだホンキを + But I am still not + $12FAB (Line 3) + C3DE D3 DC C0 B8 BC CA CF C0DE 23CE DD B7 24A6 25 | Original Japanese Hex + て " も わ た く し は ま た " # ホ ン キ # を NL | Original Japanese Text + だしてなくてよ! + trying hard! + $12FBD (Line 4) + C0DE BC C3 C5 B8 C3 D6 3A FF | Original Japanese Hex + た " し て な く て よ ! # | Original Japanese Text + $12A82 + 97 AF | Memory Address + + QUEEN3: + ホーッホホホ! + Ho ho ho! + $12FC7 (Line 1) + 23CE B0 AF CE CE CE 3A 25 | Original Japanese Hex + # ホ ー ッ ホ ホ ホ ! NL | Original Japanese Text + わたくしをホンキにさせてくれたわね! + You made me angry! + $12FD0 (Line 2) + 24DC C0 B8 BC A6 23CE DD B7 24C6 BB BE C3 B8 DA C0 DC C8 3A | Original Japanese Hex + # わ た く し を # ホ ン キ # に さ せ て く れ た わ ね ! | Original Japanese Text + さあ!わたしのまえにひざまづくのよ! + Come on! Kneel down before me! + $12FE5 (Line 3) + BB B1 3A DC C0 BC C9 CF B4 C6 CB BBDE CF C2DE B8 C9 D6 3A FF | Original Japanese Hex + さ あ ! わ た し の ま え に ひ さ " ま つ " く の よ ! # | Original Japanese Text + $12A84 + C7 AF | Memory Address \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/SETTING.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/SETTING.txt new file mode 100644 index 00000000..4abd9ae7 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/SETTING.txt @@ -0,0 +1,105 @@ +BACK GROUND + 2PキャラBG + 2P Character BG + $0121B + 32 50 B7 AC D7 42 47 FF | Original Japanese Hex + 2 P キ ャ ラ B G # | Original Japanese Text + 2 P C H R B G # | New English Text + 32 50 43 48 52 42 47 FF | New English Hex + + ハロウィン + Halloween + $01223 + CA DB B3 A8 DD 20 20 FF | Original Japanese Hex + ハ ロ ウ ィ ン # | Original Japanese Text + H A L L O W E # | New English Text + 48 41 4C 4C 4F 57 45 FF | New English Hex + + ミルルン + Mirurun + $0122B + D0 D9 D9 DD 20 20 20 FF | Original Japanese Hex + ミ ル ル ン # | Original Japanese Text + M I R U R U N # | New English Text + 4D 49 52 55 52 55 4E FF | New English Hex + + シャーマン + Shaman + $01233 + BC AC B0 CF DD 20 20 FF | Original Japanese Hex + シ ャ ー マ ン # | Original Japanese Text + S H A M A N # | New English Text + 53 48 41 4D 41 4E 20 FF | New English Hex + + アラジン + Aladdin + $0123B + B1 D7 BC DE DD 20 20 FF | Original Japanese Hex + ア ラ シ " ン # | Original Japanese Text + A L A D D I N # | New English Text + 41 4C 41 44 44 49 4E FF | New English Hex + + プリンセス + Princess + $01243 + CC DF D8 DD BE BD 20 FF | Original Japanese Hex + フ o リ ン セ ス # | Original Japanese Text + P R I N C E S # | New English Text + 50 52 49 4E 43 45 53 FF | New English Hex + + ビット + Bit + $0124B + CB DE AF C4 20 20 20 FF | Original Japanese Hex + ヒ " ッ ト # | Original Japanese Text + B I T # | New English Text + 42 49 54 20 20 20 20 FF | New English Hex + + ニンジャ + Ninja + $01253 + C6 DD BC DE AC 20 20 FF | Original Japanese Hex + ニ ン シ " ャ # | Original Japanese Text + N I N J A # | New English Text + 4E 49 4E 4A 41 20 20 FF | New English Hex + + オオカミオトコ + Wolfman + $0125B + B5 B5 B6 D0 B5 C4 BA FF | Original Japanese Hex + オ オ カ ミ オ ト コ # | Original Japanese Text + W O L F M A N # | New English Text + 57 4F 4C 46 4D 41 4E FF | New English Hex + + ドラゴン + Dragon + $01263 + C4 DE D7 BA DE DD 20 FF | Original Japanese Hex + ト " ラ コ " ン # | Original Japanese Text + D R A G O N # | New English Text + 44 52 41 47 4F 4E 20 FF | New English Hex + + グラプリ + Grand Princess (Queen) Empress + $0126B + B8 DE D7 CC DF D8 20 FF | Original Japanese Hex + ? " ラ フ o リ # | Original Japanese Text + Q U E E N # | New English Text + 51 55 45 45 4E 20 20 FF | New English Hex + +STEREO/MONO + ステレオ + Stereo + $01277 + BD C3 DA B5 FF | Original Japanese Hex + ス テ レ オ # | Original Japanese Text + S T E R # | New English Text + 53 54 45 52 FF | New English Hex + + モノラル + Monaural + $0127C + D3 C9 D7 D9 FF | Original Japanese Hex + モ ノ ラ ル # | Original Japanese Text + M O N O # | New English Text + 4D 4F 4E 4F FF | New English Hex \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/TITLESCREEN.txt b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/TITLESCREEN.txt new file mode 100644 index 00000000..1a658b57 --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/Text/TITLESCREEN.txt @@ -0,0 +1,14 @@ +TETRIS テトリスバトリ外伝 +TETRIS Battle Gaiden + +武 闘 外 伝 +BA TTLE GAI DEN + +ひとりでバトル +Battle by myself / 1 Player Battle + +ふたりでバトル +Battle between us / 2 Player Battle + +オブション +Option / Setting \ No newline at end of file diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen.rle new file mode 100644 index 00000000..b557a394 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/BPSRLEEncode.py new file mode 100644 index 00000000..2a65ed9c --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('TitleScreenENGVRAM$C000.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('TitleScreen.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/BPSRLEEncode.py new file mode 100644 index 00000000..76d1f36b --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('TitleScreenBookENGVRAM$C400.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('TitleScreenBook.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/TitleScreenBookENGVRAM$C400.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/TitleScreenBookENGVRAM$C400.bin new file mode 100644 index 00000000..08ad1d44 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBook/TitleScreenBookENGVRAM$C400.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/BPSRLEEncode.py b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/BPSRLEEncode.py new file mode 100644 index 00000000..4e25262e --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/BPSRLEEncode.py @@ -0,0 +1,70 @@ +from itertools import * + +# BPS SNES RLE Encode +BLOCKRAW = 0x00 # BLOCK: RAW Copy 7-Bit "0x00 + LENGTH (1..127), RAW BYTES" +BLOCKRLE = 0x80 # BLOCK: RLE Copy 7-Bit "0x80 + LENGTH (1..127), RLE BYTE" +# BLOCK: END "0x00, 0xFF" + +fileeven = [] # Clear EVEN Byte Array +fileodd = [] # Clear ODD Byte Array +filein = open('TitleScreenBookMode7ENGODDTILE$0001..$7FFF.bin', 'rb') +byteevenin = filein.read(1) +byteoddin = filein.read(1) +while byteevenin: # Load EVEN/ODD Byte Array + fileeven.append(ord(byteevenin)) # Convert Byte To Int + fileodd.append(ord(byteoddin)) # Convert Byte To Int + byteevenin = filein.read(1) + byteoddin = filein.read(1) +filein.close() + +groupeven = [(len(list(group)),name) for name, group in groupby(fileeven)] # Group EVEN Bytes +groupodd = [(len(list(group)),name) for name, group in groupby(fileodd)] # Group ODD Bytes + +out = [] # RLE EVEN/ODD Byte Output + +def compress(group): + rawbytes = [] # RAW Bytes + groupcount = 0 # Group Count + for (length, byte) in group: + if length >= 3: # IF RLE Length >= 3 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + if length > 127: # IF RLE Length > 127 + while length > 127: # WHILE RLE Length > 127 + out.append(BLOCKRLE+127) # Output RLE Length 127 + out.append(byte) # Output RLE Byte + length -= 127 # RLE Length -= 127 + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: # ELSE RLE Length < 3 + if length == 2 and group[groupcount+1][0] > 2: # IF RLELength == 2 && Next RLELength > 2 + if len(rawbytes) > 0: # IF RAW Length > 0 + if len(rawbytes) > 127: + while len(rawbytes) > 127: # WHILE RAW Length > 127 + out.append(BLOCKRAW+127) # Output RAW Length 127 + for rawbyte in range(127): out.append(rawbytes[rawbyte]) # Output 127 RAW Bytes + del rawbytes[0:127] # RAW Length -= 127 + out.append(BLOCKRAW+len(rawbytes)) # Output RAW Length Byte + for rawbyte in rawbytes: out.append(rawbyte) # Output RAW Bytes + rawbytes = [] # Reset RAW Bytes + out.append(BLOCKRLE+length) # Output RLE Length + out.append(byte) # Output RLE Byte + else: + for i in range(length): rawbytes.append(byte) # Store Next RAW Bytes + groupcount += 1 # Group Count++ + out.append(0x00) # Output RLE BLOCK END Bytes (0x00, 0xFF) + out.append(0xFF) + +compress(groupeven) +compress(groupodd) + +fileout = open('TitleScreenBookMode7.rle', 'wb') +for byte in out: fileout.write(b"%c" %byte) +fileout.close() diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/TitleScreenBookMode7ENGODDTILE$0001..$7FFF.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/TitleScreenBookMode7ENGODDTILE$0001..$7FFF.bin new file mode 100644 index 00000000..0bb013d0 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenBookMode7/TitleScreenBookMode7ENGODDTILE$0001..$7FFF.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenENGVRAM$C000.bin b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenENGVRAM$C000.bin new file mode 100644 index 00000000..a7641a23 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreen/TitleScreenENGVRAM$C000.bin differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBook.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBook.rle new file mode 100644 index 00000000..e15ce664 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBook.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBookMode7.rle b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBookMode7.rle new file mode 100644 index 00000000..9b695ab3 Binary files /dev/null and b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/TitleScreenBookMode7.rle differ diff --git a/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/make.bat b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/make.bat new file mode 100644 index 00000000..9cbbe3bb --- /dev/null +++ b/roms/snes/peter-lemon-snes/Translate/Tetris Battle Gaiden/make.bat @@ -0,0 +1,2 @@ +bass "Tetris Battle Gaiden.asm" +ucon64 --nbak --chk "Tetris Battle Gaiden.sfc" \ No newline at end of file diff --git a/screen/buffer/src/lib.rs b/screen/buffer/src/lib.rs index 0270b7e7..669a653e 100644 --- a/screen/buffer/src/lib.rs +++ b/screen/buffer/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub mod screen_buffer; mod screen_buffer_unit; diff --git a/screen/buffer/src/screen_buffer.rs b/screen/buffer/src/screen_buffer.rs index eefaf39f..ab1efbb3 100644 --- a/screen/buffer/src/screen_buffer.rs +++ b/screen/buffer/src/screen_buffer.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::allocate; use super::screen_buffer_unit::ScreenBufferUnit; use nerust_screen_filter::presentation::ConsoleVideoAssets; diff --git a/screen/buffer/src/screen_buffer_unit.rs b/screen/buffer/src/screen_buffer_unit.rs index 5d89037e..e25b464f 100644 --- a/screen/buffer/src/screen_buffer_unit.rs +++ b/screen/buffer/src/screen_buffer_unit.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::allocate; use nerust_screen_filter::FilterFunc; use nerust_screen_logical::LogicalSize; diff --git a/screen/filter/src/filters/mod.rs b/screen/filter/src/filters/mod.rs index 4cfa088e..f8097911 100644 --- a/screen/filter/src/filters/mod.rs +++ b/screen/filter/src/filters/mod.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub(crate) mod ntsc; pub(crate) mod rgb; diff --git a/screen/filter/src/filters/ntsc.rs b/screen/filter/src/filters/ntsc.rs index 73089dfc..965eaeea 100644 --- a/screen/filter/src/filters/ntsc.rs +++ b/screen/filter/src/filters/ntsc.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::FilterUnit; use nerust_screen_logical::LogicalSize; use nerust_screen_physical::PhysicalSize; diff --git a/screen/filter/src/filters/rgb.rs b/screen/filter/src/filters/rgb.rs index 1d26c020..dba72a2f 100644 --- a/screen/filter/src/filters/rgb.rs +++ b/screen/filter/src/filters/rgb.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::FilterUnit; use nerust_screen_logical::LogicalSize; use nerust_screen_physical::PhysicalSize; diff --git a/screen/filter/src/lib.rs b/screen/filter/src/lib.rs index 9f4d5765..ef61acfa 100644 --- a/screen/filter/src/lib.rs +++ b/screen/filter/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod filters; pub mod presentation; use nerust_screen_logical::LogicalSize; diff --git a/screen/glwrap/src/error.rs b/screen/glwrap/src/error.rs index a6cfaac0..58daec36 100644 --- a/screen/glwrap/src/error.rs +++ b/screen/glwrap/src/error.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use gl::types::*; use std::fmt; use std::fmt::Display; diff --git a/screen/glwrap/src/lib.rs b/screen/glwrap/src/lib.rs index c871d960..50527115 100644 --- a/screen/glwrap/src/lib.rs +++ b/screen/glwrap/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod error; pub mod raw; pub mod vertex; diff --git a/screen/glwrap/src/raw.rs b/screen/glwrap/src/raw.rs index 1eef8d54..8ac283fe 100644 --- a/screen/glwrap/src/raw.rs +++ b/screen/glwrap/src/raw.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #![expect( clippy::not_unsafe_ptr_arg_deref, reason = "this module intentionally mirrors pointer-based OpenGL C APIs" diff --git a/screen/glwrap/src/vertex.rs b/screen/glwrap/src/vertex.rs index 2fdd9c16..39cbb211 100644 --- a/screen/glwrap/src/vertex.rs +++ b/screen/glwrap/src/vertex.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::{Error, gl_error_handle, gl_get_error}; use gl::types::{GLenum, GLint, GLsizei, GLuint}; use std::rc::Rc; diff --git a/screen/logical/src/lib.rs b/screen/logical/src/lib.rs index 730e22db..e5856df3 100644 --- a/screen/logical/src/lib.rs +++ b/screen/logical/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #[derive(serde_derive::Serialize, serde_derive::Deserialize, Debug, Copy, Clone)] pub struct LogicalSize { pub width: usize, diff --git a/screen/opengl/src/lib.rs b/screen/opengl/src/lib.rs index e22a81f5..7649b57c 100644 --- a/screen/opengl/src/lib.rs +++ b/screen/opengl/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod mat4; mod vec2d; mod vertex_data; diff --git a/screen/opengl/src/mat4.rs b/screen/opengl/src/mat4.rs index 997a54bb..9b7e30a0 100644 --- a/screen/opengl/src/mat4.rs +++ b/screen/opengl/src/mat4.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #[derive(Debug, Copy, Clone)] pub(crate) struct Mat4 { _data: [[f32; 4]; 4], diff --git a/screen/opengl/src/vec2d.rs b/screen/opengl/src/vec2d.rs index 36b37e6e..cd9eb6a5 100644 --- a/screen/opengl/src/vec2d.rs +++ b/screen/opengl/src/vec2d.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #[repr(C, packed)] #[derive(Debug, Copy, Clone)] #[allow(dead_code)] diff --git a/screen/opengl/src/vertex_data.rs b/screen/opengl/src/vertex_data.rs index b71291bf..82048047 100644 --- a/screen/opengl/src/vertex_data.rs +++ b/screen/opengl/src/vertex_data.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::Vec2D; #[repr(C, packed)] diff --git a/screen/physical/src/lib.rs b/screen/physical/src/lib.rs index abe32916..576cd541 100644 --- a/screen/physical/src/lib.rs +++ b/screen/physical/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use nerust_screen_logical::LogicalSize; #[derive(serde_derive::Serialize, serde_derive::Deserialize, Debug, Copy, Clone)] diff --git a/screen/rgb/src/lib.rs b/screen/rgb/src/lib.rs index 73ed0baf..644bde83 100644 --- a/screen/rgb/src/lib.rs +++ b/screen/rgb/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - #[derive(serde_derive::Serialize, serde_derive::Deserialize, Debug, Copy, Clone)] pub struct RGB { pub red: u8, diff --git a/screen/video/src/lib.rs b/screen/video/src/lib.rs index 2c9fb83b..e71a2b5c 100644 --- a/screen/video/src/lib.rs +++ b/screen/video/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use nerust_screen_logical::LogicalSize; use nerust_screen_physical::PhysicalSize; diff --git a/screen/wgpu/src/lib.rs b/screen/wgpu/src/lib.rs index dc4f6b48..a0d4f6ab 100644 --- a/screen/wgpu/src/lib.rs +++ b/screen/wgpu/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub mod renderer; mod srgb_lut; pub mod surface; diff --git a/screen/wgpu/src/renderer.rs b/screen/wgpu/src/renderer.rs index 014cf428..4484f6ec 100644 --- a/screen/wgpu/src/renderer.rs +++ b/screen/wgpu/src/renderer.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - mod draw; mod setup; diff --git a/screen/wgpu/src/renderer/draw.rs b/screen/wgpu/src/renderer/draw.rs index d3822971..652a6cd6 100644 --- a/screen/wgpu/src/renderer/draw.rs +++ b/screen/wgpu/src/renderer/draw.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::{RenderOutcome, Renderer, fit_surface_size_to_limit}; use crate::{ surface::{RenderSurface, SurfaceSize, SurfaceTargetSource}, diff --git a/screen/wgpu/src/renderer/setup.rs b/screen/wgpu/src/renderer/setup.rs index 5e54e86f..0e99aef6 100644 --- a/screen/wgpu/src/renderer/setup.rs +++ b/screen/wgpu/src/renderer/setup.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::{DeviceLimitProfile, PresentationOptions, Renderer, fit_surface_size_to_limit}; use crate::{ srgb_lut::SRGB_TO_LINEAR_LUT_BYTES, diff --git a/screen/wgpu/src/surface.rs b/screen/wgpu/src/surface.rs index a7818834..f4862f72 100644 --- a/screen/wgpu/src/surface.rs +++ b/screen/wgpu/src/surface.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use raw_window_handle::{HandleError, RawDisplayHandle, RawWindowHandle}; use wgpu::{Instance, Surface}; diff --git a/screen/wgpu/src/upload.rs b/screen/wgpu/src/upload.rs index 0b3fa219..2693ddae 100644 --- a/screen/wgpu/src/upload.rs +++ b/screen/wgpu/src/upload.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use nerust_screen_logical::LogicalSize; #[derive(Debug, Copy, Clone, Eq, PartialEq)] diff --git a/serialize/src/array.rs b/serialize/src/array.rs index 47c2cb08..eacc5d5a 100644 --- a/serialize/src/array.rs +++ b/serialize/src/array.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use serde::de::{Deserialize, Deserializer, Error, SeqAccess, Visitor}; use serde::ser::{Serialize, SerializeTuple, Serializer}; use std::fmt; diff --git a/serialize/src/lib.rs b/serialize/src/lib.rs index 0f2a1f79..f5d68fcf 100644 --- a/serialize/src/lib.rs +++ b/serialize/src/lib.rs @@ -1,7 +1 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub mod array; diff --git a/snes/core/Cargo.toml b/snes/core/Cargo.toml new file mode 100644 index 00000000..16bca4d9 --- /dev/null +++ b/snes/core/Cargo.toml @@ -0,0 +1,14 @@ +[package] +name = "nerust_snes_core" +version.workspace = true +authors.workspace = true +license.workspace = true +edition.workspace = true +rust-version.workspace = true + +[dependencies] +bitflags.workspace = true +nerust_sound_traits.workspace = true +thiserror.workspace = true + +[dev-dependencies] diff --git a/snes/core/src/apu.rs b/snes/core/src/apu.rs new file mode 100644 index 00000000..7c1541c4 --- /dev/null +++ b/snes/core/src/apu.rs @@ -0,0 +1,2294 @@ +const APU_RAM_LEN: usize = 0x10000; +const APU_PORT_COUNT: usize = 4; +const DSP_REGISTER_COUNT: usize = 0x80; +const IPL_READY_PORTS: [u8; APU_PORT_COUNT] = [0xAA, 0xBB, 0x00, 0x00]; +const IPL_INITIAL_KICK: u8 = 0xCC; +const SMP_CONTROL_RESET_PORTS_0_1: u8 = 0x10; +const SMP_CONTROL_RESET_PORTS_2_3: u8 = 0x20; +const SMP_CONTROL_ENABLE_IPL_ROM: u8 = 0x80; +const SMP_IPL_ROM_START: u16 = 0xFFC0; +const SMP_IPL_ROM: [u8; 64] = [ + 0xCD, 0xEF, 0xBD, 0xE8, 0x00, 0xC6, 0x1D, 0xD0, 0xFC, 0x8F, 0xAA, 0xF4, 0x8F, 0xBB, 0xF5, 0x78, + 0xCC, 0xF4, 0xD0, 0xFB, 0x2F, 0x19, 0xEB, 0xF4, 0xD0, 0xFC, 0x7E, 0xF4, 0xD0, 0x0B, 0xE4, 0xF5, + 0xCB, 0xF4, 0xD7, 0x00, 0xFC, 0xD0, 0xF3, 0xAB, 0x01, 0x10, 0xEF, 0x7E, 0xF4, 0x10, 0xEB, 0xBA, + 0xF6, 0xDA, 0x00, 0xBA, 0xF4, 0xC4, 0xF4, 0xDD, 0x5D, 0xD0, 0xDB, 0x1F, 0x00, 0x00, 0xC0, 0xFF, +]; +const SMP_TIMER_COUNT: usize = 3; +const SMP_TIMER01_SOURCE_CPU_CYCLES: u16 = 448; +const SMP_TIMER2_SOURCE_CPU_CYCLES: u16 = 56; +pub(crate) const SMP_IPL_ENTRY_DELAY_CPU_CYCLES: u8 = 32; +const SMP_CYCLE_UNITS_PER_CPU_CYCLE: u32 = 2; +const SMP_CYCLE_UNITS_PER_SMP_CYCLE: u32 = 1; +const SNES_NTSC_CPU_CLOCK_HZ: u64 = 3_579_545; +const DSP_NATIVE_SAMPLE_RATE: u64 = 32_000; +const DSP_VOICE_COUNT: usize = 8; +const DSP_VOICE_REGISTER_STRIDE: usize = 0x10; +const DSP_MASTER_VOLUME_LEFT: usize = 0x0C; +const DSP_MASTER_VOLUME_RIGHT: usize = 0x1C; +const DSP_KEY_ON: usize = 0x4C; +const DSP_KEY_OFF: usize = 0x5C; +const DSP_FLAGS: usize = 0x6C; +const DSP_SOURCE_DIRECTORY: usize = 0x5D; +const DSP_FLAG_MUTE: u8 = 0x40; +const SMP_FLAG_C: u8 = 0x01; +const SMP_FLAG_Z: u8 = 0x02; +const SMP_FLAG_I: u8 = 0x04; +const SMP_FLAG_H: u8 = 0x08; +const SMP_FLAG_B: u8 = 0x10; +const SMP_FLAG_P: u8 = 0x20; +const SMP_FLAG_V: u8 = 0x40; +const SMP_FLAG_N: u8 = 0x80; + +use nerust_sound_traits::MixerInput; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum IplState { + WaitingForInitialKick, + Transferring { expected_index: u8 }, + Loaded, +} + +#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)] +struct SmpTimer { + target: u8, + divider: u16, + source_accumulator: u16, + output: u8, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct DspVoice { + active: bool, + current_addr: u16, + loop_addr: u16, + block_samples: [i16; 16], + block_index: u8, + prev1: i16, + prev2: i16, + pitch_phase: u64, + block_end: bool, + block_loop: bool, + envelope: u16, +} + +impl Default for DspVoice { + fn default() -> Self { + Self { + active: false, + current_addr: 0, + loop_addr: 0, + block_samples: [0; 16], + block_index: 16, + prev1: 0, + prev2: 0, + pitch_phase: 0, + block_end: false, + block_loop: false, + envelope: 0x07FF, + } + } +} + +impl SmpTimer { + fn reset_output_stages(&mut self) { + self.divider = 0; + self.output = 0; + } + + fn tick_cpu_cycles(&mut self, cycles: u32, source_period: u16, enabled: bool) { + if cycles == 0 { + return; + } + + let source_ticks = (u32::from(self.source_accumulator) + cycles) / u32::from(source_period); + self.source_accumulator = + ((u32::from(self.source_accumulator) + cycles) % u32::from(source_period)) as u16; + if !enabled || source_ticks == 0 { + return; + } + + let effective_target = u32::from(self.effective_target()); + let divider_ticks = u32::from(self.divider) + source_ticks; + let output_ticks = divider_ticks / effective_target; + self.divider = (divider_ticks % effective_target) as u16; + self.output = self.output.wrapping_add((output_ticks & 0x0F) as u8) & 0x0F; + } + + fn effective_target(&self) -> u16 { + match self.target { + 0 => 256, + value => u16::from(value), + } + } + + fn read_output(&mut self) -> u8 { + let value = self.output & 0x0F; + self.output = 0; + value + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct Apu { + ram: Box<[u8; APU_RAM_LEN]>, + cpu_to_apu_ports: [u8; APU_PORT_COUNT], + apu_to_cpu_ports: [u8; APU_PORT_COUNT], + dsp_address: u8, + dsp_registers: [u8; DSP_REGISTER_COUNT], + aux_io: [u8; 2], + control: u8, + timers: [SmpTimer; SMP_TIMER_COUNT], + ipl_state: IplState, + ipl_upload_base: u16, + smp_a: u8, + smp_x: u8, + smp_y: u8, + smp_sp: u8, + smp_psw: u8, + smp_pc: u16, + smp_running: bool, + smp_entry_delay_cpu_cycles: u8, + audio_accumulator: u64, + smp_instruction_accumulator: u32, + dsp_voices: [DspVoice; DSP_VOICE_COUNT], +} + +impl Apu { + pub(crate) fn new() -> Self { + Self { + ram: Box::new([0; APU_RAM_LEN]), + cpu_to_apu_ports: [0; APU_PORT_COUNT], + apu_to_cpu_ports: [0; APU_PORT_COUNT], + dsp_address: 0, + dsp_registers: [0; DSP_REGISTER_COUNT], + aux_io: [0; 2], + control: 0xB0, + timers: [SmpTimer::default(); SMP_TIMER_COUNT], + ipl_state: IplState::WaitingForInitialKick, + ipl_upload_base: 0, + smp_a: 0, + smp_x: 0, + smp_y: 0, + smp_sp: 0xEF, + smp_psw: SMP_FLAG_Z, + smp_pc: SMP_IPL_ROM_START, + smp_running: true, + smp_entry_delay_cpu_cycles: 0, + audio_accumulator: 0, + smp_instruction_accumulator: 0, + dsp_voices: [DspVoice::default(); DSP_VOICE_COUNT], + } + } + + pub(crate) fn reset(&mut self) { + *self = Self::new(); + } + + pub(crate) fn read_cpu_port(&self, offset: u16) -> u8 { + self.apu_to_cpu_ports[apu_port_index(offset)] + } + + pub(crate) fn peek_cpu_port(&self, offset: u16) -> u8 { + self.read_cpu_port(offset) + } + + pub(crate) fn write_cpu_port(&mut self, offset: u16, value: u8) { + let port = apu_port_index(offset); + self.cpu_to_apu_ports[port] = value; + + if port == 0 { + self.handle_ipl_port0_write(value); + } + } + + pub(crate) fn read_smp(&mut self, address: u16) -> u8 { + if self.control & SMP_CONTROL_ENABLE_IPL_ROM != 0 && address >= SMP_IPL_ROM_START { + return SMP_IPL_ROM[usize::from(address - SMP_IPL_ROM_START)]; + } + + match address { + 0x00F0..=0x00F1 => 0, + 0x00F2 => self.dsp_address, + 0x00F3 => self.dsp_registers[usize::from(self.dsp_address & 0x7F)], + 0x00F4..=0x00F7 => self.cpu_to_apu_ports[usize::from(address - 0x00F4)], + 0x00F8..=0x00F9 => self.aux_io[usize::from(address - 0x00F8)], + 0x00FA..=0x00FC => 0, + 0x00FD..=0x00FF => self.timers[usize::from(address - 0x00FD)].read_output(), + _ => self.ram[usize::from(address)], + } + } + + fn peek_smp(&self, address: u16) -> u8 { + if self.control & SMP_CONTROL_ENABLE_IPL_ROM != 0 && address >= SMP_IPL_ROM_START { + return SMP_IPL_ROM[usize::from(address - SMP_IPL_ROM_START)]; + } + + match address { + 0x00F0..=0x00F1 => 0, + 0x00F2 => self.dsp_address, + 0x00F3 => self.dsp_registers[usize::from(self.dsp_address & 0x7F)], + 0x00F4..=0x00F7 => self.cpu_to_apu_ports[usize::from(address - 0x00F4)], + 0x00F8..=0x00F9 => self.aux_io[usize::from(address - 0x00F8)], + 0x00FA..=0x00FC => 0, + 0x00FD..=0x00FF => self.timers[usize::from(address - 0x00FD)].output & 0x0F, + _ => self.ram[usize::from(address)], + } + } + + pub(crate) fn write_smp(&mut self, address: u16, value: u8) { + match address { + 0x00F1 => self.write_smp_control(value), + 0x00F2 => self.dsp_address = value, + 0x00F3 if self.dsp_address < 0x80 => self.write_dsp_register(self.dsp_address, value), + 0x00F3 => {} + 0x00F4..=0x00F7 => { + self.ram[usize::from(address)] = value; + self.apu_to_cpu_ports[usize::from(address - 0x00F4)] = value; + } + 0x00F8..=0x00F9 => { + self.aux_io[usize::from(address - 0x00F8)] = value; + } + 0x00FA..=0x00FC => { + self.timers[usize::from(address - 0x00FA)].target = value; + } + 0x00FD..=0x00FF => {} + _ => self.ram[usize::from(address)] = value, + } + } + + fn write_dsp_register(&mut self, address: u8, value: u8) { + let register = usize::from(address & 0x7F); + self.dsp_registers[register] = value; + match register { + DSP_KEY_ON => self.key_on_voices(value), + DSP_KEY_OFF => self.key_off_voices(value), + DSP_FLAGS if value & 0x80 != 0 => { + for voice in &mut self.dsp_voices { + voice.active = false; + } + } + _ => {} + } + } + + pub(crate) fn mix_audio_for_cpu_cycles( + &mut self, + cycles: u32, + mixer: &mut M, + ) { + let sample_rate = u64::from(mixer.sample_rate()).max(1); + self.audio_accumulator = self + .audio_accumulator + .saturating_add(u64::from(cycles) * sample_rate); + while self.audio_accumulator >= SNES_NTSC_CPU_CLOCK_HZ { + self.audio_accumulator -= SNES_NTSC_CPU_CLOCK_HZ; + mixer.push(self.next_audio_sample(mixer.sample_rate())); + } + } + + fn next_audio_sample(&mut self, sample_rate: u32) -> f32 { + if self.dsp_registers[DSP_FLAGS] & DSP_FLAG_MUTE != 0 { + return 0.5; + } + + let registers = self.dsp_registers; + let ram = self.ram.as_ref(); + let master_left = signed_volume(registers[DSP_MASTER_VOLUME_LEFT]); + let master_right = signed_volume(registers[DSP_MASTER_VOLUME_RIGHT]); + let mut mixed = 0_i32; + + for (index, voice) in self.dsp_voices.iter_mut().enumerate() { + mixed += mix_voice( + index, + voice, + ®isters, + ram, + sample_rate, + master_left, + master_right, + ); + } + + let signed = (mixed as f32 / 32768.0).clamp(-1.0, 1.0); + signed.mul_add(0.5, 0.5) + } + + fn key_on_voices(&mut self, mask: u8) { + for voice_index in 0..DSP_VOICE_COUNT { + if mask & (1 << voice_index) == 0 { + continue; + } + + let base = voice_index * DSP_VOICE_REGISTER_STRIDE; + let directory = u16::from(self.dsp_registers[DSP_SOURCE_DIRECTORY]) << 8; + let source = u16::from(self.dsp_registers[base + 0x04]); + let entry = directory.wrapping_add(source.wrapping_mul(4)); + let start_addr = read_word(self.ram.as_ref(), entry); + let loop_addr = read_word(self.ram.as_ref(), entry.wrapping_add(2)); + let gain = self.dsp_registers[base + 0x07]; + let voice = &mut self.dsp_voices[voice_index]; + *voice = DspVoice { + active: true, + current_addr: start_addr, + loop_addr, + envelope: envelope_from_gain(gain), + ..DspVoice::default() + }; + decode_next_brr_block(self.ram.as_ref(), voice); + } + } + + fn key_off_voices(&mut self, mask: u8) { + for voice_index in 0..DSP_VOICE_COUNT { + if mask & (1 << voice_index) != 0 { + self.dsp_voices[voice_index].active = false; + } + } + } + + pub(crate) fn step_cpu_cycles(&mut self, mut cycles: u32) { + if cycles == 0 { + return; + } + + if self.smp_entry_delay_cpu_cycles > 0 { + let delayed_cycles = cycles.min(u32::from(self.smp_entry_delay_cpu_cycles)); + self.tick_timers(delayed_cycles); + self.smp_entry_delay_cpu_cycles -= delayed_cycles as u8; + cycles -= delayed_cycles; + if self.smp_entry_delay_cpu_cycles == 0 { + self.smp_running = true; + } + if cycles == 0 { + return; + } + } + + if !self.smp_running { + self.tick_timers(cycles); + return; + } + + self.tick_timers(cycles); + self.smp_instruction_accumulator = self + .smp_instruction_accumulator + .saturating_add(cycles.saturating_mul(SMP_CYCLE_UNITS_PER_CPU_CYCLE)); + + while self.smp_running { + let opcode = self.peek_smp(self.smp_pc); + let instruction_units = Self::smp_instruction_budget_units(self, opcode); + if self.smp_instruction_accumulator < instruction_units { + break; + } + + self.execute_smp_instruction(); + self.smp_instruction_accumulator = self + .smp_instruction_accumulator + .saturating_sub(instruction_units); + } + } + + fn handle_ipl_port0_write(&mut self, value: u8) { + match self.ipl_state { + IplState::WaitingForInitialKick => { + if value == IPL_INITIAL_KICK { + self.acknowledge_ipl_port0(value); + self.ipl_state = if self.cpu_to_apu_ports[1] == 0 { + self.start_smp_at_entry(); + IplState::Loaded + } else { + self.load_ipl_upload_base(); + self.smp_running = false; + IplState::Transferring { expected_index: 0 } + }; + } + } + IplState::Transferring { expected_index } => { + self.acknowledge_ipl_port0(value); + self.ipl_state = if value == expected_index { + self.store_ipl_upload_byte(value); + if value == u8::MAX { + self.increment_ipl_upload_page(); + } + IplState::Transferring { + expected_index: expected_index.wrapping_add(1), + } + } else if self.cpu_to_apu_ports[1] == 0 { + self.start_smp_at_entry(); + IplState::Loaded + } else { + self.load_ipl_upload_base(); + IplState::Transferring { expected_index: 0 } + }; + } + IplState::Loaded => {} + } + } + + fn acknowledge_ipl_port0(&mut self, value: u8) { + self.apu_to_cpu_ports[0] = value; + } + + fn write_smp_control(&mut self, value: u8) { + let previous = self.control; + self.control = value; + self.update_timer_enable(previous, value); + if value & SMP_CONTROL_RESET_PORTS_0_1 != 0 { + self.cpu_to_apu_ports[0] = 0; + self.cpu_to_apu_ports[1] = 0; + } + if value & SMP_CONTROL_RESET_PORTS_2_3 != 0 { + self.cpu_to_apu_ports[2] = 0; + self.cpu_to_apu_ports[3] = 0; + } + if value & SMP_CONTROL_ENABLE_IPL_ROM != 0 { + self.enter_ipl_loader(); + } + } + + fn enter_ipl_loader(&mut self) { + self.apu_to_cpu_ports = IPL_READY_PORTS; + self.ipl_state = IplState::WaitingForInitialKick; + self.smp_running = false; + self.smp_entry_delay_cpu_cycles = 0; + self.smp_instruction_accumulator = 0; + } + + fn update_timer_enable(&mut self, previous: u8, value: u8) { + for index in 0..SMP_TIMER_COUNT { + let mask = 1 << index; + if previous & mask == 0 && value & mask != 0 { + self.timers[index].reset_output_stages(); + } + } + } + + fn tick_timers(&mut self, cycles: u32) { + for index in 0..SMP_TIMER_COUNT { + let source_period = if index == 2 { + SMP_TIMER2_SOURCE_CPU_CYCLES + } else { + SMP_TIMER01_SOURCE_CPU_CYCLES + }; + self.timers[index].tick_cpu_cycles( + cycles, + source_period, + self.control & (1 << index) != 0, + ); + } + } + + fn load_ipl_upload_base(&mut self) { + self.ipl_upload_base = + u16::from(self.cpu_to_apu_ports[2]) | (u16::from(self.cpu_to_apu_ports[3]) << 8); + } + + fn store_ipl_upload_byte(&mut self, index: u8) { + let address = self.ipl_upload_base.wrapping_add(u16::from(index)); + self.ram[usize::from(address)] = self.cpu_to_apu_ports[1]; + } + + fn increment_ipl_upload_page(&mut self) { + self.ipl_upload_base = self.ipl_upload_base.wrapping_add(0x0100); + } + + fn start_smp_at_entry(&mut self) { + self.smp_pc = + u16::from(self.cpu_to_apu_ports[2]) | (u16::from(self.cpu_to_apu_ports[3]) << 8); + self.control &= !SMP_CONTROL_ENABLE_IPL_ROM; + self.smp_a = 0; + self.smp_x = 0; + self.smp_y = 0; + self.smp_sp = 0xEF; + self.smp_psw = SMP_FLAG_Z; + self.smp_running = false; + self.smp_entry_delay_cpu_cycles = SMP_IPL_ENTRY_DELAY_CPU_CYCLES; + } + + fn execute_smp_instruction(&mut self) { + let opcode = self.fetch_smp_byte(); + match opcode { + 0x00 => {} + 0x01 | 0x11 | 0x21 | 0x31 | 0x41 | 0x51 | 0x61 | 0x71 | 0x81 | 0x91 | 0xA1 | 0xB1 + | 0xC1 | 0xD1 | 0xE1 | 0xF1 => { + let vector = 0xFFDE - (u16::from(opcode >> 4) * 2); + let address = self.read_smp_word_at(vector); + self.call_smp_subroutine(address); + } + 0x02 | 0x22 | 0x42 | 0x62 | 0x82 | 0xA2 | 0xC2 | 0xE2 => { + self.set_direct_bit(opcode >> 5, true); + } + 0x03 | 0x23 | 0x43 | 0x63 | 0x83 | 0xA3 | 0xC3 | 0xE3 => { + self.branch_direct_bit(opcode >> 5, true); + } + 0x04 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.or_a(value); + } + 0x05 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.or_a(value); + } + 0x06 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.or_a(value); + } + 0x07 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.or_a(value); + } + 0x08 => { + let value = self.fetch_smp_byte(); + self.or_a(value); + } + 0x09 => { + let (address, left, right) = self.fetch_direct_source_dest_values(); + self.write_logical_result(address, left | right); + } + 0x0A => self.or1_c_bit(false), + 0x0B => { + let address = self.fetch_direct_address(); + self.modify_smp_memory(address, Self::asl_value); + } + 0x0C => { + let address = self.fetch_smp_word(); + self.modify_smp_memory(address, Self::asl_value); + } + 0x0D => self.push_smp_stack(self.smp_psw), + 0x0E => self.test_and_set_absolute(true), + 0x0F => self.brk_smp_interrupt(), + 0x10 => self.branch_relative(!self.flag(SMP_FLAG_N)), + 0x12 | 0x32 | 0x52 | 0x72 | 0x92 | 0xB2 | 0xD2 | 0xF2 => { + self.set_direct_bit(opcode >> 5, false); + } + 0x13 | 0x33 | 0x53 | 0x73 | 0x93 | 0xB3 | 0xD3 | 0xF3 => { + self.branch_direct_bit(opcode >> 5, false); + } + 0x14 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.or_a(value); + } + 0x15 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.or_a(value); + } + 0x16 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.or_a(value); + } + 0x17 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.or_a(value); + } + 0x18 => { + let (address, left, right) = self.fetch_direct_immediate_dest_value(); + self.write_logical_result(address, left | right); + } + 0x19 => { + let (address, left, right) = self.indexed_source_dest_values(); + self.write_logical_result(address, left | right); + } + 0x1A => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset).wrapping_sub(1); + self.write_direct_word(offset, value); + self.set_nz16(value); + } + 0x1B => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.modify_smp_memory(address, Self::asl_value); + } + 0x1C => self.smp_a = self.asl_value(self.smp_a), + 0x1F => { + let base = self.fetch_smp_word(); + self.smp_pc = self.read_smp_word_at(base.wrapping_add(u16::from(self.smp_x))); + } + 0x20 => self.set_flag(SMP_FLAG_P, false), + 0x2A => self.or1_c_bit(true), + 0x24 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.and_a(value); + } + 0x25 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.and_a(value); + } + 0x26 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.and_a(value); + } + 0x27 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.and_a(value); + } + 0x28 => { + let value = self.fetch_smp_byte(); + self.and_a(value); + } + 0x29 => { + let (address, left, right) = self.fetch_direct_source_dest_values(); + self.write_logical_result(address, left & right); + } + 0x2B => { + let address = self.fetch_direct_address(); + self.modify_smp_memory(address, Self::rol_value); + } + 0x2C => { + let address = self.fetch_smp_word(); + self.modify_smp_memory(address, Self::rol_value); + } + 0x2D => self.push_smp_stack(self.smp_a), + 0x2E => { + let address = self.fetch_direct_address(); + self.cbne(address); + } + 0x2F => self.branch_relative(true), + 0x30 => self.branch_relative(self.flag(SMP_FLAG_N)), + 0x34 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.and_a(value); + } + 0x35 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.and_a(value); + } + 0x36 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.and_a(value); + } + 0x37 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.and_a(value); + } + 0x38 => { + let (address, left, right) = self.fetch_direct_immediate_dest_value(); + self.write_logical_result(address, left & right); + } + 0x39 => { + let (address, left, right) = self.indexed_source_dest_values(); + self.write_logical_result(address, left & right); + } + 0x3A => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset).wrapping_add(1); + self.write_direct_word(offset, value); + self.set_nz16(value); + } + 0x3B => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.modify_smp_memory(address, Self::rol_value); + } + 0x3C => self.smp_a = self.rol_value(self.smp_a), + 0x3F => { + let address = self.fetch_smp_word(); + self.call_smp_subroutine(address); + } + 0x40 => self.set_flag(SMP_FLAG_P, true), + 0x4A => self.and1_c_bit(false), + 0x4E => self.test_and_set_absolute(false), + 0x44 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x45 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x46 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x47 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x48 => { + let value = self.fetch_smp_byte(); + self.eor_a(value); + } + 0x49 => { + let (address, left, right) = self.fetch_direct_source_dest_values(); + self.write_logical_result(address, left ^ right); + } + 0x4B => { + let address = self.fetch_direct_address(); + self.modify_smp_memory(address, Self::lsr_value); + } + 0x4C => { + let address = self.fetch_smp_word(); + self.modify_smp_memory(address, Self::lsr_value); + } + 0x4D => self.push_smp_stack(self.smp_x), + 0x4F => { + let offset = self.fetch_smp_byte(); + self.call_smp_subroutine(0xFF00 | u16::from(offset)); + } + 0x50 => self.branch_relative(!self.flag(SMP_FLAG_V)), + 0x54 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x55 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x56 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x57 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.eor_a(value); + } + 0x58 => { + let (address, left, right) = self.fetch_direct_immediate_dest_value(); + self.write_logical_result(address, left ^ right); + } + 0x59 => { + let (address, left, right) = self.indexed_source_dest_values(); + self.write_logical_result(address, left ^ right); + } + 0x5A => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset); + self.compare_16(self.ya(), value); + } + 0x5B => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.modify_smp_memory(address, Self::lsr_value); + } + 0x5C => self.smp_a = self.lsr_value(self.smp_a), + 0x5D => self.mov_x(self.smp_a), + 0x5F => { + let address = self.fetch_smp_word(); + self.smp_pc = address; + } + 0x60 => self.set_flag(SMP_FLAG_C, false), + 0x6A => self.and1_c_bit(true), + 0x6D => self.push_smp_stack(self.smp_y), + 0x6F => self.return_smp_subroutine(), + 0x64 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x65 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x66 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x67 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x68 => { + let value = self.fetch_smp_byte(); + self.compare_8(self.smp_a, value); + } + 0x69 => { + let (_, left, right) = self.fetch_direct_source_dest_values(); + self.compare_8(left, right); + } + 0x6B => { + let address = self.fetch_direct_address(); + self.modify_smp_memory(address, Self::ror_value); + } + 0x6C => { + let address = self.fetch_smp_word(); + self.modify_smp_memory(address, Self::ror_value); + } + 0x6E => { + let address = self.fetch_direct_address(); + self.dbnz_direct(address); + } + 0x70 => self.branch_relative(self.flag(SMP_FLAG_V)), + 0x74 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x75 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x76 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x77 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.compare_8(self.smp_a, value); + } + 0x78 => { + let value = self.fetch_smp_byte(); + let address = self.fetch_direct_address(); + let left = self.read_smp(address); + self.compare_8(left, value); + } + 0x79 => { + let (_, left, right) = self.indexed_source_dest_values(); + self.compare_8(left, right); + } + 0x7A => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset); + let result = self.addw_ya(value); + self.set_ya(result); + } + 0x7B => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.modify_smp_memory(address, Self::ror_value); + } + 0x7C => self.smp_a = self.ror_value(self.smp_a), + 0x7D => self.mov_a(self.smp_x), + 0x7F => { + self.smp_psw = self.pop_smp_stack(); + self.return_smp_subroutine(); + } + 0x80 => self.set_flag(SMP_FLAG_C, true), + 0x84 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x85 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x86 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x87 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x88 => { + let value = self.fetch_smp_byte(); + self.adc_a(value); + } + 0x89 => { + let (address, left, right) = self.fetch_direct_source_dest_values(); + let result = self.adc_values(left, right); + self.write_smp(address, result); + } + 0x8B => { + let address = self.fetch_direct_address(); + self.dec_smp_memory(address); + } + 0x8C => { + let address = self.fetch_smp_word(); + self.dec_smp_memory(address); + } + 0x8E => self.smp_psw = self.pop_smp_stack(), + 0x8D => { + let value = self.fetch_smp_byte(); + self.mov_y(value); + } + 0x8A => self.eor1_c_bit(), + 0x8F => { + let value = self.fetch_smp_byte(); + let address = self.fetch_direct_address(); + self.write_smp(address, value); + } + 0x90 => self.branch_relative(!self.flag(SMP_FLAG_C)), + 0x9C => { + self.smp_a = self.smp_a.wrapping_sub(1); + self.set_nz(self.smp_a); + } + 0x9D => self.mov_x(self.smp_sp), + 0x9E => self.div_ya_x(), + 0x9F => { + self.smp_a = self.smp_a.rotate_left(4); + self.set_nz(self.smp_a); + } + 0x94 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x9B => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.dec_smp_memory(address); + } + 0x95 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x96 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x97 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.adc_a(value); + } + 0x98 => { + let (address, left, right) = self.fetch_direct_immediate_dest_value(); + let result = self.adc_values(left, right); + self.write_smp(address, result); + } + 0x99 => { + let (address, left, right) = self.indexed_source_dest_values(); + let result = self.adc_values(left, right); + self.write_smp(address, result); + } + 0x9A => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset); + let result = self.subw_ya(value); + self.set_ya(result); + } + 0xA0 => self.set_flag(SMP_FLAG_I, true), + 0xA4 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xA5 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xA6 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xA7 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xA8 => { + let value = self.fetch_smp_byte(); + self.sbc_a(value); + } + 0xAA => self.mov1_c_bit(), + 0xA9 => { + let (address, left, right) = self.fetch_direct_source_dest_values(); + let result = self.sbc_values(left, right); + self.write_smp(address, result); + } + 0xAB => { + let address = self.fetch_direct_address(); + self.inc_smp_memory(address); + } + 0xAC => { + let address = self.fetch_smp_word(); + self.inc_smp_memory(address); + } + 0xB0 => self.branch_relative(self.flag(SMP_FLAG_C)), + 0xB4 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xBB => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.inc_smp_memory(address); + } + 0xBE => self.das_a(), + 0xB5 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xB6 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xB7 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.sbc_a(value); + } + 0xB8 => { + let (address, left, right) = self.fetch_direct_immediate_dest_value(); + let result = self.sbc_values(left, right); + self.write_smp(address, result); + } + 0xB9 => { + let (address, left, right) = self.indexed_source_dest_values(); + let result = self.sbc_values(left, right); + self.write_smp(address, result); + } + 0xBA => { + let offset = self.fetch_smp_byte(); + let value = self.read_direct_word(offset); + self.set_ya(value); + self.set_nz16(value); + } + 0xBF => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.smp_x = self.smp_x.wrapping_add(1); + self.mov_a(value); + } + 0xBC => { + self.smp_a = self.smp_a.wrapping_add(1); + self.set_nz(self.smp_a); + } + 0xBD => { + self.smp_sp = self.smp_x; + } + 0xC0 => self.set_flag(SMP_FLAG_I, false), + 0xCE => { + let value = self.pop_smp_stack(); + self.smp_x = value; + } + 0xC4 => { + let address = self.fetch_direct_address(); + self.write_smp(address, self.smp_a); + } + 0xC5 => { + let address = self.fetch_smp_word(); + self.write_smp(address, self.smp_a); + } + 0xC6 => { + let address = self.direct_address(self.smp_x); + self.write_smp(address, self.smp_a); + } + 0xC7 => { + let address = self.fetch_direct_indexed_indirect_address(); + self.write_smp(address, self.smp_a); + } + 0xC8 => { + let value = self.fetch_smp_byte(); + self.compare_8(self.smp_x, value); + } + 0xC9 => { + let address = self.fetch_smp_word(); + self.write_smp(address, self.smp_x); + } + 0xCA => self.mov1_bit_c(), + 0xCB => { + let address = self.fetch_direct_address(); + self.write_smp(address, self.smp_y); + } + 0xCC => { + let address = self.fetch_smp_word(); + self.write_smp(address, self.smp_y); + } + 0xCD => { + let value = self.fetch_smp_byte(); + self.mov_x(value); + } + 0xCF => self.mul_ya(), + 0xD0 => self.branch_relative(!self.flag(SMP_FLAG_Z)), + 0xD4 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.write_smp(address, self.smp_a); + } + 0xD5 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + self.write_smp(address, self.smp_a); + } + 0xD6 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + self.write_smp(address, self.smp_a); + } + 0xD7 => { + let address = self.fetch_direct_indirect_indexed_address(); + self.write_smp(address, self.smp_a); + } + 0xD8 => { + let address = self.fetch_direct_address(); + self.write_smp(address, self.smp_x); + } + 0xD9 => { + let address = self.fetch_direct_indexed_address(self.smp_y); + self.write_smp(address, self.smp_x); + } + 0xDA => { + let offset = self.fetch_smp_byte(); + self.write_direct_word(offset, self.ya()); + } + 0xDB => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.write_smp(address, self.smp_y); + } + 0xDC => { + self.smp_y = self.smp_y.wrapping_sub(1); + self.set_nz(self.smp_y); + } + 0xDD => self.mov_a(self.smp_y), + 0xDE => { + let address = self.fetch_direct_indexed_address(self.smp_x); + self.cbne(address); + } + 0xDF => self.daa_a(), + 0xE0 => { + self.set_flag(SMP_FLAG_V, false); + self.set_flag(SMP_FLAG_H, false); + } + 0xE4 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xE5 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xE6 => { + let address = self.direct_address(self.smp_x); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xE7 => { + let address = self.fetch_direct_indexed_indirect_address(); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xE8 => { + let value = self.fetch_smp_byte(); + self.mov_a(value); + } + 0xE9 => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.mov_x(value); + } + 0xEA => self.not1_bit(), + 0xEB => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.mov_y(value); + } + 0xEC => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.mov_y(value); + } + 0xED => self.set_flag(SMP_FLAG_C, !self.flag(SMP_FLAG_C)), + 0xEE => { + let value = self.pop_smp_stack(); + self.smp_y = value; + } + 0xEF | 0xFF => self.smp_running = false, + 0xF0 => self.branch_relative(self.flag(SMP_FLAG_Z)), + 0xF4 => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xF5 => { + let address = self.fetch_absolute_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xF6 => { + let address = self.fetch_absolute_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xF7 => { + let address = self.fetch_direct_indirect_indexed_address(); + let value = self.read_smp(address); + self.mov_a(value); + } + 0xF8 => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.mov_x(value); + } + 0xF9 => { + let address = self.fetch_direct_indexed_address(self.smp_y); + let value = self.read_smp(address); + self.mov_x(value); + } + 0xFA => { + let (address, _, value) = self.fetch_direct_source_dest_values(); + self.write_smp(address, value); + } + 0xFB => { + let address = self.fetch_direct_indexed_address(self.smp_x); + let value = self.read_smp(address); + self.mov_y(value); + } + 0xFC => { + self.smp_y = self.smp_y.wrapping_add(1); + self.set_nz(self.smp_y); + } + 0xFD => self.mov_y(self.smp_a), + 0xFE => self.dbnz_y(), + 0x1D => { + self.smp_x = self.smp_x.wrapping_sub(1); + self.set_nz(self.smp_x); + } + 0x3D => { + self.smp_x = self.smp_x.wrapping_add(1); + self.set_nz(self.smp_x); + } + 0x7E => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.compare_8(self.smp_y, value); + } + 0xAD => { + let value = self.fetch_smp_byte(); + self.compare_8(self.smp_y, value); + } + 0xAE => { + let value = self.pop_smp_stack(); + self.smp_a = value; + } + 0xAF => { + let address = self.direct_address(self.smp_x); + self.write_smp(address, self.smp_a); + self.smp_x = self.smp_x.wrapping_add(1); + } + 0x1E => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.compare_8(self.smp_x, value); + } + 0x3E => { + let address = self.fetch_direct_address(); + let value = self.read_smp(address); + self.compare_8(self.smp_x, value); + } + 0x5E => { + let address = self.fetch_smp_word(); + let value = self.read_smp(address); + self.compare_8(self.smp_y, value); + } + } + } + + fn smp_instruction_budget_units(&self, opcode: u8) -> u32 { + Self::smp_instruction_cycles(self, opcode).saturating_mul(SMP_CYCLE_UNITS_PER_SMP_CYCLE) + } + + fn smp_instruction_cycles(&self, opcode: u8) -> u32 { + match opcode { + 0x00 => 2, + 0x01 | 0x11 | 0x21 | 0x31 | 0x41 | 0x51 | 0x61 | 0x71 | 0x81 | 0x91 | 0xA1 | 0xB1 + | 0xC1 | 0xD1 | 0xE1 | 0xF1 => 8, + 0x02 | 0x12 | 0x22 | 0x32 | 0x42 | 0x52 | 0x62 | 0x72 | 0x82 | 0x92 | 0xA2 | 0xB2 + | 0xC2 | 0xD2 | 0xE2 | 0xF2 => 4, + 0x03 | 0x13 | 0x23 | 0x33 | 0x43 | 0x53 | 0x63 | 0x73 | 0x83 | 0x93 | 0xA3 | 0xB3 + | 0xC3 | 0xD3 | 0xE3 | 0xF3 => { + let bit_set = matches!( + opcode, + 0x03 | 0x23 | 0x43 | 0x63 | 0x83 | 0xA3 | 0xC3 | 0xE3 + ); + let (address, bit) = self.peek_absolute_bit_address(); + let value = self.peek_smp(address); + let condition = if bit_set { + value & (1 << bit) != 0 + } else { + value & (1 << bit) == 0 + }; + if condition { 7 } else { 5 } + } + 0x04 | 0x24 | 0x44 | 0x64 | 0x84 | 0xA4 | 0xC4 | 0xE4 => 3, + 0x05 | 0x25 | 0x45 | 0x65 | 0x85 | 0xA5 | 0xC5 | 0xE5 => 4, + 0x06 | 0x26 | 0x46 | 0x66 | 0x86 | 0xA6 | 0xC6 | 0xE6 => 3, + 0x07 | 0x27 | 0x47 | 0x67 | 0x87 | 0xA7 | 0xC7 | 0xE7 => 6, + 0x08 | 0x28 | 0x48 | 0x68 | 0x88 | 0xA8 | 0xC8 | 0xE8 => 2, + 0x09 | 0x29 | 0x49 | 0x69 | 0x89 | 0xA9 | 0xC9 | 0xE9 => 5, + 0x0A | 0x4A | 0x6A | 0x8A | 0xAA | 0xCA => 4, + 0x0B | 0x2B | 0x4B | 0x6B | 0x8B | 0xAB | 0xBB => 4, + 0x0C | 0x2C | 0x4C | 0x6C | 0x8C | 0xAC | 0xBC => 5, + 0x0D | 0x2D | 0x4D | 0x6D | 0x8D | 0xAE | 0xEE => 4, + 0x0E | 0x4E => 6, + 0x0F => 8, + 0x10 | 0x30 | 0x50 | 0x70 | 0x90 | 0xB0 | 0xD0 | 0xF0 + if self.branch_condition(opcode) => + { + 4 + } + 0x14 | 0x15 | 0x16 | 0x17 | 0x34 | 0x35 | 0x36 | 0x37 | 0x54 | 0x55 | 0x56 | 0x57 + | 0x74 | 0x75 | 0x76 | 0x77 | 0x94 | 0x95 | 0x96 | 0x97 | 0xB4 | 0xB5 | 0xB6 | 0xB7 + | 0xD4 | 0xD5 | 0xD6 | 0xD7 | 0xF4 | 0xF5 | 0xF6 | 0xF7 => 4, + 0x18 | 0x19 | 0x38 | 0x39 | 0x58 | 0x59 | 0x78 | 0x79 | 0x98 | 0x99 | 0xB8 | 0xB9 => 5, + 0x1A | 0x3A => 6, + 0x1B | 0x3B | 0x5B | 0x7B => 5, + 0x1C | 0x3C | 0x5C | 0x7C | 0x9C | 0xDC | 0xFC | 0x1D | 0x3D | 0x5D | 0x7D | 0x9D + | 0xBD | 0xDD | 0xFD | 0xBF | 0xCE => 2, + 0x1E | 0x3E | 0x5E => 4, + 0x1F | 0x5F => 3, + 0x20 | 0x40 | 0x60 | 0x80 | 0xA0 | 0xC0 | 0xE0 | 0xED => 2, + 0x2E | 0xDE => { + let address = if opcode == 0x2E { + self.peek_direct_address() + } else { + self.peek_direct_indexed_address(self.smp_x) + }; + let value = self.peek_smp(address); + if value != self.smp_a { 7 } else { 5 } + } + 0x2F => 4, + 0x3F => 8, + 0x4F => 6, + 0x6F => 5, + 0x7F => 6, + 0x8F | 0xAF | 0xFA => 5, + 0x9A | 0xBA => 5, + 0x9E => 12, + 0x9F => 5, + 0xCF => 9, + 0xAD => 2, + 0xBE => 3, + 0xDF => 3, + 0x6E => { + let address = self.peek_direct_address(); + let value = self.peek_smp(address).wrapping_sub(1); + if value != 0 { 7 } else { 5 } + } + 0xFE => { + if self.smp_y.wrapping_sub(1) != 0 { + 6 + } else { + 4 + } + } + 0xEF | 0xFF => 2, + _ => 2, + } + } + + fn branch_condition(&self, opcode: u8) -> bool { + match opcode { + 0x10 => !self.flag(SMP_FLAG_N), + 0x30 => self.flag(SMP_FLAG_N), + 0x50 => !self.flag(SMP_FLAG_V), + 0x70 => self.flag(SMP_FLAG_V), + 0x90 => !self.flag(SMP_FLAG_C), + 0xB0 => self.flag(SMP_FLAG_C), + 0xD0 => !self.flag(SMP_FLAG_Z), + 0xF0 => self.flag(SMP_FLAG_Z), + _ => false, + } + } + + fn peek_absolute_bit_address(&self) -> (u16, u8) { + let low = u16::from(self.peek_smp(self.smp_pc.wrapping_add(1))); + let high = u16::from(self.peek_smp(self.smp_pc.wrapping_add(2))); + let operand = low | (high << 8); + let address = operand & 0x1FFF; + let bit = (operand >> 13) as u8; + (address, bit) + } + + fn peek_direct_address(&self) -> u16 { + self.direct_address(self.peek_smp(self.smp_pc.wrapping_add(1))) + } + + fn peek_direct_indexed_address(&self, index: u8) -> u16 { + self.direct_address( + self.peek_smp(self.smp_pc.wrapping_add(1)) + .wrapping_add(index), + ) + } + + fn fetch_smp_byte(&mut self) -> u8 { + let value = self.read_smp(self.smp_pc); + self.smp_pc = self.smp_pc.wrapping_add(1); + value + } + + fn fetch_smp_word(&mut self) -> u16 { + let low = u16::from(self.fetch_smp_byte()); + let high = u16::from(self.fetch_smp_byte()); + low | (high << 8) + } + + fn fetch_absolute_bit_address(&mut self) -> (u16, u8) { + let operand = self.fetch_smp_word(); + let address = operand & 0x1FFF; + let bit = (operand >> 13) as u8; + (address, bit) + } + + fn read_smp_word_at(&mut self, address: u16) -> u16 { + let low = u16::from(self.read_smp(address)); + let high = u16::from(self.read_smp(address.wrapping_add(1))); + low | (high << 8) + } + + fn read_direct_word(&mut self, offset: u8) -> u16 { + let low = u16::from(self.read_smp(self.direct_address(offset))); + let high = u16::from(self.read_smp(self.direct_address(offset.wrapping_add(1)))); + low | (high << 8) + } + + fn write_direct_word(&mut self, offset: u8, value: u16) { + let [low, high] = value.to_le_bytes(); + self.write_smp(self.direct_address(offset), low); + self.write_smp(self.direct_address(offset.wrapping_add(1)), high); + } + + fn fetch_direct_address(&mut self) -> u16 { + let offset = self.fetch_smp_byte(); + self.direct_address(offset) + } + + fn fetch_direct_indexed_address(&mut self, index: u8) -> u16 { + let offset = self.fetch_smp_byte(); + self.direct_address(offset.wrapping_add(index)) + } + + fn fetch_absolute_indexed_address(&mut self, index: u8) -> u16 { + let base = self.fetch_smp_word(); + base.wrapping_add(u16::from(index)) + } + + fn fetch_direct_indexed_indirect_address(&mut self) -> u16 { + let offset = self.fetch_smp_byte().wrapping_add(self.smp_x); + self.read_direct_word(offset) + } + + fn fetch_direct_indirect_indexed_address(&mut self) -> u16 { + let offset = self.fetch_smp_byte(); + self.read_direct_word(offset) + .wrapping_add(u16::from(self.smp_y)) + } + + fn fetch_direct_source_dest_values(&mut self) -> (u16, u8, u8) { + let source_address = self.fetch_direct_address(); + let dest_address = self.fetch_direct_address(); + let source = self.read_smp(source_address); + let dest = self.read_smp(dest_address); + (dest_address, dest, source) + } + + fn fetch_direct_immediate_dest_value(&mut self) -> (u16, u8, u8) { + let value = self.fetch_smp_byte(); + let dest_address = self.fetch_direct_address(); + let dest = self.read_smp(dest_address); + (dest_address, dest, value) + } + + fn indexed_source_dest_values(&mut self) -> (u16, u8, u8) { + let source_address = self.direct_address(self.smp_y); + let dest_address = self.direct_address(self.smp_x); + let source = self.read_smp(source_address); + let dest = self.read_smp(dest_address); + (dest_address, dest, source) + } + + fn direct_address(&self, offset: u8) -> u16 { + u16::from(offset) | if self.flag(SMP_FLAG_P) { 0x0100 } else { 0 } + } + + fn branch_relative(&mut self, condition: bool) { + let offset = self.fetch_smp_byte() as i8; + if condition { + self.apply_relative_offset(offset); + } + } + + fn apply_relative_offset(&mut self, offset: i8) { + self.smp_pc = ((i32::from(self.smp_pc) + i32::from(offset)) & 0xFFFF) as u16; + } + + fn call_smp_subroutine(&mut self, address: u16) { + let [return_low, return_high] = self.smp_pc.to_le_bytes(); + self.push_smp_stack(return_high); + self.push_smp_stack(return_low); + self.smp_pc = address; + } + + fn return_smp_subroutine(&mut self) { + let low = self.pop_smp_stack(); + let high = self.pop_smp_stack(); + self.smp_pc = u16::from_le_bytes([low, high]); + } + + fn brk_smp_interrupt(&mut self) { + let [return_low, return_high] = self.smp_pc.to_le_bytes(); + let old_psw = self.smp_psw; + self.push_smp_stack(return_high); + self.push_smp_stack(return_low); + self.push_smp_stack(old_psw); + self.set_flag(SMP_FLAG_B, true); + self.set_flag(SMP_FLAG_I, false); + self.smp_pc = self.read_smp_word_at(0xFFDE); + } + + fn push_smp_stack(&mut self, value: u8) { + let address = 0x0100 | u16::from(self.smp_sp); + self.write_smp(address, value); + self.smp_sp = self.smp_sp.wrapping_sub(1); + } + + fn pop_smp_stack(&mut self) -> u8 { + self.smp_sp = self.smp_sp.wrapping_add(1); + let address = 0x0100 | u16::from(self.smp_sp); + self.read_smp(address) + } + + fn mov_a(&mut self, value: u8) { + self.smp_a = value; + self.set_nz(value); + } + + fn mov_x(&mut self, value: u8) { + self.smp_x = value; + self.set_nz(value); + } + + fn mov_y(&mut self, value: u8) { + self.smp_y = value; + self.set_nz(value); + } + + fn ya(&self) -> u16 { + u16::from_le_bytes([self.smp_a, self.smp_y]) + } + + fn set_ya(&mut self, value: u16) { + let [low, high] = value.to_le_bytes(); + self.smp_a = low; + self.smp_y = high; + } + + fn inc_smp_memory(&mut self, address: u16) { + let value = self.read_smp(address).wrapping_add(1); + self.write_smp(address, value); + self.set_nz(value); + } + + fn dec_smp_memory(&mut self, address: u16) { + let value = self.read_smp(address).wrapping_sub(1); + self.write_smp(address, value); + self.set_nz(value); + } + + fn modify_smp_memory(&mut self, address: u16, operation: fn(&mut Self, u8) -> u8) { + let current = self.read_smp(address); + let value = operation(self, current); + self.write_smp(address, value); + } + + fn absolute_bit_value(&mut self, inverted: bool) -> bool { + let (address, bit) = self.fetch_absolute_bit_address(); + let bit_set = self.read_smp(address) & (1u8 << bit) != 0; + bit_set ^ inverted + } + + fn or1_c_bit(&mut self, inverted: bool) { + let result = self.flag(SMP_FLAG_C) | self.absolute_bit_value(inverted); + self.set_flag(SMP_FLAG_C, result); + } + + fn and1_c_bit(&mut self, inverted: bool) { + let result = self.flag(SMP_FLAG_C) & self.absolute_bit_value(inverted); + self.set_flag(SMP_FLAG_C, result); + } + + fn eor1_c_bit(&mut self) { + let result = self.flag(SMP_FLAG_C) ^ self.absolute_bit_value(false); + self.set_flag(SMP_FLAG_C, result); + } + + fn mov1_c_bit(&mut self) { + let value = self.absolute_bit_value(false); + self.set_flag(SMP_FLAG_C, value); + } + + fn mov1_bit_c(&mut self) { + let (address, bit) = self.fetch_absolute_bit_address(); + let mask = 1u8 << bit; + let value = if self.flag(SMP_FLAG_C) { + self.read_smp(address) | mask + } else { + self.read_smp(address) & !mask + }; + self.write_smp(address, value); + } + + fn not1_bit(&mut self) { + let (address, bit) = self.fetch_absolute_bit_address(); + let value = self.read_smp(address) ^ (1u8 << bit); + self.write_smp(address, value); + } + + fn set_direct_bit(&mut self, bit: u8, enabled: bool) { + let address = self.fetch_direct_address(); + let mask = 1u8 << bit; + let value = if enabled { + self.read_smp(address) | mask + } else { + self.read_smp(address) & !mask + }; + self.write_smp(address, value); + } + + fn branch_direct_bit(&mut self, bit: u8, branch_when_set: bool) { + let address = self.fetch_direct_address(); + let offset = self.fetch_smp_byte() as i8; + let bit_set = self.read_smp(address) & (1u8 << bit) != 0; + if bit_set == branch_when_set { + self.apply_relative_offset(offset); + } + } + + fn cbne(&mut self, address: u16) { + let offset = self.fetch_smp_byte() as i8; + if self.read_smp(address) != self.smp_a { + self.apply_relative_offset(offset); + } + } + + fn dbnz_direct(&mut self, address: u16) { + let offset = self.fetch_smp_byte() as i8; + let value = self.read_smp(address).wrapping_sub(1); + self.write_smp(address, value); + if value != 0 { + self.apply_relative_offset(offset); + } + } + + fn dbnz_y(&mut self) { + let offset = self.fetch_smp_byte() as i8; + self.smp_y = self.smp_y.wrapping_sub(1); + if self.smp_y != 0 { + self.apply_relative_offset(offset); + } + } + + fn mul_ya(&mut self) { + let result = u16::from(self.smp_y) * u16::from(self.smp_a); + let [low, high] = result.to_le_bytes(); + self.smp_a = low; + self.smp_y = high; + self.set_nz(high); + } + + fn div_ya_x(&mut self) { + let dividend = u16::from_be_bytes([self.smp_y, self.smp_a]); + let divisor = u16::from(self.smp_x); + self.set_flag(SMP_FLAG_H, (self.smp_y & 0x0F) >= (self.smp_x & 0x0F)); + self.set_flag(SMP_FLAG_V, self.smp_y >= self.smp_x); + + let (quotient, remainder) = if u16::from(self.smp_y) < divisor * 2 { + (dividend / divisor, dividend % divisor) + } else { + let adjusted = dividend.wrapping_sub(divisor.wrapping_mul(0x0200)); + let adjusted_divisor = 0x0100 - divisor; + ( + 0x00FF_u16.wrapping_sub(adjusted / adjusted_divisor), + divisor + (adjusted % adjusted_divisor), + ) + }; + self.smp_a = quotient as u8; + self.smp_y = remainder as u8; + self.set_nz(self.smp_a); + } + + fn daa_a(&mut self) { + let mut result = self.smp_a; + if result > 0x99 || self.flag(SMP_FLAG_C) { + result = result.wrapping_add(0x60); + self.set_flag(SMP_FLAG_C, true); + } + if (result & 0x0F) > 0x09 || self.flag(SMP_FLAG_H) { + result = result.wrapping_add(0x06); + } + self.smp_a = result; + self.set_nz(result); + } + + fn das_a(&mut self) { + let mut result = self.smp_a; + if result > 0x99 || !self.flag(SMP_FLAG_C) { + result = result.wrapping_sub(0x60); + self.set_flag(SMP_FLAG_C, false); + } + if (result & 0x0F) > 0x09 || !self.flag(SMP_FLAG_H) { + result = result.wrapping_sub(0x06); + } + self.smp_a = result; + self.set_nz(result); + } + + fn test_and_set_absolute(&mut self, set_bits: bool) { + let address = self.fetch_smp_word(); + let memory = self.read_smp(address); + self.set_nz(self.smp_a.wrapping_sub(memory)); + let value = if set_bits { + memory | self.smp_a + } else { + memory & !self.smp_a + }; + self.write_smp(address, value); + } + + fn compare_8(&mut self, left: u8, right: u8) { + let result = left.wrapping_sub(right); + self.set_nz(result); + self.set_flag(SMP_FLAG_C, left >= right); + } + + fn compare_16(&mut self, left: u16, right: u16) { + let result = left.wrapping_sub(right); + self.set_nz16(result); + self.set_flag(SMP_FLAG_C, left >= right); + } + + fn write_logical_result(&mut self, address: u16, value: u8) { + self.write_smp(address, value); + self.set_nz(value); + } + + fn or_a(&mut self, value: u8) { + self.smp_a |= value; + self.set_nz(self.smp_a); + } + + fn and_a(&mut self, value: u8) { + self.smp_a &= value; + self.set_nz(self.smp_a); + } + + fn eor_a(&mut self, value: u8) { + self.smp_a ^= value; + self.set_nz(self.smp_a); + } + + fn asl_value(&mut self, value: u8) -> u8 { + let result = value << 1; + self.set_flag(SMP_FLAG_C, value & 0x80 != 0); + self.set_nz(result); + result + } + + fn lsr_value(&mut self, value: u8) -> u8 { + let result = value >> 1; + self.set_flag(SMP_FLAG_C, value & 0x01 != 0); + self.set_nz(result); + result + } + + fn rol_value(&mut self, value: u8) -> u8 { + let carry_in = u8::from(self.flag(SMP_FLAG_C)); + let result = (value << 1) | carry_in; + self.set_flag(SMP_FLAG_C, value & 0x80 != 0); + self.set_nz(result); + result + } + + fn ror_value(&mut self, value: u8) -> u8 { + let carry_in = if self.flag(SMP_FLAG_C) { 0x80 } else { 0 }; + let result = (value >> 1) | carry_in; + self.set_flag(SMP_FLAG_C, value & 0x01 != 0); + self.set_nz(result); + result + } + + fn adc_a(&mut self, value: u8) { + self.smp_a = self.adc_values(self.smp_a, value); + } + + fn adc_values(&mut self, left: u8, right: u8) -> u8 { + let carry = u16::from(self.flag(SMP_FLAG_C)); + let sum = u16::from(left) + u16::from(right) + carry; + let result = sum as u8; + self.set_nz(result); + self.set_flag(SMP_FLAG_C, sum > 0xFF); + self.set_flag( + SMP_FLAG_H, + ((left & 0x0F) + (right & 0x0F) + carry as u8) > 0x0F, + ); + self.set_flag(SMP_FLAG_V, (!(left ^ right) & (left ^ result) & 0x80) != 0); + result + } + + fn sbc_a(&mut self, value: u8) { + self.smp_a = self.sbc_values(self.smp_a, value); + } + + fn sbc_values(&mut self, left: u8, right: u8) -> u8 { + let carry = u16::from(self.flag(SMP_FLAG_C)); + let inverted = !right; + let sum = u16::from(left) + u16::from(inverted) + carry; + let result = sum as u8; + self.set_nz(result); + self.set_flag(SMP_FLAG_C, sum > 0xFF); + self.set_flag( + SMP_FLAG_H, + ((left & 0x0F) + (inverted & 0x0F) + carry as u8) > 0x0F, + ); + self.set_flag(SMP_FLAG_V, ((left ^ right) & (left ^ result) & 0x80) != 0); + result + } + + fn addw_ya(&mut self, value: u16) -> u16 { + let left = self.ya(); + let sum = u32::from(left) + u32::from(value); + let result = sum as u16; + self.set_nz16(result); + self.set_flag(SMP_FLAG_C, sum > 0xFFFF); + self.set_flag(SMP_FLAG_H, (left & 0x0FFF) + (value & 0x0FFF) > 0x0FFF); + self.set_flag( + SMP_FLAG_V, + (!(left ^ value) & (left ^ result) & 0x8000) != 0, + ); + result + } + + fn subw_ya(&mut self, value: u16) -> u16 { + let left = self.ya(); + let result = left.wrapping_sub(value); + self.set_nz16(result); + self.set_flag(SMP_FLAG_C, left >= value); + self.set_flag(SMP_FLAG_H, (left & 0x0FFF) >= (value & 0x0FFF)); + self.set_flag(SMP_FLAG_V, ((left ^ value) & (left ^ result) & 0x8000) != 0); + result + } + + fn set_nz(&mut self, value: u8) { + self.set_flag(SMP_FLAG_N, value & 0x80 != 0); + self.set_flag(SMP_FLAG_Z, value == 0); + } + + fn set_nz16(&mut self, value: u16) { + self.set_flag(SMP_FLAG_N, value & 0x8000 != 0); + self.set_flag(SMP_FLAG_Z, value == 0); + } + + fn flag(&self, mask: u8) -> bool { + self.smp_psw & mask != 0 + } + + fn set_flag(&mut self, mask: u8, enabled: bool) { + if enabled { + self.smp_psw |= mask; + } else { + self.smp_psw &= !mask; + } + } + + pub(crate) fn peek_ram(&self, address: u16) -> u8 { + self.ram[usize::from(address)] + } +} + +fn mix_voice( + index: usize, + voice: &mut DspVoice, + registers: &[u8; DSP_REGISTER_COUNT], + ram: &[u8; APU_RAM_LEN], + sample_rate: u32, + master_left: i32, + master_right: i32, +) -> i32 { + if !voice.active { + return 0; + } + + if voice.block_index >= 16 { + decode_next_brr_block(ram, voice); + if !voice.active { + return 0; + } + } + + let base = index * DSP_VOICE_REGISTER_STRIDE; + let raw = interpolated_voice_sample(voice, sample_rate.max(1)); + advance_voice_pitch(voice, ram, voice_pitch(registers, base), sample_rate.max(1)); + + let voice_left = i64::from(signed_volume(registers[base])); + let voice_right = i64::from(signed_volume(registers[base + 0x01])); + let master_left = i64::from(master_left); + let master_right = i64::from(master_right); + let env = i64::from(voice.envelope); + let raw = i64::from(raw); + let left = raw * voice_left * master_left * env / (128 * 128 * 0x07FF); + let right = raw * voice_right * master_right * env / (128 * 128 * 0x07FF); + ((left + right) / 2).clamp(i64::from(i16::MIN), i64::from(i16::MAX)) as i32 +} + +fn interpolated_voice_sample(voice: &DspVoice, sample_rate: u32) -> i32 { + let index = usize::from(voice.block_index.min(15)); + let current = i32::from(voice.block_samples[index]); + let next = i32::from( + voice + .block_samples + .get(index + 1) + .copied() + .unwrap_or(voice.block_samples[index]), + ); + let threshold = u64::from(sample_rate) * 0x1000; + let fraction = if threshold == 0 { + 0.0 + } else { + voice.pitch_phase as f32 / threshold as f32 + }; + (current as f32 + (next - current) as f32 * fraction).round() as i32 +} + +fn advance_voice_pitch( + voice: &mut DspVoice, + ram: &[u8; APU_RAM_LEN], + pitch: u16, + sample_rate: u32, +) { + let threshold = u64::from(sample_rate) * 0x1000; + voice.pitch_phase = voice + .pitch_phase + .saturating_add(u64::from(pitch.max(1)) * DSP_NATIVE_SAMPLE_RATE); + while voice.pitch_phase >= threshold { + voice.pitch_phase -= threshold; + advance_voice_sample(voice, ram); + if !voice.active { + break; + } + } +} + +fn advance_voice_sample(voice: &mut DspVoice, ram: &[u8; APU_RAM_LEN]) { + if voice.block_index < 15 { + voice.block_index += 1; + return; + } + + if voice.block_end && !voice.block_loop { + voice.active = false; + return; + } + if voice.block_end && voice.block_loop { + voice.current_addr = voice.loop_addr; + } + decode_next_brr_block(ram, voice); +} + +fn decode_next_brr_block(ram: &[u8; APU_RAM_LEN], voice: &mut DspVoice) { + let base = voice.current_addr; + let header = read_byte(ram, base); + let shift = header >> 4; + let filter = (header >> 2) & 0x03; + voice.block_end = header & 0x01 != 0; + voice.block_loop = header & 0x02 != 0; + for sample_index in 0..16 { + let packed = read_byte(ram, base.wrapping_add(1 + (sample_index / 2) as u16)); + let nibble = if sample_index & 1 == 0 { + packed >> 4 + } else { + packed & 0x0F + }; + let decoded = decode_brr_nibble(nibble, shift, filter, voice.prev1, voice.prev2); + voice.block_samples[sample_index] = decoded; + voice.prev2 = voice.prev1; + voice.prev1 = decoded; + } + voice.current_addr = base.wrapping_add(9); + voice.block_index = 0; +} + +fn decode_brr_nibble(nibble: u8, shift: u8, filter: u8, prev1: i16, prev2: i16) -> i16 { + let signed = i32::from(((nibble << 4) as i8) >> 4); + let shifted = if shift <= 12 { + signed << shift + } else if signed < 0 { + -0x8000 + } else { + 0 + }; + let prediction = match filter { + 0 => 0, + 1 => i32::from(prev1) * 15 / 16, + 2 => i32::from(prev1) * 61 / 32 - i32::from(prev2) * 15 / 16, + _ => i32::from(prev1) * 115 / 64 - i32::from(prev2) * 13 / 16, + }; + (shifted + prediction).clamp(i32::from(i16::MIN), i32::from(i16::MAX)) as i16 +} + +fn voice_pitch(registers: &[u8; DSP_REGISTER_COUNT], base: usize) -> u16 { + u16::from(registers[base + 0x02]) | (u16::from(registers[base + 0x03] & 0x3F) << 8) +} + +fn signed_volume(value: u8) -> i32 { + i32::from(i8::from_ne_bytes([value])) +} + +fn envelope_from_gain(gain: u8) -> u16 { + if gain & 0x80 == 0 && gain != 0 { + (u16::from(gain & 0x7F) << 4).min(0x07FF) + } else { + 0x07FF + } +} + +fn read_word(ram: &[u8; APU_RAM_LEN], address: u16) -> u16 { + u16::from(read_byte(ram, address)) | (u16::from(read_byte(ram, address.wrapping_add(1))) << 8) +} + +fn read_byte(ram: &[u8; APU_RAM_LEN], address: u16) -> u8 { + ram[usize::from(address)] +} + +fn apu_port_index(offset: u16) -> usize { + usize::from(offset & 0x0003) +} + +#[cfg(test)] +mod tests { + use super::{ + Apu, DSP_KEY_ON, DSP_SOURCE_DIRECTORY, SMP_FLAG_C, SMP_FLAG_N, SMP_FLAG_V, SMP_FLAG_Z, + }; + use nerust_sound_traits::MixerInput; + + #[derive(Default)] + struct CapturingMixer { + samples: Vec, + } + + impl MixerInput for CapturingMixer { + fn push(&mut self, data: f32) { + self.samples.push(data); + } + + fn sample_rate(&self) -> u32 { + 32_000 + } + } + + fn write_dsp(apu: &mut Apu, register: usize, value: u8) { + apu.write_smp(0x00F2, register as u8); + apu.write_smp(0x00F3, value); + } + + fn assert_opcode_cycles(apu: &Apu, opcode: u8, expected_cycles: u32) { + assert_eq!( + apu.smp_instruction_cycles(opcode), + expected_cycles, + "opcode {opcode:02X}" + ); + } + + fn assert_opcode_cycles_for_all(apu: &Apu, opcodes: &[u8], expected_cycles: u32) { + for &opcode in opcodes { + assert_opcode_cycles(apu, opcode, expected_cycles); + } + } + + #[test] + fn smp_instruction_cycles_match_fullsnes_table() { + let mut apu = Apu::new(); + + assert_opcode_cycles(&apu, 0x00, 2); + + assert_opcode_cycles_for_all( + &apu, + &[ + 0x01, 0x11, 0x21, 0x31, 0x41, 0x51, 0x61, 0x71, 0x81, 0x91, 0xA1, 0xB1, 0xC1, 0xD1, + 0xE1, 0xF1, + ], + 8, + ); + assert_opcode_cycles_for_all( + &apu, + &[ + 0x02, 0x12, 0x22, 0x32, 0x42, 0x52, 0x62, 0x72, 0x82, 0x92, 0xA2, 0xB2, 0xC2, 0xD2, + 0xE2, 0xF2, + ], + 4, + ); + + apu.smp_pc = 0x0000; + apu.ram[0x0001] = 0x34; + apu.ram[0x0002] = 0x00; + apu.smp_a = 0x40; + apu.ram[0x0034] = 0x01; + assert_opcode_cycles_for_all(&apu, &[0x03, 0x23, 0x43, 0x63, 0x83, 0xA3, 0xC3, 0xE3], 7); + apu.ram[0x0034] = 0x00; + assert_opcode_cycles_for_all(&apu, &[0x13, 0x33, 0x53, 0x73, 0x93, 0xB3, 0xD3, 0xF3], 7); + + assert_opcode_cycles_for_all(&apu, &[0x04, 0x24, 0x44, 0x64, 0x84, 0xA4, 0xC4, 0xE4], 3); + assert_opcode_cycles_for_all(&apu, &[0x05, 0x25, 0x45, 0x65, 0x85, 0xA5, 0xC5, 0xE5], 4); + assert_opcode_cycles_for_all(&apu, &[0x06, 0x26, 0x46, 0x66, 0x86, 0xA6, 0xC6, 0xE6], 3); + assert_opcode_cycles_for_all(&apu, &[0x07, 0x27, 0x47, 0x67, 0x87, 0xA7, 0xC7, 0xE7], 6); + assert_opcode_cycles_for_all(&apu, &[0x08, 0x28, 0x48, 0x68, 0x88, 0xA8, 0xC8, 0xE8], 2); + assert_opcode_cycles_for_all(&apu, &[0x09, 0x29, 0x49, 0x69, 0x89, 0xA9, 0xC9, 0xE9], 5); + assert_opcode_cycles_for_all(&apu, &[0x0A, 0x4A, 0x6A, 0x8A, 0xAA, 0xCA], 4); + assert_opcode_cycles_for_all(&apu, &[0x0B, 0x2B, 0x4B, 0x6B, 0x8B, 0xAB, 0xBB], 4); + assert_opcode_cycles_for_all(&apu, &[0x0C, 0x2C, 0x4C, 0x6C, 0x8C, 0xAC, 0xBC], 5); + assert_opcode_cycles_for_all(&apu, &[0x0D, 0x2D, 0x4D, 0x6D, 0x8D, 0xAE, 0xEE], 4); + assert_opcode_cycles_for_all(&apu, &[0x0E, 0x4E], 6); + assert_opcode_cycles(&apu, 0x0F, 8); + + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0x10, 4); + apu.smp_psw = SMP_FLAG_N; + assert_opcode_cycles(&apu, 0x10, 2); + apu.smp_psw = SMP_FLAG_N; + assert_opcode_cycles(&apu, 0x30, 4); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0x30, 2); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0x50, 4); + apu.smp_psw = SMP_FLAG_V; + assert_opcode_cycles(&apu, 0x50, 2); + apu.smp_psw = SMP_FLAG_V; + assert_opcode_cycles(&apu, 0x70, 4); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0x70, 2); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0x90, 4); + apu.smp_psw = SMP_FLAG_C; + assert_opcode_cycles(&apu, 0x90, 2); + apu.smp_psw = SMP_FLAG_C; + assert_opcode_cycles(&apu, 0xB0, 4); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0xB0, 2); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0xD0, 4); + apu.smp_psw = SMP_FLAG_Z; + assert_opcode_cycles(&apu, 0xD0, 2); + apu.smp_psw = 0; + assert_opcode_cycles(&apu, 0xF0, 2); + apu.smp_psw = SMP_FLAG_Z; + assert_opcode_cycles(&apu, 0xF0, 4); + + assert_opcode_cycles_for_all( + &apu, + &[ + 0x14, 0x15, 0x16, 0x17, 0x34, 0x35, 0x36, 0x37, 0x54, 0x55, 0x56, 0x57, 0x74, 0x75, + 0x76, 0x77, 0x94, 0x95, 0x96, 0x97, 0xB4, 0xB5, 0xB6, 0xB7, 0xD4, 0xD5, 0xD6, 0xD7, + 0xF4, 0xF5, 0xF6, 0xF7, + ], + 4, + ); + assert_opcode_cycles_for_all( + &apu, + &[ + 0x18, 0x19, 0x38, 0x39, 0x58, 0x59, 0x78, 0x79, 0x98, 0x99, 0xB8, 0xB9, + ], + 5, + ); + assert_opcode_cycles_for_all(&apu, &[0x1A, 0x3A], 6); + assert_opcode_cycles_for_all(&apu, &[0x1B, 0x3B, 0x5B, 0x7B], 5); + assert_opcode_cycles_for_all( + &apu, + &[ + 0x1C, 0x3C, 0x5C, 0x7C, 0x9C, 0xDC, 0xFC, 0x1D, 0x3D, 0x5D, 0x7D, 0x9D, 0xBD, 0xDD, + 0xFD, 0xBF, 0xCE, + ], + 2, + ); + assert_opcode_cycles_for_all(&apu, &[0x1E, 0x3E, 0x5E], 4); + assert_opcode_cycles_for_all(&apu, &[0x1F, 0x5F], 3); + assert_opcode_cycles_for_all(&apu, &[0x20, 0x40, 0x60, 0x80, 0xA0, 0xC0, 0xE0, 0xED], 2); + + apu.smp_pc = 0x0000; + apu.ram[0x0001] = 0x34; + apu.smp_a = 0x40; + apu.ram[0x0034] = 0x40; + assert_opcode_cycles(&apu, 0x2E, 5); + apu.ram[0x0034] = 0x41; + assert_opcode_cycles(&apu, 0x2E, 7); + + apu.smp_x = 0; + apu.ram[0x0034] = 0x40; + assert_opcode_cycles(&apu, 0xDE, 5); + apu.ram[0x0034] = 0x41; + assert_opcode_cycles(&apu, 0xDE, 7); + + assert_opcode_cycles(&apu, 0x2F, 4); + assert_opcode_cycles(&apu, 0x3F, 8); + assert_opcode_cycles(&apu, 0x4F, 6); + assert_opcode_cycles(&apu, 0x6F, 5); + assert_opcode_cycles(&apu, 0x7F, 6); + assert_opcode_cycles_for_all(&apu, &[0x8F, 0xAF, 0xFA], 5); + assert_opcode_cycles_for_all(&apu, &[0x9A, 0xBA], 5); + assert_opcode_cycles(&apu, 0x9E, 12); + assert_opcode_cycles(&apu, 0x9F, 5); + assert_opcode_cycles(&apu, 0xCF, 9); + assert_opcode_cycles(&apu, 0xAD, 2); + assert_opcode_cycles(&apu, 0xBE, 3); + assert_opcode_cycles(&apu, 0xDF, 3); + + apu.smp_pc = 0x0000; + apu.ram[0x0001] = 0x34; + apu.ram[0x0034] = 0x01; + assert_opcode_cycles(&apu, 0x6E, 5); + apu.ram[0x0034] = 0x02; + assert_opcode_cycles(&apu, 0x6E, 7); + + apu.smp_y = 0x01; + assert_opcode_cycles(&apu, 0xFE, 4); + apu.smp_y = 0x02; + assert_opcode_cycles(&apu, 0xFE, 6); + + assert_opcode_cycles_for_all(&apu, &[0xEF, 0xFF], 2); + } + + #[test] + fn keyed_brr_voice_produces_biased_audio_samples() { + let mut apu = Apu::new(); + let directory = 0x0100; + let sample = 0x0200; + apu.ram[directory] = sample as u8; + apu.ram[directory + 1] = (sample >> 8) as u8; + apu.ram[directory + 2] = sample as u8; + apu.ram[directory + 3] = (sample >> 8) as u8; + apu.ram[sample] = 0xC1; + for byte in &mut apu.ram[sample + 1..sample + 9] { + *byte = 0x1F; + } + + write_dsp(&mut apu, DSP_SOURCE_DIRECTORY, (directory >> 8) as u8); + write_dsp(&mut apu, 0x00, 0x7F); + write_dsp(&mut apu, 0x01, 0x7F); + write_dsp(&mut apu, 0x02, 0x00); + write_dsp(&mut apu, 0x03, 0x10); + write_dsp(&mut apu, 0x04, 0x00); + write_dsp(&mut apu, 0x07, 0x7F); + write_dsp(&mut apu, 0x0C, 0x7F); + write_dsp(&mut apu, 0x1C, 0x7F); + write_dsp(&mut apu, DSP_KEY_ON, 0x01); + + let mut mixer = CapturingMixer::default(); + apu.mix_audio_for_cpu_cycles(5_000, &mut mixer); + + assert!(mixer.samples.len() > 16); + assert!(mixer.samples.iter().any(|sample| *sample > 0.55)); + assert!(mixer.samples.iter().any(|sample| *sample < 0.45)); + } +} diff --git a/snes/core/src/bus.rs b/snes/core/src/bus.rs new file mode 100644 index 00000000..dd6a7fa6 --- /dev/null +++ b/snes/core/src/bus.rs @@ -0,0 +1,5521 @@ +use crate::apu::Apu; +use crate::{ + Cartridge, PresentedBackdropLine, PresentedBg1Line, PresentedColorWindowLine, + PresentedMainScreenLine, memory::Memory, ppu1::Ppu1, ppu2::Ppu2, +}; +use nerust_sound_traits::MixerInput; + +const ADDRESS_MASK: u32 = 0x00FF_FFFF; +const CPU_IO_REGISTER_COUNT: usize = 0x20; +const DMA_REGISTER_COUNT: usize = 0x80; +const DMA_CHANNEL_COUNT: usize = 8; +const VBLANK_STUB_SCANLINES: u16 = 262; +const VBLANK_STUB_SUBTICKS_PER_SCANLINE: u16 = 4; +const VBLANK_STUB_PERIOD: u16 = VBLANK_STUB_SCANLINES * VBLANK_STUB_SUBTICKS_PER_SCANLINE; +const MASTER_CLOCKS_PER_LINE: u32 = 1364; +const CPU_MASTER_CLOCKS_PER_CYCLE_FAST: u32 = 6; +const CPU_MASTER_CLOCKS_PER_CYCLE_SLOW: u32 = 8; +const VIDEO_MASTER_CLOCKS_PER_SUBTICK: u32 = + MASTER_CLOCKS_PER_LINE / (VBLANK_STUB_SUBTICKS_PER_SCANLINE as u32); +const VBLANK_STUB_ACTIVE_START_LINE: u16 = 225; +const AUTO_JOYPAD_START_SUBTICK: u16 = 1; +const AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS: u8 = 12; +const STANDARD_CONTROLLER_PORT_COUNT: usize = 2; +const STANDARD_CONTROLLER_PAYLOAD_BITS: u8 = 16; +const JOYSER1_STANDARD_HIGH_BITS: u8 = 0x1C; +const MATH_MULTIPLY_CYCLES: u8 = 8; +const MATH_DIVIDE_CYCLES: u8 = 16; +const WRMPYB_IN_FLIGHT_ZERO_CYCLE: u8 = 7; +#[cfg(test)] +const VBLANK_STUB_ACTIVE_START: u16 = + VBLANK_STUB_ACTIVE_START_LINE * VBLANK_STUB_SUBTICKS_PER_SCANLINE; +#[cfg(test)] +const AUTO_JOYPAD_START: u16 = VBLANK_STUB_ACTIVE_START + AUTO_JOYPAD_START_SUBTICK; +const HCOUNTER_DOTS_PER_LINE: u16 = 341; +const PRESENTED_SCANLINE_COUNT: usize = 224; + +#[derive(Clone, Copy)] +struct StandardControllerPort { + latched_buttons: u16, + serial_position: u8, +} + +impl Default for StandardControllerPort { + fn default() -> Self { + Self { + latched_buttons: 0, + serial_position: STANDARD_CONTROLLER_PAYLOAD_BITS, + } + } +} + +impl StandardControllerPort { + fn load_sample(&mut self, buttons: u16, serial_position: u8) { + self.latched_buttons = buttons; + self.serial_position = serial_position; + } + + fn read_serial_bit(&mut self) -> u8 { + let bit = self.peek_serial_bit(); + if self.serial_position < STANDARD_CONTROLLER_PAYLOAD_BITS { + self.serial_position += 1; + } + bit + } + + fn peek_serial_bit(&self) -> u8 { + if self.serial_position < STANDARD_CONTROLLER_PAYLOAD_BITS { + ((self.latched_buttons + >> (u16::from(STANDARD_CONTROLLER_PAYLOAD_BITS - 1) + - u16::from(self.serial_position))) + & 0x01) as u8 + } else { + 1 + } + } +} + +#[derive(Clone, Copy)] +enum MathPending { + Multiply { + cycles_remaining: u8, + result: u16, + }, + Divide { + cycles_remaining: u8, + quotient: u16, + remainder: u16, + }, +} + +pub(crate) trait CpuBus { + fn read(&mut self, addr: u32) -> u8; + fn write(&mut self, addr: u32, data: u8); + fn tick(&mut self); + fn tick_many(&mut self, cycles: u32); + fn peek_side_effect_free(&self, _addr: u32) -> Option { + None + } + fn has_pending_interrupt(&self) -> bool { + true + } + /// Returns `true` and clears the pending-NMI flag when an NMI is waiting + /// for the CPU to service. Returns `false` otherwise. + fn poll_nmi(&mut self) -> bool { + false + } + fn poll_irq(&mut self) -> bool { + false + } +} + +pub(crate) struct Bus { + cartridge: Cartridge, + pub(crate) memory: Memory, + pub(crate) ppu1: Ppu1, + pub(crate) ppu2: Ppu2, + apu: Apu, + cpu_io_registers: [u8; CPU_IO_REGISTER_COUNT], + dma_registers: [u8; DMA_REGISTER_COUNT], + video_phase: u16, + video_master_clock_accumulator: u32, + math_quotient: u16, + math_result: u16, + math_pending: Option, + /// RDNMI flag (bit 7 of $4210): set on vblank entry, cleared by reading $4210 + /// or automatically at the end of vblank. + nmi_flag: bool, + /// Pending NMI for the CPU: set when the NMI flag rises while NMI is enabled + /// in NMITIMEN (bit 7 of $4200), cleared when the CPU takes the interrupt. + nmi_pending: bool, + irq_flag: bool, + /// MEMSEL ($420D) bit 0: 0=2.68MHz (slow ROM), 1=3.58MHz (fast ROM) + memsel_fast: bool, + latched_hcounter: u16, + latched_vcounter: u16, + ophct_high_byte: bool, + opvct_high_byte: bool, + auto_joy_armed: bool, + auto_joy_active: bool, + auto_joy_subticks_remaining: u8, + joyout_latch_high: bool, + standard_controller_buttons: [u16; STANDARD_CONTROLLER_PORT_COUNT], + controller_ports: [StandardControllerPort; STANDARD_CONTROLLER_PORT_COUNT], + hdma_active_mask: u8, + hdma_ended_mask: u8, + /// Live HDMA current address / A2A ($43x8/$43x9). + hdma_table_addr: [u16; DMA_CHANNEL_COUNT], + hdma_data_addr: [u16; DMA_CHANNEL_COUNT], + hdma_data_bank: [u8; DMA_CHANNEL_COUNT], + hdma_line_counter: [u8; DMA_CHANNEL_COUNT], + hdma_repeat: [bool; DMA_CHANNEL_COUNT], + hdma_do_transfer: [bool; DMA_CHANNEL_COUNT], + hdma_indirect: [bool; DMA_CHANNEL_COUNT], + odd_frame: bool, + completed_odd_frame: bool, + presented_backdrop_current_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_backdrop_completed_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg1_current_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg1_completed_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg2_current_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg2_completed_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg3_current_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg3_completed_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg4_current_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_bg4_completed_lines: [Option; PRESENTED_SCANLINE_COUNT], + presented_main_screen_current_lines: + [Option; PRESENTED_SCANLINE_COUNT], + presented_main_screen_completed_lines: + [Option; PRESENTED_SCANLINE_COUNT], + presented_color_window_current_lines: + [Option; PRESENTED_SCANLINE_COUNT], + presented_color_window_completed_lines: + [Option; PRESENTED_SCANLINE_COUNT], +} + +impl Bus { + pub(crate) fn new(cartridge: Cartridge) -> Self { + Self { + cartridge, + memory: Memory::new(), + ppu1: Ppu1::new(), + ppu2: Ppu2::new(), + apu: Apu::new(), + cpu_io_registers: initial_cpu_io_registers(), + dma_registers: [0; DMA_REGISTER_COUNT], + video_phase: 0, + video_master_clock_accumulator: 0, + math_quotient: 0, + math_result: 0, + math_pending: None, + nmi_flag: false, + nmi_pending: false, + irq_flag: false, + memsel_fast: true, + latched_hcounter: 0, + latched_vcounter: 0, + ophct_high_byte: false, + opvct_high_byte: false, + auto_joy_armed: false, + auto_joy_active: false, + auto_joy_subticks_remaining: 0, + joyout_latch_high: false, + standard_controller_buttons: [0; STANDARD_CONTROLLER_PORT_COUNT], + controller_ports: [StandardControllerPort::default(); STANDARD_CONTROLLER_PORT_COUNT], + hdma_active_mask: 0, + hdma_ended_mask: 0, + hdma_table_addr: [0; DMA_CHANNEL_COUNT], + hdma_data_addr: [0; DMA_CHANNEL_COUNT], + hdma_data_bank: [0; DMA_CHANNEL_COUNT], + hdma_line_counter: [0; DMA_CHANNEL_COUNT], + hdma_repeat: [false; DMA_CHANNEL_COUNT], + hdma_do_transfer: [false; DMA_CHANNEL_COUNT], + hdma_indirect: [false; DMA_CHANNEL_COUNT], + odd_frame: false, + completed_odd_frame: false, + presented_backdrop_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_backdrop_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg1_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg1_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg2_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg2_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg3_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg3_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg4_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_bg4_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_main_screen_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_main_screen_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_color_window_current_lines: [None; PRESENTED_SCANLINE_COUNT], + presented_color_window_completed_lines: [None; PRESENTED_SCANLINE_COUNT], + } + } + + pub(crate) fn cartridge(&self) -> &Cartridge { + &self.cartridge + } + + pub(crate) fn cartridge_mut(&mut self) -> &mut Cartridge { + &mut self.cartridge + } + + pub(crate) fn reset_ephemeral_state(&mut self) { + self.video_phase = 0; + self.video_master_clock_accumulator = 0; + self.math_quotient = 0; + self.math_result = 0; + self.math_pending = None; + self.apu.reset(); + self.nmi_flag = false; + self.nmi_pending = false; + self.irq_flag = false; + self.memsel_fast = false; + self.cpu_io_registers[0x01] = 0xFF; + self.latched_hcounter = 0; + self.ophct_high_byte = false; + self.auto_joy_active = false; + self.joyout_latch_high = false; + self.controller_ports = [StandardControllerPort::default(); STANDARD_CONTROLLER_PORT_COUNT]; + self.hdma_active_mask = 0; + self.hdma_ended_mask = 0; + self.hdma_table_addr = [0; DMA_CHANNEL_COUNT]; + self.hdma_data_addr = [0; DMA_CHANNEL_COUNT]; + self.hdma_data_bank = [0; DMA_CHANNEL_COUNT]; + self.hdma_line_counter = [0; DMA_CHANNEL_COUNT]; + self.hdma_repeat = [false; DMA_CHANNEL_COUNT]; + self.hdma_do_transfer = [false; DMA_CHANNEL_COUNT]; + self.hdma_indirect = [false; DMA_CHANNEL_COUNT]; + self.odd_frame = false; + self.completed_odd_frame = false; + self.presented_backdrop_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_backdrop_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg1_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg1_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg2_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg2_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg3_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg3_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg4_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg4_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_main_screen_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_main_screen_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_color_window_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_color_window_completed_lines = [None; PRESENTED_SCANLINE_COUNT]; + } + + #[cfg(test)] + pub(crate) fn tick_video_stub(&mut self) { + self.advance_video_one_subtick(); + } + + pub(crate) fn tick_cpu_cycle(&mut self) { + self.step_cpu_cycles(1); + } + + pub(crate) fn step_cpu_cycles(&mut self, cycles: u32) { + if cycles == 0 { + return; + } + + self.tick_math_io(cycles); + self.apu.step_cpu_cycles(cycles); + + let total_master_clocks = u64::from(self.video_master_clock_accumulator) + + u64::from(cycles) * u64::from(self.cpu_master_clocks_per_cycle()); + let video_subticks = total_master_clocks / u64::from(VIDEO_MASTER_CLOCKS_PER_SUBTICK); + self.video_master_clock_accumulator = + (total_master_clocks % u64::from(VIDEO_MASTER_CLOCKS_PER_SUBTICK)) as u32; + for _ in 0..video_subticks { + self.advance_video_one_subtick(); + } + } + + pub(crate) fn mix_audio_for_cpu_cycles( + &mut self, + cycles: u32, + mixer: &mut M, + ) { + self.apu.mix_audio_for_cpu_cycles(cycles, mixer); + } + + pub(crate) fn next_event_cycles(&self) -> u32 { + let video_master_clocks_remaining = + VIDEO_MASTER_CLOCKS_PER_SUBTICK - self.video_master_clock_accumulator; + let video_cycles = + video_master_clocks_remaining.div_ceil(self.cpu_master_clocks_per_cycle()); + let math_cycles = self.math_pending_cycles().unwrap_or(u32::MAX); + + video_cycles.min(math_cycles).max(1) + } + + fn math_pending_cycles(&self) -> Option { + match self.math_pending { + Some(MathPending::Multiply { + cycles_remaining, .. + }) + | Some(MathPending::Divide { + cycles_remaining, .. + }) => Some(u32::from(cycles_remaining)), + None => None, + } + } + + fn tick_math_io(&mut self, cycles: u32) { + if cycles == 0 { + return; + } + + let Some(pending) = self.math_pending else { + return; + }; + self.math_pending = match pending { + MathPending::Multiply { + cycles_remaining, + result, + } if u32::from(cycles_remaining) <= cycles => { + self.math_result = result; + None + } + MathPending::Multiply { + cycles_remaining, + result, + } => Some(MathPending::Multiply { + cycles_remaining: (u32::from(cycles_remaining) - cycles) as u8, + result, + }), + MathPending::Divide { + cycles_remaining, + quotient, + remainder, + } if u32::from(cycles_remaining) <= cycles => { + self.math_quotient = quotient; + self.math_result = remainder; + None + } + MathPending::Divide { + cycles_remaining, + quotient, + remainder, + } => Some(MathPending::Divide { + cycles_remaining: (u32::from(cycles_remaining) - cycles) as u8, + quotient, + remainder, + }), + }; + } + + fn advance_video_one_subtick(&mut self) { + let was_in_vblank = self.in_vblank(); + self.video_phase = (self.video_phase + 1) % VBLANK_STUB_PERIOD; + let current_subtick = self.current_subtick(); + let current_scanline = self.current_scanline(); + self.cartridge.tick_sa1_timer( + current_subtick, + current_scanline, + VBLANK_STUB_SUBTICKS_PER_SCANLINE, + ); + let in_vblank = self.in_vblank(); + // Rising edge of vblank: latch the NMI flag and optionally queue a + // pending NMI for the CPU (when NMITIMEN bit 7 is set). + if !was_in_vblank && in_vblank { + self.completed_odd_frame = self.odd_frame; + self.presented_backdrop_completed_lines = self.presented_backdrop_current_lines; + self.presented_bg1_completed_lines = self.presented_bg1_current_lines; + self.presented_bg2_completed_lines = self.presented_bg2_current_lines; + self.presented_bg3_completed_lines = self.presented_bg3_current_lines; + self.presented_bg4_completed_lines = self.presented_bg4_current_lines; + self.presented_main_screen_completed_lines = self.presented_main_screen_current_lines; + self.presented_color_window_completed_lines = self.presented_color_window_current_lines; + self.nmi_flag = true; + if self.nmi_enabled() { + self.nmi_pending = true; + } + self.auto_joy_armed = self.auto_joy_enabled(); + self.auto_joy_active = false; + self.auto_joy_subticks_remaining = 0; + } + if self.irq_event_matches_current_position() { + self.irq_flag = true; + } + self.tick_auto_joypad(); + if was_in_vblank && !in_vblank { + self.auto_joy_armed = false; + self.auto_joy_active = false; + self.auto_joy_subticks_remaining = 0; + self.reload_hdma_channels(); + self.odd_frame = !self.odd_frame; + self.presented_backdrop_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg1_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg2_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg3_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_bg4_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_main_screen_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + self.presented_color_window_current_lines = [None; PRESENTED_SCANLINE_COUNT]; + } + if was_in_vblank && !in_vblank { + self.nmi_flag = false; + } + if self.current_subtick() == 0 && !in_vblank { + self.capture_presented_scanline(); + } + if self.in_hblank() && !in_vblank { + self.step_hdma_line(); + } + } + + fn nmi_enabled(&self) -> bool { + // NMITIMEN ($4200) bit 7 enables VBlank NMI + self.cpu_io_registers[0x00] & 0x80 != 0 + } + + fn cpu_master_clocks_per_cycle(&self) -> u32 { + if self.memsel_fast { + CPU_MASTER_CLOCKS_PER_CYCLE_FAST + } else { + CPU_MASTER_CLOCKS_PER_CYCLE_SLOW + } + } + + fn auto_joy_enabled(&self) -> bool { + self.cpu_io_registers[0x00] & 0x01 != 0 + } + + fn vcounter_irq_enabled(&self) -> bool { + self.cpu_io_registers[0x00] & 0x20 != 0 + } + + fn hcounter_irq_enabled(&self) -> bool { + self.cpu_io_registers[0x00] & 0x10 != 0 + } + + fn vtime_target(&self) -> u16 { + u16::from(self.cpu_io_registers[0x09]) + | (u16::from(self.cpu_io_registers[0x0A] & 0x01) << 8) + } + + fn htime_target(&self) -> u16 { + u16::from(self.cpu_io_registers[0x07]) + | (u16::from(self.cpu_io_registers[0x08] & 0x01) << 8) + } + + fn current_scanline(&self) -> u16 { + self.video_phase / VBLANK_STUB_SUBTICKS_PER_SCANLINE + } + + fn current_subtick(&self) -> u16 { + self.video_phase % VBLANK_STUB_SUBTICKS_PER_SCANLINE + } + + fn resolve_presented_line( + current_line: &[Option; PRESENTED_SCANLINE_COUNT], + completed_line: &[Option; PRESENTED_SCANLINE_COUNT], + line: usize, + ) -> Option { + current_line + .get(line) + .copied() + .flatten() + .or_else(|| completed_line.get(line).copied().flatten()) + } + + pub(crate) fn presented_backdrop_line(&self, line: usize) -> Option { + Self::resolve_presented_line( + &self.presented_backdrop_current_lines, + &self.presented_backdrop_completed_lines, + line, + ) + } + + pub(crate) fn presented_bg1_line(&self, line: usize) -> Option { + Self::resolve_presented_line( + &self.presented_bg1_current_lines, + &self.presented_bg1_completed_lines, + line, + ) + } + + pub(crate) fn presented_bg2_line(&self, line: usize) -> Option { + Self::resolve_presented_line( + &self.presented_bg2_current_lines, + &self.presented_bg2_completed_lines, + line, + ) + } + + pub(crate) fn presented_bg3_line(&self, line: usize) -> Option { + Self::resolve_presented_line( + &self.presented_bg3_current_lines, + &self.presented_bg3_completed_lines, + line, + ) + } + + pub(crate) fn presented_bg4_line(&self, line: usize) -> Option { + Self::resolve_presented_line( + &self.presented_bg4_current_lines, + &self.presented_bg4_completed_lines, + line, + ) + } + + pub(crate) fn presented_main_screen_line( + &self, + line: usize, + ) -> Option { + Self::resolve_presented_line( + &self.presented_main_screen_current_lines, + &self.presented_main_screen_completed_lines, + line, + ) + } + + pub(crate) fn interlace_enabled(&self) -> bool { + self.ppu2.interlace_enabled() + } + + pub(crate) fn obj_interlace_enabled(&self) -> bool { + self.ppu2.obj_interlace_enabled() + } + + pub(crate) fn pseudo_hires_enabled(&self) -> bool { + self.ppu2.pseudo_hires_enabled() + } + + pub(crate) fn odd_frame(&self) -> bool { + self.odd_frame + } + + pub(crate) fn completed_odd_frame(&self) -> bool { + self.completed_odd_frame + } + + pub(crate) fn presented_color_window_line( + &self, + line: usize, + ) -> Option { + Self::resolve_presented_line( + &self.presented_color_window_current_lines, + &self.presented_color_window_completed_lines, + line, + ) + } + + fn auto_joy_start_reachable(&self) -> bool { + self.current_scanline() < VBLANK_STUB_ACTIVE_START_LINE + || (self.current_scanline() == VBLANK_STUB_ACTIVE_START_LINE + && self.current_subtick() <= AUTO_JOYPAD_START_SUBTICK) + } + + fn auto_joy_can_be_disarmed(&self) -> bool { + self.current_scanline() < VBLANK_STUB_ACTIVE_START_LINE + || (self.current_scanline() == VBLANK_STUB_ACTIVE_START_LINE + && self.current_subtick() < AUTO_JOYPAD_START_SUBTICK) + } + + fn at_auto_joy_start(&self) -> bool { + self.current_scanline() == VBLANK_STUB_ACTIVE_START_LINE + && self.current_subtick() == AUTO_JOYPAD_START_SUBTICK + } + + fn irq_event_matches_current_position(&self) -> bool { + let vmatch = self.vcounter_irq_enabled() && self.current_scanline() == self.vtime_target(); + let hmatch = self.hcounter_irq_enabled() + && hcounter_target_is_in_subtick(self.htime_target(), self.current_subtick()); + + match (self.vcounter_irq_enabled(), self.hcounter_irq_enabled()) { + (false, false) => false, + (false, true) => hmatch, + (true, false) => vmatch && self.current_subtick() == 0, + (true, true) => vmatch && hmatch, + } + } + + fn current_hcounter(&self) -> u16 { + hcounter_midpoint_for_subtick(self.current_subtick()) + } + + fn wrio_port2_high(&self) -> bool { + self.cpu_io_registers[0x01] & 0x40 != 0 + } + + fn latch_counters(&mut self) { + self.latched_hcounter = self.current_hcounter(); + self.latched_vcounter = self.current_scanline(); + self.ophct_high_byte = false; + self.opvct_high_byte = false; + } + + fn read_latched_hcounter(&mut self) -> u8 { + let value = counter_byte(self.latched_hcounter, self.ophct_high_byte); + self.ophct_high_byte = !self.ophct_high_byte; + value + } + + fn read_latched_vcounter(&mut self) -> u8 { + let value = counter_byte(self.latched_vcounter, self.opvct_high_byte); + self.opvct_high_byte = !self.opvct_high_byte; + value + } + + fn peek_latched_hcounter(&self) -> u8 { + counter_byte(self.latched_hcounter, self.ophct_high_byte) + } + + fn peek_latched_vcounter(&self) -> u8 { + counter_byte(self.latched_vcounter, self.opvct_high_byte) + } + + /// Consume and return the pending-NMI flag. Called by the CPU each cycle + /// while in WAI state. + pub(crate) fn poll_nmi(&mut self) -> bool { + core::mem::take(&mut self.nmi_pending) + } + + pub(crate) fn poll_irq(&self) -> bool { + self.irq_flag && (self.vcounter_irq_enabled() || self.hcounter_irq_enabled()) + } + + pub(crate) fn has_pending_interrupt(&self) -> bool { + self.nmi_pending || self.poll_irq() + } + + pub(crate) fn peek(&self, address: u32) -> u8 { + self.peek_resolved(address & ADDRESS_MASK) + } + + pub(crate) fn peek_side_effect_free(&self, address: u32) -> Option { + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if let Some(value) = self.memory.peek_cpu_bus(bank, offset) { + return Some(value); + } + if Self::is_cpu_internal_register(bank, offset) { + return None; + } + self.cartridge.read_side_effect_free(address) + } + + pub(crate) fn peek_apu_ram(&self, address: u16) -> u8 { + self.apu.peek_ram(address) + } + + pub(crate) fn read(&mut self, address: u32) -> u8 { + self.read_resolved(address & ADDRESS_MASK) + } + + pub(crate) fn write(&mut self, address: u32, value: u8) { + self.write_resolved(address & ADDRESS_MASK, value); + } + + fn is_cpu_internal_register(bank: u8, offset: u16) -> bool { + matches!(bank, 0x00..=0x3F | 0x80..=0xBF) + && matches!( + offset, + 0x2100..=0x217F + | 0x2180..=0x2183 + | 0x4016..=0x4017 + | 0x4200..=0x421F + | 0x4300..=0x437F + ) + } + + fn in_vblank(&self) -> bool { + self.current_scanline() >= VBLANK_STUB_ACTIVE_START_LINE + } + + fn in_hblank(&self) -> bool { + self.current_subtick() + 1 == VBLANK_STUB_SUBTICKS_PER_SCANLINE + } + + fn hvbjoy_value(&self) -> u8 { + u8::from(self.in_vblank()) << 7 + | u8::from(self.in_hblank()) << 6 + | u8::from(self.auto_joy_active) + } + + fn arm_auto_joy_for_current_frame(&mut self) { + self.auto_joy_armed = true; + if self.at_auto_joy_start() { + self.start_auto_joypad(); + } + } + + fn start_auto_joypad(&mut self) { + let sampled_ports = self.sample_standard_controller_ports(); + self.load_standard_controller_ports(sampled_ports, 0); + self.auto_joy_active = true; + self.auto_joy_subticks_remaining = AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS; + } + + fn tick_auto_joypad(&mut self) { + if self.auto_joy_active { + self.auto_joy_subticks_remaining -= 1; + if self.auto_joy_subticks_remaining == 0 { + self.auto_joy_active = false; + self.auto_joy_armed = false; + self.complete_auto_joypad(); + } + return; + } + + if self.auto_joy_armed && self.at_auto_joy_start() { + self.start_auto_joypad(); + } + } + + fn complete_auto_joypad(&mut self) { + let sampled_ports = self.sample_standard_controller_ports(); + let registers = self.sample_auto_joypad_registers(sampled_ports); + self.cpu_io_registers[0x18..0x20].copy_from_slice(®isters); + self.load_standard_controller_ports(sampled_ports, STANDARD_CONTROLLER_PAYLOAD_BITS); + } + + fn sample_auto_joypad_registers( + &self, + sampled_ports: [u16; STANDARD_CONTROLLER_PORT_COUNT], + ) -> [u8; 8] { + let [port1, port2] = sampled_ports; + [ + port1 as u8, + (port1 >> 8) as u8, + port2 as u8, + (port2 >> 8) as u8, + 0, + 0, + 0, + 0, + ] + } + + fn sample_standard_controller_ports(&self) -> [u16; STANDARD_CONTROLLER_PORT_COUNT] { + [ + self.sample_standard_controller_port(0), + self.sample_standard_controller_port(1), + ] + } + + pub(crate) fn set_standard_controller_buttons(&mut self, port: usize, buttons: u16) -> bool { + let Some(current) = self.standard_controller_buttons.get_mut(port) else { + return false; + }; + *current = buttons; + true + } + + fn sample_standard_controller_port(&self, port: usize) -> u16 { + self.standard_controller_buttons[port] + } + + fn load_standard_controller_ports( + &mut self, + sampled_ports: [u16; STANDARD_CONTROLLER_PORT_COUNT], + serial_position: u8, + ) { + for (port, sampled_buttons) in self.controller_ports.iter_mut().zip(sampled_ports) { + port.load_sample(sampled_buttons, serial_position); + } + } + + fn current_b_button(&self, port: usize) -> u8 { + ((self.sample_standard_controller_port(port) + >> u16::from(STANDARD_CONTROLLER_PAYLOAD_BITS - 1)) + & 0x01) as u8 + } + + fn read_joyser0(&mut self) -> u8 { + self.read_standard_controller_port(0) + } + + fn read_joyser1(&mut self) -> u8 { + JOYSER1_STANDARD_HIGH_BITS | self.read_standard_controller_port(1) + } + + fn peek_joyser0(&self) -> u8 { + self.peek_standard_controller_port(0) + } + + fn peek_joyser1(&self) -> u8 { + JOYSER1_STANDARD_HIGH_BITS | self.peek_standard_controller_port(1) + } + + fn read_standard_controller_port(&mut self, port: usize) -> u8 { + if self.joyout_latch_high { + self.current_b_button(port) + } else { + self.controller_ports[port].read_serial_bit() + } + } + + fn peek_standard_controller_port(&self, port: usize) -> u8 { + if self.joyout_latch_high { + self.current_b_button(port) + } else { + self.controller_ports[port].peek_serial_bit() + } + } + + fn write_joyout(&mut self, value: u8) { + let was_latch_high = self.joyout_latch_high; + self.joyout_latch_high = value & 0x01 != 0; + if was_latch_high && !self.joyout_latch_high { + let sampled_ports = self.sample_standard_controller_ports(); + self.load_standard_controller_ports(sampled_ports, 0); + } + } + + fn read_resolved(&mut self, address: u32) -> u8 { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if let Some(value) = self.memory.read_cpu_bus(bank, offset) { + return value; + } + + match (bank, offset) { + (0x00..=0x3F | 0x80..=0xBF, 0x2100..=0x213F) => self.read_ppu_register(offset), + (0x00..=0x3F | 0x80..=0xBF, 0x2140..=0x217F) => self.apu.read_cpu_port(offset), + (0x00..=0x3F | 0x80..=0xBF, 0x2180..=0x2183) => { + self.memory.read_mmio(offset).unwrap_or(0) + } + (0x00..=0x3F | 0x80..=0xBF, 0x4016) => self.read_joyser0(), + (0x00..=0x3F | 0x80..=0xBF, 0x4017) => self.read_joyser1(), + (0x00..=0x3F | 0x80..=0xBF, 0x4200..=0x421F) => self.read_cpu_io(offset), + (0x00..=0x3F | 0x80..=0xBF, 0x4300..=0x437F) => self.read_dma_register(offset), + _ => self.cartridge.read_mut(address).unwrap_or(0), + } + } + + fn peek_resolved(&self, address: u32) -> u8 { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if let Some(value) = self.memory.peek_cpu_bus(bank, offset) { + return value; + } + + match (bank, offset) { + (0x00..=0x3F | 0x80..=0xBF, 0x2100..=0x213F) => self.peek_ppu_register(offset), + (0x00..=0x3F | 0x80..=0xBF, 0x2140..=0x217F) => self.apu.peek_cpu_port(offset), + (0x00..=0x3F | 0x80..=0xBF, 0x2180..=0x2183) => { + self.memory.peek_mmio(offset).unwrap_or(0) + } + (0x00..=0x3F | 0x80..=0xBF, 0x4016) => self.peek_joyser0(), + (0x00..=0x3F | 0x80..=0xBF, 0x4017) => self.peek_joyser1(), + (0x00..=0x3F | 0x80..=0xBF, 0x4210) => { + if self.nmi_flag { + 0x80 + } else { + 0x00 + } + } + (0x00..=0x3F | 0x80..=0xBF, 0x4211) => { + if self.irq_flag { + 0x80 + } else { + 0x00 + } + } + (0x00..=0x3F | 0x80..=0xBF, 0x4212) => self.hvbjoy_value(), + (0x00..=0x3F | 0x80..=0xBF, 0x4214) => self.math_quotient as u8, + (0x00..=0x3F | 0x80..=0xBF, 0x4215) => (self.math_quotient >> 8) as u8, + (0x00..=0x3F | 0x80..=0xBF, 0x4216) => self.math_result as u8, + (0x00..=0x3F | 0x80..=0xBF, 0x4217) => (self.math_result >> 8) as u8, + (0x00..=0x3F | 0x80..=0xBF, 0x4218) => self.cpu_io_registers[0x18], + (0x00..=0x3F | 0x80..=0xBF, 0x4200..=0x421F) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] + } + (0x00..=0x3F | 0x80..=0xBF, 0x4300..=0x437F) => self.peek_dma_register(offset), + _ => self.cartridge.read(address).unwrap_or(0), + } + } + + fn write_resolved(&mut self, address: u32, value: u8) { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if self.memory.write_cpu_bus(bank, offset, value) { + return; + } + + match (bank, offset) { + (0x00..=0x3F | 0x80..=0xBF, 0x2100..=0x213F) => { + let _ = self.write_ppu_register(offset, value); + } + (0x00..=0x3F | 0x80..=0xBF, 0x2140..=0x217F) => { + self.apu.write_cpu_port(offset, value); + } + (0x00..=0x3F | 0x80..=0xBF, 0x2180..=0x2183) => { + let _ = self.memory.write_mmio(offset, value); + } + (0x00..=0x3F | 0x80..=0xBF, 0x4016) => self.write_joyout(value), + (0x00..=0x3F | 0x80..=0xBF, 0x4017) => {} + // MDMAEN ($420B): store then execute selected DMA channels immediately. + (0x00..=0x3F | 0x80..=0xBF, 0x420B) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] = value; + if value != 0 { + self.execute_dma(value); + self.cpu_io_registers[usize::from(offset - 0x4200)] = 0; + } + } + // MEMSEL ($420D): Memory-2 Waitstate Control + // Bit 0: 0=2.68MHz (slow ROM), 1=3.58MHz (fast ROM) + (0x00..=0x3F | 0x80..=0xBF, 0x420D) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] = value; + self.memsel_fast = value & 0x01 != 0; + } + // NMITIMEN ($4200): track whether NMI is enabled; raise a pending NMI + // immediately if the NMI flag is already latched (i.e. we are mid-vblank + // and the program enables NMI after clearing RDNMI). + (0x00..=0x3F | 0x80..=0xBF, 0x4200) => { + let previous = self.cpu_io_registers[0x00]; + let was_nmi_enabled = previous & 0x80 != 0; + let was_auto_joy_enabled = previous & 0x01 != 0; + self.cpu_io_registers[0x00] = value; + let now_nmi_enabled = value & 0x80 != 0; + let now_auto_joy_enabled = value & 0x01 != 0; + if !was_nmi_enabled && now_nmi_enabled && self.nmi_flag { + self.nmi_pending = true; + } + if self.in_vblank() + && !was_auto_joy_enabled + && now_auto_joy_enabled + && self.auto_joy_start_reachable() + { + self.arm_auto_joy_for_current_frame(); + } + if self.in_vblank() + && was_auto_joy_enabled + && !now_auto_joy_enabled + && !self.auto_joy_active + && self.auto_joy_can_be_disarmed() + { + self.auto_joy_armed = false; + } + if self.irq_event_matches_current_position() { + self.irq_flag = true; + } + } + (0x00..=0x3F | 0x80..=0xBF, 0x4201) => { + let previous = self.cpu_io_registers[0x01]; + self.cpu_io_registers[0x01] = value; + if previous & 0x40 != 0 && value & 0x40 == 0 { + self.latch_counters(); + } + } + (0x00..=0x3F | 0x80..=0xBF, 0x4202) => { + self.cpu_io_registers[0x02] = value; + } + (0x00..=0x3F | 0x80..=0xBF, 0x4203) => { + self.cpu_io_registers[0x03] = value; + self.start_multiply(value); + } + (0x00..=0x3F | 0x80..=0xBF, 0x4204..=0x4205) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] = value; + } + (0x00..=0x3F | 0x80..=0xBF, 0x4206) => { + self.cpu_io_registers[0x06] = value; + self.start_divide(value); + } + (0x00..=0x3F | 0x80..=0xBF, 0x420C) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] = value; + if !self.in_vblank() { + let previous_active_mask = self.hdma_active_mask; + self.hdma_active_mask = value & !self.hdma_ended_mask; + let newly_active = self.hdma_active_mask & !previous_active_mask; + for channel in 0..DMA_CHANNEL_COUNT { + if newly_active & (1 << channel) != 0 { + self.hdma_do_transfer[channel] = true; + } + } + if self.in_hblank() { + self.step_hdma_channels(newly_active); + } + } + } + (0x00..=0x3F | 0x80..=0xBF, 0x4218..=0x421F) => {} + (0x00..=0x3F | 0x80..=0xBF, 0x4200..=0x421F) => { + self.cpu_io_registers[usize::from(offset - 0x4200)] = value; + } + (0x00..=0x3F | 0x80..=0xBF, 0x4300..=0x437F) => { + self.write_dma_register(offset, value); + } + _ => { + let _ = self.cartridge.write(address, value); + } + } + } + + /// Execute all DMA channels whose bit is set in `mdmaen`, lowest first. + fn execute_dma(&mut self, mdmaen: u8) { + let hdmaen = self.cpu_io_registers[0x0C]; + for channel in 0..8u8 { + if mdmaen & (1 << channel) != 0 && hdmaen & (1 << channel) == 0 { + self.execute_dma_channel(channel); + } + } + } + + fn dma_read_abus(&mut self, address: u32) -> u8 { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if !dma_abus_accessible(bank, offset) { + return 0; + } + + self.memory + .read_cpu_bus(bank, offset) + .or_else(|| self.cartridge.read_mut(address)) + .unwrap_or(0) + } + + fn dma_write_abus(&mut self, address: u32, value: u8) { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if !dma_abus_accessible(bank, offset) { + return; + } + + if !self.memory.write_cpu_bus(bank, offset, value) { + let _ = self.cartridge.write(address, value); + } + } + + /// Execute a single general-purpose DMA channel. + /// + /// Register layout per channel (base = channel * 0x10): + /// +0 DMAP – bit7=direction(0=A→B), bits4:3=addr mode(00=inc, 01/11=fixed, 10=dec), + /// bits2-0=pattern + /// +1 BBAD – B-bus address offset from $2100 + /// +2 A1TL – A-bus source address low + /// +3 A1TH – A-bus source address high + /// +4 A1B – A-bus source bank + /// +5 DASL – byte count low (0+0 ⇒ 65536) + /// +6 DASH – byte count high + fn execute_dma_channel(&mut self, channel: u8) { + let base = usize::from(channel) * 0x10; + + let dmap = self.dma_registers[base]; + let bbad = self.dma_registers[base + 0x1]; + let a1t_lo = self.dma_registers[base + 0x2]; + let a1t_hi = self.dma_registers[base + 0x3]; + let a1b = self.dma_registers[base + 0x4]; + let das_lo = self.dma_registers[base + 0x5]; + let das_hi = self.dma_registers[base + 0x6]; + + // DMAP decode + let b_to_a = dmap & 0x80 != 0; // direction: 0=A→B (CPU→PPU), 1=B→A (PPU→CPU) + let fixed = dmap & 0x08 != 0; // no A-bus address change + let decrement = dmap & 0x10 != 0; // decrement A-bus address (only when !fixed) + let pattern = dmap & 0x07; + + // A-bus starting address (24-bit, bank does not wrap during transfer) + let mut a_addr: u32 = (u32::from(a1b) << 16) | (u32::from(a1t_hi) << 8) | u32::from(a1t_lo); + + // Byte count: 0 means 65536 + let mut remaining: u32 = if das_lo == 0 && das_hi == 0 { + 0x10000 + } else { + (u32::from(das_hi) << 8) | u32::from(das_lo) + }; + + // Per-pattern B-bus address offsets (cycled during transfer). + // Patterns 6 and 7 are aliases of 2 and 3 respectively. + let offsets = dma_transfer_offsets(pattern); + + let mut pidx: usize = 0; + + while remaining > 0 { + let b_addr = 0x2100 | u16::from(bbad.wrapping_add(offsets[pidx])); + + if b_to_a { + let val = self.dma_read_bbus(b_addr); + self.dma_write_abus(a_addr, val); + } else { + let val = self.dma_read_abus(a_addr); + self.dma_write_bbus(b_addr, val); + } + + if !fixed { + // Keep transfer within the source bank + let new_offset = if decrement { + (a_addr as u16).wrapping_sub(1) + } else { + (a_addr as u16).wrapping_add(1) + }; + a_addr = (a_addr & 0xFF_0000) | u32::from(new_offset); + } + + pidx = (pidx + 1) % offsets.len(); + remaining -= 1; + } + + // Write back updated A1T (bank is unchanged) and zero DAS. + self.dma_registers[base + 0x2] = a_addr as u8; + self.dma_registers[base + 0x3] = (a_addr >> 8) as u8; + self.dma_registers[base + 0x5] = 0; + self.dma_registers[base + 0x6] = 0; + self.hdma_data_addr[usize::from(channel)] = 0; + } + + /// Write one byte to the B-bus (PPU / WRAM-port / ignored). + fn dma_write_bbus(&mut self, b_addr: u16, value: u8) { + match b_addr { + 0x2100..=0x213F => { + let _ = self.write_ppu_register(b_addr, value); + } + 0x2140..=0x217F => { + self.apu.write_cpu_port(b_addr, value); + } + 0x2180..=0x2183 => { + let _ = self.memory.write_mmio(b_addr, value); + } + _ => {} // unknown B-bus address: silently discard + } + } + + /// Read one byte from the B-bus (PPU / WRAM-port / open-bus 0). + fn dma_read_bbus(&mut self, b_addr: u16) -> u8 { + match b_addr { + 0x2100..=0x213F => self.read_ppu_register(b_addr), + 0x2140..=0x217F => self.apu.read_cpu_port(b_addr), + 0x2180..=0x2183 => self.memory.read_mmio(b_addr).unwrap_or(0), + _ => 0, + } + } + + fn read_dma_register(&self, offset: u16) -> u8 { + self.peek_dma_register(offset) + } + + fn peek_dma_register(&self, offset: u16) -> u8 { + let index = usize::from((offset - 0x4300) / 0x10); + let register = usize::from((offset - 0x4300) % 0x10); + + match register { + 0x5 => self.hdma_data_addr[index] as u8, + 0x6 => (self.hdma_data_addr[index] >> 8) as u8, + 0x7 => self.hdma_data_bank[index], + 0x8 => self.hdma_table_addr[index] as u8, + 0x9 => (self.hdma_table_addr[index] >> 8) as u8, + 0xA => encode_hdma_line_control(self.hdma_line_counter[index], self.hdma_repeat[index]), + _ => self.dma_registers[usize::from(offset - 0x4300)], + } + } + + fn write_dma_register(&mut self, offset: u16, value: u8) { + let register_index = usize::from(offset - 0x4300); + let channel = register_index / 0x10; + let register = register_index % 0x10; + + self.dma_registers[register_index] = value; + + match register { + 0x0 => self.hdma_indirect[channel] = value & 0x40 != 0, + 0x5 => { + self.hdma_data_addr[channel] = + (self.hdma_data_addr[channel] & 0xFF00) | u16::from(value); + } + 0x6 => { + self.hdma_data_addr[channel] = + (self.hdma_data_addr[channel] & 0x00FF) | (u16::from(value) << 8); + } + 0x7 => self.hdma_data_bank[channel] = value, + 0x8 => { + self.hdma_table_addr[channel] = + (self.hdma_table_addr[channel] & 0xFF00) | u16::from(value); + } + 0x9 => { + self.hdma_table_addr[channel] = + (self.hdma_table_addr[channel] & 0x00FF) | (u16::from(value) << 8); + } + 0xA => { + let (line_count, repeat) = if value == 0 { + // Software can seed live HDMA state directly. A manual NLTR=0 is + // used by hardware timing ROMs to arm exactly one transfer from + // the current A2A/DAS pointer instead of the encoded 128-line form + // used when HDMA itself reloads line control from the table. + (1, false) + } else { + decode_hdma_line_control(value) + }; + self.hdma_ended_mask &= !(1 << channel); + self.hdma_line_counter[channel] = line_count; + self.hdma_repeat[channel] = repeat; + } + _ => {} + } + } + + fn reload_hdma_channels(&mut self) { + self.hdma_active_mask = self.cpu_io_registers[0x0C]; + self.hdma_ended_mask = 0; + + let hdmaen = self.cpu_io_registers[0x0C]; + for channel in 0..DMA_CHANNEL_COUNT { + let bit = 1 << channel; + if hdmaen & bit == 0 { + self.hdma_do_transfer[channel] = false; + continue; + } + + if !self.reload_hdma_channel(channel as u8) { + self.hdma_active_mask &= !bit; + self.hdma_ended_mask |= bit; + } + } + } + + fn reload_hdma_channel(&mut self, channel: u8) -> bool { + let index = usize::from(channel); + let base = index * 0x10; + self.hdma_table_addr[index] = u16::from_le_bytes([ + self.dma_registers[base + 0x2], + self.dma_registers[base + 0x3], + ]); + self.hdma_indirect[index] = self.dma_registers[base] & 0x40 != 0; + self.load_hdma_entry(channel) + } + + fn load_hdma_entry(&mut self, channel: u8) -> bool { + let index = usize::from(channel); + let base = index * 0x10; + let table_bank = self.dma_registers[base + 0x4]; + let mut table_addr = self.hdma_table_addr[index]; + + let line_control = + self.dma_read_abus((u32::from(table_bank) << 16) | u32::from(table_addr)); + table_addr = table_addr.wrapping_add(1); + if line_control == 0 { + self.hdma_line_counter[index] = 0; + self.hdma_do_transfer[index] = false; + return false; + } + + let (line_count, repeat) = decode_hdma_line_control(line_control); + self.hdma_line_counter[index] = line_count; + self.hdma_repeat[index] = repeat; + self.hdma_do_transfer[index] = true; + + if self.hdma_indirect[index] { + let low = self.dma_read_abus((u32::from(table_bank) << 16) | u32::from(table_addr)); + let high = self.dma_read_abus( + (u32::from(table_bank) << 16) | u32::from(table_addr.wrapping_add(1)), + ); + table_addr = table_addr.wrapping_add(2); + self.hdma_data_addr[index] = u16::from_le_bytes([low, high]); + self.hdma_data_bank[index] = self.dma_registers[base + 0x7]; + } + + self.hdma_table_addr[index] = table_addr; + true + } + + fn step_hdma_line(&mut self) { + self.step_hdma_channels(self.hdma_active_mask); + } + + fn step_hdma_channels(&mut self, mask: u8) { + for channel in 0..DMA_CHANNEL_COUNT { + let bit = 1 << channel; + if mask & bit == 0 || self.hdma_active_mask & bit == 0 { + continue; + } + + if self.hdma_line_counter[channel] == 0 { + continue; + } + + if self.hdma_do_transfer[channel] { + self.execute_hdma_transfer(channel as u8); + } + + self.hdma_line_counter[channel] -= 1; + if self.hdma_line_counter[channel] == 0 { + if !self.load_hdma_entry(channel as u8) { + self.hdma_active_mask &= !bit; + self.hdma_ended_mask |= bit; + } else if self.hdma_do_transfer[channel] { + self.execute_hdma_transfer(channel as u8); + self.hdma_do_transfer[channel] = !self.hdma_repeat[channel]; + } + } else { + self.hdma_do_transfer[channel] = !self.hdma_repeat[channel]; + } + } + } + + fn execute_hdma_transfer(&mut self, channel: u8) { + let index = usize::from(channel); + let base = index * 0x10; + let dmap = self.dma_registers[base]; + let bbad = self.dma_registers[base + 0x1]; + let offsets = dma_transfer_offsets(dmap & 0x07); + + for (byte_index, offset) in offsets.iter().copied().enumerate() { + let source_addr = if self.hdma_indirect[index] { + self.hdma_data_addr[index].wrapping_add(byte_index as u16) + } else { + self.hdma_table_addr[index].wrapping_add(byte_index as u16) + }; + let value = self.dma_read_abus( + (u32::from(if self.hdma_indirect[index] { + self.hdma_data_bank[index] + } else { + self.dma_registers[base + 0x4] + }) << 16) + | u32::from(source_addr), + ); + let b_addr = 0x2100 | u16::from(bbad.wrapping_add(offset)); + self.dma_write_bbus(b_addr, value); + } + + if self.hdma_indirect[index] { + self.hdma_data_addr[index] = + self.hdma_data_addr[index].wrapping_add(offsets.len() as u16); + } else { + self.hdma_table_addr[index] = + self.hdma_table_addr[index].wrapping_add(offsets.len() as u16); + } + } + + fn capture_presented_scanline(&mut self) { + let scanline = usize::from(self.current_scanline()); + if scanline >= PRESENTED_SCANLINE_COUNT { + return; + } + + let color0 = + u16::from_le_bytes([self.ppu2.peek_cgram(0), self.ppu2.peek_cgram(1)]) & 0x7FFF; + let inidisp = self.ppu2.peek(0x2100).unwrap_or(0); + self.presented_backdrop_current_lines[scanline] = + Some(PresentedBackdropLine { inidisp, color0 }); + self.presented_bg1_current_lines[scanline] = Some(PresentedBg1Line { + hofs: self.ppu1.bg1_hofs(), + vofs: self.ppu1.bg1_vofs(), + }); + self.presented_bg2_current_lines[scanline] = Some(PresentedBg1Line { + hofs: self.ppu1.bg2_hofs(), + vofs: self.ppu1.bg2_vofs(), + }); + self.presented_bg3_current_lines[scanline] = Some(PresentedBg1Line { + hofs: self.ppu1.bg3_hofs(), + vofs: self.ppu1.bg3_vofs(), + }); + self.presented_bg4_current_lines[scanline] = Some(PresentedBg1Line { + hofs: self.ppu1.bg4_hofs(), + vofs: self.ppu1.bg4_vofs(), + }); + self.presented_main_screen_current_lines[scanline] = Some(PresentedMainScreenLine { + tm: self.ppu2.peek(0x212C).unwrap_or(0), + }); + self.presented_color_window_current_lines[scanline] = Some(PresentedColorWindowLine { + wh0: self.ppu2.peek(0x2126).unwrap_or(0), + wh1: self.ppu2.peek(0x2127).unwrap_or(0), + wh2: self.ppu2.peek(0x2128).unwrap_or(0), + wh3: self.ppu2.peek(0x2129).unwrap_or(0), + }); + } + + fn read_ppu_register(&mut self, offset: u16) -> u8 { + match offset { + 0x2137 => { + if self.wrio_port2_high() { + self.latch_counters(); + } + 0 + } + 0x213C => self.read_latched_hcounter(), + 0x213D => self.read_latched_vcounter(), + 0x213F => { + self.ophct_high_byte = false; + self.opvct_high_byte = false; + self.ppu2.read(offset).unwrap_or(0) + } + _ => self + .ppu1 + .read(offset) + .or_else(|| self.ppu2.read(offset)) + .unwrap_or(0), + } + } + + fn peek_ppu_register(&self, offset: u16) -> u8 { + match offset { + 0x2137 => 0, + 0x213C => self.peek_latched_hcounter(), + 0x213D => self.peek_latched_vcounter(), + _ => self + .ppu1 + .peek(offset) + .or_else(|| self.ppu2.peek(offset)) + .unwrap_or(0), + } + } + + fn vram_port_accessible(&self) -> bool { + self.in_vblank() || self.ppu2.force_blank() + } + + fn write_ppu_register(&mut self, offset: u16, value: u8) -> bool { + match offset { + 0x2118 | 0x2119 => { + self.ppu1 + .write_with_vram_access(offset, value, self.vram_port_accessible()) + } + _ => self.ppu1.write(offset, value) || self.ppu2.write(offset, value), + } + } + + fn read_cpu_io(&mut self, offset: u16) -> u8 { + match offset { + // RDNMI ($4210): returns NMI flag in bit 7 and clears it on read. + 0x4210 => { + // Keep bit 6 asserted so BIT $4210 behaves like the hardware + // open-bus pattern used by several ROM tests. + let val = 0x40 | if self.nmi_flag { 0x80 } else { 0x00 }; + self.nmi_flag = false; + val + } + 0x4211 => { + let val = 0x40 | if self.irq_flag { 0x80 } else { 0x00 }; + self.irq_flag = false; + val + } + 0x4212 => self.hvbjoy_value(), + 0x4214 => self.math_quotient as u8, + 0x4215 => (self.math_quotient >> 8) as u8, + 0x4216 => self.math_result as u8, + 0x4217 => (self.math_result >> 8) as u8, + 0x4218 => self.cpu_io_registers[0x18], + _ => self.cpu_io_registers[usize::from(offset - 0x4200)], + } + } + + fn start_multiply(&mut self, factor_b: u8) { + let cycles_since_previous_multiply = match self.math_pending { + Some(MathPending::Multiply { + cycles_remaining, .. + }) => MATH_MULTIPLY_CYCLES.saturating_sub(cycles_remaining), + _ => MATH_MULTIPLY_CYCLES, + }; + self.math_quotient = u16::from(factor_b); + self.math_result = 0; + if cycles_since_previous_multiply == WRMPYB_IN_FLIGHT_ZERO_CYCLE { + self.math_pending = None; + return; + } + + self.math_pending = Some(MathPending::Multiply { + cycles_remaining: MATH_MULTIPLY_CYCLES, + result: u16::from(self.cpu_io_registers[0x02]) * u16::from(factor_b), + }); + } + + fn start_divide(&mut self, divisor: u8) { + let dividend = + u16::from_le_bytes([self.cpu_io_registers[0x04], self.cpu_io_registers[0x05]]); + let (quotient, remainder) = if divisor == 0 { + (0xFFFF, dividend) + } else { + (dividend / u16::from(divisor), dividend % u16::from(divisor)) + }; + self.math_pending = Some(MathPending::Divide { + cycles_remaining: MATH_DIVIDE_CYCLES, + quotient, + remainder, + }); + } +} + +impl CpuBus for Bus { + fn read(&mut self, addr: u32) -> u8 { + Bus::read(self, addr) + } + + fn write(&mut self, addr: u32, data: u8) { + Bus::write(self, addr, data); + } + + fn tick(&mut self) { + self.tick_cpu_cycle(); + } + + fn tick_many(&mut self, cycles: u32) { + self.step_cpu_cycles(cycles); + } + + fn peek_side_effect_free(&self, addr: u32) -> Option { + Bus::peek_side_effect_free(self, addr) + } + + fn has_pending_interrupt(&self) -> bool { + Bus::has_pending_interrupt(self) + } + + fn poll_nmi(&mut self) -> bool { + Bus::poll_nmi(self) + } + + fn poll_irq(&mut self) -> bool { + Bus::poll_irq(self) + } +} + +pub(crate) struct ScheduledCpuBus<'a> { + bus: &'a mut Bus, + pending_cycles: u32, + audio_mixer: Option<&'a mut dyn MixerInput>, +} + +impl<'a> ScheduledCpuBus<'a> { + pub(crate) fn new(bus: &'a mut Bus) -> Self { + Self { + bus, + pending_cycles: 0, + audio_mixer: None, + } + } + + pub(crate) fn new_with_audio(bus: &'a mut Bus, mixer: &'a mut M) -> Self { + Self { + bus, + pending_cycles: 0, + audio_mixer: Some(mixer), + } + } + + pub(crate) fn flush(&mut self) { + if self.pending_cycles == 0 { + return; + } + let cycles = self.pending_cycles; + self.pending_cycles = 0; + self.bus.step_cpu_cycles(cycles); + if let Some(mixer) = self.audio_mixer.as_deref_mut() { + self.bus.mix_audio_for_cpu_cycles(cycles, mixer); + } + } +} + +impl CpuBus for ScheduledCpuBus<'_> { + fn read(&mut self, addr: u32) -> u8 { + self.flush(); + self.bus.read(addr) + } + + fn write(&mut self, addr: u32, data: u8) { + self.flush(); + self.bus.write(addr, data); + } + + fn tick(&mut self) { + self.tick_many(1); + } + + fn tick_many(&mut self, cycles: u32) { + self.pending_cycles = self + .pending_cycles + .checked_add(cycles) + .expect("scheduled CPU bus pending cycle accumulator overflowed"); + } + + fn peek_side_effect_free(&self, addr: u32) -> Option { + (self.pending_cycles == 0) + .then(|| self.bus.peek_side_effect_free(addr)) + .flatten() + } + + fn has_pending_interrupt(&self) -> bool { + self.pending_cycles != 0 || self.bus.has_pending_interrupt() + } + + fn poll_nmi(&mut self) -> bool { + self.flush(); + self.bus.poll_nmi() + } + + fn poll_irq(&mut self) -> bool { + self.flush(); + self.bus.poll_irq() + } +} + +fn dma_abus_accessible(bank: u8, offset: u16) -> bool { + !matches!( + (bank, offset), + ( + 0x00..=0x3F | 0x80..=0xBF, + 0x2100..=0x21FF | 0x4000..=0x41FF | 0x4200..=0x421F | 0x4300..=0x437F, + ) + ) +} + +fn initial_cpu_io_registers() -> [u8; CPU_IO_REGISTER_COUNT] { + let mut registers = [0; CPU_IO_REGISTER_COUNT]; + registers[0x01] = 0xFF; + registers +} + +fn decode_hdma_line_control(value: u8) -> (u8, bool) { + let line_count = if value & 0x7F == 0 { + 0x80 + } else { + value & 0x7F + }; + let repeat = if value & 0x7F == 0 { + value & 0x80 != 0 + } else { + value & 0x80 == 0 + }; + (line_count, repeat) +} + +fn encode_hdma_line_control(line_count: u8, repeat: bool) -> u8 { + if line_count == 0 { + 0 + } else if line_count & 0x7F == 0 { + u8::from(repeat) << 7 + } else { + (line_count & 0x7F) | (u8::from(!repeat) << 7) + } +} + +fn hcounter_target_is_in_subtick(target: u16, subtick: u16) -> bool { + let start = (u32::from(subtick) * u32::from(HCOUNTER_DOTS_PER_LINE)) + / u32::from(VBLANK_STUB_SUBTICKS_PER_SCANLINE); + let end = (u32::from(subtick + 1) * u32::from(HCOUNTER_DOTS_PER_LINE)) + / u32::from(VBLANK_STUB_SUBTICKS_PER_SCANLINE); + let target = u32::from(target.min(HCOUNTER_DOTS_PER_LINE.saturating_sub(1))); + target >= start && target < end +} + +fn hcounter_midpoint_for_subtick(subtick: u16) -> u16 { + let start = (u32::from(subtick) * u32::from(HCOUNTER_DOTS_PER_LINE)) + / u32::from(VBLANK_STUB_SUBTICKS_PER_SCANLINE); + let end = (u32::from(subtick + 1) * u32::from(HCOUNTER_DOTS_PER_LINE)) + / u32::from(VBLANK_STUB_SUBTICKS_PER_SCANLINE); + let midpoint = start + ((end - start).saturating_sub(1) / 2); + midpoint as u16 +} + +fn counter_byte(counter: u16, high: bool) -> u8 { + if high { + ((counter >> 8) & 0x01) as u8 + } else { + counter as u8 + } +} + +fn dma_transfer_offsets(pattern: u8) -> &'static [u8] { + match pattern & 0x07 { + 0 => &[0], + 1 => &[0, 1], + 2 | 6 => &[0, 0], + 3 | 7 => &[0, 0, 1, 1], + 4 => &[0, 1, 2, 3], + 5 => &[0, 1, 0, 1], + _ => &[0], + } +} + +#[cfg(test)] +mod tests { + use super::{ + AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS, AUTO_JOYPAD_START, Bus, + CPU_MASTER_CLOCKS_PER_CYCLE_FAST, STANDARD_CONTROLLER_PAYLOAD_BITS, + STANDARD_CONTROLLER_PORT_COUNT, VBLANK_STUB_ACTIVE_START, VBLANK_STUB_PERIOD, + VBLANK_STUB_SUBTICKS_PER_SCANLINE, VIDEO_MASTER_CLOCKS_PER_SUBTICK, + }; + use crate::{ + Cartridge, PresentedBackdropLine, PresentedBg1Line, PresentedColorWindowLine, + PresentedMainScreenLine, apu::SMP_IPL_ENTRY_DELAY_CPU_CYCLES, + }; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + + fn test_cartridge() -> Cartridge { + let mut rom = vec![0; 0x8000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"WRAM BUS TEST "); + rom[0x7FD5] = 0x30; + rom[0x7FD8] = 0x03; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&0x8000_u16.to_le_bytes()); + Cartridge::from_bytes(&rom).unwrap() + } + + fn test_sa1_cartridge() -> Cartridge { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"SA1 BUS TEST "); + rom[0x7FD5] = 0x23; + rom[0x7FD6] = 0x34; + rom[0x7FD7] = 0x0C; + rom[0x7FD8] = 0x03; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&0x8000_u16.to_le_bytes()); + Cartridge::from_bytes(&rom).unwrap() + } + + #[test] + fn low_ram_mirrors_and_full_wram_alias_each_other() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x000123, 0x5A); + assert_eq!(bus.read(0x7E0123), 0x5A); + + bus.write(0x7E1ABC, 0xC3); + assert_eq!(bus.read(0x001ABC), 0xC3); + + bus.write(0x7F0001, 0x99); + assert_eq!(bus.read(0x7F0001), 0x99); + } + + #[test] + fn cartridge_sram_reads_writes_through_cpu_bus() { + let mut bus = Bus::new(test_cartridge()); + + assert_eq!(bus.read(0x700456), 0x00); + bus.write(0x700456, 0xA5); + + assert_eq!(bus.read(0x700456), 0xA5); + assert_eq!(bus.read(0x702456), 0xA5); + } + + #[test] + fn sa1_timer_ticks_with_video_stub() { + let mut bus = Bus::new(test_sa1_cartridge()); + + bus.write(0x002212, 0x7F); + bus.write(0x002213, 0x00); + bus.write(0x002214, 0x00); + bus.write(0x002215, 0x00); + bus.write(0x002210, 0x03); + + bus.tick_video_stub(); + + assert_eq!(bus.read(0x002301) & 0x40, 0x40); + assert_eq!(bus.read(0x002302), 0x7F); + assert_eq!(bus.read(0x002304), 0x00); + } + + #[test] + fn apu_ports_expose_ipl_ready_word_after_boot_and_mirrors() { + let mut bus = Bus::new(test_cartridge()); + + // Ports start at zero; the SPC700 writes the ready values during IPL boot. + assert_eq!(bus.read(0x002140), 0x00); + assert_eq!(bus.read(0x002141), 0x00); + assert_eq!(bus.read(0x002142), 0x00); + + // Let the SPC700 boot so it writes the ready values to the ports. + // The IPL ROM loop runs 239 times (X from 0xEF to 0x00), each iteration ~4-5 cycles. + for _ in 0..1500 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xAA); + assert_eq!(bus.read(0x002141), 0xBB); + assert_eq!(bus.peek(0x802144), 0xAA); + assert_eq!(bus.read(0x80217D), 0xBB); + assert_eq!(bus.read(0x00217F), 0x00); + } + + #[test] + fn apu_ipl_acknowledges_upload_then_stops_echoing_after_entry() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + assert_eq!(bus.read(0x002140), 0xCC); + assert_eq!(bus.read(0x002141), 0x00); + + bus.write(0x002141, 0x42); + bus.write(0x002140, 0x00); + assert_eq!(bus.read(0x002140), 0x00); + + bus.write(0x002141, 0x99); + bus.write(0x002140, 0x01); + assert_eq!(bus.read(0x002140), 0x01); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x80); + bus.write(0x002141, 0x00); + bus.write(0x002140, 0x05); + assert_eq!(bus.read(0x002140), 0x05); + + bus.write(0x002140, 0x77); + assert_eq!(bus.read(0x002140), 0x05); + } + + #[test] + fn apu_ipl_upload_stores_data_bytes_in_apu_ram() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + + bus.write(0x002141, 0xDE); + bus.write(0x002140, 0x00); + bus.write(0x002141, 0xAD); + bus.write(0x002140, 0x01); + + assert_eq!(bus.apu.peek_ram(0x0200), 0xDE); + assert_eq!(bus.apu.peek_ram(0x0201), 0xAD); + } + + #[test] + fn apu_ipl_upload_continues_with_new_block_address() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + bus.write(0x002141, 0x11); + bus.write(0x002140, 0x00); + + bus.write(0x002142, 0x10); + bus.write(0x002143, 0x03); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0x03); + assert_eq!(bus.read(0x002140), 0x03); + + bus.write(0x002141, 0x22); + bus.write(0x002140, 0x00); + + assert_eq!(bus.apu.peek_ram(0x0200), 0x11); + assert_eq!(bus.apu.peek_ram(0x0310), 0x22); + } + + #[test] + fn apu_ipl_upload_wraps_to_next_page_after_index_ff() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + + for index in 0..=u8::MAX { + bus.write(0x002141, index.wrapping_add(1)); + bus.write(0x002140, index); + } + bus.write(0x002141, 0x5A); + bus.write(0x002140, 0x00); + + assert_eq!(bus.apu.peek_ram(0x0200), 0x01); + assert_eq!(bus.apu.peek_ram(0x02FF), 0x00); + assert_eq!(bus.apu.peek_ram(0x0300), 0x5A); + } + + #[test] + fn apu_reset_restores_ports_to_zero_and_starts_spc700() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + assert_eq!(bus.read(0x002140), 0xCC); + + bus.reset_ephemeral_state(); + + // After reset, ports are zero and SPC700 starts IPL boot. + assert_eq!(bus.read(0x002140), 0x00); + assert_eq!(bus.read(0x002141), 0x00); + + // After letting the SPC700 boot, it writes the ready values. + for _ in 0..1500 { + bus.tick_cpu_cycle(); + } + assert_eq!(bus.read(0x002140), 0xAA); + assert_eq!(bus.read(0x002141), 0xBB); + } + + #[test] + fn apu_smp_ports_bridge_cpu_communication() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002140, 0x12); + bus.write(0x002141, 0x34); + bus.write(0x002142, 0x56); + bus.write(0x002143, 0x78); + assert_eq!(bus.apu.read_smp(0x00F4), 0x12); + assert_eq!(bus.apu.read_smp(0x00F5), 0x34); + assert_eq!(bus.apu.read_smp(0x00F6), 0x56); + assert_eq!(bus.apu.read_smp(0x00F7), 0x78); + + bus.apu.write_smp(0x00F4, 0x9A); + bus.apu.write_smp(0x00F5, 0xBC); + bus.apu.write_smp(0x00F6, 0xDE); + bus.apu.write_smp(0x00F7, 0xF0); + assert_eq!(bus.apu.peek_ram(0x00F4), 0x9A); + assert_eq!(bus.apu.peek_ram(0x00F5), 0xBC); + assert_eq!(bus.apu.peek_ram(0x00F6), 0xDE); + assert_eq!(bus.apu.peek_ram(0x00F7), 0xF0); + assert_eq!(bus.read(0x002140), 0x9A); + assert_eq!(bus.read(0x002141), 0xBC); + assert_eq!(bus.read(0x002142), 0xDE); + assert_eq!(bus.read(0x002143), 0xF0); + } + + #[test] + fn apu_smp_control_resets_cpu_input_latches() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002140, 0x12); + bus.write(0x002141, 0x34); + bus.write(0x002142, 0x56); + bus.write(0x002143, 0x78); + + bus.apu.write_smp(0x00F1, 0x10); + assert_eq!(bus.apu.read_smp(0x00F4), 0x00); + assert_eq!(bus.apu.read_smp(0x00F5), 0x00); + assert_eq!(bus.apu.read_smp(0x00F6), 0x56); + assert_eq!(bus.apu.read_smp(0x00F7), 0x78); + + bus.apu.write_smp(0x00F1, 0x20); + assert_eq!(bus.apu.read_smp(0x00F6), 0x00); + assert_eq!(bus.apu.read_smp(0x00F7), 0x00); + } + + #[test] + fn apu_smp_dspaddr_reads_full_address_and_data_uses_lower_window() { + let mut bus = Bus::new(test_cartridge()); + + bus.apu.write_smp(0x00F2, 0x12); + bus.apu.write_smp(0x00F3, 0xAB); + assert_eq!(bus.apu.read_smp(0x00F2), 0x12); + assert_eq!(bus.apu.read_smp(0x00F3), 0xAB); + + bus.apu.write_smp(0x00F2, 0x92); + assert_eq!(bus.apu.read_smp(0x00F2), 0x92); + assert_eq!(bus.apu.read_smp(0x00F3), 0xAB); + bus.apu.write_smp(0x00F3, 0xCD); + assert_eq!(bus.apu.read_smp(0x00F3), 0xAB); + } + + #[test] + fn apu_smp_aux_and_ram_are_readable_storage() { + let mut bus = Bus::new(test_cartridge()); + + bus.apu.write_smp(0x00F8, 0x12); + bus.apu.write_smp(0x00F9, 0x34); + bus.apu.write_smp(0x0200, 0x56); + + assert_eq!(bus.apu.read_smp(0x00F8), 0x12); + assert_eq!(bus.apu.read_smp(0x00F9), 0x34); + assert_eq!(bus.apu.read_smp(0x0200), 0x56); + } + + #[test] + fn apu_smp_timer_outputs_increment_and_reset_on_read() { + let mut bus = Bus::new(test_cartridge()); + + bus.apu.write_smp(0x00FC, 0x01); + bus.apu.write_smp(0x00F1, 0x04); + for _ in 0..(56 * 3) { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.read_smp(0x00FF), 0x03); + assert_eq!(bus.apu.read_smp(0x00FF), 0x00); + } + + #[test] + fn apu_smp_timer_disable_preserves_output_and_reenable_resets_divider() { + let mut bus = Bus::new(test_cartridge()); + + bus.apu.write_smp(0x00FA, 0x02); + bus.apu.write_smp(0x00F1, 0x01); + for _ in 0..(448 * 2) { + bus.tick_cpu_cycle(); + } + bus.apu.write_smp(0x00F1, 0x00); + + assert_eq!(bus.apu.read_smp(0x00FD), 0x01); + assert_eq!(bus.apu.read_smp(0x00FD), 0x00); + + bus.apu.write_smp(0x00F1, 0x01); + for _ in 0..447 { + bus.tick_cpu_cycle(); + } + assert_eq!(bus.apu.read_smp(0x00FD), 0x00); + bus.tick_cpu_cycle(); + assert_eq!(bus.apu.read_smp(0x00FD), 0x00); + for _ in 0..448 { + bus.tick_cpu_cycle(); + } + assert_eq!(bus.apu.read_smp(0x00FD), 0x01); + } + + #[test] + fn apu_smp_timer_source_clock_free_runs_while_disabled() { + let mut bus = Bus::new(test_cartridge()); + + bus.apu.write_smp(0x00FA, 0x01); + bus.apu.write_smp(0x00F1, 0x01); + for _ in 0..100 { + bus.tick_cpu_cycle(); + } + bus.apu.write_smp(0x00F1, 0x00); + for _ in 0..300 { + bus.tick_cpu_cycle(); + } + + bus.apu.write_smp(0x00F1, 0x01); + for _ in 0..47 { + bus.tick_cpu_cycle(); + } + assert_eq!(bus.apu.read_smp(0x00FD), 0x00); + bus.tick_cpu_cycle(); + assert_eq!(bus.apu.read_smp(0x00FD), 0x01); + } + + #[test] + fn bulk_cpu_cycle_step_matches_single_cycle_apu_timer_progress() { + let mut single = Bus::new(test_cartridge()); + let mut bulk = Bus::new(test_cartridge()); + + for bus in [&mut single, &mut bulk] { + bus.apu.write_smp(0x00FC, 0x03); + bus.apu.write_smp(0x00F1, 0x04); + } + for _ in 0..(56 * 4 + 19) { + single.tick_cpu_cycle(); + } + bulk.step_cpu_cycles(56 * 4 + 19); + + assert_eq!(bulk.apu.read_smp(0x00FF), single.apu.read_smp(0x00FF)); + assert_eq!(bulk.apu.read_smp(0x00FF), single.apu.read_smp(0x00FF)); + } + + #[test] + fn bulk_cpu_cycle_step_matches_single_cycle_math_completion() { + let mut single = Bus::new(test_cartridge()); + let mut bulk = Bus::new(test_cartridge()); + + for bus in [&mut single, &mut bulk] { + bus.write(0x004202, 0x12); + bus.write(0x004203, 0x34); + } + for _ in 0..8 { + single.tick_cpu_cycle(); + } + bulk.step_cpu_cycles(8); + + assert_eq!(bulk.read(0x004216), single.read(0x004216)); + assert_eq!(bulk.read(0x004217), single.read(0x004217)); + } + + #[test] + fn bulk_cpu_cycle_step_keeps_nmi_pending_after_vblank_window() { + fn cycles_for_subticks(subticks: u32) -> u32 { + (subticks * VIDEO_MASTER_CLOCKS_PER_SUBTICK).div_ceil(CPU_MASTER_CLOCKS_PER_CYCLE_FAST) + } + + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004200, 0x80); + + bus.step_cpu_cycles(cycles_for_subticks(u32::from(VBLANK_STUB_PERIOD) + 1)); + + assert!(bus.poll_nmi()); + assert!(!bus.poll_nmi()); + } + + fn upload_and_start_apu_program(bus: &mut Bus, entry: u16, program: &[u8]) { + assert!(program.len() <= 0x100); + + bus.write(0x002142, entry as u8); + bus.write(0x002143, (entry >> 8) as u8); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + for (index, value) in program.iter().copied().enumerate() { + bus.write(0x002141, value); + bus.write(0x002140, index as u8); + } + + let kick = ((program.len() as u8).wrapping_add(2)) | 1; + bus.write(0x002142, entry as u8); + bus.write(0x002143, (entry >> 8) as u8); + bus.write(0x002141, 0x00); + bus.write(0x002140, kick); + tick_cpu_cycles(bus, SMP_IPL_ENTRY_DELAY_CPU_CYCLES); + } + + #[test] + fn apu_runs_minimal_smp_code_after_ipl_entry() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x01); + bus.write(0x002140, 0xCC); + for (index, value) in [0x8F, 0x5A, 0xF4, 0xFF].into_iter().enumerate() { + bus.write(0x002141, value); + bus.write(0x002140, index as u8); + } + + bus.write(0x002142, 0x00); + bus.write(0x002143, 0x02); + bus.write(0x002141, 0x00); + bus.write(0x002140, 0x06); + + for _ in 0..(SMP_IPL_ENTRY_DELAY_CPU_CYCLES / 2) { + bus.tick_cpu_cycle(); + } + assert_eq!(bus.read(0x002140), 0x06); + tick_cpu_cycles(&mut bus, SMP_IPL_ENTRY_DELAY_CPU_CYCLES); + assert_eq!(bus.read(0x002140), 0x5A); + bus.apu.write_smp(0x00F4, 0xA5); + assert_eq!(bus.read(0x002140), 0xA5); + } + + #[test] + fn apu_spc700_ipl_rom_overlays_high_ram_when_enabled() { + let mut bus = Bus::new(test_cartridge()); + + assert_eq!(bus.apu.read_smp(0xFFC0), 0xCD); + assert_eq!(bus.apu.read_smp(0xFFFE), 0xC0); + assert_eq!(bus.apu.read_smp(0xFFFF), 0xFF); + + bus.apu.write_smp(0xFFC0, 0x42); + assert_eq!(bus.apu.peek_ram(0xFFC0), 0x42); + assert_eq!(bus.apu.read_smp(0xFFC0), 0xCD); + + bus.apu.write_smp(0x00F1, 0x00); + assert_eq!(bus.apu.read_smp(0xFFC0), 0x42); + + bus.apu.write_smp(0x00F1, 0x80); + assert_eq!(bus.apu.read_smp(0xFFC0), 0xCD); + } + + #[test] + fn apu_spc700_ipl_enable_reenters_high_level_loader() { + let mut bus = Bus::new(test_cartridge()); + let reenter_ipl = [ + 0x8F, 0x80, 0xF1, // MOV $F1,#$80 + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &reenter_ipl); + tick_cpu_cycles(&mut bus, 8); + + assert_eq!(bus.read(0x002140), 0xAA); + assert_eq!(bus.read(0x002141), 0xBB); + + let second_program = [ + 0x8F, 0x5A, 0xF4, // MOV $F4,#$5A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0300, &second_program); + tick_cpu_cycles(&mut bus, 8); + + assert_eq!(bus.read(0x002140), 0x5A); + } + + #[test] + fn apu_spc700_polling_loop_acknowledges_cpu_command() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE4, 0xF4, // MOV A,$F4 + 0x68, 0x7E, // CMP A,#$7E + 0xD0, 0xFA, // BNE $0200 + 0x8F, 0xA5, 0xF4, // MOV $F4,#$A5 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..12 { + bus.tick_cpu_cycle(); + } + assert_ne!(bus.read(0x002140), 0xA5); + + bus.write(0x002140, 0x7E); + for _ in 0..12 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xA5); + } + + #[test] + fn apu_spc700_index_loop_runs_until_zero() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xCD, 0x03, // MOV X,#$03 + 0x1D, // DEC X + 0xD0, 0xFD, // BNE DEC X + 0xE8, 0x5A, // MOV A,#$5A + 0xC4, 0xF4, // MOV $F4,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..200 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x5A); + } + + #[test] + fn apu_spc700_direct_page_flag_selects_page() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0x11, // MOV A,#$11 + 0xC4, 0x10, // MOV $10,A + 0x40, // SETP + 0xE8, 0x22, // MOV A,#$22 + 0xC4, 0x10, // MOV $110,A + 0xE4, 0x10, // MOV A,$110 + 0x20, // CLRP + 0xC4, 0xF4, // MOV $F4,A + 0xE4, 0x10, // MOV A,$10 + 0xC4, 0xF5, // MOV $F5,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..16 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x22); + assert_eq!(bus.read(0x002141), 0x11); + } + + #[test] + fn apu_spc700_absolute_store_and_compare() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xCD, 0x42, // MOV X,#$42 + 0xC9, 0x00, 0x03, // MOV $0300,X + 0xE8, 0x42, // MOV A,#$42 + 0x65, 0x00, 0x03, // CMP A,$0300 + 0xD0, 0x04, // BNE failure + 0x8F, 0xA5, 0xF4, // MOV $F4,#$A5 + 0xFF, // STOP + 0x8F, 0x00, 0xF4, // failure: MOV $F4,#$00 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..12 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xA5); + } + + #[test] + fn apu_spc700_compares_direct_immediate_and_ya_word() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x05, 0x10, // MOV $10,#$05 + 0x8F, 0x05, 0x11, // MOV $11,#$05 + 0x69, 0x11, 0x10, // CMP $10,$11 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF4, // MOV $F4,A + 0x8F, 0x05, 0x12, // MOV $12,#$05 + 0x78, 0x06, 0x10, // CMP $10,#$06 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF5, // MOV $F5,A + 0x8F, 0x34, 0x20, // MOV $20,#$34 + 0x8F, 0x34, 0x21, // MOV $21,#$34 + 0xCD, 0x20, // MOV X,#$20 + 0x8D, 0x21, // MOV Y,#$21 + 0x79, // CMP (X),(Y) + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF6, // MOV $F6,A + 0x8F, 0x34, 0x30, // MOV $30,#$34 + 0x8F, 0x12, 0x31, // MOV $31,#$12 + 0xE8, 0x34, // MOV A,#$34 + 0x8D, 0x12, // MOV Y,#$12 + 0x5A, 0x30, // CMPW YA,$30 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF7, // MOV $F7,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..200 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140) & 0x83, 0x03); + assert_eq!(bus.read(0x002141) & 0x83, 0x80); + assert_eq!(bus.read(0x002142) & 0x83, 0x03); + assert_eq!(bus.read(0x002143) & 0x83, 0x03); + } + + #[test] + fn apu_spc700_memory_alu_modes_update_destination() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x12, 0x01, // MOV $01,#$12 + 0x8F, 0x34, 0x02, // MOV $02,#$34 + 0x60, // CLRC + 0x89, 0x02, 0x01, // ADC $01,$02 + 0xE4, 0x01, // MOV A,$01 + 0xC4, 0xF4, // MOV $F4,A + 0x8F, 0xC0, 0x03, // MOV $03,#$C0 + 0x18, 0x0F, 0x03, // OR $03,#$0F + 0xE4, 0x03, // MOV A,$03 + 0xC4, 0xF5, // MOV $F5,A + 0x8F, 0xF0, 0x04, // MOV $04,#$F0 + 0x8F, 0x0F, 0x05, // MOV $05,#$0F + 0x49, 0x05, 0x04, // EOR $04,$05 + 0xE4, 0x04, // MOV A,$04 + 0xC4, 0xF6, // MOV $F6,A + 0x8F, 0xF0, 0x06, // MOV $06,#$F0 + 0x8F, 0x0F, 0x07, // MOV $07,#$0F + 0xCD, 0x06, // MOV X,#$06 + 0x8D, 0x07, // MOV Y,#$07 + 0x39, // AND (X),(Y) + 0xE4, 0x06, // MOV A,$06 + 0xC4, 0xF7, // MOV $F7,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..64 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x46); + assert_eq!(bus.read(0x002141), 0xCF); + assert_eq!(bus.read(0x002142), 0xFF); + assert_eq!(bus.read(0x002143), 0x00); + } + + #[test] + fn apu_spc700_word_add_sub_updates_ya_and_flags() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0xFF, 0x20, // MOV $20,#$FF + 0x8F, 0x00, 0x21, // MOV $21,#$00 + 0xE8, 0x12, // MOV A,#$12 + 0x8D, 0x34, // MOV Y,#$34 + 0x7A, 0x20, // ADDW YA,$20 + 0xC4, 0xF4, // MOV $F4,A + 0xCB, 0xF5, // MOV $F5,Y + 0x8F, 0x01, 0x22, // MOV $22,#$01 + 0x8F, 0x00, 0x23, // MOV $23,#$00 + 0x9A, 0x22, // SUBW YA,$22 + 0xC4, 0xF6, // MOV $F6,A + 0xCB, 0xF7, // MOV $F7,Y + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..48 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x11); + assert_eq!(bus.read(0x002141), 0x35); + assert_eq!(bus.read(0x002142), 0x10); + assert_eq!(bus.read(0x002143), 0x35); + } + + #[test] + fn apu_spc700_call_ret_restores_stack_and_resumes() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0x10, // MOV A,#$10 + 0x3F, 0x0B, 0x02, // CALL $020B + 0xC4, 0xF4, // MOV $F4,A + 0x9D, // MOV X,SP + 0xD8, 0xF5, // MOV $F5,X + 0xFF, // STOP + 0xBC, // subroutine: INC A + 0x6F, // RET + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..16 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x11); + assert_eq!(bus.read(0x002141), 0xEF); + assert_eq!(bus.apu.peek_ram(0x01EF), 0x02); + assert_eq!(bus.apu.peek_ram(0x01EE), 0x05); + } + + #[test] + fn apu_spc700_push_pop_round_trips_registers_and_psw() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xCD, 0x12, // MOV X,#$12 + 0x4D, // PUSH X + 0xCD, 0x00, // MOV X,#$00 + 0xCE, // POP X + 0xD8, 0xF6, // MOV $F6,X + 0x8D, 0x34, // MOV Y,#$34 + 0x6D, // PUSH Y + 0x8D, 0x00, // MOV Y,#$00 + 0xEE, // POP Y + 0xCB, 0xF7, // MOV $F7,Y + 0xE8, 0x80, // MOV A,#$80 + 0x2D, // PUSH A + 0xE8, 0x00, // MOV A,#$00 + 0xAE, // POP A + 0xC4, 0xF5, // MOV $F5,A + 0xE8, 0x80, // MOV A,#$80 + 0x0D, // PUSH PSW + 0xE8, 0x00, // MOV A,#$00 + 0x8E, // POP PSW + 0x10, 0x04, // BPL failure + 0x8F, 0xA5, 0xF4, // MOV $F4,#$A5 + 0xFF, // STOP + 0x8F, 0x00, 0xF4, // failure: MOV $F4,#$00 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..40 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xA5); + assert_eq!(bus.read(0x002141), 0x80); + assert_eq!(bus.read(0x002142), 0x12); + assert_eq!(bus.read(0x002143), 0x34); + } + + #[test] + fn apu_spc700_pop_registers_preserve_psw_flags() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0x98, // MOV A,#$98 + 0x2D, // PUSH A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xAE, // POP A + 0xC5, 0x20, 0x03, // MOV $0320,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x21, 0x03, // MOV $0321,A + 0xE8, 0x98, // MOV A,#$98 + 0x2D, // PUSH A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xCE, // POP X + 0xC9, 0x22, 0x03, // MOV $0322,X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x23, 0x03, // MOV $0323,A + 0xE8, 0x98, // MOV A,#$98 + 0x2D, // PUSH A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xEE, // POP Y + 0xCC, 0x24, 0x03, // MOV $0324,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x25, 0x03, // MOV $0325,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xAE, // POP A + 0xC5, 0x26, 0x03, // MOV $0326,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x27, 0x03, // MOV $0327,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..120 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0320), 0x98); + assert_eq!(bus.apu.peek_ram(0x0321), 0x00); + assert_eq!(bus.apu.peek_ram(0x0322), 0x98); + assert_eq!(bus.apu.peek_ram(0x0323), 0x00); + assert_eq!(bus.apu.peek_ram(0x0324), 0x98); + assert_eq!(bus.apu.peek_ram(0x0325), 0x00); + assert_eq!(bus.apu.peek_ram(0x0326), 0x00); + assert_eq!(bus.apu.peek_ram(0x0327), 0xFF); + } + + #[test] + fn apu_spc700_decimal_adjust_matches_bcd_flags() { + let mut bus = Bus::new(test_cartridge()); + let cases = [ + (0xDF, 0x10, 0x00, 0x10, 0x00), + (0xDF, 0x1A, 0x00, 0x20, 0x00), + (0xDF, 0x10, 0x01, 0x70, 0x01), + (0xDF, 0x10, 0x09, 0x76, 0x09), + (0xDF, 0xFF, 0xF6, 0x65, 0x75), + (0xDF, 0x9A, 0x00, 0x00, 0x03), + (0xDF, 0x91, 0x01, 0xF1, 0x81), + (0xDF, 0x9A, 0x08, 0x00, 0x0B), + (0xDF, 0x99, 0x08, 0x9F, 0x88), + (0xBE, 0x10, 0x09, 0x10, 0x09), + (0xBE, 0x1A, 0x09, 0x14, 0x09), + (0xBE, 0xA1, 0xFF, 0x41, 0x7C), + (0xBE, 0xFF, 0x09, 0x99, 0x88), + (0xBE, 0x99, 0x00, 0x33, 0x00), + (0xBE, 0x9A, 0x01, 0x34, 0x00), + (0xBE, 0x66, 0x00, 0x00, 0x02), + (0xBE, 0x11, 0x00, 0xAB, 0x80), + ]; + let mut program = Vec::new(); + for (index, (opcode, input_a, input_psw, _, _)) in cases.iter().copied().enumerate() { + let address = 0x0340_u16 + (index as u16 * 2); + let [result_low, result_high] = address.to_le_bytes(); + let [psw_low, psw_high] = address.wrapping_add(1).to_le_bytes(); + program.extend_from_slice(&[ + 0xE8, + input_psw, // MOV A,#psw + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xE8, + input_a, // MOV A,#input + opcode, + 0xC5, + result_low, + result_high, // MOV result,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, + psw_low, + psw_high, // MOV psw,A + ]); + } + program.push(0xFF); + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..600 { + bus.tick_cpu_cycle(); + } + + for (index, (_, _, _, expected_a, expected_psw)) in cases.iter().copied().enumerate() { + let address = 0x0340_u16 + (index as u16 * 2); + assert_eq!(bus.apu.peek_ram(address), expected_a); + assert_eq!(bus.apu.peek_ram(address + 1), expected_psw); + } + } + + #[test] + fn apu_spc700_div_ya_x_matches_overflow_and_divide_by_zero() { + let mut bus = Bus::new(test_cartridge()); + let cases = [ + (0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0xC8), + (0x23, 0x10, 0x01, 0x00, 0x12, 0x03, 0x08), + (0x10, 0x88, 0x01, 0xFF, 0x02, 0x00, 0x35), + (0x0F, 0x88, 0x01, 0xFF, 0x01, 0x87, 0x35), + (0x23, 0x01, 0x01, 0x00, 0x23, 0x00, 0x48), + (0xFF, 0x00, 0xFF, 0x00, 0x00, 0xFF, 0x4A), + (0xCD, 0x03, 0xAB, 0x00, 0x58, 0xC5, 0x48), + ]; + let mut program = Vec::new(); + for (index, (input_a, input_x, input_y, input_psw, _, _, _)) in + cases.iter().copied().enumerate() + { + let address = 0x0370_u16 + (index as u16 * 4); + let [a_low, a_high] = address.to_le_bytes(); + let [x_low, x_high] = address.wrapping_add(1).to_le_bytes(); + let [y_low, y_high] = address.wrapping_add(2).to_le_bytes(); + let [psw_low, psw_high] = address.wrapping_add(3).to_le_bytes(); + program.extend_from_slice(&[ + 0xE8, input_psw, // MOV A,#psw + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xCD, input_x, // MOV X,#input_x + 0x8D, input_y, // MOV Y,#input_y + 0xE8, input_a, // MOV A,#input_a + 0x9E, // DIV YA,X + 0xC5, a_low, a_high, // MOV result_a,A + 0xC9, x_low, x_high, // MOV result_x,X + 0xCC, y_low, y_high, // MOV result_y,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, psw_low, psw_high, // MOV result_psw,A + ]); + } + program.push(0xFF); + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..700 { + bus.tick_cpu_cycle(); + } + + for (index, (_, expected_x, _, _, expected_a, expected_y, expected_psw)) in + cases.iter().copied().enumerate() + { + let address = 0x0370_u16 + (index as u16 * 4); + assert_eq!(bus.apu.peek_ram(address), expected_a); + assert_eq!(bus.apu.peek_ram(address + 1), expected_x); + assert_eq!(bus.apu.peek_ram(address + 2), expected_y); + assert_eq!(bus.apu.peek_ram(address + 3), expected_psw); + } + } + + #[test] + fn apu_spc700_psw_control_ops_update_status_bits() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xC0, // DI + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x20, 0x03, // MOV $0320,A + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xA0, // EI + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x21, 0x03, // MOV $0321,A + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xED, // NOTC + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x22, 0x03, // MOV $0322,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xC0, // DI + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x23, 0x03, // MOV $0323,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xA0, // EI + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x24, 0x03, // MOV $0324,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xED, // NOTC + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x25, 0x03, // MOV $0325,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..96 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0320), 0xFB); + assert_eq!(bus.apu.peek_ram(0x0321), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0322), 0xFE); + assert_eq!(bus.apu.peek_ram(0x0323), 0x00); + assert_eq!(bus.apu.peek_ram(0x0324), 0x04); + assert_eq!(bus.apu.peek_ram(0x0325), 0x01); + } + + #[test] + fn apu_spc700_mul_ya_sets_result_and_high_byte_nz() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xE8, 0xAB, // MOV A,#$AB + 0x8D, 0xCD, // MOV Y,#$CD + 0xCF, // MUL YA + 0xC5, 0x20, 0x03, // MOV $0320,A + 0xCC, 0x21, 0x03, // MOV $0321,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x22, 0x03, // MOV $0322,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xE8, 0x05, // MOV A,#$05 + 0x8D, 0x02, // MOV Y,#$02 + 0xCF, // MUL YA + 0xC5, 0x23, 0x03, // MOV $0323,A + 0xCC, 0x24, 0x03, // MOV $0324,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x25, 0x03, // MOV $0325,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xE8, 0xFF, // MOV A,#$FF + 0x8D, 0xFF, // MOV Y,#$FF + 0xCF, // MUL YA + 0xC5, 0x26, 0x03, // MOV $0326,A + 0xCC, 0x27, 0x03, // MOV $0327,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x28, 0x03, // MOV $0328,A + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xE8, 0x80, // MOV A,#$80 + 0x8D, 0x02, // MOV Y,#$02 + 0xCF, // MUL YA + 0xC5, 0x29, 0x03, // MOV $0329,A + 0xCC, 0x2A, 0x03, // MOV $032A,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x2B, 0x03, // MOV $032B,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..160 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0320), 0xEF); + assert_eq!(bus.apu.peek_ram(0x0321), 0x88); + assert_eq!(bus.apu.peek_ram(0x0322), 0xFD); + assert_eq!(bus.apu.peek_ram(0x0323), 0x0A); + assert_eq!(bus.apu.peek_ram(0x0324), 0x00); + assert_eq!(bus.apu.peek_ram(0x0325), 0x02); + assert_eq!(bus.apu.peek_ram(0x0326), 0x01); + assert_eq!(bus.apu.peek_ram(0x0327), 0xFE); + assert_eq!(bus.apu.peek_ram(0x0328), 0x80); + assert_eq!(bus.apu.peek_ram(0x0329), 0x00); + assert_eq!(bus.apu.peek_ram(0x032A), 0x01); + assert_eq!(bus.apu.peek_ram(0x032B), 0x00); + } + + #[test] + fn apu_spc700_pcall_and_tcall_use_stack_vectors() { + let mut bus = Bus::new(test_cartridge()); + for (offset, value) in [0x8F, 0x11, 0xF4, 0x6F].into_iter().enumerate() { + bus.apu.write_smp(0xFF80 + offset as u16, value); + } + for (offset, value) in [0x8F, 0x22, 0xF5, 0x6F].into_iter().enumerate() { + bus.apu.write_smp(0x0300 + offset as u16, value); + } + bus.apu.write_smp(0xFFDE, 0x00); + bus.apu.write_smp(0xFFDF, 0x03); + + let program = [ + 0x4F, 0x80, // PCALL $80 + 0x01, // TCALL 0 + 0x8F, 0xA5, 0xF6, // MOV $F6,#$A5 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..24 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0x11); + assert_eq!(bus.read(0x002141), 0x22); + assert_eq!(bus.read(0x002142), 0xA5); + } + + #[test] + fn apu_spc700_absolute_indexed_indirect_jump_wraps_pointer() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xCD, 0xFF, // MOV X,#$FF + 0x1F, 0x00, 0xFF, // JMP [$FF00+X] + 0x8F, 0xEE, 0xF4, // fail: MOV $F4,#$EE + 0xFF, // STOP + 0x8F, 0xA5, 0xF4, // success: MOV $F4,#$A5 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + bus.apu.write_smp(0xFFFF, 0x09); + bus.apu.write_smp(0x0000, 0x02); + + for _ in 0..16 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xA5); + } + + #[test] + fn apu_spc700_brk_pushes_return_psw_and_vectors() { + let mut bus = Bus::new(test_cartridge()); + bus.apu.write_smp(0xFFDE, 0x00); + bus.apu.write_smp(0xFFDF, 0x03); + let target = [ + 0x0D, // PUSH PSW + 0xAE, // POP A + 0x20, // CLRP so result stores use page 0 + 0xC4, 0x20, // MOV $20,A + 0x9D, // MOV X,SP + 0xD8, 0x21, // MOV $21,X + 0xE5, 0xED, 0x01, // MOV A,$01ED + 0xC4, 0x22, // MOV $22,A + 0xE5, 0xEE, 0x01, // MOV A,$01EE + 0xC4, 0x23, // MOV $23,A + 0xE5, 0xEF, 0x01, // MOV A,$01EF + 0xC4, 0x24, // MOV $24,A + 0xFF, // STOP + ]; + for (offset, value) in target.into_iter().enumerate() { + bus.apu.write_smp(0x0300 + offset as u16, value); + } + + let program = [ + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0x0F, // BRK + 0xFF, // STOP if BRK fails to vector + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0020), 0xFB); + assert_eq!(bus.apu.peek_ram(0x0021), 0xEC); + assert_eq!(bus.apu.peek_ram(0x0022), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0023), 0x05); + assert_eq!(bus.apu.peek_ram(0x0024), 0x02); + } + + #[test] + fn apu_spc700_logical_alu_handles_immediate_and_direct_operands() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0x0F, // MOV A,#$0F + 0x08, 0xF0, // OR A,#$F0 + 0xC4, 0xF4, // MOV $F4,A + 0x28, 0x3C, // AND A,#$3C + 0xC4, 0xF5, // MOV $F5,A + 0x8F, 0x55, 0x10, // MOV $10,#$55 + 0x44, 0x10, // EOR A,$10 + 0xC4, 0xF6, // MOV $F6,A + 0x24, 0x10, // AND A,$10 + 0xC4, 0xF7, // MOV $F7,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..20 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.read(0x002140), 0xFF); + assert_eq!(bus.read(0x002141), 0x3C); + assert_eq!(bus.read(0x002142), 0x69); + assert_eq!(bus.read(0x002143), 0x41); + } + + #[test] + fn apu_spc700_logical_alu_handles_indexed_and_absolute_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0012, 0xF0), + (0x0013, 0x3C), + (0x0310, 0xF0), + (0x0402, 0x3C), + (0x0503, 0x3C), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0x8D, 0x03, // MOV Y,#$03 + 0xE8, 0x0F, // MOV A,#$0F + 0x14, 0x10, // OR A,$10+X + 0xC4, 0x20, // MOV $20,A + 0xE8, 0x0F, // MOV A,#$0F + 0x15, 0x0E, 0x03, // OR A,!$030E+X + 0xC4, 0x21, // MOV $21,A + 0xE8, 0x0F, // MOV A,#$0F + 0x16, 0x0D, 0x03, // OR A,!$030D+Y + 0xC4, 0x22, // MOV $22,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x34, 0x11, // AND A,$11+X + 0xC4, 0x23, // MOV $23,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x35, 0x00, 0x04, // AND A,!$0400+X + 0xC4, 0x24, // MOV $24,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x36, 0x00, 0x05, // AND A,!$0500+Y + 0xC4, 0x25, // MOV $25,A + 0xE8, 0x55, // MOV A,#$55 + 0x54, 0x10, // EOR A,$10+X + 0xC4, 0x26, // MOV $26,A + 0xE8, 0x55, // MOV A,#$55 + 0x55, 0x0E, 0x03, // EOR A,!$030E+X + 0xC4, 0x27, // MOV $27,A + 0xE8, 0x55, // MOV A,#$55 + 0x56, 0x0D, 0x03, // EOR A,!$030D+Y + 0xC4, 0x28, // MOV $28,A + 0xE8, 0x0F, // MOV A,#$0F + 0x05, 0x10, 0x03, // OR A,!$0310 + 0xC4, 0x29, // MOV $29,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x25, 0x02, 0x04, // AND A,!$0402 + 0xC4, 0x2A, // MOV $2A,A + 0xE8, 0x55, // MOV A,#$55 + 0x45, 0x10, 0x03, // EOR A,!$0310 + 0xC4, 0x2B, // MOV $2B,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + for address in 0x0020..=0x0022 { + assert_eq!(bus.apu.peek_ram(address), 0xFF); + } + for address in 0x0023..=0x0025 { + assert_eq!(bus.apu.peek_ram(address), 0x30); + } + for address in 0x0026..=0x0028 { + assert_eq!(bus.apu.peek_ram(address), 0xA5); + } + assert_eq!(bus.apu.peek_ram(0x0029), 0xFF); + assert_eq!(bus.apu.peek_ram(0x002A), 0x30); + assert_eq!(bus.apu.peek_ram(0x002B), 0xA5); + } + + #[test] + fn apu_spc700_logical_alu_handles_indirect_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0004, 0xF0), + (0x0012, 0x00), + (0x0013, 0x04), + (0x0020, 0x00), + (0x0021, 0x05), + (0x0400, 0x0F), + (0x0503, 0x33), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x04, // MOV X,#$04 + 0x8D, 0x03, // MOV Y,#$03 + 0xE8, 0x0F, // MOV A,#$0F + 0x06, // OR A,(X) + 0xC4, 0x40, // MOV $40,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x07, 0x0E, // OR A,($0E+X) + 0xC4, 0x41, // MOV $41,A + 0xE8, 0xCC, // MOV A,#$CC + 0x17, 0x20, // OR A,($20)+Y + 0xC4, 0x42, // MOV $42,A + 0xE8, 0xF3, // MOV A,#$F3 + 0x26, // AND A,(X) + 0xC4, 0x43, // MOV $43,A + 0xE8, 0xF3, // MOV A,#$F3 + 0x27, 0x0E, // AND A,($0E+X) + 0xC4, 0x44, // MOV $44,A + 0xE8, 0xF3, // MOV A,#$F3 + 0x37, 0x20, // AND A,($20)+Y + 0xC4, 0x45, // MOV $45,A + 0xE8, 0x0F, // MOV A,#$0F + 0x46, // EOR A,(X) + 0xC4, 0x46, // MOV $46,A + 0xE8, 0xF0, // MOV A,#$F0 + 0x47, 0x0E, // EOR A,($0E+X) + 0xC4, 0x47, // MOV $47,A + 0xE8, 0x55, // MOV A,#$55 + 0x57, 0x20, // EOR A,($20)+Y + 0xC4, 0x48, // MOV $48,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..140 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0040), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0041), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0042), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0043), 0xF0); + assert_eq!(bus.apu.peek_ram(0x0044), 0x03); + assert_eq!(bus.apu.peek_ram(0x0045), 0x33); + assert_eq!(bus.apu.peek_ram(0x0046), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0047), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0048), 0x66); + } + + #[test] + fn apu_spc700_mov_loads_indirect_and_indexed_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0004, 0x66), + (0x0012, 0x00), + (0x0013, 0x04), + (0x0020, 0x00), + (0x0021, 0x05), + (0x0304, 0x99), + (0x0400, 0x77), + (0x0403, 0xAA), + (0x0503, 0x88), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x04, // MOV X,#$04 + 0x8D, 0x03, // MOV Y,#$03 + 0xE6, // MOV A,(X) + 0xC4, 0x30, // MOV $30,A + 0xE7, 0x0E, // MOV A,($0E+X) + 0xC4, 0x31, // MOV $31,A + 0xF7, 0x20, // MOV A,($20)+Y + 0xC4, 0x32, // MOV $32,A + 0xF5, 0x00, 0x03, // MOV A,!$0300+X + 0xC4, 0x33, // MOV $33,A + 0xF6, 0x00, 0x04, // MOV A,!$0400+Y + 0xC4, 0x34, // MOV $34,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0030), 0x66); + assert_eq!(bus.apu.peek_ram(0x0031), 0x77); + assert_eq!(bus.apu.peek_ram(0x0032), 0x88); + assert_eq!(bus.apu.peek_ram(0x0033), 0x99); + assert_eq!(bus.apu.peek_ram(0x0034), 0xAA); + } + + #[test] + fn apu_spc700_mov_stores_indirect_and_indexed_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0012, 0x00), + (0x0013, 0x06), + (0x0020, 0x00), + (0x0021, 0x07), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0x8D, 0x03, // MOV Y,#$03 + 0xE8, 0xA1, // MOV A,#$A1 + 0xC6, // MOV (X),A + 0xE8, 0xB2, // MOV A,#$B2 + 0xC7, 0x10, // MOV ($10+X),A + 0xE8, 0xC3, // MOV A,#$C3 + 0xD7, 0x20, // MOV ($20)+Y,A + 0xE8, 0xD4, // MOV A,#$D4 + 0xD5, 0x00, 0x08, // MOV !$0800+X,A + 0xE8, 0xE5, // MOV A,#$E5 + 0xD6, 0x00, 0x09, // MOV !$0900+Y,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..90 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0002), 0xA1); + assert_eq!(bus.apu.peek_ram(0x0600), 0xB2); + assert_eq!(bus.apu.peek_ram(0x0703), 0xC3); + assert_eq!(bus.apu.peek_ram(0x0802), 0xD4); + assert_eq!(bus.apu.peek_ram(0x0903), 0xE5); + } + + #[test] + fn apu_spc700_adc_sbc_cmp_handle_indirect_and_indexed_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0002, 0x01), + (0x0012, 0x00), + (0x0013, 0x06), + (0x0020, 0x00), + (0x0021, 0x07), + (0x0032, 0x40), + (0x0600, 0x02), + (0x0703, 0x03), + (0x0802, 0x50), + (0x0903, 0x60), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0x8D, 0x03, // MOV Y,#$03 + 0x60, // CLRC + 0xE8, 0x01, // MOV A,#$01 + 0x86, // ADC A,(X) + 0xC4, 0x40, // MOV $40,A + 0x60, // CLRC + 0xE8, 0x01, // MOV A,#$01 + 0x87, 0x10, // ADC A,($10+X) + 0xC4, 0x41, // MOV $41,A + 0x60, // CLRC + 0xE8, 0x01, // MOV A,#$01 + 0x97, 0x20, // ADC A,($20)+Y + 0xC4, 0x42, // MOV $42,A + 0x80, // SETC + 0xE8, 0x05, // MOV A,#$05 + 0xA6, // SBC A,(X) + 0xC4, 0x43, // MOV $43,A + 0x80, // SETC + 0xE8, 0x05, // MOV A,#$05 + 0xA7, 0x10, // SBC A,($10+X) + 0xC4, 0x44, // MOV $44,A + 0x80, // SETC + 0xE8, 0x05, // MOV A,#$05 + 0xB7, 0x20, // SBC A,($20)+Y + 0xC4, 0x45, // MOV $45,A + 0xE8, 0x40, // MOV A,#$40 + 0x74, 0x30, // CMP A,$30+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x50, // MOV $50,A + 0xE8, 0x60, // MOV A,#$60 + 0x75, 0x00, 0x08, // CMP A,!$0800+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x51, // MOV $51,A + 0xE8, 0x50, // MOV A,#$50 + 0x76, 0x00, 0x09, // CMP A,!$0900+Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x52, // MOV $52,A + 0xE8, 0x01, // MOV A,#$01 + 0x66, // CMP A,(X) + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x53, // MOV $53,A + 0xE8, 0x02, // MOV A,#$02 + 0x67, 0x10, // CMP A,($10+X) + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x54, // MOV $54,A + 0xE8, 0x03, // MOV A,#$03 + 0x77, 0x20, // CMP A,($20)+Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x55, // MOV $55,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..220 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0040), 0x02); + assert_eq!(bus.apu.peek_ram(0x0041), 0x03); + assert_eq!(bus.apu.peek_ram(0x0042), 0x04); + assert_eq!(bus.apu.peek_ram(0x0043), 0x04); + assert_eq!(bus.apu.peek_ram(0x0044), 0x03); + assert_eq!(bus.apu.peek_ram(0x0045), 0x02); + assert_eq!(bus.apu.peek_ram(0x0050) & 0x83, 0x03); + assert_eq!(bus.apu.peek_ram(0x0051) & 0x83, 0x01); + assert_eq!(bus.apu.peek_ram(0x0052) & 0x83, 0x80); + assert_eq!(bus.apu.peek_ram(0x0053) & 0x83, 0x03); + assert_eq!(bus.apu.peek_ram(0x0054) & 0x83, 0x03); + assert_eq!(bus.apu.peek_ram(0x0055) & 0x83, 0x03); + } + + #[test] + fn apu_spc700_inc_dec_memory_wraps_and_sets_flags() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [(0x0010, 0x00), (0x0012, 0x80), (0x0300, 0xFF)] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0xAB, 0x10, // INC $10 + 0xAC, 0x00, 0x03, // INC !$0300 + 0xBB, 0x10, // INC $10+X + 0x8B, 0x10, // DEC $10 + 0x8C, 0x00, 0x03, // DEC !$0300 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x40, // MOV $40,A + 0x9B, 0x10, // DEC $10+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x41, // MOV $41,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0010), 0x00); + assert_eq!(bus.apu.peek_ram(0x0012), 0x80); + assert_eq!(bus.apu.peek_ram(0x0300), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0040) & 0x82, 0x80); + assert_eq!(bus.apu.peek_ram(0x0041) & 0x82, 0x80); + } + + #[test] + fn apu_spc700_adc_sets_carry_halfcarry_and_overflow_flags() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x60, // CLRC + 0xE8, 0x7F, // MOV A,#$7F + 0x88, 0x01, // ADC A,#$01 + 0xC4, 0xF4, // MOV $F4,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF5, // MOV $F5,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..12 { + bus.tick_cpu_cycle(); + } + + let psw = bus.read(0x002141); + assert_eq!(bus.read(0x002140), 0x80); + assert_eq!(psw & 0x01, 0); + assert_eq!(psw & 0x02, 0); + assert_ne!(psw & 0x08, 0); + assert_ne!(psw & 0x40, 0); + assert_ne!(psw & 0x80, 0); + } + + #[test] + fn apu_spc700_sbc_uses_carry_as_not_borrow() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x80, // SETC + 0xE8, 0x10, // MOV A,#$10 + 0xA8, 0x01, // SBC A,#$01 + 0xC4, 0xF4, // MOV $F4,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF5, // MOV $F5,A + 0x60, // CLRC + 0xE8, 0x00, // MOV A,#$00 + 0x8F, 0x00, 0x10, // MOV $10,#$00 + 0xA4, 0x10, // SBC A,$10 + 0xC4, 0xF6, // MOV $F6,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0xF7, // MOV $F7,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..28 { + bus.tick_cpu_cycle(); + } + + let no_borrow_psw = bus.read(0x002141); + let borrow_psw = bus.read(0x002143); + assert_eq!(bus.read(0x002140), 0x0F); + assert_ne!(no_borrow_psw & 0x01, 0); + assert_eq!(no_borrow_psw & 0x0A, 0); + assert_eq!(bus.read(0x002142), 0xFF); + assert_eq!(borrow_psw & 0x01, 0); + assert_eq!(borrow_psw & 0x02, 0); + assert_ne!(borrow_psw & 0x80, 0); + } + + #[test] + fn apu_spc700_adc_sbc_handle_indexed_and_absolute_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0012, 0x01), + (0x0310, 0x02), + (0x0402, 0x03), + (0x0503, 0x04), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0x8D, 0x03, // MOV Y,#$03 + 0x60, // CLRC + 0xE8, 0x10, // MOV A,#$10 + 0x94, 0x10, // ADC A,$10+X + 0xC4, 0x30, // MOV $30,A + 0x60, // CLRC + 0xE8, 0x10, // MOV A,#$10 + 0x85, 0x10, 0x03, // ADC A,!$0310 + 0xC4, 0x31, // MOV $31,A + 0x60, // CLRC + 0xE8, 0x10, // MOV A,#$10 + 0x95, 0x00, 0x04, // ADC A,!$0400+X + 0xC4, 0x32, // MOV $32,A + 0x60, // CLRC + 0xE8, 0x10, // MOV A,#$10 + 0x96, 0x00, 0x05, // ADC A,!$0500+Y + 0xC4, 0x33, // MOV $33,A + 0x80, // SETC + 0xE8, 0x10, // MOV A,#$10 + 0xB4, 0x10, // SBC A,$10+X + 0xC4, 0x34, // MOV $34,A + 0x80, // SETC + 0xE8, 0x10, // MOV A,#$10 + 0xA5, 0x10, 0x03, // SBC A,!$0310 + 0xC4, 0x35, // MOV $35,A + 0x80, // SETC + 0xE8, 0x10, // MOV A,#$10 + 0xB5, 0x00, 0x04, // SBC A,!$0400+X + 0xC4, 0x36, // MOV $36,A + 0x80, // SETC + 0xE8, 0x10, // MOV A,#$10 + 0xB6, 0x00, 0x05, // SBC A,!$0500+Y + 0xC4, 0x37, // MOV $37,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0030), 0x11); + assert_eq!(bus.apu.peek_ram(0x0031), 0x12); + assert_eq!(bus.apu.peek_ram(0x0032), 0x13); + assert_eq!(bus.apu.peek_ram(0x0033), 0x14); + assert_eq!(bus.apu.peek_ram(0x0034), 0x0F); + assert_eq!(bus.apu.peek_ram(0x0035), 0x0E); + assert_eq!(bus.apu.peek_ram(0x0036), 0x0D); + assert_eq!(bus.apu.peek_ram(0x0037), 0x0C); + } + + #[test] + fn apu_spc700_movw_incw_decw_transfer_words() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x34, 0x20, // MOV $20,#$34 + 0x8F, 0x12, 0x21, // MOV $21,#$12 + 0xBA, 0x20, // MOVW YA,$20 + 0xDA, 0x22, // MOVW $22,YA + 0x3A, 0x22, // INCW $22 + 0x1A, 0x22, // DECW $22 + 0xBA, 0x22, // MOVW YA,$22 + 0xC4, 0xF4, // MOV $F4,A + 0xCB, 0xF5, // MOV $F5,Y + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..24 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0022), 0x34); + assert_eq!(bus.apu.peek_ram(0x0023), 0x12); + assert_eq!(bus.read(0x002140), 0x34); + assert_eq!(bus.read(0x002141), 0x12); + } + + #[test] + fn apu_spc700_word_ops_set_16bit_flags_and_wrap_direct_page() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x40, // SETP + 0x8F, 0xFF, 0xFF, // MOV $FF,#$FF + 0x8F, 0xFF, 0x00, // MOV $00,#$FF + 0x3A, 0xFF, // INCW $FF + 0x0D, // PUSH PSW + 0xAE, // POP A + 0x20, // CLRP + 0xC4, 0xF4, // MOV $F4,A + 0x40, // SETP + 0x1A, 0xFF, // DECW $FF + 0x0D, // PUSH PSW + 0xAE, // POP A + 0x20, // CLRP + 0xC4, 0xF5, // MOV $F5,A + 0x40, // SETP + 0xBA, 0xFF, // MOVW YA,$FF + 0x20, // CLRP + 0xC4, 0xF6, // MOV $F6,A + 0xCB, 0xF7, // MOV $F7,Y + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..200 { + bus.tick_cpu_cycle(); + } + + let zero_psw = bus.read(0x002140); + let negative_psw = bus.read(0x002141); + assert_ne!(zero_psw & 0x02, 0); + assert_eq!(zero_psw & 0x80, 0); + assert_eq!(negative_psw & 0x02, 0); + assert_ne!(negative_psw & 0x80, 0); + assert_eq!(bus.apu.peek_ram(0x01FF), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0100), 0xFF); + assert_eq!(bus.read(0x002142), 0xFF); + assert_eq!(bus.read(0x002143), 0xFF); + } + + #[test] + fn apu_spc700_shift_rotate_accumulator_and_xcn() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0xE8, 0x81, // MOV A,#$81 + 0x1C, // ASL A + 0xC4, 0x20, // MOV $20,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x21, // MOV $21,A + 0xE8, 0x01, // MOV A,#$01 + 0x5C, // LSR A + 0xC4, 0x22, // MOV $22,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x23, // MOV $23,A + 0x80, // SETC + 0xE8, 0x40, // MOV A,#$40 + 0x3C, // ROL A + 0xC4, 0x24, // MOV $24,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x25, // MOV $25,A + 0x60, // CLRC + 0xE8, 0x01, // MOV A,#$01 + 0x7C, // ROR A + 0xC4, 0x26, // MOV $26,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x27, // MOV $27,A + 0xE8, 0x3C, // MOV A,#$3C + 0x9F, // XCN A + 0xC4, 0x28, // MOV $28,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..48 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0020), 0x02); + assert_ne!(bus.apu.peek_ram(0x0021) & 0x01, 0); + assert_eq!(bus.apu.peek_ram(0x0022), 0x00); + assert_ne!(bus.apu.peek_ram(0x0023) & 0x01, 0); + assert_ne!(bus.apu.peek_ram(0x0023) & 0x02, 0); + assert_eq!(bus.apu.peek_ram(0x0024), 0x81); + assert_eq!(bus.apu.peek_ram(0x0025) & 0x01, 0); + assert_ne!(bus.apu.peek_ram(0x0025) & 0x80, 0); + assert_eq!(bus.apu.peek_ram(0x0026), 0x00); + assert_ne!(bus.apu.peek_ram(0x0027) & 0x01, 0); + assert_ne!(bus.apu.peek_ram(0x0027) & 0x02, 0); + assert_eq!(bus.apu.peek_ram(0x0028), 0xC3); + } + + #[test] + fn apu_spc700_shift_rotate_direct_operands() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x80, 0x30, // MOV $30,#$80 + 0x0B, 0x30, // ASL $30 + 0x8F, 0x01, 0x31, // MOV $31,#$01 + 0x4B, 0x31, // LSR $31 + 0x80, // SETC + 0x8F, 0x80, 0x32, // MOV $32,#$80 + 0x2B, 0x32, // ROL $32 + 0x80, // SETC + 0x8F, 0x01, 0x33, // MOV $33,#$01 + 0x6B, 0x33, // ROR $33 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..32 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0030), 0x00); + assert_eq!(bus.apu.peek_ram(0x0031), 0x00); + assert_eq!(bus.apu.peek_ram(0x0032), 0x01); + assert_eq!(bus.apu.peek_ram(0x0033), 0x80); + } + + #[test] + fn apu_spc700_shift_rotate_indexed_and_absolute_operands() { + let mut bus = Bus::new(test_cartridge()); + for (address, value) in [ + (0x0000, 0x80), + (0x0001, 0xFF), + (0x0101, 0x80), + (0x0400, 0x01), + (0x0401, 0x01), + ] { + bus.apu.write_smp(address, value); + } + + let program = [ + 0xCD, 0x02, // MOV X,#$02 + 0x1B, 0xFF, // ASL $FF+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x20, // MOV $20,A + 0x40, // SETP + 0x1B, 0xFF, // ASL $FF+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0x20, // CLRP + 0xC4, 0x21, // MOV $21,A + 0x4C, 0x00, 0x04, // LSR $0400 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x22, // MOV $22,A + 0x80, // SETC + 0x3B, 0xFE, // ROL $FE+X + 0x60, // CLRC + 0x6C, 0x01, 0x04, // ROR $0401 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x23, // MOV $23,A + 0x80, // SETC + 0x7B, 0xFF, // ROR $FF+X + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x24, // MOV $24,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..120 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0020) & 0x83, 0x81); + assert_eq!(bus.apu.peek_ram(0x0021) & 0xA3, 0x23); + assert_eq!(bus.apu.peek_ram(0x0022) & 0x83, 0x03); + assert_eq!(bus.apu.peek_ram(0x0023) & 0x83, 0x03); + assert_eq!(bus.apu.peek_ram(0x0024) & 0x83, 0x80); + assert_eq!(bus.apu.peek_ram(0x0000), 0x01); + assert_eq!(bus.apu.peek_ram(0x0001), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0101), 0x00); + assert_eq!(bus.apu.peek_ram(0x0400), 0x00); + assert_eq!(bus.apu.peek_ram(0x0401), 0x00); + } + + #[test] + fn apu_spc700_absolute_bit_ops_update_carry_and_memory() { + let mut bus = Bus::new(test_cartridge()); + bus.apu.write_smp(0x0102, 0x0C); + + let program = [ + 0x80, // SETC + 0x4A, 0x02, 0x41, // AND1 C,$0102.2 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x20, // MOV $20,A + 0x80, // SETC + 0x6A, 0x02, 0x41, // AND1 C,/$0102.2 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x21, // MOV $21,A + 0x60, // CLRC + 0x0A, 0x02, 0x41, // OR1 C,$0102.2 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x22, // MOV $22,A + 0x80, // SETC + 0x8A, 0x02, 0x41, // EOR1 C,$0102.2 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x23, // MOV $23,A + 0xAA, 0x02, 0x41, // MOV1 C,$0102.2 + 0xCA, 0x02, 0x61, // MOV1 $0102.3,C + 0x60, // CLRC + 0xCA, 0x02, 0x61, // MOV1 $0102.3,C + 0xEA, 0x02, 0x41, // NOT1 $0102.2 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_ne!(bus.apu.peek_ram(0x0020) & 0x01, 0); + assert_eq!(bus.apu.peek_ram(0x0021) & 0x01, 0); + assert_ne!(bus.apu.peek_ram(0x0022) & 0x01, 0); + assert_eq!(bus.apu.peek_ram(0x0023) & 0x01, 0); + assert_eq!(bus.apu.peek_ram(0x0102), 0x00); + } + + #[test] + fn apu_spc700_direct_bit_set_clear_and_branch_use_direct_page() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x00, 0x10, // MOV $10,#$00 + 0x02, 0x10, // SET1 $10.0 + 0x22, 0x10, // SET1 $10.1 + 0x12, 0x10, // CLR1 $10.0 + 0x03, 0x10, 0x03, // BBS $10.0,skip + 0x8F, 0xA1, 0x20, // MOV $20,#$A1 + 0x23, 0x10, 0x03, // BBS $10.1,skip + 0x8F, 0xEE, 0x20, // MOV $20,#$EE + 0x33, 0x10, 0x03, // BBC $10.1,skip + 0x8F, 0xA2, 0x21, // MOV $21,#$A2 + 0x13, 0x10, 0x03, // BBC $10.0,skip + 0x8F, 0xEE, 0x21, // MOV $21,#$EE + 0x40, // SETP + 0xC2, 0x11, // SET1 $11.6 + 0x20, // CLRP + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..80 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0010), 0x02); + assert_eq!(bus.apu.peek_ram(0x0020), 0xA1); + assert_eq!(bus.apu.peek_ram(0x0021), 0xA2); + assert_eq!(bus.apu.peek_ram(0x0111), 0x40); + } + + #[test] + fn apu_spc700_tset_tclr_update_memory_and_nz_from_test() { + let mut bus = Bus::new(test_cartridge()); + bus.apu.write_smp(0x0300, 0x11); + bus.apu.write_smp(0x0301, 0x05); + let program = [ + 0xE8, 0x09, // MOV A,#$09 + 0x0E, 0x00, 0x03, // TSET1 $0300 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x20, // MOV $20,A + 0xE8, 0x15, // MOV A,#$15 + 0x4E, 0x01, 0x03, // TCLR1 $0301 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x21, // MOV $21,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..36 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0300), 0x19); + assert_eq!(bus.apu.peek_ram(0x0301), 0x00); + assert_ne!(bus.apu.peek_ram(0x0020) & 0x80, 0); + assert_eq!(bus.apu.peek_ram(0x0020) & 0x02, 0); + assert_eq!(bus.apu.peek_ram(0x0021) & 0x82, 0); + } + + #[test] + fn apu_spc700_cbne_branches_without_changing_flags() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x80, // SETC + 0xE8, 0x12, // MOV A,#$12 + 0x8F, 0x13, 0x10, // MOV $10,#$13 + 0x2E, 0x10, 0x03, // CBNE $10,skip + 0x8F, 0xEE, 0x20, // MOV $20,#$EE + 0x8F, 0xA1, 0x20, // MOV $20,#$A1 + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC4, 0x24, // MOV $24,A + 0xE8, 0x80, // MOV A,#$80 + 0x8F, 0x80, 0x11, // MOV $11,#$80 + 0x2E, 0x11, 0x03, // CBNE $11,fail + 0x8F, 0xA2, 0x21, // MOV $21,#$A2 + 0x2F, 0x03, // BRA skip_fail + 0x8F, 0xEE, 0x21, // MOV $21,#$EE + 0xCD, 0x02, // MOV X,#$02 + 0xE8, 0xFF, // MOV A,#$FF + 0x8F, 0x00, 0x01, // MOV $01,#$00 + 0xDE, 0xFF, 0x03, // CBNE $FF+X,skip + 0x8F, 0xEE, 0x22, // MOV $22,#$EE + 0x8F, 0xA3, 0x22, // MOV $22,#$A3 + 0x40, // SETP + 0xCD, 0x04, // MOV X,#$04 + 0x8F, 0x00, 0x03, // MOV $03,#$00 + 0xDE, 0xFF, 0x06, // CBNE $FF+X,skip + 0x20, // CLRP + 0x8F, 0xEE, 0x23, // MOV $23,#$EE + 0x2F, 0x04, // BRA done + 0x20, // CLRP + 0x8F, 0xA4, 0x23, // MOV $23,#$A4 + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..140 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x0020), 0xA1); + assert_eq!(bus.apu.peek_ram(0x0021), 0xA2); + assert_eq!(bus.apu.peek_ram(0x0022), 0xA3); + assert_eq!(bus.apu.peek_ram(0x0023), 0xA4); + assert_eq!(bus.apu.peek_ram(0x0024) & 0x83, 0x01); + assert_eq!(bus.apu.peek_ram(0x0103), 0x00); + } + + #[test] + fn apu_spc700_dbnz_decrements_and_branches_without_flags() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8D, 0x00, // MOV Y,#$00 + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xFE, 0x05, // DBNZ Y,skip_fail + 0xE8, 0xEE, // fail: MOV A,#$EE + 0xC5, 0x2F, 0x03, // MOV $032F,A + 0xCC, 0x20, 0x03, // MOV $0320,Y + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x21, 0x03, // MOV $0321,A + 0x8D, 0x01, // MOV Y,#$01 + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0xFE, 0x05, // DBNZ Y,skip_capture + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x23, 0x03, // MOV $0323,A + 0xCC, 0x22, 0x03, // MOV $0322,Y + 0xE8, 0x00, // MOV A,#$00 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0x8F, 0x00, 0x10, // MOV $10,#$00 + 0x6E, 0x10, 0x05, // DBNZ $10,skip_fail + 0xE8, 0xEE, // fail: MOV A,#$EE + 0xC5, 0x2F, 0x03, // MOV $032F,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x30, 0x03, // MOV $0330,A + 0xE8, 0x01, // MOV A,#$01 + 0x2D, // PUSH A + 0x8E, // POP PSW + 0x8F, 0x01, 0x12, // MOV $12,#$01 + 0x6E, 0x12, 0x05, // DBNZ $12,skip_capture + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x32, 0x03, // MOV $0332,A + 0xE8, 0x00, // MOV A,#$00 + 0xC5, 0x02, 0x01, // MOV $0102,A + 0xE8, 0xFF, // MOV A,#$FF + 0x2D, // PUSH A + 0x8E, // POP PSW + 0x6E, 0x02, 0x05, // DBNZ $02,skip_fail + 0xE8, 0xEE, // fail: MOV A,#$EE + 0xC5, 0x2F, 0x03, // MOV $032F,A + 0x0D, // PUSH PSW + 0xAE, // POP A + 0xC5, 0x31, 0x03, // MOV $0331,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..180 { + bus.tick_cpu_cycle(); + } + + assert_eq!(bus.apu.peek_ram(0x032F), 0x00); + assert_eq!(bus.apu.peek_ram(0x0320), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0321), 0x00); + assert_eq!(bus.apu.peek_ram(0x0322), 0x00); + assert_eq!(bus.apu.peek_ram(0x0323), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0010), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0330), 0x00); + assert_eq!(bus.apu.peek_ram(0x0012), 0x00); + assert_eq!(bus.apu.peek_ram(0x0332), 0x01); + assert_eq!(bus.apu.peek_ram(0x0102), 0xFF); + assert_eq!(bus.apu.peek_ram(0x0331), 0xFF); + } + + #[test] + fn apu_spc700_program_can_wait_for_timer_output() { + let mut bus = Bus::new(test_cartridge()); + let program = [ + 0x8F, 0x02, 0xFC, // MOV $FC,#$02 + 0x8F, 0x04, 0xF1, // MOV $F1,#$04 + 0xE4, 0xFF, // MOV A,$FF + 0xF0, 0xFC, // BEQ read timer again + 0xC4, 0xF4, // MOV $F4,A + 0xFF, // STOP + ]; + upload_and_start_apu_program(&mut bus, 0x0200, &program); + + for _ in 0..160 { + bus.tick_cpu_cycle(); + } + + assert_ne!(bus.read(0x002140), 0x00); + } + + #[test] + fn cartridge_sram_reads_writes_through_dma_abus() { + let mut bus = Bus::new(test_cartridge()); + + bus.dma_write_abus(0x700321, 0x3C); + + assert_eq!(bus.dma_read_abus(0x700321), 0x3C); + assert_eq!(bus.read(0x702321), 0x3C); + } + + #[test] + fn apu_ports_are_accessible_through_dma_bbus() { + let mut bus = Bus::new(test_cartridge()); + + // Let the SPC700 boot so it writes the ready values to the ports. + for _ in 0..1500 { + bus.tick_cpu_cycle(); + } + + bus.write(0x002141, 0x01); + bus.write(0x7E1000, 0xCC); + setup_dma_ch0(&mut bus, 0x00, 0x40, 0x7E1000, 1); + bus.write(0x00420B, 0x01); + assert_eq!(bus.read(0x002140), 0xCC); + + setup_dma_ch0(&mut bus, 0x80, 0x40, 0x7E1001, 1); + bus.write(0x00420B, 0x01); + assert_eq!(bus.read(0x7E1001), 0xCC); + + bus.dma_write_bbus(0x2142, 0x34); + bus.dma_write_bbus(0x2143, 0x12); + assert_eq!(bus.dma_read_bbus(0x2140), 0xCC); + assert_eq!(bus.dma_read_bbus(0x2141), 0xBB); + assert_eq!(bus.dma_read_bbus(0x2142), 0x00); + assert_eq!(bus.dma_read_bbus(0x2143), 0x00); + } + + #[test] + fn multiply_registers_update_rdmpy_on_wrmpyb_write() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004202, 0x12); + bus.write(0x004203, 0x34); + + tick_cpu_cycles(&mut bus, 8); + assert_eq!(bus.read(0x004216), 0xA8); + assert_eq!(bus.read(0x004217), 0x03); + } + + #[test] + fn multiply_result_is_not_visible_until_eight_cpu_cycles_elapse() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004202, 0x12); + bus.write(0x004203, 0x34); + + tick_cpu_cycles(&mut bus, 7); + assert_eq!(bus.read(0x004216), 0x00); + assert_eq!(bus.read(0x004217), 0x00); + + tick_cpu_cycles(&mut bus, 1); + assert_eq!(bus.read(0x004216), 0xA8); + assert_eq!(bus.read(0x004217), 0x03); + } + + #[test] + fn wrmpyb_write_seven_cycles_after_previous_multiply_clears_result() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004202, 0xFF); + bus.write(0x004203, 0xFF); + tick_cpu_cycles(&mut bus, 7); + bus.write(0x004203, 0x80); + tick_cpu_cycles(&mut bus, 8); + + assert_eq!(bus.read(0x004216), 0x00); + assert_eq!(bus.read(0x004217), 0x00); + } + + #[test] + fn wrmpyb_write_six_cycles_after_previous_multiply_starts_new_result() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004202, 0xFF); + bus.write(0x004203, 0xFF); + tick_cpu_cycles(&mut bus, 6); + bus.write(0x004203, 0x80); + tick_cpu_cycles(&mut bus, 8); + + assert_eq!(bus.read(0x004216), 0x80); + assert_eq!(bus.read(0x004217), 0x7F); + } + + #[test] + fn divide_registers_update_rddiv_and_rdmpy_on_wrdivb_write() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004204, 0x34); + bus.write(0x004205, 0x12); + bus.write(0x004206, 0x12); + + tick_cpu_cycles(&mut bus, 16); + assert_eq!(bus.read(0x004214), 0x02); + assert_eq!(bus.read(0x004215), 0x01); + assert_eq!(bus.read(0x004216), 0x10); + assert_eq!(bus.read(0x004217), 0x00); + } + + #[test] + fn divide_by_zero_returns_full_quotient_and_dividend_remainder() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004204, 0xAD); + bus.write(0x004205, 0xDE); + bus.write(0x004206, 0x00); + + tick_cpu_cycles(&mut bus, 16); + assert_eq!(bus.read(0x004214), 0xFF); + assert_eq!(bus.read(0x004215), 0xFF); + assert_eq!(bus.read(0x004216), 0xAD); + assert_eq!(bus.read(0x004217), 0xDE); + } + + #[test] + fn vblank_stub_allows_wait_loops_to_observe_both_edges() { + let mut bus = Bus::new(test_cartridge()); + + assert_eq!(bus.read(0x004210), 0x40); + assert_eq!(bus.read(0x004212), 0x00); + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert_eq!(bus.read(0x004210), 0xC0); + assert_eq!(bus.read(0x004212), 0x80); + for _ in 0..(VBLANK_STUB_PERIOD - VBLANK_STUB_ACTIVE_START) { + bus.tick_video_stub(); + } + assert_eq!(bus.read(0x004210), 0x40); + assert_eq!(bus.read(0x004218), 0x00); + } + + #[test] + fn auto_joy_hvbjoy_bit_becomes_active_then_clears_during_early_vblank() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004200, 0x01); + + tick_subticks(&mut bus, VBLANK_STUB_ACTIVE_START); + assert_eq!(bus.read(0x004212), 0x80); + + tick_subticks(&mut bus, 1); + assert_eq!(bus.read(0x004212), 0x81); + + tick_subticks( + &mut bus, + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS.saturating_sub(1)), + ); + assert_eq!(bus.read(0x004212), 0x81); + + tick_subticks(&mut bus, 1); + assert_eq!(bus.read(0x004212), 0x80); + } + + #[test] + fn auto_joy_completion_latches_joy_registers_to_zero() { + let mut bus = Bus::new(test_cartridge()); + bus.cpu_io_registers[0x18..0x20].fill(0xFF); + bus.write(0x004200, 0x01); + + tick_subticks( + &mut bus, + AUTO_JOYPAD_START + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS), + ); + + for offset in 0x4218u16..=0x421Fu16 { + bus.write(u32::from(offset), 0xA5); + assert_eq!( + bus.read(u32::from(offset)), + 0x00, + "JOY register {offset:04X}" + ); + } + } + + #[test] + fn joyout_latch_pulse_resets_the_serial_read_sequence() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + for _ in 0..STANDARD_CONTROLLER_PAYLOAD_BITS { + assert_eq!(bus.read(0x004016), 0x00); + } + assert_eq!(bus.read(0x004016), 0x01); + + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + assert_eq!(bus.read(0x004016), 0x00); + } + + #[test] + fn joyser0_returns_sixteen_zero_bits_then_ones_for_a_no_input_controller() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + for read_index in 0..STANDARD_CONTROLLER_PAYLOAD_BITS { + assert_eq!(bus.read(0x004016), 0x00, "read {}", read_index + 1); + } + assert_eq!(bus.read(0x004016), 0x01); + assert_eq!(bus.read(0x004016), 0x01); + } + + #[test] + fn manual_read_sequence_uses_standard_controller_bit_order() { + let mut bus = Bus::new(test_cartridge()); + bus.load_standard_controller_ports([0x8080, 0], 0); + + assert_eq!(bus.read(0x004016), 0x01); + for _ in 0..7 { + assert_eq!(bus.read(0x004016), 0x00); + } + assert_eq!(bus.read(0x004016), 0x01); + } + + #[test] + fn standard_controller_buttons_feed_manual_and_autojoy_reads() { + let mut bus = Bus::new(test_cartridge()); + assert!(bus.set_standard_controller_buttons(0, 0x8080)); + assert!(!bus.set_standard_controller_buttons(STANDARD_CONTROLLER_PORT_COUNT, 0x8000)); + + bus.write(0x004016, 0x01); + assert_eq!(bus.read(0x004016), 0x01); + bus.write(0x004016, 0x00); + assert_eq!(bus.read(0x004016), 0x01); + for _ in 0..7 { + assert_eq!(bus.read(0x004016), 0x00); + } + assert_eq!(bus.read(0x004016), 0x01); + + bus.write(0x004200, 0x01); + tick_subticks( + &mut bus, + AUTO_JOYPAD_START + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS), + ); + + assert_eq!(bus.read(0x004218), 0x80); + assert_eq!(bus.read(0x004219), 0x80); + } + + #[test] + fn standard_controller_buttons_survive_bus_reset() { + let mut bus = Bus::new(test_cartridge()); + assert!(bus.set_standard_controller_buttons(0, 0x8000)); + + bus.reset_ephemeral_state(); + bus.write(0x004016, 0x01); + + assert_eq!(bus.read(0x004016), 0x01); + } + + #[test] + fn joyser1_returns_fixed_high_bits_mask_plus_the_serial_bit() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + for read_index in 0..STANDARD_CONTROLLER_PAYLOAD_BITS { + assert_eq!(bus.read(0x004017), 0x1C, "read {}", read_index + 1); + } + assert_eq!(bus.read(0x004017), 0x1D); + assert_eq!(bus.peek(0x004017), 0x1D); + } + + #[test] + fn latch_high_reads_do_not_advance_the_serial_position() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004016, 0x01); + for _ in 0..4 { + assert_eq!(bus.read(0x004016), 0x00); + assert_eq!(bus.read(0x004017), 0x1C); + } + + bus.write(0x004016, 0x00); + for read_index in 0..STANDARD_CONTROLLER_PAYLOAD_BITS { + assert_eq!(bus.read(0x004016), 0x00, "read {}", read_index + 1); + } + assert_eq!(bus.read(0x004016), 0x01); + } + + #[test] + fn auto_joy_completion_leaves_manual_reads_exhausted_until_relatched() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004200, 0x01); + + tick_subticks( + &mut bus, + AUTO_JOYPAD_START + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS), + ); + + assert_eq!(bus.read(0x004016), 0x01); + assert_eq!(bus.read(0x004017), 0x1D); + + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + assert_eq!(bus.read(0x004016), 0x00); + assert_eq!(bus.read(0x004017), 0x1C); + } + + #[test] + fn auto_joy_start_reloads_manual_joyser_state_during_active_window() { + let mut bus = Bus::new(test_cartridge()); + bus.load_standard_controller_ports([0, 0], STANDARD_CONTROLLER_PAYLOAD_BITS); + bus.write(0x004200, 0x01); + + tick_subticks(&mut bus, AUTO_JOYPAD_START + 1); + + assert_eq!(bus.read(0x004212) & 0x01, 0x01); + assert_eq!(bus.read(0x004016), 0x00); + } + + #[test] + fn joyout_relatched_manual_reading_still_works_after_auto_joy_completion() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004200, 0x01); + + tick_subticks( + &mut bus, + AUTO_JOYPAD_START + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS), + ); + + bus.write(0x004016, 0x01); + bus.write(0x004016, 0x00); + + for read_index in 0..STANDARD_CONTROLLER_PAYLOAD_BITS { + assert_eq!(bus.read(0x004016), 0x00, "read {}", read_index + 1); + } + assert_eq!(bus.read(0x004016), 0x01); + } + + #[test] + fn enabling_auto_joy_during_scanline_225_before_start_still_runs_this_frame() { + let mut bus = Bus::new(test_cartridge()); + + tick_subticks(&mut bus, VBLANK_STUB_ACTIVE_START); + assert_eq!(bus.read(0x004212), 0x80); + + bus.write(0x004200, 0x01); + tick_subticks(&mut bus, 1); + + assert_eq!(bus.read(0x004212), 0x81); + } + + #[test] + fn enabling_auto_joy_exactly_at_start_still_runs_this_frame() { + let mut bus = Bus::new(test_cartridge()); + + tick_subticks(&mut bus, AUTO_JOYPAD_START); + assert_eq!(bus.read(0x004212), 0x80); + + bus.write(0x004200, 0x01); + + assert_eq!(bus.read(0x004212), 0x81); + } + + #[test] + fn clearing_auto_joy_before_start_prevents_it_for_that_frame() { + let mut bus = Bus::new(test_cartridge()); + bus.cpu_io_registers[0x18..0x20].fill(0xAA); + bus.write(0x004200, 0x01); + + tick_subticks(&mut bus, VBLANK_STUB_ACTIVE_START); + bus.write(0x004200, 0x00); + tick_subticks( + &mut bus, + 1 + u16::from(AUTO_JOYPAD_ACTIVE_DURATION_SUBTICKS), + ); + + assert_eq!(bus.read(0x004212), 0x80); + for offset in 0x4218u16..=0x421Fu16 { + assert_eq!( + bus.read(u32::from(offset)), + 0xAA, + "JOY register {offset:04X}" + ); + } + } + + // ----------------------------------------------------------------------- + // DMA tests + // ----------------------------------------------------------------------- + + /// Configure helpers: write a DMA channel's register block. + /// + /// `dmap` – DMAP byte (bit7=dir, bits4:3=addr mode, bits2-0=pattern) + /// `bbad` – B-bus address offset from $2100 + /// `a_addr` – 24-bit A-bus source address + /// `count` – DAS byte count (0 means 65536) + fn setup_dma_channel(bus: &mut Bus, channel: u8, dmap: u8, bbad: u8, a_addr: u32, count: u16) { + let base = 0x00_4300 + (u32::from(channel) * 0x10); + bus.write(base, dmap); + bus.write(base + 0x1, bbad); + bus.write(base + 0x2, a_addr as u8); + bus.write(base + 0x3, (a_addr >> 8) as u8); + bus.write(base + 0x4, (a_addr >> 16) as u8); + bus.write(base + 0x5, count as u8); + bus.write(base + 0x6, (count >> 8) as u8); + } + + fn setup_dma_ch0(bus: &mut Bus, dmap: u8, bbad: u8, a_addr: u32, count: u16) { + setup_dma_channel(bus, 0, dmap, bbad, a_addr, count); + } + + fn setup_hdma_channel(bus: &mut Bus, channel: u8, dmap: u8, bbad: u8, table_addr: u32) { + let base = 0x00_4300 + (u32::from(channel) * 0x10); + bus.write(base, dmap); + bus.write(base + 0x1, bbad); + bus.write(base + 0x2, table_addr as u8); + bus.write(base + 0x3, (table_addr >> 8) as u8); + bus.write(base + 0x4, (table_addr >> 16) as u8); + } + + fn tick_into_new_active_frame(bus: &mut Bus) { + bus.video_phase = VBLANK_STUB_PERIOD - 1; + bus.tick_video_stub(); + } + + fn tick_scanline(bus: &mut Bus) { + for _ in 0..VBLANK_STUB_SUBTICKS_PER_SCANLINE { + bus.tick_video_stub(); + } + } + + fn tick_subticks(bus: &mut Bus, count: u16) { + for _ in 0..count { + bus.tick_video_stub(); + } + } + + fn tick_cpu_cycles(bus: &mut Bus, count: u8) { + for _ in 0..count { + bus.tick_cpu_cycle(); + } + } + + #[test] + fn presented_backdrop_lines_capture_scanline_color0_and_inidisp() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2121, 0x00); + bus.write(0x00_2122, 0xFF); + bus.write(0x00_2122, 0x7F); + bus.write(0x00_2100, 0x0F); + + tick_into_new_active_frame(&mut bus); + assert_eq!( + bus.presented_backdrop_line(0), + Some(PresentedBackdropLine { + inidisp: 0x0F, + color0: 0x7FFF, + }) + ); + + bus.write(0x00_2121, 0x00); + bus.write(0x00_2122, 0x1F); + bus.write(0x00_2122, 0x00); + + tick_scanline(&mut bus); + assert_eq!( + bus.presented_backdrop_line(1), + Some(PresentedBackdropLine { + inidisp: 0x0F, + color0: 0x001F, + }) + ); + + bus.write(0x00_2121, 0x00); + bus.write(0x00_2122, 0xE0); + bus.write(0x00_2122, 0x03); + bus.video_phase = VBLANK_STUB_ACTIVE_START - 1; + bus.tick_video_stub(); + tick_into_new_active_frame(&mut bus); + assert_eq!( + bus.presented_backdrop_line(0), + Some(PresentedBackdropLine { + inidisp: 0x0F, + color0: 0x7FFF, + }), + "completed-frame lines take priority over the current partial frame" + ); + assert_eq!( + bus.presented_backdrop_line(1), + Some(PresentedBackdropLine { + inidisp: 0x0F, + color0: 0x001F, + }), + "the API should keep serving the last completed frame until the next one finishes" + ); + assert_eq!( + bus.presented_backdrop_line(2), + None, + "the completed frame should not invent uncaptured lines" + ); + } + + #[test] + fn presented_bg1_lines_capture_scanline_scroll_offsets() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_210D, 0x23); + bus.write(0x00_210D, 0x01); + bus.write(0x00_210E, 0xAB); + bus.write(0x00_210E, 0x02); + + tick_into_new_active_frame(&mut bus); + assert_eq!( + bus.presented_bg1_line(0), + Some(PresentedBg1Line { + hofs: 0x0123, + vofs: 0x02AB, + }) + ); + + bus.write(0x00_210D, 0x45); + bus.write(0x00_210D, 0x03); + bus.write(0x00_210E, 0x67); + bus.write(0x00_210E, 0x00); + + tick_scanline(&mut bus); + assert_eq!( + bus.presented_bg1_line(1), + Some(PresentedBg1Line { + hofs: 0x0345, + vofs: 0x0067, + }) + ); + } + + #[test] + fn presented_lines_capture_bg2_bg3_bg4_scroll_and_main_screen() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_210F, 0x56); + bus.write(0x00_210F, 0x03); + bus.write(0x00_2110, 0x9A); + bus.write(0x00_2110, 0x00); + bus.write(0x00_2111, 0xBC); + bus.write(0x00_2111, 0x02); + bus.write(0x00_2112, 0xDE); + bus.write(0x00_2112, 0x01); + bus.write(0x00_2113, 0x24); + bus.write(0x00_2113, 0x03); + bus.write(0x00_2114, 0x68); + bus.write(0x00_2114, 0x00); + bus.write(0x00_212C, 0x0F); + bus.write(0x00_2126, 0x10); + bus.write(0x00_2127, 0x80); + bus.write(0x00_2128, 0x20); + bus.write(0x00_2129, 0x90); + + tick_into_new_active_frame(&mut bus); + + assert_eq!( + bus.presented_bg2_line(0), + Some(PresentedBg1Line { + hofs: 0x0356, + vofs: 0x009A, + }) + ); + assert_eq!( + bus.presented_bg3_line(0), + Some(PresentedBg1Line { + hofs: 0x02BC, + vofs: 0x01DE, + }) + ); + assert_eq!( + bus.presented_bg4_line(0), + Some(PresentedBg1Line { + hofs: 0x0324, + vofs: 0x0068, + }) + ); + assert_eq!( + bus.presented_main_screen_line(0), + Some(PresentedMainScreenLine { tm: 0x0F }) + ); + assert_eq!( + bus.presented_color_window_line(0), + Some(PresentedColorWindowLine { + wh0: 0x10, + wh1: 0x80, + wh2: 0x20, + wh3: 0x90, + }) + ); + } + + /// DMA ch0, pattern 1 (two-register: VMDATAL/VMDATAH), increment source. + /// Transfers 4 bytes from WRAM[$7E:0100] to VRAM word 0 via $2118/$2119. + /// Verifies VRAM contents, VMADD advanced, A1T updated, DAS zeroed. + #[test] + fn dma_pattern1_increment_writes_to_vram_and_updates_registers() { + let mut bus = Bus::new(test_cartridge()); + + // Place source data in WRAM + bus.write(0x7E_0100, 0x11); + bus.write(0x7E_0101, 0x22); + bus.write(0x7E_0102, 0x33); + bus.write(0x7E_0103, 0x44); + + // VMAIN = 0x80: increment after high-byte write, step = 1 word + bus.write(0x00_2100, 0x80); + bus.write(0x00_2115, 0x80); + // VMADD = 0 + bus.write(0x00_2116, 0x00); + bus.write(0x00_2117, 0x00); + + // DMAP=0x01: A→B, increment, pattern 1 (+0,+1) + // BBAD=0x18: VMDATA ($2118) + setup_dma_ch0(&mut bus, 0x01, 0x18, 0x7E_0100, 4); + + // Trigger MDMAEN – channel 0 + bus.write(0x00_420B, 0x01); + + // VRAM word 0 (bytes 0-1) and word 1 (bytes 2-3) + assert_eq!(bus.ppu1.peek_vram(0), 0x11, "VRAM[0] low"); + assert_eq!(bus.ppu1.peek_vram(1), 0x22, "VRAM[0] high"); + assert_eq!(bus.ppu1.peek_vram(2), 0x33, "VRAM[1] low"); + assert_eq!(bus.ppu1.peek_vram(3), 0x44, "VRAM[1] high"); + + // VMADD incremented once per word → 2 words transferred + assert_eq!(bus.ppu1.vmadd(), 2, "VMADD after DMA"); + + // A1T updated to 0x0104 (started 0x0100, incremented 4 times) + assert_eq!(bus.read(0x00_4302), 0x04, "A1TL post-DMA"); + assert_eq!(bus.read(0x00_4303), 0x01, "A1TH post-DMA"); + // A1B unchanged + assert_eq!(bus.read(0x00_4304), 0x7E, "A1B unchanged"); + // DAS zeroed + assert_eq!(bus.read(0x00_4305), 0x00, "DASL zeroed"); + assert_eq!(bus.read(0x00_4306), 0x00, "DASH zeroed"); + } + + #[test] + fn active_display_vram_port_writes_are_ignored_until_force_blank() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2115, 0x80); + bus.write(0x00_2116, 0x00); + bus.write(0x00_2117, 0x00); + + bus.write(0x00_2118, 0x34); + bus.write(0x00_2119, 0x12); + + assert_eq!(bus.ppu1.peek_vram(0), 0x00); + assert_eq!(bus.ppu1.peek_vram(1), 0x00); + assert_eq!(bus.ppu1.vmadd(), 0x0001); + + bus.write(0x00_2100, 0x80); + bus.write(0x00_2116, 0x00); + bus.write(0x00_2117, 0x00); + bus.write(0x00_2118, 0x78); + bus.write(0x00_2119, 0x56); + + assert_eq!(bus.ppu1.peek_vram(0), 0x78); + assert_eq!(bus.ppu1.peek_vram(1), 0x56); + assert_eq!(bus.ppu1.vmadd(), 0x0001); + } + + /// DMA ch0, pattern 0, fixed source → WRAM port ($2180). + /// One byte repeated into 4 consecutive WRAM locations; WMADD advances. + #[test] + fn dma_fixed_source_pattern0_to_wram_port_repeats_byte() { + let mut bus = Bus::new(test_cartridge()); + + // Source byte in WRAM + bus.write(0x7E_0200, 0x42); + + // WMADD = 0 + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + // DMAP=0x08: A→B, fixed, pattern 0 + // BBAD=0x80: WMDATA ($2180) + setup_dma_ch0(&mut bus, 0x08, 0x80, 0x7E_0200, 4); + + bus.write(0x00_420B, 0x01); + + // Each of the 4 WRAM bytes should be the repeated source value + assert_eq!(bus.memory.peek_wram(0), 0x42, "WRAM[0]"); + assert_eq!(bus.memory.peek_wram(1), 0x42, "WRAM[1]"); + assert_eq!(bus.memory.peek_wram(2), 0x42, "WRAM[2]"); + assert_eq!(bus.memory.peek_wram(3), 0x42, "WRAM[3]"); + + // WMADD advanced 4 times + assert_eq!(bus.memory.wmadd(), 4, "WMADD after fixed DMA"); + + // A1T unchanged (fixed transfer) + assert_eq!(bus.read(0x00_4302), 0x00, "A1TL fixed unchanged"); + assert_eq!(bus.read(0x00_4303), 0x02, "A1TH fixed unchanged"); + // DAS zeroed + assert_eq!(bus.read(0x00_4305), 0x00, "DASL zeroed"); + assert_eq!(bus.read(0x00_4306), 0x00, "DASH zeroed"); + } + + /// DMA ch0, pattern 0, increment source → CGDATA ($2122). + /// Writing 2 bytes commits one CGRAM color entry. + #[test] + fn dma_pattern0_increment_writes_to_cgram() { + let mut bus = Bus::new(test_cartridge()); + + // Source: two palette bytes + bus.write(0x7E_0300, 0xAB); + bus.write(0x7E_0301, 0x5C); + + // CGADD = color 0 + bus.write(0x00_2121, 0x00); + + // DMAP=0x00: A→B, increment, pattern 0 (single register) + // BBAD=0x22: CGDATA ($2122) + setup_dma_ch0(&mut bus, 0x00, 0x22, 0x7E_0300, 2); + + bus.write(0x00_420B, 0x01); + + // First write latches low byte; second write commits the pair + assert_eq!(bus.ppu2.peek_cgram(0), 0xAB, "CGRAM color0 low"); + assert_eq!(bus.ppu2.peek_cgram(1), 0x5C, "CGRAM color0 high"); + + // A1T updated to 0x0302 + assert_eq!(bus.read(0x00_4302), 0x02, "A1TL post-CGRAM DMA"); + assert_eq!(bus.read(0x00_4303), 0x03, "A1TH post-CGRAM DMA"); + // DAS zeroed + assert_eq!(bus.read(0x00_4305), 0x00); + assert_eq!(bus.read(0x00_4306), 0x00); + } + + /// MDMAEN=0 must not touch any DMA channel. + #[test] + fn mdmaen_zero_does_not_execute_any_channel() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_0000, 0xFF); + + // Configure ch0 to write to WRAM port but do NOT trigger + bus.write(0x00_2181, 0x10); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + setup_dma_ch0(&mut bus, 0x08, 0x80, 0x7E_0000, 8); + + bus.write(0x00_420B, 0x00); // trigger with no channels set + + // WRAM at $10 must be untouched + assert_eq!(bus.memory.peek_wram(0x10), 0x00, "WRAM untouched"); + // WMADD stays at 0x10 + assert_eq!(bus.memory.wmadd(), 0x10, "WMADD untouched"); + } + + #[test] + fn dma_pattern4_wraps_bbus_address_within_21xx_page() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_0500, 0xAA); + bus.write(0x7E_0501, 0xBB); + bus.write(0x7E_0502, 0xCC); + bus.write(0x7E_0503, 0xDD); + + setup_dma_ch0(&mut bus, 0x04, 0xFF, 0x7E_0500, 4); + bus.write(0x00_420B, 0x01); + + assert_eq!(bus.ppu2.inidisp(), 0xBB, "wrapped write reaches $2100"); + assert_eq!( + bus.ppu1.peek(0x2101), + Some(0xCC), + "wrapped write reaches $2101" + ); + assert_eq!( + bus.ppu1.peek(0x2102), + Some(0xDD), + "wrapped write reaches $2102" + ); + } + + #[test] + fn dma_b_to_a_ignores_abus_mmio_destinations() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2121, 0x00); + bus.write(0x00_2122, 0x02); + bus.write(0x00_2122, 0x00); + bus.write(0x00_2121, 0x00); + + bus.write(0x7E_0400, 0x99); + bus.write(0x00_2181, 0x20); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_dma_ch0(&mut bus, 0x80, 0x3B, 0x00_420B, 1); + setup_dma_channel(&mut bus, 1, 0x00, 0x80, 0x7E_0400, 1); + + bus.write(0x00_420B, 0x01); + + assert_eq!(bus.read(0x00_420B), 0x00, "MDMAEN self-clears after DMA"); + assert_eq!( + bus.memory.peek_wram(0x20), + 0x00, + "channel 1 was not spuriously triggered" + ); + } + + #[test] + fn dma_b_to_a_writes_to_cartridge_sram() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_1234, 0x6D); + bus.write(0x00_2181, 0x34); + bus.write(0x00_2182, 0x12); + bus.write(0x00_2183, 0x7E); + + setup_dma_ch0(&mut bus, 0x80, 0x80, 0x70_0321, 1); + bus.write(0x00_420B, 0x01); + + assert_eq!(bus.read(0x70_0321), 0x6D); + assert_eq!(bus.read(0x72_0321), 0x6D); + } + + #[test] + fn hdma_nonrepeat_entry_transfers_only_on_first_line() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_1000, 0x03); + bus.write(0x7E_1001, 0x5A); + bus.write(0x7E_1002, 0x00); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_1000); + bus.write(0x00_420C, 0x01); + + tick_into_new_active_frame(&mut bus); + assert_eq!(bus.memory.peek_wram(0), 0x00); + assert_eq!(bus.memory.wmadd(), 0); + + tick_scanline(&mut bus); + assert_eq!(bus.memory.peek_wram(0), 0x5A); + assert_eq!(bus.memory.wmadd(), 1); + + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(1), + 0x00, + "non-repeat entry skips later lines" + ); + assert_eq!( + bus.memory.wmadd(), + 1, + "WMADD should not advance after first transfer" + ); + + tick_scanline(&mut bus); + assert_eq!( + bus.hdma_active_mask & 0x01, + 0, + "channel disables at table terminator" + ); + } + + #[test] + fn hdma_repeat_entry_transfers_on_every_line() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_1100, 0x83); + bus.write(0x7E_1101, 0xA5); + bus.write(0x7E_1102, 0xA5); + bus.write(0x7E_1103, 0xA5); + bus.write(0x7E_1104, 0x00); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_1100); + bus.write(0x00_420C, 0x01); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + tick_scanline(&mut bus); + tick_scanline(&mut bus); + + assert_eq!(bus.memory.peek_wram(0), 0xA5); + assert_eq!(bus.memory.peek_wram(1), 0xA5); + assert_eq!(bus.memory.peek_wram(2), 0xA5); + assert_eq!(bus.memory.wmadd(), 3); + + assert_eq!(bus.hdma_active_mask & 0x01, 0); + } + + #[test] + fn hdma_midframe_enable_uses_live_a2a_and_nltr_state() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + bus.write(0x7E_0000, 0xEE); + bus.write(0x7E_2000, 0x5A); + bus.write(0x7E_2001, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2000); + bus.write(0x00_420C, 0x00); + + tick_into_new_active_frame(&mut bus); + + bus.write(0x00_4308, 0x00); + bus.write(0x00_4309, 0x20); + bus.write(0x00_430A, 0x82); + assert_eq!(bus.read(0x00_4308), 0x00); + assert_eq!(bus.read(0x00_4309), 0x20); + assert_eq!(bus.read(0x00_430A), 0x82); + + bus.write(0x00_420C, 0x01); + assert_eq!(bus.hdma_active_mask & 0x01, 0x01); + + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(0), + 0x5A, + "first enabled line uses the software-written A2A source at the next HBlank" + ); + assert_eq!(bus.read(0x00_430A), 0x81, "live NLTR decrements in place"); + } + + #[test] + fn hdma_midframe_enable_uses_live_indirect_pointer_state() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + bus.write(0x7E_0000, 0xEE); + bus.write(0x7E_2400, 0x00); + bus.write(0x7E_2500, 0x77); + + setup_hdma_channel(&mut bus, 0, 0x40, 0x80, 0x7E_2400); + bus.write(0x00_420C, 0x00); + + tick_into_new_active_frame(&mut bus); + + bus.write(0x00_4305, 0x00); + bus.write(0x00_4306, 0x25); + bus.write(0x00_4307, 0x7E); + bus.write(0x00_4308, 0x00); + bus.write(0x00_4309, 0x24); + bus.write(0x00_430A, 0x82); + assert_eq!(bus.read(0x00_4305), 0x00); + assert_eq!(bus.read(0x00_4306), 0x25); + assert_eq!(bus.read(0x00_4307), 0x7E); + + bus.write(0x00_420C, 0x01); + + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(0), + 0x77, + "first enabled line uses the software-written indirect DAS/DASB source" + ); + assert_eq!(bus.read(0x00_4305), 0x01); + assert_eq!(bus.read(0x00_4306), 0x25); + } + + #[test] + fn hdma_midframe_enable_during_hblank_transfers_in_the_current_line_window() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + bus.write(0x7E_2700, 0x5A); + bus.write(0x7E_2701, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2700); + bus.write(0x00_420C, 0x00); + + tick_into_new_active_frame(&mut bus); + bus.write(0x00_4308, 0x00); + bus.write(0x00_4309, 0x27); + bus.write(0x00_430A, 0x01); + + tick_subticks(&mut bus, 3); + assert!(bus.in_hblank()); + + bus.write(0x00_420C, 0x01); + + assert_eq!(bus.memory.peek_wram(0), 0x5A); + assert_eq!(bus.memory.wmadd(), 1); + assert_eq!(bus.hdma_active_mask & 0x01, 0); + } + + #[test] + fn hdma_midframe_enable_with_manual_zero_nltr_executes_one_transfer() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + bus.write(0x7E_2600, 0x5A); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2600); + bus.write(0x00_420C, 0x00); + + tick_into_new_active_frame(&mut bus); + bus.write(0x00_4308, 0x00); + bus.write(0x00_4309, 0x26); + bus.write(0x00_430A, 0x00); + + bus.write(0x00_420C, 0x01); + tick_scanline(&mut bus); + + assert_eq!(bus.memory.peek_wram(0), 0x5A); + assert_eq!(bus.memory.wmadd(), 1); + assert_eq!(bus.hdma_active_mask & 0x01, 0); + } + + #[test] + fn manual_nltr_write_rearms_an_ended_hdma_channel_within_the_same_frame() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + bus.write(0x7E_2600, 0x5A); + bus.write(0x7E_2601, 0x00); + bus.write(0x7E_2602, 0x6B); + bus.write(0x7E_2603, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2600); + bus.write(0x00_420C, 0x00); + + tick_into_new_active_frame(&mut bus); + + bus.write(0x00_4308, 0x00); + bus.write(0x00_4309, 0x26); + bus.write(0x00_430A, 0x00); + bus.write(0x00_420C, 0x01); + tick_scanline(&mut bus); + + assert_eq!(bus.memory.peek_wram(0), 0x5A); + assert_eq!(bus.hdma_active_mask & 0x01, 0); + + bus.write(0x00_4308, 0x02); + bus.write(0x00_4309, 0x26); + bus.write(0x00_430A, 0x00); + bus.write(0x00_420C, 0x01); + tick_scanline(&mut bus); + + assert_eq!(bus.memory.peek_wram(1), 0x6B); + assert_eq!(bus.hdma_active_mask & 0x01, 0); + } + + #[test] + fn hdma_midframe_420c_write_does_not_reload_current_progress() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_2200, 0x82); + bus.write(0x7E_2201, 0x11); + bus.write(0x7E_2202, 0x22); + bus.write(0x7E_2203, 0x00); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2200); + bus.write(0x00_420C, 0x01); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + assert_eq!(bus.memory.peek_wram(0), 0x11); + assert_eq!( + bus.read(0x00_4308), + 0x02, + "A2A advanced after the first line" + ); + + bus.write(0x00_420C, 0x00); + bus.write(0x00_420C, 0x01); + assert_eq!( + bus.read(0x00_4308), + 0x02, + "mid-frame HDMAEN writes keep the current live A2A" + ); + + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(1), + 0x22, + "channel resumes from the current HDMA position instead of reloading" + ); + assert_eq!(bus.memory.wmadd(), 2); + } + + #[test] + fn hdma_ended_channel_stays_ended_after_midframe_reenable() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_2300, 0x01); + bus.write(0x7E_2301, 0x33); + bus.write(0x7E_2302, 0x00); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2300); + bus.write(0x00_420C, 0x01); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + assert_eq!(bus.memory.peek_wram(0), 0x33); + assert_eq!( + bus.hdma_active_mask & 0x01, + 0, + "terminator ends the channel" + ); + + bus.write(0x00_420C, 0x00); + bus.write(0x00_420C, 0x01); + assert_eq!( + bus.hdma_active_mask & 0x01, + 0, + "re-enabling a channel after its terminator does not revive it" + ); + + tick_scanline(&mut bus); + assert_eq!( + bus.memory.wmadd(), + 1, + "no extra transfers occur after re-enable" + ); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(1), + 0x33, + "a fresh frame reload clears the ended mask and restarts the channel" + ); + } + + #[test] + fn hdmaen_writes_during_vblank_wait_until_the_next_active_frame() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_2600, 0x01); + bus.write(0x7E_2601, 0x44); + bus.write(0x7E_2602, 0x00); + + bus.write(0x00_2181, 0x00); + bus.write(0x00_2182, 0x00); + bus.write(0x00_2183, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x80, 0x7E_2600); + tick_subticks(&mut bus, VBLANK_STUB_ACTIVE_START); + assert!(bus.in_vblank()); + + bus.write(0x00_420C, 0x01); + assert_eq!( + bus.hdma_active_mask & 0x01, + 0, + "writing HDMAEN during vblank should not change the current frame mask" + ); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + assert_eq!( + bus.memory.peek_wram(0), + 0x44, + "the queued HDMAEN value transfers at the next frame's first HBlank" + ); + } + + #[test] + fn hdma_two_channels_run_low_to_high_for_cgadd_then_cgdata() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_1200, 0x01); + bus.write(0x7E_1201, 0x01); + bus.write(0x7E_1202, 0x00); + bus.write(0x7E_1210, 0x01); + bus.write(0x7E_1211, 0x34); + bus.write(0x7E_1212, 0x12); + bus.write(0x7E_1213, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x00, 0x21, 0x7E_1200); + setup_hdma_channel(&mut bus, 1, 0x02, 0x22, 0x7E_1210); + bus.write(0x00_420C, 0x03); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + + assert_eq!(bus.ppu2.peek_cgram(2), 0x34); + assert_eq!(bus.ppu2.peek_cgram(3), 0x12); + } + + #[test] + fn hdma_pattern3_can_update_cgadd_and_cgdata_in_one_channel() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x7E_1300, 0x01); + bus.write(0x7E_1301, 0x00); + bus.write(0x7E_1302, 0x01); + bus.write(0x7E_1303, 0x78); + bus.write(0x7E_1304, 0x56); + bus.write(0x7E_1305, 0x00); + + setup_hdma_channel(&mut bus, 0, 0x03, 0x21, 0x7E_1300); + bus.write(0x00_420C, 0x01); + + tick_into_new_active_frame(&mut bus); + tick_scanline(&mut bus); + + assert_eq!(bus.ppu2.peek_cgram(2), 0x78); + assert_eq!(bus.ppu2.peek_cgram(3), 0x56); + } + + #[test] + fn dma_pattern0_increment_writes_to_oam() { + let mut bus = Bus::new(test_cartridge()); + + for (offset, value) in [0x40, 0x50, 0x00, 0x30, 0x60, 0x50, 0x04, 0x30] + .into_iter() + .enumerate() + { + bus.write(0x7E_0600 + offset as u32, value); + } + + bus.write(0x00_2102, 0x00); + bus.write(0x00_2103, 0x00); + setup_dma_ch0(&mut bus, 0x00, 0x04, 0x7E_0600, 8); + + bus.write(0x00_420B, 0x01); + + assert_eq!(bus.ppu1.peek_oam(0), 0x40); + assert_eq!(bus.ppu1.peek_oam(1), 0x50); + assert_eq!(bus.ppu1.peek_oam(2), 0x00); + assert_eq!(bus.ppu1.peek_oam(3), 0x30); + assert_eq!(bus.ppu1.peek_oam(4), 0x60); + assert_eq!(bus.ppu1.peek_oam(5), 0x50); + assert_eq!(bus.ppu1.peek_oam(6), 0x04); + assert_eq!(bus.ppu1.peek_oam(7), 0x30); + } + + #[test] + fn dma_pattern0_increment_can_target_oam_high_table() { + let mut bus = Bus::new(test_cartridge()); + + for offset in 0..4 { + bus.write(0x7E_0700 + offset, 0xAA); + } + + bus.write(0x00_2102, 0x00); + bus.write(0x00_2103, 0x01); + setup_dma_ch0(&mut bus, 0x00, 0x04, 0x7E_0700, 4); + + bus.write(0x00_420B, 0x01); + + assert_eq!(bus.ppu1.peek_oam(512), 0xAA); + assert_eq!(bus.ppu1.peek_oam(513), 0xAA); + assert_eq!(bus.ppu1.peek_oam(514), 0xAA); + assert_eq!(bus.ppu1.peek_oam(515), 0xAA); + } + + // ----------------------------------------------------------------------- + // NMI / RDNMI tests + // ----------------------------------------------------------------------- + + #[test] + fn rdnmi_flag_is_set_on_vblank_entry_and_cleared_by_read() { + let mut bus = Bus::new(test_cartridge()); + + // No vblank yet: RDNMI reads 0x40 and flag stays clear. + assert_eq!(bus.read(0x004210), 0x40); + assert!(!bus.nmi_flag); + + // Tick until vblank starts + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!(bus.nmi_flag, "nmi_flag should be set on vblank entry"); + + // First read returns 0xC0 and clears the flag + assert_eq!(bus.read(0x004210), 0xC0); + assert!(!bus.nmi_flag, "nmi_flag should be cleared after read"); + + // Second read returns 0x40 (flag already cleared) + assert_eq!(bus.read(0x004210), 0x40); + } + + #[test] + fn rdnmi_flag_clears_automatically_at_vblank_end() { + let mut bus = Bus::new(test_cartridge()); + + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!(bus.nmi_flag, "nmi_flag should be set on vblank entry"); + + for _ in 0..(VBLANK_STUB_PERIOD - VBLANK_STUB_ACTIVE_START) { + bus.tick_video_stub(); + } + assert!( + !bus.nmi_flag, + "nmi_flag should clear automatically when vblank ends" + ); + } + + #[test] + fn nmi_pending_is_raised_when_vblank_starts_while_nmi_enabled() { + let mut bus = Bus::new(test_cartridge()); + + // Enable NMI via NMITIMEN ($4200 bit 7) + bus.write(0x004200, 0x80); + assert!(!bus.nmi_pending); + + // Tick into vblank + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!( + bus.nmi_pending, + "nmi_pending should be set when NMI is enabled at vblank" + ); + + // poll_nmi consumes the pending flag + assert!(bus.poll_nmi()); + assert!(!bus.nmi_pending); + assert!(!bus.poll_nmi(), "second poll should return false"); + } + + #[test] + fn nmi_not_pending_when_nmi_disabled_at_vblank() { + let mut bus = Bus::new(test_cartridge()); + + // NMI disabled (NMITIMEN bit 7 = 0, default) + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!(bus.nmi_flag); + assert!( + !bus.nmi_pending, + "nmi_pending should NOT be set when NMI is disabled" + ); + } + + #[test] + fn enabling_nmi_while_nmi_flag_is_set_raises_pending_nmi() { + let mut bus = Bus::new(test_cartridge()); + + // Tick into vblank without NMI enabled + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!(bus.nmi_flag); + assert!(!bus.nmi_pending); + + // Now enable NMI – should immediately queue pending NMI + bus.write(0x004200, 0x80); + assert!( + bus.nmi_pending, + "enabling NMI mid-vblank should queue pending NMI" + ); + } + + #[test] + fn rdnmi_peek_reflects_nmi_flag_without_clearing() { + let mut bus = Bus::new(test_cartridge()); + + for _ in 0..VBLANK_STUB_ACTIVE_START { + bus.tick_video_stub(); + } + assert!(bus.nmi_flag); + + // Peek is non-destructive + assert_eq!(bus.peek(0x004210), 0x80); + assert!(bus.nmi_flag, "peek must not clear the NMI flag"); + assert_eq!(bus.peek(0x004210), 0x80); + } + + #[test] + fn timeup_flag_is_set_when_vcounter_irq_fires_and_cleared_by_read() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 40); + bus.write(0x00420A, 0); + bus.write(0x004200, 0x20); + + for _ in 0..(40 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + + assert!(bus.irq_flag); + assert_eq!(bus.peek(0x004211), 0x80); + assert_eq!(bus.read(0x004211), 0xC0); + assert!(!bus.irq_flag); + assert_eq!(bus.read(0x004211), 0x40); + } + + #[test] + fn poll_irq_stays_asserted_until_timeup_is_acknowledged() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 40); + bus.write(0x00420A, 0); + bus.write(0x004200, 0x20); + + for _ in 0..(40 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + + assert!(bus.poll_irq()); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + assert!(!bus.poll_irq()); + } + + #[test] + fn disabling_vcounter_irq_cancels_pending_delivery() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 40); + bus.write(0x00420A, 0); + bus.write(0x004200, 0x20); + + for _ in 0..(40 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + + bus.write(0x004200, 0x00); + + assert!(bus.irq_flag); + assert!(!bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn hcounter_irq_raises_timeup_without_vcounter_programming() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004207, 0x35); + bus.write(0x004208, 0x01); + bus.write(0x004200, 0x10); + + for _ in 0..3 { + bus.tick_video_stub(); + } + + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn combined_hv_irq_waits_for_both_targets() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 103); + bus.write(0x00420A, 0); + bus.write(0x004207, 137); + bus.write(0x004208, 0); + bus.write(0x004200, 0x30); + + for _ in 0..(103 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn combined_hv_irq_reasserts_on_later_frames_after_acknowledgement() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 1); + bus.write(0x00420A, 0); + bus.write(0x004207, 137); + bus.write(0x004208, 0); + bus.write(0x004200, 0x30); + + for _ in 0..(VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + assert_eq!(bus.read(0x004211), 0xC0); + + for _ in 0..VBLANK_STUB_PERIOD { + bus.tick_video_stub(); + } + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn enabling_hcounter_irq_at_matching_subtick_raises_timeup_immediately() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004207, 137); + bus.write(0x004208, 0); + bus.tick_video_stub(); + + bus.write(0x004200, 0x10); + + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn enabling_combined_hv_irq_at_matching_position_raises_timeup_immediately() { + let mut bus = Bus::new(test_cartridge()); + + bus.write(0x004209, 2); + bus.write(0x00420A, 0); + bus.write(0x004207, 137); + bus.write(0x004208, 0); + + for _ in 0..(2 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + + bus.write(0x004200, 0x30); + + assert!(bus.irq_flag); + assert!(bus.poll_irq()); + assert_eq!(bus.read(0x004211), 0xC0); + } + + #[test] + fn slhv_latches_current_h_and_v_counters() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x40); + + for _ in 0..(5 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 5); + assert_eq!(bus.read(0x00213D), 0); + assert_eq!(bus.read(0x00213C), 127); + assert_eq!(bus.read(0x00213C), 0); + } + + #[test] + fn slhv_latches_with_reset_default_wrio_state() { + let mut bus = Bus::new(test_cartridge()); + + for _ in 0..(4 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 4); + assert_eq!(bus.read(0x00213D), 0); + } + + #[test] + fn stat78_resets_ophct_and_opvct_byte_order() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x40); + + for _ in 0..(6 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 3) { + bus.tick_video_stub(); + } + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 6); + assert_eq!(bus.read(0x00213F), 0x01); + assert_eq!(bus.read(0x00213D), 6); + assert_eq!(bus.read(0x00213C), 41); + assert_eq!(bus.read(0x00213C), 1); + assert_eq!(bus.read(0x00213F), 0x01); + assert_eq!(bus.read(0x00213C), 41); + } + + #[test] + fn slhv_relatch_resets_counter_byte_order_and_preserves_high_bits() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x40); + + for _ in 0..(257 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 1); + assert_eq!(bus.read(0x00213C), 127); + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 1); + assert_eq!(bus.read(0x00213D), 1); + assert_eq!(bus.read(0x00213C), 127); + assert_eq!(bus.read(0x00213C), 0); + } + + #[test] + fn slhv_does_not_relatch_when_wrio_port2_is_low() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x40); + + for _ in 0..(5 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + assert_eq!(bus.read(0x002137), 0x00); + + bus.write(0x004201, 0x00); + for _ in 0..(2 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + assert_eq!(bus.read(0x00213F), 0x01); + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 5); + } + + #[test] + fn wrio_port2_falling_edge_latches_h_and_v_counters() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x40); + + for _ in 0..(8 * VBLANK_STUB_SUBTICKS_PER_SCANLINE + 1) { + bus.tick_video_stub(); + } + bus.write(0x004201, 0x00); + + assert_eq!(bus.read(0x00213D), 8); + assert_eq!(bus.read(0x00213D), 0); + assert_eq!(bus.read(0x00213C), 127); + assert_eq!(bus.read(0x00213C), 0); + } + + #[test] + fn reset_ephemeral_state_restores_wrio_default_high() { + let mut bus = Bus::new(test_cartridge()); + bus.write(0x004201, 0x00); + bus.reset_ephemeral_state(); + + for _ in 0..(3 * VBLANK_STUB_SUBTICKS_PER_SCANLINE) { + bus.tick_video_stub(); + } + + assert_eq!(bus.read(0x002137), 0x00); + assert_eq!(bus.read(0x00213D), 3); + } +} diff --git a/snes/core/src/cartridge.rs b/snes/core/src/cartridge.rs new file mode 100644 index 00000000..bed2178d --- /dev/null +++ b/snes/core/src/cartridge.rs @@ -0,0 +1,3289 @@ +use crate::enhancement::{EnhancementChip, EnhancementState, Msu1State}; +use crate::mapper::{HiRomMapper, LoRomMapper, Mapper, MapperKind, Sa1Mapper, superfx_ram_index}; + +const COPIER_HEADER_LEN: usize = 512; +const LOROM_HEADER_OFFSET: usize = 0x7FC0; +const LOROM_RESET_VECTOR_OFFSET: usize = 0x7FFC; +const HIROM_HEADER_OFFSET: usize = 0xFFC0; +const HIROM_RESET_VECTOR_OFFSET: usize = 0xFFFC; +const HEADER_TITLE_LEN: usize = 21; +const LOROM_MAP_MODE_MASK: u8 = 0x2F; +const LOROM_MAP_MODE_VALUE: u8 = 0x20; +const SA1_MAP_MODE_VALUE: u8 = 0x23; +const HIROM_MAP_MODE_MASK: u8 = 0x2F; +const HIROM_MAP_MODE_VALUE: u8 = 0x21; +const MAX_RAM_SIZE_CODE: u8 = 0x08; + +#[derive(Debug, thiserror::Error, PartialEq, Eq)] +pub enum CartridgeError { + #[error( + "ROM size must be an even multiple of 32 KiB, optionally plus a 512-byte copier header" + )] + InvalidRomSize, + #[error("ROM is too small to contain a supported SNES header")] + MissingHeader, + #[error("unsupported SNES map mode 0x{0:02X}")] + UnsupportedMapMode(u8), + #[error("unsupported SNES cartridge RAM size code 0x{0:02X}")] + UnsupportedRamSizeCode(u8), + #[error("invalid SNES save RAM size: expected {expected} bytes, got {actual}")] + InvalidSaveRamSize { expected: usize, actual: usize }, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub struct CartridgeHeader { + title: String, + map_mode: u8, + chipset: u8, + expansion_chip_subtype: Option, + enhancement_chip: EnhancementChip, + rom_size_code: u8, + ram_size_code: u8, + reset_vector: u16, + has_copier_header: bool, + mapper_kind: MapperKind, +} + +impl CartridgeHeader { + pub fn title(&self) -> &str { + &self.title + } + + pub fn map_mode(&self) -> u8 { + self.map_mode + } + + pub fn chipset(&self) -> u8 { + self.chipset + } + + pub fn expansion_chip_subtype(&self) -> Option { + self.expansion_chip_subtype + } + + pub fn enhancement_chip(&self) -> EnhancementChip { + self.enhancement_chip + } + + pub fn rom_size_code(&self) -> u8 { + self.rom_size_code + } + + pub fn ram_size_code(&self) -> u8 { + self.ram_size_code + } + + pub fn reset_vector(&self) -> u16 { + self.reset_vector + } + + pub fn has_copier_header(&self) -> bool { + self.has_copier_header + } + + pub fn mapper_kind(&self) -> MapperKind { + self.mapper_kind + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub struct Cartridge { + rom: Box<[u8]>, + save_ram: Box<[u8]>, + header: CartridgeHeader, + mapper: Mapper, + enhancement: EnhancementState, + msu1: Msu1State, +} + +impl Cartridge { + pub fn from_bytes(bytes: &[u8]) -> Result { + let (rom, has_copier_header) = strip_copier_header(bytes)?; + if rom.len() <= LOROM_RESET_VECTOR_OFFSET + 1 { + return Err(CartridgeError::MissingHeader); + } + + let Some((header, mapper)) = Self::parse_header(rom, has_copier_header) else { + return Err(CartridgeError::UnsupportedMapMode( + rom[LOROM_HEADER_OFFSET + 0x15], + )); + }; + + let mut save_ram = vec![0; ram_size_bytes(header.ram_size_code)?].into_boxed_slice(); + + // SuperFX needs at least some RAM for the GSU's working memory. + // The header's RAM size byte covers battery-backed SRAM, not GSU RAM. + // If the header claims zero RAM, default to 64KB. + if header.enhancement_chip().is_superfx() && save_ram.is_empty() { + save_ram = vec![0; 0x10000].into_boxed_slice(); + } + + let enhancement = EnhancementState::from_chip(header.enhancement_chip()); + + Ok(Self { + rom: rom.to_vec().into_boxed_slice(), + save_ram, + header, + mapper, + enhancement, + msu1: Msu1State::new(), + }) + } + + fn parse_header(rom: &[u8], has_copier_header: bool) -> Option<(CartridgeHeader, Mapper)> { + Self::parse_header_at( + rom, + has_copier_header, + LOROM_HEADER_OFFSET, + LOROM_RESET_VECTOR_OFFSET, + MapperKind::Sa1, + Mapper::Sa1(Sa1Mapper), + ) + .or_else(|| { + Self::parse_header_at( + rom, + has_copier_header, + LOROM_HEADER_OFFSET, + LOROM_RESET_VECTOR_OFFSET, + MapperKind::LoRom, + Mapper::LoRom(LoRomMapper), + ) + }) + .or_else(|| { + Self::parse_header_at( + rom, + has_copier_header, + HIROM_HEADER_OFFSET, + HIROM_RESET_VECTOR_OFFSET, + MapperKind::HiRom, + Mapper::HiRom(HiRomMapper), + ) + }) + } + + fn parse_header_at( + rom: &[u8], + has_copier_header: bool, + header_offset: usize, + reset_vector_offset: usize, + mapper_kind: MapperKind, + mapper: Mapper, + ) -> Option<(CartridgeHeader, Mapper)> { + if rom.len() <= reset_vector_offset + 1 { + return None; + } + let map_mode = rom[header_offset + 0x15]; + let chipset = rom[header_offset + 0x16]; + if !Self::supported_map_mode(map_mode, chipset, mapper_kind) { + return None; + } + + let title_bytes = &rom[header_offset..header_offset + HEADER_TITLE_LEN]; + let title = String::from_utf8_lossy(title_bytes) + .trim_end_matches(char::from(0)) + .trim_end() + .to_owned(); + let reset_vector = + u16::from_le_bytes([rom[reset_vector_offset], rom[reset_vector_offset + 1]]); + let expansion_chip_subtype = expansion_chip_subtype(rom, header_offset, chipset); + let enhancement_chip = enhancement_chip_for_header( + map_mode, + chipset, + expansion_chip_subtype, + rom[header_offset + 0x17], + rom[header_offset + 0x1A], + ); + + Some(( + CartridgeHeader { + title, + map_mode, + chipset, + expansion_chip_subtype, + enhancement_chip, + rom_size_code: rom[header_offset + 0x17], + ram_size_code: rom[header_offset + 0x18], + reset_vector, + has_copier_header, + mapper_kind, + }, + mapper, + )) + } + + fn supported_map_mode(map_mode: u8, chipset: u8, mapper_kind: MapperKind) -> bool { + match mapper_kind { + MapperKind::LoRom => map_mode & LOROM_MAP_MODE_MASK == LOROM_MAP_MODE_VALUE, + MapperKind::HiRom => map_mode & HIROM_MAP_MODE_MASK == HIROM_MAP_MODE_VALUE, + MapperKind::Sa1 => { + map_mode & LOROM_MAP_MODE_MASK == SA1_MAP_MODE_VALUE && is_sa1_chipset(chipset) + } + } + } + + pub fn header(&self) -> &CartridgeHeader { + &self.header + } + + pub fn read(&self, address: u32) -> Option { + self.peek(address) + } + + pub(crate) fn read_mut(&mut self, address: u32) -> Option { + if let Some(value) = self.msu1.read(address) { + return Some(value); + } + if let Some(value) = self.enhancement.read( + self.header.mapper_kind(), + address, + &self.rom, + &self.save_ram, + ) { + return Some(value); + } + self.read_mapped_mut(address) + } + + pub(crate) fn read_side_effect_free(&self, address: u32) -> Option { + if self.msu1.peek(address).is_some() { + return None; + } + if self + .enhancement + .peek( + self.header.mapper_kind(), + address, + &self.rom, + &self.save_ram, + ) + .is_some() + { + return None; + } + self.read_mapped(address) + } + + pub(crate) fn tick_sa1_timer( + &mut self, + h_subtick: u16, + v_counter: u16, + h_subticks_per_line: u16, + ) { + if let EnhancementState::Sa1(state) = &mut self.enhancement { + state.tick_timer(h_subtick, v_counter, h_subticks_per_line); + } + } + + fn peek(&self, address: u32) -> Option { + if let Some(value) = self.msu1.peek(address) { + return Some(value); + } + if let Some(value) = self.enhancement.peek( + self.header.mapper_kind(), + address, + &self.rom, + &self.save_ram, + ) { + return Some(value); + } + self.read_mapped(address) + } + + fn read_mapped(&self, address: u32) -> Option { + if let EnhancementState::Sa1(state) = &self.enhancement { + if is_sa1_cpu_bitmap_bank(address) { + return state.read_sa1_cpu_bwram(address, &self.save_ram); + } + if let Some(index) = state.sa1_bwram_index(address, self.save_ram.len()) { + return Some(self.save_ram[index]); + } + return state + .sa1_banked_rom_index(address, self.rom.len()) + .map(|index| self.rom[index]); + } + + if self.header.enhancement_chip().is_superfx() + && let Some(index) = superfx_ram_index(address, self.save_ram.len()) + { + return Some(self.save_ram[index]); + } + + self.mapper.read(&self.rom, &self.save_ram, address) + } + + fn read_mapped_mut(&mut self, address: u32) -> Option { + if let EnhancementState::Sa1(state) = &mut self.enhancement { + if is_sa1_cpu_bitmap_bank(address) { + return state.read_sa1_cpu_bwram(address, &self.save_ram); + } + if let Some(value) = state.read_sa1_bwram(address, &self.save_ram) { + return Some(value); + } + return state + .sa1_banked_rom_index(address, self.rom.len()) + .map(|index| self.rom[index]); + } + + self.read_mapped(address) + } + + pub fn write(&mut self, address: u32, value: u8) -> bool { + if self.msu1.write(address, value) { + return true; + } + if self.enhancement.write( + self.header.mapper_kind(), + address, + value, + &self.rom, + &mut self.save_ram, + ) { + return true; + } + if self.header.enhancement_chip().is_superfx() + && let Some(index) = superfx_ram_index(address, self.save_ram.len()) + { + self.save_ram[index] = value; + return true; + } + if let EnhancementState::Sa1(state) = &self.enhancement + && is_sa1_cpu_bitmap_bank(address) + { + return state.write_sa1_cpu_bwram(address, value, &mut self.save_ram); + } + if let EnhancementState::Sa1(state) = &self.enhancement + && let Some(index) = state.sa1_bwram_index(address, self.save_ram.len()) + { + if state.can_write_sa1_bwram(address) { + self.save_ram[index] = value; + } + return true; + } + + self.mapper.write_ram(&mut self.save_ram, address, value) + } + + pub fn rom_len(&self) -> usize { + self.rom.len() + } + + pub fn save_ram(&self) -> &[u8] { + &self.save_ram + } + + pub fn load_save_ram(&mut self, save_ram: &[u8]) -> Result<(), CartridgeError> { + if save_ram.len() != self.save_ram.len() { + return Err(CartridgeError::InvalidSaveRamSize { + expected: self.save_ram.len(), + actual: save_ram.len(), + }); + } + + self.save_ram.copy_from_slice(save_ram); + Ok(()) + } + + pub fn load_msu1_data(&mut self, data: &[u8]) { + self.msu1.load_data(data); + } + + pub fn set_msu1_audio_tracks(&mut self, tracks: I) + where + I: IntoIterator, + { + self.msu1.set_audio_tracks(tracks); + } +} + +fn cartridge_coprocessor(chipset: u8) -> u8 { + chipset >> 4 +} + +fn cartridge_features(chipset: u8) -> u8 { + chipset & 0x0F +} + +fn is_sa1_chipset(chipset: u8) -> bool { + matches!(chipset, 0x34 | 0x35) +} + +fn has_coprocessor(chipset: u8) -> bool { + cartridge_features(chipset) >= 0x03 +} + +fn expansion_chip_subtype(rom: &[u8], header_offset: usize, chipset: u8) -> Option { + if !has_coprocessor(chipset) || cartridge_coprocessor(chipset) != 0x0F { + return None; + } + header_offset + .checked_sub(1) + .and_then(|offset| rom.get(offset)) + .copied() +} + +fn enhancement_chip_for_header( + map_mode: u8, + chipset: u8, + expansion_chip_subtype: Option, + rom_size_code: u8, + old_maker_code: u8, +) -> EnhancementChip { + if !has_coprocessor(chipset) { + return EnhancementChip::None; + } + + match cartridge_coprocessor(chipset) { + 0x0 => dsp1_enhancement_chip(map_mode, chipset, old_maker_code), + 0x1 => { + if chipset == 0x1A || rom_size_code > 0x0A { + EnhancementChip::SuperFxGsu2 + } else { + EnhancementChip::SuperFxGsu1 + } + } + 0x3 if map_mode & LOROM_MAP_MODE_MASK == SA1_MAP_MODE_VALUE && is_sa1_chipset(chipset) => { + EnhancementChip::Sa1 + } + 0xF if matches!(expansion_chip_subtype, Some(0x03 | 0x10)) => EnhancementChip::Cx4, + _ => EnhancementChip::None, + } +} + +fn dsp1_enhancement_chip(map_mode: u8, chipset: u8, old_maker_code: u8) -> EnhancementChip { + // DSP-1 and DSP-1A share firmware. Keep known DSP-2/DSP-3/DSP-4 headers out of the + // DSP-1 path until those distinct coprocessors are implemented. + if matches!((map_mode, chipset), (0x20, 0x05) | (0x30, 0x03)) + || (map_mode == 0x30 && chipset == 0x05 && old_maker_code == 0xB2) + { + return EnhancementChip::None; + } + // Common DSP-1B boards are HiROM with DSP+RAM+Battery. + if map_mode & HIROM_MAP_MODE_MASK == HIROM_MAP_MODE_VALUE && chipset == 0x05 { + EnhancementChip::Dsp1B + } else { + EnhancementChip::Dsp1 + } +} + +fn strip_copier_header(bytes: &[u8]) -> Result<(&[u8], bool), CartridgeError> { + match bytes.len() % 0x8000 { + 0 => Ok((bytes, false)), + COPIER_HEADER_LEN => Ok((&bytes[COPIER_HEADER_LEN..], true)), + _ => Err(CartridgeError::InvalidRomSize), + } +} + +fn ram_size_bytes(code: u8) -> Result { + if code == 0 { + return Ok(0); + } + if code > MAX_RAM_SIZE_CODE { + return Err(CartridgeError::UnsupportedRamSizeCode(code)); + } + + Ok(1024usize << code) +} + +fn is_sa1_cpu_bitmap_bank(address: u32) -> bool { + let bank = ((address >> 16) & 0xFF) as u8; + matches!(bank, 0x60..=0x6F) +} + +#[cfg(test)] +mod tests { + use super::{Cartridge, CartridgeError}; + use crate::{EnhancementChip, MapperKind}; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + const HIROM_HEADER_OFFSET: usize = 0xFFC0; + const HIROM_RESET_VECTOR_OFFSET: usize = 0xFFFC; + + fn build_lorom() -> Vec { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"CPU TEST HEADER "); + rom[0x7FD5] = 0x30; + rom[0x7FD7] = 0x08; + rom[0x7FD8] = 0x03; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&0x8000_u16.to_le_bytes()); + rom[0x0000] = 0xEA; + rom[0x8000] = 0xA2; + rom + } + + fn build_lorom_with_header( + title: &str, + map_mode: u8, + chipset: u8, + expansion_chip_subtype: Option, + rom_size_code: u8, + ) -> Vec { + let mut rom = build_lorom(); + write_title(&mut rom, HEADER_OFFSET, title); + rom[HEADER_OFFSET + 0x15] = map_mode; + rom[HEADER_OFFSET + 0x16] = chipset; + rom[HEADER_OFFSET + 0x17] = rom_size_code; + if let Some(subtype) = expansion_chip_subtype { + rom[HEADER_OFFSET - 1] = subtype; + } + rom + } + + fn build_sa1_rom(rom_len: usize, ram_size_code: u8) -> Vec { + let mut rom = build_lorom_with_header("SA1 MAPPER", 0x23, 0x34, None, 0x0C); + rom.resize(rom_len, 0); + rom[HEADER_OFFSET + 0x18] = ram_size_code; + rom + } + + fn build_hirom() -> Vec { + let mut rom = vec![0; 0x20000]; + rom[HIROM_HEADER_OFFSET..HIROM_HEADER_OFFSET + 21] + .copy_from_slice(b"HIROM TEST HEADER "); + rom[0xFFD5] = 0x31; + rom[0xFFD7] = 0x09; + rom[0xFFD8] = 0x03; + rom[HIROM_RESET_VECTOR_OFFSET..HIROM_RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&0x8000_u16.to_le_bytes()); + rom[0x8000] = 0xEA; + rom[0x10000] = 0xA2; + rom + } + + fn build_hirom_with_header( + title: &str, + map_mode: u8, + chipset: u8, + expansion_chip_subtype: Option, + rom_size_code: u8, + ) -> Vec { + let mut rom = build_hirom(); + write_title(&mut rom, HIROM_HEADER_OFFSET, title); + rom[HIROM_HEADER_OFFSET + 0x15] = map_mode; + rom[HIROM_HEADER_OFFSET + 0x16] = chipset; + rom[HIROM_HEADER_OFFSET + 0x17] = rom_size_code; + if let Some(subtype) = expansion_chip_subtype { + rom[HIROM_HEADER_OFFSET - 1] = subtype; + } + rom + } + + fn write_title(rom: &mut [u8], header_offset: usize, title: &str) { + let mut title_bytes = [b' '; 21]; + for (target, source) in title_bytes.iter_mut().zip(title.as_bytes()) { + *target = *source; + } + rom[header_offset..header_offset + title_bytes.len()].copy_from_slice(&title_bytes); + } + + #[test] + fn msu1_registers_are_absent_without_sidecars() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + + assert_eq!(cartridge.read(0x002000), None); + assert_eq!(cartridge.read(0x002002), None); + assert_eq!(cartridge.read(0x802002), None); + assert!(!cartridge.write(0x002000, 0x12)); + assert_eq!(cartridge.read_mut(0x802007), None); + } + + #[test] + fn msu1_status_and_identity_are_available_after_data_sidecar_load() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + cartridge.load_msu1_data(&[]); + + assert_eq!(cartridge.read(0x002000), Some(0x0A)); + let signature: Vec = (0x2002_u32..=0x2007) + .map(|offset| cartridge.read(offset).unwrap()) + .collect(); + assert_eq!(signature, b"S-MSU1"); + assert_eq!(cartridge.read(0x802002), Some(b'S')); + assert_eq!(cartridge.read_mut(0x802007), Some(b'1')); + } + + #[test] + fn msu1_data_seek_commits_on_high_byte_write() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + cartridge.load_msu1_data(&[]); + + assert!(cartridge.write(0x002000, 0x12)); + assert!(cartridge.write(0x002001, 0x34)); + assert!(cartridge.write(0x002002, 0x56)); + assert_eq!(cartridge.msu1.data_seek_offset(), 0x0056_3412); + assert_eq!(cartridge.msu1.data_read_offset(), 0); + + assert!(cartridge.write(0x002003, 0x78)); + assert_eq!(cartridge.msu1.data_seek_offset(), 0x7856_3412); + assert_eq!(cartridge.msu1.data_read_offset(), 0x7856_3412); + assert_eq!(cartridge.read_mut(0x002001), Some(0x00)); + assert_eq!(cartridge.msu1.data_read_offset(), 0x7856_3412); + } + + #[test] + fn msu1_data_port_reads_mounted_sidecar_and_advances() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + cartridge.load_msu1_data(&[0x11, 0x22, 0x33]); + + assert_eq!(cartridge.msu1.data_len(), 3); + assert!(cartridge.write(0x002000, 0x01)); + assert!(cartridge.write(0x002001, 0x00)); + assert!(cartridge.write(0x002002, 0x00)); + assert!(cartridge.write(0x002003, 0x00)); + + assert_eq!(cartridge.read_mut(0x002001), Some(0x22)); + assert_eq!(cartridge.read_mut(0x002001), Some(0x33)); + assert_eq!(cartridge.read_mut(0x002001), Some(0x00)); + assert_eq!(cartridge.msu1.data_read_offset(), 3); + assert_eq!(cartridge.read_mut(0x002001), Some(0x00)); + assert_eq!(cartridge.msu1.data_read_offset(), 3); + assert_eq!(cartridge.read(0x002000), Some(0x0A)); + } + + #[test] + fn msu1_audio_registers_report_no_media_until_audio_is_available() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + cartridge.set_msu1_audio_tracks([0x1234, 0x1234]); + + assert!(cartridge.write(0x002004, 0x34)); + assert!(cartridge.write(0x002005, 0x12)); + assert!(cartridge.write(0x002006, 0x7F)); + assert_eq!(cartridge.read(0x002000), Some(0x02)); + assert!(cartridge.write(0x002007, 0x03)); + + assert_eq!(cartridge.msu1.audio_track(), 0x1234); + assert_eq!(cartridge.msu1.audio_track_count(), 1); + assert_eq!(cartridge.msu1.audio_volume(), 0x7F); + assert_eq!(cartridge.read(0x002000), Some(0x32)); + + assert!(cartridge.write(0x002007, 0x00)); + assert_eq!(cartridge.read(0x002000), Some(0x02)); + + assert!(cartridge.write(0x002004, 0x35)); + assert!(cartridge.write(0x002005, 0x12)); + assert!(cartridge.write(0x002007, 0x03)); + assert_eq!(cartridge.read(0x002000), Some(0x0A)); + } + + #[test] + fn parses_lorom_header_and_supports_copier_header_stripping() { + let rom = build_lorom(); + let mut with_copier_header = vec![0; 512]; + with_copier_header.extend_from_slice(&rom); + + let cartridge = Cartridge::from_bytes(&with_copier_header).unwrap(); + + assert_eq!(cartridge.header().title(), "CPU TEST HEADER"); + assert_eq!(cartridge.header().map_mode(), 0x30); + assert_eq!(cartridge.header().chipset(), 0x00); + assert_eq!(cartridge.header().expansion_chip_subtype(), None); + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::None); + assert_eq!(cartridge.header().rom_size_code(), 0x08); + assert_eq!(cartridge.header().ram_size_code(), 0x03); + assert_eq!(cartridge.header().reset_vector(), 0x8000); + assert!(cartridge.header().has_copier_header()); + assert_eq!(cartridge.header().mapper_kind(), MapperKind::LoRom); + assert_eq!(cartridge.save_ram().len(), 8 * 1024); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + assert_eq!(cartridge.read(0x018000), Some(0xA2)); + assert_eq!(cartridge.read(0x808000), Some(0xEA)); + } + + #[test] + fn parses_hirom_header_and_maps_64k_rom_banks() { + let cartridge = Cartridge::from_bytes(&build_hirom()).unwrap(); + + assert_eq!(cartridge.header().title(), "HIROM TEST HEADER"); + assert_eq!(cartridge.header().map_mode(), 0x31); + assert_eq!(cartridge.header().chipset(), 0x00); + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::None); + assert_eq!(cartridge.header().rom_size_code(), 0x09); + assert_eq!(cartridge.header().ram_size_code(), 0x03); + assert_eq!(cartridge.header().reset_vector(), 0x8000); + assert_eq!(cartridge.header().mapper_kind(), MapperKind::HiRom); + assert_eq!(cartridge.save_ram().len(), 8 * 1024); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + assert_eq!(cartridge.read(0xC08000), Some(0xEA)); + assert_eq!(cartridge.read(0xC10000), Some(0xA2)); + } + + #[test] + fn lorom_sram_reads_writes_and_mirrors() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + + assert_eq!(cartridge.read(0x700123), Some(0x00)); + assert!(cartridge.write(0x700123, 0x5A)); + assert_eq!(cartridge.read(0x700123), Some(0x5A)); + assert_eq!(cartridge.read(0x702123), Some(0x5A)); + assert_eq!(cartridge.read(0xF00123), Some(0x5A)); + assert!(!cartridge.write(0x708000, 0xC3)); + } + + #[test] + fn hirom_sram_reads_writes_and_mirrors() { + let mut cartridge = Cartridge::from_bytes(&build_hirom()).unwrap(); + + assert_eq!(cartridge.read(0x206123), Some(0x00)); + assert!(cartridge.write(0x206123, 0xA5)); + assert_eq!(cartridge.read(0x206123), Some(0xA5)); + assert_eq!(cartridge.read(0x216123), Some(0xA5)); + assert_eq!(cartridge.read(0xA06123), Some(0xA5)); + assert!(!cartridge.write(0x208000, 0xC3)); + } + + #[test] + fn save_ram_can_be_restored_from_persisted_bytes() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + let mut save_ram = vec![0x5A; cartridge.save_ram().len()]; + save_ram[0x0123] = 0xC3; + + cartridge.load_save_ram(&save_ram).unwrap(); + + assert_eq!(cartridge.save_ram()[0x0123], 0xC3); + assert_eq!(cartridge.read(0x700123), Some(0xC3)); + assert_eq!(cartridge.read(0x702123), Some(0xC3)); + } + + #[test] + fn save_ram_restore_rejects_size_mismatch() { + let mut cartridge = Cartridge::from_bytes(&build_lorom()).unwrap(); + + assert_eq!( + cartridge.load_save_ram(&[0x5A]).unwrap_err(), + CartridgeError::InvalidSaveRamSize { + expected: 8 * 1024, + actual: 1 + } + ); + } + + #[test] + fn rejects_unsupported_ram_size_codes() { + let mut rom = build_lorom(); + rom[0x7FD8] = 0x09; + + assert_eq!( + Cartridge::from_bytes(&rom).unwrap_err(), + CartridgeError::UnsupportedRamSizeCode(0x09) + ); + } + + #[test] + fn rejects_non_lorom_headers() { + let mut rom = build_lorom(); + rom[0x7FD5] = 0x21; + assert_eq!( + Cartridge::from_bytes(&rom).unwrap_err(), + CartridgeError::UnsupportedMapMode(0x21) + ); + } + + #[test] + fn detects_requested_enhancement_chips_from_headers() { + for (title, mapper_kind, map_mode, chipset, subtype, rom_size_code, expected) in [ + ( + "SA1 TEST HEADER", + MapperKind::Sa1, + 0x23, + 0x34, + None, + 0x0A, + EnhancementChip::Sa1, + ), + ( + "GSU1 TEST HEADER", + MapperKind::LoRom, + 0x20, + 0x13, + None, + 0x0A, + EnhancementChip::SuperFxGsu1, + ), + ( + "GSU2 TEST HEADER", + MapperKind::LoRom, + 0x20, + 0x1A, + None, + 0x0C, + EnhancementChip::SuperFxGsu2, + ), + ( + "CX4 TEST HEADER", + MapperKind::LoRom, + 0x20, + 0xF3, + Some(0x03), + 0x0A, + EnhancementChip::Cx4, + ), + ( + "CX4 HITACHI HEADER", + MapperKind::LoRom, + 0x20, + 0xF3, + Some(0x10), + 0x0A, + EnhancementChip::Cx4, + ), + ( + "DSP1 TEST HEADER", + MapperKind::LoRom, + 0x20, + 0x03, + None, + 0x0A, + EnhancementChip::Dsp1, + ), + ( + "DSP1A FASTROM HDR", + MapperKind::LoRom, + 0x30, + 0x05, + None, + 0x0A, + EnhancementChip::Dsp1, + ), + ( + "DSP1B TEST HEADER", + MapperKind::HiRom, + 0x21, + 0x05, + None, + 0x0A, + EnhancementChip::Dsp1B, + ), + ] { + let rom = match mapper_kind { + MapperKind::LoRom | MapperKind::Sa1 => { + build_lorom_with_header(title, map_mode, chipset, subtype, rom_size_code) + } + MapperKind::HiRom => { + build_hirom_with_header(title, map_mode, chipset, subtype, rom_size_code) + } + }; + let cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.header().mapper_kind(), mapper_kind); + assert_eq!(cartridge.header().chipset(), chipset); + assert_eq!(cartridge.header().expansion_chip_subtype(), subtype); + assert_eq!(cartridge.header().enhancement_chip(), expected); + } + } + + #[test] + fn does_not_misdetect_other_dsp_headers_as_dsp1() { + for (title, map_mode, chipset) in [("DSP2 HEADER", 0x20, 0x05), ("DSP4 HEADER", 0x30, 0x03)] + { + let cartridge = Cartridge::from_bytes(&build_lorom_with_header( + title, map_mode, chipset, None, 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::None); + } + + let mut dsp3_rom = build_lorom_with_header("DSP3 HEADER", 0x30, 0x05, None, 0x0A); + dsp3_rom[HEADER_OFFSET + 0x1A] = 0xB2; + let cartridge = Cartridge::from_bytes(&dsp3_rom).unwrap(); + + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::None); + } + + #[test] + fn rejects_sa1_map_mode_without_sa1_chipset() { + let rom = build_lorom_with_header("BAD SA1 HEADER", 0x23, 0x00, None, 0x0A); + + assert_eq!( + Cartridge::from_bytes(&rom).unwrap_err(), + CartridgeError::UnsupportedMapMode(0x23) + ); + } + + #[test] + fn rejects_sa1_map_mode_with_unverified_sa1_family_chipset() { + let rom = build_lorom_with_header("BAD SA1 CHIPSET", 0x23, 0x33, None, 0x0A); + + assert_eq!( + Cartridge::from_bytes(&rom).unwrap_err(), + CartridgeError::UnsupportedMapMode(0x23) + ); + } + + #[test] + fn does_not_report_sa1_without_sa1_map_mode() { + let cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "PLAIN LOROM", + 0x20, + 0x34, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::None); + } + + #[test] + fn sa1_register_and_iram_windows_are_accessible_without_hiding_rom() { + let mut cartridge = + Cartridge::from_bytes(&build_lorom_with_header("SA1 MMIO", 0x23, 0x34, None, 0x0A)) + .unwrap(); + + assert_eq!(cartridge.read(0x002200), Some(0x00)); + assert!(cartridge.write(0x002200, 0x5A)); + assert_eq!(cartridge.read(0x002200), Some(0x5A)); + assert_eq!(cartridge.read(0x802200), Some(0x5A)); + + assert_eq!(cartridge.read(0x003000), Some(0x00)); + assert!(cartridge.write(0x003000, 0xC3)); + assert_eq!(cartridge.read(0x003000), Some(0x00)); + assert!(cartridge.write(0x002229, 0x01)); + assert!(cartridge.write(0x003000, 0xC3)); + assert_eq!(cartridge.read(0x003000), Some(0xC3)); + + assert_eq!(cartridge.read(0xC08000), Some(0xA2)); + } + + #[test] + fn sa1_iram_write_protection_masks_cpu_pages() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x03)).unwrap(); + + assert!(cartridge.write(0x003100, 0x11)); + assert_eq!(cartridge.read(0x003100), Some(0x00)); + + assert!(cartridge.write(0x002229, 0x02)); + assert!(cartridge.write(0x003100, 0x22)); + assert_eq!(cartridge.read(0x003100), Some(0x22)); + assert!(cartridge.write(0x003200, 0x33)); + assert_eq!(cartridge.read(0x003200), Some(0x00)); + + assert!(cartridge.write(0x002229, 0x06)); + assert!(cartridge.write(0x003200, 0x44)); + assert_eq!(cartridge.read(0x003200), Some(0x44)); + } + + #[test] + fn sa1_status_registers_reflect_control_and_dma_flags() { + let mut rom = build_sa1_rom(0x10000, 0x03); + rom[0] = 0x5A; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.read(0x002300), Some(0x00)); + assert_eq!(cartridge.read(0x002301), Some(0x00)); + + assert!(cartridge.write(0x002209, 0xD3)); + assert_eq!(cartridge.read(0x002300), Some(0xD3)); + assert!(cartridge.write(0x002202, 0x80)); + assert_eq!(cartridge.read(0x002300), Some(0x53)); + + assert!(cartridge.write(0x002200, 0x9A)); + assert_eq!(cartridge.read(0x002301), Some(0x9A)); + assert!(cartridge.write(0x00220B, 0x90)); + assert_eq!(cartridge.read(0x002301), Some(0x0A)); + + write_word(&mut cartridge, 0x002238, 1); + assert!(cartridge.write(0x002230, 0x80)); + assert!(cartridge.write(0x002236, 0x03)); + assert_eq!(cartridge.read(0x002301).unwrap() & 0x20, 0x20); + assert!(cartridge.write(0x00220B, 0x20)); + assert_eq!(cartridge.read(0x002301).unwrap() & 0x20, 0x00); + + assert!(cartridge.write(0x002230, 0xB0)); + assert!(cartridge.write(0x002236, 0x03)); + assert_eq!(cartridge.read(0x002300).unwrap() & 0x20, 0x20); + assert!(cartridge.write(0x002202, 0x20)); + assert_eq!(cartridge.read(0x002300).unwrap() & 0x20, 0x00); + } + + #[test] + fn sa1_timer_latches_counters_and_sets_irq_flag() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x03)).unwrap(); + + write_word(&mut cartridge, 0x002212, 0x007F); + write_word(&mut cartridge, 0x002214, 0x0005); + assert!(cartridge.write(0x002210, 0x03)); + + cartridge.tick_sa1_timer(1, 5, 4); + + assert_eq!(cartridge.read(0x002301).unwrap() & 0x40, 0x40); + assert_eq!(cartridge.read_mut(0x002302), Some(0x7F)); + assert_eq!(cartridge.read_mut(0x002303), Some(0x00)); + assert_eq!(cartridge.read_mut(0x002304), Some(0x05)); + assert_eq!(cartridge.read_mut(0x002305), Some(0x00)); + + cartridge.tick_sa1_timer(2, 6, 4); + assert_eq!(cartridge.read(0x002302), Some(0x7F)); + assert_eq!(cartridge.read(0x002304), Some(0x05)); + assert_eq!(cartridge.read_mut(0x002302), Some(0xD4)); + assert_eq!(cartridge.read_mut(0x002304), Some(0x06)); + + assert!(cartridge.write(0x00220B, 0x40)); + assert_eq!(cartridge.read(0x002301).unwrap() & 0x40, 0x00); + + assert!(cartridge.write(0x002211, 0x00)); + assert_eq!(cartridge.read_mut(0x002302), Some(0x00)); + assert_eq!(cartridge.read_mut(0x002304), Some(0x00)); + } + + #[test] + fn sa1_bwram_maps_direct_and_system_windows() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "SA1 BWRAM", + 0x23, + 0x34, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.read(0x006000), Some(0x00)); + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x006000, 0x5A)); + assert_eq!(cartridge.read(0x006000), Some(0x5A)); + assert_eq!(cartridge.read(0x806000), Some(0x5A)); + assert_eq!(cartridge.read(0x400000), Some(0x5A)); + + assert!(cartridge.write(0x407FFF, 0xC3)); + assert_eq!(cartridge.read(0x007FFF), Some(0xC3)); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + } + + #[test] + fn sa1_bwram_write_protection_requires_enable_or_unprotected_range() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert_eq!(cartridge.read(0x002226), Some(0x00)); + assert_eq!(cartridge.read(0x002227), Some(0x00)); + assert_eq!(cartridge.read(0x002228), Some(0x0F)); + assert!(cartridge.write(0x006000, 0xAA)); + assert_eq!(cartridge.read(0x006000), Some(0x00)); + + assert!(cartridge.write(0x002228, 0x00)); + assert!(cartridge.write(0x006000, 0x11)); + assert_eq!(cartridge.read(0x006000), Some(0x00)); + assert!(cartridge.write(0x006100, 0x22)); + assert_eq!(cartridge.read(0x006100), Some(0x22)); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x006000, 0x33)); + assert_eq!(cartridge.read(0x006000), Some(0x33)); + + assert!(cartridge.write(0x002226, 0x00)); + assert!(cartridge.write(0x002227, 0x80)); + assert!(cartridge.write(0x006000, 0x44)); + assert_eq!(cartridge.read(0x006000), Some(0x44)); + } + + #[test] + fn sa1_super_mmc_physical_banks_use_runtime_selectors() { + let mut rom = build_sa1_rom(0x400000, 0x03); + rom[0x000000] = 0x11; + rom[0x100000] = 0x22; + rom[0x200000] = 0x33; + rom[0x300000] = 0x44; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.read(0x002220), Some(0x00)); + assert_eq!(cartridge.read(0x002221), Some(0x01)); + assert_eq!(cartridge.read(0x002222), Some(0x02)); + assert_eq!(cartridge.read(0x002223), Some(0x03)); + assert_eq!(cartridge.read(0x002228), Some(0x0F)); + assert_eq!(cartridge.read(0xC00000), Some(0x11)); + assert_eq!(cartridge.read(0xD00000), Some(0x22)); + assert_eq!(cartridge.read(0xE00000), Some(0x33)); + assert_eq!(cartridge.read(0xF00000), Some(0x44)); + + assert!(cartridge.write(0x002220, 0x03)); + assert!(cartridge.write(0x002221, 0x00)); + assert!(cartridge.write(0x002222, 0x01)); + assert!(cartridge.write(0x002223, 0x02)); + + assert_eq!(cartridge.read(0xC00000), Some(0x44)); + assert_eq!(cartridge.read(0xD00000), Some(0x11)); + assert_eq!(cartridge.read(0xE00000), Some(0x22)); + assert_eq!(cartridge.read(0xF00000), Some(0x33)); + } + + #[test] + fn sa1_super_mmc_lorom_mirrors_require_xmode() { + let mut rom = build_sa1_rom(0x400000, 0x03); + rom[0x000000] = 0x11; + rom[0x100000] = 0x22; + rom[0x300000] = 0x44; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.read(0x008000), Some(0x11)); + assert_eq!(cartridge.read(0x208000), Some(0x22)); + assert_eq!(cartridge.read(0x808000), Some(0x11)); + + assert!(cartridge.write(0x002220, 0x03)); + assert_eq!(cartridge.read(0x008000), Some(0x11)); + + assert!(cartridge.write(0x002220, 0x83)); + assert_eq!(cartridge.read(0x008000), Some(0x44)); + assert_eq!(cartridge.read(0x808000), Some(0x44)); + + assert!(cartridge.write(0x002221, 0x80)); + assert_eq!(cartridge.read(0x208000), Some(0x11)); + + assert!(cartridge.write(0x002221, 0x01)); + assert_eq!(cartridge.read(0x208000), Some(0x22)); + } + + #[test] + fn sa1_bmaps_shifts_system_bwram_window() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert_eq!(cartridge.save_ram().len(), 16 * 1024); + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x006000, 0x11)); + assert_eq!(cartridge.read(0x400000), Some(0x11)); + + assert!(cartridge.write(0x002224, 0x01)); + assert_eq!(cartridge.read(0x002224), Some(0x01)); + assert_eq!(cartridge.read(0x006000), Some(0x00)); + assert!(cartridge.write(0x006000, 0x22)); + assert_eq!(cartridge.read(0x806000), Some(0x22)); + assert_eq!(cartridge.read(0x402000), Some(0x22)); + assert_eq!(cartridge.read(0x400000), Some(0x11)); + + assert!(cartridge.write(0x002224, 0x00)); + assert_eq!(cartridge.read(0x006000), Some(0x11)); + } + + #[test] + fn sa1_bmap_is_independent_from_bmaps_for_variable_data() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x400000, 0x11)); + assert!(cartridge.write(0x402000, 0x22)); + + assert!(cartridge.write(0x002224, 0x00)); + assert!(cartridge.write(0x002225, 0x01)); + assert_eq!(cartridge.read(0x006000), Some(0x11)); + + write_u24(&mut cartridge, 0x002259, 0x006000); + assert_eq!(cartridge.read(0x00230C), Some(0x22)); + assert_eq!(cartridge.read(0x002225), Some(0x01)); + } + + #[test] + fn sa1_bmap_bitmap_reads_variable_data_pixels() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x400000, 0xAB)); + assert!(cartridge.write(0x00223F, 0x00)); + assert!(cartridge.write(0x002225, 0x80)); + + write_u24(&mut cartridge, 0x002259, 0x006000); + assert_eq!(cartridge.read(0x00230C), Some(0x0B)); + assert_eq!(cartridge.read(0x00230D), Some(0x0A)); + + assert!(cartridge.write(0x400000, 0xE4)); + assert!(cartridge.write(0x00223F, 0x80)); + + write_u24(&mut cartridge, 0x002259, 0x006000); + assert_eq!(cartridge.read(0x00230C), Some(0x00)); + assert_eq!(cartridge.read(0x00230D), Some(0x01)); + } + + #[test] + fn sa1_bitmap_banks_always_read_variable_data_pixels() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x400000, 0xAB)); + assert!(cartridge.write(0x00223F, 0x00)); + assert!(cartridge.write(0x002225, 0x00)); + + write_u24(&mut cartridge, 0x002259, 0x006000); + assert_eq!(cartridge.read(0x00230C), Some(0xAB)); + + write_u24(&mut cartridge, 0x002259, 0x600000); + assert_eq!(cartridge.read(0x00230C), Some(0x0B)); + assert_eq!(cartridge.read(0x00230D), Some(0x0A)); + } + + #[test] + fn sa1_bitmap_banks_write_pixels_even_when_bmap_is_linear() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002227, 0x80)); + assert!(cartridge.write(0x00223F, 0x00)); + assert!(cartridge.write(0x002225, 0x00)); + + assert!(cartridge.write(0x600001, 0x0A)); + assert_eq!(cartridge.save_ram()[0], 0xA0); + assert_eq!(cartridge.read(0x600000), Some(0x00)); + assert_eq!(cartridge.read(0x600001), Some(0x0A)); + assert_eq!(cartridge.read(0x006000), Some(0xA0)); + } + + #[test] + fn sa1_variable_length_data_reads_rom_and_auto_increments() { + let mut rom = build_sa1_rom(0x400000, 0x03); + rom[0x000000] = 0x12; + rom[0x000001] = 0x34; + rom[0x000002] = 0x56; + rom[0x200000] = 0x77; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + write_u24(&mut cartridge, 0x002259, 0xC00000); + assert!(cartridge.write(0x002258, 0x84)); + assert_eq!(cartridge.read(0x00230C), Some(0x12)); + assert_eq!(cartridge.read_mut(0x00230D), Some(0x34)); + assert_eq!(cartridge.read_mut(0x00230C), Some(0x41)); + assert_eq!(cartridge.read_mut(0x00230D), Some(0x63)); + assert_eq!(cartridge.read_mut(0x00230C), Some(0x34)); + + write_u24(&mut cartridge, 0x002259, 0x808000); + assert_eq!(cartridge.read(0x00230C), Some(0x77)); + } + + #[test] + fn sa1_variable_length_data_reads_bwram_and_iram() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x400000, 0xAB)); + assert!(cartridge.write(0x002229, 0x01)); + assert!(cartridge.write(0x003000, 0xCD)); + + write_u24(&mut cartridge, 0x002259, 0x400000); + assert_eq!(cartridge.read(0x00230C), Some(0xAB)); + + write_u24(&mut cartridge, 0x002259, 0x003000); + assert_eq!(cartridge.read(0x00230C), Some(0xCD)); + } + + #[test] + fn sa1_normal_dma_copies_rom_to_iram() { + let mut rom = build_sa1_rom(0x400000, 0x03); + rom[0x000000] = 0xA1; + rom[0x000001] = 0xB2; + rom[0x000002] = 0xC3; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + write_u24(&mut cartridge, 0x002232, 0xC00000); + assert!(cartridge.write(0x002235, 0x00)); + write_word(&mut cartridge, 0x002238, 3); + assert!(cartridge.write(0x002230, 0x80)); + assert!(cartridge.write(0x002236, 0x03)); + + assert_eq!(cartridge.read(0x003300), Some(0xA1)); + assert_eq!(cartridge.read(0x003301), Some(0xB2)); + assert_eq!(cartridge.read(0x003302), Some(0xC3)); + } + + #[test] + fn sa1_normal_dma_copies_iram_to_bwram() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002229, 0x01)); + assert!(cartridge.write(0x003010, 0x44)); + assert!(cartridge.write(0x003011, 0x55)); + write_u24(&mut cartridge, 0x002232, 0x000010); + assert!(cartridge.write(0x002235, 0x00)); + assert!(cartridge.write(0x002236, 0x00)); + write_word(&mut cartridge, 0x002238, 2); + assert!(cartridge.write(0x002230, 0x86)); + assert!(cartridge.write(0x002237, 0x00)); + + assert_eq!(cartridge.read(0x400000), Some(0x44)); + assert_eq!(cartridge.read(0x400001), Some(0x55)); + } + + #[test] + fn sa1_character_conversion_type2_writes_planar_rows_to_iram() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x03)).unwrap(); + + assert!(cartridge.write(0x002235, 0x00)); + assert!(cartridge.write(0x002236, 0x03)); + assert!(cartridge.write(0x002230, 0xA0)); + assert!(cartridge.write(0x002231, 0x02)); + + for (index, value) in [0x01, 0x02, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02] + .into_iter() + .enumerate() + { + assert!(cartridge.write(0x002240 + index as u32, value)); + } + assert_eq!(cartridge.read(0x003300), Some(0xAA)); + assert_eq!(cartridge.read(0x003301), Some(0x55)); + + for (index, value) in [0x03, 0x00, 0x03, 0x00, 0x03, 0x00, 0x03, 0x00] + .into_iter() + .enumerate() + { + assert!(cartridge.write(0x002248 + index as u32, value)); + } + assert_eq!(cartridge.read(0x003302), Some(0xAA)); + assert_eq!(cartridge.read(0x003303), Some(0xAA)); + } + + #[test] + fn sa1_character_conversion_type1_buffers_bwram_rows_on_read() { + let mut cartridge = Cartridge::from_bytes(&build_sa1_rom(0x10000, 0x04)).unwrap(); + + assert!(cartridge.write(0x002226, 0x80)); + assert!(cartridge.write(0x400000, 0x99)); + assert!(cartridge.write(0x400001, 0x99)); + write_u24(&mut cartridge, 0x002232, 0x000000); + assert!(cartridge.write(0x002235, 0x00)); + assert!(cartridge.write(0x002231, 0x02)); + assert!(cartridge.write(0x002230, 0xB0)); + assert!(cartridge.write(0x002236, 0x03)); + + assert_eq!(cartridge.read_mut(0x400000), Some(0xAA)); + assert_eq!(cartridge.read_mut(0x400001), Some(0x55)); + assert_eq!(cartridge.read(0x003300), Some(0xAA)); + assert_eq!(cartridge.read(0x003301), Some(0x55)); + + assert!(cartridge.write(0x002231, 0x82)); + assert_eq!(cartridge.read_mut(0x400000), Some(0x99)); + } + + #[test] + fn sa1_arithmetic_multiplies_signed_operands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "SA1 ARITH MUL", + 0x23, + 0x34, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x002250, 0x00)); + write_word(&mut cartridge, 0x002251, (-1_i16) as u16); + write_word(&mut cartridge, 0x002253, 1); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0x0000_FFFF_FFFF); + + write_word(&mut cartridge, 0x002251, 5); + write_word(&mut cartridge, 0x002253, 3); + assert_eq!(read_u40(&mut cartridge, 0x002306), 15); + + write_word(&mut cartridge, 0x002253, 4); + assert_eq!(read_u40(&mut cartridge, 0x002306), 20); + + assert!(cartridge.write(0x002254, 0)); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0); + } + + #[test] + fn sa1_arithmetic_divides_signed_by_unsigned() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "SA1 ARITH DIV", + 0x23, + 0x34, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x002250, 0x01)); + write_word(&mut cartridge, 0x002251, 10); + write_word(&mut cartridge, 0x002253, 3); + assert_eq!(read_word(&mut cartridge, 0x002306), 3); + assert_eq!(read_word(&mut cartridge, 0x002308), 1); + + write_word(&mut cartridge, 0x002251, (-7_i16) as u16); + write_word(&mut cartridge, 0x002253, 3); + assert_eq!(read_word(&mut cartridge, 0x002306) as i16, -3); + assert_eq!(read_word(&mut cartridge, 0x002308), 2); + + assert!(cartridge.write(0x002254, 0)); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0); + + write_word(&mut cartridge, 0x002251, 99); + write_word(&mut cartridge, 0x002253, 0); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0); + } + + #[test] + fn sa1_arithmetic_accumulates_signed_products() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "SA1 ARITH SUM", + 0x23, + 0x34, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x002250, 0x02)); + write_word(&mut cartridge, 0x002251, 2); + write_word(&mut cartridge, 0x002253, 3); + write_word(&mut cartridge, 0x002251, 4); + write_word(&mut cartridge, 0x002253, 5); + assert_eq!(read_u40(&mut cartridge, 0x002306), 26); + assert_eq!(cartridge.read(0x00230B), Some(0x00)); + + assert!(cartridge.write(0x002250, 0x00)); + assert_eq!(read_u40(&mut cartridge, 0x002306), 26); + assert!(cartridge.write(0x002250, 0x02)); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0); + + write_word(&mut cartridge, 0x002251, (-1_i16) as u16); + write_word(&mut cartridge, 0x002253, 1); + assert_eq!(read_u40(&mut cartridge, 0x002306), 0x00FF_FFFF_FFFF); + assert_eq!(cartridge.read(0x00230B), Some(0x80)); + } + + #[test] + fn super_fx_register_window_is_accessible() { + let mut cartridge = + Cartridge::from_bytes(&build_lorom_with_header("GSU MMIO", 0x20, 0x13, None, 0x0A)) + .unwrap(); + + assert_eq!(cartridge.read(0x003000), Some(0x00)); + assert!(cartridge.write(0x003000, 0x24)); + assert_eq!(cartridge.read(0x003000), Some(0x24)); + assert_eq!(cartridge.read(0x803000), Some(0x24)); + assert_eq!(cartridge.read(0x00303B), Some(0x04)); + assert!(cartridge.write(0x00303B, 0xFF)); + assert_eq!(cartridge.read(0x00303B), Some(0x04)); + assert!(cartridge.write(0x003033, 0x01)); + assert_eq!(cartridge.read(0x003033), Some(0x01)); + assert!(cartridge.write(0x003034, 0xFF)); + assert_eq!(cartridge.read(0x003034), Some(0x7F)); + assert!(cartridge.write(0x003036, 0x12)); + assert_eq!(cartridge.read(0x003036), Some(0x12)); + assert!(cartridge.write(0x003037, 0xAA)); + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x003039, 0x01)); + assert!(cartridge.write(0x00303A, 0x15)); + assert_eq!(cartridge.read(0x003037), Some(0xAA)); + assert_eq!(cartridge.read(0x003038), Some(0x03)); + assert_eq!(cartridge.read(0x003039), Some(0x01)); + assert_eq!(cartridge.read(0x00303A), Some(0x15)); + assert!(cartridge.write(0x00303C, 0x01)); + assert_eq!(cartridge.read(0x00303C), Some(0x01)); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + } + + const GSU_PIXEL_TEST_PROGRAM: [u8; 28] = [ + 0x02, 0xA0, 0x05, 0x4E, 0xA4, 0x00, 0xA5, 0x08, 0x22, 0xB4, 0xA1, 0x00, 0xAC, 0x08, 0x2D, + 0xBF, 0x4C, 0x3C, 0x01, 0xD4, 0xB4, 0x3F, 0x65, 0x08, 0xEF, 0x01, 0x00, 0x01, + ]; + const GSU_PIXEL_TEST_TILE_4BPP: [u8; 32] = [ + 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, + 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, 0xFF, 0x00, + 0xFF, 0x00, + ]; + const GSU_DEMO_PROGRAM: [u8; 103] = [ + 0x02, 0xF1, 0x00, 0x0C, 0xF8, 0x02, 0x00, 0xF0, 0xAA, 0x66, 0x31, 0x21, 0x58, 0xF0, 0x55, + 0xCC, 0x31, 0x21, 0x58, 0xF0, 0xAA, 0x99, 0x31, 0x21, 0x58, 0xF0, 0x55, 0x33, 0x31, 0x21, + 0x58, 0xF0, 0xAA, 0x66, 0x31, 0x21, 0x58, 0xF0, 0x55, 0xCC, 0x31, 0x21, 0x58, 0xF0, 0xAA, + 0x99, 0x31, 0x21, 0x58, 0xF0, 0x55, 0x33, 0x31, 0x21, 0x58, 0xF0, 0x1E, 0x01, 0x31, 0x21, + 0x58, 0xF0, 0x3C, 0x03, 0x31, 0x21, 0x58, 0xF0, 0x78, 0x07, 0x31, 0x21, 0x58, 0xF0, 0xF0, + 0x0F, 0x31, 0x21, 0x58, 0xF0, 0xE1, 0x1F, 0x31, 0x21, 0x58, 0xF0, 0xC3, 0x3F, 0x31, 0x21, + 0x58, 0xF0, 0x87, 0x7F, 0x31, 0x21, 0x58, 0xF0, 0x0F, 0xFF, 0x31, 0x00, 0x01, + ]; + const GSU_DEMO_TILE_4BPP: [u8; 32] = [ + 0xAA, 0x66, 0x55, 0xCC, 0xAA, 0x99, 0x55, 0x33, 0xAA, 0x66, 0x55, 0xCC, 0xAA, 0x99, 0x55, + 0x33, 0x1E, 0x01, 0x3C, 0x03, 0x78, 0x07, 0xF0, 0x0F, 0xE1, 0x1F, 0xC3, 0x3F, 0x87, 0x7F, + 0x0F, 0xFF, + ]; + const GSU_RAM_LOAD_STORE_PROGRAM: [u8; 30] = [ + 0xF1, 0x00, 0x01, 0xF0, 0xEF, 0xBE, 0x31, 0x3D, 0x41, 0xF2, 0x10, 0x01, 0xB0, 0x3D, 0x32, + 0x41, 0xF3, 0x20, 0x01, 0xB0, 0x33, 0xFD, 0x30, 0x01, 0xB0, 0x3D, 0x3D, 0x00, 0x01, 0x01, + ]; + const GSU_ALU_BRANCH_PROGRAM: &[u8] = &[ + 0xA0, 0x0F, 0x13, 0xB0, 0x3E, 0x51, 0xB3, 0x03, 0xF1, 0x00, 0x02, 0xB0, 0x31, 0xB3, 0x3E, + 0x77, 0x09, 0x08, 0xF0, 0xAD, 0xDE, 0xF1, 0x10, 0x02, 0xB0, 0x31, 0xF4, 0x34, 0x12, 0xB4, + 0xC0, 0xF1, 0x04, 0x02, 0xB0, 0x31, 0xB4, 0x4D, 0xF1, 0x06, 0x02, 0xB0, 0x31, 0xF0, 0x0F, + 0x00, 0xF5, 0xF0, 0x00, 0xB0, 0xC5, 0xF1, 0x08, 0x02, 0xB0, 0x31, 0xA0, 0x06, 0xA5, 0x07, + 0xB0, 0x85, 0xF1, 0x0A, 0x02, 0xB0, 0x31, 0xF0, 0xF0, 0x00, 0xF5, 0x3C, 0x00, 0xB0, 0x75, + 0xF1, 0x0C, 0x02, 0xB0, 0x31, 0xFD, 0xDC, 0x00, 0x9D, 0xF0, 0xEF, 0xBE, 0xF1, 0x12, 0x02, + 0xB0, 0x31, 0x00, 0x01, 0x01, + ]; + const GSU_ALU_VARIANTS_PROGRAM: &[u8] = &[ + 0xF0, 0x10, 0x00, 0xF2, 0x03, 0x00, 0xB0, 0x62, 0xF1, 0x00, 0x02, 0x31, 0xF0, 0x10, 0x00, + 0xB0, 0x3E, 0x65, 0xF1, 0x02, 0x02, 0x31, 0xF0, 0xF0, 0x00, 0xB0, 0x3E, 0xCF, 0xF1, 0x04, + 0x02, 0x31, 0xF0, 0xFF, 0x00, 0xB0, 0x3F, 0xCF, 0xF1, 0x06, 0x02, 0x31, 0xF0, 0xF0, 0x00, + 0xF2, 0x0F, 0x0F, 0xB0, 0x3D, 0xC2, 0xF1, 0x08, 0x02, 0x31, 0xF0, 0x07, 0x00, 0xB0, 0x3E, + 0x86, 0xF1, 0x0A, 0x02, 0x31, 0xF4, 0x01, 0x00, 0xE4, 0xB4, 0x3E, 0x50, 0xF1, 0x0C, 0x02, + 0x31, 0xF0, 0xF0, 0x00, 0xB0, 0x4F, 0xF1, 0x0E, 0x02, 0x31, 0xF0, 0xAB, 0x12, 0xB0, 0x9E, + 0xF1, 0x10, 0x02, 0x31, 0xF0, 0x80, 0x00, 0xB0, 0x95, 0xF1, 0x12, 0x02, 0x31, 0xF0, 0x80, + 0xFF, 0xB0, 0x96, 0xF1, 0x14, 0x02, 0x31, 0x00, 0x01, + ]; + const GSU_CONDITIONAL_BRANCH_PROGRAM: &[u8] = &[ + 0x05, 0x07, 0xF1, 0x00, 0x03, 0xF0, 0xAD, 0xDE, 0x31, 0xF1, 0x00, 0x03, 0xF0, 0x34, 0x12, + 0x31, 0xF0, 0x00, 0x00, 0x3E, 0x61, 0x0B, 0x07, 0xF1, 0x02, 0x03, 0xF0, 0xAD, 0xDE, 0x31, + 0xF1, 0x02, 0x03, 0xF0, 0xFE, 0xCA, 0x31, 0xF0, 0x02, 0x00, 0x3E, 0x61, 0x0D, 0x07, 0xF1, + 0x04, 0x03, 0xF0, 0xAD, 0xDE, 0x31, 0xF1, 0x04, 0x03, 0xF0, 0xEF, 0xBE, 0x31, 0xF0, 0x00, + 0x00, 0x3E, 0x61, 0x00, 0x01, + ]; + const GSU_DIRECT_RAM_PROGRAM: &[u8] = &[ + 0xF2, 0x33, 0x22, 0x3E, 0xF2, 0x00, 0x03, 0x3D, 0xF3, 0x00, 0x03, 0x3E, 0xF3, 0x10, 0x03, + 0xF2, 0x55, 0x44, 0x3E, 0xF2, 0x01, 0x03, 0x3D, 0xF4, 0x01, 0x03, 0xF4, 0x77, 0x66, 0x90, + 0x3D, 0xF5, 0x01, 0x03, 0x3E, 0xF5, 0x20, 0x03, 0x00, 0x01, + ]; + const GSU_SOURCE_STORE_PROGRAM: [u8; 19] = [ + 0xF1, 0xEF, 0xBE, 0xB1, 0xF2, 0x00, 0x03, 0x32, 0xF1, 0xAB, 0x12, 0xB1, 0xF2, 0x02, 0x03, + 0x3D, 0x32, 0x00, 0x01, + ]; + const GSU_ALU_EXTENSIONS_PROGRAM: &[u8] = &[ + 0x91, 0xF0, 0x02, 0x00, 0x3E, 0x61, 0xF0, 0xFF, 0xFF, 0x3F, 0x51, 0xF1, 0x00, 0x03, 0x31, + 0xF0, 0x00, 0x00, 0x3E, 0x61, 0xF0, 0x03, 0x00, 0xF1, 0x01, 0x00, 0x3D, 0x61, 0xF1, 0x02, + 0x03, 0x31, 0xF0, 0xFF, 0x00, 0x3F, 0x7F, 0xF1, 0x04, 0x03, 0x31, 0xF0, 0x01, 0x80, 0x04, + 0xF1, 0x06, 0x03, 0x31, 0x97, 0xF1, 0x08, 0x03, 0x31, 0xF0, 0xFE, 0x00, 0xF1, 0x02, 0x00, + 0x3D, 0x81, 0xF1, 0x0A, 0x03, 0x31, 0xF7, 0xCD, 0xAB, 0xF8, 0x12, 0xEF, 0x70, 0xF1, 0x0C, + 0x03, 0x31, 0x3E, 0xFB, 0x0E, 0x03, 0xF0, 0x00, 0x40, 0xF6, 0x00, 0x40, 0xB0, 0x9F, 0xF1, + 0x10, 0x03, 0x31, 0xF0, 0x00, 0x40, 0x3D, 0x9F, 0xF1, 0x12, 0x03, 0x31, 0x00, 0x01, + ]; + const GSU_LOB_SIGN_PROGRAM: [u8; 6] = [0xF0, 0x80, 0x00, 0x9E, 0x00, 0x01]; + const GSU_LOB_ZERO_PROGRAM: [u8; 6] = [0xF0, 0x00, 0x01, 0x9E, 0x00, 0x01]; + const GSU_HIB_SIGN_PROGRAM: [u8; 6] = [0xF0, 0x00, 0x80, 0xC0, 0x00, 0x01]; + const GSU_BITMAP_2BPP_RPIX_PROGRAM: &[u8] = &[ + 0xF0, 0x03, 0x00, 0x4E, 0x4C, 0xF1, 0x00, 0x00, 0x3D, 0x4C, 0xF1, 0x00, 0x01, 0x31, 0x00, + 0x01, + ]; + const GSU_BITMAP_8BPP_PROGRAM: &[u8] = &[0xF0, 0xA5, 0x00, 0x4E, 0x4C, 0x00, 0x01]; + const GSU_BITMAP_X8_PLOT_PROGRAM: &[u8] = &[ + 0xF0, 0x01, 0x00, 0x4E, 0xF1, 0x08, 0x00, 0xF2, 0x00, 0x00, 0x4C, 0x00, 0x01, + ]; + const GSU_BITMAP_X128_PLOT_PROGRAM: &[u8] = &[ + 0xF0, 0x01, 0x00, 0x4E, 0xF1, 0x80, 0x00, 0xF2, 0x00, 0x00, 0x4C, 0x00, 0x01, + ]; + const GSU_CACHE_PROGRAM: &[u8] = &[0x02, 0x00, 0x01]; + const GSU_LJMP_SOURCE_PROGRAM: &[u8] = &[ + 0xF0, 0x00, 0x80, 0xF8, 0x01, 0x00, 0xB0, 0x3D, 0x98, 0x00, 0x01, + ]; + const GSU_LJMP_TARGET_PROGRAM: &[u8] = &[0xF1, 0x00, 0x04, 0xF0, 0xEF, 0xBE, 0x31, 0x00, 0x01]; + const GSU_ROM_STORE_PROGRAM: [u8; 8] = [0xF1, 0x00, 0x01, 0xF0, 0xEF, 0xBE, 0x31, 0x00]; + const GSU_MOVE_REGISTER_PROGRAM: [u8; 11] = [ + 0xF1, 0xEF, 0xBE, 0x21, 0x10, 0xF1, 0x40, 0x01, 0x31, 0x00, 0x01, + ]; + const GSU_MOVES_OVERFLOW_SET_PROGRAM: [u8; 6] = [0xF1, 0x80, 0x00, 0x20, 0xB1, 0x00]; + const GSU_MOVES_OVERFLOW_CLEAR_PROGRAM: [u8; 6] = [0xF1, 0x01, 0x00, 0x20, 0xB1, 0x00]; + const GSU_IMMEDIATE_LOAD_FLAGS_PROGRAM: [u8; 4] = [0xF1, 0x00, 0x00, 0x00]; + const GSU_IBT_SIGN_EXTENSION_PROGRAM: [u8; 9] = + [0xA1, 0x80, 0x21, 0x10, 0xF1, 0x40, 0x01, 0x31, 0x00]; + const GSU_RAM_LOAD_FLAGS_PROGRAM: [u8; 5] = [0xF1, 0x40, 0x01, 0x41, 0x00]; + const GSU_ROM_WITH_STORE_PROGRAM: [u8; 10] = + [0xF0, 0xEF, 0xBE, 0xF1, 0x00, 0x01, 0x22, 0xB1, 0x32, 0x00]; + const GSU_GETB_PROGRAM: [u8; 9] = [0xFE, 0x23, 0x81, 0xEF, 0xF1, 0x00, 0x01, 0x31, 0x00]; + const GSU_GETB_FLAGS_PROGRAM: [u8; 6] = [0xFE, 0x23, 0x01, 0xEF, 0x00, 0x01]; + const GSU_CPU_ROMBR_GETB_PROGRAM: [u8; 10] = + [0xFE, 0x00, 0x80, 0xEF, 0xF1, 0x00, 0x01, 0x31, 0x00, 0x01]; + const GSU_CPU_RAMB_STORE_PROGRAM: [u8; 9] = + [0xF0, 0xEF, 0xBE, 0xF1, 0x00, 0x01, 0x31, 0x00, 0x01]; + const GSU_ROMB_GETB_PROGRAM: [u8; 15] = [ + 0xF0, 0x01, 0x00, 0x3F, 0xDF, 0xFE, 0x00, 0x80, 0xEF, 0xF1, 0x00, 0x01, 0x31, 0x00, 0x00, + ]; + const GSU_RAMB_PROGRAM: [u8; 16] = [ + 0xF0, 0x01, 0x00, 0x3E, 0xDF, 0xF0, 0xEF, 0xBE, 0xF1, 0x00, 0x01, 0x31, 0x00, 0x00, 0x00, + 0x00, + ]; + const GSU_SPRITE_SCALER_PROGRAM: &[u8] = include_bytes!( + "../../../roms/snes-coprocessor-tests/hirom-gsu-test/build/sprite_scaler.bin" + ); + const GSU_BITMASK_LUT: [u8; 8] = [0x80, 0x40, 0x20, 0x10, 0x08, 0x04, 0x02, 0x01]; + const CX4_PACKED_NIBBLE_PATTERN: [u8; 4] = [0x10, 0x32, 0x54, 0x76]; + const CX4_PATTERN_BITPLANES: [u8; 32] = [ + 0x55, 0x33, 0x55, 0x33, 0x55, 0x33, 0x55, 0x33, 0x55, 0x33, 0x55, 0x33, 0x55, 0x33, 0x55, + 0x33, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, 0x0F, 0x00, + 0x0F, 0x00, + ]; + + fn start_super_fx_program(cartridge: &mut Cartridge, pbr: u8, r15: u16) { + assert!(cartridge.write(0x003034, pbr)); + assert!(cartridge.write(0x00301E, (r15 & 0x00FF) as u8)); + assert!(cartridge.write(0x00301F, (r15 >> 8) as u8)); + } + + #[test] + fn super_fx_game_ram_maps_full_direct_banks_and_starts_programs() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU MMIO", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + assert_eq!( + cartridge.header().enhancement_chip(), + EnhancementChip::SuperFxGsu2 + ); + assert_eq!(cartridge.save_ram().len(), 8 * 1024); + assert_eq!(cartridge.read(0x00303B), Some(0x04)); + assert!(cartridge.write(0x700000, 0x34)); + assert!(cartridge.write(0x700001, 0x12)); + assert_eq!(cartridge.read(0x700000), Some(0x34)); + assert_eq!(cartridge.read(0x700001), Some(0x12)); + assert!(cartridge.write(0x702000, 0xA5)); + assert_eq!(cartridge.read(0x700000), Some(0xA5)); + + for (offset, value) in GSU_PIXEL_TEST_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700200 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, 0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0200); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + for (offset, expected) in GSU_PIXEL_TEST_TILE_4BPP.iter().copied().enumerate() { + assert_eq!(cartridge.read(0x700C00 + offset as u32), Some(expected)); + } + + for (offset, value) in GSU_DEMO_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700100 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0100); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + for (offset, expected) in GSU_DEMO_TILE_4BPP.iter().copied().enumerate() { + assert_eq!(cartridge.read(0x700C00 + offset as u32), Some(expected)); + } + assert_eq!(cartridge.read(0xC08000), Some(0xEA)); + } + + #[test] + fn super_fx_system_ram_window_mirrors_first_game_ram_page() { + let mut rom = build_hirom_with_header("HIROM GSU RAM MAP", 0x31, 0x15, None, 0x0C); + rom[HIROM_HEADER_OFFSET + 0x18] = 0x07; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.save_ram().len(), 128 * 1024); + assert!(cartridge.write(0x700123, 0x11)); + assert!(cartridge.write(0x710123, 0x22)); + assert_eq!(cartridge.read(0x700123), Some(0x11)); + assert_eq!(cartridge.read(0x710123), Some(0x22)); + assert_eq!(cartridge.read(0x006123), Some(0x11)); + assert_eq!(cartridge.read(0x016123), Some(0x11)); + assert_eq!(cartridge.read(0x3F6123), Some(0x11)); + assert_eq!(cartridge.read(0x806123), Some(0x11)); + assert_eq!(cartridge.read(0xBF6123), Some(0x11)); + + assert!(cartridge.write(0x016123, 0x33)); + assert_eq!(cartridge.read(0x700123), Some(0x33)); + assert_eq!(cartridge.read(0x710123), Some(0x22)); + } + + #[test] + fn super_fx_alt_loads_and_byte_stores_game_ram() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU RAM OPS", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_RAM_LOAD_STORE_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x700100), Some(0xEF)); + assert_eq!(cartridge.read(0x700101), Some(0xBE)); + assert_eq!(cartridge.read(0x700110), Some(0xEF)); + assert_eq!(cartridge.read(0x700111), Some(0x00)); + assert_eq!(cartridge.read(0x700120), Some(0xEF)); + assert_eq!(cartridge.read(0x700121), Some(0xBE)); + assert_eq!(cartridge.read(0x700130), Some(0xEF)); + assert_eq!(cartridge.read(0x700131), Some(0x00)); + } + + #[test] + fn super_fx_move_copies_between_registers_without_with_prefix() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU MOVE", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_MOVE_REGISTER_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700140), Some(0xEF)); + assert_eq!(cartridge.read(0x700141), Some(0xBE)); + } + + #[test] + fn super_fx_moves_sets_overflow_from_source_bit_seven() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU MOVES V", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_MOVES_OVERFLOW_SET_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1A, 0x10); + + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU MOVES NV", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + for (offset, value) in GSU_MOVES_OVERFLOW_CLEAR_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003030, 0x10)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1A, 0x00); + } + + #[test] + fn super_fx_immediate_loads_preserve_alu_flags() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU LOAD FLG", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_IMMEDIATE_LOAD_FLAGS_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003030, 0x08)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1A, 0x08); + } + + #[test] + fn super_fx_ibt_sign_extends_immediate_operand() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU IBT SIGN", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_IBT_SIGN_EXTENSION_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700140), Some(0x80)); + assert_eq!(cartridge.read(0x700141), Some(0xFF)); + } + + #[test] + fn super_fx_ram_loads_preserve_alu_flags() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU RAM FLAGS", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_RAM_LOAD_FLAGS_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003030, 0x08)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1A, 0x08); + } + + #[test] + fn super_fx_stop_advances_program_counter_once() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU STOP PC", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + assert!(cartridge.write(0x700080, 0x00)); + assert!(cartridge.write(0x700081, 0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x00301E), Some(0x81)); + assert_eq!(cartridge.read(0x00301F), Some(0x00)); + } + + #[test] + fn super_fx_executes_program_from_rom_pbr() { + let mut rom = build_hirom_with_header("HIROM GSU ROM OPS", 0x31, 0x15, None, 0x0C); + rom[..GSU_ROM_STORE_PROGRAM.len()].copy_from_slice(&GSU_ROM_STORE_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + assert_eq!(cartridge.read(0x003034), Some(0x00)); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x700100), Some(0xEF)); + assert_eq!(cartridge.read(0x700101), Some(0xBE)); + } + + #[test] + fn super_fx_starts_on_r15_high_and_restarts_on_go_flag() { + let mut rom = build_hirom_with_header("HIROM GSU GO", 0x31, 0x15, None, 0x0C); + let programs = [ + 0xF1, 0x00, 0x01, 0xF0, 0xEF, 0xBE, 0x31, 0x00, 0x01, 0xF1, 0x02, 0x01, 0xF0, 0xFE, + 0xCA, 0x31, 0x00, + ]; + rom[..programs.len()].copy_from_slice(&programs); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert!(cartridge.write(0x003034, 0x00)); + assert!(cartridge.write(0x00301E, 0x00)); + assert_eq!(cartridge.read(0x700100), Some(0x00)); + assert_eq!(cartridge.read(0x700101), Some(0x00)); + + assert!(cartridge.write(0x003030, 0x00)); + assert_eq!(cartridge.read(0x700100), Some(0x00)); + assert_eq!(cartridge.read(0x700101), Some(0x00)); + + assert!(cartridge.write(0x00301F, 0x80)); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x003031).unwrap() & 0x80, 0x80); + assert_eq!(cartridge.read_mut(0x003031).unwrap() & 0x80, 0x80); + assert_eq!(cartridge.read(0x003031).unwrap() & 0x80, 0x00); + assert_eq!(cartridge.read(0x700100), Some(0xEF)); + assert_eq!(cartridge.read(0x700101), Some(0xBE)); + assert_eq!(cartridge.read(0x700102), Some(0x00)); + assert_eq!(cartridge.read(0x700103), Some(0x00)); + assert_eq!(cartridge.read(0x003000), Some(0xEF)); + assert_eq!(cartridge.read(0x003001), Some(0xBE)); + assert_eq!(cartridge.read(0x00301E), Some(0x08)); + assert_eq!(cartridge.read(0x00301F), Some(0x80)); + + assert!(cartridge.write(0x003030, 0x20)); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x003031).unwrap() & 0x80, 0x80); + assert_eq!(cartridge.read(0x700102), Some(0xFE)); + assert_eq!(cartridge.read(0x700103), Some(0xCA)); + } + + #[test] + fn super_fx_rom_fetch_uses_pbr_for_with_lookahead() { + let mut rom = build_hirom_with_header("HIROM GSU ROM WITH", 0x31, 0x15, None, 0x0C); + rom[..GSU_ROM_WITH_STORE_PROGRAM.len()].copy_from_slice(&GSU_ROM_WITH_STORE_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.read(0x700100), Some(0xEF)); + assert_eq!(cartridge.read(0x700101), Some(0xBE)); + assert_eq!(cartridge.read(0x700000), Some(0x00)); + assert_eq!(cartridge.read(0x700001), Some(0x00)); + } + + #[test] + fn super_fx_getb_reads_rom_buffer() { + let mut rom = build_hirom_with_header("HIROM GSU GETB", 0x31, 0x15, None, 0x0C); + rom[0x0123] = 0x7A; + for (offset, value) in GSU_GETB_PROGRAM.iter().copied().enumerate() { + assert_ne!(offset, 0x0123); + rom[offset] = value; + } + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.read(0x700100), Some(0x7A)); + assert_eq!(cartridge.read(0x700101), Some(0x00)); + assert_eq!(cartridge.read(0x003036), Some(0x00)); + } + + #[test] + fn super_fx_getb_preserves_alu_flags() { + let mut rom = build_hirom_with_header("HIROM GSU GETB FLAGS", 0x31, 0x15, None, 0x0C); + rom[0x0123] = 0x80; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + for (offset, value) in GSU_GETB_FLAGS_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003030, 0x1E)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1E, 0x1E); + } + + #[test] + fn super_fx_romb_selects_rom_buffer_bank() { + let mut rom = build_hirom_with_header("HIROM GSU ROMB", 0x31, 0x15, None, 0x0C); + rom[0x8000] = 0x5C; + rom[..GSU_ROMB_GETB_PROGRAM.len()].copy_from_slice(&GSU_ROMB_GETB_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.read(0x700100), Some(0x5C)); + assert_eq!(cartridge.read(0x003036), Some(0x01)); + } + + #[test] + fn super_fx_ramb_selects_game_ram_bank() { + let mut rom = build_hirom_with_header("HIROM GSU RAMB", 0x31, 0x15, None, 0x0C); + rom[HIROM_HEADER_OFFSET + 0x18] = 0x07; + rom[..GSU_RAMB_PROGRAM.len()].copy_from_slice(&GSU_RAMB_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.save_ram()[0x0100], 0x00); + assert_eq!(cartridge.save_ram()[0x0101], 0x00); + assert_eq!(cartridge.save_ram()[0x10100], 0xEF); + assert_eq!(cartridge.save_ram()[0x10101], 0xBE); + assert_eq!(cartridge.read(0x00303C), Some(0x01)); + } + + #[test] + fn super_fx_cpu_bank_register_writes_seed_gsu_runtime_state() { + let mut rom = build_hirom_with_header("HIROM GSU CPU ROMB", 0x31, 0x15, None, 0x0C); + rom[0x0000] = 0x11; + rom[0x8000] = 0x5C; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + for (offset, value) in GSU_CPU_ROMBR_GETB_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003036, 0x81)); + assert_eq!(cartridge.read(0x003036), Some(0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700100), Some(0x5C)); + assert_eq!(cartridge.read(0x700101), Some(0x00)); + + let mut rom = build_hirom_with_header("HIROM GSU CPU RAMB", 0x31, 0x15, None, 0x0C); + rom[HIROM_HEADER_OFFSET + 0x18] = 0x07; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + for (offset, value) in GSU_CPU_RAMB_STORE_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x00303C, 0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.save_ram()[0x0100], 0x00); + assert_eq!(cartridge.save_ram()[0x0101], 0x00); + assert_eq!(cartridge.save_ram()[0x10100], 0xEF); + assert_eq!(cartridge.save_ram()[0x10101], 0xBE); + assert_eq!(cartridge.read(0x00303C), Some(0x01)); + } + + #[test] + fn super_fx_plot_ignores_ramb_framebuffer_bank() { + let mut rom = build_hirom_with_header("HIROM GSU RAMB PLOT", 0x31, 0x15, None, 0x0C); + rom[HIROM_HEADER_OFFSET + 0x18] = 0x07; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + let program = GSU_RAMB_PROGRAM[..5] + .iter() + .chain(GSU_PIXEL_TEST_PROGRAM.iter()) + .copied(); + for (offset, value) in program.enumerate() { + assert!(cartridge.write(0x700200 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, 0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0200); + + for (offset, expected) in GSU_PIXEL_TEST_TILE_4BPP.iter().copied().enumerate() { + assert_eq!(cartridge.read(0x700C00 + offset as u32), Some(expected)); + assert_eq!(cartridge.read(0x710C00 + offset as u32), Some(0x00)); + } + assert_eq!(cartridge.read(0x00303C), Some(0x01)); + } + + #[test] + fn super_fx_bitmap_modes_plot_and_read_pixels() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU BITMAP 2", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_BITMAP_2BPP_RPIX_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, 0x00)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700C00), Some(0x80)); + assert_eq!(cartridge.read(0x700C01), Some(0x80)); + assert_eq!(cartridge.read(0x700C10), Some(0x00)); + assert_eq!(cartridge.read(0x700100), Some(0x03)); + assert_eq!(cartridge.read(0x700101), Some(0x00)); + + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU BITMAP 8", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_BITMAP_8BPP_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, 0x03)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700C00), Some(0x80)); + assert_eq!(cartridge.read(0x700C01), Some(0x00)); + assert_eq!(cartridge.read(0x700C10), Some(0x80)); + assert_eq!(cartridge.read(0x700C11), Some(0x00)); + assert_eq!(cartridge.read(0x700C20), Some(0x00)); + assert_eq!(cartridge.read(0x700C21), Some(0x80)); + assert_eq!(cartridge.read(0x700C30), Some(0x00)); + assert_eq!(cartridge.read(0x700C31), Some(0x80)); + } + + #[test] + fn super_fx_bitmap_tile_addressing_uses_screen_height_modes() { + for (screen_mode, expected_address) in + [(0x01, 0x700E00), (0x05, 0x700E80), (0x21, 0x700F00)] + { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU HEIGHT", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_BITMAP_X8_PLOT_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, screen_mode)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(expected_address), Some(0x80)); + assert_eq!(cartridge.read(0x700C20), Some(0x00)); + } + + let mut rom = build_hirom_with_header("HIROM GSU OBJ", 0x31, 0x15, None, 0x0C); + rom[HIROM_HEADER_OFFSET + 0x18] = 0x07; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + for (offset, value) in GSU_BITMAP_X128_PLOT_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003038, 0x03)); + assert!(cartridge.write(0x00303A, 0x25)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x702C00), Some(0x80)); + assert_eq!(cartridge.read(0x700C20), Some(0x00)); + } + + #[test] + fn super_fx_cache_and_long_jump_update_cbr_and_pbr() { + let mut rom = build_hirom_with_header("HIROM GSU CACHE", 0x31, 0x15, None, 0x0C); + rom[..GSU_CACHE_PROGRAM.len()].copy_from_slice(GSU_CACHE_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert!(cartridge.write(0x00303E, 0xFF)); + assert!(cartridge.write(0x00303F, 0xFF)); + assert_eq!(cartridge.read(0x00303E), Some(0xFF)); + assert_eq!(cartridge.read(0x00303F), Some(0xFF)); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.read(0x00303E), Some(0x00)); + assert_eq!(cartridge.read(0x00303F), Some(0x80)); + assert!(cartridge.write(0x003030, 0x00)); + assert_eq!(cartridge.read(0x00303E), Some(0x00)); + assert_eq!(cartridge.read(0x00303F), Some(0x00)); + + let mut rom = build_hirom_with_header("HIROM GSU LJMP", 0x31, 0x15, None, 0x0C); + rom[..GSU_LJMP_SOURCE_PROGRAM.len()].copy_from_slice(GSU_LJMP_SOURCE_PROGRAM); + rom[0x8000..0x8000 + GSU_LJMP_TARGET_PROGRAM.len()] + .copy_from_slice(GSU_LJMP_TARGET_PROGRAM); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + start_super_fx_program(&mut cartridge, 0x00, 0x8000); + + assert_eq!(cartridge.read(0x003034), Some(0x01)); + assert_eq!(cartridge.read(0x00303E), Some(0x00)); + assert_eq!(cartridge.read(0x00303F), Some(0x80)); + assert_eq!(cartridge.read(0x700400), Some(0xEF)); + assert_eq!(cartridge.read(0x700401), Some(0xBE)); + } + + #[test] + fn super_fx_alu_and_branch_ops_update_game_ram() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU ALU OPS", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_ALU_BRANCH_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + assert_eq!(cartridge.read(0x700200), Some(0x08)); + assert_eq!(cartridge.read(0x700201), Some(0x00)); + assert_eq!(cartridge.read(0x700210), Some(0x00)); + assert_eq!(cartridge.read(0x700211), Some(0x00)); + assert_eq!(cartridge.read(0x700204), Some(0xF4)); + assert_eq!(cartridge.read(0x700205), Some(0x34)); + assert_eq!(cartridge.read(0x700206), Some(0x00)); + assert_eq!(cartridge.read(0x700207), Some(0x00)); + assert_eq!(cartridge.read(0x700208), Some(0xFF)); + assert_eq!(cartridge.read(0x700209), Some(0x00)); + assert_eq!(cartridge.read(0x70020A), Some(0x2A)); + assert_eq!(cartridge.read(0x70020B), Some(0x00)); + assert_eq!(cartridge.read(0x70020C), Some(0x30)); + assert_eq!(cartridge.read(0x70020D), Some(0x00)); + assert_eq!(cartridge.read(0x70020E), Some(0x00)); + assert_eq!(cartridge.read(0x70020F), Some(0x00)); + assert_eq!(cartridge.read(0x700212), Some(0x00)); + assert_eq!(cartridge.read(0x700213), Some(0x00)); + } + + #[test] + fn super_fx_alu_variants_update_game_ram() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU ALU VARIANTS", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_ALU_VARIANTS_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + for (offset, expected) in [ + 0x0D, 0x00, 0x0B, 0x00, 0xFF, 0x00, 0xF0, 0x00, 0xFF, 0x0F, 0x2A, 0x00, 0x00, 0x00, + 0x0F, 0xFF, 0xAB, 0x00, 0x80, 0xFF, 0xC0, 0xFF, + ] + .into_iter() + .enumerate() + { + assert_eq!(cartridge.read(0x700200 + offset as u32), Some(expected)); + } + } + + #[test] + fn super_fx_conditional_branches_use_alu_flags() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU BRANCHES", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_CONDITIONAL_BRANCH_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700300), Some(0x00)); + assert_eq!(cartridge.read(0x700301), Some(0x00)); + assert_eq!(cartridge.read(0x700302), Some(0x00)); + assert_eq!(cartridge.read(0x700303), Some(0x00)); + assert_eq!(cartridge.read(0x700304), Some(0x00)); + assert_eq!(cartridge.read(0x700305), Some(0x00)); + assert_eq!(cartridge.read(0x003030).unwrap() & 0x3E, 0x08); + } + + #[test] + fn super_fx_direct_ram_ops_and_sbk_use_last_address() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU DIRECT RAM", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_DIRECT_RAM_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700310), Some(0x33)); + assert_eq!(cartridge.read(0x700311), Some(0x22)); + assert_eq!(cartridge.read(0x003006), Some(0x33)); + assert_eq!(cartridge.read(0x003007), Some(0x22)); + assert_eq!(cartridge.read(0x700300), Some(0x66)); + assert_eq!(cartridge.read(0x700301), Some(0x77)); + assert_eq!(cartridge.read(0x003008), Some(0x77)); + assert_eq!(cartridge.read(0x003009), Some(0x66)); + assert_eq!(cartridge.read(0x00300A), Some(0x77)); + assert_eq!(cartridge.read(0x00300B), Some(0x66)); + assert_eq!(cartridge.read(0x700320), Some(0x77)); + assert_eq!(cartridge.read(0x700321), Some(0x66)); + } + + #[test] + fn super_fx_direct_stores_use_selected_source_register() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU SRC STORE", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_SOURCE_STORE_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700300), Some(0xEF)); + assert_eq!(cartridge.read(0x700301), Some(0xBE)); + assert_eq!(cartridge.read(0x700302), Some(0xAB)); + } + + #[test] + fn super_fx_extended_alu_ops_update_results() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU ALU EXT", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in GSU_ALU_EXTENSIONS_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x700300), Some(0x01)); + assert_eq!(cartridge.read(0x700301), Some(0x00)); + assert_eq!(cartridge.read(0x700302), Some(0x01)); + assert_eq!(cartridge.read(0x700303), Some(0x00)); + assert_eq!(cartridge.read(0x700304), Some(0xF0)); + assert_eq!(cartridge.read(0x700305), Some(0x00)); + assert_eq!(cartridge.read(0x700306), Some(0x02)); + assert_eq!(cartridge.read(0x700307), Some(0x00)); + assert_eq!(cartridge.read(0x700308), Some(0x01)); + assert_eq!(cartridge.read(0x700309), Some(0x80)); + assert_eq!(cartridge.read(0x70030A), Some(0xFC)); + assert_eq!(cartridge.read(0x70030B), Some(0x01)); + assert_eq!(cartridge.read(0x70030C), Some(0xEF)); + assert_eq!(cartridge.read(0x70030D), Some(0xAB)); + assert_eq!(cartridge.read(0x70030E), Some(0x82)); + assert_eq!(cartridge.read(0x70030F), Some(0x00)); + assert_eq!(cartridge.read(0x700310), Some(0x00)); + assert_eq!(cartridge.read(0x700311), Some(0x10)); + assert_eq!(cartridge.read(0x700312), Some(0x00)); + assert_eq!(cartridge.read(0x700313), Some(0x10)); + assert_eq!(cartridge.read(0x003008), Some(0x00)); + assert_eq!(cartridge.read(0x003009), Some(0x00)); + } + + #[test] + fn super_fx_lob_and_hib_use_byte_sign_flags() { + for (program, expected_flags) in [ + (GSU_LOB_SIGN_PROGRAM, 0x08), + (GSU_LOB_ZERO_PROGRAM, 0x02), + (GSU_HIB_SIGN_PROGRAM, 0x08), + ] { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU BYTE FLAG", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in program.iter().copied().enumerate() { + assert!(cartridge.write(0x700080 + offset as u32, value)); + } + assert!(cartridge.write(0x003030, 0x1E)); + start_super_fx_program(&mut cartridge, 0x70, 0x0080); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x1E, expected_flags); + } + } + + #[test] + fn super_fx_runs_sprite_scaler_fixture() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "HIROM GSU SCALER", + 0x31, + 0x15, + None, + 0x0C, + )) + .unwrap(); + + for (offset, value) in [8, 8, 8, 8, 0x00, 0x04, 1, 1, 0x00, 0x01, 0x00, 0x01] + .into_iter() + .enumerate() + { + assert!(cartridge.write(0x700000 + offset as u32, value)); + } + for (offset, value) in GSU_BITMASK_LUT.iter().copied().enumerate() { + assert!(cartridge.write(0x700060 + offset as u32, value)); + } + for (offset, value) in GSU_DEMO_TILE_4BPP.iter().copied().enumerate() { + assert!(cartridge.write(0x700400 + offset as u32, value)); + } + for (offset, value) in GSU_SPRITE_SCALER_PROGRAM.iter().copied().enumerate() { + assert!(cartridge.write(0x700100 + offset as u32, value)); + } + assert!(cartridge.write(0x00303A, 0x01)); + start_super_fx_program(&mut cartridge, 0x70, 0x0100); + + assert_eq!(cartridge.read(0x003030).unwrap() & 0x20, 0x00); + for (offset, expected) in GSU_DEMO_TILE_4BPP.iter().copied().enumerate() { + assert_eq!(cartridge.read(0x700C00 + offset as u32), Some(expected)); + } + } + + #[test] + fn cx4_register_window_is_accessible() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 MMIO", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.read(0x007F40), Some(0x00)); + assert!(cartridge.write(0x007F40, 0x66)); + assert_eq!(cartridge.read(0x007F40), Some(0x66)); + assert_eq!(cartridge.read(0x807F40), Some(0x66)); + assert!(cartridge.write(0x006000, 0x42)); + assert_eq!(cartridge.read(0x006000), Some(0x42)); + assert_eq!(cartridge.read(0x806000), Some(0x42)); + assert_eq!(cartridge.read(0x007F5E), Some(0x00)); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + } + + #[test] + fn cx4_absent_sram_window_reads_as_zero() { + let mut rom = build_lorom_with_header("CX4 NO SRAM", 0x20, 0xF3, Some(0x10), 0x0A); + let rom_index = crate::mapper::lorom_rom_index(0x700123, rom.len()).unwrap(); + rom[rom_index] = 0xCC; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert_eq!(cartridge.read(0x700123), Some(0x00)); + assert!(cartridge.write(0x700123, 0xAA)); + assert_eq!(cartridge.read(0x700123), Some(0x00)); + assert_eq!(cartridge.read(0xF00123), Some(0x00)); + } + + #[test] + fn cx4_executes_core_math_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 COMMANDS", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_u24(&mut cartridge, 0x007F80, 0x000123); + write_u24(&mut cartridge, 0x007F83, 0x000004); + assert!(cartridge.write(0x007F4F, 0x25)); + assert_eq!(read_u24(&mut cartridge, 0x007F80), 0x00048C); + + write_word(&mut cartridge, 0x007F80, 3); + write_word(&mut cartridge, 0x007F83, 4); + assert!(cartridge.write(0x007F4F, 0x15)); + assert_eq!(read_word(&mut cartridge, 0x007F80), 5); + + for offset in 0..0x800 { + assert!(cartridge.write(0x006000 + offset, 1)); + } + assert!(cartridge.write(0x007F4F, 0x40)); + assert_eq!(read_word(&mut cartridge, 0x007F80), 0x0800); + + assert!(cartridge.write(0x007F4D, 0x0E)); + assert!(cartridge.write(0x007F4F, 0x20)); + assert_eq!(cartridge.read(0x007F80), Some(0x08)); + + assert!(cartridge.write(0x007F4F, 0x89)); + assert_eq!(read_u24(&mut cartridge, 0x007F80), 0x054336); + } + + #[test] + fn cx4_executes_geometry_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 GEOMETRY", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_word(&mut cartridge, 0x007F81, 10); + write_word(&mut cartridge, 0x007F84, (-20_i16) as u16); + write_word(&mut cartridge, 0x007F87, 7); + assert!(cartridge.write(0x007F89, 0)); + assert!(cartridge.write(0x007F8A, 0)); + assert!(cartridge.write(0x007F8B, 0)); + write_word(&mut cartridge, 0x007F90, 0x0100); + assert!(cartridge.write(0x007F4F, 0x2D)); + assert_eq!(read_word(&mut cartridge, 0x007F80), 10); + assert_eq!(read_word(&mut cartridge, 0x007F83), (-20_i16) as u16); + + write_word(&mut cartridge, 0x007F80, 5); + write_word(&mut cartridge, 0x007F83, 10); + write_word(&mut cartridge, 0x007F86, 20); + write_word(&mut cartridge, 0x007F89, 8); + write_word(&mut cartridge, 0x007F8C, 0); + write_word(&mut cartridge, 0x007F8F, 0); + write_word(&mut cartridge, 0x007F93, 30); + assert!(cartridge.write(0x007F4F, 0x22)); + assert_eq!(cartridge.read(0x006800), Some(15)); + assert_eq!(cartridge.read(0x006900), Some(45)); + assert_eq!(cartridge.read(0x0068E0), Some(15)); + assert_eq!(cartridge.read(0x0069E0), Some(45)); + + write_word(&mut cartridge, 0x007F83, 7); + write_word(&mut cartridge, 0x007F89, 8); + assert!(cartridge.write(0x007F4F, 0x22)); + assert_eq!(cartridge.read(0x006800), Some(1)); + assert_eq!(cartridge.read(0x006900), Some(0)); + assert_eq!(cartridge.read(0x006801), Some(15)); + assert_eq!(cartridge.read(0x006901), Some(45)); + } + + #[test] + fn cx4_loads_lorom_data_into_internal_ram() { + let mut rom = build_lorom_with_header("CX4 LOAD", 0x20, 0xF3, Some(0x10), 0x0A); + rom[0x8123] = 0xAA; + rom[0x8124] = 0xBB; + rom[0x8125] = 0xCC; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + write_u24(&mut cartridge, 0x007F40, 0x018123); + write_word(&mut cartridge, 0x007F43, 3); + write_word(&mut cartridge, 0x007F45, 0x6008); + assert!(cartridge.write(0x007F47, 0x00)); + + assert_eq!(cartridge.read(0x006008), Some(0xAA)); + assert_eq!(cartridge.read(0x006009), Some(0xBB)); + assert_eq!(cartridge.read(0x00600A), Some(0xCC)); + } + + #[test] + fn cx4_executes_immediate_register_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 IMMEDIATE", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_u24(&mut cartridge, 0x007F80, 0x000077); + assert!(cartridge.write(0x007F4F, 0x5C)); + assert_eq!(read_u24(&mut cartridge, 0x007F80), 0x000030); + assert_eq!(cartridge.read(0x006000), Some(0x00)); + assert_eq!(cartridge.read(0x006003), Some(0xFF)); + assert_eq!(cartridge.read(0x00602F), Some(0x00)); + + write_u24(&mut cartridge, 0x007F80, 0x000020); + assert!(cartridge.write(0x007F4F, 0x66)); + assert_eq!(read_u24(&mut cartridge, 0x007F80), 0x000044); + assert_eq!(cartridge.read(0x006020), Some(0xFF)); + assert_eq!(cartridge.read(0x006027), Some(0x00)); + assert_eq!(cartridge.read(0x006043), Some(0x00)); + + write_u24(&mut cartridge, 0x007F80, 0x000BFE); + assert!(cartridge.write(0x007F4F, 0x7C)); + assert_eq!(read_u24(&mut cartridge, 0x007F80), 0x000C01); + assert_eq!(cartridge.read(0x006BFE), Some(0xFF)); + assert_eq!(cartridge.read(0x006BFF), Some(0xFE)); + } + + #[test] + fn cx4_disintegrates_packed_pixels_to_bitplanes() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 DISINTEGRATE", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_word(&mut cartridge, 0x007F80, 4); + write_word(&mut cartridge, 0x007F83, 4); + write_word(&mut cartridge, 0x007F86, 0x0100); + assert!(cartridge.write(0x007F89, 8)); + assert!(cartridge.write(0x007F8C, 8)); + write_word(&mut cartridge, 0x007F8F, 0x0100); + + write_cx4_packed_pattern(&mut cartridge); + + assert!(cartridge.write(0x007F4D, 0x0B)); + assert!(cartridge.write(0x007F4F, 0x00)); + + assert_cx4_pattern_bitplanes(&mut cartridge); + } + + #[test] + fn cx4_scale_rotates_packed_pixels_to_bitplanes() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 SCALE ROTATE", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_word(&mut cartridge, 0x007F80, 0); + write_word(&mut cartridge, 0x007F83, 4); + write_word(&mut cartridge, 0x007F86, 4); + assert!(cartridge.write(0x007F89, 8)); + assert!(cartridge.write(0x007F8C, 8)); + write_word(&mut cartridge, 0x007F8F, 0x1000); + write_word(&mut cartridge, 0x007F92, 0x1000); + write_cx4_packed_pattern(&mut cartridge); + + assert!(cartridge.write(0x007F4D, 0x03)); + assert!(cartridge.write(0x007F4F, 0x00)); + assert_cx4_pattern_bitplanes(&mut cartridge); + + assert!(cartridge.write(0x007F4D, 0x07)); + assert!(cartridge.write(0x007F4F, 0x00)); + assert_cx4_pattern_bitplanes(&mut cartridge); + } + + #[test] + fn cx4_applies_bitplane_wave() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 BITPLANE WAVE", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + for row in 0..8u32 { + write_word(&mut cartridge, 0x006A00 + row * 2, 0xFFFF); + write_word(&mut cartridge, 0x006A10 + row * 2, 0xFFFF); + } + for offset in 0..0x80 { + assert!(cartridge.write(0x006B00 + offset, 0xF0)); + } + + assert!(cartridge.write(0x007F83, 0)); + assert!(cartridge.write(0x007F4D, 0x0C)); + assert!(cartridge.write(0x007F4F, 0x00)); + + assert_eq!(read_word(&mut cartridge, 0x006000), 0xFFFF); + assert_eq!(read_word(&mut cartridge, 0x00600E), 0xFFFF); + assert_eq!(read_word(&mut cartridge, 0x006200), 0xFF00); + assert_eq!(read_word(&mut cartridge, 0x00680E), 0xFF00); + assert_eq!(read_word(&mut cartridge, 0x006010), 0xFFFF); + assert_eq!(read_word(&mut cartridge, 0x006210), 0xFF00); + } + + #[test] + fn cx4_transforms_line_vertices() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "CX4 LINES", + 0x20, + 0xF3, + Some(0x10), + 0x0A, + )) + .unwrap(); + + write_word(&mut cartridge, 0x007F80, 1); + assert!(cartridge.write(0x007F83, 0)); + assert!(cartridge.write(0x007F86, 0)); + assert!(cartridge.write(0x007F89, 0)); + assert!(cartridge.write(0x007F8C, 0x90)); + write_word(&mut cartridge, 0x006001, 10); + write_word(&mut cartridge, 0x006005, 20); + write_word(&mut cartridge, 0x006009, 0x0095); + + assert!(cartridge.write(0x007F4D, 0x05)); + assert!(cartridge.write(0x007F4F, 0x00)); + + assert_eq!(read_word(&mut cartridge, 0x006001), 0x008A); + assert_eq!(read_word(&mut cartridge, 0x006005), 0x0064); + assert_eq!(read_word(&mut cartridge, 0x006600), 23); + assert_eq!(read_word(&mut cartridge, 0x006602), 0x60); + assert_eq!(read_word(&mut cartridge, 0x006605), 0x40); + assert_eq!(read_word(&mut cartridge, 0x006608), 23); + assert_eq!(read_word(&mut cartridge, 0x00660A), 0x60); + assert_eq!(read_word(&mut cartridge, 0x00660D), 0x40); + } + + #[test] + fn cx4_draws_wireframe_from_rom() { + let mut rom = build_lorom_with_header("CX4 WIREFRAME", 0x20, 0xF3, Some(0x10), 0x0A); + rom[0x0100..0x0105].copy_from_slice(&[0x81, 0x10, 0x81, 0x16, 0x03]); + rom[0x0110..0x0116].copy_from_slice(&[0x00, 0x00, 0x00, 0x00, 0x00, 0x00]); + rom[0x0116..0x011C].copy_from_slice(&[0x00, 0x08, 0x00, 0x00, 0x00, 0x00]); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + write_u24(&mut cartridge, 0x007F80, 0x008100); + assert!(cartridge.write(0x006295, 1)); + assert!(cartridge.write(0x007F90, 0x80)); + + assert!(cartridge.write(0x007F4F, 0x01)); + assert_eq!(cartridge.read(0x0067E0), Some(0xF8)); + assert_eq!(cartridge.read(0x0067E1), Some(0xF8)); + + assert!(cartridge.write(0x0067E0, 0)); + assert!(cartridge.write(0x0067E1, 0)); + assert!(cartridge.write(0x007F4D, 0x08)); + assert!(cartridge.write(0x007F4F, 0x00)); + assert_eq!(cartridge.read(0x0067E0), Some(0xF8)); + assert_eq!(cartridge.read(0x0067E1), Some(0xF8)); + } + + #[test] + fn cx4_builds_oam_from_sprite_records() { + let mut rom = build_lorom_with_header("CX4 OAM", 0x20, 0xF3, Some(0x10), 0x0A); + rom[0x0100] = 0; + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert!(cartridge.write(0x006620, 1)); + write_word(&mut cartridge, 0x006220, 0x0012); + write_word(&mut cartridge, 0x006222, 0x0034); + assert!(cartridge.write(0x006224, 0x20)); + assert!(cartridge.write(0x006225, 0x40)); + assert!(cartridge.write(0x006226, 0x05)); + write_u24(&mut cartridge, 0x006227, 0x008100); + + assert!(cartridge.write(0x007F4D, 0x00)); + assert!(cartridge.write(0x007F4F, 0x00)); + + assert_eq!(cartridge.read(0x006000), Some(0x12)); + assert_eq!(cartridge.read(0x006001), Some(0x34)); + assert_eq!(cartridge.read(0x006002), Some(0x40)); + assert_eq!(cartridge.read(0x006003), Some(0x25)); + assert_eq!(cartridge.read(0x006200), Some(0x02)); + assert_eq!(cartridge.read(0x0061FD), Some(0xE0)); + } + + fn write_cx4_packed_pattern(cartridge: &mut Cartridge) { + for row in 0..8u32 { + for (column_pair, byte) in CX4_PACKED_NIBBLE_PATTERN.into_iter().enumerate() { + assert!(cartridge.write(0x006600 + row * 4 + column_pair as u32, byte)); + } + } + } + + fn assert_cx4_pattern_bitplanes(cartridge: &mut Cartridge) { + for (offset, expected) in CX4_PATTERN_BITPLANES.into_iter().enumerate() { + assert_eq!(cartridge.read(0x006000 + offset as u32), Some(expected)); + } + } + + fn write_word(cartridge: &mut Cartridge, address: u32, word: u16) { + let [low, high] = word.to_le_bytes(); + assert!(cartridge.write(address, low)); + assert!(cartridge.write(address + 1, high)); + } + + fn read_word(cartridge: &mut Cartridge, address: u32) -> u16 { + u16::from_le_bytes([ + cartridge.read(address).unwrap(), + cartridge.read(address + 1).unwrap(), + ]) + } + + fn write_u24(cartridge: &mut Cartridge, address: u32, value: u32) { + assert!(cartridge.write(address, value as u8)); + assert!(cartridge.write(address + 1, (value >> 8) as u8)); + assert!(cartridge.write(address + 2, (value >> 16) as u8)); + } + + fn read_u24(cartridge: &mut Cartridge, address: u32) -> u32 { + u32::from(cartridge.read(address).unwrap()) + | (u32::from(cartridge.read(address + 1).unwrap()) << 8) + | (u32::from(cartridge.read(address + 2).unwrap()) << 16) + } + + fn read_u40(cartridge: &mut Cartridge, address: u32) -> u64 { + (0..5).fold(0, |value, byte| { + value | (u64::from(cartridge.read(address + byte).unwrap()) << (byte * 8)) + }) + } + + #[test] + fn dsp1_lorom_register_window_reports_ready_status() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 MMIO", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.read(0x208000), Some(0x00)); + assert_eq!(cartridge.read(0x20C000), Some(0x84)); + assert_eq!(cartridge.read(0x308000), Some(0x00)); + assert_eq!(cartridge.read(0x30C000), Some(0x84)); + assert!(cartridge.write(0x30C000, 0x00)); + assert_eq!(cartridge.read(0x30C000), Some(0x84)); + assert!(cartridge.write(0x308000, 0x99)); + assert_eq!(cartridge.read(0x308000), Some(0x99)); + assert_eq!(cartridge.read(0xA0C000), Some(0x84)); + assert_eq!(cartridge.read(0xB0C000), Some(0x84)); + assert_eq!(cartridge.read(0x008000), Some(0xEA)); + } + + #[test] + fn dsp1_lorom_small_uses_20_3f_bank_window() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 MMIO BANKS", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.read(0x20C000), Some(0x84)); + assert_eq!(cartridge.read(0x30C000), Some(0x84)); + assert!(cartridge.write(0x208000, 0x2F)); + assert_eq!(cartridge.read(0x208000), Some(0x2F)); + assert!(!cartridge.write(0x600000, 0x2F)); + assert_eq!(cartridge.read(0x604000), Some(0x00)); + } + + fn write_dsp1_word(cartridge: &mut Cartridge, data_address: u32, word: u16) { + let [low, high] = word.to_le_bytes(); + assert!(cartridge.write(data_address, low)); + assert!(cartridge.write(data_address, high)); + } + + fn read_dsp1_word(cartridge: &mut Cartridge, data_address: u32) -> u16 { + let low = cartridge.read_mut(data_address).unwrap(); + let high = cartridge.read_mut(data_address).unwrap(); + u16::from_le_bytes([low, high]) + } + + #[test] + fn dsp1_lorom_executes_tier1_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 COMMANDS", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x308000, 0x00)); + assert_eq!(cartridge.read(0x30C000), Some(0x80)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x2000); + assert_eq!(cartridge.read(0x30C000), Some(0x84)); + + assert!(cartridge.write(0x308000, 0x20)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x2001); + + assert!(cartridge.write(0x308000, 0x0F)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + + assert!(cartridge.write(0x308000, 0x2F)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + + assert!(cartridge.write(0x308000, 0x08)); + write_dsp1_word(&mut cartridge, 0x308000, 3); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 12); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 169); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x18)); + write_dsp1_word(&mut cartridge, 0x308000, 3); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 12); + write_dsp1_word(&mut cartridge, 0x308000, 13); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x38)); + write_dsp1_word(&mut cartridge, 0x308000, 3); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 12); + write_dsp1_word(&mut cartridge, 0x308000, 13); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 1); + + assert!(cartridge.write(0x308000, 0x10)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x7FFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 1); + + assert!(cartridge.write(0x308000, 0x30)); + write_dsp1_word(&mut cartridge, 0x308000, 0x2000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x7FFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 2); + + assert!(cartridge.write(0x308000, 0x10)); + write_dsp1_word(&mut cartridge, 0x308000, (-0x4000_i16) as u16); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!( + read_dsp1_word(&mut cartridge, 0x308000), + (-0x4000_i16) as u16 + ); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 2); + + assert!(cartridge.write(0x308000, 0x10)); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x7FFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x002F); + } + + #[test] + fn dsp1_lorom_executes_geometry_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 GEOMETRY", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x308000, 0x04)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + + assert!(cartridge.write(0x308000, 0x0C)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 10); + write_dsp1_word(&mut cartridge, 0x308000, 20); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 20); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), (-10_i16) as u16); + + assert!(cartridge.write(0x308000, 0x1C)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x0000); + write_dsp1_word(&mut cartridge, 0x308000, 0x0000); + write_dsp1_word(&mut cartridge, 0x308000, 10); + write_dsp1_word(&mut cartridge, 0x308000, 20); + write_dsp1_word(&mut cartridge, 0x308000, 30); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 20); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), (-10_i16) as u16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 30); + + assert!(cartridge.write(0x308000, 0x14)); + write_dsp1_word(&mut cartridge, 0x308000, 100); + write_dsp1_word(&mut cartridge, 0x308000, 200); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 5); + write_dsp1_word(&mut cartridge, 0x308000, 7); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 100); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 205); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 7); + + assert!(cartridge.write(0x308000, 0x34)); + write_dsp1_word(&mut cartridge, 0x308000, 100); + write_dsp1_word(&mut cartridge, 0x308000, 200); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 10); + write_dsp1_word(&mut cartridge, 0x308000, 20); + write_dsp1_word(&mut cartridge, 0x308000, 30); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 80); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 210); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x4000 + 30); + + assert!(cartridge.write(0x308000, 0x28)); + write_dsp1_word(&mut cartridge, 0x308000, 3); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 12); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 13); + } + + #[test] + fn dsp1_lorom_executes_projection_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 PROJECT", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x308000, 0x02)); + write_dsp1_word(&mut cartridge, 0x308000, 100); + write_dsp1_word(&mut cartridge, 0x308000, 200); + write_dsp1_word(&mut cartridge, 0x308000, 300); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 100); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 200); + + assert!(cartridge.write(0x308000, 0x0A)); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + + assert!(cartridge.write(0x308000, 0x1A)); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + + assert!(cartridge.write(0x308000, 0x06)); + write_dsp1_word(&mut cartridge, 0x308000, 116); + write_dsp1_word(&mut cartridge, 0x308000, 232); + write_dsp1_word(&mut cartridge, 0x308000, 300); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 32); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + + assert!(cartridge.write(0x308000, 0x16)); + write_dsp1_word(&mut cartridge, 0x308000, 101); + write_dsp1_word(&mut cartridge, 0x308000, 200); + write_dsp1_word(&mut cartridge, 0x308000, (-20000_i16) as u16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x7FFF); + + assert!(cartridge.write(0x308000, 0x3E)); + write_dsp1_word(&mut cartridge, 0x308000, 16); + write_dsp1_word(&mut cartridge, 0x308000, 32); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 116); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 232); + } + + #[test] + fn dsp1_raster_command_streams_successive_scanlines() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 RASTER STREAM", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x308000, 0x02)); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0x0100); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x0A)); + write_dsp1_word(&mut cartridge, 0x308000, 1); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x00FF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x00FF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x00FE); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x00FE); + + assert!(cartridge.write(0x308000, 0x04)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x4000); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + } + + #[test] + fn dsp1_lorom_executes_matrix_commands() { + let mut cartridge = Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 MATRICES", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x308000, 0x01)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + + assert!(cartridge.write(0x308000, 0x0D)); + write_dsp1_word(&mut cartridge, 0x308000, 40); + write_dsp1_word(&mut cartridge, 0x308000, (-80_i16) as u16); + write_dsp1_word(&mut cartridge, 0x308000, 120); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 10); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), (-20_i16) as u16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 30); + + assert!(cartridge.write(0x308000, 0x03)); + write_dsp1_word(&mut cartridge, 0x308000, 40); + write_dsp1_word(&mut cartridge, 0x308000, (-80_i16) as u16); + write_dsp1_word(&mut cartridge, 0x308000, 120); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 10); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), (-20_i16) as u16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 30); + + assert!(cartridge.write(0x308000, 0x0B)); + write_dsp1_word(&mut cartridge, 0x308000, 40); + write_dsp1_word(&mut cartridge, 0x308000, (-80_i16) as u16); + write_dsp1_word(&mut cartridge, 0x308000, 120); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 10); + + assert!(cartridge.write(0x308000, 0x11)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert!(cartridge.write(0x308000, 0x1D)); + write_dsp1_word(&mut cartridge, 0x308000, 64); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x21)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert!(cartridge.write(0x308000, 0x2D)); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 64); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 16); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x01)); + write_dsp1_word(&mut cartridge, 0x308000, 0x4000); + write_dsp1_word(&mut cartridge, 0x308000, 0x2000); + write_dsp1_word(&mut cartridge, 0x308000, 0); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert!(cartridge.write(0x308000, 0x09)); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 1); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + + assert!(cartridge.write(0x308000, 0x03)); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 4); + write_dsp1_word(&mut cartridge, 0x308000, 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 1); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0); + } + + #[test] + fn dsp1_lorom_executes_memory_command_aliases() { + let new_cartridge = || { + Cartridge::from_bytes(&build_lorom_with_header( + "DSP1 MEMORY", + 0x20, + 0x03, + None, + 0x0A, + )) + .unwrap() + }; + + let mut cartridge = new_cartridge(); + assert!(cartridge.write(0x308000, 0x07)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + + let mut cartridge = new_cartridge(); + assert!(cartridge.write(0x308000, 0x27)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0100); + + let mut cartridge = new_cartridge(); + assert!(cartridge.write(0x308000, 0x17)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + for _ in 0..1023 { + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + assert_eq!(cartridge.read(0x30C000), Some(0x80)); + } + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + assert_eq!(cartridge.read(0x30C000), Some(0x84)); + + let mut cartridge = new_cartridge(); + assert!(cartridge.write(0x308000, 0x37)); + write_dsp1_word(&mut cartridge, 0x308000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x308000), 0x0000); + assert_eq!(cartridge.read(0x30C000), Some(0x80)); + } + + #[test] + fn dsp1b_reports_fixed_rom_version() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "DSP1B VERSION", + 0x21, + 0x05, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!( + cartridge.header().enhancement_chip(), + EnhancementChip::Dsp1B + ); + assert!(cartridge.write(0x006000, 0x2F)); + write_dsp1_word(&mut cartridge, 0x006000, 0xFFFF); + assert_eq!(read_dsp1_word(&mut cartridge, 0x006000), 0x0101); + } + + #[test] + fn dsp1_hirom_uses_legacy_bank_window() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "DSP1 HIROM", + 0x21, + 0x03, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.header().enhancement_chip(), EnhancementChip::Dsp1); + assert_eq!(cartridge.read(0x007000), Some(0x84)); + assert!(cartridge.write(0x207000, 0x5A)); + assert_eq!(cartridge.read(0x207000), Some(0x5A)); + } + + #[test] + fn dsp1b_hirom_uses_split_bank_window() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "DSP1B HIROM", + 0x21, + 0x05, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!( + cartridge.header().enhancement_chip(), + EnhancementChip::Dsp1B + ); + assert_eq!(cartridge.read(0x207000), Some(0x84)); + assert!(!cartridge.write(0x107000, 0x5A)); + assert_eq!(cartridge.read(0x107000), None); + } + + #[test] + fn dsp1_hirom_register_window_reports_ready_status() { + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "DSP1B MMIO", + 0x21, + 0x05, + None, + 0x0A, + )) + .unwrap(); + + assert_eq!(cartridge.read(0x006000), Some(0x00)); + assert_eq!(cartridge.read(0x007000), Some(0x84)); + assert!(cartridge.write(0x006000, 0x77)); + assert_eq!(cartridge.read(0x006000), Some(0x77)); + assert_eq!(cartridge.read(0x807000), Some(0x84)); + assert_eq!(cartridge.read(0xC08000), Some(0xEA)); + } + + #[test] + fn dsp1_register_window_supports_documented_board_maps() { + let mut rom = build_lorom_with_header("DSP1 2MB MMIO", 0x20, 0x03, None, 0x0B); + rom.resize(0x200000, 0xEA); + let mut cartridge = Cartridge::from_bytes(&rom).unwrap(); + + assert!(cartridge.write(0x600000, 0x55)); + assert_eq!(cartridge.read(0x600000), Some(0x55)); + assert_eq!(cartridge.read(0x604000), Some(0x84)); + assert_eq!(cartridge.read(0xE04000), Some(0x84)); + assert!(!cartridge.write(0x308000, 0x66)); + assert_eq!(cartridge.read(0x30C000), Some(0xEA)); + + let mut cartridge = Cartridge::from_bytes(&build_hirom_with_header( + "DSP1B MAD2 MMIO", + 0x21, + 0x05, + None, + 0x0A, + )) + .unwrap(); + + assert!(cartridge.write(0x206000, 0x66)); + assert_eq!(cartridge.read(0x206000), Some(0x66)); + assert_eq!(cartridge.read(0x207000), Some(0x84)); + assert_eq!(cartridge.read(0xA07000), Some(0x84)); + } +} diff --git a/snes/core/src/cpu.rs b/snes/core/src/cpu.rs new file mode 100644 index 00000000..7f08d304 --- /dev/null +++ b/snes/core/src/cpu.rs @@ -0,0 +1,9576 @@ +use crate::bus::CpuBus; + +pub(crate) const RESET_CYCLES: u8 = 7; +const BRA_OPCODE: u8 = 0x80; +const BRA_SELF_OFFSET: u8 = 0xFE; +const BRA_SELF_LOOP_CYCLES: u32 = 2; +const JMP_ABSOLUTE_OPCODE: u8 = 0x4C; +const JMP_ABSOLUTE_SELF_LOOP_CYCLES: u32 = 3; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum CpuFault { + UnsupportedOpcode { opcode: u8, bank: u8, address: u16 }, +} + +bitflags::bitflags! { + #[derive(Debug, Clone, Copy, PartialEq, Eq)] + pub struct CpuStatus: u8 { + const CARRY = 0b0000_0001; + const ZERO = 0b0000_0010; + const IRQ_DISABLE = 0b0000_0100; + const DECIMAL = 0b0000_1000; + const INDEX_8BIT = 0b0001_0000; + const ACCUMULATOR_8BIT = 0b0010_0000; + const OVERFLOW = 0b0100_0000; + const NEGATIVE = 0b1000_0000; + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct Registers { + pc: u16, + pb: u8, + db: u8, + s: u16, + d: u16, + a: u16, + x: u16, + y: u16, + p: CpuStatus, + e: bool, +} + +impl Default for Registers { + fn default() -> Self { + Self { + pc: 0, + pb: 0, + db: 0, + s: 0x01FF, + d: 0, + a: 0, + x: 0, + y: 0, + p: CpuStatus::IRQ_DISABLE | CpuStatus::INDEX_8BIT | CpuStatus::ACCUMULATOR_8BIT, + e: true, + } + } +} + +impl Registers { + pub fn pc(&self) -> u16 { + self.pc + } + + pub fn pb(&self) -> u8 { + self.pb + } + + pub fn db(&self) -> u8 { + self.db + } + + pub fn s(&self) -> u16 { + self.s + } + + pub fn d(&self) -> u16 { + self.d + } + + pub fn a(&self) -> u16 { + self.a + } + + pub fn x(&self) -> u16 { + self.x + } + + pub fn y(&self) -> u16 { + self.y + } + + pub fn status(&self) -> CpuStatus { + self.p + } + + pub fn emulation_mode(&self) -> bool { + self.e + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub enum CpuState { + #[default] + Resetting, + Running, + /// CPU has executed WAI and is suspended until an interrupt is asserted. + Waiting, + Stopped, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum ImpliedOp { + Nop, + Clc, + Cld, + Cli, + Clv, + Sec, + Sed, + Sei, + IncA, + DecA, + Inx, + Iny, + Dex, + Dey, + AslAcc, + RolAcc, + RorAcc, + LsrAcc, + Tax, + Tay, + Txa, + Tya, + Txy, + Tyx, + Tsx, + Tcd, + Tdc, + Tsc, + Tcs, + Xba, + Xce, + Txs, + Stp, + Wai, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Immediate8Op { + Rep, + Sep, + Wdm, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Immediate16Op { + Pea, + Per, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum ImmediateLoadTarget { + A, + X, + Y, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum ImmediateMathOp { + BitA, + AndA, + OraA, + EorA, + AdcA, + SbcA, + CmpA, + CmpX, + CmpY, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum ShiftOp { + Asl, + Rol, + Ror, + Lsr, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum TestModifyOp { + Trb, + Tsb, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum RmwOp { + Inc, + Dec, + Asl, + Lsr, + Rol, + Ror, + Trb, + Tsb, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum BlockMoveDirection { + Increment, + Decrement, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum AbsoluteOp { + Adc { + wide: bool, + }, + AdcIndexedX { + wide: bool, + }, + AdcIndexedY { + wide: bool, + }, + Sbc { + wide: bool, + }, + SbcIndexedX { + wide: bool, + }, + SbcIndexedY { + wide: bool, + }, + And { + wide: bool, + }, + AndIndexedX { + wide: bool, + }, + AndIndexedY { + wide: bool, + }, + Ora { + wide: bool, + }, + OraIndexedX { + wide: bool, + }, + OraIndexedY { + wide: bool, + }, + Eor { + wide: bool, + }, + EorIndexedX { + wide: bool, + }, + EorIndexedY { + wide: bool, + }, + Inc { + indexed_x: bool, + wide: bool, + }, + CmpA { + wide: bool, + }, + CmpAIndexedX { + wide: bool, + }, + CmpAIndexedY { + wide: bool, + }, + Dec { + indexed_x: bool, + wide: bool, + }, + Cpx { + wide: bool, + }, + Cpy { + wide: bool, + }, + Ldx { + wide: bool, + }, + LdxIndexedY { + wide: bool, + }, + Ldy { + wide: bool, + }, + LdyIndexedX { + wide: bool, + }, + Lda { + wide: bool, + }, + LdaIndexedX { + wide: bool, + }, + LdaIndexedY { + wide: bool, + }, + Sta { + wide: bool, + }, + StaIndexedX { + wide: bool, + }, + StaIndexedY { + wide: bool, + }, + Stx { + wide: bool, + }, + Sty { + wide: bool, + }, + Stz { + wide: bool, + }, + StzIndexedX { + wide: bool, + }, + Bit { + indexed_x: bool, + wide: bool, + }, + Trb { + wide: bool, + }, + Tsb { + wide: bool, + }, + Shift { + op: ShiftOp, + indexed_x: bool, + wide: bool, + }, + Jmp, + JmpIndirect, + JmpIndexedXIndirect, + JmlIndirect, + Jsr, + JsrIndexedXIndirect, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum DirectOp { + Adc { + wide: bool, + }, + AdcIndexedX { + wide: bool, + }, + Sbc { + wide: bool, + }, + SbcIndexedX { + wide: bool, + }, + And { + wide: bool, + }, + AndIndexedX { + wide: bool, + }, + Ora { + wide: bool, + }, + OraIndexedX { + wide: bool, + }, + Eor { + wide: bool, + }, + EorIndexedX { + wide: bool, + }, + Inc { + indexed_x: bool, + wide: bool, + }, + CmpA { + wide: bool, + }, + CmpAIndexedX { + wide: bool, + }, + Bit { + indexed_x: bool, + wide: bool, + }, + Trb { + wide: bool, + }, + Tsb { + wide: bool, + }, + Shift { + op: ShiftOp, + indexed_x: bool, + wide: bool, + }, + Lda { + wide: bool, + }, + Sta { + wide: bool, + }, + StaIndexedX { + wide: bool, + }, + Stx { + wide: bool, + }, + StxIndexedY { + wide: bool, + }, + Sty { + wide: bool, + }, + StyIndexedX { + wide: bool, + }, + Stz { + wide: bool, + }, + StzIndexedX { + wide: bool, + }, + Dec { + indexed_x: bool, + wide: bool, + }, + Ldx { + wide: bool, + }, + LdxIndexedY { + wide: bool, + }, + Ldy { + wide: bool, + }, + LdyIndexedX { + wide: bool, + }, + LdaIndexedX { + wide: bool, + }, + Cpx { + wide: bool, + }, + Cpy { + wide: bool, + }, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum DirectIndexedIndirectOp { + AdcA, + SbcA, + AndA, + OraA, + EorA, + CmpA, + Lda, + Sta, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum DirectIndirectOp { + AdcA, + SbcA, + AndA, + OraA, + EorA, + CmpA, + Lda, + Sta, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum DirectIndirectLongOp { + AdcA, + SbcA, + AndA, + OraA, + EorA, + CmpA, + Lda, + Sta, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum DirectIndirectIndexedYOp { + AdcA, + AdcALong, + SbcA, + SbcALong, + AndA, + AndALong, + OraA, + OraALong, + EorA, + EorALong, + CmpA, + CmpALong, + Lda, + LdaLong, + Sta, + StaLong, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum StackRelativeOp { + AdcA, + SbcA, + AndA, + OraA, + EorA, + CmpA, + Lda, + Sta, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum StackRelativeIndirectIndexedYOp { + AdcA, + SbcA, + AndA, + OraA, + EorA, + CmpA, + Lda, + Sta, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum AbsoluteLongOp { + Adc { wide: bool }, + AdcIndexedX { wide: bool }, + Sbc { wide: bool }, + SbcIndexedX { wide: bool }, + And { wide: bool }, + AndIndexedX { wide: bool }, + Ora { wide: bool }, + OraIndexedX { wide: bool }, + Eor { wide: bool }, + EorIndexedX { wide: bool }, + CmpA { wide: bool }, + CmpAIndexedX { wide: bool }, + Lda { wide: bool }, + LdaIndexedX { wide: bool }, + Sta { wide: bool }, + StaIndexedX { wide: bool }, + Jml, + Jsl, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum StackOp { + Pha, + Pla, + Php, + Plp, + Phx, + Phy, + Phb, + Phk, + Phd, + Plx, + Ply, + Plb, + Pld, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum BranchKind { + Always, + CarryClear, + CarrySet, + Equal, + NotEqual, + Minus, + Plus, + OverflowClear, + OverflowSet, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum ExceptionKind { + Brk, + Cop, + Nmi, + Irq, +} + +impl ExceptionKind { + fn vector_address(self, emulation: bool) -> u32 { + match (self, emulation) { + (Self::Cop, true) => 0x00FFF4, + (Self::Brk, true) => 0x00FFFE, + (Self::Nmi, true) => 0x00FFFA, + (Self::Irq, true) => 0x00FFFE, + (Self::Cop, false) => 0x00FFE4, + (Self::Brk, false) => 0x00FFE6, + (Self::Nmi, false) => 0x00FFEA, + (Self::Irq, false) => 0x00FFEE, + } + } + + /// BRK/COP encode an implicit operand byte that fetch_opcode already skipped; + /// return_address points one past the opcode so we add another +1 to skip + /// the operand. NMI has no operand: the return address is the instruction + /// immediately after the WAI (or the one that was about to execute). + fn increments_pc(self) -> bool { + matches!(self, Self::Brk | Self::Cop) + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum MicroState { + Reset { + remaining: u8, + low: u8, + }, + Fetch, + Implied(ImpliedOp), + Immediate8(Immediate8Op), + ImmediateLoadLow(ImmediateLoadTarget), + ImmediateLoadHigh(ImmediateLoadTarget, u8), + ImmediateMathLow(ImmediateMathOp), + ImmediateMathHigh(ImmediateMathOp, u8), + BlockMoveFirstBank(BlockMoveDirection), + BlockMoveSecondBank(BlockMoveDirection, u8), + BlockMoveTransfer { + direction: BlockMoveDirection, + source_bank: u8, + dest_bank: u8, + }, + BranchLongLow, + BranchLongHigh(u8), + Direct(DirectOp), + DirectMathHigh { + op: ImmediateMathOp, + address: u16, + low: u8, + }, + DirectReadHigh { + address: u16, + low: u8, + }, + DirectReadXHigh { + address: u16, + low: u8, + }, + DirectReadYHigh { + address: u16, + low: u8, + }, + DirectIncHigh { + address: u16, + low: u8, + }, + DirectDecHigh { + address: u16, + low: u8, + }, + DirectBitHigh { + address: u16, + low: u8, + }, + DirectTestModifyHigh { + op: TestModifyOp, + address: u16, + low: u8, + }, + DirectShiftHigh { + op: ShiftOp, + address: u16, + low: u8, + }, + DirectIndexedIndirect(DirectIndexedIndirectOp), + DirectIndirect(DirectIndirectOp), + DirectIndirectLong(DirectIndirectLongOp), + DirectIndirectIndexedY(DirectIndirectIndexedYOp), + DirectIndexedIndirectPointerHigh { + op: DirectIndexedIndirectOp, + pointer_addr: u16, + low: u8, + }, + DirectIndexedIndirectReadHigh { + op: DirectIndexedIndirectOp, + address: u32, + low: u8, + }, + StackRelative(StackRelativeOp), + StackRelativeReadHigh { + op: StackRelativeOp, + address: u16, + low: u8, + }, + StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp), + Stack(StackOp), + Immediate16Low(Immediate16Op), + Immediate16High(Immediate16Op, u8), + PeiPointerLow, + PeiPointerHigh { + pointer_addr: u16, + low: u8, + }, + PushLow(u8), + PushLowRaw { + low: u8, + stack_addr: u16, + }, + PullAccumulatorHigh(u8), + PullXHigh(u8), + PullYHigh(u8), + PullDHighRaw { + low: u8, + stack_addr: u16, + }, + Branch(BranchKind), + AbsoluteLow(AbsoluteOp), + AbsoluteHigh(AbsoluteOp, u8), + AbsoluteMathHigh { + op: ImmediateMathOp, + address: u32, + low: u8, + }, + AbsoluteReadAccumulatorHigh { + address: u32, + low: u8, + }, + AbsoluteReadXHigh { + address: u32, + low: u8, + }, + AbsoluteReadYHigh { + address: u32, + low: u8, + }, + AbsoluteBitHigh { + address: u32, + low: u8, + }, + AbsoluteTestModifyHigh { + op: TestModifyOp, + address: u32, + low: u8, + }, + AbsoluteIncHigh { + address: u32, + low: u8, + }, + AbsoluteDecHigh { + address: u32, + low: u8, + }, + AbsoluteShiftHigh { + op: ShiftOp, + address: u32, + low: u8, + }, + AbsoluteReadData { + target: ImmediateLoadTarget, + address: u32, + }, + AbsoluteMathData { + op: ImmediateMathOp, + address: u32, + }, + AbsoluteBitData { + address: u32, + }, + AbsoluteStoreData { + address: u32, + value: u8, + }, + AbsoluteRmwRead { + op: RmwOp, + address: u32, + }, + AbsoluteRmwModify { + op: RmwOp, + address: u32, + value: u8, + }, + AbsoluteRmwWrite { + address: u32, + value: u8, + }, + AbsoluteLongLow(AbsoluteLongOp), + AbsoluteLongHigh(AbsoluteLongOp, u8), + AbsoluteLongBank(AbsoluteLongOp, u16), + AbsoluteLongMathHigh { + op: ImmediateMathOp, + address: u32, + low: u8, + }, + AbsoluteLongReadAccumulatorHigh { + address: u32, + low: u8, + }, + WriteHigh { + address: u32, + value: u8, + }, + JsrPushHigh { + target: u16, + return_addr: u16, + stack_addr: Option, + }, + JsrPushLow { + target: u16, + return_addr: u16, + stack_addr: Option, + }, + JslPushBank { + target_bank: u8, + target_addr: u16, + return_addr: u16, + stack_addr: u16, + }, + JslPushHigh { + target_bank: u8, + target_addr: u16, + return_addr: u16, + stack_addr: u16, + }, + JslPushLow { + target_bank: u8, + target_addr: u16, + return_addr: u16, + stack_addr: u16, + }, + Exception(ExceptionKind), + ExceptionPushBank { + kind: ExceptionKind, + return_addr: u16, + }, + ExceptionPushHigh { + kind: ExceptionKind, + return_addr: u16, + }, + ExceptionPushLow { + kind: ExceptionKind, + return_addr: u16, + }, + ExceptionPushStatus(ExceptionKind), + ExceptionVectorLow(ExceptionKind), + ExceptionVectorHigh { + address: u32, + low: u8, + }, + RtsPullLow, + RtsPullHigh(u8), + RtsFinalize, + RtlPullLow, + RtlPullHigh { + low: u8, + stack_addr: u16, + }, + RtlPullBank { + addr: u16, + stack_addr: u16, + }, + RtiPullStatus, + RtiPullLow, + RtiPullHigh(u8), + RtiPullBank(u16), + Stopped, + /// WAI has been executed; CPU burns cycles here until an interrupt is pending. + WaitingForInterrupt, +} + +pub(crate) struct Cpu { + registers: Registers, + cycles: u64, + current_opcode: u8, + current_state: CpuState, + defer_irq_for_one_fetch: bool, + micro_state: MicroState, + fault: Option, +} + +impl Default for Cpu { + fn default() -> Self { + Self { + registers: Registers::default(), + cycles: 0, + current_opcode: 0, + current_state: CpuState::Resetting, + defer_irq_for_one_fetch: false, + micro_state: MicroState::Reset { + remaining: RESET_CYCLES, + low: 0, + }, + fault: None, + } + } +} + +impl Cpu { + pub(crate) fn new() -> Self { + Self::default() + } + + pub(crate) fn reset(&mut self) { + *self = Self::default(); + } + + pub(crate) fn registers(&self) -> &Registers { + &self.registers + } + + pub(crate) fn cycles(&self) -> u64 { + self.cycles + } + + pub(crate) fn current_opcode(&self) -> u8 { + self.current_opcode + } + + pub(crate) fn current_state(&self) -> CpuState { + self.current_state + } + + pub(crate) fn take_fault(&mut self) -> Option { + self.fault.take() + } + + pub(crate) fn step(&mut self, bus: &mut dyn CpuBus) { + if self.current_state == CpuState::Stopped { + return; + } + + self.cycles = self.cycles.wrapping_add(1); + match self.micro_state { + MicroState::Reset { remaining, low } => self.step_reset(bus, remaining, low), + MicroState::Fetch => self.fetch_opcode(bus), + MicroState::Implied(op) => self.execute_implied(op), + MicroState::Immediate8(op) => self.execute_immediate8(bus, op), + MicroState::ImmediateLoadLow(target) => self.execute_immediate_load_low(bus, target), + MicroState::ImmediateLoadHigh(target, low) => { + self.execute_immediate_load_high(bus, target, low) + } + MicroState::ImmediateMathLow(op) => self.execute_immediate_math_low(bus, op), + MicroState::ImmediateMathHigh(op, low) => { + self.execute_immediate_math_high(bus, op, low) + } + MicroState::BlockMoveFirstBank(direction) => { + self.execute_block_move_first_bank(bus, direction) + } + MicroState::BlockMoveSecondBank(direction, first_bank) => { + self.execute_block_move_second_bank(bus, direction, first_bank) + } + MicroState::BlockMoveTransfer { + direction, + source_bank, + dest_bank, + } => self.execute_block_move_transfer(bus, direction, source_bank, dest_bank), + MicroState::BranchLongLow => self.execute_branch_long_low(bus), + MicroState::BranchLongHigh(low) => self.execute_branch_long_high(bus, low), + MicroState::Direct(op) => self.execute_direct(bus, op), + MicroState::DirectMathHigh { op, address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = u16::from_le_bytes([low, high]); + self.apply_immediate_math(op, value); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectReadHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + self.registers.a = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.a); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectReadXHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + self.registers.x = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.x); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectReadYHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + self.registers.y = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.y); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectIncHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = u16::from_le_bytes([low, high]).wrapping_add(1); + bus.write(u32::from(address), value as u8); + bus.write(u32::from(address.wrapping_add(1)), (value >> 8) as u8); + self.update_nz16(value); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectDecHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = u16::from_le_bytes([low, high]).wrapping_sub(1); + bus.write(u32::from(address), value as u8); + bus.write(u32::from(address.wrapping_add(1)), (value >> 8) as u8); + self.update_nz16(value); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectBitHigh { address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + self.apply_memory_bit(u16::from_le_bytes([low, high])); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectTestModifyHigh { op, address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = self.apply_test_modify16(op, u16::from_le_bytes([low, high])); + bus.write(u32::from(address), value as u8); + bus.write(u32::from(address.wrapping_add(1)), (value >> 8) as u8); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectShiftHigh { op, address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = self.apply_shift16(op, u16::from_le_bytes([low, high])); + bus.write(u32::from(address), value as u8); + bus.write(u32::from(address.wrapping_add(1)), (value >> 8) as u8); + self.micro_state = MicroState::Fetch; + } + MicroState::DirectIndexedIndirect(op) => self.execute_direct_indexed_indirect(bus, op), + MicroState::DirectIndirect(op) => self.execute_direct_indirect(bus, op), + MicroState::DirectIndirectLong(op) => self.execute_direct_indirect_long(bus, op), + MicroState::DirectIndirectIndexedY(op) => { + self.execute_direct_indirect_indexed_y(bus, op) + } + MicroState::DirectIndexedIndirectPointerHigh { + op, + pointer_addr, + low, + } => { + let high_addr = if self.registers.e { + Self::page_wrapped_next(pointer_addr) + } else { + pointer_addr.wrapping_add(1) + }; + let high = bus.read(u32::from(high_addr)); + let target = u16::from_le_bytes([low, high]); + let address = self.full_data_address(target); + if matches!(op, DirectIndexedIndirectOp::Sta) { + self.store_accumulator(bus, address); + } else { + let low = bus.read(address); + if self.accumulator_is_8bit() { + self.apply_direct_indexed_indirect(op, u16::from(low)); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = + MicroState::DirectIndexedIndirectReadHigh { op, address, low }; + } + } + } + MicroState::DirectIndexedIndirectReadHigh { op, address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = u16::from_le_bytes([low, high]); + self.apply_direct_indexed_indirect(op, value); + self.micro_state = MicroState::Fetch; + } + MicroState::StackRelative(op) => self.execute_stack_relative(bus, op), + MicroState::StackRelativeReadHigh { op, address, low } => { + let high = bus.read(u32::from(address.wrapping_add(1))); + let value = u16::from_le_bytes([low, high]); + self.apply_stack_relative(op, value); + self.micro_state = MicroState::Fetch; + } + MicroState::StackRelativeIndirectIndexedY(op) => { + self.execute_stack_relative_indirect_indexed_y(bus, op) + } + MicroState::Stack(op) => self.execute_stack(bus, op), + MicroState::Immediate16Low(op) => self.execute_immediate16_low(bus, op), + MicroState::Immediate16High(op, low) => self.execute_immediate16_high(bus, op, low), + MicroState::PeiPointerLow => self.execute_pei_pointer_low(bus), + MicroState::PeiPointerHigh { pointer_addr, low } => { + let high = bus.read(u32::from(pointer_addr.wrapping_add(1))); + let stack_addr = self.stack_push_raw(bus, self.registers.s, high); + self.micro_state = MicroState::PushLowRaw { low, stack_addr }; + } + MicroState::PushLow(low) => { + self.stack_push(bus, low); + self.micro_state = MicroState::Fetch; + } + MicroState::PushLowRaw { low, stack_addr } => { + let stack_addr = self.stack_push_raw(bus, stack_addr, low); + self.registers.s = self.normalize_stack_pointer(stack_addr); + self.micro_state = MicroState::Fetch; + } + MicroState::PullAccumulatorHigh(low) => { + let high = self.stack_pop(bus); + self.registers.a = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.a); + self.micro_state = MicroState::Fetch; + } + MicroState::PullXHigh(low) => { + let high = self.stack_pop(bus); + self.registers.x = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.x); + self.micro_state = MicroState::Fetch; + } + MicroState::PullYHigh(low) => { + let high = self.stack_pop(bus); + self.registers.y = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.y); + self.micro_state = MicroState::Fetch; + } + MicroState::PullDHighRaw { low, stack_addr } => { + let (stack_addr, high) = self.stack_pop_raw(bus, stack_addr); + self.registers.s = self.normalize_stack_pointer(stack_addr); + self.registers.d = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.d); + self.micro_state = MicroState::Fetch; + } + MicroState::Branch(kind) => self.execute_branch(bus, kind), + MicroState::AbsoluteLow(op) => self.execute_absolute_low(bus, op), + MicroState::AbsoluteHigh(op, low) => self.execute_absolute_high(bus, op, low), + MicroState::AbsoluteMathHigh { op, address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = u16::from_le_bytes([low, high]); + self.apply_immediate_math(op, value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteReadAccumulatorHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + self.registers.a = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.a); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteReadXHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + self.registers.x = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.x); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteReadYHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + self.registers.y = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.y); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteBitHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + self.apply_memory_bit(u16::from_le_bytes([low, high])); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteTestModifyHigh { op, address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = self.apply_test_modify16(op, u16::from_le_bytes([low, high])); + bus.write(address, value as u8); + bus.write(address.wrapping_add(1), (value >> 8) as u8); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteIncHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = u16::from_le_bytes([low, high]).wrapping_add(1); + bus.write(address, value as u8); + bus.write(address.wrapping_add(1), (value >> 8) as u8); + self.update_nz16(value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteDecHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = u16::from_le_bytes([low, high]).wrapping_sub(1); + bus.write(address, value as u8); + bus.write(address.wrapping_add(1), (value >> 8) as u8); + self.update_nz16(value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteShiftHigh { op, address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = self.apply_shift16(op, u16::from_le_bytes([low, high])); + bus.write(address, value as u8); + bus.write(address.wrapping_add(1), (value >> 8) as u8); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteReadData { target, address } => { + let low = bus.read(address); + self.apply_immediate_load(target, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteMathData { op, address } => { + let low = bus.read(address); + self.apply_immediate_math(op, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteBitData { address } => { + let value = bus.read(address); + self.apply_memory_bit(u16::from(value)); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteStoreData { address, value } => { + bus.write(address, value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteRmwRead { op, address } => { + let value = bus.read(address); + self.micro_state = MicroState::AbsoluteRmwModify { op, address, value }; + } + MicroState::AbsoluteRmwModify { op, address, value } => { + let result = self.apply_rmw8(op, value); + self.micro_state = MicroState::AbsoluteRmwWrite { + address, + value: result, + }; + } + MicroState::AbsoluteRmwWrite { address, value } => { + bus.write(address, value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteLongLow(op) => self.execute_absolute_long_low(bus, op), + MicroState::AbsoluteLongHigh(op, low) => self.execute_absolute_long_high(bus, op, low), + MicroState::AbsoluteLongBank(op, addr) => { + self.execute_absolute_long_bank(bus, op, addr) + } + MicroState::AbsoluteLongMathHigh { op, address, low } => { + let high = bus.read(address.wrapping_add(1)); + let value = u16::from_le_bytes([low, high]); + self.apply_immediate_math(op, value); + self.micro_state = MicroState::Fetch; + } + MicroState::AbsoluteLongReadAccumulatorHigh { address, low } => { + let high = bus.read(address.wrapping_add(1)); + self.registers.a = u16::from_le_bytes([low, high]); + self.update_nz16(self.registers.a); + self.micro_state = MicroState::Fetch; + } + MicroState::WriteHigh { address, value } => { + bus.write(address, value); + self.micro_state = MicroState::Fetch; + } + MicroState::JsrPushHigh { + target, + return_addr, + stack_addr, + } => { + let stack_addr = if let Some(stack_addr) = stack_addr { + Some(self.stack_push_raw(bus, stack_addr, (return_addr >> 8) as u8)) + } else { + self.stack_push(bus, (return_addr >> 8) as u8); + None + }; + self.micro_state = MicroState::JsrPushLow { + target, + return_addr, + stack_addr, + }; + } + MicroState::JsrPushLow { + target, + return_addr, + stack_addr, + } => { + if let Some(stack_addr) = stack_addr { + let stack_addr = self.stack_push_raw(bus, stack_addr, return_addr as u8); + self.registers.s = self.normalize_stack_pointer(stack_addr); + } else { + self.stack_push(bus, return_addr as u8); + } + self.registers.pc = target; + self.micro_state = MicroState::Fetch; + } + MicroState::JslPushBank { + target_bank, + target_addr, + return_addr, + stack_addr, + } => { + let stack_addr = self.stack_push_raw(bus, stack_addr, self.registers.pb); + self.micro_state = MicroState::JslPushHigh { + target_bank, + target_addr, + return_addr, + stack_addr, + }; + } + MicroState::JslPushHigh { + target_bank, + target_addr, + return_addr, + stack_addr, + } => { + let stack_addr = self.stack_push_raw(bus, stack_addr, (return_addr >> 8) as u8); + self.micro_state = MicroState::JslPushLow { + target_bank, + target_addr, + return_addr, + stack_addr, + }; + } + MicroState::JslPushLow { + target_bank, + target_addr, + return_addr, + stack_addr, + } => { + let stack_addr = self.stack_push_raw(bus, stack_addr, return_addr as u8); + self.registers.s = self.normalize_stack_pointer(stack_addr); + self.registers.pb = target_bank; + self.registers.pc = target_addr; + self.micro_state = MicroState::Fetch; + } + MicroState::Exception(kind) => self.execute_exception(kind), + MicroState::ExceptionPushBank { kind, return_addr } => { + self.stack_push(bus, self.registers.pb); + self.micro_state = MicroState::ExceptionPushHigh { kind, return_addr }; + } + MicroState::ExceptionPushHigh { kind, return_addr } => { + self.stack_push(bus, (return_addr >> 8) as u8); + self.micro_state = MicroState::ExceptionPushLow { kind, return_addr }; + } + MicroState::ExceptionPushLow { kind, return_addr } => { + self.stack_push(bus, return_addr as u8); + self.micro_state = MicroState::ExceptionPushStatus(kind); + } + MicroState::ExceptionPushStatus(kind) => { + self.stack_push(bus, self.registers.p.bits()); + self.registers.p.insert(CpuStatus::IRQ_DISABLE); + self.registers.p.remove(CpuStatus::DECIMAL); + self.micro_state = MicroState::ExceptionVectorLow(kind); + } + MicroState::ExceptionVectorLow(kind) => { + let address = kind.vector_address(self.registers.e); + let low = bus.read(address); + self.micro_state = MicroState::ExceptionVectorHigh { + address: address.wrapping_add(1), + low, + }; + } + MicroState::ExceptionVectorHigh { address, low } => { + let high = bus.read(address); + self.registers.pb = 0; + self.registers.pc = u16::from_le_bytes([low, high]); + self.micro_state = MicroState::Fetch; + } + MicroState::RtsPullLow => { + let low = self.stack_pop(bus); + self.micro_state = MicroState::RtsPullHigh(low); + } + MicroState::RtsPullHigh(low) => { + let high = self.stack_pop(bus); + self.registers.pc = u16::from_le_bytes([low, high]); + self.micro_state = MicroState::RtsFinalize; + } + MicroState::RtsFinalize => { + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::Fetch; + } + MicroState::RtlPullLow => { + let (stack_addr, low) = self.stack_pop_raw(bus, self.registers.s); + self.micro_state = MicroState::RtlPullHigh { low, stack_addr }; + } + MicroState::RtlPullHigh { low, stack_addr } => { + let (stack_addr, high) = self.stack_pop_raw(bus, stack_addr); + self.micro_state = MicroState::RtlPullBank { + addr: u16::from_le_bytes([low, high]), + stack_addr, + }; + } + MicroState::RtlPullBank { addr, stack_addr } => { + let (stack_addr, bank) = self.stack_pop_raw(bus, stack_addr); + self.registers.s = self.normalize_stack_pointer(stack_addr); + self.registers.pb = bank; + self.registers.pc = addr.wrapping_add(1); + self.micro_state = MicroState::Fetch; + } + MicroState::RtiPullStatus => { + let value = self.stack_pop(bus); + self.set_status(value); + self.micro_state = MicroState::RtiPullLow; + } + MicroState::RtiPullLow => { + let low = self.stack_pop(bus); + self.micro_state = MicroState::RtiPullHigh(low); + } + MicroState::RtiPullHigh(low) => { + let high = self.stack_pop(bus); + let addr = u16::from_le_bytes([low, high]); + if self.registers.e { + self.registers.pc = addr; + self.defer_irq_for_one_fetch = true; + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::RtiPullBank(addr); + } + } + MicroState::RtiPullBank(addr) => { + let bank = self.stack_pop(bus); + self.registers.pb = bank; + self.registers.pc = addr; + self.defer_irq_for_one_fetch = true; + self.micro_state = MicroState::Fetch; + } + MicroState::Stopped => { + self.current_state = CpuState::Stopped; + } + MicroState::WaitingForInterrupt => self.execute_wai(bus), + } + self.refresh_state(); + } + + pub(crate) fn execute_instruction(&mut self, bus: &mut dyn CpuBus) -> u32 { + if self.current_state == CpuState::Stopped || self.fault.is_some() { + return 0; + } + + let start_cycles = self.cycles; + loop { + bus.tick(); + self.step(bus); + + if self.current_state == CpuState::Stopped || self.fault.is_some() { + break; + } + if matches!(self.micro_state, MicroState::Fetch) { + break; + } + if self.current_state == CpuState::Waiting + && matches!(self.micro_state, MicroState::WaitingForInterrupt) + { + break; + } + } + + self.cycles.wrapping_sub(start_cycles) as u32 + } + + pub(crate) fn execute_until( + &mut self, + bus: &mut dyn CpuBus, + allowed_cycles: u32, + ) -> (u32, bool) { + if allowed_cycles == 0 || self.current_state == CpuState::Stopped || self.fault.is_some() { + return (0, false); + } + + let start_cycles = self.cycles; + loop { + let used_cycles = self.cycles.wrapping_sub(start_cycles); + if used_cycles >= u64::from(allowed_cycles) + || self.current_state == CpuState::Stopped + || self.fault.is_some() + { + return (used_cycles as u32, used_cycles > u64::from(allowed_cycles)); + } + + let remaining_cycles = (u64::from(allowed_cycles) - used_cycles) as u32; + if self.try_fast_forward_waiting(bus, remaining_cycles) != 0 { + continue; + } + if self.try_fast_forward_self_branch(bus, remaining_cycles) != 0 { + continue; + } + + let instruction_cycles = self.execute_instruction(bus); + if instruction_cycles == 0 { + let used_cycles = self.cycles.wrapping_sub(start_cycles); + return (used_cycles as u32, used_cycles > u64::from(allowed_cycles)); + } + if self.current_state == CpuState::Waiting { + let used_cycles = self.cycles.wrapping_sub(start_cycles); + return (used_cycles as u32, used_cycles > u64::from(allowed_cycles)); + } + } + } + + fn try_fast_forward_waiting(&mut self, bus: &mut dyn CpuBus, allowed_cycles: u32) -> u32 { + if allowed_cycles == 0 + || self.current_state != CpuState::Waiting + || !matches!(self.micro_state, MicroState::WaitingForInterrupt) + || bus.has_pending_interrupt() + { + return 0; + } + + bus.tick_many(allowed_cycles); + self.cycles = self.cycles.wrapping_add(u64::from(allowed_cycles)); + allowed_cycles + } + + fn try_fast_forward_self_branch(&mut self, bus: &mut dyn CpuBus, allowed_cycles: u32) -> u32 { + if allowed_cycles < BRA_SELF_LOOP_CYCLES + || self.current_state != CpuState::Running + || !matches!(self.micro_state, MicroState::Fetch) + || self.defer_irq_for_one_fetch + || bus.has_pending_interrupt() + { + return 0; + } + + let opcode_address = self.full_pc(); + let operand_address = |offset: u16| { + (u32::from(self.registers.pb) << 16) | u32::from(self.registers.pc.wrapping_add(offset)) + }; + let (opcode, loop_cycles) = match bus.peek_side_effect_free(opcode_address) { + Some(BRA_OPCODE) + if bus.peek_side_effect_free(operand_address(1)) == Some(BRA_SELF_OFFSET) => + { + (BRA_OPCODE, BRA_SELF_LOOP_CYCLES) + } + Some(JMP_ABSOLUTE_OPCODE) + if allowed_cycles >= JMP_ABSOLUTE_SELF_LOOP_CYCLES + && bus.peek_side_effect_free(operand_address(1)) + == Some((self.registers.pc & 0x00FF) as u8) + && bus.peek_side_effect_free(operand_address(2)) + == Some((self.registers.pc >> 8) as u8) => + { + (JMP_ABSOLUTE_OPCODE, JMP_ABSOLUTE_SELF_LOOP_CYCLES) + } + _ => return 0, + }; + + let cycles = (allowed_cycles / loop_cycles) * loop_cycles; + bus.tick_many(cycles); + self.cycles = self.cycles.wrapping_add(u64::from(cycles)); + self.current_opcode = opcode; + cycles + } + + fn step_reset(&mut self, bus: &mut dyn CpuBus, remaining: u8, low: u8) { + match remaining { + 0 => self.micro_state = MicroState::Fetch, + 1 => { + let high = bus.read(0x00FFFD); + self.registers.pc = u16::from_le_bytes([low, high]); + self.registers.pb = 0; + self.registers.db = 0; + self.registers.d = 0; + self.micro_state = MicroState::Fetch; + } + 2 => { + let low = bus.read(0x00FFFC); + self.micro_state = MicroState::Reset { remaining: 1, low }; + } + _ => { + self.micro_state = MicroState::Reset { + remaining: remaining - 1, + low, + }; + } + } + } + + fn fetch_opcode(&mut self, bus: &mut dyn CpuBus) { + if bus.poll_nmi() { + self.start_nmi_sequence(); + return; + } + if self.defer_irq_for_one_fetch { + self.defer_irq_for_one_fetch = false; + } else if !self.registers.p.contains(CpuStatus::IRQ_DISABLE) && bus.poll_irq() { + self.start_irq_sequence(); + return; + } + let address = self.registers.pc; + let opcode = bus.read(self.full_pc()); + self.current_opcode = opcode; + self.registers.pc = self.registers.pc.wrapping_add(1); + let state = self.decode_opcode(opcode); + if matches!(state, MicroState::Stopped) { + self.fault = Some(CpuFault::UnsupportedOpcode { + opcode, + bank: self.registers.pb, + address, + }); + } + self.micro_state = state; + } + + fn execute_implied(&mut self, op: ImpliedOp) { + match op { + ImpliedOp::Nop => {} + ImpliedOp::Clc => self.registers.p.remove(CpuStatus::CARRY), + ImpliedOp::Cld => self.registers.p.remove(CpuStatus::DECIMAL), + ImpliedOp::Cli => self.registers.p.remove(CpuStatus::IRQ_DISABLE), + ImpliedOp::Clv => self.registers.p.remove(CpuStatus::OVERFLOW), + ImpliedOp::Sec => self.registers.p.insert(CpuStatus::CARRY), + ImpliedOp::Sed => self.registers.p.insert(CpuStatus::DECIMAL), + ImpliedOp::Sei => self.registers.p.insert(CpuStatus::IRQ_DISABLE), + ImpliedOp::IncA => { + if self.accumulator_is_8bit() { + let value = (self.registers.a as u8).wrapping_add(1); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(value); + self.update_nz8(value); + } else { + self.registers.a = self.registers.a.wrapping_add(1); + self.update_nz16(self.registers.a); + } + } + ImpliedOp::DecA => { + if self.accumulator_is_8bit() { + let value = (self.registers.a as u8).wrapping_sub(1); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(value); + self.update_nz8(value); + } else { + self.registers.a = self.registers.a.wrapping_sub(1); + self.update_nz16(self.registers.a); + } + } + ImpliedOp::Inx => { + if self.index_is_8bit() { + let value = (self.registers.x as u8).wrapping_add(1); + self.registers.x = u16::from(value); + self.update_nz8(value); + } else { + self.registers.x = self.registers.x.wrapping_add(1); + self.update_nz16(self.registers.x); + } + } + ImpliedOp::Iny => { + if self.index_is_8bit() { + let value = (self.registers.y as u8).wrapping_add(1); + self.registers.y = u16::from(value); + self.update_nz8(value); + } else { + self.registers.y = self.registers.y.wrapping_add(1); + self.update_nz16(self.registers.y); + } + } + ImpliedOp::Dex => { + if self.index_is_8bit() { + let value = (self.registers.x as u8).wrapping_sub(1); + self.registers.x = u16::from(value); + self.update_nz8(value); + } else { + self.registers.x = self.registers.x.wrapping_sub(1); + self.update_nz16(self.registers.x); + } + } + ImpliedOp::Dey => { + if self.index_is_8bit() { + let value = (self.registers.y as u8).wrapping_sub(1); + self.registers.y = u16::from(value); + self.update_nz8(value); + } else { + self.registers.y = self.registers.y.wrapping_sub(1); + self.update_nz16(self.registers.y); + } + } + ImpliedOp::AslAcc => self.shift_accumulator(ShiftOp::Asl), + ImpliedOp::RolAcc => self.shift_accumulator(ShiftOp::Rol), + ImpliedOp::RorAcc => self.shift_accumulator(ShiftOp::Ror), + ImpliedOp::LsrAcc => self.shift_accumulator(ShiftOp::Lsr), + ImpliedOp::Tax => self.load_x(self.registers.a), + ImpliedOp::Tay => self.load_y(self.registers.a), + ImpliedOp::Txa => self.load_accumulator(self.registers.x), + ImpliedOp::Tya => self.load_accumulator(self.registers.y), + ImpliedOp::Txy => self.load_y(self.registers.x), + ImpliedOp::Tyx => self.load_x(self.registers.y), + ImpliedOp::Tsx => self.load_x(self.registers.s), + ImpliedOp::Tcd => { + self.registers.d = self.registers.a; + self.update_nz16(self.registers.d); + } + ImpliedOp::Tdc => { + self.registers.a = self.registers.d; + self.update_nz16(self.registers.a); + } + ImpliedOp::Tsc => { + self.registers.a = self.registers.s; + self.update_nz16(self.registers.a); + } + ImpliedOp::Tcs => { + self.registers.s = self.registers.a; + if self.registers.e { + self.registers.s = (self.registers.s & 0x00FF) | 0x0100; + } + } + ImpliedOp::Xba => { + let low = self.registers.a as u8; + let high = (self.registers.a >> 8) as u8; + self.registers.a = (u16::from(low) << 8) | u16::from(high); + self.update_nz8(high); + } + ImpliedOp::Xce => self.execute_xce(), + ImpliedOp::Txs => { + if self.index_is_8bit() { + self.registers.s = (self.registers.s & 0xFF00) | (self.registers.x & 0x00FF); + } else { + self.registers.s = self.registers.x; + } + if self.registers.e { + self.registers.s = (self.registers.s & 0x00FF) | 0x0100; + } + } + ImpliedOp::Stp => { + self.micro_state = MicroState::Stopped; + self.current_state = CpuState::Stopped; + return; + } + ImpliedOp::Wai => { + self.micro_state = MicroState::WaitingForInterrupt; + return; + } + } + self.micro_state = MicroState::Fetch; + } + + fn execute_direct(&mut self, bus: &mut dyn CpuBus, op: DirectOp) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let base = self.registers.d.wrapping_add(u16::from(offset)); + + match op { + DirectOp::Adc { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::AdcA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AdcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::AdcIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::AdcA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AdcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Sbc { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::SbcA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::SbcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::SbcIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::SbcA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::SbcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::And { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::AndA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AndA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::AndIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::AndA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AndA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Ora { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::OraA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::OraA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::OraIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::OraA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::OraA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Eor { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::EorA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::EorA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::EorIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::EorA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::EorA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Inc { indexed_x, wide } => { + let address = if indexed_x { + self.direct_indexed_addr(offset, self.registers.x) + } else { + base + }; + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectIncHigh { address, low }; + } else { + let value = low.wrapping_add(1); + bus.write(u32::from(address), value); + self.update_nz8(value); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::CmpA { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::CmpA, + address: base, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::CmpA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::CmpAIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::CmpA, + address, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::CmpA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Bit { indexed_x, wide } => { + let address = if indexed_x { + self.direct_indexed_addr(offset, self.registers.x) + } else { + base + }; + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectBitHigh { address, low }; + } else { + self.apply_memory_bit(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Trb { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectTestModifyHigh { + op: TestModifyOp::Trb, + address: base, + low, + }; + } else { + let value = self.apply_test_modify8(TestModifyOp::Trb, low); + bus.write(u32::from(base), value); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Tsb { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectTestModifyHigh { + op: TestModifyOp::Tsb, + address: base, + low, + }; + } else { + let value = self.apply_test_modify8(TestModifyOp::Tsb, low); + bus.write(u32::from(base), value); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Shift { + op, + indexed_x, + wide, + } => { + let address = if indexed_x { + self.direct_indexed_addr(offset, self.registers.x) + } else { + base + }; + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectShiftHigh { op, address, low }; + } else { + let value = self.apply_shift8(op, low); + bus.write(u32::from(address), value); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Lda { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectReadHigh { address: base, low }; + } else { + self.registers.a = (self.registers.a & 0xFF00) | u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Sta { wide } => { + self.write_operand_value_zero_bank(bus, base, self.registers.a, wide); + } + DirectOp::StaIndexedX { wide } => { + self.write_operand_value_zero_bank( + bus, + self.direct_indexed_addr(offset, self.registers.x), + self.registers.a, + wide, + ); + } + DirectOp::Stx { wide } => { + self.write_operand_value_zero_bank(bus, base, self.registers.x, wide); + } + DirectOp::StxIndexedY { wide } => { + self.write_operand_value_zero_bank( + bus, + self.direct_indexed_addr(offset, self.registers.y), + self.registers.x, + wide, + ); + } + DirectOp::Dec { indexed_x, wide } => { + let address = if indexed_x { + self.direct_indexed_addr(offset, self.registers.x) + } else { + base + }; + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectDecHigh { address, low }; + } else { + let value = low.wrapping_sub(1); + bus.write(u32::from(address), value); + self.update_nz8(value); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Sty { wide } => { + self.write_operand_value_zero_bank(bus, base, self.registers.y, wide); + } + DirectOp::StyIndexedX { wide } => { + self.write_operand_value_zero_bank( + bus, + self.direct_indexed_addr(offset, self.registers.x), + self.registers.y, + wide, + ); + } + DirectOp::Stz { wide } => { + self.write_operand_value_zero_bank(bus, base, 0, wide); + } + DirectOp::StzIndexedX { wide } => { + self.write_operand_value_zero_bank( + bus, + self.direct_indexed_addr(offset, self.registers.x), + 0, + wide, + ); + } + DirectOp::LdaIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectReadHigh { address, low }; + } else { + self.registers.a = (self.registers.a & 0xFF00) | u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Ldx { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectReadXHigh { address: base, low }; + } else { + self.load_x(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::LdxIndexedY { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.y); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectReadXHigh { address, low }; + } else { + self.load_x(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Ldy { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectReadYHigh { address: base, low }; + } else { + self.load_y(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::LdyIndexedX { wide } => { + let address = self.direct_indexed_addr(offset, self.registers.x); + let low = bus.read(u32::from(address)); + if wide { + self.micro_state = MicroState::DirectReadYHigh { address, low }; + } else { + self.load_y(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Cpx { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::CmpX, + address: base, + low, + }; + } else { + self.compare_x(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + DirectOp::Cpy { wide } => { + let low = bus.read(u32::from(base)); + if wide { + self.micro_state = MicroState::DirectMathHigh { + op: ImmediateMathOp::CmpY, + address: base, + low, + }; + } else { + self.compare_y(u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + } + } + + fn execute_direct_indexed_indirect( + &mut self, + bus: &mut dyn CpuBus, + op: DirectIndexedIndirectOp, + ) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.direct_indexed_indirect_pointer_addr(offset); + let low = bus.read(u32::from(pointer_addr)); + self.micro_state = MicroState::DirectIndexedIndirectPointerHigh { + op, + pointer_addr, + low, + }; + } + + fn apply_direct_indexed_indirect(&mut self, op: DirectIndexedIndirectOp, value: u16) { + match op { + DirectIndexedIndirectOp::AdcA => { + self.apply_immediate_math(ImmediateMathOp::AdcA, value) + } + DirectIndexedIndirectOp::SbcA => { + self.apply_immediate_math(ImmediateMathOp::SbcA, value) + } + DirectIndexedIndirectOp::AndA => { + self.apply_immediate_math(ImmediateMathOp::AndA, value) + } + DirectIndexedIndirectOp::OraA => { + self.apply_immediate_math(ImmediateMathOp::OraA, value) + } + DirectIndexedIndirectOp::EorA => { + self.apply_immediate_math(ImmediateMathOp::EorA, value) + } + DirectIndexedIndirectOp::CmpA => { + self.apply_immediate_math(ImmediateMathOp::CmpA, value) + } + DirectIndexedIndirectOp::Lda => self.load_accumulator(value), + DirectIndexedIndirectOp::Sta => unreachable!("STA handled during address resolution"), + } + } + + fn execute_direct_indirect(&mut self, bus: &mut dyn CpuBus, op: DirectIndirectOp) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.registers.d.wrapping_add(u16::from(offset)); + let target = self.read_zero_bank_u16(bus, pointer_addr); + let full = self.full_data_address(target); + let extra_cycles = + (if self.accumulator_is_8bit() { 3 } else { 4 }) + self.direct_page_cycle_penalty(); + self.burn_internal_cycles(bus, extra_cycles); + if matches!(op, DirectIndirectOp::Sta) { + self.store_accumulator(bus, full); + } else { + let value = self.read_operand_value(bus, full, !self.accumulator_is_8bit()); + self.apply_direct_indirect(op, value); + self.micro_state = MicroState::Fetch; + } + } + + fn apply_direct_indirect(&mut self, op: DirectIndirectOp, value: u16) { + match op { + DirectIndirectOp::AdcA => self.apply_immediate_math(ImmediateMathOp::AdcA, value), + DirectIndirectOp::SbcA => self.apply_immediate_math(ImmediateMathOp::SbcA, value), + DirectIndirectOp::AndA => self.apply_immediate_math(ImmediateMathOp::AndA, value), + DirectIndirectOp::OraA => self.apply_immediate_math(ImmediateMathOp::OraA, value), + DirectIndirectOp::EorA => self.apply_immediate_math(ImmediateMathOp::EorA, value), + DirectIndirectOp::CmpA => self.apply_immediate_math(ImmediateMathOp::CmpA, value), + DirectIndirectOp::Lda => self.load_accumulator(value), + DirectIndirectOp::Sta => unreachable!("STA handled during address resolution"), + } + } + + fn execute_direct_indirect_long(&mut self, bus: &mut dyn CpuBus, op: DirectIndirectLongOp) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.registers.d.wrapping_add(u16::from(offset)); + let full = self.read_zero_bank_u24(bus, pointer_addr); + let extra_cycles = + (if self.accumulator_is_8bit() { 4 } else { 5 }) + self.direct_page_cycle_penalty(); + self.burn_internal_cycles(bus, extra_cycles); + if matches!(op, DirectIndirectLongOp::Sta) { + self.store_accumulator(bus, full); + } else { + let value = self.read_operand_value(bus, full, !self.accumulator_is_8bit()); + self.apply_direct_indirect_long(op, value); + self.micro_state = MicroState::Fetch; + } + } + + fn apply_direct_indirect_long(&mut self, op: DirectIndirectLongOp, value: u16) { + match op { + DirectIndirectLongOp::AdcA => self.apply_immediate_math(ImmediateMathOp::AdcA, value), + DirectIndirectLongOp::SbcA => self.apply_immediate_math(ImmediateMathOp::SbcA, value), + DirectIndirectLongOp::AndA => self.apply_immediate_math(ImmediateMathOp::AndA, value), + DirectIndirectLongOp::OraA => self.apply_immediate_math(ImmediateMathOp::OraA, value), + DirectIndirectLongOp::EorA => self.apply_immediate_math(ImmediateMathOp::EorA, value), + DirectIndirectLongOp::CmpA => self.apply_immediate_math(ImmediateMathOp::CmpA, value), + DirectIndirectLongOp::Lda => self.load_accumulator(value), + DirectIndirectLongOp::Sta => unreachable!("STA handled during address resolution"), + } + } + + fn execute_direct_indirect_indexed_y( + &mut self, + bus: &mut dyn CpuBus, + op: DirectIndirectIndexedYOp, + ) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.registers.d.wrapping_add(u16::from(offset)); + let (full, extra_cycles) = match op { + DirectIndirectIndexedYOp::AdcA + | DirectIndirectIndexedYOp::AndA + | DirectIndirectIndexedYOp::OraA + | DirectIndirectIndexedYOp::EorA + | DirectIndirectIndexedYOp::SbcA + | DirectIndirectIndexedYOp::CmpA + | DirectIndirectIndexedYOp::Lda + | DirectIndirectIndexedYOp::Sta => { + let target = self.read_zero_bank_u16(bus, pointer_addr); + ( + self.full_data_address(target) + .wrapping_add(u32::from(self.registers.y)), + (if self.accumulator_is_8bit() { 3 } else { 4 }) + + self.direct_page_cycle_penalty() + + self.direct_indirect_indexed_y_cycle_penalty(target), + ) + } + DirectIndirectIndexedYOp::AdcALong + | DirectIndirectIndexedYOp::AndALong + | DirectIndirectIndexedYOp::OraALong + | DirectIndirectIndexedYOp::EorALong + | DirectIndirectIndexedYOp::SbcALong + | DirectIndirectIndexedYOp::CmpALong + | DirectIndirectIndexedYOp::LdaLong + | DirectIndirectIndexedYOp::StaLong => ( + self.read_zero_bank_u24(bus, pointer_addr) + .wrapping_add(u32::from(self.registers.y)), + (if self.accumulator_is_8bit() { 4 } else { 5 }) + self.direct_page_cycle_penalty(), + ), + }; + self.burn_internal_cycles(bus, extra_cycles); + if matches!( + op, + DirectIndirectIndexedYOp::Sta | DirectIndirectIndexedYOp::StaLong + ) { + self.store_accumulator(bus, full); + } else { + let value = self.read_operand_value(bus, full, !self.accumulator_is_8bit()); + self.apply_direct_indirect_indexed_y(op, value); + self.micro_state = MicroState::Fetch; + } + } + + fn apply_direct_indirect_indexed_y(&mut self, op: DirectIndirectIndexedYOp, value: u16) { + match op { + DirectIndirectIndexedYOp::AdcA + | DirectIndirectIndexedYOp::AdcALong + | DirectIndirectIndexedYOp::SbcA + | DirectIndirectIndexedYOp::SbcALong + | DirectIndirectIndexedYOp::AndA + | DirectIndirectIndexedYOp::AndALong + | DirectIndirectIndexedYOp::OraA + | DirectIndirectIndexedYOp::OraALong + | DirectIndirectIndexedYOp::EorA + | DirectIndirectIndexedYOp::EorALong + | DirectIndirectIndexedYOp::CmpA + | DirectIndirectIndexedYOp::CmpALong => { + let math_op = match op { + DirectIndirectIndexedYOp::AdcA | DirectIndirectIndexedYOp::AdcALong => { + ImmediateMathOp::AdcA + } + DirectIndirectIndexedYOp::SbcA | DirectIndirectIndexedYOp::SbcALong => { + ImmediateMathOp::SbcA + } + DirectIndirectIndexedYOp::AndA | DirectIndirectIndexedYOp::AndALong => { + ImmediateMathOp::AndA + } + DirectIndirectIndexedYOp::OraA | DirectIndirectIndexedYOp::OraALong => { + ImmediateMathOp::OraA + } + DirectIndirectIndexedYOp::EorA | DirectIndirectIndexedYOp::EorALong => { + ImmediateMathOp::EorA + } + DirectIndirectIndexedYOp::CmpA | DirectIndirectIndexedYOp::CmpALong => { + ImmediateMathOp::CmpA + } + DirectIndirectIndexedYOp::Lda | DirectIndirectIndexedYOp::LdaLong => { + unreachable!("LDA handled below") + } + DirectIndirectIndexedYOp::Sta | DirectIndirectIndexedYOp::StaLong => { + unreachable!("STA handled during address resolution") + } + }; + self.apply_immediate_math(math_op, value) + } + DirectIndirectIndexedYOp::Lda | DirectIndirectIndexedYOp::LdaLong => { + self.load_accumulator(value) + } + DirectIndirectIndexedYOp::Sta | DirectIndirectIndexedYOp::StaLong => { + unreachable!("STA handled during address resolution") + } + } + } + + fn apply_stack_relative(&mut self, op: StackRelativeOp, value: u16) { + match op { + StackRelativeOp::AdcA => self.apply_immediate_math(ImmediateMathOp::AdcA, value), + StackRelativeOp::SbcA => self.apply_immediate_math(ImmediateMathOp::SbcA, value), + StackRelativeOp::AndA => self.apply_immediate_math(ImmediateMathOp::AndA, value), + StackRelativeOp::OraA => self.apply_immediate_math(ImmediateMathOp::OraA, value), + StackRelativeOp::EorA => self.apply_immediate_math(ImmediateMathOp::EorA, value), + StackRelativeOp::CmpA => self.apply_immediate_math(ImmediateMathOp::CmpA, value), + StackRelativeOp::Lda => self.load_accumulator(value), + StackRelativeOp::Sta => unreachable!("STA handled in execute_stack_relative"), + } + } + + fn apply_stack_relative_indirect_indexed_y( + &mut self, + op: StackRelativeIndirectIndexedYOp, + value: u16, + ) { + match op { + StackRelativeIndirectIndexedYOp::AdcA => { + self.apply_immediate_math(ImmediateMathOp::AdcA, value) + } + StackRelativeIndirectIndexedYOp::SbcA => { + self.apply_immediate_math(ImmediateMathOp::SbcA, value) + } + StackRelativeIndirectIndexedYOp::AndA => { + self.apply_immediate_math(ImmediateMathOp::AndA, value) + } + StackRelativeIndirectIndexedYOp::OraA => { + self.apply_immediate_math(ImmediateMathOp::OraA, value) + } + StackRelativeIndirectIndexedYOp::EorA => { + self.apply_immediate_math(ImmediateMathOp::EorA, value) + } + StackRelativeIndirectIndexedYOp::CmpA => { + self.apply_immediate_math(ImmediateMathOp::CmpA, value) + } + StackRelativeIndirectIndexedYOp::Lda => self.load_accumulator(value), + StackRelativeIndirectIndexedYOp::Sta => { + unreachable!("STA handled during address resolution") + } + } + } + + fn execute_stack_relative(&mut self, bus: &mut dyn CpuBus, op: StackRelativeOp) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let address = self.registers.s.wrapping_add(u16::from(offset)); + if matches!(op, StackRelativeOp::Sta) { + self.write_operand_value_zero_bank( + bus, + address, + self.registers.a, + !self.accumulator_is_8bit(), + ); + } else { + let low = bus.read(u32::from(address)); + if self.accumulator_is_8bit() { + self.apply_stack_relative(op, u16::from(low)); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::StackRelativeReadHigh { op, address, low }; + } + } + } + + fn execute_stack_relative_indirect_indexed_y( + &mut self, + bus: &mut dyn CpuBus, + op: StackRelativeIndirectIndexedYOp, + ) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.registers.s.wrapping_add(u16::from(offset)); + let target = self.read_zero_bank_u16(bus, pointer_addr); + let full = self + .full_data_address(target) + .wrapping_add(u32::from(self.registers.y)); + self.burn_internal_cycles(bus, if self.accumulator_is_8bit() { 5 } else { 6 }); + if matches!(op, StackRelativeIndirectIndexedYOp::Sta) { + self.store_accumulator(bus, full); + } else { + let value = self.read_operand_value(bus, full, !self.accumulator_is_8bit()); + self.apply_stack_relative_indirect_indexed_y(op, value); + self.micro_state = MicroState::Fetch; + } + } + + fn execute_branch(&mut self, bus: &mut dyn CpuBus, kind: BranchKind) { + let offset = bus.read(self.full_pc()) as i8; + self.registers.pc = self.registers.pc.wrapping_add(1); + if self.branch_taken(kind) { + self.registers.pc = self.registers.pc.wrapping_add_signed(i16::from(offset)); + } + self.micro_state = MicroState::Fetch; + } + + fn execute_exception(&mut self, kind: ExceptionKind) { + // BRK and COP have an implicit operand byte; the opcode fetch already + // advanced PC past the opcode itself, so we add +1 to also skip the + // operand byte. NMI has no operand; the return address is the PC as-is. + if kind.increments_pc() { + self.registers.pc = self.registers.pc.wrapping_add(1); + } + let return_addr = self.registers.pc; + if self.registers.e { + self.micro_state = MicroState::ExceptionPushHigh { kind, return_addr }; + } else { + self.micro_state = MicroState::ExceptionPushBank { kind, return_addr }; + } + } + + fn start_nmi_sequence(&mut self) { + let return_addr = self.registers.pc; + if self.registers.e { + self.micro_state = MicroState::ExceptionPushHigh { + kind: ExceptionKind::Nmi, + return_addr, + }; + } else { + self.micro_state = MicroState::ExceptionPushBank { + kind: ExceptionKind::Nmi, + return_addr, + }; + } + } + + fn start_irq_sequence(&mut self) { + let return_addr = self.registers.pc; + if self.registers.e { + self.micro_state = MicroState::ExceptionPushHigh { + kind: ExceptionKind::Irq, + return_addr, + }; + } else { + self.micro_state = MicroState::ExceptionPushBank { + kind: ExceptionKind::Irq, + return_addr, + }; + } + } + + fn execute_branch_long_low(&mut self, bus: &mut dyn CpuBus) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::BranchLongHigh(low); + } + + fn execute_branch_long_high(&mut self, bus: &mut dyn CpuBus, low: u8) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let offset = i16::from_le_bytes([low, high]); + self.registers.pc = self.registers.pc.wrapping_add_signed(offset); + self.micro_state = MicroState::Fetch; + } + + /// Idle cycle for WAI: burn a cycle and poll for a pending interrupt. + /// A masked IRQ still wakes the CPU, but execution resumes at the next + /// instruction until software clears I and takes the still-asserted source. + fn execute_wai(&mut self, bus: &mut dyn CpuBus) { + if bus.poll_nmi() { + self.start_nmi_sequence(); + } else if bus.poll_irq() { + if self.registers.p.contains(CpuStatus::IRQ_DISABLE) { + self.micro_state = MicroState::Fetch; + } else { + self.start_irq_sequence(); + } + } + // If no interrupt is pending, WaitingForInterrupt remains set; the CPU + // simply burns another cycle on the next step. + } + + fn execute_immediate8(&mut self, bus: &mut dyn CpuBus, op: Immediate8Op) { + let value = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + match op { + Immediate8Op::Rep => self.apply_status_mask(value, false), + Immediate8Op::Sep => self.apply_status_mask(value, true), + Immediate8Op::Wdm => {} + } + self.micro_state = MicroState::Fetch; + } + + fn execute_immediate16_low(&mut self, bus: &mut dyn CpuBus, op: Immediate16Op) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::Immediate16High(op, low); + } + + fn execute_immediate16_high(&mut self, bus: &mut dyn CpuBus, op: Immediate16Op, low: u8) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let value = match op { + Immediate16Op::Pea => u16::from_le_bytes([low, high]), + Immediate16Op::Per => { + let offset = i16::from_le_bytes([low, high]); + self.registers.pc.wrapping_add_signed(offset) + } + }; + let stack_addr = self.stack_push_raw(bus, self.registers.s, (value >> 8) as u8); + self.micro_state = MicroState::PushLowRaw { + low: value as u8, + stack_addr, + }; + } + + fn execute_pei_pointer_low(&mut self, bus: &mut dyn CpuBus) { + let offset = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let pointer_addr = self.registers.d.wrapping_add(u16::from(offset)); + let low = bus.read(u32::from(pointer_addr)); + self.micro_state = MicroState::PeiPointerHigh { pointer_addr, low }; + } + + fn execute_immediate_load_low(&mut self, bus: &mut dyn CpuBus, target: ImmediateLoadTarget) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + if self.load_width(target) == 1 { + self.apply_immediate_load(target, u16::from(low)); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::ImmediateLoadHigh(target, low); + } + } + + fn execute_immediate_load_high( + &mut self, + bus: &mut dyn CpuBus, + target: ImmediateLoadTarget, + low: u8, + ) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.apply_immediate_load(target, u16::from_le_bytes([low, high])); + self.micro_state = MicroState::Fetch; + } + + fn execute_immediate_math_low(&mut self, bus: &mut dyn CpuBus, op: ImmediateMathOp) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + if self.immediate_math_width(op) == 1 { + self.apply_immediate_math(op, u16::from(low)); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::ImmediateMathHigh(op, low); + } + } + + fn execute_immediate_math_high(&mut self, bus: &mut dyn CpuBus, op: ImmediateMathOp, low: u8) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.apply_immediate_math(op, u16::from_le_bytes([low, high])); + self.micro_state = MicroState::Fetch; + } + + fn execute_block_move_first_bank( + &mut self, + bus: &mut dyn CpuBus, + direction: BlockMoveDirection, + ) { + let first_bank = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::BlockMoveSecondBank(direction, first_bank); + } + + fn execute_block_move_second_bank( + &mut self, + bus: &mut dyn CpuBus, + direction: BlockMoveDirection, + dest_bank: u8, + ) { + let source_bank = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::BlockMoveTransfer { + direction, + source_bank, + dest_bank, + }; + } + + fn execute_block_move_transfer( + &mut self, + bus: &mut dyn CpuBus, + direction: BlockMoveDirection, + source_bank: u8, + dest_bank: u8, + ) { + let source = ((source_bank as u32) << 16) | u32::from(self.registers.x); + let dest = ((dest_bank as u32) << 16) | u32::from(self.registers.y); + let value = bus.read(source); + bus.write(dest, value); + self.registers.db = dest_bank; + self.registers.a = self.registers.a.wrapping_sub(1); + self.adjust_block_move_indexes(direction); + self.burn_internal_cycles(bus, 6); + self.micro_state = if self.registers.a == 0xFFFF { + MicroState::Fetch + } else { + MicroState::BlockMoveTransfer { + direction, + source_bank, + dest_bank, + } + }; + } + + fn execute_stack(&mut self, bus: &mut dyn CpuBus, op: StackOp) { + match op { + StackOp::Pha => { + if self.accumulator_is_8bit() { + self.stack_push(bus, self.registers.a as u8); + self.micro_state = MicroState::Fetch; + } else { + self.stack_push(bus, (self.registers.a >> 8) as u8); + self.micro_state = MicroState::PushLow(self.registers.a as u8); + } + } + StackOp::Pla => { + let low = self.stack_pop(bus); + if self.accumulator_is_8bit() { + self.registers.a = (self.registers.a & 0xFF00) | u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::PullAccumulatorHigh(low); + } + } + StackOp::Php => { + self.stack_push(bus, self.registers.p.bits()); + self.micro_state = MicroState::Fetch; + } + StackOp::Plp => { + let value = self.stack_pop(bus); + self.set_status(value); + self.micro_state = MicroState::Fetch; + } + StackOp::Phx => { + if self.index_is_8bit() { + self.stack_push(bus, self.registers.x as u8); + self.micro_state = MicroState::Fetch; + } else { + self.stack_push(bus, (self.registers.x >> 8) as u8); + self.micro_state = MicroState::PushLow(self.registers.x as u8); + } + } + StackOp::Phy => { + if self.index_is_8bit() { + self.stack_push(bus, self.registers.y as u8); + self.micro_state = MicroState::Fetch; + } else { + self.stack_push(bus, (self.registers.y >> 8) as u8); + self.micro_state = MicroState::PushLow(self.registers.y as u8); + } + } + StackOp::Phb => { + self.stack_push(bus, self.registers.db); + self.micro_state = MicroState::Fetch; + } + StackOp::Phk => { + self.stack_push(bus, self.registers.pb); + self.micro_state = MicroState::Fetch; + } + StackOp::Phd => { + let stack_addr = + self.stack_push_raw(bus, self.registers.s, (self.registers.d >> 8) as u8); + self.micro_state = MicroState::PushLowRaw { + low: self.registers.d as u8, + stack_addr, + }; + } + StackOp::Plx => { + let low = self.stack_pop(bus); + if self.index_is_8bit() { + self.registers.x = u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::PullXHigh(low); + } + } + StackOp::Ply => { + let low = self.stack_pop(bus); + if self.index_is_8bit() { + self.registers.y = u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } else { + self.micro_state = MicroState::PullYHigh(low); + } + } + StackOp::Plb => { + let (stack_addr, value) = self.stack_pop_raw(bus, self.registers.s); + self.registers.s = self.normalize_stack_pointer(stack_addr); + self.registers.db = value; + self.update_nz8(value); + self.micro_state = MicroState::Fetch; + } + StackOp::Pld => { + let (stack_addr, low) = self.stack_pop_raw(bus, self.registers.s); + self.micro_state = MicroState::PullDHighRaw { low, stack_addr }; + } + } + } + + fn execute_absolute_low(&mut self, bus: &mut dyn CpuBus, op: AbsoluteOp) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::AbsoluteHigh(op, low); + } + + fn execute_absolute_high(&mut self, bus: &mut dyn CpuBus, op: AbsoluteOp, low: u8) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let address = u16::from_le_bytes([low, high]); + + match op { + AbsoluteOp::Adc { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AdcA, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AdcA, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::AdcIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AdcA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AdcA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + }; + } + } + AbsoluteOp::AdcIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AdcA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AdcA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + }; + } + } + AbsoluteOp::Sbc { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::SbcA, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::SbcA, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::SbcIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::SbcA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::SbcA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + }; + } + } + AbsoluteOp::SbcIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::SbcA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::SbcA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + }; + } + } + AbsoluteOp::And { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AndA, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AndA, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::AndIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AndA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AndA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + }; + } + } + AbsoluteOp::AndIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::AndA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::AndA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + }; + } + } + AbsoluteOp::Ora { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::OraA, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::OraA, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::OraIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::OraA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::OraA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + }; + } + } + AbsoluteOp::OraIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::OraA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::OraA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + }; + } + } + AbsoluteOp::Eor { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::EorA, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::EorA, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::EorIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::EorA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::EorA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + }; + } + } + AbsoluteOp::EorIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::EorA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::EorA, + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + }; + } + } + AbsoluteOp::Inc { indexed_x, wide } => { + let full = if indexed_x { + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)) + } else { + self.full_data_address(address) + }; + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteIncHigh { + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteRmwRead { + op: RmwOp::Inc, + address: full, + }; + } + } + AbsoluteOp::CmpA { wide } => { + let full = self.full_data_address(address); + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::CmpA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::CmpA, + address: full, + }; + } + } + AbsoluteOp::CmpAIndexedX { wide } => { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::CmpA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::CmpA, + address: full, + }; + } + } + AbsoluteOp::CmpAIndexedY { wide } => { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::CmpA, + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::CmpA, + address: full, + }; + } + } + AbsoluteOp::Dec { indexed_x, wide } => { + let full = if indexed_x { + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)) + } else { + self.full_data_address(address) + }; + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteDecHigh { + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteRmwRead { + op: RmwOp::Dec, + address: full, + }; + } + } + AbsoluteOp::Cpx { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::CmpX, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::CmpX, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::Cpy { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteMathHigh { + op: ImmediateMathOp::CmpY, + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteMathData { + op: ImmediateMathOp::CmpY, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::Ldx { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteReadXHigh { + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::X, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::LdxIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteReadXHigh { + address: full, + low: value, + }; + } else { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::X, + address: full, + }; + } + } + AbsoluteOp::Ldy { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteReadYHigh { + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::Y, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::LdyIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteReadYHigh { + address: full, + low: value, + }; + } else { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::Y, + address: full, + }; + } + } + AbsoluteOp::Lda { wide } => { + if wide { + let value = self.read_data_bank(bus, address); + self.micro_state = MicroState::AbsoluteReadAccumulatorHigh { + address: self.full_data_address(address), + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::A, + address: self.full_data_address(address), + }; + } + } + AbsoluteOp::LdaIndexedX { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteReadAccumulatorHigh { + address: full, + low: value, + }; + } else { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)); + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::A, + address: full, + }; + } + } + AbsoluteOp::LdaIndexedY { wide } => { + if wide { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteReadAccumulatorHigh { + address: full, + low: value, + }; + } else { + let full = self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)); + self.micro_state = MicroState::AbsoluteReadData { + target: ImmediateLoadTarget::A, + address: full, + }; + } + } + AbsoluteOp::Sta { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address), + self.registers.a, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self.full_data_address(address), + value: self.registers.a as u8, + }; + } + } + AbsoluteOp::StaIndexedX { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + self.registers.a, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + value: self.registers.a as u8, + }; + } + } + AbsoluteOp::StaIndexedY { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + self.registers.a, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.y)), + value: self.registers.a as u8, + }; + } + } + AbsoluteOp::Stx { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address), + self.registers.x, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self.full_data_address(address), + value: self.registers.x as u8, + }; + } + } + AbsoluteOp::Sty { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address), + self.registers.y, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self.full_data_address(address), + value: self.registers.y as u8, + }; + } + } + AbsoluteOp::Stz { wide } => { + if wide { + self.write_operand_value(bus, self.full_data_address(address), 0, true); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self.full_data_address(address), + value: 0, + }; + } + } + AbsoluteOp::StzIndexedX { wide } => { + if wide { + self.write_operand_value( + bus, + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + 0, + true, + ); + } else { + self.micro_state = MicroState::AbsoluteStoreData { + address: self + .full_data_address(address) + .wrapping_add(u32::from(self.registers.x)), + value: 0, + }; + } + } + AbsoluteOp::Bit { indexed_x, wide } => { + let full = if indexed_x { + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)) + } else { + self.full_data_address(address) + }; + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteBitHigh { + address: full, + low: value, + }; + } else { + self.micro_state = MicroState::AbsoluteBitData { address: full }; + } + } + AbsoluteOp::Trb { wide } | AbsoluteOp::Tsb { wide } => { + let full = self.full_data_address(address); + if wide { + let value = bus.read(full); + let test_op = if matches!(op, AbsoluteOp::Trb { .. }) { + TestModifyOp::Trb + } else { + TestModifyOp::Tsb + }; + self.micro_state = MicroState::AbsoluteTestModifyHigh { + op: test_op, + address: full, + low: value, + }; + } else { + let rmw_op = if matches!(op, AbsoluteOp::Trb { .. }) { + RmwOp::Trb + } else { + RmwOp::Tsb + }; + self.micro_state = MicroState::AbsoluteRmwRead { + op: rmw_op, + address: full, + }; + } + } + AbsoluteOp::Shift { + op: shift_op, + indexed_x, + wide, + } => { + let full = if indexed_x { + self.full_data_address(address) + .wrapping_add(u32::from(self.registers.x)) + } else { + self.full_data_address(address) + }; + if wide { + let value = bus.read(full); + self.micro_state = MicroState::AbsoluteShiftHigh { + op: shift_op, + address: full, + low: value, + }; + } else { + let rmw_op = match shift_op { + ShiftOp::Asl => RmwOp::Asl, + ShiftOp::Lsr => RmwOp::Lsr, + ShiftOp::Rol => RmwOp::Rol, + ShiftOp::Ror => RmwOp::Ror, + }; + self.micro_state = MicroState::AbsoluteRmwRead { + op: rmw_op, + address: full, + }; + } + } + AbsoluteOp::Jmp => { + self.registers.pc = address; + self.micro_state = MicroState::Fetch; + } + AbsoluteOp::JmpIndirect => { + self.registers.pc = self.read_zero_bank_u16(bus, address); + self.micro_state = MicroState::Fetch; + } + AbsoluteOp::JmpIndexedXIndirect => { + let pointer = address.wrapping_add(self.registers.x); + self.registers.pc = self.read_program_bank_u16(bus, pointer); + self.micro_state = MicroState::Fetch; + } + AbsoluteOp::JmlIndirect => { + let full = self.read_zero_bank_u24(bus, address); + self.registers.pb = (full >> 16) as u8; + self.registers.pc = full as u16; + self.micro_state = MicroState::Fetch; + } + AbsoluteOp::Jsr => { + let return_addr = self.registers.pc.wrapping_sub(1); + self.micro_state = MicroState::JsrPushHigh { + target: address, + return_addr, + stack_addr: None, + }; + } + AbsoluteOp::JsrIndexedXIndirect => { + let return_addr = self.registers.pc.wrapping_sub(1); + let target = + self.read_program_bank_u16(bus, address.wrapping_add(self.registers.x)); + self.micro_state = MicroState::JsrPushHigh { + target, + return_addr, + stack_addr: Some(self.registers.s), + }; + } + } + } + + fn execute_absolute_long_low(&mut self, bus: &mut dyn CpuBus, op: AbsoluteLongOp) { + let low = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::AbsoluteLongHigh(op, low); + } + + fn execute_absolute_long_high(&mut self, bus: &mut dyn CpuBus, op: AbsoluteLongOp, low: u8) { + let high = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + self.micro_state = MicroState::AbsoluteLongBank(op, u16::from_le_bytes([low, high])); + } + + fn execute_absolute_long_bank( + &mut self, + bus: &mut dyn CpuBus, + op: AbsoluteLongOp, + address: u16, + ) { + let bank = bus.read(self.full_pc()); + self.registers.pc = self.registers.pc.wrapping_add(1); + let full = ((bank as u32) << 16) | u32::from(address); + + match op { + AbsoluteLongOp::Adc { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::AdcA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AdcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::AdcIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::AdcA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AdcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::Sbc { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::SbcA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::SbcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::SbcIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::SbcA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::SbcA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::And { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::AndA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AndA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::AndIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::AndA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::AndA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::Ora { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::OraA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::OraA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::OraIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::OraA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::OraA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::Eor { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::EorA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::EorA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::EorIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::EorA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::EorA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::CmpA { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::CmpA, + address: full, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::CmpA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::CmpAIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongMathHigh { + op: ImmediateMathOp::CmpA, + address: indexed, + low, + }; + } else { + self.apply_immediate_math(ImmediateMathOp::CmpA, u16::from(low)); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::Lda { wide } => { + let low = bus.read(full); + if wide { + self.micro_state = + MicroState::AbsoluteLongReadAccumulatorHigh { address: full, low }; + } else { + self.registers.a = (self.registers.a & 0xFF00) | u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::LdaIndexedX { wide } => { + let indexed = full.wrapping_add(u32::from(self.registers.x)); + let low = bus.read(indexed); + if wide { + self.micro_state = MicroState::AbsoluteLongReadAccumulatorHigh { + address: indexed, + low, + }; + } else { + self.registers.a = (self.registers.a & 0xFF00) | u16::from(low); + self.update_nz8(low); + self.micro_state = MicroState::Fetch; + } + } + AbsoluteLongOp::Sta { wide } => { + self.write_operand_value(bus, full, self.registers.a, wide); + } + AbsoluteLongOp::StaIndexedX { wide } => { + self.write_operand_value( + bus, + full.wrapping_add(u32::from(self.registers.x)), + self.registers.a, + wide, + ); + } + AbsoluteLongOp::Jml => { + self.registers.pb = bank; + self.registers.pc = address; + self.micro_state = MicroState::Fetch; + } + AbsoluteLongOp::Jsl => { + let return_addr = self.registers.pc.wrapping_sub(1); + self.micro_state = MicroState::JslPushBank { + target_bank: bank, + target_addr: address, + return_addr, + stack_addr: self.registers.s, + }; + } + } + } + + fn execute_xce(&mut self) { + let carry = self.registers.p.contains(CpuStatus::CARRY); + let old_emulation = self.registers.e; + + if old_emulation { + self.registers.p.insert(CpuStatus::CARRY); + } else { + self.registers.p.remove(CpuStatus::CARRY); + } + + self.registers.e = carry; + if self.registers.e { + self.registers + .p + .insert(CpuStatus::ACCUMULATOR_8BIT | CpuStatus::INDEX_8BIT); + self.registers.x &= 0x00FF; + self.registers.y &= 0x00FF; + self.registers.s = (self.registers.s & 0x00FF) | 0x0100; + } + } + + fn apply_status_mask(&mut self, value: u8, set: bool) { + let mask = CpuStatus::from_bits_truncate(value); + if set { + self.registers.p.insert(mask); + } else { + self.registers.p.remove(mask); + } + + self.normalize_status_after_mode_change(); + } + + fn set_status(&mut self, value: u8) { + self.registers.p = CpuStatus::from_bits_truncate(value); + self.normalize_status_after_mode_change(); + } + + fn normalize_status_after_mode_change(&mut self) { + if self.registers.e { + self.registers + .p + .insert(CpuStatus::ACCUMULATOR_8BIT | CpuStatus::INDEX_8BIT); + } + + if self.index_is_8bit() { + self.registers.x &= 0x00FF; + self.registers.y &= 0x00FF; + } + } + + fn apply_immediate_load(&mut self, target: ImmediateLoadTarget, value: u16) { + match target { + ImmediateLoadTarget::A => { + if self.accumulator_is_8bit() { + let value = value as u8; + self.registers.a = (self.registers.a & 0xFF00) | u16::from(value); + self.update_nz8(value); + } else { + self.registers.a = value; + self.update_nz16(value); + } + } + ImmediateLoadTarget::X => { + if self.index_is_8bit() { + let value = value as u8; + self.registers.x = u16::from(value); + self.update_nz8(value); + } else { + self.registers.x = value; + self.update_nz16(value); + } + } + ImmediateLoadTarget::Y => { + if self.index_is_8bit() { + let value = value as u8; + self.registers.y = u16::from(value); + self.update_nz8(value); + } else { + self.registers.y = value; + self.update_nz16(value); + } + } + } + } + + fn load_accumulator(&mut self, value: u16) { + if self.accumulator_is_8bit() { + let value = value as u8; + self.registers.a = (self.registers.a & 0xFF00) | u16::from(value); + self.update_nz8(value); + } else { + self.registers.a = value; + self.update_nz16(value); + } + } + + fn load_x(&mut self, value: u16) { + if self.index_is_8bit() { + let value = value as u8; + self.registers.x = u16::from(value); + self.update_nz8(value); + } else { + self.registers.x = value; + self.update_nz16(value); + } + } + + fn load_y(&mut self, value: u16) { + if self.index_is_8bit() { + let value = value as u8; + self.registers.y = u16::from(value); + self.update_nz8(value); + } else { + self.registers.y = value; + self.update_nz16(value); + } + } + + fn page_wrapped_next(address: u16) -> u16 { + (address & 0xFF00) | u16::from((address as u8).wrapping_add(1)) + } + + fn direct_indexed_addr(&self, offset: u8, index: u16) -> u16 { + if self.registers.e && (self.registers.d & 0x00FF) == 0 { + (self.registers.d & 0xFF00) | u16::from(offset.wrapping_add(index as u8)) + } else { + self.registers + .d + .wrapping_add(u16::from(offset)) + .wrapping_add(index) + } + } + + fn direct_indexed_indirect_pointer_addr(&self, offset: u8) -> u16 { + self.direct_indexed_addr(offset, self.registers.x) + } + + fn adc_decimal8(a: u8, operand: u8, carry_in: bool) -> (u8, bool, bool) { + let carry_in = i16::from(carry_in); + let mut low = i16::from(a & 0x0F) + i16::from(operand & 0x0F) + carry_in; + if low >= 0x0A { + low = ((low + 0x06) & 0x0F) + 0x10; + } + + let mut result = i16::from(a & 0xF0) + i16::from(operand & 0xF0) + low; + if result >= 0xA0 { + result += 0x60; + } + + let signed_result = i16::from((a & 0xF0) as i8) + i16::from((operand & 0xF0) as i8) + low; + + ( + result as u8, + result >= 0x100, + !(-128..=127).contains(&signed_result), + ) + } + + fn adc_decimal16(a: u16, operand: u16, carry_in: bool) -> (u16, bool, bool) { + let (low, carry, _) = Self::adc_decimal8(a as u8, operand as u8, carry_in); + let (high, carry, overflow) = + Self::adc_decimal8((a >> 8) as u8, (operand >> 8) as u8, carry); + ((u16::from(high) << 8) | u16::from(low), carry, overflow) + } + + fn sbc_decimal8(a: u8, operand: u8, carry_in: bool) -> (u8, bool, bool) { + let carry_in_u8 = u8::from(carry_in); + let inverted = !operand; + let (sum1, carry1) = a.overflowing_add(inverted); + let (binary_result, carry2) = sum1.overflowing_add(carry_in_u8); + + let mut low = i16::from(a & 0x0F) - i16::from(operand & 0x0F) + i16::from(carry_in_u8) - 1; + if low < 0 { + low = ((low - 0x06) & 0x0F) - 0x10; + } + + let mut result = i16::from(a & 0xF0) - i16::from(operand & 0xF0) + low; + if result < 0 { + result -= 0x60; + } + + ( + result as u8, + carry1 || carry2, + ((!(a ^ inverted) & (a ^ binary_result)) & 0x80) != 0, + ) + } + + fn sbc_decimal16(a: u16, operand: u16, carry_in: bool) -> (u16, bool, bool) { + let (low, carry, _) = Self::sbc_decimal8(a as u8, operand as u8, carry_in); + let (high, carry, overflow) = + Self::sbc_decimal8((a >> 8) as u8, (operand >> 8) as u8, carry); + ((u16::from(high) << 8) | u16::from(low), carry, overflow) + } + + fn apply_immediate_math(&mut self, op: ImmediateMathOp, value: u16) { + match op { + ImmediateMathOp::BitA => { + if self.accumulator_is_8bit() { + self.registers.p.set( + CpuStatus::ZERO, + (self.registers.a as u8) & (value as u8) == 0, + ); + } else { + self.registers + .p + .set(CpuStatus::ZERO, self.registers.a & value == 0); + } + } + ImmediateMathOp::AndA => { + if self.accumulator_is_8bit() { + let result = (self.registers.a as u8) & (value as u8); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(result); + self.update_nz8(result); + } else { + self.registers.a &= value; + self.update_nz16(self.registers.a); + } + } + ImmediateMathOp::OraA => { + if self.accumulator_is_8bit() { + let result = (self.registers.a as u8) | (value as u8); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(result); + self.update_nz8(result); + } else { + self.registers.a |= value; + self.update_nz16(self.registers.a); + } + } + ImmediateMathOp::EorA => { + if self.accumulator_is_8bit() { + let result = (self.registers.a as u8) ^ (value as u8); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(result); + self.update_nz8(result); + } else { + self.registers.a ^= value; + self.update_nz16(self.registers.a); + } + } + ImmediateMathOp::AdcA => { + if self.accumulator_is_8bit() { + let a = self.registers.a as u8; + let operand = value as u8; + let carry_in = self.registers.p.contains(CpuStatus::CARRY); + let (result, carry, overflow) = if self.registers.p.contains(CpuStatus::DECIMAL) + { + Self::adc_decimal8(a, operand, carry_in) + } else { + let carry_in = u8::from(carry_in); + let (sum1, carry1) = a.overflowing_add(operand); + let (result, carry2) = sum1.overflowing_add(carry_in); + ( + result, + carry1 || carry2, + ((!(a ^ operand) & (a ^ result)) & 0x80) != 0, + ) + }; + self.registers.a = (self.registers.a & 0xFF00) | u16::from(result); + self.registers.p.set(CpuStatus::CARRY, carry); + self.registers.p.set(CpuStatus::OVERFLOW, overflow); + self.update_nz8(result); + } else { + let a = self.registers.a; + let carry_in = self.registers.p.contains(CpuStatus::CARRY); + let (result, carry, overflow) = if self.registers.p.contains(CpuStatus::DECIMAL) + { + Self::adc_decimal16(a, value, carry_in) + } else { + let carry_in = u16::from(carry_in); + let (sum1, carry1) = a.overflowing_add(value); + let (result, carry2) = sum1.overflowing_add(carry_in); + ( + result, + carry1 || carry2, + ((!(a ^ value) & (a ^ result)) & 0x8000) != 0, + ) + }; + self.registers.a = result; + self.registers.p.set(CpuStatus::CARRY, carry); + self.registers.p.set(CpuStatus::OVERFLOW, overflow); + self.update_nz16(result); + } + } + ImmediateMathOp::SbcA => { + if self.accumulator_is_8bit() { + let a = self.registers.a as u8; + let operand = value as u8; + let carry_in = self.registers.p.contains(CpuStatus::CARRY); + let (result, carry, overflow) = if self.registers.p.contains(CpuStatus::DECIMAL) + { + Self::sbc_decimal8(a, operand, carry_in) + } else { + let carry_in = u8::from(carry_in); + let inverted = !operand; + let (sum1, carry1) = a.overflowing_add(inverted); + let (result, carry2) = sum1.overflowing_add(carry_in); + ( + result, + carry1 || carry2, + ((!(a ^ inverted) & (a ^ result)) & 0x80) != 0, + ) + }; + self.registers.a = (self.registers.a & 0xFF00) | u16::from(result); + self.registers.p.set(CpuStatus::CARRY, carry); + self.registers.p.set(CpuStatus::OVERFLOW, overflow); + self.update_nz8(result); + } else { + let a = self.registers.a; + let carry_in = self.registers.p.contains(CpuStatus::CARRY); + let (result, carry, overflow) = if self.registers.p.contains(CpuStatus::DECIMAL) + { + Self::sbc_decimal16(a, value, carry_in) + } else { + let carry_in = u16::from(carry_in); + let inverted = !value; + let (sum1, carry1) = a.overflowing_add(inverted); + let (result, carry2) = sum1.overflowing_add(carry_in); + ( + result, + carry1 || carry2, + ((!(a ^ inverted) & (a ^ result)) & 0x8000) != 0, + ) + }; + self.registers.a = result; + self.registers.p.set(CpuStatus::CARRY, carry); + self.registers.p.set(CpuStatus::OVERFLOW, overflow); + self.update_nz16(result); + } + } + ImmediateMathOp::CmpA => { + if self.accumulator_is_8bit() { + self.compare_value8(self.registers.a as u8, value as u8); + } else { + self.compare_value16(self.registers.a, value); + } + } + ImmediateMathOp::CmpX => self.compare_x(value), + ImmediateMathOp::CmpY => self.compare_y(value), + } + } + + fn immediate_math_width(&self, op: ImmediateMathOp) -> u8 { + match op { + ImmediateMathOp::BitA + | ImmediateMathOp::AndA + | ImmediateMathOp::OraA + | ImmediateMathOp::EorA + | ImmediateMathOp::AdcA + | ImmediateMathOp::SbcA + | ImmediateMathOp::CmpA + if self.accumulator_is_8bit() => + { + 1 + } + ImmediateMathOp::CmpX | ImmediateMathOp::CmpY if self.index_is_8bit() => 1, + _ => 2, + } + } + + fn decode_opcode(&mut self, opcode: u8) -> MicroState { + match opcode { + 0x00 => MicroState::Exception(ExceptionKind::Brk), + 0x02 => MicroState::Exception(ExceptionKind::Cop), + 0xEA => MicroState::Implied(ImpliedOp::Nop), + 0x18 => MicroState::Implied(ImpliedOp::Clc), + 0xD8 => MicroState::Implied(ImpliedOp::Cld), + 0x58 => MicroState::Implied(ImpliedOp::Cli), + 0xB8 => MicroState::Implied(ImpliedOp::Clv), + 0x38 => MicroState::Implied(ImpliedOp::Sec), + 0xF8 => MicroState::Implied(ImpliedOp::Sed), + 0x78 => MicroState::Implied(ImpliedOp::Sei), + 0x0A => MicroState::Implied(ImpliedOp::AslAcc), + 0x2A => MicroState::Implied(ImpliedOp::RolAcc), + 0x6A => MicroState::Implied(ImpliedOp::RorAcc), + 0x1A => MicroState::Implied(ImpliedOp::IncA), + 0x3A => MicroState::Implied(ImpliedOp::DecA), + 0xE8 => MicroState::Implied(ImpliedOp::Inx), + 0xC8 => MicroState::Implied(ImpliedOp::Iny), + 0xCA => MicroState::Implied(ImpliedOp::Dex), + 0x88 => MicroState::Implied(ImpliedOp::Dey), + 0x4A => MicroState::Implied(ImpliedOp::LsrAcc), + 0x8A => MicroState::Implied(ImpliedOp::Txa), + 0x98 => MicroState::Implied(ImpliedOp::Tya), + 0xA8 => MicroState::Implied(ImpliedOp::Tay), + 0xAA => MicroState::Implied(ImpliedOp::Tax), + 0x9B => MicroState::Implied(ImpliedOp::Txy), + 0xBB => MicroState::Implied(ImpliedOp::Tyx), + 0xBA => MicroState::Implied(ImpliedOp::Tsx), + 0x1B => MicroState::Implied(ImpliedOp::Tcs), + 0x5B => MicroState::Implied(ImpliedOp::Tcd), + 0x7B => MicroState::Implied(ImpliedOp::Tdc), + 0x3B => MicroState::Implied(ImpliedOp::Tsc), + 0xEB => MicroState::Implied(ImpliedOp::Xba), + 0xFB => MicroState::Implied(ImpliedOp::Xce), + 0x9A => MicroState::Implied(ImpliedOp::Txs), + 0xDB => MicroState::Implied(ImpliedOp::Stp), + 0xCB => MicroState::Implied(ImpliedOp::Wai), + 0x80 => MicroState::Branch(BranchKind::Always), + 0x90 => MicroState::Branch(BranchKind::CarryClear), + 0xB0 => MicroState::Branch(BranchKind::CarrySet), + 0xF0 => MicroState::Branch(BranchKind::Equal), + 0xD0 => MicroState::Branch(BranchKind::NotEqual), + 0x30 => MicroState::Branch(BranchKind::Minus), + 0x10 => MicroState::Branch(BranchKind::Plus), + 0x50 => MicroState::Branch(BranchKind::OverflowClear), + 0x70 => MicroState::Branch(BranchKind::OverflowSet), + 0xC2 => MicroState::Immediate8(Immediate8Op::Rep), + 0xE2 => MicroState::Immediate8(Immediate8Op::Sep), + 0x42 => MicroState::Immediate8(Immediate8Op::Wdm), + 0x44 => MicroState::BlockMoveFirstBank(BlockMoveDirection::Decrement), + 0x54 => MicroState::BlockMoveFirstBank(BlockMoveDirection::Increment), + 0x62 => MicroState::Immediate16Low(Immediate16Op::Per), + 0x82 => MicroState::BranchLongLow, + 0xA9 => MicroState::ImmediateLoadLow(ImmediateLoadTarget::A), + 0xA2 => MicroState::ImmediateLoadLow(ImmediateLoadTarget::X), + 0xA0 => MicroState::ImmediateLoadLow(ImmediateLoadTarget::Y), + 0x29 => MicroState::ImmediateMathLow(ImmediateMathOp::AndA), + 0x09 => MicroState::ImmediateMathLow(ImmediateMathOp::OraA), + 0x49 => MicroState::ImmediateMathLow(ImmediateMathOp::EorA), + 0x69 => MicroState::ImmediateMathLow(ImmediateMathOp::AdcA), + 0xE9 => MicroState::ImmediateMathLow(ImmediateMathOp::SbcA), + 0x89 => MicroState::ImmediateMathLow(ImmediateMathOp::BitA), + 0xC9 => MicroState::ImmediateMathLow(ImmediateMathOp::CmpA), + 0xE0 => MicroState::ImmediateMathLow(ImmediateMathOp::CmpX), + 0xC0 => MicroState::ImmediateMathLow(ImmediateMathOp::CmpY), + 0x85 => MicroState::Direct(DirectOp::Sta { + wide: !self.accumulator_is_8bit(), + }), + 0x06 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Asl, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x26 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Rol, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x46 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Lsr, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x66 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Ror, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x86 => MicroState::Direct(DirectOp::Stx { + wide: !self.index_is_8bit(), + }), + 0x23 => MicroState::StackRelative(StackRelativeOp::AndA), + 0x03 => MicroState::StackRelative(StackRelativeOp::OraA), + 0x43 => MicroState::StackRelative(StackRelativeOp::EorA), + 0x25 => MicroState::Direct(DirectOp::And { + wide: !self.accumulator_is_8bit(), + }), + 0x05 => MicroState::Direct(DirectOp::Ora { + wide: !self.accumulator_is_8bit(), + }), + 0x45 => MicroState::Direct(DirectOp::Eor { + wide: !self.accumulator_is_8bit(), + }), + 0xA4 => MicroState::Direct(DirectOp::Ldy { + wide: !self.index_is_8bit(), + }), + 0xC4 => MicroState::Direct(DirectOp::Cpy { + wide: !self.index_is_8bit(), + }), + 0xC5 => MicroState::Direct(DirectOp::CmpA { + wide: !self.accumulator_is_8bit(), + }), + 0xE6 => MicroState::Direct(DirectOp::Inc { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x24 => MicroState::Direct(DirectOp::Bit { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x84 => MicroState::Direct(DirectOp::Sty { + wide: !self.index_is_8bit(), + }), + 0x64 => MicroState::Direct(DirectOp::Stz { + wide: !self.accumulator_is_8bit(), + }), + 0x14 => MicroState::Direct(DirectOp::Trb { + wide: !self.accumulator_is_8bit(), + }), + 0x04 => MicroState::Direct(DirectOp::Tsb { + wide: !self.accumulator_is_8bit(), + }), + 0xA5 => MicroState::Direct(DirectOp::Lda { + wide: !self.accumulator_is_8bit(), + }), + 0x65 => MicroState::Direct(DirectOp::Adc { + wide: !self.accumulator_is_8bit(), + }), + 0xE5 => MicroState::Direct(DirectOp::Sbc { + wide: !self.accumulator_is_8bit(), + }), + 0x35 => MicroState::Direct(DirectOp::AndIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x15 => MicroState::Direct(DirectOp::OraIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x55 => MicroState::Direct(DirectOp::EorIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xD5 => MicroState::Direct(DirectOp::CmpAIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xF6 => MicroState::Direct(DirectOp::Inc { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x34 => MicroState::Direct(DirectOp::Bit { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0xD6 => MicroState::Direct(DirectOp::Dec { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x16 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Asl, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x36 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Rol, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x56 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Lsr, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x76 => MicroState::Direct(DirectOp::Shift { + op: ShiftOp::Ror, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x75 => MicroState::Direct(DirectOp::AdcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x95 => MicroState::Direct(DirectOp::StaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x96 => MicroState::Direct(DirectOp::StxIndexedY { + wide: !self.index_is_8bit(), + }), + 0xF5 => MicroState::Direct(DirectOp::SbcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xB4 => MicroState::Direct(DirectOp::LdyIndexedX { + wide: !self.index_is_8bit(), + }), + 0x94 => MicroState::Direct(DirectOp::StyIndexedX { + wide: !self.index_is_8bit(), + }), + 0x74 => MicroState::Direct(DirectOp::StzIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xA6 => MicroState::Direct(DirectOp::Ldx { + wide: !self.index_is_8bit(), + }), + 0xB6 => MicroState::Direct(DirectOp::LdxIndexedY { + wide: !self.index_is_8bit(), + }), + 0xB5 => MicroState::Direct(DirectOp::LdaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xC6 => MicroState::Direct(DirectOp::Dec { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0xE4 => MicroState::Direct(DirectOp::Cpx { + wide: !self.index_is_8bit(), + }), + 0x61 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::AdcA), + 0x81 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::Sta), + 0xE1 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::SbcA), + 0x21 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::AndA), + 0x01 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::OraA), + 0x41 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::EorA), + 0xA1 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::Lda), + 0xC1 => MicroState::DirectIndexedIndirect(DirectIndexedIndirectOp::CmpA), + 0x63 => MicroState::StackRelative(StackRelativeOp::AdcA), + 0x83 => MicroState::StackRelative(StackRelativeOp::Sta), + 0xE3 => MicroState::StackRelative(StackRelativeOp::SbcA), + 0xA3 => MicroState::StackRelative(StackRelativeOp::Lda), + 0xC3 => MicroState::StackRelative(StackRelativeOp::CmpA), + 0x67 => MicroState::DirectIndirectLong(DirectIndirectLongOp::AdcA), + 0x87 => MicroState::DirectIndirectLong(DirectIndirectLongOp::Sta), + 0xE7 => MicroState::DirectIndirectLong(DirectIndirectLongOp::SbcA), + 0x27 => MicroState::DirectIndirectLong(DirectIndirectLongOp::AndA), + 0x07 => MicroState::DirectIndirectLong(DirectIndirectLongOp::OraA), + 0x47 => MicroState::DirectIndirectLong(DirectIndirectLongOp::EorA), + 0xA7 => MicroState::DirectIndirectLong(DirectIndirectLongOp::Lda), + 0xC7 => MicroState::DirectIndirectLong(DirectIndirectLongOp::CmpA), + 0x31 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::AndA), + 0x11 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::OraA), + 0x51 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::EorA), + 0x91 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::Sta), + 0xF1 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::SbcA), + 0xB1 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::Lda), + 0x92 => MicroState::DirectIndirect(DirectIndirectOp::Sta), + 0x32 => MicroState::DirectIndirect(DirectIndirectOp::AndA), + 0x12 => MicroState::DirectIndirect(DirectIndirectOp::OraA), + 0x52 => MicroState::DirectIndirect(DirectIndirectOp::EorA), + 0xF2 => MicroState::DirectIndirect(DirectIndirectOp::SbcA), + 0xB2 => MicroState::DirectIndirect(DirectIndirectOp::Lda), + 0xD1 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::CmpA), + 0xD2 => MicroState::DirectIndirect(DirectIndirectOp::CmpA), + 0xD4 => MicroState::PeiPointerLow, + 0x33 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::AndA) + } + 0x13 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::OraA) + } + 0x53 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::EorA) + } + 0x93 => MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::Sta), + 0xF3 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::SbcA) + } + 0xB3 => MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::Lda), + 0xD3 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::CmpA) + } + 0x37 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::AndALong), + 0x17 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::OraALong), + 0x57 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::EorALong), + 0x97 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::StaLong), + 0xF7 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::SbcALong), + 0xB7 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::LdaLong), + 0x71 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::AdcA), + 0x72 => MicroState::DirectIndirect(DirectIndirectOp::AdcA), + 0x73 => { + MicroState::StackRelativeIndirectIndexedY(StackRelativeIndirectIndexedYOp::AdcA) + } + 0x77 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::AdcALong), + 0xD7 => MicroState::DirectIndirectIndexedY(DirectIndirectIndexedYOp::CmpALong), + 0x39 => MicroState::AbsoluteLow(AbsoluteOp::AndIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0x19 => MicroState::AbsoluteLow(AbsoluteOp::OraIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0x59 => MicroState::AbsoluteLow(AbsoluteOp::EorIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0xB9 => MicroState::AbsoluteLow(AbsoluteOp::LdaIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0xD9 => MicroState::AbsoluteLow(AbsoluteOp::CmpAIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0x79 => MicroState::AbsoluteLow(AbsoluteOp::AdcIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0x99 => MicroState::AbsoluteLow(AbsoluteOp::StaIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0xF9 => MicroState::AbsoluteLow(AbsoluteOp::SbcIndexedY { + wide: !self.accumulator_is_8bit(), + }), + 0x2D => MicroState::AbsoluteLow(AbsoluteOp::And { + wide: !self.accumulator_is_8bit(), + }), + 0x0D => MicroState::AbsoluteLow(AbsoluteOp::Ora { + wide: !self.accumulator_is_8bit(), + }), + 0x4D => MicroState::AbsoluteLow(AbsoluteOp::Eor { + wide: !self.accumulator_is_8bit(), + }), + 0xCD => MicroState::AbsoluteLow(AbsoluteOp::CmpA { + wide: !self.accumulator_is_8bit(), + }), + 0xAC => MicroState::AbsoluteLow(AbsoluteOp::Ldy { + wide: !self.index_is_8bit(), + }), + 0xCC => MicroState::AbsoluteLow(AbsoluteOp::Cpy { + wide: !self.index_is_8bit(), + }), + 0xCE => MicroState::AbsoluteLow(AbsoluteOp::Dec { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0xEC => MicroState::AbsoluteLow(AbsoluteOp::Cpx { + wide: !self.index_is_8bit(), + }), + 0xEE => MicroState::AbsoluteLow(AbsoluteOp::Inc { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x6D => MicroState::AbsoluteLow(AbsoluteOp::Adc { + wide: !self.accumulator_is_8bit(), + }), + 0xED => MicroState::AbsoluteLow(AbsoluteOp::Sbc { + wide: !self.accumulator_is_8bit(), + }), + 0x3D => MicroState::AbsoluteLow(AbsoluteOp::AndIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x1D => MicroState::AbsoluteLow(AbsoluteOp::OraIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x5D => MicroState::AbsoluteLow(AbsoluteOp::EorIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xBC => MicroState::AbsoluteLow(AbsoluteOp::LdyIndexedX { + wide: !self.index_is_8bit(), + }), + 0xBD => MicroState::AbsoluteLow(AbsoluteOp::LdaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xBE => MicroState::AbsoluteLow(AbsoluteOp::LdxIndexedY { + wide: !self.index_is_8bit(), + }), + 0xDD => MicroState::AbsoluteLow(AbsoluteOp::CmpAIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xFE => MicroState::AbsoluteLow(AbsoluteOp::Inc { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0xDE => MicroState::AbsoluteLow(AbsoluteOp::Dec { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x7D => MicroState::AbsoluteLow(AbsoluteOp::AdcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x9D => MicroState::AbsoluteLow(AbsoluteOp::StaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xFD => MicroState::AbsoluteLow(AbsoluteOp::SbcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xAD => MicroState::AbsoluteLow(AbsoluteOp::Lda { + wide: !self.accumulator_is_8bit(), + }), + 0xAE => MicroState::AbsoluteLow(AbsoluteOp::Ldx { + wide: !self.index_is_8bit(), + }), + 0x8E => MicroState::AbsoluteLow(AbsoluteOp::Stx { + wide: !self.index_is_8bit(), + }), + 0x8D => MicroState::AbsoluteLow(AbsoluteOp::Sta { + wide: !self.accumulator_is_8bit(), + }), + 0x8C => MicroState::AbsoluteLow(AbsoluteOp::Sty { + wide: !self.index_is_8bit(), + }), + 0x9C => MicroState::AbsoluteLow(AbsoluteOp::Stz { + wide: !self.accumulator_is_8bit(), + }), + 0x9E => MicroState::AbsoluteLow(AbsoluteOp::StzIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x1C => MicroState::AbsoluteLow(AbsoluteOp::Trb { + wide: !self.accumulator_is_8bit(), + }), + 0x0C => MicroState::AbsoluteLow(AbsoluteOp::Tsb { + wide: !self.accumulator_is_8bit(), + }), + 0x2C => MicroState::AbsoluteLow(AbsoluteOp::Bit { + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x3C => MicroState::AbsoluteLow(AbsoluteOp::Bit { + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x0E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Asl, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x2E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Rol, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x4E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Lsr, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x6E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Ror, + indexed_x: false, + wide: !self.accumulator_is_8bit(), + }), + 0x6C => MicroState::AbsoluteLow(AbsoluteOp::JmpIndirect), + 0x1E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Asl, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x3E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Rol, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x5E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Lsr, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x7E => MicroState::AbsoluteLow(AbsoluteOp::Shift { + op: ShiftOp::Ror, + indexed_x: true, + wide: !self.accumulator_is_8bit(), + }), + 0x7C => MicroState::AbsoluteLow(AbsoluteOp::JmpIndexedXIndirect), + 0x4C => MicroState::AbsoluteLow(AbsoluteOp::Jmp), + 0x20 => MicroState::AbsoluteLow(AbsoluteOp::Jsr), + 0xFC => MicroState::AbsoluteLow(AbsoluteOp::JsrIndexedXIndirect), + 0xDC => MicroState::AbsoluteLow(AbsoluteOp::JmlIndirect), + 0x2F => MicroState::AbsoluteLongLow(AbsoluteLongOp::And { + wide: !self.accumulator_is_8bit(), + }), + 0x0F => MicroState::AbsoluteLongLow(AbsoluteLongOp::Ora { + wide: !self.accumulator_is_8bit(), + }), + 0x4F => MicroState::AbsoluteLongLow(AbsoluteLongOp::Eor { + wide: !self.accumulator_is_8bit(), + }), + 0xCF => MicroState::AbsoluteLongLow(AbsoluteLongOp::CmpA { + wide: !self.accumulator_is_8bit(), + }), + 0x6F => MicroState::AbsoluteLongLow(AbsoluteLongOp::Adc { + wide: !self.accumulator_is_8bit(), + }), + 0xEF => MicroState::AbsoluteLongLow(AbsoluteLongOp::Sbc { + wide: !self.accumulator_is_8bit(), + }), + 0x3F => MicroState::AbsoluteLongLow(AbsoluteLongOp::AndIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x1F => MicroState::AbsoluteLongLow(AbsoluteLongOp::OraIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x5F => MicroState::AbsoluteLongLow(AbsoluteLongOp::EorIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xDF => MicroState::AbsoluteLongLow(AbsoluteLongOp::CmpAIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x7F => MicroState::AbsoluteLongLow(AbsoluteLongOp::AdcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x9F => MicroState::AbsoluteLongLow(AbsoluteLongOp::StaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xFF => MicroState::AbsoluteLongLow(AbsoluteLongOp::SbcIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0xAF => MicroState::AbsoluteLongLow(AbsoluteLongOp::Lda { + wide: !self.accumulator_is_8bit(), + }), + 0xBF => MicroState::AbsoluteLongLow(AbsoluteLongOp::LdaIndexedX { + wide: !self.accumulator_is_8bit(), + }), + 0x22 => MicroState::AbsoluteLongLow(AbsoluteLongOp::Jsl), + 0x5C => MicroState::AbsoluteLongLow(AbsoluteLongOp::Jml), + 0x8F => MicroState::AbsoluteLongLow(AbsoluteLongOp::Sta { + wide: !self.accumulator_is_8bit(), + }), + 0x48 => MicroState::Stack(StackOp::Pha), + 0x68 => MicroState::Stack(StackOp::Pla), + 0x08 => MicroState::Stack(StackOp::Php), + 0x28 => MicroState::Stack(StackOp::Plp), + 0xDA => MicroState::Stack(StackOp::Phx), + 0x5A => MicroState::Stack(StackOp::Phy), + 0x8B => MicroState::Stack(StackOp::Phb), + 0x4B => MicroState::Stack(StackOp::Phk), + 0x0B => MicroState::Stack(StackOp::Phd), + 0xFA => MicroState::Stack(StackOp::Plx), + 0x7A => MicroState::Stack(StackOp::Ply), + 0xAB => MicroState::Stack(StackOp::Plb), + 0x2B => MicroState::Stack(StackOp::Pld), + 0xF4 => MicroState::Immediate16Low(Immediate16Op::Pea), + 0x40 => MicroState::RtiPullStatus, + 0x60 => MicroState::RtsPullLow, + 0x6B => MicroState::RtlPullLow, + } + } + + fn full_pc(&self) -> u32 { + ((self.registers.pb as u32) << 16) | (self.registers.pc as u32) + } + + fn read_data_bank(&mut self, bus: &mut dyn CpuBus, address: u16) -> u8 { + bus.read(self.full_data_address(address)) + } + + fn full_data_address(&self, address: u16) -> u32 { + ((self.registers.db as u32) << 16) | u32::from(address) + } + + fn read_zero_bank_u16(&mut self, bus: &mut dyn CpuBus, address: u16) -> u16 { + let low = bus.read(u32::from(address)); + let high = bus.read(u32::from(address.wrapping_add(1))); + u16::from_le_bytes([low, high]) + } + + fn read_zero_bank_u24(&mut self, bus: &mut dyn CpuBus, address: u16) -> u32 { + let target = self.read_zero_bank_u16(bus, address); + let bank = bus.read(u32::from(address.wrapping_add(2))); + ((bank as u32) << 16) | u32::from(target) + } + + fn read_program_bank_u16(&mut self, bus: &mut dyn CpuBus, address: u16) -> u16 { + let bank_base = (self.registers.pb as u32) << 16; + let low = bus.read(bank_base | u32::from(address)); + let high = bus.read(bank_base | u32::from(address.wrapping_add(1))); + u16::from_le_bytes([low, high]) + } + + fn read_operand_value(&mut self, bus: &mut dyn CpuBus, address: u32, wide: bool) -> u16 { + let low = bus.read(address); + if wide { + let high = bus.read(address.wrapping_add(1)); + u16::from_le_bytes([low, high]) + } else { + u16::from(low) + } + } + + fn write_operand_value(&mut self, bus: &mut dyn CpuBus, address: u32, value: u16, wide: bool) { + bus.write(address, value as u8); + if wide { + self.micro_state = MicroState::WriteHigh { + address: address.wrapping_add(1), + value: (value >> 8) as u8, + }; + } else { + self.micro_state = MicroState::Fetch; + } + } + + fn write_operand_value_zero_bank( + &mut self, + bus: &mut dyn CpuBus, + address: u16, + value: u16, + wide: bool, + ) { + bus.write(u32::from(address), value as u8); + if wide { + self.micro_state = MicroState::WriteHigh { + address: u32::from(address.wrapping_add(1)), + value: (value >> 8) as u8, + }; + } else { + self.micro_state = MicroState::Fetch; + } + } + + fn store_accumulator(&mut self, bus: &mut dyn CpuBus, address: u32) { + self.write_operand_value(bus, address, self.registers.a, !self.accumulator_is_8bit()); + } + + fn adjust_block_move_indexes(&mut self, direction: BlockMoveDirection) { + let adjust = |value: u16, index_8bit: bool, direction| match (index_8bit, direction) { + (true, BlockMoveDirection::Increment) => u16::from((value as u8).wrapping_add(1)), + (true, BlockMoveDirection::Decrement) => u16::from((value as u8).wrapping_sub(1)), + (false, BlockMoveDirection::Increment) => value.wrapping_add(1), + (false, BlockMoveDirection::Decrement) => value.wrapping_sub(1), + }; + self.registers.x = adjust(self.registers.x, self.index_is_8bit(), direction); + self.registers.y = adjust(self.registers.y, self.index_is_8bit(), direction); + } + + fn burn_internal_cycles(&mut self, bus: &mut dyn CpuBus, additional: u8) { + self.cycles = self.cycles.wrapping_add(u64::from(additional)); + bus.tick_many(u32::from(additional)); + } + + fn direct_page_cycle_penalty(&self) -> u8 { + u8::from((self.registers.d & 0x00FF) != 0) + } + + fn direct_indirect_indexed_y_cycle_penalty(&self, base: u16) -> u8 { + if !self.index_is_8bit() { + 1 + } else { + u8::from(u16::from(base as u8) + (self.registers.y & 0x00FF) > 0x00FF) + } + } + + fn stack_push(&mut self, bus: &mut dyn CpuBus, value: u8) { + bus.write(u32::from(self.registers.s), value); + self.registers.s = self.registers.s.wrapping_sub(1); + self.registers.s = self.normalize_stack_pointer(self.registers.s); + } + + fn stack_pop(&mut self, bus: &mut dyn CpuBus) -> u8 { + self.registers.s = self.registers.s.wrapping_add(1); + self.registers.s = self.normalize_stack_pointer(self.registers.s); + bus.read(u32::from(self.registers.s)) + } + + fn stack_push_raw(&mut self, bus: &mut dyn CpuBus, stack_addr: u16, value: u8) -> u16 { + bus.write(u32::from(stack_addr), value); + stack_addr.wrapping_sub(1) + } + + fn stack_pop_raw(&mut self, bus: &mut dyn CpuBus, stack_addr: u16) -> (u16, u8) { + let stack_addr = stack_addr.wrapping_add(1); + let value = bus.read(u32::from(stack_addr)); + (stack_addr, value) + } + + fn normalize_stack_pointer(&self, stack_addr: u16) -> u16 { + if self.registers.e { + (stack_addr & 0x00FF) | 0x0100 + } else { + stack_addr + } + } + + fn accumulator_is_8bit(&self) -> bool { + self.registers.e || self.registers.p.contains(CpuStatus::ACCUMULATOR_8BIT) + } + + fn index_is_8bit(&self) -> bool { + self.registers.e || self.registers.p.contains(CpuStatus::INDEX_8BIT) + } + + fn load_width(&self, target: ImmediateLoadTarget) -> u8 { + match target { + ImmediateLoadTarget::A if self.accumulator_is_8bit() => 1, + ImmediateLoadTarget::X | ImmediateLoadTarget::Y if self.index_is_8bit() => 1, + _ => 2, + } + } + + fn shift_accumulator(&mut self, op: ShiftOp) { + if self.accumulator_is_8bit() { + let value = self.apply_shift8(op, self.registers.a as u8); + self.registers.a = (self.registers.a & 0xFF00) | u16::from(value); + } else { + self.registers.a = self.apply_shift16(op, self.registers.a); + } + } + + fn apply_shift8(&mut self, op: ShiftOp, value: u8) -> u8 { + match op { + ShiftOp::Asl => { + self.registers.p.set(CpuStatus::CARRY, value & 0x80 != 0); + let result = value << 1; + self.update_nz8(result); + result + } + ShiftOp::Rol => { + let carry_in = u8::from(self.registers.p.contains(CpuStatus::CARRY)); + self.registers.p.set(CpuStatus::CARRY, value & 0x80 != 0); + let result = (value << 1) | carry_in; + self.update_nz8(result); + result + } + ShiftOp::Ror => { + let carry_in = u8::from(self.registers.p.contains(CpuStatus::CARRY)) << 7; + self.registers.p.set(CpuStatus::CARRY, value & 0x01 != 0); + let result = (value >> 1) | carry_in; + self.update_nz8(result); + result + } + ShiftOp::Lsr => { + self.registers.p.set(CpuStatus::CARRY, value & 0x01 != 0); + let result = value >> 1; + self.update_nz8(result); + result + } + } + } + + fn apply_shift16(&mut self, op: ShiftOp, value: u16) -> u16 { + match op { + ShiftOp::Asl => { + self.registers.p.set(CpuStatus::CARRY, value & 0x8000 != 0); + let result = value << 1; + self.update_nz16(result); + result + } + ShiftOp::Rol => { + let carry_in = u16::from(self.registers.p.contains(CpuStatus::CARRY)); + self.registers.p.set(CpuStatus::CARRY, value & 0x8000 != 0); + let result = (value << 1) | carry_in; + self.update_nz16(result); + result + } + ShiftOp::Ror => { + let carry_in = u16::from(self.registers.p.contains(CpuStatus::CARRY)) << 15; + self.registers.p.set(CpuStatus::CARRY, value & 0x0001 != 0); + let result = (value >> 1) | carry_in; + self.update_nz16(result); + result + } + ShiftOp::Lsr => { + self.registers.p.set(CpuStatus::CARRY, value & 0x0001 != 0); + let result = value >> 1; + self.update_nz16(result); + result + } + } + } + + fn apply_memory_bit(&mut self, value: u16) { + if self.accumulator_is_8bit() { + let value = value as u8; + self.registers + .p + .set(CpuStatus::ZERO, (self.registers.a as u8) & value == 0); + self.registers.p.set(CpuStatus::NEGATIVE, value & 0x80 != 0); + self.registers.p.set(CpuStatus::OVERFLOW, value & 0x40 != 0); + } else { + self.registers + .p + .set(CpuStatus::ZERO, self.registers.a & value == 0); + self.registers + .p + .set(CpuStatus::NEGATIVE, value & 0x8000 != 0); + self.registers + .p + .set(CpuStatus::OVERFLOW, value & 0x4000 != 0); + } + } + + fn apply_test_modify8(&mut self, op: TestModifyOp, value: u8) -> u8 { + let a = self.registers.a as u8; + self.registers.p.set(CpuStatus::ZERO, a & value == 0); + match op { + TestModifyOp::Trb => value & !a, + TestModifyOp::Tsb => value | a, + } + } + + fn apply_test_modify16(&mut self, op: TestModifyOp, value: u16) -> u16 { + let a = self.registers.a; + self.registers.p.set(CpuStatus::ZERO, a & value == 0); + match op { + TestModifyOp::Trb => value & !a, + TestModifyOp::Tsb => value | a, + } + } + + fn branch_taken(&self, kind: BranchKind) -> bool { + match kind { + BranchKind::Always => true, + BranchKind::CarryClear => !self.registers.p.contains(CpuStatus::CARRY), + BranchKind::CarrySet => self.registers.p.contains(CpuStatus::CARRY), + BranchKind::Equal => self.registers.p.contains(CpuStatus::ZERO), + BranchKind::NotEqual => !self.registers.p.contains(CpuStatus::ZERO), + BranchKind::Minus => self.registers.p.contains(CpuStatus::NEGATIVE), + BranchKind::Plus => !self.registers.p.contains(CpuStatus::NEGATIVE), + BranchKind::OverflowClear => !self.registers.p.contains(CpuStatus::OVERFLOW), + BranchKind::OverflowSet => self.registers.p.contains(CpuStatus::OVERFLOW), + } + } + + fn apply_rmw8(&mut self, op: RmwOp, value: u8) -> u8 { + match op { + RmwOp::Inc => { + let r = value.wrapping_add(1); + self.update_nz8(r); + r + } + RmwOp::Dec => { + let r = value.wrapping_sub(1); + self.update_nz8(r); + r + } + RmwOp::Asl => self.apply_shift8(ShiftOp::Asl, value), + RmwOp::Lsr => self.apply_shift8(ShiftOp::Lsr, value), + RmwOp::Rol => self.apply_shift8(ShiftOp::Rol, value), + RmwOp::Ror => self.apply_shift8(ShiftOp::Ror, value), + RmwOp::Trb => self.apply_test_modify8(TestModifyOp::Trb, value), + RmwOp::Tsb => self.apply_test_modify8(TestModifyOp::Tsb, value), + } + } + + fn update_nz8(&mut self, value: u8) { + self.registers.p.set(CpuStatus::ZERO, value == 0); + self.registers.p.set(CpuStatus::NEGATIVE, value & 0x80 != 0); + } + + fn update_nz16(&mut self, value: u16) { + self.registers.p.set(CpuStatus::ZERO, value == 0); + self.registers + .p + .set(CpuStatus::NEGATIVE, value & 0x8000 != 0); + } + + fn compare_x(&mut self, value: u16) { + if self.index_is_8bit() { + self.compare_value8(self.registers.x as u8, value as u8); + } else { + self.compare_value16(self.registers.x, value); + } + } + + fn compare_y(&mut self, value: u16) { + if self.index_is_8bit() { + self.compare_value8(self.registers.y as u8, value as u8); + } else { + self.compare_value16(self.registers.y, value); + } + } + + fn compare_value8(&mut self, left: u8, right: u8) { + let result = left.wrapping_sub(right); + self.registers.p.set(CpuStatus::CARRY, left >= right); + self.update_nz8(result); + } + + fn compare_value16(&mut self, left: u16, right: u16) { + let result = left.wrapping_sub(right); + self.registers.p.set(CpuStatus::CARRY, left >= right); + self.update_nz16(result); + } + + fn refresh_state(&mut self) { + self.current_state = match self.micro_state { + MicroState::Reset { .. } => CpuState::Resetting, + MicroState::Stopped => CpuState::Stopped, + MicroState::WaitingForInterrupt => CpuState::Waiting, + _ => CpuState::Running, + }; + } +} + +#[cfg(test)] +mod tests { + use super::{Cpu, CpuState, CpuStatus}; + use crate::bus::CpuBus; + use std::collections::BTreeMap; + + #[derive(Default)] + struct TestBus { + memory: BTreeMap, + nmi_pending: bool, + irq_pending: bool, + } + + impl TestBus { + fn with_reset_vector(vector: u16) -> Self { + let mut system = Self::default(); + system.load(0x00FFFC, &vector.to_le_bytes()); + system + } + + fn load_native_exception_vectors(&mut self, cop: u16, brk: u16) { + self.load(0x00FFE4, &cop.to_le_bytes()); + self.load(0x00FFE6, &brk.to_le_bytes()); + } + + fn load_native_nmi_vector(&mut self, nmi: u16) { + self.load(0x00FFEA, &nmi.to_le_bytes()); + } + + fn load_emulation_irq_vector(&mut self, irq: u16) { + self.load(0x00FFFE, &irq.to_le_bytes()); + } + + fn load(&mut self, base: u32, bytes: &[u8]) { + for (offset, value) in bytes.iter().copied().enumerate() { + self.memory.insert(base + offset as u32, value); + } + } + } + + impl CpuBus for TestBus { + fn read(&mut self, addr: u32) -> u8 { + *self.memory.get(&addr).unwrap_or(&0) + } + + fn write(&mut self, addr: u32, data: u8) { + self.memory.insert(addr, data); + } + + fn tick(&mut self) {} + + fn tick_many(&mut self, _cycles: u32) {} + + fn poll_nmi(&mut self) -> bool { + core::mem::take(&mut self.nmi_pending) + } + + fn poll_irq(&mut self) -> bool { + self.irq_pending + } + } + + fn step_n(cpu: &mut Cpu, system: &mut TestBus, cycles: usize) { + for _ in 0..cycles { + cpu.step(system); + } + } + + fn run_until_stopped(cpu: &mut Cpu, system: &mut TestBus, max_cycles: usize) { + for _ in 0..max_cycles { + cpu.step(system); + if cpu.current_state() == CpuState::Stopped { + return; + } + } + + panic!("CPU did not stop within {max_cycles} cycles"); + } + + #[test] + fn reset_takes_seven_cycles_and_populates_register_snapshot() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x1234); + + step_n(&mut cpu, &mut system, 7); + + assert_eq!(cpu.current_state(), CpuState::Running); + assert_eq!(cpu.cycles(), 7); + assert_eq!(cpu.registers().pc(), 0x1234); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().db(), 0x00); + assert_eq!(cpu.registers().d(), 0x0000); + assert_eq!(cpu.registers().s(), 0x01FF); + assert_eq!( + cpu.registers().status(), + CpuStatus::IRQ_DISABLE | CpuStatus::INDEX_8BIT | CpuStatus::ACCUMULATOR_8BIT + ); + assert!(cpu.registers().emulation_mode()); + } + + #[test] + fn wrapper_tracks_fetched_opcode_and_stopped_state() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xEA, 0xDB]); + + step_n(&mut cpu, &mut system, 8); + assert_eq!(cpu.current_opcode(), 0xEA); + assert_eq!(cpu.registers().pc(), 0x8001); + assert_eq!(cpu.current_state(), CpuState::Running); + + run_until_stopped(&mut cpu, &mut system, 8); + assert_eq!(cpu.current_opcode(), 0xDB); + assert_eq!(cpu.current_state(), CpuState::Stopped); + } + + #[test] + fn wrapper_exposes_native_mode_bootstrap_registers() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 32); + + assert!(!cpu.registers().emulation_mode()); + assert_eq!(cpu.registers().x(), 0x01EF); + assert_eq!(cpu.registers().s(), 0x01EF); + assert!( + !cpu.registers() + .status() + .contains(CpuStatus::ACCUMULATOR_8BIT | CpuStatus::INDEX_8BIT) + ); + } + + #[test] + fn absolute_store_instructions_write_expected_bytes() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0xA9, 0x34, 0x8D, 0x34, 0x12, 0x9C, 0x35, 0x12, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(system.memory.get(&0x001234), Some(&0x34)); + assert_eq!(system.memory.get(&0x001235), Some(&0x00)); + } + + #[test] + fn absolute_load_instruction_reads_expected_bytes() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x001234, &[0xED]); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xAD, 0x34, 0x12, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().a(), 0x00ED); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn jsr_and_rts_restore_program_counter_and_stack() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x20, 0x06, 0x80, 0xDB, 0xEA, 0xEA, 0x18, 0x60]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().pc(), 0x8004); + assert_eq!(cpu.registers().s(), 0x01FF); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + } + + #[test] + fn emulation_mode_jsr_preserves_page_one_stack_wrap() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x5C, 0x00, 0x70, 0x7E]); + system.load(0x7E7000, &[0x20, 0x00, 0x80]); + system.load(0x7E8000, &[0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().s(), 0x01FE); + assert_eq!(system.memory.get(&0x0001FF), Some(&0x02)); + assert_eq!(system.memory.get(&0x000100), Some(&0x70)); + } + + #[test] + fn emulation_mode_pea_wraps_pushes_across_page_zero_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xF4, 0x76, 0x98, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().s(), 0x01FE); + assert_eq!(system.memory.get(&0x0000FF), Some(&0x76)); + assert_eq!(system.memory.get(&0x000100), Some(&0x98)); + } + + #[test] + fn emulation_mode_pei_wraps_pushes_across_page_zero_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000034, &[0x54, 0x76]); + system.load(0x008000, &[0xD4, 0x34, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().s(), 0x01FE); + assert_eq!(system.memory.get(&0x0000FF), Some(&0x54)); + assert_eq!(system.memory.get(&0x000100), Some(&0x76)); + } + + #[test] + fn direct_page_indexed_loads_and_branches_work() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x01, 0x85, 0x10, 0xC6, 0x10, 0xF0, 0x01, + 0xDB, 0xA2, 0x10, 0x00, 0xB5, 0x00, 0x10, 0x01, 0xDB, 0xE8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(system.memory.get(&0x0010), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0x0011); + } + + #[test] + fn bcs_bvs_and_bvc_branch_when_condition_matches() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA0, 0x00, 0x00, 0x38, 0xB0, 0x01, 0xDB, 0xC8, 0xE2, 0x40, + 0x70, 0x01, 0xDB, 0xC8, 0xC2, 0x40, 0x50, 0x01, 0xDB, 0xC8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().y(), 0x0003); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn bcs_bvs_and_bvc_fall_through_when_condition_mismatches() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0x00, 0x00, 0x18, 0xB0, 0x01, 0xE8, 0xC2, 0x40, 0x70, + 0x01, 0xE8, 0xE2, 0x40, 0x50, 0x01, 0xE8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().x(), 0x0003); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + } + + #[test] + fn brk_native_mode_pushes_bank_pc_and_status_then_vectors_to_bank_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load_native_exception_vectors(0x9004, 0x9000); + system.load(0x009000, &[0xDB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x34, 0x12, 0xA2, 0x56, 0x34, 0xA0, 0x78, 0x56, 0xC2, + 0xF4, 0xE2, 0x0B, 0x5C, 0x00, 0x80, 0x7E, + ], + ); + system.load(0x7E8000, &[0x00, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 192); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0x3456); + assert_eq!(cpu.registers().y(), 0x5678); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9001); + assert_eq!(cpu.registers().s(), 0x01FB); + assert_eq!(cpu.registers().status().bits(), 0x07); + assert_eq!(system.memory.get(&0x0001FF), Some(&0x7E)); + assert_eq!(system.memory.get(&0x0001FE), Some(&0x80)); + assert_eq!(system.memory.get(&0x0001FD), Some(&0x02)); + assert_eq!(system.memory.get(&0x0001FC), Some(&0x0B)); + } + + #[test] + fn cop_native_mode_uses_cop_vector_and_pushes_return_state() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load_native_exception_vectors(0x9004, 0x9000); + system.load(0x009004, &[0xDB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x34, 0x12, 0xA2, 0x56, 0x34, 0xA0, 0x78, 0x56, 0xC2, + 0xF4, 0xE2, 0x0B, 0x5C, 0x00, 0x80, 0x7E, + ], + ); + system.load(0x7E8000, &[0x02, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 192); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0x3456); + assert_eq!(cpu.registers().y(), 0x5678); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9005); + assert_eq!(cpu.registers().s(), 0x01FB); + assert_eq!(cpu.registers().status().bits(), 0x07); + assert_eq!(system.memory.get(&0x0001FF), Some(&0x7E)); + assert_eq!(system.memory.get(&0x0001FE), Some(&0x80)); + assert_eq!(system.memory.get(&0x0001FD), Some(&0x02)); + assert_eq!(system.memory.get(&0x0001FC), Some(&0x0B)); + } + + #[test] + fn brl_applies_a_signed_16bit_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x82, 0x03, 0x00, 0xDB, 0xDB, 0xDB, 0xA9, 0x7F, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x007F); + } + + #[test] + fn cld_cli_clv_and_sed_update_only_their_target_flags() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xE2, 0xFF, 0xD8, 0x58, 0xB8, 0xF8, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().status().bits(), 0xBB); + } + + #[test] + fn absolute_bit_and_sty_support_wait_loop_primitives() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA0, 0x21, 0x00, 0x8C, 0x16, 0x21, 0xA9, 0x80, + 0x8D, 0x00, 0x20, 0x2C, 0x00, 0x20, 0x30, 0x01, 0xDB, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(system.memory.get(&0x002116), Some(&0x21)); + assert_eq!(system.memory.get(&0x002117), Some(&0x00)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn jsl_rtl_and_long_addressing_restore_caller_context() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x34, 0x12, 0x22, 0x10, 0x80, 0x01, 0xDB, 0xEA, 0xEA, + 0xEA, 0xEA, + ], + ); + system.load( + 0x018010, + &[ + 0x8F, 0x00, 0x00, 0x7E, 0xA9, 0x78, 0x56, 0x5C, 0x1B, 0x80, 0x01, 0x8F, 0x02, 0x00, + 0x7E, 0x6B, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x7E0000), Some(&0x34)); + assert_eq!(system.memory.get(&0x7E0001), Some(&0x12)); + assert_eq!(system.memory.get(&0x7E0002), Some(&0x78)); + assert_eq!(system.memory.get(&0x7E0003), Some(&0x56)); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x800C); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn emulation_mode_jsl_wraps_pushes_across_page_zero_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x5C, 0x00, 0x70, 0x7F]); + system.load(0x7F7000, &[0x22, 0x00, 0x80, 0xFE]); + system.load(0xFE8000, &[0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().s(), 0x01FD); + assert_eq!(system.memory.get(&0x0000FE), Some(&0x03)); + assert_eq!(system.memory.get(&0x0000FF), Some(&0x70)); + assert_eq!(system.memory.get(&0x000100), Some(&0x7F)); + } + + #[test] + fn emulation_mode_plb_reads_from_second_page_when_stack_is_01ff() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0x99]); + system.load(0x000200, &[0x3D]); + system.load(0x008000, &[0xAB, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x01FF; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().db(), 0x3D); + assert_eq!(cpu.registers().s(), 0x0100); + } + + #[test] + fn emulation_mode_pld_reads_from_second_page_when_stack_is_01ff() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0xAA, 0xBB]); + system.load(0x000200, &[0x56, 0x13]); + system.load(0x008000, &[0x2B, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x01FF; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().d(), 0x1356); + assert_eq!(cpu.registers().s(), 0x0101); + } + + #[test] + fn emulation_mode_pld_crosses_into_second_page_after_first_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0xAA]); + system.load(0x0001FF, &[0x56]); + system.load(0x000200, &[0x13]); + system.load(0x008000, &[0x2B, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x01FE; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().d(), 0x1356); + assert_eq!(cpu.registers().s(), 0x0100); + } + + #[test] + fn emulation_mode_rtl_reads_from_second_page_when_stack_is_01ff() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0x00, 0x10, 0x7F]); + system.load(0x000200, &[0xFF, 0x80, 0x00]); + system.load(0x008000, &[0x6B]); + system.load(0x008100, &[0xA9, 0x42, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x01FF; + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().a(), 0x0042); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().s(), 0x0102); + } + + #[test] + fn emulation_mode_rtl_crosses_into_second_page_for_bank_byte_only() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0x7F]); + system.load(0x0001FE, &[0xFF]); + system.load(0x0001FF, &[0x80]); + system.load(0x000200, &[0x00]); + system.load(0x008000, &[0x6B]); + system.load(0x008100, &[0xA9, 0x24, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x01FD; + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().a(), 0x0024); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().s(), 0x0100); + } + + #[test] + fn rti_restores_native_status_pc_bank_and_stack() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001F0, &[0x88, 0x00, 0x80, 0x7E]); + system.load(0x7E8000, &[0xDB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x31, 0xA9, 0x34, 0x12, 0xA2, 0xEF, 0x01, 0x9A, 0xA2, 0x56, 0x34, + 0xA0, 0x78, 0x56, 0x40, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0x3456); + assert_eq!(cpu.registers().y(), 0x5678); + assert_eq!(cpu.registers().pb(), 0x7E); + assert_eq!(cpu.registers().pc(), 0x8001); + assert_eq!(cpu.registers().s(), 0x01F3); + assert_eq!(cpu.registers().status().bits(), 0x88); + } + + #[test] + fn jmp_indirect_reads_zero_bank_target() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFF0, &[0x10, 0x80]); + system.load(0x008000, &[0x6C, 0xF0, 0xFF, 0xDB]); + system.load(0x008010, &[0xA9, 0x42, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0042); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x8013); + } + + #[test] + fn jml_indirect_reads_zero_bank_long_target() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFF2, &[0x00, 0x80, 0x7E]); + system.load(0x008000, &[0xDC, 0xF2, 0xFF, 0xDB]); + system.load(0x7E8000, &[0xA9, 0x5A, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x005A); + assert_eq!(cpu.registers().pb(), 0x7E); + assert_eq!(cpu.registers().pc(), 0x8003); + } + + #[test] + fn jmp_indexed_x_indirect_uses_program_bank_and_wraps() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x5C, 0x00, 0x70, 0x7E]); + system.load(0x7E7000, &[0xA2, 0x81, 0x7C, 0xFF, 0xFF, 0xDB]); + system.load(0x7E0080, &[0x00, 0x80]); + system.load(0x7E8000, &[0xA9, 0x99, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x0099); + assert_eq!(cpu.registers().x(), 0x0081); + assert_eq!(cpu.registers().pb(), 0x7E); + assert_eq!(cpu.registers().pc(), 0x8003); + } + + #[test] + fn jsr_indexed_x_indirect_uses_program_bank_and_wraps() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x5C, 0x00, 0x70, 0x7E]); + system.load(0x7E7000, &[0xA2, 0x81, 0xFC, 0xFF, 0xFF, 0xDB]); + system.load(0x7E0080, &[0x00, 0x80]); + system.load(0x7E8000, &[0xA9, 0x5A, 0x60]); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x005A); + assert_eq!(cpu.registers().x(), 0x0081); + assert_eq!(cpu.registers().pb(), 0x7E); + assert_eq!(cpu.registers().pc(), 0x7006); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn emulation_mode_jsr_indexed_x_indirect_wraps_pushes_across_page_zero_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x5C, 0x00, 0x70, 0x7F]); + system.load(0x7F7000, &[0xFC, 0xFF, 0xFF]); + system.load(0x7FFFFF, &[0x00]); + system.load(0x7F0000, &[0x80]); + system.load(0x7F8000, &[0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().s(), 0x01FE); + assert_eq!(system.memory.get(&0x0000FF), Some(&0x02)); + assert_eq!(system.memory.get(&0x000100), Some(&0x70)); + } + + #[test] + fn emulation_mode_phd_wraps_pushes_across_page_zero_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x0B, 0xDB]); + + step_n(&mut cpu, &mut system, 7); + cpu.registers.d = 0x1357; + cpu.registers.s = 0x0100; + + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.registers().s(), 0x01FE); + assert_eq!(system.memory.get(&0x0000FF), Some(&0x57)); + assert_eq!(system.memory.get(&0x000100), Some(&0x13)); + } + + #[test] + fn mvn_copies_forward_across_bank_wrap() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x21]); + system.load(0x7E0000, &[0x22, 0x23, 0x24]); + system.load(0x7F0001, &[0x00, 0x99]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x03, 0x00, 0xA2, 0xFF, 0xFF, 0xA0, 0xFE, 0xFF, 0x54, + 0x7F, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 256); + + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().x(), 0x0003); + assert_eq!(cpu.registers().y(), 0x0002); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(system.memory.get(&0x7FFFFE), Some(&0x21)); + assert_eq!(system.memory.get(&0x7FFFFF), Some(&0x22)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x23)); + assert_eq!(system.memory.get(&0x7F0001), Some(&0x24)); + assert_eq!(system.memory.get(&0x7F0002), Some(&0x99)); + } + + #[test] + fn mvn_with_8bit_indexes_wraps_low_bytes() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7E00FF, &[0x51]); + system.load(0x7E0000, &[0x52, 0x53, 0x54]); + system.load(0x7F0001, &[0x00, 0x99]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x03, 0x00, 0xA2, 0xFF, 0x05, 0xA0, 0xFE, 0x05, 0xE2, + 0x10, 0x54, 0x7F, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 256); + + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().x(), 0x0003); + assert_eq!(cpu.registers().y(), 0x0002); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(system.memory.get(&0x7F00FE), Some(&0x51)); + assert_eq!(system.memory.get(&0x7F00FF), Some(&0x52)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x53)); + assert_eq!(system.memory.get(&0x7F0001), Some(&0x54)); + assert_eq!(system.memory.get(&0x7F0002), Some(&0x99)); + } + + #[test] + fn mvp_copies_backward_across_bank_wrap() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x21]); + system.load(0x7E0000, &[0x22, 0x23, 0x24]); + system.load(0x7F0001, &[0x00]); + system.load(0x7FFFFD, &[0x99]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x03, 0x00, 0xA2, 0x02, 0x00, 0xA0, 0x01, 0x00, 0x44, + 0x7F, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 256); + + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().x(), 0xFFFE); + assert_eq!(cpu.registers().y(), 0xFFFD); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(system.memory.get(&0x7FFFFE), Some(&0x21)); + assert_eq!(system.memory.get(&0x7FFFFF), Some(&0x22)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x23)); + assert_eq!(system.memory.get(&0x7F0001), Some(&0x24)); + assert_eq!(system.memory.get(&0x7FFFFD), Some(&0x99)); + } + + #[test] + fn mvp_with_8bit_indexes_wraps_low_bytes() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7E00FF, &[0x51]); + system.load(0x7E0000, &[0x52, 0x53, 0x54]); + system.load(0x7F0001, &[0x00, 0x99]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x03, 0x00, 0xA2, 0x02, 0x05, 0xA0, 0x01, 0x05, 0xE2, + 0x10, 0x44, 0x7F, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 256); + + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().x(), 0x00FE); + assert_eq!(cpu.registers().y(), 0x00FD); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(system.memory.get(&0x7F00FE), Some(&0x51)); + assert_eq!(system.memory.get(&0x7F00FF), Some(&0x52)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x53)); + assert_eq!(system.memory.get(&0x7F0001), Some(&0x54)); + assert_eq!(system.memory.get(&0x7F0002), Some(&0x99)); + } + + #[test] + fn stack_immediate_math_and_compare_primitives_match_bootstrap_needs() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x01, 0x85, 0x10, 0xA2, 0x02, 0x00, 0xCA, + 0xE4, 0x10, 0xD0, 0x0E, 0xA9, 0xB5, 0x48, 0x4A, 0x68, 0x29, 0x0F, 0x69, 0x03, 0xC9, + 0x09, 0x90, 0x01, 0xC8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x0009); + assert_eq!(cpu.registers().x(), 0x0001); + assert_eq!(cpu.registers().y(), 0x0001); + assert_eq!(cpu.registers().s(), 0x01FF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn bit_immediate_16bit_updates_only_zero_flag() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x77, 0x93, 0xE2, 0xC0, 0x89, 0x34, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x9377); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn bit_immediate_8bit_preserves_nv_and_sets_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x55, 0x00, 0xE2, 0xE0, 0x89, 0xAA, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0055); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn cpx_and_cpy_immediate_support_16bit_test_checks() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0x56, 0x34, 0xA0, 0x78, 0x56, 0xE0, 0x56, 0x34, 0xD0, + 0x02, 0xC0, 0x78, 0x56, 0xD0, 0x01, 0xC8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x3456); + assert_eq!(cpu.registers().y(), 0x5679); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x7F, 0x48, 0xAB, 0xC2, 0x20, 0xA9, 0xFF, + 0xFF, 0x5B, 0xA9, 0xCD, 0xAB, 0xA2, 0x91, 0xFF, 0xC2, 0xFF, 0xC1, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_stack_relative_reads_from_stack_window() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000201, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0xCD, 0xAB, 0xC2, 0xFF, 0xC3, + 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().s(), 0x01EF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FEC, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0xCD, 0xAB, 0xA0, 0x10, 0x11, 0xC2, 0xFF, 0xD3, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 176); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1110); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0xCD, 0xAB, 0xA2, 0x33, 0x01, + 0xC2, 0xFF, 0xD5, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xCD]); + system.load(0x7F0300, &[0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xCD, 0xAB, 0xA0, 0x00, 0x03, 0xC2, 0xFF, 0xD9, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cmp_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xCD]); + system.load(0x7F0300, &[0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xCD, 0xAB, 0xA2, 0x00, 0x03, 0xC2, 0xFF, 0xDF, 0xFF, + 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().a(), 0xABCD); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cpx_absolute_reads_from_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA2, 0xCD, 0xAB, 0xC2, 0xFF, 0xEC, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0xABCD); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cpy_direct_reads_wrapped_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA0, 0xCD, 0xAB, + 0xC2, 0xFF, 0xC4, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().y(), 0xABCD); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn cpy_absolute_reads_from_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0xCD, 0xAB]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA0, 0xCD, 0xAB, 0xC2, 0xFF, 0xCC, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().y(), 0xABCD); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dec_accumulator_16bit_updates_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x01, 0x00, 0x3A, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dec_accumulator_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x01, 0x12, 0xE2, 0x20, 0x3A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x1200); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dec_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x01, 0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0xD6, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dec_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x01]); + system.load(0x7F0300, &[0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0xA2, + 0x00, 0x03, 0xDE, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x00)); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn inc_direct_16bit_wraps_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xFF, 0xFF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xE6, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000033), Some(&0x00)); + assert_eq!(system.memory.get(&0x000034), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn inc_absolute_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0xFF]); + system.load(0x7F0000, &[0xFF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xEE, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn inc_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0xFF, 0xFF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA2, 0x33, 0x01, + 0xF6, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn inc_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xFF]); + system.load(0x7F0300, &[0xFF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA2, 0x00, 0x03, 0xFE, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dey_16bit_updates_flags() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x10, 0xA0, 0x00, 0x80, 0x88, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().y(), 0x7FFF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn dey_8bit_wraps_with_zero_extended_register() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x18, 0xFB, 0xA0, 0x00, 0x88, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().y(), 0x00FF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x7F, 0x48, 0xAB, 0xC2, 0x20, 0xA9, 0xFF, + 0xFF, 0x5B, 0xA9, 0x12, 0x11, 0xA2, 0x91, 0xFF, 0xE2, 0x20, 0x38, 0x61, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indexed_indirect_emulation_wraps_pointer_high_within_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0x34]); + system.load(0x000100, &[0x12]); + system.load(0x7F1234, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xA2, 0xEF, 0x9A, 0xA9, 0x7F, 0x48, 0xAB, 0xC2, 0x30, 0xA9, 0x00, 0x01, + 0x5B, 0xA9, 0x12, 0x11, 0xA2, 0x10, 0x00, 0xA0, 0x78, 0x56, 0x38, 0xFB, 0xC2, 0xDE, + 0xE2, 0x21, 0x61, 0xEF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 192); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().x(), 0x0010); + assert_eq!(cpu.registers().y(), 0x0078); + assert_eq!(cpu.registers().d(), 0x0100); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indexed_indirect_emulation_wraps_low_pointer_with_zero_direct_page_low() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000100, &[0x34, 0x12]); + system.load(0x7F1234, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xA2, 0xEF, 0x9A, 0xA9, 0x7F, 0x48, 0xAB, 0xC2, 0x30, 0xA9, 0x00, 0x01, + 0x5B, 0xA9, 0x12, 0x11, 0xA2, 0x10, 0x00, 0xA0, 0x78, 0x56, 0x38, 0xFB, 0xC2, 0xDE, + 0xE2, 0x21, 0x61, 0xF0, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 192); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().x(), 0x0010); + assert_eq!(cpu.registers().y(), 0x0078); + assert_eq!(cpu.registers().d(), 0x0100); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indexed_indirect_emulation_wraps_pointer_high_for_nonzero_direct_page_low() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0002FF, &[0x34]); + system.load(0x000200, &[0x12]); + system.load(0x7F1234, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xA9, 0x7F, 0x48, 0xAB, 0xC2, 0x30, 0xA9, 0x1A, 0x01, 0x5B, 0xA9, 0x12, + 0x11, 0xA2, 0xEE, 0x00, 0xA0, 0x78, 0x56, 0x38, 0xFB, 0xC2, 0xDE, 0xE2, 0x21, 0x61, + 0xF7, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 192); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().x(), 0x00EE); + assert_eq!(cpu.registers().y(), 0x0078); + assert_eq!(cpu.registers().d(), 0x011A); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_stack_relative_reads_from_stack_window() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000201, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x12, 0x11, 0xE2, 0x20, 0x38, + 0x63, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().s(), 0x01EF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_reads_from_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x12, 0x11, 0xE2, 0x20, 0x38, 0x65, 0x33, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn lda_direct_reads_from_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xED]); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA5, 0x33, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x00ED); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_immediate_16bit_updates_negative_flag() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x00, 0x80, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().a(), 0x8000); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldx_and_ldy_immediate_8bit_update_zero_flag() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xA2, 0x00, 0xA0, 0x00, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().x(), 0x0000); + assert_eq!(cpu.registers().y(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn lda_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA2, 0x91, 0xFF, 0xA1, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_stack_relative_reads_from_stack_window() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000201, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x34, 0x12, 0xA3, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().s(), 0x01EF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_direct_indirect_long_reads_full_24bit_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12, 0x7F]); + system.load(0x7F1234, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA7, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_direct_indirect_reads_via_data_bank_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12]); + system.load(0x7F1234, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xB2, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_direct_indirect_indexed_y_applies_y_offset_in_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA0, 0x00, 0x11, 0xB1, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0x34, 0x12, 0xA0, 0x00, 0x11, 0xB3, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA0, 0x00, 0x11, + 0xB7, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA0, 0x00, 0x03, 0xB9, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lda_absolute_indexed_x_and_long_indexed_x_carry_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA2, 0x00, 0x03, 0xBD, 0xFF, 0xFF, 0xBF, 0xFF, 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldx_absolute_reads_from_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xAE, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldx_direct_indexed_y_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA0, 0x33, 0x01, + 0xB6, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().y(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldx_direct_indexed_y_wraps_in_emulation_when_direct_page_low_is_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000133, &[0x56]); + system.load(0x000233, &[0xA9]); + system.load( + 0x008000, + &[0xA9, 0x01, 0xEB, 0x5B, 0xA0, 0x34, 0xB6, 0xFF, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().x(), 0x0056); + assert_eq!(cpu.registers().y(), 0x0034); + assert_eq!(cpu.registers().d(), 0x0100); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldx_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA0, 0x00, 0x03, 0xBE, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().y(), 0x0300); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldy_absolute_reads_from_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xAC, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldy_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA2, 0x33, 0x01, + 0xB4, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ldy_absolute_indexed_x_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA2, 0x00, 0x03, 0xBC, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().x(), 0x0300); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_absolute_and_absolute_long_read_memory_operands() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xED]); + system.load(0x7EFFFF, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x12, 0x11, 0xE2, 0x20, 0x38, 0x6D, 0x33, 0x00, 0xC2, + 0x20, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, 0x12, 0x11, 0xE2, + 0x20, 0x38, 0x6F, 0xFF, 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indexed_x_uses_direct_page_wrap_and_index() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0xCB, 0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x34, 0x12, 0xA2, 0x33, 0x01, + 0x38, 0x75, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_direct_indexed_x_wraps_in_emulation_when_direct_page_low_is_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000133, &[0x21]); + system.load(0x000233, &[0x80]); + system.load( + 0x008000, + &[ + 0xA9, 0x01, 0xEB, 0x5B, 0xA2, 0x34, 0xA9, 0x12, 0x18, 0x75, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x0133); + assert_eq!(cpu.registers().x(), 0x0034); + assert_eq!(cpu.registers().d(), 0x0100); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xCB, 0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA0, 0x00, 0x03, 0x38, 0x79, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_absolute_indexed_x_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xCB, 0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x34, 0x12, 0xA2, 0x00, 0x03, 0x38, 0x7D, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xCB, 0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x34, 0x12, 0xA2, 0x00, 0x03, 0x38, 0x7F, 0xFF, 0xFF, + 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn and_direct_indexed_indirect_uses_direct_page_pointer_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0xFF, 0xFE, 0xA2, 0x91, 0xFF, 0x21, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0xEE5C); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn and_direct_indexed_x_uses_direct_page_wrap_and_index() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0xFF, 0xFE, 0xA2, 0x33, 0x01, + 0x35, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0xEE5C); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn and_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFE, 0xA0, 0x00, 0x03, 0x39, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0xEE5C); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn and_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFE, 0xA2, 0x00, 0x03, 0x3F, 0xFF, 0xFF, 0x7E, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0xEE5C); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_immediate_16bit_updates_negative() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFE, 0x49, 0x8C, 0x6F, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x9173); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_immediate_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xF0, 0x12, 0xE2, 0x20, 0x49, 0xAA, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x125A); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0xFF, 0xFE, 0xA2, 0x91, 0xFF, 0x41, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x11A3); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0xFF, 0xFE, 0xA0, 0x00, 0x11, 0x53, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x11A3); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0xFF, 0xFE, 0xA0, 0x00, 0x11, + 0x57, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x11A3); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFE, 0xA0, 0x00, 0x03, 0x59, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x11A3); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn eor_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFE, 0xA2, 0x00, 0x03, 0x5F, 0xFF, 0xFF, 0x7E, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x11A3); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_immediate_16bit_updates_negative() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x00, 0x7F, 0x09, 0x5C, 0x80, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xFF5C); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_immediate_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x50, 0x12, 0xE2, 0x20, 0x09, 0x0A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x125A); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0xFF, 0xFE, 0xA2, 0x91, 0xFF, 0x01, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_direct_indexed_x_uses_direct_page_wrap_and_index() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x03, 0x10, 0xA2, 0x33, 0x01, + 0x15, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0xFF5F); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0x00, 0x7F, 0xA0, 0x00, 0x11, 0x13, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0xFF5C); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x03, 0x10, 0xA0, 0x00, 0x11, + 0x17, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0xFF5F); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x00, 0x7F, 0xA0, 0x00, 0x03, 0x19, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0xFF5C); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ora_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x5C, 0xEF]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0xA2, 0x00, 0x03, 0xA9, 0x03, 0x10, 0x1F, + 0xFF, 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0xFF5F); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn adc_decimal_immediate_16bit_sets_carry_and_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xF8, 0xA9, 0x34, 0x12, 0x38, 0x69, 0x65, 0x87, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn adc_decimal_immediate_16bit_sets_overflow_and_negative() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xF8, 0xA9, 0x50, 0x35, 0x18, 0x69, 0x70, 0x44, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x8020); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn adc_decimal_immediate_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x12, 0xCC, 0xE2, 0x20, 0xF8, 0x38, 0x69, 0x87, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xCC00); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_immediate_16bit_sets_carry_and_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x90, 0x90, 0xE9, 0x90, 0x90, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_immediate_16bit_sets_overflow_and_negative() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0x18, 0xC2, 0x20, 0xA9, 0x00, 0x70, 0xE9, 0x00, 0xA0, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xCFFF); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_decimal_immediate_16bit_sets_carry_and_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xF8, 0x18, 0xA9, 0x90, 0x90, 0xE9, 0x89, 0x90, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_decimal_immediate_16bit_sets_overflow_without_carry() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xF8, 0x38, 0xA9, 0x00, 0x10, 0xE9, 0x00, 0x90, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x2000); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_decimal_immediate_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x90, 0xCC, 0xE2, 0x20, 0xF8, 0x18, 0xE9, 0x89, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xCC00); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + } + + #[test] + fn sbc_immediate_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x90, 0xCC, 0xE2, 0x20, 0xE9, 0x90, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xCC00); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn sbc_direct_indexed_x_uses_direct_page_wrap_and_index() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x90, 0x90, 0xA2, 0x33, 0x01, + 0xF5, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sbc_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x90, 0x90, 0xA2, 0x91, 0xFF, 0xE1, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sbc_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0x90, 0x90, 0xA0, 0x00, 0x11, 0xF3, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sbc_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x90, 0x90, 0xA0, 0x00, 0x11, + 0xF7, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sbc_absolute_and_absolute_long_read_memory_operands() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x90, 0x90]); + system.load(0x7EFFFF, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x90, 0x90, 0xED, 0x33, 0x00, 0xA9, 0x90, 0x90, 0xEF, + 0xFF, 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn sbc_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x90, 0x90, 0xA0, 0x00, 0x03, 0xF9, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sbc_absolute_long_indexed_x_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x90, 0x90]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x90, 0x90, 0xA2, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0x7E, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x0000); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn sta_direct_indexed_indirect_uses_direct_page_and_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x00FFA0, &[0x12, 0x12]); + system.load(0x7F1212, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0xA2, 0x91, 0xFF, 0x81, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().x(), 0xFF91); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x7F1212), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F1213), Some(&0x80)); + } + + #[test] + fn sta_stack_relative_writes_stack_window() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000201, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x00, 0x80, 0x83, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(system.memory.get(&0x000201), Some(&0x00)); + assert_eq!(system.memory.get(&0x000202), Some(&0x80)); + } + + #[test] + fn sta_stack_relative_wraps_high_byte_at_zero_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xED, 0xFF, 0x9A, 0xA9, 0x00, 0x80, 0x83, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().s(), 0xFFED); + assert_eq!(system.memory.get(&0x00FFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x000000), Some(&0x80)); + } + + #[test] + fn sta_direct_writes_wrapped_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0x85, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x000033), Some(&0x00)); + assert_eq!(system.memory.get(&0x000034), Some(&0x80)); + } + + #[test] + fn sta_direct_wraps_high_byte_at_zero_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0x85, 0x00, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x00FFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x000000), Some(&0x80)); + } + + #[test] + fn sta_direct_indirect_long_writes_full_24bit_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12, 0x7F]); + system.load(0x7F1234, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0x87, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x7F1234), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F1235), Some(&0x80)); + } + + #[test] + fn sta_absolute_and_absolute_long_write_expected_bytes() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F1234, &[0x34, 0x12]); + system.load(0x7EFFFF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x00, 0x80, 0x8D, 0x34, 0x12, 0x8F, 0xFF, 0xFF, 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(system.memory.get(&0x7F1234), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F1235), Some(&0x80)); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x80)); + } + + #[test] + fn sta_direct_indirect_indexed_y_writes_with_data_bank_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0xA0, 0x00, 0x11, 0x91, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().y(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(system.memory.get(&0x7F0FDC), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0FDD), Some(&0x80)); + } + + #[test] + fn sta_direct_indirect_writes_via_data_bank_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12]); + system.load(0x7F1234, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0x92, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x7F1234), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F1235), Some(&0x80)); + } + + #[test] + fn sta_stack_relative_indirect_indexed_y_writes_using_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0x00, 0x80, 0xA0, 0x00, 0x11, 0x93, 0x10, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(system.memory.get(&0x7F0FDC), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0FDD), Some(&0x80)); + } + + #[test] + fn sta_direct_indexed_x_writes_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0xA2, 0x33, 0x01, + 0x95, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x80)); + } + + #[test] + fn sta_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x00, 0x80, 0xA0, 0x00, 0x11, + 0x97, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().y(), 0x1100); + assert_eq!(system.memory.get(&0x7F0FDC), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0FDD), Some(&0x80)); + } + + #[test] + fn sta_absolute_indexed_y_carries_into_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x00, 0x80, 0xA0, 0x00, 0x03, 0x99, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x0300); + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x80)); + } + + #[test] + fn sta_absolute_indexed_x_and_long_indexed_x_carry_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x34, 0x12]); + system.load(0x7F01FF, &[0x78, 0x56]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x00, 0x80, 0xA2, 0x00, 0x03, 0x9D, 0xFF, 0xFF, 0xA9, 0x34, 0x12, 0x9F, 0xFF, 0xFE, + 0x7E, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x80)); + assert_eq!(system.memory.get(&0x7F01FF), Some(&0x34)); + assert_eq!(system.memory.get(&0x7F0200), Some(&0x12)); + } + + #[test] + fn stx_direct_indexed_y_writes_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x00, 0x80, 0xA0, 0x33, 0x01, + 0x96, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().y(), 0x0133); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x80)); + } + + #[test] + fn stx_direct_indexed_y_wraps_high_byte_at_zero_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x00, 0x80, 0xA0, 0x00, 0x00, + 0x96, 0x00, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().y(), 0x0000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x00FFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x000000), Some(&0x80)); + } + + #[test] + fn stx_absolute_writes_across_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA2, + 0x00, 0x80, 0x8E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x80)); + } + + #[test] + fn sty_direct_indexed_x_writes_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA0, 0x00, 0x80, 0xA2, 0x33, 0x01, + 0x94, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x80)); + } + + #[test] + fn sty_direct_indexed_x_wraps_high_byte_at_zero_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA0, 0x00, 0x80, 0xA2, 0x00, 0x00, + 0x94, 0x00, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x0000); + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x00FFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x000000), Some(&0x80)); + } + + #[test] + fn sty_absolute_writes_across_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA0, + 0x00, 0x80, 0x8C, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().y(), 0x8000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x80)); + } + + #[test] + fn stz_direct_wraps_high_byte_at_zero_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0x64, 0x00, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x00FFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x000000), Some(&0x00)); + } + + #[test] + fn stz_direct_indexed_x_8bit_wraps_and_clears_one_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x12, 0x34]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x32, 0x12, 0xE2, 0x30, 0x74, + 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().x(), 0x0032); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(system.memory.get(&0x000033), Some(&0x00)); + assert_eq!(system.memory.get(&0x000034), Some(&0x34)); + } + + #[test] + fn stz_absolute_writes_zero_across_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0x9C, + 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x00)); + } + + #[test] + fn stz_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x34, 0x12]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA2, + 0x00, 0x03, 0x9E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x00)); + } + + #[test] + fn trb_direct_16bit_clears_bits_and_zero_clear() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x92]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x30, 0x16, 0x14, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x1630); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x000033), Some(&0x04)); + assert_eq!(system.memory.get(&0x000034), Some(&0x80)); + } + + #[test] + fn trb_absolute_16bit_sets_zero_when_no_bits_overlap() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0xAA, 0xAA]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x55, 0x55, 0x1C, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0xAA)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0xAA)); + } + + #[test] + fn trb_direct_8bit_clears_bits_and_zero_clear() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x92]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xE2, 0x20, 0xA9, 0x16, 0x14, 0x34, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x000033), Some(&0x80)); + } + + #[test] + fn tsb_direct_16bit_sets_bits_and_zero_clear() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x92]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x30, 0x16, 0x04, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x1630); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x000033), Some(&0x34)); + assert_eq!(system.memory.get(&0x000034), Some(&0x96)); + } + + #[test] + fn tsb_absolute_16bit_sets_zero_when_no_bits_overlap_and_ors_bits() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0xAA, 0xAA]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0x55, 0x55, 0x0C, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0xFF)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0xFF)); + } + + #[test] + fn tsb_direct_8bit_sets_bits_and_zero_clear() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x92]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xE2, 0x20, 0xA9, 0x16, 0x04, 0x34, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert_eq!(system.memory.get(&0x000033), Some(&0x96)); + } + + #[test] + fn adc_direct_indirect_long_reads_full_24bit_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12, 0x7F]); + system.load(0x7F1234, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x12, 0x11, 0xE2, 0x20, 0x38, + 0x67, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indirect_reads_via_data_bank_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x12]); + system.load(0x7F1234, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7F, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x12, 0x11, 0xE2, 0x20, 0x38, 0x72, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7F); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indirect_indexed_y_applies_y_offset_in_data_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x20, 0xA9, + 0xFF, 0xFF, 0x5B, 0xA9, 0x12, 0x11, 0xA0, 0x00, 0x11, 0xE2, 0x20, 0x38, 0x71, 0x34, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_stack_relative_indirect_indexed_y_uses_stack_pointer_and_offset() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x0001FF, &[0xDC, 0xFE]); + system.load(0x7F0FDC, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, + 0xAB, 0xC2, 0x20, 0xA9, 0x12, 0x11, 0xA0, 0x00, 0x11, 0xE2, 0x20, 0x38, 0x73, 0x10, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().s(), 0x01EF); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn adc_direct_indirect_long_indexed_y_carries_into_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xDC, 0xFE, 0x7E]); + system.load(0x7F0FDC, &[0xED]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x12, 0x11, 0xA0, 0x00, 0x11, + 0xE2, 0x20, 0x38, 0x77, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(cpu.registers().a(), 0x1100); + assert_eq!(cpu.registers().y(), 0x1100); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn wdm_immediate_is_a_two_byte_nop() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x31, 0xA9, 0x34, 0x12, 0xA2, 0x56, 0x34, 0xA0, 0x78, 0x56, 0x42, + 0xAB, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x1234); + assert_eq!(cpu.registers().x(), 0x3456); + assert_eq!(cpu.registers().y(), 0x5678); + assert_eq!(cpu.registers().status().bits(), 0x04); + } + + #[test] + fn pea_pushes_immediate_word_onto_stack() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x18, 0xFB, 0xC2, 0x31, 0xF4, 0xCD, 0xAB, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().s(), 0x01FD); + assert_eq!(system.memory.get(&0x0001FE), Some(&0xCD)); + assert_eq!(system.memory.get(&0x0001FF), Some(&0xAB)); + } + + #[test] + fn pei_pushes_direct_indirect_word_from_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x65, 0x87]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x31, 0xA9, 0xFF, 0xFF, 0x5B, 0xD4, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().d(), 0xFFFF); + assert_eq!(cpu.registers().s(), 0x01FD); + assert_eq!(system.memory.get(&0x0001FE), Some(&0x65)); + assert_eq!(system.memory.get(&0x0001FF), Some(&0x87)); + } + + #[test] + fn per_pushes_signed_target_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x18, 0xFB, 0xC2, 0x31, 0x62, 0xFD, 0xFF, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 48); + + assert_eq!(cpu.registers().s(), 0x01FD); + assert_eq!(system.memory.get(&0x0001FE), Some(&0x04)); + assert_eq!(system.memory.get(&0x0001FF), Some(&0x80)); + } + + #[test] + fn phy_and_ply_round_trip_16bit_y() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x31, 0xA0, 0xDC, 0xFE, 0x5A, 0xA0, 0x00, 0x00, 0x7A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().y(), 0xFEDC); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn phk_pushes_program_bank_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x18, 0xFB, 0xC2, 0x31, 0x5C, 0x00, 0x80, 0x7E]); + system.load(0x7E8000, &[0xE2, 0x20, 0x4B, 0x68, 0xDB]); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().pb(), 0x7E); + assert_eq!(cpu.registers().a(), 0x007E); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn pld_pulls_direct_register_and_updates_flags() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x31, 0xF4, 0x53, 0x97, 0x2B, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().d(), 0x9753); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn plp_restores_status_and_truncates_index_registers() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x31, 0xA2, 0x56, 0x34, 0xA0, 0x78, 0x56, 0xA9, 0x10, 0x00, 0xE2, + 0x20, 0x48, 0xC2, 0x20, 0x28, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().status().bits(), 0x10); + assert_eq!(cpu.registers().x(), 0x0056); + assert_eq!(cpu.registers().y(), 0x0078); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn php_and_phx_round_trip_status_and_index_values() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0x34, 0x12, 0xE2, 0x20, 0x08, 0x68, 0x85, 0x10, 0xC2, + 0x20, 0xDA, 0xFA, 0x86, 0x12, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x0010), Some(&0x25)); + assert_eq!(system.memory.get(&0x0012), Some(&0x34)); + assert_eq!(system.memory.get(&0x0013), Some(&0x12)); + assert_eq!(cpu.registers().x(), 0x1234); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn save_results_style_stack_and_transfer_ops_capture_state() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7E0000, &[0x9A, 0xBC]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x55, 0x44, 0xA2, 0x34, 0x12, 0xA0, 0x78, 0x56, 0x0B, + 0x48, 0xA9, 0x00, 0x00, 0x5B, 0x68, 0x85, 0x12, 0x86, 0x14, 0x84, 0x16, 0xFA, 0x86, + 0x1C, 0x3B, 0x1A, 0x1A, 0x1A, 0x85, 0x1A, 0xE2, 0x20, 0x8B, 0x68, 0x85, 0x1E, 0xA9, + 0x7E, 0x48, 0xAB, 0xC2, 0x20, 0xAF, 0x00, 0x00, 0x7E, 0xA6, 0x1C, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 160); + + assert_eq!(system.memory.get(&0x0012), Some(&0x55)); + assert_eq!(system.memory.get(&0x0013), Some(&0x44)); + assert_eq!(system.memory.get(&0x0014), Some(&0x34)); + assert_eq!(system.memory.get(&0x0015), Some(&0x12)); + assert_eq!(system.memory.get(&0x0016), Some(&0x78)); + assert_eq!(system.memory.get(&0x0017), Some(&0x56)); + assert_eq!(system.memory.get(&0x001A), Some(&0x02)); + assert_eq!(system.memory.get(&0x001B), Some(&0x02)); + assert_eq!(system.memory.get(&0x001C), Some(&0x00)); + assert_eq!(system.memory.get(&0x001D), Some(&0x00)); + assert_eq!(system.memory.get(&0x001E), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0xBC9A); + assert_eq!(cpu.registers().d(), 0x0000); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0000); + assert_eq!(cpu.registers().s(), 0x01FF); + } + + #[test] + fn asl_accumulator_16bit_sets_carry_and_zero() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x00, 0x80, 0x0A, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn asl_accumulator_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x34, 0x12, 0xE2, 0x20, 0xA9, 0x81, 0x0A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x1202); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn asl_direct_16bit_wraps_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFF, 0x5B, 0x06, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(system.memory.get(&0x000033), Some(&0x00)); + assert_eq!(system.memory.get(&0x000034), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn asl_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0x16, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn asl_absolute_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x00]); + system.load(0x7F0000, &[0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0x0E, + 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x00)); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn rol_accumulator_16bit_rotates_carry_in_and_out() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x00, 0x80, 0x38, 0x2A, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0001); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn rol_accumulator_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x34, 0x12, 0xE2, 0x20, 0xA9, 0x80, 0x18, 0x2A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x1200); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn rol_direct_16bit_wraps_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x11, 0x41]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFF, 0x5B, 0x38, 0x26, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(system.memory.get(&0x000033), Some(&0x23)); + assert_eq!(system.memory.get(&0x000034), Some(&0x82)); + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn rol_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x00, 0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0x38, 0x36, 0x02, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x01)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn rol_absolute_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x11]); + system.load(0x7F0000, &[0x41]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0x38, + 0x2E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x23)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x82)); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn rol_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x00]); + system.load(0x7F0300, &[0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0xA2, + 0x00, 0x03, 0x18, 0x3E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x00)); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ror_accumulator_16bit_rotates_carry_in_and_out() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x01, 0x00, 0x38, 0x6A, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x8000); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn ror_accumulator_8bit_preserves_high_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x34, 0x12, 0xE2, 0x20, 0xA9, 0x01, 0x18, 0x6A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x1200); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn ror_direct_16bit_wraps_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x22, 0x42]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFF, 0x5B, 0x38, 0x66, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(system.memory.get(&0x000033), Some(&0x11)); + assert_eq!(system.memory.get(&0x000034), Some(&0xA1)); + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn ror_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x01, 0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0x18, 0x76, 0x02, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x00)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn ror_absolute_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x22]); + system.load(0x7F0000, &[0x42]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0x38, + 0x6E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x11)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0xA1)); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(!cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn ror_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x01]); + system.load(0x7F0300, &[0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0xA2, + 0x00, 0x03, 0x18, 0x7E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x00)); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn lsr_direct_16bit_wraps_direct_page() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x01, 0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFF, 0x5B, 0x46, 0x34, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(system.memory.get(&0x000033), Some(&0x00)); + assert_eq!(system.memory.get(&0x000034), Some(&0x00)); + assert_eq!(cpu.registers().a(), 0xFFFF); + assert_eq!(cpu.registers().d(), 0xFFFF); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn lsr_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0x03, 0x00]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0x56, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(system.memory.get(&0x000134), Some(&0x01)); + assert_eq!(system.memory.get(&0x000135), Some(&0x00)); + assert_eq!(cpu.registers().x(), 0x0133); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn lsr_absolute_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7EFFFF, &[0x01]); + system.load(0x7F0000, &[0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0x4E, + 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7EFFFF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0000), Some(&0x40)); + assert_eq!(cpu.registers().db(), 0x7E); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn lsr_absolute_indexed_x_carries_into_next_bank() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0x01]); + system.load(0x7F0300, &[0x80]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0xA2, + 0x00, 0x03, 0x5E, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 128); + + assert_eq!(system.memory.get(&0x7F02FF), Some(&0x00)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0x40)); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + } + + #[test] + fn bit_direct_16bit_updates_flags_without_writing_memory() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0x34, 0x52]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0xFF, 0xFF, 0x5B, 0xA9, 0x77, 0x93, 0x38, 0x24, 0x34, + 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x9377); + assert_eq!(system.memory.get(&0x000033), Some(&0x34)); + assert_eq!(system.memory.get(&0x000034), Some(&0x52)); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn bit_direct_8bit_uses_low_byte_for_n_and_v() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000033, &[0xC0]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x20, 0xA9, 0x40, 0x12, 0xE2, 0x20, 0x38, 0x24, 0x33, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x1240); + assert_eq!(system.memory.get(&0x000033), Some(&0xC0)); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::OVERFLOW)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn bit_direct_indexed_x_uses_wrapped_direct_page_address() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x000134, &[0xAA, 0xAA]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xFF, 0xFF, 0x5B, 0xA2, 0x33, 0x01, 0xA9, 0x55, 0x55, + 0x38, 0x34, 0x02, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 112); + + assert_eq!(cpu.registers().a(), 0x5555); + assert_eq!(cpu.registers().x(), 0x0133); + assert_eq!(system.memory.get(&0x000134), Some(&0xAA)); + assert_eq!(system.memory.get(&0x000135), Some(&0xAA)); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn bit_absolute_indexed_x_reads_across_bank_boundary() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x7F02FF, &[0xAA]); + system.load(0x7F0300, &[0xAA]); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x7E, 0x00, 0xE2, 0x20, 0x48, 0xAB, 0xC2, 0x30, 0xA2, + 0x00, 0x03, 0xA9, 0x55, 0x55, 0x38, 0x3C, 0xFF, 0xFF, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 144); + + assert_eq!(cpu.registers().a(), 0x5555); + assert_eq!(cpu.registers().db(), 0x7E); + assert_eq!(cpu.registers().x(), 0x0300); + assert_eq!(system.memory.get(&0x7F02FF), Some(&0xAA)); + assert_eq!(system.memory.get(&0x7F0300), Some(&0xAA)); + assert!(cpu.registers().status().contains(CpuStatus::CARRY)); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::OVERFLOW)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tax_transfers_full_accumulator_to_x_in_16bit_mode() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x65, 0x87, 0xAA, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x8765); + assert_eq!(cpu.registers().x(), 0x8765); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tay_truncates_to_low_byte_when_index_registers_are_8bit() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xAB, 0x87, 0xE2, 0x10, 0xA8, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x87AB); + assert_eq!(cpu.registers().y(), 0x00AB); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn txa_zero_extends_8bit_x_into_16bit_accumulator() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xCD, 0xAB, 0xE2, 0x10, 0x8A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x00CD); + assert_eq!(cpu.registers().x(), 0x00CD); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn txa_preserves_accumulator_high_byte_in_8bit_mode() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x34, 0x12, 0xA2, 0xCD, 0xAB, 0xE2, 0x20, 0x8A, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x12CD); + assert_eq!(cpu.registers().x(), 0xABCD); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tya_preserves_accumulator_high_byte_in_8bit_mode() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x78, 0x56, 0xA0, 0xEF, 0xCD, 0xE2, 0x20, 0x98, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().a(), 0x56EF); + assert_eq!(cpu.registers().y(), 0xCDEF); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn txy_follows_index_width() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0x98, 0xFE, 0xE2, 0x10, 0x9B, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().x(), 0x0098); + assert_eq!(cpu.registers().y(), 0x0098); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tyx_follows_index_width() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA0, 0x00, 0x00, 0xE2, 0x10, 0xBB, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().x(), 0x0000); + assert_eq!(cpu.registers().y(), 0x0000); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tsx_loads_stack_pointer_using_index_width() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA2, 0x00, 0x02, 0x9A, 0xE2, 0x10, 0xBA, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 80); + + assert_eq!(cpu.registers().s(), 0x0200); + assert_eq!(cpu.registers().x(), 0x0000); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn tcs_transfers_full_accumulator_to_stack_pointer() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x00, 0x02, 0xE2, 0x20, 0x1B, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x0200); + assert_eq!(cpu.registers().s(), 0x0200); + } + + #[test] + fn tsc_and_tdc_transfer_full_16bit_values_even_when_accumulator_is_8bit() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[ + 0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x00, 0x02, 0x1B, 0xA9, 0x76, 0x98, 0x5B, 0xE2, 0x20, + 0x3B, 0x7B, 0xDB, + ], + ); + + run_until_stopped(&mut cpu, &mut system, 96); + + assert_eq!(cpu.registers().a(), 0x9876); + assert_eq!(cpu.registers().d(), 0x9876); + assert_eq!(cpu.registers().s(), 0x0200); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn xba_swaps_accumulator_bytes_and_sets_negative_from_new_low_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xA9, 0x12, 0x98, 0xEB, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0x1298); + assert!(cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(!cpu.registers().status().contains(CpuStatus::ZERO)); + } + + #[test] + fn xba_sets_zero_from_new_low_byte() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load( + 0x008000, + &[0x18, 0xFB, 0xC2, 0x30, 0xA9, 0xAA, 0x00, 0xEB, 0xDB], + ); + + run_until_stopped(&mut cpu, &mut system, 64); + + assert_eq!(cpu.registers().a(), 0xAA00); + assert!(!cpu.registers().status().contains(CpuStatus::NEGATIVE)); + assert!(cpu.registers().status().contains(CpuStatus::ZERO)); + } + + // ----------------------------------------------------------------------- + // WAI + NMI tests + // ----------------------------------------------------------------------- + + #[test] + fn wai_enters_waiting_state_and_burns_cycles_without_nmi() { + // WAI at reset PC; no NMI is ever raised. + // CPU should stay in Waiting state indefinitely. + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xCB]); // WAI + + // 7-cycle reset + step_n(&mut cpu, &mut system, 7); + assert_eq!(cpu.current_state(), CpuState::Running); + + // fetch WAI (1 cycle) + cpu.step(&mut system); + assert_eq!(cpu.current_state(), CpuState::Running); + + // execute WAI (1 cycle) → enters Waiting + cpu.step(&mut system); + assert_eq!(cpu.current_state(), CpuState::Waiting); + + // Extra idle cycles keep the CPU in Waiting with no NMI + step_n(&mut cpu, &mut system, 10); + assert_eq!(cpu.current_state(), CpuState::Waiting); + } + + #[test] + fn wai_resumes_on_nmi_and_pushes_correct_return_address_native_mode() { + // Native-mode program: + // CLC / XCE / REP #$30 – switch to native, 16-bit A/X/Y + // WAI – suspend; return address will be $8005 + // STP – code after WAI (never reached in this test) + // + // NMI handler at $9000: + // STP – we stop there to inspect state + // + // Assert that after NMI is taken: + // - PC = $9001 (one past STP), PB = $00 + // - stack contains the saved PB, return_addr_high, return_addr_low, P + + let nmi_handler_addr: u16 = 0x9000; + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + // Switch to native / 16-bit, then WAI at $8004, STP at $8005 + system.load(0x008000, &[0x18, 0xFB, 0xC2, 0x30, 0xCB, 0xDB]); + system.load_native_nmi_vector(nmi_handler_addr); + system.load(0x009000, &[0xDB]); // NMI handler: STP + + // Reset (7 cycles) + step_n(&mut cpu, &mut system, 7); + + // Run until WAI is executing idle cycles (state = Waiting) + for _ in 0..50 { + cpu.step(&mut system); + if cpu.current_state() == CpuState::Waiting { + break; + } + } + assert_eq!(cpu.current_state(), CpuState::Waiting); + // PC should point to the instruction AFTER WAI ($8005) + assert_eq!(cpu.registers().pc(), 0x8005); + + // Raise NMI on the next poll + system.nmi_pending = true; + + // Run through the full NMI exception sequence + STP handler + run_until_stopped(&mut cpu, &mut system, 20); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + // PB is zeroed on exception; PC is one past the STP in NMI handler + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9001); + + // Stack: the exception pushed PB($00), return_addr_high($80), return_addr_low($05), P + // Stack pointer started at $01FF; after 4 pushes it's at $01FB. + // Verify the return address bytes that were pushed. + assert_eq!(system.memory[&0x0001FF], 0x00); // PB + assert_eq!(system.memory[&0x0001FE], 0x80); // return addr high ($8005 → $80, $05) + assert_eq!(system.memory[&0x0001FD], 0x05); // return addr low + // $01FC = P (status flags) – value depends on state; just confirm it exists + assert!(system.memory.contains_key(&0x0001FC)); + } + + #[test] + fn wai_wakes_on_masked_irq_without_vectoring() { + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xCB, 0xDB]); // WAI, STP + + step_n(&mut cpu, &mut system, 7); + for _ in 0..50 { + cpu.step(&mut system); + if cpu.current_state() == CpuState::Waiting { + break; + } + } + assert_eq!(cpu.current_state(), CpuState::Waiting); + assert_eq!(cpu.registers().pc(), 0x8001); + + system.irq_pending = true; + run_until_stopped(&mut cpu, &mut system, 8); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.current_opcode(), 0xDB); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x8002); + assert!(system.irq_pending); + assert!(!system.memory.contains_key(&0x0001FF)); + } + + #[test] + fn wai_vectors_on_irq_when_interrupts_are_enabled() { + let irq_handler_addr: u16 = 0x9000; + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0x58, 0xCB, 0xDB]); // CLI, WAI, STP + system.load_emulation_irq_vector(irq_handler_addr); + system.load(0x009000, &[0xDB]); // STP + + step_n(&mut cpu, &mut system, 7); + for _ in 0..50 { + cpu.step(&mut system); + if cpu.current_state() == CpuState::Waiting { + break; + } + } + assert_eq!(cpu.current_state(), CpuState::Waiting); + assert_eq!(cpu.registers().pc(), 0x8002); + + system.irq_pending = true; + run_until_stopped(&mut cpu, &mut system, 32); + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9001); + assert_eq!(system.memory[&0x0001FF], 0x80); + assert_eq!(system.memory[&0x0001FE], 0x02); + } + + #[test] + fn masked_wai_irq_is_taken_after_cli_on_next_fetch_boundary() { + let irq_handler_addr: u16 = 0x9000; + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xCB, 0x58, 0xDB]); // WAI, CLI, STP + system.load_emulation_irq_vector(irq_handler_addr); + system.load(0x009000, &[0xDB]); // STP + + step_n(&mut cpu, &mut system, 7); + for _ in 0..50 { + cpu.step(&mut system); + if cpu.current_state() == CpuState::Waiting { + break; + } + } + assert_eq!(cpu.current_state(), CpuState::Waiting); + assert_eq!(cpu.registers().pc(), 0x8001); + + system.irq_pending = true; + run_until_stopped(&mut cpu, &mut system, 32); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9001); + assert_eq!(system.memory[&0x0001FF], 0x80); + assert_eq!(system.memory[&0x0001FE], 0x02); + } + + #[test] + fn nmi_uses_emulation_vector_in_emulation_mode() { + // Emulation-mode NMI vector is at $FFFA/$FFFB. + // Program: WAI (emulation mode, default after reset) + let nmi_handler_addr: u16 = 0xA000; + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xCB, 0xDB]); // WAI, STP + // Emulation NMI vector + system.load(0x00FFFA, &nmi_handler_addr.to_le_bytes()); + system.load(0x00A000, &[0xDB]); // NMI handler: STP + + step_n(&mut cpu, &mut system, 7); // reset + for _ in 0..50 { + cpu.step(&mut system); + if cpu.current_state() == CpuState::Waiting { + break; + } + } + assert_eq!(cpu.current_state(), CpuState::Waiting); + + system.nmi_pending = true; + run_until_stopped(&mut cpu, &mut system, 20); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0xA001); + } + + #[test] + fn nmi_is_taken_at_instruction_boundary_without_wai() { + let nmi_handler_addr: u16 = 0x9000; + let mut cpu = Cpu::new(); + let mut system = TestBus::with_reset_vector(0x8000); + system.load(0x008000, &[0xEA, 0xEA, 0xDB]); // NOP, NOP, STP + system.load(0x00FFFA, &nmi_handler_addr.to_le_bytes()); + system.load(0x009000, &[0xDB]); // NMI handler: STP + + step_n(&mut cpu, &mut system, 7); // reset + cpu.step(&mut system); // fetch first NOP + cpu.step(&mut system); // execute first NOP -> fetch boundary at $8001 + + system.nmi_pending = true; + run_until_stopped(&mut cpu, &mut system, 20); + + assert_eq!(cpu.current_state(), CpuState::Stopped); + assert_eq!(cpu.registers().pb(), 0x00); + assert_eq!(cpu.registers().pc(), 0x9001); + assert_eq!(system.memory[&0x0001FF], 0x80); + assert_eq!(system.memory[&0x0001FE], 0x01); + } +} diff --git a/snes/core/src/enhancement.rs b/snes/core/src/enhancement.rs new file mode 100644 index 00000000..44d28db0 --- /dev/null +++ b/snes/core/src/enhancement.rs @@ -0,0 +1,4463 @@ +use crate::mapper::{MapperKind, lorom_rom_index}; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum EnhancementChip { + None, + Sa1, + SuperFxGsu1, + SuperFxGsu2, + Cx4, + Dsp1, + Dsp1B, +} + +impl EnhancementChip { + pub(crate) fn is_superfx(self) -> bool { + matches!(self, Self::SuperFxGsu1 | Self::SuperFxGsu2) + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) enum EnhancementState { + None, + Sa1(Sa1State), + SuperFx(SuperFxState), + Cx4(Cx4State), + Dsp1(Dsp1State), +} + +impl EnhancementState { + pub(crate) fn from_chip(chip: EnhancementChip) -> Self { + match chip { + EnhancementChip::None => Self::None, + EnhancementChip::Sa1 => Self::Sa1(Sa1State::new()), + EnhancementChip::SuperFxGsu1 | EnhancementChip::SuperFxGsu2 => { + Self::SuperFx(SuperFxState::new()) + } + EnhancementChip::Cx4 => Self::Cx4(Cx4State::new()), + EnhancementChip::Dsp1 => Self::Dsp1(Dsp1State::new(Dsp1Variant::Dsp1)), + EnhancementChip::Dsp1B => Self::Dsp1(Dsp1State::new(Dsp1Variant::Dsp1B)), + } + } + + pub(crate) fn peek( + &self, + mapper_kind: MapperKind, + address: u32, + rom: &[u8], + save_ram: &[u8], + ) -> Option { + match self { + Self::None => None, + Self::Sa1(state) => state.peek(address, rom, save_ram), + Self::SuperFx(state) => state.peek(address), + Self::Cx4(state) => state.read(address), + Self::Dsp1(state) => state.peek(mapper_kind, address, rom.len()), + } + } + + pub(crate) fn read( + &mut self, + mapper_kind: MapperKind, + address: u32, + rom: &[u8], + save_ram: &[u8], + ) -> Option { + match self { + Self::None => None, + Self::Sa1(state) => state.read(address, rom, save_ram), + Self::SuperFx(state) => state.read(address), + Self::Cx4(state) => state.read(address), + Self::Dsp1(state) => state.read(mapper_kind, address, rom.len()), + } + } + + pub(crate) fn write( + &mut self, + mapper_kind: MapperKind, + address: u32, + value: u8, + rom: &[u8], + save_ram: &mut [u8], + ) -> bool { + match self { + Self::None => false, + Self::Sa1(state) => state.write(address, value, rom, save_ram), + Self::SuperFx(state) => state.write(address, value, rom, save_ram), + Self::Cx4(state) => state.write(address, value, rom), + Self::Dsp1(state) => state.write(mapper_kind, address, value, rom.len()), + } + } +} + +const MSU1_STATUS_REVISION: u8 = 0x02; +const MSU1_STATUS_AUDIO_ERROR: u8 = 0x08; +const MSU1_STATUS_AUDIO_PLAYING: u8 = 0x10; +const MSU1_STATUS_AUDIO_REPEATING: u8 = 0x20; +const MSU1_STATUS_AUDIO_BUSY: u8 = 0x40; +const MSU1_STATUS_DATA_BUSY: u8 = 0x80; +const MSU1_SIGNATURE: [u8; 6] = *b"S-MSU1"; + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct Msu1State { + present: bool, + data: Box<[u8]>, + audio_tracks: Box<[u16]>, + data_seek_offset: u32, + data_read_offset: u32, + audio_track: u16, + audio_volume: u8, + audio_error: bool, + audio_playing: bool, + audio_repeating: bool, + audio_busy: bool, + data_busy: bool, +} + +impl Msu1State { + pub(crate) fn new() -> Self { + Self { + present: false, + data: Box::new([]), + audio_tracks: Box::new([]), + data_seek_offset: 0, + data_read_offset: 0, + audio_track: 0, + audio_volume: 0, + audio_error: true, + audio_playing: false, + audio_repeating: false, + audio_busy: false, + data_busy: false, + } + } + + pub(crate) fn load_data(&mut self, data: &[u8]) { + self.present = true; + self.data = data.to_vec().into_boxed_slice(); + } + + pub(crate) fn set_audio_tracks(&mut self, tracks: I) + where + I: IntoIterator, + { + let mut tracks = tracks.into_iter().collect::>(); + tracks.sort_unstable(); + tracks.dedup(); + if !tracks.is_empty() { + self.present = true; + } + self.audio_tracks = tracks.into_boxed_slice(); + self.refresh_audio_track_status(); + } + + pub(crate) fn peek(&self, address: u32) -> Option { + if !self.present { + return None; + } + let offset = msu1_register_offset(address)?; + Some(self.peek_register(offset)) + } + + pub(crate) fn read(&mut self, address: u32) -> Option { + if !self.present { + return None; + } + let offset = msu1_register_offset(address)?; + Some(match offset { + 0x2001 => self.read_data(), + _ => self.peek_register(offset), + }) + } + + pub(crate) fn write(&mut self, address: u32, value: u8) -> bool { + if !self.present { + return false; + } + let Some(offset) = msu1_register_offset(address) else { + return false; + }; + + match offset { + 0x2000 => { + self.data_seek_offset = (self.data_seek_offset & 0xFFFF_FF00) | u32::from(value); + } + 0x2001 => { + self.data_seek_offset = + (self.data_seek_offset & 0xFFFF_00FF) | (u32::from(value) << 8); + } + 0x2002 => { + self.data_seek_offset = + (self.data_seek_offset & 0xFF00_FFFF) | (u32::from(value) << 16); + } + 0x2003 => { + self.data_seek_offset = + (self.data_seek_offset & 0x00FF_FFFF) | (u32::from(value) << 24); + self.data_read_offset = self.data_seek_offset; + } + 0x2004 => { + self.audio_track = (self.audio_track & 0xFF00) | u16::from(value); + } + 0x2005 => { + self.audio_track = (self.audio_track & 0x00FF) | (u16::from(value) << 8); + self.audio_playing = false; + self.audio_repeating = false; + self.refresh_audio_track_status(); + } + 0x2006 => { + self.audio_volume = value; + } + 0x2007 => { + if !self.audio_busy && !self.audio_error { + self.audio_playing = value & 0x01 != 0; + self.audio_repeating = value & 0x02 != 0; + } + } + _ => unreachable!("MSU-1 register offset outside $2000-$2007"), + } + + true + } + + fn peek_register(&self, offset: u16) -> u8 { + match offset { + 0x2000 => self.status(), + 0x2001 => 0x00, + 0x2002..=0x2007 => MSU1_SIGNATURE[usize::from(offset - 0x2002)], + _ => unreachable!("MSU-1 register offset outside $2000-$2007"), + } + } + + fn read_data(&mut self) -> u8 { + if self.data_busy { + return 0x00; + } + if self.data.is_empty() { + return 0x00; + } + + let Some(value) = usize::try_from(self.data_read_offset) + .ok() + .and_then(|offset| self.data.get(offset).copied()) + else { + return 0x00; + }; + self.data_read_offset = self.data_read_offset.wrapping_add(1); + value + } + + fn refresh_audio_track_status(&mut self) { + self.audio_error = self.audio_tracks.binary_search(&self.audio_track).is_err(); + } + + fn status(&self) -> u8 { + MSU1_STATUS_REVISION + | if self.audio_error { + MSU1_STATUS_AUDIO_ERROR + } else { + 0 + } + | if self.audio_playing { + MSU1_STATUS_AUDIO_PLAYING + } else { + 0 + } + | if self.audio_repeating { + MSU1_STATUS_AUDIO_REPEATING + } else { + 0 + } + | if self.audio_busy { + MSU1_STATUS_AUDIO_BUSY + } else { + 0 + } + | if self.data_busy { + MSU1_STATUS_DATA_BUSY + } else { + 0 + } + } + + #[cfg(test)] + pub(crate) fn data_seek_offset(&self) -> u32 { + self.data_seek_offset + } + + #[cfg(test)] + pub(crate) fn data_read_offset(&self) -> u32 { + self.data_read_offset + } + + #[cfg(test)] + pub(crate) fn data_len(&self) -> usize { + self.data.len() + } + + #[cfg(test)] + pub(crate) fn audio_track(&self) -> u16 { + self.audio_track + } + + #[cfg(test)] + pub(crate) fn audio_volume(&self) -> u8 { + self.audio_volume + } + + #[cfg(test)] + pub(crate) fn audio_track_count(&self) -> usize { + self.audio_tracks.len() + } +} + +fn msu1_register_offset(address: u32) -> Option { + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + if matches!(bank, 0x00..=0x3F | 0x80..=0xBF) && matches!(offset, 0x2000..=0x2007) { + Some(offset) + } else { + None + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct Sa1State { + registers: ByteWindow, + iram: ByteWindow, + cbmode: bool, + cb: u8, + dbmode: bool, + db: u8, + ebmode: bool, + eb: u8, + fbmode: bool, + fb: u8, + sbm: u8, + sa1_bwbank: u8, + sa1_bwmode: bool, + swen: bool, + cwen: bool, + bwp: u8, + siwp: u8, + ciwp: u8, + cpu_irq_flag: bool, + cpu_irq_vector_override: bool, + cpu_nmi_vector_override: bool, + cpu_message: u8, + sa1_irq_flag: bool, + sa1_nmi_flag: bool, + dma_irq_flag: bool, + character_dma_irq_flag: bool, + sa1_message: u8, + vbr_auto_increment: bool, + vbr_shift: u8, + vbr_bits: u8, + vbr_address: u32, + dma_enabled: bool, + dma_char_conversion: bool, + dma_char_conversion_target: bool, + dma_dest_bwram: bool, + dma_source_device: u8, + dma_conversion_size: u8, + dma_conversion_depth: u8, + dma_source_address: u32, + dma_dest_address: u32, + dma_length: u16, + dma_line: u8, + dma_bwram_conversion_active: bool, + bitmap_register_file: [u8; 16], + bwram_bitmap_2bpp: bool, + timer_control: u8, + timer_h_target: u16, + timer_v_target: u16, + timer_h_counter: u16, + timer_v_counter: u16, + timer_latched_h_counter: u16, + timer_latched_v_counter: u16, + timer_linear_counter: u32, + timer_irq_flag: bool, + arithmetic_acm: bool, + arithmetic_md: bool, + ma: u16, + mb: u16, + mr: u64, + arithmetic_overflow: bool, +} + +const SA1_CXB: u16 = 0x2220; +const SA1_CCNT: u16 = 0x2200; +const SA1_SIC: u16 = 0x2202; +const SA1_SCNT: u16 = 0x2209; +const SA1_CIC: u16 = 0x220B; +const SA1_TMC: u16 = 0x2210; +const SA1_CTR: u16 = 0x2211; +const SA1_HCNTL: u16 = 0x2212; +const SA1_HCNTH: u16 = 0x2213; +const SA1_VCNTL: u16 = 0x2214; +const SA1_VCNTH: u16 = 0x2215; +const SA1_DXB: u16 = 0x2221; +const SA1_EXB: u16 = 0x2222; +const SA1_FXB: u16 = 0x2223; +const SA1_BMAPS: u16 = 0x2224; +const SA1_BMAP: u16 = 0x2225; +const SA1_SBWE: u16 = 0x2226; +const SA1_CBWE: u16 = 0x2227; +const SA1_BWPA: u16 = 0x2228; +const SA1_SIWP: u16 = 0x2229; +const SA1_CIWP: u16 = 0x222A; +const SA1_BBF: u16 = 0x223F; +const SA1_MCNT: u16 = 0x2250; +const SA1_MAL: u16 = 0x2251; +const SA1_MAH: u16 = 0x2252; +const SA1_MBL: u16 = 0x2253; +const SA1_MBH: u16 = 0x2254; +const SA1_VBD: u16 = 0x2258; +const SA1_VDAL: u16 = 0x2259; +const SA1_VDAM: u16 = 0x225A; +const SA1_VDAH: u16 = 0x225B; +const SA1_DCNT: u16 = 0x2230; +const SA1_CDMA: u16 = 0x2231; +const SA1_DSAL: u16 = 0x2232; +const SA1_DSAM: u16 = 0x2233; +const SA1_DSAH: u16 = 0x2234; +const SA1_DDAL: u16 = 0x2235; +const SA1_DDAM: u16 = 0x2236; +const SA1_DDAH: u16 = 0x2237; +const SA1_DTCL: u16 = 0x2238; +const SA1_DTCH: u16 = 0x2239; +const SA1_BRF0: u16 = 0x2240; +const SA1_BRF7: u16 = 0x2247; +const SA1_BRF15: u16 = 0x224F; +const SA1_SFR: u16 = 0x2300; +const SA1_CFR: u16 = 0x2301; +const SA1_HCRL: u16 = 0x2302; +const SA1_HCRH: u16 = 0x2303; +const SA1_VCRL: u16 = 0x2304; +const SA1_VCRH: u16 = 0x2305; +const SA1_MR0: u16 = 0x2306; +const SA1_OF: u16 = 0x230B; +const SA1_VDPL: u16 = 0x230C; +const SA1_VDPH: u16 = 0x230D; +const SA1_MR_MASK: u64 = (1 << 40) - 1; +const SA1_HCOUNTER_DOTS_PER_LINE: u16 = 341; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Sa1BwramAccess { + Linear(usize), + Bitmap(usize), +} + +impl Sa1State { + fn new() -> Self { + let mut registers = ByteWindow::new(0x2200, 0x0200); + registers.write(SA1_DXB, 0x01); + registers.write(SA1_EXB, 0x02); + registers.write(SA1_FXB, 0x03); + registers.write(SA1_BWPA, 0x0F); + + Self { + registers, + iram: ByteWindow::new(0x3000, 0x0800), + cbmode: false, + cb: 0, + dbmode: false, + db: 1, + ebmode: false, + eb: 2, + fbmode: false, + fb: 3, + sbm: 0, + sa1_bwbank: 0, + sa1_bwmode: false, + swen: false, + cwen: false, + bwp: 0x0F, + siwp: 0, + ciwp: 0, + cpu_irq_flag: false, + cpu_irq_vector_override: false, + cpu_nmi_vector_override: false, + cpu_message: 0, + sa1_irq_flag: false, + sa1_nmi_flag: false, + dma_irq_flag: false, + character_dma_irq_flag: false, + sa1_message: 0, + vbr_auto_increment: false, + vbr_shift: 16, + vbr_bits: 0, + vbr_address: 0, + dma_enabled: false, + dma_char_conversion: false, + dma_char_conversion_target: false, + dma_dest_bwram: false, + dma_source_device: 0, + dma_conversion_size: 0, + dma_conversion_depth: 0, + dma_source_address: 0, + dma_dest_address: 0, + dma_length: 0, + dma_line: 0, + dma_bwram_conversion_active: false, + bitmap_register_file: [0; 16], + bwram_bitmap_2bpp: false, + timer_control: 0, + timer_h_target: 0, + timer_v_target: 0, + timer_h_counter: 0, + timer_v_counter: 0, + timer_latched_h_counter: 0, + timer_latched_v_counter: 0, + timer_linear_counter: 0, + timer_irq_flag: false, + arithmetic_acm: false, + arithmetic_md: false, + ma: 0, + mb: 0, + mr: 0, + arithmetic_overflow: false, + } + } + + fn peek(&self, address: u32, rom: &[u8], save_ram: &[u8]) -> Option { + if !is_system_bank(address) { + return None; + } + + let address_offset = offset(address); + if let Some(value) = self.read_status(address_offset) { + return Some(value); + } + if let Some(value) = self.peek_timer(address_offset) { + return Some(value); + } + if let Some(value) = self.read_arithmetic(address_offset) { + return Some(value); + } + if let Some(value) = self.peek_variable_data(address_offset, rom, save_ram) { + return Some(value); + } + + self.registers + .read(address_offset) + .or_else(|| self.iram.read(address_offset)) + } + + fn read(&mut self, address: u32, rom: &[u8], save_ram: &[u8]) -> Option { + if is_system_bank(address) + && let Some(value) = self.read_timer(offset(address)) + { + return Some(value); + } + + let value = self.peek(address, rom, save_ram)?; + if is_system_bank(address) && offset(address) == SA1_VDPH && self.vbr_auto_increment { + self.increment_variable_data_address(); + } + Some(value) + } + + fn write(&mut self, address: u32, value: u8, rom: &[u8], save_ram: &mut [u8]) -> bool { + if !is_system_bank(address) { + return false; + } + + let address_offset = offset(address); + if self.write_arithmetic(address_offset, value) { + return true; + } + + if self.registers.write(address_offset, value) { + self.write_mapper_register(address_offset, value, rom, save_ram); + return true; + } + + self.write_iram(address_offset, value) + } + + pub(crate) fn sa1_banked_rom_index(&self, address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let bank = bank(address); + let offset = offset(address); + let (slot, slot_offset, lo_access) = match bank { + 0xC0..=0xFF => { + let slot = usize::from((bank - 0xC0) >> 4); + let slot_offset = usize::from(bank & 0x0F) * 0x10000 + usize::from(offset); + (slot, slot_offset, false) + } + 0x00..=0x3F | 0x80..=0xBF if offset >= 0x8000 => { + let mirror_bank = bank & 0x3F; + let slot = usize::from(mirror_bank >> 5); + let slot_offset = + usize::from(mirror_bank & 0x1F) * 0x8000 + usize::from(offset - 0x8000); + (slot, slot_offset, true) + } + _ => return None, + }; + + let (xmode, selected_bank) = match slot { + 0 => (self.cbmode, self.cb), + 1 => (self.dbmode, self.db), + 2 => (self.ebmode, self.eb), + 3 => (self.fbmode, self.fb), + _ => unreachable!("SA-1 Super MMC slot is constrained to 0..=3"), + }; + let base = if lo_access && !xmode { + slot * 0x100000 + } else { + usize::from(selected_bank) * 0x100000 + }; + + Some((base + slot_offset) % rom_len) + } + + pub(crate) fn sa1_bwram_index(&self, address: u32, ram_len: usize) -> Option { + if ram_len == 0 { + return None; + } + + let linear = self.s_cpu_bwram_linear_address(address)?; + + Some(linear % ram_len) + } + + pub(crate) fn read_sa1_bwram(&mut self, address: u32, save_ram: &[u8]) -> Option { + let linear = self.s_cpu_bwram_linear_address(address)?; + if save_ram.is_empty() { + return None; + } + if self.dma_bwram_conversion_active { + return Some(self.read_character_conversion_type1(linear, save_ram)); + } + + Some(save_ram[linear % save_ram.len()]) + } + + pub(crate) fn can_write_sa1_bwram(&self, address: u32) -> bool { + let Some(linear) = self.s_cpu_bwram_linear_address(address) else { + return false; + }; + // BWPA is checked against the 256 KiB SA-1 BWRAM address space before SRAM mirroring. + let protection_address = linear & 0x3FFFF; + self.swen || self.cwen || protection_address >= (0x100usize << self.bwp) + } + + fn s_cpu_bwram_linear_address(&self, address: u32) -> Option { + let bank = bank(address); + let offset = offset(address); + match bank { + 0x00..=0x3F | 0x80..=0xBF if (0x6000..=0x7FFF).contains(&offset) => { + Some(usize::from(self.sbm) * 0x2000 + usize::from(offset - 0x6000)) + } + 0x40..=0x4F => Some(usize::from(bank & 0x0F) * 0x10000 + usize::from(offset)), + _ => None, + } + } + + pub(crate) fn read_sa1_cpu_bwram(&self, address: u32, save_ram: &[u8]) -> Option { + if save_ram.is_empty() { + return None; + } + + match self.sa1_cpu_bwram_access(address)? { + Sa1BwramAccess::Linear(linear) => Some(save_ram[linear % save_ram.len()]), + Sa1BwramAccess::Bitmap(pixel_address) => { + Some(self.read_bwram_bitmap_pixel(pixel_address, save_ram)) + } + } + } + + pub(crate) fn write_sa1_cpu_bwram(&self, address: u32, value: u8, save_ram: &mut [u8]) -> bool { + if save_ram.is_empty() { + return false; + } + let Some(access) = self.sa1_cpu_bwram_access(address) else { + return false; + }; + if !self.can_write_sa1_cpu_bwram(access) { + return true; + } + + match access { + Sa1BwramAccess::Linear(linear) => save_ram[linear % save_ram.len()] = value, + Sa1BwramAccess::Bitmap(pixel_address) => { + self.write_bwram_bitmap_pixel(pixel_address, value, save_ram); + } + } + true + } + + fn sa1_cpu_bwram_access(&self, address: u32) -> Option { + let bank = bank(address); + let offset = offset(address); + match bank { + 0x00..=0x3F | 0x80..=0xBF if (0x6000..=0x7FFF).contains(&offset) => { + let address = usize::from(self.sa1_bwbank) * 0x2000 + usize::from(offset - 0x6000); + if self.sa1_bwmode { + Some(Sa1BwramAccess::Bitmap(address)) + } else { + Some(Sa1BwramAccess::Linear(address)) + } + } + 0x40..=0x4F => Some(Sa1BwramAccess::Linear( + usize::from(bank & 0x0F) * 0x10000 + usize::from(offset), + )), + 0x60..=0x6F => Some(Sa1BwramAccess::Bitmap( + usize::from(bank & 0x0F) * 0x10000 + usize::from(offset), + )), + _ => None, + } + } + + fn can_write_sa1_cpu_bwram(&self, access: Sa1BwramAccess) -> bool { + let byte_address = match access { + Sa1BwramAccess::Linear(linear) => linear, + Sa1BwramAccess::Bitmap(pixel_address) => { + if self.bwram_bitmap_2bpp { + pixel_address >> 2 + } else { + pixel_address >> 1 + } + } + }; + let protection_address = byte_address & 0x3FFFF; + self.cwen || protection_address >= (0x100usize << self.bwp) + } + + fn read_bwram_bitmap_pixel(&self, pixel_address: usize, save_ram: &[u8]) -> u8 { + if self.bwram_bitmap_2bpp { + let shift = (pixel_address & 0x03) * 2; + (save_ram[(pixel_address >> 2) % save_ram.len()] >> shift) & 0x03 + } else { + let shift = (pixel_address & 0x01) * 4; + (save_ram[(pixel_address >> 1) % save_ram.len()] >> shift) & 0x0F + } + } + + fn write_bwram_bitmap_pixel(&self, pixel_address: usize, value: u8, save_ram: &mut [u8]) { + if self.bwram_bitmap_2bpp { + let shift = (pixel_address & 0x03) * 2; + let index = (pixel_address >> 2) % save_ram.len(); + save_ram[index] = (save_ram[index] & !(0x03 << shift)) | ((value & 0x03) << shift); + } else { + let shift = (pixel_address & 0x01) * 4; + let index = (pixel_address >> 1) % save_ram.len(); + save_ram[index] = (save_ram[index] & !(0x0F << shift)) | ((value & 0x0F) << shift); + } + } + + fn write_iram(&mut self, address_offset: u16, value: u8) -> bool { + let Some(index) = self.iram.index(address_offset) else { + return false; + }; + let page = (index >> 8) & 0x07; + if self.siwp & (1u8 << page) != 0 { + self.iram.bytes[index] = value; + } + true + } + + fn write_mapper_register( + &mut self, + address_offset: u16, + value: u8, + rom: &[u8], + save_ram: &mut [u8], + ) { + match address_offset { + SA1_CCNT => { + self.sa1_message = value & 0x0F; + if value & 0x80 != 0 { + self.sa1_irq_flag = true; + } + if value & 0x10 != 0 { + self.sa1_nmi_flag = true; + } + } + SA1_SIC => { + if value & 0x80 != 0 { + self.cpu_irq_flag = false; + } + if value & 0x20 != 0 { + self.character_dma_irq_flag = false; + } + } + SA1_SCNT => { + self.cpu_irq_vector_override = value & 0x40 != 0; + self.cpu_nmi_vector_override = value & 0x10 != 0; + self.cpu_message = value & 0x0F; + if value & 0x80 != 0 { + self.cpu_irq_flag = true; + } + } + SA1_CIC => { + if value & 0x80 != 0 { + self.sa1_irq_flag = false; + } + if value & 0x40 != 0 { + self.timer_irq_flag = false; + } + if value & 0x20 != 0 { + self.dma_irq_flag = false; + } + if value & 0x10 != 0 { + self.sa1_nmi_flag = false; + } + } + SA1_TMC => self.timer_control = value & 0x83, + SA1_CTR => self.restart_timer(), + SA1_HCNTL => self.timer_h_target = (self.timer_h_target & 0x0100) | u16::from(value), + SA1_HCNTH => { + self.timer_h_target = + (self.timer_h_target & 0x00FF) | (u16::from(value & 0x01) << 8); + } + SA1_VCNTL => self.timer_v_target = (self.timer_v_target & 0x0100) | u16::from(value), + SA1_VCNTH => { + self.timer_v_target = + (self.timer_v_target & 0x00FF) | (u16::from(value & 0x01) << 8); + } + SA1_CXB => { + self.cbmode = value & 0x80 != 0; + self.cb = value & 0x07; + } + SA1_DXB => { + self.dbmode = value & 0x80 != 0; + self.db = value & 0x07; + } + SA1_EXB => { + self.ebmode = value & 0x80 != 0; + self.eb = value & 0x07; + } + SA1_FXB => { + self.fbmode = value & 0x80 != 0; + self.fb = value & 0x07; + } + SA1_BMAPS => self.sbm = value & 0x1F, + SA1_BMAP => { + self.sa1_bwbank = value & 0x7F; + self.sa1_bwmode = value & 0x80 != 0; + } + SA1_SBWE => self.swen = value & 0x80 != 0, + SA1_CBWE => self.cwen = value & 0x80 != 0, + SA1_BWPA => self.bwp = value & 0x0F, + SA1_SIWP => self.siwp = value, + SA1_CIWP => self.ciwp = value, + SA1_VBD => { + self.vbr_auto_increment = value & 0x80 != 0; + self.vbr_shift = value & 0x0F; + if self.vbr_shift == 0 { + self.vbr_shift = 16; + } + if !self.vbr_auto_increment { + self.increment_variable_data_address(); + } + } + SA1_VDAL => self.vbr_address = (self.vbr_address & 0xFFFF00) | u32::from(value), + SA1_VDAM => { + self.vbr_address = (self.vbr_address & 0xFF00FF) | (u32::from(value) << 8); + } + SA1_VDAH => { + self.vbr_address = (self.vbr_address & 0x00FFFF) | (u32::from(value) << 16); + self.vbr_bits = 0; + } + SA1_DCNT => { + self.dma_enabled = value & 0x80 != 0; + self.dma_char_conversion = value & 0x20 != 0; + self.dma_char_conversion_target = value & 0x10 != 0; + self.dma_dest_bwram = value & 0x04 != 0; + self.dma_source_device = value & 0x03; + } + SA1_CDMA => { + if value & 0x80 != 0 { + self.dma_bwram_conversion_active = false; + } + self.dma_conversion_size = ((value >> 2) & 0x07).min(5); + self.dma_conversion_depth = (value & 0x03).min(2); + } + SA1_DSAL => { + self.dma_source_address = (self.dma_source_address & 0xFFFF00) | u32::from(value); + } + SA1_DSAM => { + self.dma_source_address = + (self.dma_source_address & 0xFF00FF) | (u32::from(value) << 8); + } + SA1_DSAH => { + self.dma_source_address = + (self.dma_source_address & 0x00FFFF) | (u32::from(value) << 16); + } + SA1_DDAL => { + self.dma_dest_address = (self.dma_dest_address & 0xFFFF00) | u32::from(value); + } + SA1_DDAM => { + self.dma_dest_address = + (self.dma_dest_address & 0xFF00FF) | (u32::from(value) << 8); + // IRAM destinations trigger after the middle DDA byte; BWRAM waits for DDAH. + if !self.dma_dest_bwram { + if self.dma_char_conversion && self.dma_char_conversion_target { + self.dma_bwram_conversion_active = self.dma_enabled; + if self.dma_enabled { + self.character_dma_irq_flag = true; + } + } else { + self.execute_normal_dma(rom, save_ram); + } + } + } + SA1_DDAH => { + self.dma_dest_address = + (self.dma_dest_address & 0x00FFFF) | (u32::from(value) << 16); + if self.dma_dest_bwram { + self.execute_normal_dma(rom, save_ram); + } + } + SA1_DTCL => self.dma_length = (self.dma_length & 0xFF00) | u16::from(value), + SA1_DTCH => self.dma_length = (self.dma_length & 0x00FF) | (u16::from(value) << 8), + SA1_BRF0..=SA1_BRF15 => { + self.bitmap_register_file[usize::from(address_offset - SA1_BRF0)] = value; + if matches!(address_offset, SA1_BRF7 | SA1_BRF15) { + self.execute_character_conversion_type2(); + } + } + SA1_BBF => self.bwram_bitmap_2bpp = value & 0x80 != 0, + _ => {} + } + } + + pub(crate) fn tick_timer(&mut self, h_subtick: u16, v_counter: u16, h_subticks_per_line: u16) { + if self.timer_control & 0x80 != 0 { + self.timer_linear_counter = self.timer_linear_counter.wrapping_add(1) & 0x3_FFFF; + self.timer_h_counter = (self.timer_linear_counter & 0x01FF) as u16; + self.timer_v_counter = ((self.timer_linear_counter >> 9) & 0x01FF) as u16; + } else { + self.timer_h_counter = + sa1_hcounter_midpoint_for_subtick(h_subtick, h_subticks_per_line); + self.timer_v_counter = v_counter & 0x01FF; + } + + if self.timer_matches(h_subtick, h_subticks_per_line) { + self.timer_irq_flag = true; + } + } + + fn restart_timer(&mut self) { + self.timer_linear_counter = 0; + self.timer_h_counter = 0; + self.timer_v_counter = 0; + self.timer_latched_h_counter = 0; + self.timer_latched_v_counter = 0; + self.timer_irq_flag = false; + } + + fn timer_matches(&self, h_subtick: u16, h_subticks_per_line: u16) -> bool { + let h_enabled = self.timer_control & 0x01 != 0; + let v_enabled = self.timer_control & 0x02 != 0; + if !h_enabled && !v_enabled { + return false; + } + + let h_match = if self.timer_control & 0x80 != 0 { + self.timer_h_counter == self.timer_h_target + } else { + sa1_hcounter_target_is_in_subtick(self.timer_h_target, h_subtick, h_subticks_per_line) + }; + let v_match = self.timer_v_counter == self.timer_v_target; + match (h_enabled, v_enabled) { + (true, true) => h_match && v_match, + (true, false) => h_match, + (false, true) => v_match, + (false, false) => false, + } + } + + fn read_timer(&mut self, address_offset: u16) -> Option { + if address_offset == SA1_HCRL { + self.latch_timer_counters(); + } + self.peek_timer(address_offset) + } + + fn peek_timer(&self, address_offset: u16) -> Option { + match address_offset { + SA1_HCRL => Some(self.timer_latched_h_counter as u8), + SA1_HCRH => Some(((self.timer_latched_h_counter >> 8) & 0x01) as u8), + SA1_VCRL => Some(self.timer_latched_v_counter as u8), + SA1_VCRH => Some(((self.timer_latched_v_counter >> 8) & 0x01) as u8), + _ => None, + } + } + + fn latch_timer_counters(&mut self) { + self.timer_latched_h_counter = self.timer_h_counter; + self.timer_latched_v_counter = self.timer_v_counter; + } + + fn peek_variable_data(&self, address_offset: u16, rom: &[u8], save_ram: &[u8]) -> Option { + if !matches!(address_offset, SA1_VDPL | SA1_VDPH) { + return None; + } + + let data = u32::from(self.read_variable_data_byte(self.vbr_address, rom, save_ram)) + | (u32::from(self.read_variable_data_byte( + self.vbr_address.wrapping_add(1), + rom, + save_ram, + )) << 8) + | (u32::from(self.read_variable_data_byte( + self.vbr_address.wrapping_add(2), + rom, + save_ram, + )) << 16); + let shifted = data >> self.vbr_bits; + Some(if address_offset == SA1_VDPL { + shifted as u8 + } else { + (shifted >> 8) as u8 + }) + } + + fn read_variable_data_byte(&self, address: u32, rom: &[u8], save_ram: &[u8]) -> u8 { + let address = address & 0x00FF_FFFF; + if is_sa1_rom_address(address) { + return self + .sa1_cpu_banked_rom_index(address, rom.len()) + .map(|index| rom[index]) + .unwrap_or(0xFF); + } + if let Some(value) = self.read_sa1_cpu_bwram(address, save_ram) { + return value; + } + if (address & 0x40F800) == 0x000000 || (address & 0x40F800) == 0x003000 { + return self.iram.bytes[address as usize & 0x07FF]; + } + 0xFF + } + + fn increment_variable_data_address(&mut self) { + let bits = self.vbr_bits + self.vbr_shift; + self.vbr_address = self.vbr_address.wrapping_add(u32::from(bits >> 3)) & 0x00FF_FFFF; + self.vbr_bits = bits & 0x07; + } + + fn sa1_cpu_banked_rom_index(&self, address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let address = address & 0x00FF_FFFF; + let translated = if (address & 0x408000) == 0x008000 { + ((address & 0x800000) >> 2) | ((address & 0x3F0000) >> 1) | (address & 0x007FFF) + } else { + address + }; + let lo_access = translated < 0x400000; + let normalized = translated & 0x3FFFFF; + let slot = (normalized >> 20) as usize; + let slot_offset = normalized as usize & 0x0F_FFFF; + let (xmode, selected_bank) = match slot { + 0 => (self.cbmode, self.cb), + 1 => (self.dbmode, self.db), + 2 => (self.ebmode, self.eb), + 3 => (self.fbmode, self.fb), + _ => return None, + }; + let base = if lo_access && !xmode { + slot * 0x100000 + } else { + usize::from(selected_bank) * 0x100000 + }; + Some((base + slot_offset) % rom_len) + } + + fn execute_normal_dma(&mut self, rom: &[u8], save_ram: &mut [u8]) { + if !self.dma_enabled || self.dma_char_conversion { + return; + } + + for offset in 0..u32::from(self.dma_length) { + let source = self.dma_source_address.wrapping_add(offset) & 0x00FF_FFFF; + let target = self.dma_dest_address.wrapping_add(offset) & 0x00FF_FFFF; + let value = self.read_dma_source(source, rom, save_ram); + if self.dma_dest_bwram { + if !save_ram.is_empty() { + save_ram[target as usize % save_ram.len()] = value; + } + } else { + self.iram.bytes[target as usize & 0x07FF] = value; + } + } + + self.dma_source_address = self + .dma_source_address + .wrapping_add(u32::from(self.dma_length)) + & 0x00FF_FFFF; + self.dma_dest_address = self + .dma_dest_address + .wrapping_add(u32::from(self.dma_length)) + & 0x00FF_FFFF; + self.dma_length = 0; + self.dma_irq_flag = true; + } + + fn read_dma_source(&self, address: u32, rom: &[u8], save_ram: &[u8]) -> u8 { + match self.dma_source_device { + 0 => self + .sa1_cpu_banked_rom_index(address, rom.len()) + .map(|index| rom[index]) + .unwrap_or(0xFF), + 1 => { + if save_ram.is_empty() { + 0xFF + } else { + save_ram[address as usize % save_ram.len()] + } + } + 2 => self.iram.bytes[address as usize & 0x07FF], + _ => 0xFF, + } + } + + fn execute_character_conversion_type2(&mut self) { + if !self.dma_enabled || !self.dma_char_conversion || self.dma_char_conversion_target { + return; + } + + let bytes_per_row = 2usize << (2 - self.dma_conversion_depth); + let mut target = self.dma_dest_address as usize & 0x07FF; + target &= !((1usize << (7 - self.dma_conversion_depth)) - 1); + target += usize::from(self.dma_line & 0x08) * bytes_per_row; + target += usize::from(self.dma_line & 0x07) * 2; + + let source_offset = usize::from(self.dma_line & 0x01) * 8; + for byte_index in 0..bytes_per_row { + let mut output = 0; + for bit_index in 0..8 { + let bit = (self.bitmap_register_file[source_offset + bit_index] >> byte_index) & 1; + output |= bit << (7 - bit_index); + } + let plane_offset = ((byte_index & 0x06) << 3) + (byte_index & 0x01); + self.iram.bytes[(target + plane_offset) & 0x07FF] = output; + } + + self.dma_line = self.dma_line.wrapping_add(1) & 0x0F; + } + + fn read_character_conversion_type1(&mut self, address: usize, save_ram: &[u8]) -> u8 { + let character_mask = (1usize << (6 - self.dma_conversion_depth)) - 1; + if address & character_mask == 0 { + self.buffer_character_conversion_type1(address, save_ram); + } + + let iram_index = (self.dma_dest_address as usize + (address & character_mask)) & 0x07FF; + self.iram.bytes[iram_index] + } + + fn buffer_character_conversion_type1(&mut self, address: usize, save_ram: &[u8]) { + let bytes_per_row = 2usize << (2 - self.dma_conversion_depth); + let bytes_per_line = (8usize << self.dma_conversion_size) >> self.dma_conversion_depth; + let bwram_mask = save_ram.len() - 1; + let tile = (address.wrapping_sub(self.dma_source_address as usize) & bwram_mask) + >> (6 - self.dma_conversion_depth); + let tile_y = tile >> self.dma_conversion_size; + let tile_x = tile & ((1usize << self.dma_conversion_size) - 1); + let mut bwram_address = + self.dma_source_address as usize + tile_y * 8 * bytes_per_line + tile_x * bytes_per_row; + + for row in 0..8 { + let mut data = 0u64; + for byte_index in 0..bytes_per_row { + data |= u64::from(save_ram[(bwram_address + byte_index) & bwram_mask]) + << (byte_index * 8); + } + bwram_address += bytes_per_line; + + let mut output = [0u8; 8]; + for pixel in 0..8 { + output[0] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + output[1] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + if self.dma_conversion_depth == 2 { + continue; + } + output[2] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + output[3] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + if self.dma_conversion_depth == 1 { + continue; + } + output[4] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + output[5] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + output[6] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + output[7] |= ((data & 1) as u8) << (7 - pixel); + data >>= 1; + } + + for (byte_index, byte) in output.into_iter().take(bytes_per_row).enumerate() { + let plane_offset = ((byte_index & 0x06) << 3) + (byte_index & 0x01); + let target = (self.dma_dest_address as usize + row * 2 + plane_offset) & 0x07FF; + self.iram.bytes[target] = byte; + } + } + } + + fn read_status(&self, address_offset: u16) -> Option { + match address_offset { + SA1_SFR => Some( + u8::from(self.cpu_irq_flag) << 7 + | u8::from(self.cpu_irq_vector_override) << 6 + | u8::from(self.character_dma_irq_flag) << 5 + | u8::from(self.cpu_nmi_vector_override) << 4 + | (self.cpu_message & 0x0F), + ), + SA1_CFR => Some( + u8::from(self.sa1_irq_flag) << 7 + | u8::from(self.timer_irq_flag) << 6 + | u8::from(self.dma_irq_flag) << 5 + | u8::from(self.sa1_nmi_flag) << 4 + | (self.sa1_message & 0x0F), + ), + _ => None, + } + } + + fn read_arithmetic(&self, address_offset: u16) -> Option { + match address_offset { + SA1_MR0..=0x230A => Some((self.mr >> ((address_offset - SA1_MR0) * 8)) as u8), + SA1_OF => Some(if self.arithmetic_overflow { 0x80 } else { 0x00 }), + _ => None, + } + } + + fn write_arithmetic(&mut self, address_offset: u16, value: u8) -> bool { + if !matches!(address_offset, SA1_MCNT..=SA1_MBH) { + return false; + } + + self.registers.write(address_offset, value); + match address_offset { + SA1_MCNT => { + self.arithmetic_md = value & 0x01 != 0; + self.arithmetic_acm = value & 0x02 != 0; + if self.arithmetic_acm { + self.mr = 0; + } + } + SA1_MAL => self.ma = (self.ma & 0xFF00) | u16::from(value), + SA1_MAH => self.ma = (self.ma & 0x00FF) | (u16::from(value) << 8), + SA1_MBL => self.mb = (self.mb & 0xFF00) | u16::from(value), + SA1_MBH => { + self.mb = (self.mb & 0x00FF) | (u16::from(value) << 8); + self.execute_arithmetic(); + } + _ => {} + } + true + } + + fn execute_arithmetic(&mut self) { + if self.arithmetic_acm { + let product = i64::from(self.ma as i16) * i64::from(self.mb as i16); + let sum = self.mr.wrapping_add(product as u64); + self.arithmetic_overflow = (sum >> 40) != 0; + self.mr = sum & SA1_MR_MASK; + self.mb = 0; + } else if self.arithmetic_md { + self.execute_divide(); + self.ma = 0; + self.mb = 0; + } else { + let product = i32::from(self.ma as i16) * i32::from(self.mb as i16); + self.mr = u64::from(product as u32); + self.mb = 0; + } + } + + fn execute_divide(&mut self) { + if self.mb == 0 { + self.mr = 0; + return; + } + + let dividend = i32::from(self.ma as i16); + let divisor = i32::from(self.mb); + let remainder = dividend.rem_euclid(divisor); + let quotient = (dividend - remainder) / divisor; + self.mr = (u64::from(remainder as u16) << 16) | u64::from(quotient as i16 as u16); + } +} + +fn sa1_hcounter_target_is_in_subtick(target: u16, subtick: u16, subticks_per_line: u16) -> bool { + let subticks_per_line = u32::from(subticks_per_line.max(1)); + let start = (u32::from(subtick) * u32::from(SA1_HCOUNTER_DOTS_PER_LINE)) / subticks_per_line; + let end = (u32::from(subtick + 1) * u32::from(SA1_HCOUNTER_DOTS_PER_LINE)) / subticks_per_line; + let target = u32::from(target.min(SA1_HCOUNTER_DOTS_PER_LINE.saturating_sub(1))); + target >= start && target < end +} + +fn sa1_hcounter_midpoint_for_subtick(subtick: u16, subticks_per_line: u16) -> u16 { + let subticks_per_line = u32::from(subticks_per_line.max(1)); + let start = (u32::from(subtick) * u32::from(SA1_HCOUNTER_DOTS_PER_LINE)) / subticks_per_line; + let end = (u32::from(subtick + 1) * u32::from(SA1_HCOUNTER_DOTS_PER_LINE)) / subticks_per_line; + (start + ((end - start).saturating_sub(1) / 2)) as u16 +} + +#[cfg(test)] +mod tests { + use super::{SA1_BBF, SA1_BMAP, SA1_CBWE, SA1_SBWE, Sa1State}; + + fn write_register(state: &mut Sa1State, save_ram: &mut [u8], offset: u16, value: u8) { + assert!(state.write(u32::from(offset), value, &[], save_ram)); + } + + #[test] + fn sa1_cpu_bmap_linear_writes_use_sa1_bank() { + let mut state = Sa1State::new(); + let mut save_ram = vec![0; 0x4000]; + save_ram[0] = 0x11; + + write_register(&mut state, &mut save_ram, SA1_BMAP, 0x01); + write_register(&mut state, &mut save_ram, SA1_CBWE, 0x80); + + assert!(state.write_sa1_cpu_bwram(0x006000, 0x55, &mut save_ram)); + assert_eq!(save_ram[0], 0x11); + assert_eq!(save_ram[0x2000], 0x55); + assert_eq!(state.read_sa1_cpu_bwram(0x006000, &save_ram), Some(0x55)); + } + + #[test] + fn sa1_cpu_writes_require_sa1_write_enable_for_protected_bwram() { + let mut state = Sa1State::new(); + let mut save_ram = vec![0; 0x2000]; + + write_register(&mut state, &mut save_ram, SA1_SBWE, 0x80); + assert!(state.write_sa1_cpu_bwram(0x006000, 0x12, &mut save_ram)); + assert_eq!(save_ram[0], 0x00); + + write_register(&mut state, &mut save_ram, SA1_CBWE, 0x80); + assert!(state.write_sa1_cpu_bwram(0x006000, 0x34, &mut save_ram)); + assert_eq!(save_ram[0], 0x34); + } + + #[test] + fn sa1_cpu_bmap_bitmap_writes_pack_4bpp_pixels() { + let mut state = Sa1State::new(); + let mut save_ram = vec![0; 0x2000]; + save_ram[0] = 0xAB; + + write_register(&mut state, &mut save_ram, SA1_CBWE, 0x80); + write_register(&mut state, &mut save_ram, SA1_BBF, 0x00); + write_register(&mut state, &mut save_ram, SA1_BMAP, 0x80); + + assert!(state.write_sa1_cpu_bwram(0x006000, 0x07, &mut save_ram)); + assert_eq!(save_ram[0], 0xA7); + assert_eq!(state.read_sa1_cpu_bwram(0x006000, &save_ram), Some(0x07)); + assert_eq!(state.read_sa1_cpu_bwram(0x006001, &save_ram), Some(0x0A)); + + assert!(state.write_sa1_cpu_bwram(0x006001, 0x03, &mut save_ram)); + assert_eq!(save_ram[0], 0x37); + assert_eq!(state.read_sa1_cpu_bwram(0x006000, &save_ram), Some(0x07)); + assert_eq!(state.read_sa1_cpu_bwram(0x006001, &save_ram), Some(0x03)); + } + + #[test] + fn sa1_cpu_bmap_bitmap_writes_pack_2bpp_pixels() { + let mut state = Sa1State::new(); + let mut save_ram = vec![0; 0x2000]; + + write_register(&mut state, &mut save_ram, SA1_CBWE, 0x80); + write_register(&mut state, &mut save_ram, SA1_BBF, 0x80); + write_register(&mut state, &mut save_ram, SA1_BMAP, 0x80); + + assert!(state.write_sa1_cpu_bwram(0x006001, 0x03, &mut save_ram)); + assert_eq!(save_ram[0], 0x0C); + assert_eq!(state.read_sa1_cpu_bwram(0x006001, &save_ram), Some(0x03)); + + assert!(state.write_sa1_cpu_bwram(0x006003, 0x02, &mut save_ram)); + assert_eq!(save_ram[0], 0x8C); + assert_eq!(state.read_sa1_cpu_bwram(0x006003, &save_ram), Some(0x02)); + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct SuperFxState { + registers: ByteWindow, +} + +const SUPERFX_VCR: u16 = 0x303B; +const SUPERFX_SFR: u16 = 0x3030; +const SUPERFX_R15: u16 = 0x301E; +const SUPERFX_R15_HIGH: u16 = 0x301F; +const SUPERFX_PBR: u16 = 0x3034; +const SUPERFX_ROMBR: u16 = 0x3036; +const SUPERFX_SCBR: u16 = 0x3038; +const SUPERFX_SCMR: u16 = 0x303A; +const SUPERFX_RAMBR: u16 = 0x303C; +const SUPERFX_CBR: u16 = 0x303E; +const SUPERFX_CBR_HIGH: u16 = 0x303F; +const SUPERFX_SFR_HIGH: u16 = SUPERFX_SFR + 1; +const SUPERFX_ZERO_FLAG: u8 = 0x02; +const SUPERFX_CARRY_FLAG: u8 = 0x04; +const SUPERFX_SIGN_FLAG: u8 = 0x08; +const SUPERFX_OVERFLOW_FLAG: u8 = 0x10; +const SUPERFX_GO_FLAG: u8 = 0x20; +const SUPERFX_IRQ_FLAG: u8 = 0x80; +const SUPERFX_ALU_FLAGS: u8 = + SUPERFX_ZERO_FLAG | SUPERFX_CARRY_FLAG | SUPERFX_SIGN_FLAG | SUPERFX_OVERFLOW_FLAG; +const GSU_MAX_INTERPRETER_STEPS: usize = 256 * 1024; + +impl SuperFxState { + fn new() -> Self { + let mut registers = ByteWindow::new(0x3000, 0x0500); + registers.write(SUPERFX_VCR, 0x04); + Self { registers } + } + + fn peek(&self, address: u32) -> Option { + if is_system_bank(address) { + let address_offset = offset(address); + self.registers + .contains(address_offset) + .then(|| self.read_register(address_offset)) + } else { + None + } + } + + fn read(&mut self, address: u32) -> Option { + let address_offset = offset(address); + let value = self.peek(address)?; + if is_system_bank(address) && address_offset == SUPERFX_SFR_HIGH { + self.registers + .write(SUPERFX_SFR_HIGH, value & !SUPERFX_IRQ_FLAG); + } + Some(value) + } + + fn write(&mut self, address: u32, value: u8, rom: &[u8], save_ram: &mut [u8]) -> bool { + if !is_system_bank(address) { + return false; + } + + let address_offset = offset(address); + if address_offset == SUPERFX_VCR { + return self.registers.contains(address_offset); + } + + let value = if matches!(address_offset, SUPERFX_PBR | SUPERFX_ROMBR) { + value & 0x7F + } else { + value + }; + let handled = self.registers.write(address_offset, value); + if handled && address_offset == SUPERFX_SFR && value & SUPERFX_GO_FLAG == 0 { + self.registers.write(SUPERFX_CBR, 0); + self.registers.write(SUPERFX_CBR_HIGH, 0); + } + if handled + && (address_offset == SUPERFX_R15_HIGH + || address_offset == SUPERFX_SFR && value & SUPERFX_GO_FLAG != 0) + { + self.run_program(rom, save_ram); + } + handled + } + + fn read_register(&self, address_offset: u16) -> u8 { + if matches!(address_offset, 0x3032 | 0x3035 | 0x303D) { + 0 + } else { + self.registers.read(address_offset).unwrap_or(0) + } + } + + fn run_program(&mut self, rom: &[u8], save_ram: &mut [u8]) { + let r15 = u16::from_le_bytes([ + self.registers.read(SUPERFX_R15).unwrap_or(0), + self.registers.read(SUPERFX_R15 + 1).unwrap_or(0), + ]); + let pbr = self.registers.read(SUPERFX_PBR).unwrap_or(0) & 0x7F; + let rombr = self.registers.read(SUPERFX_ROMBR).unwrap_or(0) & 0x7F; + let rambr = self.registers.read(SUPERFX_RAMBR).unwrap_or(0) & 0x01 != 0; + let cbr = u16::from_le_bytes([ + self.registers.read(SUPERFX_CBR).unwrap_or(0), + self.registers.read(SUPERFX_CBR_HIGH).unwrap_or(0), + ]) & 0xFFF0; + let screen_base = usize::from(self.registers.read(SUPERFX_SCBR).unwrap_or(0)) * 0x400; + let screen_mode = self.registers.read(SUPERFX_SCMR).unwrap_or(0); + let sfr = self.registers.read(SUPERFX_SFR).unwrap_or(0); + + let mut registers = [0u16; 16]; + for (i, value) in registers.iter_mut().enumerate() { + let offset = 0x3000 + i as u16 * 2; + let low = self.registers.read(offset).unwrap_or(0); + let high = self.registers.read(offset + 1).unwrap_or(0); + *value = u16::from_le_bytes([low, high]); + } + + // Read cache from $3100-$32FF + let mut cache = [0u8; 512]; + let mut cache_has_data = false; + for (i, byte) in cache.iter_mut().enumerate() { + let offset = 0x3100 + i as u16; + *byte = self.registers.read(offset).unwrap_or(0); + if *byte != 0 { + cache_has_data = true; + } + } + + let start = GsuStartState { + entry: r15, + pbr, + rombr, + rambr, + cbr, + screen_base, + screen_mode, + sfr, + }; + let mut interpreter = GsuInterpreter::new_with_registers( + start, + registers, + rom, + save_ram, + cache, + cache_has_data, + ); + interpreter.run(); + let stopped = interpreter.halted; + for (register, value) in interpreter.registers.iter().copied().enumerate() { + let [low, high] = value.to_le_bytes(); + let offset = 0x3000 + register as u16 * 2; + self.registers.write(offset, low); + self.registers.write(offset + 1, high); + } + self.registers.write(SUPERFX_PBR, interpreter.pbr & 0x7F); + self.registers.write(SUPERFX_ROMBR, interpreter.rombr); + self.registers + .write(SUPERFX_RAMBR, u8::from(interpreter.rambr)); + let [cbr_low, cbr_high] = (interpreter.cbr & 0xFFF0).to_le_bytes(); + self.registers.write(SUPERFX_CBR, cbr_low); + self.registers.write(SUPERFX_CBR_HIGH, cbr_high); + + let sfr = (self.registers.read(SUPERFX_SFR).unwrap_or(0) + & !(SUPERFX_ALU_FLAGS | SUPERFX_GO_FLAG)) + | interpreter.sfr_flags(); + self.registers.write(SUPERFX_SFR, sfr); + if stopped { + let sfr_high = self.registers.read(SUPERFX_SFR_HIGH).unwrap_or(0) | SUPERFX_IRQ_FLAG; + self.registers.write(SUPERFX_SFR_HIGH, sfr_high); + } + } +} + +struct GsuInterpreter<'a> { + rom: &'a [u8], + ram: &'a mut [u8], + registers: [u16; 16], + pc: u16, + pbr: u8, + rombr: u8, + rambr: bool, + cbr: u16, + cache: [u8; 512], + cache_valid: bool, + source: usize, + destination: Option, + alt_mode: u8, + color: u8, + plot_option: u8, + zero: bool, + carry: bool, + sign: bool, + overflow: bool, + screen_base: usize, + screen_mode: u8, + halted: bool, + last_ram_address: Option, + last_ram_word_swapped: bool, + pending_branch: Option, +} + +#[derive(Clone, Copy)] +struct GsuStartState { + entry: u16, + pbr: u8, + rombr: u8, + rambr: bool, + cbr: u16, + screen_base: usize, + screen_mode: u8, + sfr: u8, +} + +impl<'a> GsuInterpreter<'a> { + fn new_with_registers( + start: GsuStartState, + mut registers: [u16; 16], + rom: &'a [u8], + ram: &'a mut [u8], + cache: [u8; 512], + cache_valid: bool, + ) -> Self { + registers[15] = start.entry; + Self { + rom, + ram, + registers, + pc: start.entry, + pbr: start.pbr, + rombr: start.rombr, + rambr: start.rambr, + cbr: start.cbr, + cache, + cache_valid, + source: 0, + destination: None, + alt_mode: 0, + color: 0, + plot_option: 0, + zero: start.sfr & SUPERFX_ZERO_FLAG != 0, + carry: start.sfr & SUPERFX_CARRY_FLAG != 0, + sign: start.sfr & SUPERFX_SIGN_FLAG != 0, + overflow: start.sfr & SUPERFX_OVERFLOW_FLAG != 0, + screen_base: start.screen_base, + screen_mode: start.screen_mode, + halted: false, + last_ram_address: None, + last_ram_word_swapped: false, + pending_branch: None, + } + } + + fn run(&mut self) { + for _ in 0..GSU_MAX_INTERPRETER_STEPS { + if self.halted { + break; + } + if !self.step() { + break; + } + } + } + + fn step(&mut self) -> bool { + let opcode = self.fetch(); + + if let Some(target) = self.pending_branch.take() { + self.pc = target; + self.registers[15] = self.pc; + } + + if self.alt_mode == 0 && matches!(opcode, 0x3D..=0x3F) { + self.sync_program_counter(); + self.alt_mode = opcode - 0x3C; + return true; + } + + let alt_mode = std::mem::take(&mut self.alt_mode); + match (alt_mode, opcode) { + (_, 0x00) => { + self.sync_program_counter(); + self.halted = true; + } + (_, 0x01) => self.sync_program_counter(), + (_, 0x02) => { + self.sync_program_counter(); + self.cache(); + } + (0, 0x04) => { + self.sync_program_counter(); + self.rotate_left(); + } + (_, 0x05..=0x0F) => { + let relative = self.fetch() as i8; + self.sync_program_counter(); + if self.branch_condition(opcode) { + self.pending_branch = Some(self.pc.wrapping_add_signed(i16::from(relative))); + } + } + (0, 0x03) => { + self.sync_program_counter(); + self.shift_right(); + } + (_, 0x10..=0x1F) => { + self.sync_program_counter(); + self.destination = Some(usize::from(opcode & 0x0F)); + } + (_, 0x20..=0x2F) => { + let register = usize::from(opcode & 0x0F); + let next = self.peek_instruction_byte(); + if next & 0xF0 == 0x10 { + let operand = self.fetch(); + self.sync_program_counter(); + let destination = usize::from(operand & 0x0F); + self.move_register(destination, register); + } else if next & 0xF0 == 0xB0 { + let operand = self.fetch(); + self.sync_program_counter(); + let destination = register; + let source = usize::from(operand & 0x0F); + let value = self.registers[source]; + self.set_register_with_moves_flags(destination, value); + } else { + self.sync_program_counter(); + self.source = register; + if self.destination.is_none() { + self.destination = Some(register); + } + } + } + (0, 0x3C) => { + let r13 = self.registers[13]; + self.sync_program_counter(); + self.registers[12] = self.registers[12].wrapping_sub(1); + self.set_zero_sign(self.registers[12]); + self.carry = false; + self.overflow = false; + if !self.zero { + self.pending_branch = Some(r13); + self.source = 0; + } + } + (0, 0x30..=0x3B) => { + self.sync_program_counter(); + self.store_word(usize::from(opcode & 0x0F)); + } + (1, 0x30..=0x3F) => { + self.sync_program_counter(); + self.store_byte(usize::from(opcode & 0x0F)); + } + (0, 0x40..=0x4B) => { + self.sync_program_counter(); + self.load_word(usize::from(opcode & 0x0F)); + } + (1, 0x40..=0x4B) => { + self.sync_program_counter(); + self.load_byte(usize::from(opcode & 0x0F)); + } + (0, 0x4C) => { + self.sync_program_counter(); + self.plot(); + } + (1, 0x4C) => { + self.sync_program_counter(); + self.read_pixel(); + } + (0, 0x4D) => { + self.sync_program_counter(); + self.swap_bytes(); + } + (1, 0x4E) => { + self.sync_program_counter(); + self.plot_option = self.registers[self.source] as u8 & 0x1F; + self.destination = None; + } + (0, 0x4E) => { + self.sync_program_counter(); + let source = self.registers[self.source] as u8; + self.apply_color_input(source); + } + (0, 0x4F) => { + self.sync_program_counter(); + self.not(); + } + (2, 0x50..=0x5F) => { + self.sync_program_counter(); + self.add_immediate(u16::from(opcode & 0x0F)); + } + (1, 0x50..=0x5F) => { + self.sync_program_counter(); + self.add_with_carry_register(usize::from(opcode & 0x0F)); + } + (3, 0x50..=0x5F) => { + self.sync_program_counter(); + self.add_with_carry_immediate(u16::from(opcode & 0x0F)); + } + (0, 0x50..=0x5F) => { + self.sync_program_counter(); + self.add_register(usize::from(opcode & 0x0F)); + } + (3, 0x60..=0x6F) => { + self.sync_program_counter(); + self.compare_register(usize::from(opcode & 0x0F)); + } + (1, 0x60..=0x6F) => { + self.sync_program_counter(); + self.subtract_with_carry_register(usize::from(opcode & 0x0F)); + } + (2, 0x60..=0x6F) => { + self.sync_program_counter(); + self.subtract_immediate(u16::from(opcode & 0x0F)); + } + (0, 0x60..=0x6F) => { + self.sync_program_counter(); + self.subtract_register(usize::from(opcode & 0x0F)); + } + (2, 0x71..=0x7F) => { + self.sync_program_counter(); + self.and_immediate(u16::from(opcode & 0x0F)); + } + (1, 0x71..=0x7F) => { + self.sync_program_counter(); + self.bit_clear_register(usize::from(opcode & 0x0F)); + } + (3, 0x71..=0x7F) => { + self.sync_program_counter(); + self.bic_immediate(u16::from(opcode & 0x0F)); + } + (_, 0x70) => { + self.sync_program_counter(); + self.merge_bytes(); + } + (0, 0x71..=0x7F) => { + self.sync_program_counter(); + self.and_register(usize::from(opcode & 0x0F)); + } + (0, 0x80..=0x8F) => { + self.sync_program_counter(); + self.multiply_register(usize::from(opcode & 0x0F)); + } + (1, 0x80..=0x8F) => { + self.sync_program_counter(); + self.unsigned_multiply_register(usize::from(opcode & 0x0F)); + } + (2, 0x80..=0x8F) => { + self.sync_program_counter(); + self.multiply_immediate(u16::from(opcode & 0x0F)); + } + (3, 0x80..=0x8F) => { + self.sync_program_counter(); + self.unsigned_multiply_immediate(u16::from(opcode & 0x0F)); + } + (_, 0x90) => { + self.sync_program_counter(); + self.store_last_ram_word(); + } + (0, 0x91..=0x94) => { + self.sync_program_counter(); + self.link(u16::from(opcode & 0x0F)); + } + (0, 0x95) => { + self.sync_program_counter(); + self.sign_extend(); + } + (1, 0x96) => { + self.sync_program_counter(); + self.divide_by_two(); + } + (0, 0x96) => { + self.sync_program_counter(); + self.arithmetic_shift_right(); + } + (0, 0x97) => { + self.sync_program_counter(); + self.rotate_right(); + } + (0, 0x98..=0x9D) => { + self.jump_register(usize::from(opcode & 0x0F)); + } + (1, 0x98..=0x9D) => { + self.long_jump_register(usize::from(opcode & 0x0F)); + } + (0, 0x9E) => { + self.sync_program_counter(); + self.low_byte(); + } + (0, 0x9F) => { + self.sync_program_counter(); + self.fractional_multiply(false); + } + (1, 0x9F) => { + self.sync_program_counter(); + self.fractional_multiply(true); + } + (1, 0xA0..=0xAF) => { + let address = u16::from(self.fetch()) * 2; + self.sync_program_counter(); + self.load_absolute_word(usize::from(opcode & 0x0F), address); + } + (2, 0xA0..=0xAF) => { + let address = u16::from(self.fetch()) * 2; + self.sync_program_counter(); + self.store_absolute_word(address, usize::from(opcode & 0x0F)); + } + (_, 0xA0..=0xAF) => { + let value = self.fetch(); + self.sync_program_counter(); + self.load_register(usize::from(opcode & 0x0F), i16::from(value as i8) as u16); + } + (_, 0xB0..=0xBF) => { + self.sync_program_counter(); + self.source = usize::from(opcode & 0x0F); + } + (_, 0xDF) => { + self.sync_program_counter(); + self.getc_ramb_romb(alt_mode); + } + (_, 0xEF) => { + self.sync_program_counter(); + self.getb(alt_mode); + } + (_, 0xD0..=0xDF) => { + self.sync_program_counter(); + let register = usize::from(opcode & 0x0F); + self.registers[register] = self.registers[register].wrapping_add(1); + self.set_zero_sign(self.registers[register]); + self.carry = false; + self.overflow = false; + } + (_, 0xE0..=0xEF) => { + self.sync_program_counter(); + let register = usize::from(opcode & 0x0F); + self.registers[register] = self.registers[register].wrapping_sub(1); + self.set_zero_sign(self.registers[register]); + self.carry = false; + self.overflow = false; + } + (_, 0xC0) => { + self.sync_program_counter(); + self.high_byte(); + } + (2, 0xC1..=0xCF) => { + self.sync_program_counter(); + self.or_immediate(u16::from(opcode & 0x0F)); + } + (1, 0xC1..=0xCF) => { + self.sync_program_counter(); + self.xor_register(usize::from(opcode & 0x0F)); + } + (3, 0xC1..=0xCF) => { + self.sync_program_counter(); + self.xor_immediate(u16::from(opcode & 0x0F)); + } + (0, 0xC1..=0xCF) => { + self.sync_program_counter(); + self.or_register(usize::from(opcode & 0x0F)); + } + (1, 0xF0..=0xFF) => { + let low = self.fetch(); + let high = self.fetch(); + self.sync_program_counter(); + self.load_absolute_word( + usize::from(opcode & 0x0F), + u16::from_le_bytes([low, high]), + ); + } + (2, 0xF0..=0xFF) => { + let low = self.fetch(); + let high = self.fetch(); + self.sync_program_counter(); + self.store_absolute_word( + u16::from_le_bytes([low, high]), + usize::from(opcode & 0x0F), + ); + } + (_, 0xF0..=0xFF) => { + let low = self.fetch(); + let high = self.fetch(); + self.sync_program_counter(); + self.load_register(usize::from(opcode & 0x0F), u16::from_le_bytes([low, high])); + } + _ => return false, + } + true + } + + fn sfr_flags(&self) -> u8 { + (if self.zero { SUPERFX_ZERO_FLAG } else { 0 }) + | (if self.carry { SUPERFX_CARRY_FLAG } else { 0 }) + | (if self.sign { SUPERFX_SIGN_FLAG } else { 0 }) + | (if self.overflow { + SUPERFX_OVERFLOW_FLAG + } else { + 0 + }) + } + + fn fetch(&mut self) -> u8 { + let value = self.peek_instruction_byte(); + self.pc = self.pc.wrapping_add(1); + value + } + + fn peek_instruction_byte(&self) -> u8 { + let address = (u32::from(self.pbr) << 16) | u32::from(self.pc); + + // Check if executing from cache (PC in [CBR, CBR+0x1FF] range and cache is valid) + if self.cache_valid && self.pc >= self.cbr && self.pc < self.cbr.wrapping_add(0x200) { + let cache_offset = (self.pc.wrapping_sub(self.cbr) & 0x01FF) as usize; + return self.cache[cache_offset]; + } + + if self.pbr <= 0x5F { + return superfx_rom_index(address, self.rom.len()) + .map(|index| self.rom[index]) + .unwrap_or(0); + } + + let ram_address = (usize::from(self.pbr & 0x01) << 16) | usize::from(self.pc); + self.read_ram_raw_usize(ram_address) + } + + fn sync_program_counter(&mut self) { + self.registers[15] = self.pc; + } + + fn branch_condition(&self, opcode: u8) -> bool { + match opcode { + 0x05 => true, + 0x06 => self.sign == self.overflow, + 0x07 => self.sign != self.overflow, + 0x08 => !self.zero, + 0x09 => self.zero, + 0x0A => !self.sign, + 0x0B => self.sign, + 0x0C => !self.carry, + 0x0D => self.carry, + 0x0E => !self.overflow, + 0x0F => self.overflow, + _ => false, + } + } + + fn set_zero_sign(&mut self, value: u16) { + self.zero = value == 0; + self.sign = value & 0x8000 != 0; + } + + fn jump_register(&mut self, register: usize) { + self.pc = self.registers[register]; + self.registers[15] = self.pc; + } + + fn long_jump_register(&mut self, register: usize) { + self.pbr = self.registers[register] as u8 & 0x7F; + self.pc = self.read_alu_source(); + self.registers[15] = self.pc; + self.cbr = self.pc & 0xFFF0; + } + + fn cache(&mut self) { + let new_cbr = self.registers[15] & 0xFFF0; + if self.cbr != new_cbr || !self.cache_valid { + self.cbr = new_cbr; + self.flush_cache(); + } + } + + fn flush_cache(&mut self) { + let address = (u32::from(self.pbr) << 16) | u32::from(self.cbr); + for i in 0..512 { + let addr = address.wrapping_add(i as u32); + self.cache[i] = self.read_memory_byte(addr); + } + self.cache_valid = true; + } + + fn read_memory_byte(&self, address: u32) -> u8 { + let pbr = (address >> 16) & 0xFF; + if pbr <= 0x5F { + return self.read_rom_byte(address); + } + let ram_address = (usize::from((pbr & 0x01) as u8) << 16) | (address & 0xFFFF) as usize; + self.read_ram_raw_usize(ram_address) + } + + fn read_rom_byte(&self, address: u32) -> u8 { + superfx_rom_index(address, self.rom.len()) + .map(|index| self.rom[index]) + .unwrap_or(0) + } + + fn set_register(&mut self, register: usize, value: u16) { + self.registers[register] = value; + self.set_zero_sign(value); + self.source = register; + self.destination = None; + } + + fn set_register_with_moves_flags(&mut self, register: usize, value: u16) { + self.registers[register] = value; + self.set_zero_sign(value); + self.overflow = value & 0x0080 != 0; + self.destination = None; + } + + fn move_register(&mut self, destination: usize, source: usize) { + self.registers[destination] = self.registers[source]; + self.destination = None; + } + + fn load_register(&mut self, register: usize, value: u16) { + self.registers[register] = value; + if register == 0 { + self.source = 0; + } + } + + fn compare_register(&mut self, register: usize) { + let lhs = self.read_alu_source(); + let rhs = self.registers[register]; + let result = lhs.wrapping_sub(rhs); + self.set_subtract_flags(lhs, rhs, result); + self.destination = None; + } + + fn add_register(&mut self, register: usize) { + let lhs = self.read_alu_source(); + let rhs = self.registers[register]; + let result = lhs.wrapping_add(rhs); + self.set_add_flags(lhs, rhs, result); + self.write_result(result); + } + + fn add_immediate(&mut self, value: u16) { + let lhs = self.read_alu_source(); + let result = lhs.wrapping_add(value); + self.set_add_flags(lhs, value, result); + self.write_result(result); + } + + fn add_with_carry_register(&mut self, register: usize) { + self.add_with_carry(self.registers[register]); + } + + fn add_with_carry_immediate(&mut self, value: u16) { + self.add_with_carry(value); + } + + fn add_with_carry(&mut self, value: u16) { + let lhs = self.read_alu_source(); + let carry = u16::from(self.carry); + let result = lhs.wrapping_add(value).wrapping_add(carry); + self.set_zero_sign(result); + self.carry = u32::from(lhs) + u32::from(value) + u32::from(carry) > 0xFFFF; + self.overflow = (!(lhs ^ value) & (lhs ^ result) & 0x8000) != 0; + self.write_result(result); + } + + fn subtract_register(&mut self, register: usize) { + let lhs = self.read_alu_source(); + let rhs = self.registers[register]; + let result = lhs.wrapping_sub(rhs); + self.set_subtract_flags(lhs, rhs, result); + self.write_result(result); + } + + fn subtract_immediate(&mut self, value: u16) { + let lhs = self.read_alu_source(); + let result = lhs.wrapping_sub(value); + self.set_subtract_flags(lhs, value, result); + self.write_result(result); + } + + fn subtract_with_carry_register(&mut self, register: usize) { + let lhs = self.read_alu_source(); + let rhs = self.registers[register]; + let borrow = u16::from(!self.carry); + let subtrahend = rhs.wrapping_add(borrow); + let result = lhs.wrapping_sub(subtrahend); + self.set_zero_sign(result); + self.carry = u32::from(lhs) >= u32::from(rhs) + u32::from(borrow); + self.overflow = ((lhs ^ subtrahend) & (lhs ^ result) & 0x8000) != 0; + self.write_result(result); + } + + fn and_immediate(&mut self, value: u16) { + let result = self.read_alu_source() & value; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn bic_immediate(&mut self, value: u16) { + let result = self.read_alu_source() & !value; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn and_register(&mut self, register: usize) { + let result = self.read_alu_source() & self.registers[register]; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn bit_clear_register(&mut self, register: usize) { + let result = self.read_alu_source() & !self.registers[register]; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn or_register(&mut self, register: usize) { + let result = self.read_alu_source() | self.registers[register]; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn or_immediate(&mut self, value: u16) { + let result = self.read_alu_source() | value; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn xor_register(&mut self, register: usize) { + let result = self.read_alu_source() ^ self.registers[register]; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn xor_immediate(&mut self, value: u16) { + let result = self.read_alu_source() ^ value; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn merge_bytes(&mut self) { + let result = (self.registers[7] & 0xFF00) | (self.registers[8] >> 8); + let destination = self.destination.take().unwrap_or(0); + self.registers[destination] = result; + self.source = destination; + self.sign = result & 0x8080 != 0; + self.overflow = result & 0xC0C0 != 0; + self.carry = result & 0xE0E0 != 0; + self.zero = result & 0xF0F0 != 0; + } + + fn multiply_register(&mut self, register: usize) { + let a = self.read_alu_source() as i8 as i16; + let b = self.registers[register] as i8 as i16; + let result = (a * b) as u16; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn multiply_immediate(&mut self, value: u16) { + let a = self.read_alu_source() as i8 as i16; + let b = value as i8 as i16; + let result = (a * b) as u16; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn unsigned_multiply_register(&mut self, register: usize) { + let result = + u16::from(self.read_alu_source() as u8) * u16::from(self.registers[register] as u8); + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn unsigned_multiply_immediate(&mut self, value: u16) { + let result = u16::from(self.read_alu_source() as u8) * value; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn fractional_multiply(&mut self, long: bool) { + let product = + i32::from(self.read_alu_source() as i16) * i32::from(self.registers[6] as i16); + if long { + self.registers[4] = product as u16; + } + let result = (product >> 16) as u16; + self.clear_arithmetic_flags(); + let destination = self.destination.take().unwrap_or(0); + self.set_register(destination, result); + if result & 0x8000 != 0 { + self.carry = true; + } + } + + fn not(&mut self) { + let result = !self.read_alu_source(); + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn rotate_left(&mut self) { + let value = self.read_alu_source(); + let carry = self.carry; + self.carry = value & 0x8000 != 0; + self.overflow = false; + let result = (value << 1) | u16::from(carry); + self.write_result(result); + } + + fn shift_right(&mut self) { + self.carry = self.read_alu_source() & 0x0001 != 0; + self.overflow = false; + let result = self.read_alu_source() >> 1; + self.write_result(result); + } + + fn arithmetic_shift_right(&mut self) { + self.carry = self.read_alu_source() & 0x0001 != 0; + self.overflow = false; + let result = ((self.read_alu_source() as i16) >> 1) as u16; + self.write_result(result); + } + + fn divide_by_two(&mut self) { + let value = self.read_alu_source(); + self.carry = value & 0x0001 != 0; + self.overflow = false; + let result = if value == 0xFFFF { + 0 + } else { + ((value as i16) >> 1) as u16 + }; + self.write_result(result); + } + + fn rotate_right(&mut self) { + let value = self.read_alu_source(); + let carry = self.carry; + self.carry = value & 0x0001 != 0; + self.overflow = false; + let result = (value >> 1) | if carry { 0x8000 } else { 0 }; + self.write_result(result); + } + + fn link(&mut self, offset: u16) { + self.registers[11] = self.pc.wrapping_add(offset); + self.source = 11; + self.destination = None; + } + + fn high_byte(&mut self) { + let result = self.read_alu_source() >> 8; + self.clear_arithmetic_flags(); + self.write_byte_result(result); + } + + fn low_byte(&mut self) { + let result = self.read_alu_source() & 0x00FF; + self.clear_arithmetic_flags(); + self.write_byte_result(result); + } + + fn sign_extend(&mut self) { + let result = i16::from(self.read_alu_source() as u8 as i8) as u16; + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn swap_bytes(&mut self) { + let result = self.read_alu_source().swap_bytes(); + self.clear_arithmetic_flags(); + self.write_result(result); + } + + fn set_add_flags(&mut self, lhs: u16, rhs: u16, result: u16) { + self.set_zero_sign(result); + self.carry = u32::from(lhs) + u32::from(rhs) > 0xFFFF; + self.overflow = (!(lhs ^ rhs) & (lhs ^ result) & 0x8000) != 0; + } + + fn set_subtract_flags(&mut self, lhs: u16, rhs: u16, result: u16) { + self.set_zero_sign(result); + self.carry = lhs >= rhs; + self.overflow = ((lhs ^ rhs) & (lhs ^ result) & 0x8000) != 0; + } + + fn clear_arithmetic_flags(&mut self) { + self.carry = false; + self.overflow = false; + } + + fn getc_ramb_romb(&mut self, alt_mode: u8) { + match alt_mode { + 2 => self.rambr = self.registers[self.source] & 0x01 != 0, + 3 => self.rombr = self.registers[self.source] as u8 & 0x7F, + _ => { + let value = self.read_rom_buffer(); + self.apply_color_input(value); + } + } + self.destination = None; + } + + fn getb(&mut self, alt_mode: u8) { + let value = self.read_rom_buffer(); + let source = self.registers[self.source]; + let result = match alt_mode { + 1 => (u16::from(value) << 8) | (source & 0x00FF), + 2 => (source & 0xFF00) | u16::from(value), + 3 => value as i8 as i16 as u16, + _ => u16::from(value), + }; + self.write_load_result(result); + } + + fn read_rom_buffer(&self) -> u8 { + let address = (u32::from(self.rombr) << 16) | u32::from(self.registers[14]); + superfx_rom_index(address, self.rom.len()) + .map(|index| self.rom[index]) + .unwrap_or(0) + } + + fn read_alu_source(&self) -> u16 { + self.registers[self.source] + } + + fn write_result(&mut self, result: u16) { + let destination = self.destination.take().unwrap_or(0); + self.registers[destination] = result; + self.set_zero_sign(result); + self.source = 0; + self.destination = None; + } + + fn write_byte_result(&mut self, result: u16) { + let destination = self.destination.take().unwrap_or(0); + self.registers[destination] = result; + self.zero = result == 0; + self.sign = result & 0x0080 != 0; + self.source = destination; + } + + fn store_word(&mut self, register: usize) { + let address = self.registers[register]; + let value = self.read_alu_source(); + self.write_ram_word(address, value); + self.destination = None; + } + + fn store_byte(&mut self, register: usize) { + let address = self.registers[register]; + let value = self.read_alu_source() as u8; + self.write_ram(address, value); + self.destination = None; + } + + fn load_word(&mut self, register: usize) { + let address = self.registers[register]; + let value = self.read_ram_word(address); + self.write_load_result(value); + } + + fn load_byte(&mut self, register: usize) { + let value = u16::from(self.read_ram(self.registers[register])); + self.write_load_result(value); + } + + fn load_absolute_word(&mut self, register: usize, address: u16) { + let value = self.read_ram_word(address); + self.registers[register] = value; + self.source = register; + } + + fn store_absolute_word(&mut self, address: u16, register: usize) { + self.write_ram_word(address, self.registers[register]); + self.source = register; + self.destination = None; + } + + fn store_last_ram_word(&mut self) { + if let Some(address) = self.last_ram_address { + self.write_ram_word_raw( + address, + self.last_ram_word_swapped, + self.registers[self.source], + ); + } + self.destination = None; + } + + fn write_load_result(&mut self, value: u16) { + if let Some(destination) = self.destination.take() { + self.registers[destination] = value; + } else { + self.registers[0] = value; + self.source = 0; + } + } + + fn plot(&mut self) { + let x = usize::from(self.registers[1]); + let y = usize::from(self.registers[2]); + if let Some(color) = self.plot_color(x, y) { + let bit = 0x80 >> (x & 0x07); + let row_base = self.tile_row_base(x, y); + for plane in 0..self.bitmap_planes() { + let plane = usize::from(plane); + let byte_offset = row_base + (plane & 0x01) + (plane / 2) * 16; + let mut value = self.read_ram_raw_usize(byte_offset); + if color & (1 << plane) != 0 { + value |= bit; + } else { + value &= !bit; + } + self.write_ram_raw_usize(byte_offset, value); + } + } + self.registers[1] = self.registers[1].wrapping_add(1); + self.destination = None; + } + + fn read_pixel(&mut self) { + let x = usize::from(self.registers[1]); + let y = usize::from(self.registers[2]); + let bit = 0x80 >> (x & 0x07); + let row_base = self.tile_row_base(x, y); + let mut color = 0; + for plane in 0..self.bitmap_planes() { + let plane = usize::from(plane); + let byte_offset = row_base + (plane & 0x01) + (plane / 2) * 16; + if self.read_ram_raw_usize(byte_offset) & bit != 0 { + color |= 1 << plane; + } + } + self.write_result(color); + } + + fn apply_color_input(&mut self, value: u8) { + let mut value = value; + if self.plot_option & 0x04 != 0 { + value = (value & 0xF0) | (value >> 4); + } + if self.plot_option & 0x08 != 0 { + value = (self.color & 0xF0) | (value & 0x0F); + } + self.color = value; + } + + fn plot_color(&self, x: usize, y: usize) -> Option { + let mut color = self.color; + if self.bitmap_planes() != 8 && self.plot_option & 0x02 != 0 && (x ^ y) & 0x01 != 0 { + color >>= 4; + } + let mask = if self.bitmap_planes() == 8 { + 0xFF + } else { + (1 << self.bitmap_planes()) - 1 + }; + color &= mask; + if self.plot_option & 0x01 == 0 && color == 0 { + None + } else { + Some(color) + } + } + + fn bitmap_planes(&self) -> u8 { + match self.screen_mode & 0x03 { + 0 => 2, + 1 => 4, + 3 => 8, + _ => 4, + } + } + + fn tile_row_base(&self, x: usize, y: usize) -> usize { + let tile_index = if self.is_obj_mode() { + (y / 128) * 0x200 + (x / 128) * 0x100 + ((y / 8) & 0x0F) * 0x10 + ((x / 8) & 0x0F) + } else { + (x / 8) * self.screen_height_tiles() + (y / 8) + }; + let bytes_per_tile = usize::from(self.bitmap_planes()) * 8; + self.screen_base + tile_index * bytes_per_tile + (y & 0x07) * 2 + } + + fn is_obj_mode(&self) -> bool { + self.plot_option & 0x10 != 0 || self.screen_height_mode() == 3 + } + + fn screen_height_tiles(&self) -> usize { + match self.screen_height_mode() { + 1 => 20, + 2 => 24, + _ => 16, + } + } + + fn screen_height_mode(&self) -> u8 { + ((self.screen_mode >> 2) & 0x01) | ((self.screen_mode >> 4) & 0x02) + } + + fn read_ram(&mut self, address: u16) -> u8 { + let address = self.ram_raw_address(usize::from(address)); + self.last_ram_address = Some(address); + self.last_ram_word_swapped = false; + self.read_ram_raw_usize(address) + } + + fn read_ram_raw_usize(&self, address: usize) -> u8 { + if self.ram.is_empty() { + 0 + } else { + self.ram[address % self.ram.len()] + } + } + + fn write_ram(&mut self, address: u16, value: u8) { + let address = self.ram_raw_address(usize::from(address)); + self.last_ram_address = Some(address); + self.last_ram_word_swapped = false; + self.write_ram_raw_usize(address, value); + } + + fn read_ram_word(&mut self, address: u16) -> u16 { + let swapped = address & 0x0001 != 0; + let address = self.ram_raw_address(usize::from(address & !1)); + self.last_ram_address = Some(address); + self.last_ram_word_swapped = swapped; + let low = self.read_ram_raw_usize(address); + let high = self.read_ram_raw_usize(address + 1); + if swapped { + u16::from_le_bytes([high, low]) + } else { + u16::from_le_bytes([low, high]) + } + } + + fn write_ram_word(&mut self, address: u16, value: u16) { + let swapped = address & 0x0001 != 0; + let address = self.ram_raw_address(usize::from(address & !1)); + self.last_ram_address = Some(address); + self.last_ram_word_swapped = swapped; + self.write_ram_word_raw(address, swapped, value); + } + + fn write_ram_word_raw(&mut self, address: usize, swapped: bool, value: u16) { + let [low, high] = value.to_le_bytes(); + if swapped { + self.write_ram_raw_usize(address, high); + self.write_ram_raw_usize(address + 1, low); + } else { + self.write_ram_raw_usize(address, low); + self.write_ram_raw_usize(address + 1, high); + } + } + + fn ram_raw_address(&self, address: usize) -> usize { + (usize::from(self.rambr) << 16) | address + } + + fn write_ram_raw_usize(&mut self, address: usize, value: u8) { + if !self.ram.is_empty() { + self.ram[address % self.ram.len()] = value; + } + } +} + +fn superfx_rom_index(address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let address = address & 0x007F_FFFF; + let linear = if address & 0x00C0_0000 == 0 { + ((address & 0x003F_0000) >> 1) | (address & 0x0000_7FFF) + } else if address & 0x00E0_0000 == 0x0040_0000 { + address + } else { + return None; + }; + Some(linear as usize % rom_len) +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct Cx4State { + ram: Box<[u8; CX4_RAM_LEN]>, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct Cx4Point { + x: i16, + y: i16, + z: i16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct Cx4OamCursor { + oam: usize, + oam_hi: usize, + size_offset: u8, + sprite_slots: u8, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct Cx4OamEntry { + x: i16, + y: i16, + name: u8, + attributes: u8, + large: bool, +} + +const CX4_RAM_START: u16 = 0x6000; +const CX4_RAM_LEN: usize = 0x2000; +const CX4_LOAD_TRIGGER: u16 = 0x7F47; +const CX4_COMMAND_TRIGGER: u16 = 0x7F4F; +const CX4_BUSY_STATUS: u16 = 0x7F5E; +const CX4_DATA_START: usize = 0x1F80; +const CX4_COMMAND_MODE: usize = 0x1F4D; +const CX4_LOAD_SOURCE: usize = 0x1F40; +const CX4_LOAD_LEN: usize = 0x1F43; +const CX4_LOAD_DEST: usize = 0x1F45; +const CX4_IMMEDIATE_DATA: [u8; 48] = [ + 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, + 0xFF, 0xFF, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x7F, 0x00, 0x80, 0x00, 0xFF, 0x7F, 0x00, 0xFF, 0x7F, + 0xFF, 0x7F, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0xFE, 0x00, 0x01, 0x00, 0xFF, 0xFE, 0x00, +]; +const CX4_WAVE_DATA: [usize; 40] = [ + 0x0000, 0x0002, 0x0004, 0x0006, 0x0008, 0x000A, 0x000C, 0x000E, 0x0200, 0x0202, 0x0204, 0x0206, + 0x0208, 0x020A, 0x020C, 0x020E, 0x0400, 0x0402, 0x0404, 0x0406, 0x0408, 0x040A, 0x040C, 0x040E, + 0x0600, 0x0602, 0x0604, 0x0606, 0x0608, 0x060A, 0x060C, 0x060E, 0x0800, 0x0802, 0x0804, 0x0806, + 0x0808, 0x080A, 0x080C, 0x080E, +]; + +impl Cx4State { + fn new() -> Self { + Self { + ram: Box::new([0; CX4_RAM_LEN]), + } + } + + fn read(&self, address: u32) -> Option { + if is_cx4_absent_sram_address(address) { + return Some(0); + } + if !is_system_bank(address) { + return None; + } + + let offset = offset(address); + if offset == CX4_BUSY_STATUS { + return Some(0); + } + + self.index(offset).map(|index| self.ram[index]) + } + + fn write(&mut self, address: u32, value: u8, rom: &[u8]) -> bool { + if is_cx4_absent_sram_address(address) { + return true; + } + if !is_system_bank(address) { + return false; + } + + let offset = offset(address); + let Some(index) = self.index(offset) else { + return false; + }; + + self.ram[index] = value; + match offset { + CX4_LOAD_TRIGGER => self.load_rom_window(rom), + CX4_COMMAND_TRIGGER => self.execute_command(value, rom), + _ => {} + } + true + } + + fn index(&self, address_offset: u16) -> Option { + let relative = address_offset.checked_sub(CX4_RAM_START)? as usize; + (relative < self.ram.len()).then_some(relative) + } + + fn load_rom_window(&mut self, rom: &[u8]) { + let source = self.read_u24(CX4_LOAD_SOURCE); + let len = usize::from(self.read_u16(CX4_LOAD_LEN)); + let dest = usize::from(self.read_u16(CX4_LOAD_DEST) & 0x1FFF); + + for byte_index in 0..len { + let Some(source_index) = + lorom_rom_index(source.wrapping_add(byte_index as u32), rom.len()) + else { + break; + }; + let dest_index = (dest + byte_index) % self.ram.len(); + self.ram[dest_index] = rom[source_index]; + } + } + + fn execute_command(&mut self, command: u8, rom: &[u8]) { + if self.ram[CX4_COMMAND_MODE] == 0x0E && command < 0x40 && command & 0x03 == 0 { + self.ram[CX4_DATA_START] = command >> 2; + return; + } + + match command { + 0x00 => self.command_sprite(rom), + 0x01 => self.command_draw_wireframe_clear(rom), + 0x05 => self.command_propulsion(), + 0x0D => self.command_set_vector_length(), + 0x10 => self.command_polar_to_rectangular(true), + 0x13 => self.command_polar_to_rectangular(false), + 0x15 => self.command_pythagorean(), + 0x1F => self.command_atan(), + 0x22 => self.command_trapezoid(), + 0x25 => self.command_multiply(), + 0x2D => self.command_transform_coordinates(), + 0x40 => self.command_sum(), + 0x54 => self.command_square(), + 0x5C => self.command_immediate_register_reset(), + 0x5E => self.command_immediate_register(0), + 0x60..=0x7C if command.is_multiple_of(2) => { + self.command_immediate_register(usize::from((command - 0x5E) / 2) * 3) + } + 0x89 => { + self.ram[CX4_DATA_START] = 0x36; + self.ram[CX4_DATA_START + 1] = 0x43; + self.ram[CX4_DATA_START + 2] = 0x05; + } + _ => {} + } + } + + fn command_sprite(&mut self, rom: &[u8]) { + match self.ram[CX4_COMMAND_MODE] { + 0x00 => self.command_build_oam(rom), + 0x03 => self.command_scale_rotate(0), + 0x05 => self.command_transform_lines(), + 0x07 => self.command_scale_rotate(64), + 0x08 => self.command_draw_wireframe(rom), + 0x0B => self.command_disintegrate(), + 0x0C => self.command_bitplane_wave(), + _ => {} + } + } + + fn command_build_oam(&mut self, rom: &[u8]) { + let oam = usize::from(self.ram[0x0626]) << 2; + let mut clear = 0x01FDusize; + while clear > oam { + self.ram[clear] = 0xE0; + if clear < 4 { + break; + } + clear -= 4; + } + + let global_x = self.read_u16(0x0621); + let global_y = self.read_u16(0x0623); + let oam_hi = 0x0200 + (usize::from(self.ram[0x0626]) >> 2); + if self.ram[0x0620] == 0 { + return; + } + + let mut cursor = Cx4OamCursor { + oam, + oam_hi, + size_offset: (self.ram[0x0626] & 0x03) * 2, + sprite_slots: 128u8.saturating_sub(self.ram[0x0626]), + }; + let mut source = 0x0220usize; + for _ in 0..self.ram[0x0620] { + if cursor.sprite_slots == 0 || source + 15 >= self.ram.len() { + break; + } + + let sprite_x = self.read_u16(source).wrapping_sub(global_x) as i16; + let sprite_y = self.read_u16(source + 2).wrapping_sub(global_y) as i16; + let name = self.ram[source + 5]; + let attributes = self.ram[source + 4] | self.ram[source + 6]; + let mut sprite_data = self.read_u24(source + 7); + + let sprite_count = cx4_rom_read(rom, sprite_data); + if sprite_count != 0 { + sprite_data = sprite_data.wrapping_add(1); + for _ in 0..sprite_count { + if cursor.sprite_slots == 0 { + break; + } + let flags = cx4_rom_read(rom, sprite_data); + let mut x = i16::from(cx4_rom_read(rom, sprite_data.wrapping_add(1)) as i8); + if attributes & 0x40 != 0 { + x = -x - if flags & 0x20 != 0 { 16 } else { 8 }; + } + x = x.wrapping_add(sprite_x); + if (-16..=272).contains(&i32::from(x)) { + let mut y = i16::from(cx4_rom_read(rom, sprite_data.wrapping_add(2)) as i8); + if attributes & 0x80 != 0 { + y = -y - if flags & 0x20 != 0 { 16 } else { 8 }; + } + y = y.wrapping_add(sprite_y); + if (-16..=224).contains(&i32::from(y)) { + self.write_oam_entry( + &mut cursor, + Cx4OamEntry { + x, + y, + name: name.wrapping_add(cx4_rom_read( + rom, + sprite_data.wrapping_add(3), + )), + attributes: attributes ^ (flags & 0xC0), + large: flags & 0x20 != 0, + }, + ); + } + } + sprite_data = sprite_data.wrapping_add(4); + } + } else { + self.write_oam_entry( + &mut cursor, + Cx4OamEntry { + x: sprite_x, + y: sprite_y, + name, + attributes, + large: true, + }, + ); + } + + source += 16; + } + } + + fn write_oam_entry(&mut self, cursor: &mut Cx4OamCursor, entry: Cx4OamEntry) { + if cursor.sprite_slots == 0 + || cursor.oam + 3 >= self.ram.len() + || cursor.oam_hi >= self.ram.len() + { + return; + } + + self.ram[cursor.oam] = entry.x as u8; + self.ram[cursor.oam + 1] = entry.y as u8; + self.ram[cursor.oam + 2] = entry.name; + self.ram[cursor.oam + 3] = entry.attributes; + let mask = 0x03 << cursor.size_offset; + self.ram[cursor.oam_hi] &= !mask; + if entry.x & 0x0100 != 0 { + self.ram[cursor.oam_hi] |= 0x01 << cursor.size_offset; + } + if entry.large { + self.ram[cursor.oam_hi] |= 0x02 << cursor.size_offset; + } + + cursor.oam += 4; + cursor.sprite_slots = cursor.sprite_slots.saturating_sub(1); + cursor.size_offset = (cursor.size_offset + 2) & 0x06; + if cursor.size_offset == 0 { + cursor.oam_hi += 1; + } + } + + fn command_propulsion(&mut self) { + let divisor = u32::from(self.read_u16(CX4_DATA_START + 3)); + let quotient = 0x1_0000u32.checked_div(divisor).unwrap_or(0x1_0000); + let output = (quotient * u32::from(self.read_u16(CX4_DATA_START + 1))) >> 8; + self.write_u16(CX4_DATA_START, output as u16); + } + + fn command_set_vector_length(&mut self) { + let x = f64::from(self.read_i16(CX4_DATA_START)); + let y = f64::from(self.read_i16(CX4_DATA_START + 3)); + let distance = f64::from(self.read_i16(CX4_DATA_START + 6)); + let radius = (x * x + y * y).sqrt(); + if radius == 0.0 { + self.write_u16(CX4_DATA_START + 9, 0); + self.write_u16(CX4_DATA_START + 12, 0); + return; + } + + self.write_i16(CX4_DATA_START + 9, (x * distance / radius * 0.98) as i16); + self.write_i16(CX4_DATA_START + 12, (y * distance / radius * 0.99) as i16); + } + + fn command_polar_to_rectangular(&mut self, signed_radius: bool) { + let angle = + f64::from(self.read_u16(CX4_DATA_START) & 0x01FF) * std::f64::consts::TAU / 512.0; + let raw_radius = i32::from(self.read_i16(CX4_DATA_START + 3)); + let radius = if signed_radius { + (raw_radius << 1) >> 1 + } else { + raw_radius + } as f64; + let scale = if signed_radius { 1.0 } else { 256.0 }; + let x = (radius * angle.cos() * scale) as i32; + let mut y = (radius * angle.sin() * scale) as i32; + if signed_radius { + y -= y >> 6; + } + self.write_u24(CX4_DATA_START + 6, x as u32); + self.write_u24(CX4_DATA_START + 9, y as u32); + } + + fn command_pythagorean(&mut self) { + let x = f64::from(self.read_i16(CX4_DATA_START)); + let y = f64::from(self.read_i16(CX4_DATA_START + 3)); + self.write_i16(CX4_DATA_START, (x.hypot(y)) as i16); + } + + fn command_atan(&mut self) { + let x = f64::from(self.read_i16(CX4_DATA_START)); + let y = f64::from(self.read_i16(CX4_DATA_START + 3)); + let angle = if x == 0.0 { + if y > 0.0 { 0x80 } else { 0x180 } + } else { + let mut result = (y / x).atan() / std::f64::consts::TAU * 512.0; + if x < 0.0 { + result += 0x100 as f64; + } + (result as i16) & 0x01FF + }; + self.write_u16(CX4_DATA_START + 6, angle as u16); + } + + fn command_trapezoid(&mut self) { + let angle1 = cx4_angle512(self.read_u16(CX4_DATA_START + 12) & 0x01FF); + let angle2 = cx4_angle512(self.read_u16(CX4_DATA_START + 15) & 0x01FF); + let tan1 = cx4_tan(angle1); + let tan2 = cx4_tan(angle2); + + let initial_y = i32::from(self.read_i16(CX4_DATA_START + 3)) + - i32::from(self.read_i16(CX4_DATA_START + 9)); + let origin_x = i32::from(self.read_i16(CX4_DATA_START)); + let center_x = i32::from(self.read_i16(CX4_DATA_START + 6)); + let width = i32::from(self.read_i16(CX4_DATA_START + 19)); + + for (line, y) in (0..225).zip(initial_y..) { + let (left, right) = if y < 0 { + (1, 0) + } else { + let left = (tan1 * f64::from(y)) as i32 - origin_x + center_x; + let right = (tan2 * f64::from(y)) as i32 - origin_x + center_x + width; + cx4_clip_trapezoid_span(left, right) + }; + self.ram[0x0800 + line] = left; + self.ram[0x0900 + line] = right; + } + } + + fn command_multiply(&mut self) { + let left = self.read_u24(CX4_DATA_START); + let right = self.read_u24(CX4_DATA_START + 3); + self.write_u24(CX4_DATA_START, left.wrapping_mul(right)); + } + + fn command_transform_coordinates(&mut self) { + let mut x = f64::from(self.read_i16(CX4_DATA_START + 1)); + let y = f64::from(self.read_i16(CX4_DATA_START + 4)); + let z = f64::from(self.read_i16(CX4_DATA_START + 7)); + let rotate_x = -cx4_angle128(self.ram[CX4_DATA_START + 9]); + let rotate_y = -cx4_angle128(self.ram[CX4_DATA_START + 10]); + let rotate_z = -cx4_angle128(self.ram[CX4_DATA_START + 11]); + let scale = f64::from(self.read_u16(CX4_DATA_START + 16)); + + let y2 = y * rotate_x.cos() - z * rotate_x.sin(); + let z2 = y * rotate_x.sin() + z * rotate_x.cos(); + + let x2 = x * rotate_y.cos() + z2 * rotate_y.sin(); + let y = x2 * rotate_z.sin() + y2 * rotate_z.cos(); + x = x2 * rotate_z.cos() - y2 * rotate_z.sin(); + + self.write_i16(CX4_DATA_START, (x * scale / 256.0) as i16); + self.write_i16(CX4_DATA_START + 3, (y * scale / 256.0) as i16); + } + + fn command_sum(&mut self) { + let sum = self.ram[..0x800] + .iter() + .fold(0u16, |sum, value| sum.wrapping_add(u16::from(*value))); + self.write_u16(CX4_DATA_START, sum); + } + + fn command_square(&mut self) { + let value = i64::from(self.read_i24(CX4_DATA_START)); + let squared = value * value; + self.write_u24(CX4_DATA_START + 3, squared as u32); + self.write_u24(CX4_DATA_START + 6, (squared >> 24) as u32); + } + + fn command_transform_lines(&mut self) { + let rotate_x = self.ram[CX4_DATA_START + 3]; + let rotate_y = self.ram[CX4_DATA_START + 6]; + let rotate_z = self.ram[CX4_DATA_START + 9]; + let scale = self.ram[CX4_DATA_START + 12]; + + let vertex_count = usize::from(self.read_u16(CX4_DATA_START)); + let max_vertices = if self.ram.len() > 10 { + (self.ram.len() - 11) / 0x10 + 1 + } else { + 0 + }; + for vertex in 0..vertex_count.min(max_vertices) { + let base = vertex * 0x10; + let (x, y) = cx4_transform_wireframe( + self.read_i16(base + 1), + self.read_i16(base + 5), + self.read_i16(base + 9), + rotate_x, + rotate_y, + rotate_z, + scale, + ); + self.write_i16(base + 1, x.wrapping_add(0x80)); + self.write_i16(base + 5, y.wrapping_add(0x50)); + } + + self.write_u16(0x0600, 23); + self.write_u16(0x0602, 0x60); + self.write_u16(0x0605, 0x40); + self.write_u16(0x0608, 23); + self.write_u16(0x060A, 0x60); + self.write_u16(0x060D, 0x40); + + let line_count = usize::from(self.read_u16(0x0B00)); + let max_line_sources = if self.ram.len() > 0x0B03 { + (self.ram.len() - 0x0B04) / 2 + 1 + } else { + 0 + }; + let max_line_outputs = if self.ram.len() > 0x0606 { + (self.ram.len() - 0x0607) / 8 + 1 + } else { + 0 + }; + for line in 0..line_count.min(max_line_sources).min(max_line_outputs) { + let source = 0x0B02 + line * 2; + let output = 0x0600 + line * 8; + let start = usize::from(self.ram[source]) << 4; + let end = usize::from(self.ram[source + 1]) << 4; + let (distance, step_x, step_y) = cx4_calc_wireframe( + self.read_i16(start + 1), + self.read_i16(start + 5), + self.read_i16(end + 1), + self.read_i16(end + 5), + ); + self.write_u16(output, distance); + self.write_i16(output + 2, step_x); + self.write_i16(output + 5, step_y); + } + } + + fn command_draw_wireframe_clear(&mut self, rom: &[u8]) { + for byte in self.ram[0x0300..0x0C00].iter_mut() { + *byte = 0; + } + self.command_draw_wireframe(rom); + } + + fn command_draw_wireframe(&mut self, rom: &[u8]) { + let mut line = self.read_u24(CX4_DATA_START); + for _ in 0..self.ram[0x0295] { + let point1 = if cx4_rom_read(rom, line) == 0xFF + && cx4_rom_read(rom, line.wrapping_add(1)) == 0xFF + { + let mut previous = line.wrapping_sub(5); + while cx4_rom_read(rom, previous.wrapping_add(2)) == 0xFF + && cx4_rom_read(rom, previous.wrapping_add(3)) == 0xFF + && previous >= 5 + { + previous = previous.wrapping_sub(5); + } + u32::from(self.ram[CX4_DATA_START + 2]) << 16 + | (u32::from(cx4_rom_read(rom, previous.wrapping_add(2))) << 8) + | u32::from(cx4_rom_read(rom, previous.wrapping_add(3))) + } else { + u32::from(self.ram[CX4_DATA_START + 2]) << 16 + | (u32::from(cx4_rom_read(rom, line)) << 8) + | u32::from(cx4_rom_read(rom, line.wrapping_add(1))) + }; + let point2 = u32::from(self.ram[CX4_DATA_START + 2]) << 16 + | (u32::from(cx4_rom_read(rom, line.wrapping_add(2))) << 8) + | u32::from(cx4_rom_read(rom, line.wrapping_add(3))); + let color = cx4_rom_read(rom, line.wrapping_add(4)); + self.draw_wireframe_line( + cx4_rom_read_point(rom, point1), + cx4_rom_read_point(rom, point2), + color, + ); + line = line.wrapping_add(5); + } + } + + fn draw_wireframe_line(&mut self, start: Cx4Point, end: Cx4Point, color: u8) { + let (x1, y1) = cx4_transform_wireframe_2( + start.x, + start.y, + start.z, + self.ram[CX4_DATA_START + 6], + self.ram[CX4_DATA_START + 7], + self.ram[CX4_DATA_START + 8], + self.ram[CX4_DATA_START + 16], + ); + let (x2, y2) = cx4_transform_wireframe_2( + end.x, + end.y, + end.z, + self.ram[CX4_DATA_START + 6], + self.ram[CX4_DATA_START + 7], + self.ram[CX4_DATA_START + 8], + self.ram[CX4_DATA_START + 16], + ); + + let mut x = (i32::from(x1) + 48) << 8; + let mut y = (i32::from(y1) + 48) << 8; + let end_x = (i32::from(x2) + 48) << 8; + let end_y = (i32::from(y2) + 48) << 8; + let (distance, step_x, step_y) = cx4_calc_wireframe( + (x >> 8) as i16, + (y >> 8) as i16, + (end_x >> 8) as i16, + (end_y >> 8) as i16, + ); + + for _ in 0..distance { + if x > 0xFF && y > 0xFF && x < 0x6000 && y < 0x6000 { + let pixel_x = (x >> 8) as usize; + let pixel_y = (y >> 8) as usize; + let address = ((pixel_y >> 3) << 8) - ((pixel_y >> 3) << 6) + + ((pixel_x >> 3) << 4) + + (pixel_y & 7) * 2 + + 0x0300; + let mask = 0x80 >> (pixel_x & 7); + if address + 1 < self.ram.len() { + self.ram[address] &= !mask; + self.ram[address + 1] &= !mask; + if color & 0x01 != 0 { + self.ram[address] |= mask; + } + if color & 0x02 != 0 { + self.ram[address + 1] |= mask; + } + } + } + x += i32::from(step_x); + y += i32::from(step_y); + } + } + + fn command_scale_rotate(&mut self, row_padding: usize) { + let angle = self.read_u16(CX4_DATA_START) & 0x01FF; + let scale_x = cx4_scale_factor(self.read_u16(CX4_DATA_START + 15)); + let scale_y = cx4_scale_factor(self.read_u16(CX4_DATA_START + 18)); + let (a, b, c, d) = cx4_scale_rotate_matrix(angle, scale_x, scale_y); + + let width = i32::from(self.ram[CX4_DATA_START + 9] & !7); + let height = i32::from(self.ram[CX4_DATA_START + 12] & !7); + let clear_len = ((width as usize + row_padding / 4) * height as usize) / 2; + for byte in self.ram.iter_mut().take(clear_len) { + *byte = 0; + } + + let center_x = i32::from(self.read_i16(CX4_DATA_START + 3)); + let center_y = i32::from(self.read_i16(CX4_DATA_START + 6)); + let mut line_x = (center_x << 12) - center_x * a - center_x * b; + let mut line_y = (center_y << 12) - center_y * c - center_y * d; + let mut output_index = 0i32; + let mut mask = 0x80; + + for _ in 0..height { + let mut source_x = line_x; + let mut source_y = line_y; + for _ in 0..width { + let sample_x = source_x >> 12; + let sample_y = source_y >> 12; + let pixel = if (0..width).contains(&sample_x) && (0..height).contains(&sample_y) { + let packed_index = sample_y as usize * width as usize + sample_x as usize; + let mut pixel = self + .ram + .get(0x0600 + (packed_index >> 1)) + .copied() + .unwrap_or(0); + if packed_index & 1 != 0 { + pixel >>= 4; + } + pixel &= 0x0F; + pixel + } else { + 0 + }; + + if output_index >= 0 { + self.write_bitplane_pixel(output_index as usize, mask, pixel); + } + mask >>= 1; + if mask == 0 { + mask = 0x80; + output_index += 32; + } + + source_x += a; + source_y += c; + } + + output_index += 2 + row_padding as i32; + if output_index & 0x10 != 0 { + output_index &= !0x10; + } else { + output_index -= width * 4 + row_padding as i32; + } + line_x += b; + line_y += d; + } + } + + fn command_disintegrate(&mut self) { + let center_x = i32::from(self.read_i16(CX4_DATA_START)); + let center_y = i32::from(self.read_i16(CX4_DATA_START + 3)); + let scale_x = i32::from(self.read_i16(CX4_DATA_START + 6)); + let width = i32::from(self.ram[CX4_DATA_START + 9]); + let height = i32::from(self.ram[CX4_DATA_START + 12]); + let scale_y = i32::from(self.read_i16(CX4_DATA_START + 15)); + + let clear_len = (width.max(0) as usize * height.max(0) as usize) / 2; + for byte in self.ram.iter_mut().take(clear_len) { + *byte = 0; + } + + let mut source_index = 0x0600usize; + let mut source_byte = self.ram[source_index]; + let mut source_low_nibble = true; + let mut source_y = -center_y * scale_y + (center_y << 8); + for _ in 0..height { + let mut source_x = -center_x * scale_x + (center_x << 8); + for _ in 0..width { + let pixel = if source_low_nibble { + source_byte & 0x0F + } else { + (source_byte >> 4) & 0x0F + }; + if !source_low_nibble { + source_index += 1; + source_byte = self.ram.get(source_index).copied().unwrap_or(0); + } + source_low_nibble = !source_low_nibble; + + let sample_x = source_x >> 8; + let sample_y = source_y >> 8; + if (0..width).contains(&sample_x) && (0..height).contains(&sample_y) { + let sample_x = sample_x as usize; + let sample_y = sample_y as usize; + let output_index = (sample_y >> 3) * width as usize * 4 + + (sample_x >> 3) * 32 + + (sample_y & 7) * 2; + let mask = 0x80 >> (sample_x & 7); + self.write_bitplane_pixel(output_index, mask, pixel); + } + source_x += scale_x; + } + source_y += scale_y; + } + } + + fn write_bitplane_pixel(&mut self, output_index: usize, mask: u8, pixel: u8) { + if output_index >= self.ram.len().saturating_sub(17) { + return; + } + if pixel & 0x01 != 0 { + self.ram[output_index] |= mask; + } + if pixel & 0x02 != 0 { + self.ram[output_index + 1] |= mask; + } + if pixel & 0x04 != 0 { + self.ram[output_index + 16] |= mask; + } + if pixel & 0x08 != 0 { + self.ram[output_index + 17] |= mask; + } + } + + fn command_bitplane_wave(&mut self) { + let mut dest = 0usize; + let mut wave = usize::from(self.ram[CX4_DATA_START + 3]); + for _ in 0..0x10 { + self.apply_bitplane_wave_group(dest, 0x0A00, &mut wave); + dest += 16; + self.apply_bitplane_wave_group(dest, 0x0A10, &mut wave); + dest += 16; + } + } + + fn apply_bitplane_wave_group(&mut self, dest: usize, source: usize, wave: &mut usize) { + let mut mask = 0xC0C0u16; + loop { + let start_height = -i16::from(self.ram[0x0B00 + *wave] as i8) - 16; + for (height, offset) in (start_height..).zip(CX4_WAVE_DATA) { + let index = dest + offset; + let mut value = self.read_u16(index) & !mask; + if height >= 0 { + value |= if height < 8 { + mask & self.read_u16(source + height as usize * 2) + } else { + mask & 0xFF00 + }; + } + self.write_u16(index, value); + } + *wave = (*wave + 1) & 0x7F; + mask = (mask >> 2) | (mask << 6); + if mask == 0xC0C0 { + break; + } + } + } + + fn command_immediate_register_reset(&mut self) { + self.write_u24(CX4_DATA_START, 0); + self.command_immediate_register(0); + } + + fn command_immediate_register(&mut self, start: usize) { + let mut address = self.read_u24(CX4_DATA_START); + for value in CX4_IMMEDIATE_DATA[start..].iter().copied() { + let index = (address & 0x0FFF) as usize; + if index < 0x0C00 { + self.ram[index] = value; + } + address = address.wrapping_add(1); + } + self.write_u24(CX4_DATA_START, address); + } + + fn read_u16(&self, index: usize) -> u16 { + u16::from_le_bytes([self.ram[index], self.ram[index + 1]]) + } + + fn read_i16(&self, index: usize) -> i16 { + i16::from_le_bytes([self.ram[index], self.ram[index + 1]]) + } + + fn read_u24(&self, index: usize) -> u32 { + u32::from(self.ram[index]) + | (u32::from(self.ram[index + 1]) << 8) + | (u32::from(self.ram[index + 2]) << 16) + } + + fn read_i24(&self, index: usize) -> i32 { + let value = self.read_u24(index) as i32; + if value & 0x80_0000 != 0 { + value | !0xFF_FFFF + } else { + value + } + } + + fn write_u16(&mut self, index: usize, value: u16) { + let [low, high] = value.to_le_bytes(); + self.ram[index] = low; + self.ram[index + 1] = high; + } + + fn write_i16(&mut self, index: usize, value: i16) { + self.write_u16(index, value as u16); + } + + fn write_u24(&mut self, index: usize, value: u32) { + self.ram[index] = value as u8; + self.ram[index + 1] = (value >> 8) as u8; + self.ram[index + 2] = (value >> 16) as u8; + } +} + +fn cx4_angle128(value: u8) -> f64 { + f64::from(value) * std::f64::consts::TAU / 128.0 +} + +fn cx4_scale_factor(raw: u16) -> i32 { + if raw & 0x8000 != 0 { + 0x7FFF + } else { + i32::from(raw) + } +} + +fn cx4_scale_rotate_matrix(angle: u16, scale_x: i32, scale_y: i32) -> (i32, i32, i32, i32) { + match angle { + 0 => (scale_x, 0, 0, scale_y), + 128 => (0, -scale_y, scale_x, 0), + 256 => (-scale_x, 0, 0, -scale_y), + 384 => (0, scale_y, -scale_x, 0), + _ => { + let sin = cx4_sin512(angle); + let cos = cx4_cos512(angle); + ( + (cos * scale_x) >> 15, + -((sin * scale_y) >> 15), + (sin * scale_x) >> 15, + (cos * scale_y) >> 15, + ) + } + } +} + +fn cx4_sin512(value: u16) -> i32 { + ((f64::from(value & 0x01FF) * std::f64::consts::TAU / 512.0).sin() * 32767.0).round() as i32 +} + +fn cx4_cos512(value: u16) -> i32 { + ((f64::from(value & 0x01FF) * std::f64::consts::TAU / 512.0).cos() * 32767.0).round() as i32 +} + +fn cx4_transform_wireframe( + x: i16, + y: i16, + z: i16, + rotate_x: u8, + rotate_y: u8, + rotate_z: u8, + scale: u8, +) -> (i16, i16) { + let c4x = f64::from(x); + let c4y = f64::from(y); + let c4z = f64::from(z) - 0x95 as f64; + + let angle_x = -cx4_angle128(rotate_x); + let y2 = c4y * angle_x.cos() - c4z * angle_x.sin(); + let z2 = c4y * angle_x.sin() + c4z * angle_x.cos(); + + let angle_y = -cx4_angle128(rotate_y); + let x2 = c4x * angle_y.cos() + z2 * angle_y.sin(); + let z = c4x * -angle_y.sin() + z2 * angle_y.cos(); + + let angle_z = -cx4_angle128(rotate_z); + let x = x2 * angle_z.cos() - y2 * angle_z.sin(); + let y = x2 * angle_z.sin() + y2 * angle_z.cos(); + + let projection = f64::from(scale) / (0x90 as f64 * (z + 0x95 as f64)) * 0x95 as f64; + ( + cx4_saturating_trunc_i16(x * projection), + cx4_saturating_trunc_i16(y * projection), + ) +} + +fn cx4_transform_wireframe_2( + x: i16, + y: i16, + z: i16, + rotate_x: u8, + rotate_y: u8, + rotate_z: u8, + scale: u8, +) -> (i16, i16) { + let c4x = f64::from(x); + let c4y = f64::from(y); + let c4z = f64::from(z); + + let angle_x = -cx4_angle128(rotate_x); + let y2 = c4y * angle_x.cos() - c4z * angle_x.sin(); + let z2 = c4y * angle_x.sin() + c4z * angle_x.cos(); + + let angle_y = -cx4_angle128(rotate_y); + let x2 = c4x * angle_y.cos() + z2 * angle_y.sin(); + let _z = c4x * -angle_y.sin() + z2 * angle_y.cos(); + + let angle_z = -cx4_angle128(rotate_z); + let x = x2 * angle_z.cos() - y2 * angle_z.sin(); + let y = x2 * angle_z.sin() + y2 * angle_z.cos(); + + let projection = f64::from(scale) / 256.0; + ( + cx4_saturating_trunc_i16(x * projection), + cx4_saturating_trunc_i16(y * projection), + ) +} + +fn cx4_saturating_trunc_i16(value: f64) -> i16 { + if value.is_nan() { + 0 + } else { + value.clamp(f64::from(i16::MIN), f64::from(i16::MAX)) as i16 + } +} + +fn cx4_calc_wireframe(x1: i16, y1: i16, x2: i16, y2: i16) -> (u16, i16, i16) { + let mut dx = i32::from(x2) - i32::from(x1); + let mut dy = i32::from(y2) - i32::from(y1); + + let distance = if dx.abs() > dy.abs() { + let distance = dx.abs() + 1; + dy = 256 * dy / dx.abs(); + dx = if dx < 0 { -256 } else { 256 }; + distance + } else if dy != 0 { + let distance = dy.abs() + 1; + dx = 256 * dx / dy.abs(); + dy = if dy < 0 { -256 } else { 256 }; + distance + } else { + 0 + }; + + (distance.max(1) as u16, dx as i16, dy as i16) +} + +fn cx4_rom_read(rom: &[u8], address: u32) -> u8 { + lorom_rom_index(address, rom.len()) + .map(|index| rom[index]) + .unwrap_or(0) +} + +fn cx4_rom_read_be_i16(rom: &[u8], address: u32) -> i16 { + i16::from_be_bytes([ + cx4_rom_read(rom, address), + cx4_rom_read(rom, address.wrapping_add(1)), + ]) +} + +fn cx4_rom_read_point(rom: &[u8], address: u32) -> Cx4Point { + Cx4Point { + x: cx4_rom_read_be_i16(rom, address), + y: cx4_rom_read_be_i16(rom, address.wrapping_add(2)), + z: cx4_rom_read_be_i16(rom, address.wrapping_add(4)), + } +} + +fn cx4_angle512(value: u16) -> f64 { + f64::from(value) * std::f64::consts::TAU / 512.0 +} + +fn cx4_tan(angle: f64) -> f64 { + let cosine = angle.cos(); + if cosine.abs() < f64::EPSILON { + f64::from(i32::MIN) + } else { + angle.sin() / cosine + } +} + +fn cx4_clip_trapezoid_span(left: i32, right: i32) -> (u8, u8) { + if left < 0 && right < 0 { + return (1, 0); + } + if left > 255 && right > 255 { + return (255, 254); + } + + (left.clamp(0, 255) as u8, right.clamp(0, 255) as u8) +} + +fn is_cx4_absent_sram_address(address: u32) -> bool { + matches!(bank(address) & 0x7F, 0x70..=0x77) && offset(address) < 0x8000 +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) struct Dsp1State { + variant: Dsp1Variant, + data: u8, + status: u8, + phase: Dsp1Phase, + command: u8, + expected_input_words: usize, + input_low_byte: u8, + input_words: Vec, + output_words: Vec, + output_index: usize, + matrices: [[[i16; 3]; 3]; 3], + projection: Dsp1ProjectionState, + raster_line: u16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Dsp1Variant { + Dsp1, + Dsp1B, +} + +impl Dsp1Variant { + fn rom_version(self) -> u16 { + match self { + Self::Dsp1 => 0x0100, + Self::Dsp1B => 0x0101, + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Dsp1Phase { + WaitingCommand, + ReadingData, + WritingData, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Dsp1Operation { + Multiply, + Multiply2, + MemoryTest, + MemorySize, + Radius, + Range, + Range2, + Inverse, + ProjectionParameter, + Raster, + ProjectObject, + Target, + SetMatrix(Dsp1MatrixKind), + ObjectiveMatrix(Dsp1MatrixKind), + SubjectiveMatrix(Dsp1MatrixKind), + ScalarProduct(Dsp1MatrixKind), + Trigonometric, + Rotate2d, + Rotate3d, + AttitudeDelta, + VectorLength, + MemoryDump, + Unsupported, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum Dsp1MatrixKind { + A, + B, + C, +} + +impl Dsp1MatrixKind { + fn index(self) -> usize { + match self { + Self::A => 0, + Self::B => 1, + Self::C => 2, + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +struct Dsp1ProjectionState { + fx: i16, + fy: i16, + fz: i16, + lfe: i16, + les: i16, + aas: u16, + azs: u16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct Dsp1CommandSpec { + reads: usize, + writes: usize, + operation: Dsp1Operation, +} + +const DSP1_STATUS_DRC: u8 = 0x04; +const DSP1_STATUS_DRS: u8 = 0x10; +const DSP1_STATUS_RQM: u8 = 0x80; +const DSP1_RESET_STATUS: u8 = DSP1_STATUS_DRC | DSP1_STATUS_RQM; + +impl Dsp1State { + fn new(variant: Dsp1Variant) -> Self { + Self { + variant, + data: 0, + status: DSP1_RESET_STATUS, + phase: Dsp1Phase::WaitingCommand, + command: 0, + expected_input_words: 0, + input_low_byte: 0, + input_words: Vec::new(), + output_words: Vec::new(), + output_index: 0, + matrices: [[[0; 3]; 3]; 3], + projection: Dsp1ProjectionState::default(), + raster_line: 0, + } + } + + fn peek(&self, mapper_kind: MapperKind, address: u32, rom_len: usize) -> Option { + let register_offset = dsp1_register_offset(self.variant, mapper_kind, address, rom_len)?; + Some(if register_offset & 1 == 0 { + self.peek_data() + } else { + self.status + }) + } + + fn read(&mut self, mapper_kind: MapperKind, address: u32, rom_len: usize) -> Option { + let register_offset = dsp1_register_offset(self.variant, mapper_kind, address, rom_len)?; + Some(if register_offset & 1 == 0 { + self.read_data() + } else { + self.status + }) + } + + fn write(&mut self, mapper_kind: MapperKind, address: u32, value: u8, rom_len: usize) -> bool { + if let Some(register_offset) = + dsp1_register_offset(self.variant, mapper_kind, address, rom_len) + { + if register_offset & 1 == 0 { + self.write_data(value); + } + true + } else { + false + } + } + + fn peek_data(&self) -> u8 { + if self.phase != Dsp1Phase::WritingData { + return self.data; + } + + let word = self + .output_words + .get(self.output_index) + .copied() + .unwrap_or(0x0080); + if self.status & DSP1_STATUS_DRS == 0 { + word as u8 + } else { + (word >> 8) as u8 + } + } + + fn read_data(&mut self) -> u8 { + if self.phase != Dsp1Phase::WritingData { + return self.data; + } + + self.prepare_next_raster_output_if_needed(); + let word = self + .output_words + .get(self.output_index) + .copied() + .unwrap_or(0x0080); + if self.status & DSP1_STATUS_DRS == 0 { + self.status |= DSP1_STATUS_DRS; + let value = word as u8; + self.data = value; + return value; + } + + self.status &= !DSP1_STATUS_DRS; + let value = (word >> 8) as u8; + self.data = value; + self.output_index += 1; + if self.output_index >= self.output_words.len() { + if self.current_command_is_raster() { + self.status = (self.status & !DSP1_STATUS_DRS) | DSP1_STATUS_RQM; + } else { + self.finish_command(); + } + } + value + } + + fn write_data(&mut self, value: u8) { + self.data = value; + match self.phase { + Dsp1Phase::WaitingCommand => self.start_command(value), + Dsp1Phase::ReadingData => self.write_input_byte(value), + Dsp1Phase::WritingData if self.raster_output_drained() => self.start_command(value), + Dsp1Phase::WritingData => {} + } + } + + fn start_command(&mut self, value: u8) { + if value & 0xC0 != 0 { + return; + } + + self.command = value & 0x3F; + let spec = dsp1_command_spec(self.command); + + self.status = DSP1_STATUS_RQM; + self.expected_input_words = spec.reads; + self.input_low_byte = 0; + self.input_words.clear(); + self.output_words.clear(); + self.output_index = 0; + if spec.reads == 0 { + self.execute_command(spec); + } else { + self.phase = Dsp1Phase::ReadingData; + } + } + + fn write_input_byte(&mut self, value: u8) { + if self.status & DSP1_STATUS_DRS == 0 { + self.input_low_byte = value; + self.status |= DSP1_STATUS_DRS; + return; + } + + self.status &= !DSP1_STATUS_DRS; + self.input_words + .push(u16::from_le_bytes([self.input_low_byte, value])); + if self.input_words.len() >= self.expected_input_words { + self.execute_command(dsp1_command_spec(self.command)); + } + } + + fn execute_command(&mut self, spec: Dsp1CommandSpec) { + self.output_words = match spec.operation { + Dsp1Operation::Multiply => { + vec![dsp1_multiply(self.input_words[0], self.input_words[1], 0)] + } + Dsp1Operation::Multiply2 => { + vec![dsp1_multiply(self.input_words[0], self.input_words[1], 1)] + } + Dsp1Operation::MemoryTest => vec![0x0000], + Dsp1Operation::MemorySize => vec![self.variant.rom_version()], + Dsp1Operation::Radius => dsp1_radius(&self.input_words), + Dsp1Operation::Range => vec![dsp1_range(&self.input_words, 0)], + Dsp1Operation::Range2 => vec![dsp1_range(&self.input_words, 1)], + Dsp1Operation::Inverse => dsp1_inverse(&self.input_words), + Dsp1Operation::ProjectionParameter => { + self.projection = Dsp1ProjectionState::from_words(&self.input_words); + self.projection.parameter() + } + Dsp1Operation::Raster => self.start_raster_output(self.input_words[0]), + Dsp1Operation::ProjectObject => self.projection.project(&self.input_words), + Dsp1Operation::Target => self.projection.target(&self.input_words), + Dsp1Operation::SetMatrix(kind) => { + self.matrices[kind.index()] = dsp1_attitude_matrix(&self.input_words); + Vec::new() + } + Dsp1Operation::ObjectiveMatrix(kind) => { + dsp1_objective_matrix(&self.matrices[kind.index()], &self.input_words) + } + Dsp1Operation::SubjectiveMatrix(kind) => { + dsp1_subjective_matrix(&self.matrices[kind.index()], &self.input_words) + } + Dsp1Operation::ScalarProduct(kind) => { + vec![dsp1_scalar_product( + &self.matrices[kind.index()], + &self.input_words, + )] + } + Dsp1Operation::Trigonometric => dsp1_trigonometric(&self.input_words), + Dsp1Operation::Rotate2d => dsp1_rotate_2d(&self.input_words), + Dsp1Operation::Rotate3d => dsp1_rotate_3d(&self.input_words), + Dsp1Operation::AttitudeDelta => dsp1_attitude_delta(&self.input_words), + Dsp1Operation::VectorLength => vec![dsp1_vector_length(&self.input_words)], + Dsp1Operation::MemoryDump => vec![0; spec.writes], + Dsp1Operation::Unsupported => vec![0; spec.writes], + }; + self.output_index = 0; + self.status &= !DSP1_STATUS_DRS; + if self.output_words.is_empty() { + self.finish_command(); + } else { + self.phase = Dsp1Phase::WritingData; + } + } + + fn finish_command(&mut self) { + self.data = 0x80; + self.status = DSP1_RESET_STATUS; + self.phase = Dsp1Phase::WaitingCommand; + self.expected_input_words = 0; + self.input_words.clear(); + self.output_words.clear(); + self.output_index = 0; + } + + fn start_raster_output(&mut self, screen_line: u16) -> Vec { + self.raster_line = screen_line.wrapping_add(1); + self.projection.raster(screen_line) + } + + fn prepare_next_raster_output_if_needed(&mut self) { + if !self.raster_output_drained() { + return; + } + + let screen_line = self.raster_line; + self.output_words = self.projection.raster(screen_line); + self.raster_line = screen_line.wrapping_add(1); + self.output_index = 0; + self.status = (self.status & !DSP1_STATUS_DRS) | DSP1_STATUS_RQM; + } + + fn raster_output_drained(&self) -> bool { + self.current_command_is_raster() + && !self.output_words.is_empty() + && self.output_index >= self.output_words.len() + } + + fn current_command_is_raster(&self) -> bool { + matches!( + dsp1_command_spec(self.command).operation, + Dsp1Operation::Raster + ) + } +} + +fn dsp1_command_spec(command: u8) -> Dsp1CommandSpec { + use Dsp1MatrixKind as Matrix; + use Dsp1Operation as Op; + + let (reads, writes, operation) = match command { + 0x00 => (2, 1, Op::Multiply), + 0x01 | 0x05 | 0x31 | 0x35 => (4, 0, Op::SetMatrix(Matrix::A)), + 0x11 | 0x15 => (4, 0, Op::SetMatrix(Matrix::B)), + 0x21 | 0x25 => (4, 0, Op::SetMatrix(Matrix::C)), + 0x02 | 0x12 | 0x22 | 0x32 => (7, 4, Op::ProjectionParameter), + 0x03 | 0x33 => (3, 3, Op::SubjectiveMatrix(Matrix::A)), + 0x13 => (3, 3, Op::SubjectiveMatrix(Matrix::B)), + 0x23 => (3, 3, Op::SubjectiveMatrix(Matrix::C)), + 0x04 | 0x24 => (2, 2, Op::Trigonometric), + 0x06 | 0x16 | 0x26 | 0x36 => (3, 3, Op::ProjectObject), + 0x07 | 0x0F => (1, 1, Op::MemoryTest), + 0x08 => (3, 2, Op::Radius), + 0x0A | 0x1A | 0x2A | 0x3A => (1, 4, Op::Raster), + 0x0B | 0x3B => (3, 1, Op::ScalarProduct(Matrix::A)), + 0x1B => (3, 1, Op::ScalarProduct(Matrix::B)), + 0x2B => (3, 1, Op::ScalarProduct(Matrix::C)), + 0x0C | 0x2C => (3, 2, Op::Rotate2d), + 0x09 | 0x0D | 0x39 | 0x3D => (3, 3, Op::ObjectiveMatrix(Matrix::A)), + 0x19 | 0x1D => (3, 3, Op::ObjectiveMatrix(Matrix::B)), + 0x29 | 0x2D => (3, 3, Op::ObjectiveMatrix(Matrix::C)), + 0x0E | 0x1E | 0x2E | 0x3E => (2, 2, Op::Target), + 0x10 | 0x30 => (2, 2, Op::Inverse), + 0x14 | 0x34 => (6, 3, Op::AttitudeDelta), + 0x1C | 0x3C => (6, 3, Op::Rotate3d), + 0x18 => (4, 1, Op::Range), + 0x17 | 0x1F | 0x37 | 0x3F => (1, 1024, Op::MemoryDump), + 0x20 => (2, 1, Op::Multiply2), + 0x28 => (3, 1, Op::VectorLength), + 0x27 | 0x2F => (1, 1, Op::MemorySize), + 0x38 => (4, 1, Op::Range2), + _ => (0, 0, Op::Unsupported), + }; + + Dsp1CommandSpec { + reads, + writes, + operation, + } +} + +fn dsp1_multiply(left: u16, right: u16, round: i32) -> u16 { + let product = i32::from(left as i16) * i32::from(right as i16); + ((product >> 15) + round) as i16 as u16 +} + +fn dsp1_radius(input_words: &[u16]) -> Vec { + let sum = input_words + .iter() + .take(3) + .map(|value| { + let value = i64::from(*value as i16); + value * value + }) + .sum::() as u32; + vec![sum as u16, (sum >> 16) as u16] +} + +fn dsp1_range(input_words: &[u16], round: i64) -> u16 { + let sum = input_words + .iter() + .take(3) + .map(|value| { + let value = i64::from(*value as i16); + value * value + }) + .sum::(); + let radius = i64::from(input_words.get(3).copied().unwrap_or(0) as i16); + (((sum - radius * radius) >> 15) + round) as i16 as u16 +} + +fn dsp1_inverse(input_words: &[u16]) -> Vec { + let coefficient = input_words[0] as i16; + let mut exponent = input_words[1] as i16; + if coefficient == 0 { + return vec![0x7FFF, 0x002F]; + } + + let sign = if coefficient < 0 { -1 } else { 1 }; + let mut normalized = i32::from(coefficient); + if normalized < 0 { + normalized = (-normalized).min(i32::from(i16::MAX)); + } + while normalized < 0x4000 { + normalized <<= 1; + exponent = exponent.wrapping_sub(1); + } + + let reciprocal = if normalized == 0x4000 { + if sign > 0 { + i16::MAX + } else { + exponent = exponent.wrapping_sub(1); + -0x4000 + } + } else { + let value = (536_870_912.0 / f64::from(normalized)).round() as i16; + if sign < 0 { -value } else { value } + }; + + vec![reciprocal as u16, 1_i16.wrapping_sub(exponent) as u16] +} + +impl Dsp1ProjectionState { + fn from_words(input_words: &[u16]) -> Self { + Self { + fx: input_words[0] as i16, + fy: input_words[1] as i16, + fz: input_words[2] as i16, + lfe: input_words[3] as i16, + les: input_words[4] as i16, + aas: input_words[5], + azs: input_words[6], + } + } + + fn parameter(self) -> Vec { + let axes = self.axes(); + let center = self.center(&axes); + vec![ + 0, + dsp1_saturating_i16(f64::from(self.les) * axes.normal[2]), + dsp1_saturating_i16(center[0]), + dsp1_saturating_i16(center[1]), + ] + } + + fn raster(self, screen_line: u16) -> Vec { + let axes = self.axes(); + let line = f64::from(screen_line as i16); + let depth = (f64::from(self.les) + line * axes.normal[2]).max(1.0); + let scale = f64::from(self.les) / depth * 256.0; + vec![ + dsp1_saturating_i16(scale * axes.horizontal[0]), + dsp1_saturating_i16(scale * -axes.vertical[0]), + dsp1_saturating_i16(scale * axes.horizontal[1]), + dsp1_saturating_i16(scale * axes.vertical[1]), + ] + } + + fn project(self, input_words: &[u16]) -> Vec { + let axes = self.axes(); + let center = self.center(&axes); + let point = [ + f64::from(input_words[0] as i16), + f64::from(input_words[1] as i16), + f64::from(input_words[2] as i16), + ]; + let relative = [ + point[0] - center[0], + point[1] - center[1], + point[2] - center[2], + ]; + let depth = (f64::from(self.les) + dot3(relative, axes.normal)).max(1.0); + let scale = f64::from(self.les) / depth; + vec![ + dsp1_saturating_i16(dot3(relative, axes.horizontal) * scale), + dsp1_saturating_i16(dot3(relative, axes.vertical) * scale), + dsp1_saturating_i16(scale * 256.0), + ] + } + + fn target(self, input_words: &[u16]) -> Vec { + let axes = self.axes(); + let center = self.center(&axes); + let h = f64::from(input_words[0] as i16); + let v = f64::from(input_words[1] as i16); + let target = [ + center[0] + h * axes.horizontal[0] + v * axes.vertical[0], + center[1] + h * axes.horizontal[1] + v * axes.vertical[1], + ]; + vec![ + dsp1_saturating_i16(target[0]), + dsp1_saturating_i16(target[1]), + ] + } + + fn center(self, axes: &Dsp1ProjectionAxes) -> [f64; 3] { + let lfe = f64::from(self.lfe); + [ + f64::from(self.fx) + lfe * axes.normal[0], + f64::from(self.fy) + lfe * axes.normal[1], + f64::from(self.fz) + lfe * axes.normal[2], + ] + } + + fn axes(self) -> Dsp1ProjectionAxes { + let aas = dsp1_angle(self.aas); + let azs = dsp1_angle(self.azs); + let sin_aas = aas.sin(); + let cos_aas = aas.cos(); + let sin_azs = azs.sin(); + let cos_azs = azs.cos(); + + Dsp1ProjectionAxes { + normal: [-sin_azs * sin_aas, sin_azs * cos_aas, cos_azs], + horizontal: [cos_aas, sin_aas, 0.0], + vertical: [-cos_azs * sin_aas, cos_azs * cos_aas, -sin_azs], + } + } +} + +struct Dsp1ProjectionAxes { + normal: [f64; 3], + horizontal: [f64; 3], + vertical: [f64; 3], +} + +fn dot3(left: [f64; 3], right: [f64; 3]) -> f64 { + left[0] * right[0] + left[1] * right[1] + left[2] * right[2] +} + +fn dsp1_attitude_matrix(input_words: &[u16]) -> [[i16; 3]; 3] { + let scale = f64::from((input_words[0] as i16) >> 1); + let z_angle = dsp1_angle(input_words[1]); + let y_angle = dsp1_angle(input_words[2]); + let x_angle = dsp1_angle(input_words[3]); + let sin_z = z_angle.sin(); + let cos_z = z_angle.cos(); + let sin_y = y_angle.sin(); + let cos_y = y_angle.cos(); + let sin_x = x_angle.sin(); + let cos_x = x_angle.cos(); + + [ + [ + dsp1_saturating_i16_value(scale * cos_z * cos_y), + dsp1_saturating_i16_value(-(scale * sin_z * cos_y)), + dsp1_saturating_i16_value(scale * sin_y), + ], + [ + dsp1_saturating_i16_value(scale * sin_z * cos_x + scale * cos_z * sin_x * sin_y), + dsp1_saturating_i16_value(scale * cos_z * cos_x - scale * sin_z * sin_x * sin_y), + dsp1_saturating_i16_value(-(scale * sin_x * cos_y)), + ], + [ + dsp1_saturating_i16_value(scale * sin_z * sin_x - scale * cos_z * cos_x * sin_y), + dsp1_saturating_i16_value(scale * cos_z * sin_x + scale * sin_z * cos_x * sin_y), + dsp1_saturating_i16_value(scale * cos_x * cos_y), + ], + ] +} + +fn dsp1_objective_matrix(matrix: &[[i16; 3]; 3], input_words: &[u16]) -> Vec { + let vector = dsp1_vector3(input_words); + matrix + .iter() + .map(|row| { + let sum: i64 = (0..3) + .map(|index| i64::from(vector[index]) * i64::from(row[index])) + .sum(); + dsp1_saturating_i16_i64(sum >> 15) + }) + .collect() +} + +fn dsp1_subjective_matrix(matrix: &[[i16; 3]; 3], input_words: &[u16]) -> Vec { + let vector = dsp1_vector3(input_words); + (0..3) + .map(|column| { + let sum: i64 = (0..3) + .map(|row| i64::from(vector[row]) * i64::from(matrix[row][column])) + .sum(); + dsp1_saturating_i16_i64(sum >> 15) + }) + .collect() +} + +fn dsp1_scalar_product(matrix: &[[i16; 3]; 3], input_words: &[u16]) -> u16 { + let vector = dsp1_vector3(input_words); + let sum: i64 = (0..3) + .map(|index| i64::from(vector[index]) * i64::from(matrix[0][index])) + .sum(); + dsp1_saturating_i16_i64(sum >> 15) +} + +fn dsp1_trigonometric(input_words: &[u16]) -> Vec { + let angle = dsp1_angle(input_words[0]); + let radius = f64::from(input_words[1] as i16); + vec![ + dsp1_saturating_i16(radius * angle.sin()), + dsp1_saturating_i16(radius * angle.cos()), + ] +} + +fn dsp1_rotate_2d(input_words: &[u16]) -> Vec { + let angle = dsp1_angle(input_words[0]); + let x = f64::from(input_words[1] as i16); + let y = f64::from(input_words[2] as i16); + vec![ + dsp1_saturating_i16(y * angle.sin() + x * angle.cos()), + dsp1_saturating_i16(y * angle.cos() - x * angle.sin()), + ] +} + +fn dsp1_rotate_3d(input_words: &[u16]) -> Vec { + let z_angle = dsp1_angle(input_words[0]); + let y_angle = dsp1_angle(input_words[1]); + let x_angle = dsp1_angle(input_words[2]); + let x = f64::from(input_words[3] as i16); + let y = f64::from(input_words[4] as i16); + let z = f64::from(input_words[5] as i16); + + let x_after_z = y * z_angle.sin() + x * z_angle.cos(); + let y_after_z = y * z_angle.cos() - x * z_angle.sin(); + + let z_after_y = x_after_z * y_angle.sin() + z * y_angle.cos(); + let x_after_y = x_after_z * y_angle.cos() - z * y_angle.sin(); + + let y_after_x = z_after_y * x_angle.sin() + y_after_z * x_angle.cos(); + let z_after_x = z_after_y * x_angle.cos() - y_after_z * x_angle.sin(); + + vec![ + dsp1_saturating_i16(x_after_y), + dsp1_saturating_i16(y_after_x), + dsp1_saturating_i16(z_after_x), + ] +} + +fn dsp1_attitude_delta(input_words: &[u16]) -> Vec { + let z_rotation = input_words[0] as i16; + let x_rotation = input_words[1] as i16; + let y_rotation = input_words[2] as i16; + let u_delta = f64::from(input_words[3] as i16); + let f_delta = f64::from(input_words[4] as i16); + let l_delta = f64::from(input_words[5] as i16); + + let x_angle = dsp1_angle(input_words[1]); + let y_angle = dsp1_angle(input_words[2]); + let sin_y = y_angle.sin(); + let cos_y = y_angle.cos(); + let cos_x = x_angle.cos(); + let tan_x = x_angle.tan(); + + let z_delta = if cos_x.abs() < f64::EPSILON { + (u_delta * cos_y - f_delta * sin_y).signum() * f64::from(i16::MAX) + } else { + (u_delta * cos_y - f_delta * sin_y) / cos_x + }; + let x_delta = u_delta * sin_y + f_delta * cos_y; + let y_delta = l_delta - (u_delta * cos_y + f_delta * sin_y) * tan_x; + + vec![ + z_rotation.wrapping_add(dsp1_saturating_i16_value(z_delta)) as u16, + x_rotation.wrapping_add(dsp1_saturating_i16_value(x_delta)) as u16, + y_rotation.wrapping_add(dsp1_saturating_i16_value(y_delta)) as u16, + ] +} + +fn dsp1_vector_length(input_words: &[u16]) -> u16 { + let sum = input_words + .iter() + .take(3) + .map(|value| { + let value = f64::from(*value as i16); + value * value + }) + .sum::(); + dsp1_saturating_i16(sum.sqrt()) +} + +fn dsp1_vector3(input_words: &[u16]) -> [i16; 3] { + [ + input_words[0] as i16, + input_words[1] as i16, + input_words[2] as i16, + ] +} + +fn dsp1_angle(value: u16) -> f64 { + f64::from(value as i16) * std::f64::consts::TAU / 65536.0 +} + +fn dsp1_saturating_i16(value: f64) -> u16 { + dsp1_saturating_i16_value(value) as u16 +} + +fn dsp1_saturating_i16_value(value: f64) -> i16 { + value + .round() + .clamp(f64::from(i16::MIN), f64::from(i16::MAX)) as i16 +} + +fn dsp1_saturating_i16_i64(value: i64) -> u16 { + value.clamp(i64::from(i16::MIN), i64::from(i16::MAX)) as i16 as u16 +} + +#[derive(Debug, Clone, PartialEq, Eq)] +struct ByteWindow { + start: u16, + bytes: Vec, +} + +impl ByteWindow { + fn new(start: u16, len: usize) -> Self { + Self { + start, + bytes: vec![0; len], + } + } + + fn read(&self, address_offset: u16) -> Option { + self.index(address_offset).map(|index| self.bytes[index]) + } + + fn write(&mut self, address_offset: u16, value: u8) -> bool { + if let Some(index) = self.index(address_offset) { + self.bytes[index] = value; + true + } else { + false + } + } + + fn contains(&self, address_offset: u16) -> bool { + self.index(address_offset).is_some() + } + + fn index(&self, address_offset: u16) -> Option { + let relative = address_offset.checked_sub(self.start)? as usize; + (relative < self.bytes.len()).then_some(relative) + } +} + +fn dsp1_register_offset( + variant: Dsp1Variant, + mapper_kind: MapperKind, + address: u32, + rom_len: usize, +) -> Option { + let bank = bank(address) & 0x7F; + let offset = offset(address); + + match mapper_kind { + MapperKind::LoRom if rom_len > 0x100000 => match (bank, offset) { + (0x60..=0x6F, 0x0000..=0x3FFF) => Some(0), + (0x60..=0x6F, 0x4000..=0x7FFF) => Some(1), + _ => None, + }, + MapperKind::LoRom => match (bank, offset) { + (0x20..=0x3F, 0x8000..=0xBFFF) => Some(0), + (0x20..=0x3F, 0xC000..=0xFFFF) => Some(1), + _ => None, + }, + MapperKind::HiRom => match (bank, offset) { + (_, 0x6000..=0x6FFF) if dsp1_hirom_bank_matches(variant, bank) => Some(0), + (_, 0x7000..=0x7FFF) if dsp1_hirom_bank_matches(variant, bank) => Some(1), + _ => None, + }, + MapperKind::Sa1 => None, + } +} + +fn dsp1_hirom_bank_matches(variant: Dsp1Variant, bank: u8) -> bool { + match variant { + Dsp1Variant::Dsp1 => matches!(bank, 0x00..=0x1F), + Dsp1Variant::Dsp1B => matches!(bank, 0x00..=0x0F | 0x20..=0x2F), + } +} + +fn is_system_bank(address: u32) -> bool { + matches!(bank(address), 0x00..=0x3F | 0x80..=0xBF) +} + +fn is_sa1_rom_address(address: u32) -> bool { + (address & 0x408000) == 0x008000 || (address & 0xC00000) == 0xC00000 +} + +fn bank(address: u32) -> u8 { + ((address >> 16) & 0xFF) as u8 +} + +fn offset(address: u32) -> u16 { + (address & 0xFFFF) as u16 +} diff --git a/snes/core/src/lib.rs b/snes/core/src/lib.rs new file mode 100644 index 00000000..526d8fcf --- /dev/null +++ b/snes/core/src/lib.rs @@ -0,0 +1,678 @@ +mod apu; +mod bus; +mod cartridge; +mod cpu; +mod enhancement; +mod mapper; +mod memory; +mod ppu1; +mod ppu2; +mod scheduler; + +pub use cartridge::{Cartridge, CartridgeError, CartridgeHeader}; +pub use cpu::{CpuState, CpuStatus, Registers}; +pub use enhancement::EnhancementChip; +pub use mapper::MapperKind; +pub use ppu1::Mode7Registers; + +use bus::Bus; +use cpu::{Cpu, CpuFault}; +use nerust_sound_traits::MixerInput; +use scheduler::Scheduler; + +#[derive(Debug, thiserror::Error, PartialEq, Eq)] +pub enum CoreError { + #[error(transparent)] + Cartridge(#[from] CartridgeError), + #[error("unsupported SNES CPU opcode 0x{opcode:02X} at {bank:02X}:{address:04X}")] + UnsupportedOpcode { opcode: u8, bank: u8, address: u16 }, +} + +impl From for CoreError { + fn from(value: CpuFault) -> Self { + match value { + CpuFault::UnsupportedOpcode { + opcode, + bank, + address, + } => Self::UnsupportedOpcode { + opcode, + bank, + address, + }, + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct PresentedBackdropLine { + pub inidisp: u8, + pub color0: u16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct PresentedBg1Line { + pub hofs: u16, + pub vofs: u16, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct PresentedMainScreenLine { + pub tm: u8, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct PresentedColorWindowLine { + pub wh0: u8, + pub wh1: u8, + pub wh2: u8, + pub wh3: u8, +} + +pub struct Core { + cpu: Cpu, + bus: Bus, + scheduler: Scheduler, +} + +impl Core { + pub fn new(cartridge: Cartridge) -> Self { + Self { + cpu: Cpu::new(), + bus: Bus::new(cartridge), + scheduler: Scheduler::new(), + } + } + + pub fn from_rom_bytes(bytes: &[u8]) -> Result { + Ok(Self::new(Cartridge::from_bytes(bytes)?)) + } + + pub fn from_rom_bytes_with_msu1_data( + bytes: &[u8], + msu1_data: &[u8], + ) -> Result { + let mut cartridge = Cartridge::from_bytes(bytes)?; + cartridge.load_msu1_data(msu1_data); + Ok(Self::new(cartridge)) + } + + pub fn from_rom_bytes_with_msu1_sidecars( + bytes: &[u8], + msu1_data: Option<&[u8]>, + msu1_audio_tracks: &[u16], + ) -> Result { + let mut cartridge = Cartridge::from_bytes(bytes)?; + if let Some(msu1_data) = msu1_data { + cartridge.load_msu1_data(msu1_data); + } + cartridge.set_msu1_audio_tracks(msu1_audio_tracks.iter().copied()); + Ok(Self::new(cartridge)) + } + + pub fn step(&mut self) -> Result<(), CoreError> { + if self.cpu.current_state() == CpuState::Stopped { + return Ok(()); + } + let start_cycles = self.cpu.cycles(); + self.bus.tick_cpu_cycle(); + self.cpu.step(&mut self.bus); + self.scheduler + .advance(self.cpu.cycles().wrapping_sub(start_cycles)); + if let Some(fault) = self.cpu.take_fault() { + return Err(fault.into()); + } + Ok(()) + } + + /// Runs at least `cycles` CPU cycles, stopping early if the CPU stops. + /// + /// Execution is instruction-bounded and may overshoot the requested budget + /// by the remaining cycles in the current instruction. + pub fn run_for_cycles(&mut self, cycles: u64) -> Result<(), CoreError> { + self.scheduler + .run_for_cycles(&mut self.cpu, &mut self.bus, cycles) + .map_err(Into::into) + } + + pub fn run_for_cycles_with_audio( + &mut self, + cycles: u64, + mixer: &mut M, + ) -> Result<(), CoreError> { + self.scheduler + .run_for_cycles_with_audio(&mut self.cpu, &mut self.bus, cycles, mixer) + .map_err(Into::into) + } + + pub fn reset_cpu(&mut self) { + self.cpu.reset(); + self.bus.reset_ephemeral_state(); + self.scheduler.reset(); + } + + pub fn registers(&self) -> &Registers { + self.cpu.registers() + } + + pub fn cycles(&self) -> u64 { + self.cpu.cycles() + } + + pub fn master_cycles(&self) -> u64 { + self.scheduler.master_cycles() + } + + pub fn current_opcode(&self) -> u8 { + self.cpu.current_opcode() + } + + pub fn current_state(&self) -> CpuState { + self.cpu.current_state() + } + + pub fn cartridge(&self) -> &Cartridge { + self.bus.cartridge() + } + + pub fn export_save_ram(&self) -> Option> { + let save_ram = self.bus.cartridge().save_ram(); + (!save_ram.is_empty()).then(|| save_ram.to_vec()) + } + + pub fn load_save_ram(&mut self, save_ram: &[u8]) -> Result<(), CoreError> { + self.bus.cartridge_mut().load_save_ram(save_ram)?; + Ok(()) + } + + pub fn load_msu1_data(&mut self, data: &[u8]) { + self.bus.cartridge_mut().load_msu1_data(data); + } + + pub fn set_msu1_audio_tracks(&mut self, tracks: I) + where + I: IntoIterator, + { + self.bus.cartridge_mut().set_msu1_audio_tracks(tracks); + } + + pub fn set_standard_controller_buttons(&mut self, port: usize, buttons: u16) -> bool { + self.bus.set_standard_controller_buttons(port, buttons) + } + + pub fn peek(&self, address: u32) -> u8 { + self.bus.peek(address) + } + + pub fn peek_wram(&self, address: usize) -> u8 { + self.bus.memory.peek_wram(address) + } + + pub fn peek_apu_ram(&self, address: u16) -> u8 { + self.bus.peek_apu_ram(address) + } + + pub fn peek_vram(&self, address: usize) -> u8 { + self.bus.ppu1.peek_vram(address) + } + + pub fn peek_cgram(&self, index: usize) -> u8 { + self.bus.ppu2.peek_cgram(index) + } + + pub fn fixed_color(&self) -> u16 { + self.bus.ppu2.fixed_color() + } + + pub fn interlace_enabled(&self) -> bool { + self.bus.interlace_enabled() + } + + pub fn obj_interlace_enabled(&self) -> bool { + self.bus.obj_interlace_enabled() + } + + pub fn pseudo_hires_enabled(&self) -> bool { + self.bus.pseudo_hires_enabled() + } + + pub fn odd_frame(&self) -> bool { + self.bus.odd_frame() + } + + pub fn completed_odd_frame(&self) -> bool { + self.bus.completed_odd_frame() + } + + pub fn peek_oam(&self, address: usize) -> u8 { + self.bus.ppu1.peek_oam(address) + } + + pub fn bg1_hofs(&self) -> u16 { + self.bus.ppu1.bg1_hofs() + } + + pub fn bg1_vofs(&self) -> u16 { + self.bus.ppu1.bg1_vofs() + } + + pub fn bg2_hofs(&self) -> u16 { + self.bus.ppu1.bg2_hofs() + } + + pub fn bg2_vofs(&self) -> u16 { + self.bus.ppu1.bg2_vofs() + } + + pub fn bg3_hofs(&self) -> u16 { + self.bus.ppu1.bg3_hofs() + } + + pub fn bg3_vofs(&self) -> u16 { + self.bus.ppu1.bg3_vofs() + } + + pub fn bg4_hofs(&self) -> u16 { + self.bus.ppu1.bg4_hofs() + } + + pub fn bg4_vofs(&self) -> u16 { + self.bus.ppu1.bg4_vofs() + } + + pub fn mode7_registers(&self) -> Mode7Registers { + self.bus.ppu1.mode7_registers() + } + + pub fn presented_backdrop_line(&self, line: usize) -> Option { + self.bus.presented_backdrop_line(line) + } + + pub fn presented_bg1_line(&self, line: usize) -> Option { + self.bus.presented_bg1_line(line) + } + + pub fn presented_bg2_line(&self, line: usize) -> Option { + self.bus.presented_bg2_line(line) + } + + pub fn presented_bg3_line(&self, line: usize) -> Option { + self.bus.presented_bg3_line(line) + } + + pub fn presented_bg4_line(&self, line: usize) -> Option { + self.bus.presented_bg4_line(line) + } + + pub fn presented_main_screen_line(&self, line: usize) -> Option { + self.bus.presented_main_screen_line(line) + } + + pub fn presented_color_window_line(&self, line: usize) -> Option { + self.bus.presented_color_window_line(line) + } +} + +#[cfg(test)] +mod tests { + use super::{Core, CpuState, CpuStatus, MapperKind}; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + const IRQ_VECTOR_OFFSET: usize = 0x7FFE; + const HIROM_HEADER_OFFSET: usize = 0xFFC0; + const HIROM_RESET_VECTOR_OFFSET: usize = 0xFFFC; + + fn build_lorom(reset_vector: u16) -> Vec { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"TEST CORE ROM "); + rom[0x7FD5] = 0x30; + rom[0x7FD7] = 0x08; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&reset_vector.to_le_bytes()); + rom + } + + fn build_hirom(reset_vector: u16) -> Vec { + let mut rom = vec![0; 0x20000]; + rom[HIROM_HEADER_OFFSET..HIROM_HEADER_OFFSET + 21] + .copy_from_slice(b"TEST HIROM CORE "); + rom[0xFFD5] = 0x31; + rom[0xFFD7] = 0x09; + rom[HIROM_RESET_VECTOR_OFFSET..HIROM_RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&reset_vector.to_le_bytes()); + rom + } + + fn run_until_stopped(core: &mut Core, max_cycles: usize) { + for _ in 0..max_cycles { + core.step().unwrap(); + if core.current_state() == CpuState::Stopped { + return; + } + } + + panic!("core did not stop within {max_cycles} cycles"); + } + + #[test] + fn core_reset_fetches_the_lorom_reset_vector() { + let mut rom = build_lorom(0x8000); + rom[0] = 0xEA; + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + + for _ in 0..7 { + core.step().unwrap(); + } + + assert_eq!(core.registers().pc(), 0x8000); + assert_eq!(core.registers().pb(), 0x00); + assert_eq!(core.current_state(), CpuState::Running); + assert_eq!(core.cartridge().header().mapper_kind(), MapperKind::LoRom); + } + + #[test] + fn core_reset_fetches_the_hirom_reset_vector_and_program_byte() { + let mut rom = build_hirom(0x8000); + rom[0x8000] = 0xDB; + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 16); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.registers().pc(), 0x8001); + assert_eq!(core.cartridge().header().mapper_kind(), MapperKind::HiRom); + } + + #[test] + fn core_exports_and_restores_cartridge_save_ram() { + let mut rom = build_lorom(0x8000); + rom[0x7FD8] = 0x03; + let mut core = Core::from_rom_bytes(&rom).unwrap(); + let mut save_ram = vec![0x5A; core.export_save_ram().unwrap().len()]; + save_ram[0x0123] = 0xC3; + + core.load_save_ram(&save_ram).unwrap(); + + assert_eq!(core.export_save_ram().unwrap()[0x0123], 0xC3); + } + + #[test] + fn core_runs_basic_native_mode_bootstrap_sequence() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x0009] + .copy_from_slice(&[0x18, 0xFB, 0xC2, 0x30, 0xA2, 0xEF, 0x01, 0x9A, 0xDB]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 32); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.registers().x(), 0x01EF); + assert_eq!(core.registers().s(), 0x01EF); + assert!( + !core + .registers() + .status() + .contains(CpuStatus::ACCUMULATOR_8BIT | CpuStatus::INDEX_8BIT) + ); + } + + #[test] + fn core_run_for_cycles_matches_step_loop_until_stopped() { + let program = [0xEA, 0xEA, 0xDB]; + let mut rom = build_lorom(0x8000); + rom[..program.len()].copy_from_slice(&program); + + let mut stepped = Core::from_rom_bytes(&rom).unwrap(); + let mut scheduled = Core::from_rom_bytes(&rom).unwrap(); + + run_until_stopped(&mut stepped, 512); + scheduled.run_for_cycles(512).unwrap(); + + assert_eq!(scheduled.current_state(), CpuState::Stopped); + assert_eq!(scheduled.current_opcode(), stepped.current_opcode()); + assert_eq!(scheduled.registers(), stepped.registers()); + assert_eq!(scheduled.cycles(), stepped.cycles()); + assert_eq!(scheduled.master_cycles(), scheduled.cycles()); + } + + #[test] + fn core_run_for_cycles_fast_forwards_self_branch_idle_loop() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x0002].copy_from_slice(&[0x80, 0xFE]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + core.run_for_cycles(10_000).unwrap(); + + assert_eq!(core.current_state(), CpuState::Running); + assert_eq!(core.current_opcode(), 0x80); + assert_eq!(core.registers().pc(), 0x8000); + assert!(core.cycles() >= 10_000); + assert_eq!(core.master_cycles(), core.cycles()); + } + + #[test] + fn core_run_for_cycles_fast_forwards_absolute_jmp_idle_loop() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x0003].copy_from_slice(&[0x4C, 0x00, 0x80]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + core.run_for_cycles(10_000).unwrap(); + + assert_eq!(core.current_state(), CpuState::Running); + assert_eq!(core.current_opcode(), 0x4C); + assert_eq!(core.registers().pc(), 0x8000); + assert!(core.cycles() >= 10_000); + assert_eq!(core.master_cycles(), core.cycles()); + } + + #[test] + fn core_run_for_cycles_fast_forwards_wai_until_interrupt_event() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x0006].copy_from_slice(&[0xA9, 0x80, 0x8D, 0x00, 0x42, 0xCB]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + core.run_for_cycles(1_000).unwrap(); + + assert_eq!(core.current_state(), CpuState::Waiting); + assert_eq!(core.current_opcode(), 0xCB); + assert!(core.cycles() >= 1_000); + assert_eq!(core.master_cycles(), core.cycles()); + } + + #[test] + fn core_executes_bootstrap_rom_across_cpu_ppu_and_memory() { + let program = [ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA2, 0xEF, 0x01, 0x9A, 0xA9, 0x8F, 0x8D, 0x00, + 0x21, 0xA9, 0x80, 0x8D, 0x15, 0x21, 0x9C, 0x16, 0x21, 0x9C, 0x17, 0x21, 0xA9, 0x34, + 0x8D, 0x18, 0x21, 0xA9, 0x12, 0x8D, 0x19, 0x21, 0xA9, 0x01, 0x8D, 0x21, 0x21, 0xA9, + 0x7F, 0x8D, 0x22, 0x21, 0xA9, 0x00, 0x8D, 0x22, 0x21, 0x9C, 0x81, 0x21, 0x9C, 0x82, + 0x21, 0x9C, 0x83, 0x21, 0xA9, 0x5A, 0x8D, 0x80, 0x21, 0xDB, + ]; + + let mut rom = build_lorom(0x8000); + rom[..program.len()].copy_from_slice(&program); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 128); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.bus.ppu2.inidisp(), 0x8F); + assert_eq!(core.bus.ppu1.peek_vram(0), 0x34); + assert_eq!(core.bus.ppu1.peek_vram(1), 0x12); + assert_eq!(core.bus.ppu1.vmadd(), 0x0001); + assert_eq!(core.bus.ppu2.peek_cgram(2), 0x7F); + assert_eq!(core.bus.ppu2.peek_cgram(3), 0x00); + assert_eq!(core.peek(0x7E0000), 0x5A); + assert_eq!(core.bus.memory.wmadd(), 0x0001); + } + + #[test] + fn core_wai_suspends_until_nmi_fires() { + // 0xCB (WAI) is now supported: the core should enter Waiting state and + // NOT report an UnsupportedOpcode error. + let mut rom = build_lorom(0x8000); + // WAI followed by STP so we can check the state machine exits cleanly. + rom[0x0000] = 0xCB; // WAI + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + // Run reset (7 cycles) + fetch WAI (1) + execute WAI (1) = 9 total + for _ in 0..9 { + core.step().unwrap(); + } + assert_eq!(core.current_state(), CpuState::Waiting); + assert_eq!(core.current_opcode(), 0xCB); + } + + #[test] + fn core_vcounter_irq_wakes_wai_and_returns_through_timeup_handler() { + let mut rom = build_lorom(0x8000); + rom[IRQ_VECTOR_OFFSET..IRQ_VECTOR_OFFSET + 2].copy_from_slice(&0x9000u16.to_le_bytes()); + rom[0x0000..0x000C].copy_from_slice(&[ + 0xA0, 0x28, 0x8C, 0x09, 0x42, 0xA9, 0x20, 0x8D, 0x00, 0x42, 0x58, 0xCB, + ]); + rom[0x000C] = 0xDB; // STP after WAI returns + rom[0x1000..0x1004].copy_from_slice(&[0xAD, 0x11, 0x42, 0x40]); // LDA $4211 ; RTI + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 20_000); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.registers().pc(), 0x800D); + assert_eq!(core.peek(0x004211), 0x00); + } + + #[test] + fn core_combined_hv_irq_wakes_wai_and_returns_through_timeup_handler() { + let mut rom = build_lorom(0x8000); + rom[IRQ_VECTOR_OFFSET..IRQ_VECTOR_OFFSET + 2].copy_from_slice(&0x9000u16.to_le_bytes()); + rom[0x0000..0x0012].copy_from_slice(&[ + 0xA0, 0x14, 0x8C, 0x09, 0x42, // LDY #20 ; STY VTIME + 0xA0, 0x89, 0x8C, 0x07, 0x42, // LDY #137 ; STY HTIME + 0xA9, 0x30, 0x8D, 0x00, 0x42, // LDA #$30 ; STA NMITIMEN + 0x58, 0xCB, 0xDB, // CLI ; WAI ; STP + ]); + rom[0x1000..0x1004].copy_from_slice(&[0xAD, 0x11, 0x42, 0x40]); // LDA $4211 ; RTI + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 20_000); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.registers().pc(), 0x8012); + assert_eq!(core.peek(0x004211), 0x00); + } + + #[test] + fn core_recurring_hcounter_irq_allows_progress_after_rti() { + let mut rom = build_lorom(0x8000); + rom[IRQ_VECTOR_OFFSET..IRQ_VECTOR_OFFSET + 2].copy_from_slice(&0x9000u16.to_le_bytes()); + rom[0x0000..0x000F].copy_from_slice(&[ + 0xA9, 0x01, 0x8D, 0x07, 0x42, // LDA #$01 ; STA HTIMEL + 0xA9, 0x10, 0x8D, 0x00, 0x42, // LDA #$10 ; STA NMITIMEN + 0x58, 0xCB, 0xE6, 0x00, 0xDB, // CLI ; WAI ; INC $00 ; STP + ]); + rom[0x1000..0x1004].copy_from_slice(&[0xAD, 0x11, 0x42, 0x40]); // LDA $4211 ; RTI + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 1024); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.peek(0x7E0000), 0x01); + } + + #[test] + fn stepping_a_stopped_core_does_not_advance_vblank_stub() { + let mut rom = build_lorom(0x8000); + rom[0x0000] = 0xDB; + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 16); + + let before = core.peek(0x004210); + for _ in 0..8 { + core.step().unwrap(); + } + assert_eq!(core.peek(0x004210), before); + } + + #[test] + fn core_accepts_supported_vmain_remap_modes() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x0006].copy_from_slice(&[0xA9, 0x0C, 0x8D, 0x15, 0x21, 0xDB]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 32); + + assert_eq!(core.peek(0x002115), 0x0C); + } + + #[test] + fn core_can_wait_for_auto_joy_hvbjoy_pulse_and_read_zeroed_joy1() { + let mut rom = build_lorom(0x8000); + rom[0x0000..0x001A].copy_from_slice(&[ + 0xA9, 0x01, // LDA #$01 + 0x8D, 0x00, 0x42, // STA $4200 + 0xAD, 0x12, 0x42, // wait_set: LDA $4212 + 0x29, 0x01, // AND #$01 + 0xF0, 0xF9, // BEQ wait_set + 0xAD, 0x12, 0x42, // wait_clear: LDA $4212 + 0x29, 0x01, // AND #$01 + 0xD0, 0xF9, // BNE wait_clear + 0xAD, 0x18, 0x42, // LDA $4218 + 0x8D, 0x00, 0x00, // STA $0000 + 0xDB, // STP + ]); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 120_000); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.peek(0x7E0000), 0x00); + assert_eq!(core.peek(0x004218), 0x00); + } + + #[test] + fn core_can_pulse_joyout_and_observe_the_seventeenth_joyser0_read() { + let mut rom = build_lorom(0x8000); + let program = [ + 0xA9, 0x01, // LDA #$01 + 0x8D, 0x16, 0x40, // STA $4016 + 0xA9, 0x00, // LDA #$00 + 0x8D, 0x16, 0x40, // STA $4016 + 0xAD, 0x16, 0x40, // 1 + 0xAD, 0x16, 0x40, // 2 + 0xAD, 0x16, 0x40, // 3 + 0xAD, 0x16, 0x40, // 4 + 0xAD, 0x16, 0x40, // 5 + 0xAD, 0x16, 0x40, // 6 + 0xAD, 0x16, 0x40, // 7 + 0xAD, 0x16, 0x40, // 8 + 0xAD, 0x16, 0x40, // 9 + 0xAD, 0x16, 0x40, // 10 + 0xAD, 0x16, 0x40, // 11 + 0xAD, 0x16, 0x40, // 12 + 0xAD, 0x16, 0x40, // 13 + 0xAD, 0x16, 0x40, // 14 + 0xAD, 0x16, 0x40, // 15 + 0xAD, 0x16, 0x40, // 16 + 0xAD, 0x16, 0x40, // 17 + 0x8D, 0x00, 0x00, // STA $0000 + 0xDB, // STP + ]; + rom[..program.len()].copy_from_slice(&program); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 256); + + assert_eq!(core.current_state(), CpuState::Stopped); + assert_eq!(core.current_opcode(), 0xDB); + assert_eq!(core.peek(0x7E0000), 0x01); + } +} diff --git a/snes/core/src/mapper.rs b/snes/core/src/mapper.rs new file mode 100644 index 00000000..6cdf12bf --- /dev/null +++ b/snes/core/src/mapper.rs @@ -0,0 +1,319 @@ +const ADDRESS_MASK: u32 = 0x00FF_FFFF; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum MapperKind { + LoRom, + HiRom, + Sa1, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub(crate) enum Mapper { + LoRom(LoRomMapper), + HiRom(HiRomMapper), + Sa1(Sa1Mapper), +} + +impl Mapper { + pub(crate) fn read(&self, rom: &[u8], ram: &[u8], address: u32) -> Option { + self.ram_index(address, ram.len()) + .map(|index| ram[index]) + .or_else(|| self.read_rom(rom, address)) + } + + pub(crate) fn write_ram(&self, ram: &mut [u8], address: u32, value: u8) -> bool { + let Some(index) = self.ram_index(address, ram.len()) else { + return false; + }; + ram[index] = value; + true + } + + fn read_rom(&self, rom: &[u8], address: u32) -> Option { + match self { + Self::LoRom(mapper) => mapper.read_rom(rom, address), + Self::HiRom(mapper) => mapper.read_rom(rom, address), + Self::Sa1(mapper) => mapper.read_rom(rom, address), + } + } + + fn ram_index(&self, address: u32, ram_len: usize) -> Option { + match self { + Self::LoRom(_) => lorom_ram_index(address, ram_len), + Self::HiRom(_) => hirom_ram_index(address, ram_len), + Self::Sa1(_) => sa1_ram_index(address, ram_len), + } + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) struct LoRomMapper; + +impl LoRomMapper { + pub(crate) fn read_rom(&self, rom: &[u8], address: u32) -> Option { + lorom_rom_index(address, rom.len()).map(|index| rom[index]) + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) struct HiRomMapper; + +impl HiRomMapper { + pub(crate) fn read_rom(&self, rom: &[u8], address: u32) -> Option { + hirom_rom_index(address, rom.len()).map(|index| rom[index]) + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)] +pub(crate) struct Sa1Mapper; + +impl Sa1Mapper { + pub(crate) fn read_rom(&self, rom: &[u8], address: u32) -> Option { + sa1_rom_index(address, rom.len()).map(|index| rom[index]) + } +} + +pub(crate) fn lorom_rom_index(address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if (0x7E..=0x7F).contains(&bank) { + return None; + } + + let page = usize::from(bank & 0x7F); + let page_offset = match bank { + 0x00..=0x3F | 0x80..=0xBF => { + if offset < 0x8000 { + return None; + } + usize::from(offset - 0x8000) + } + _ => usize::from(offset & 0x7FFF), + }; + let linear = page * 0x8000 + page_offset; + Some(linear % rom_len) +} + +pub(crate) fn hirom_rom_index(address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if (0x7E..=0x7F).contains(&bank) { + return None; + } + + let page = usize::from(bank & 0x3F); + let page_offset = match bank { + 0x00..=0x3F | 0x80..=0xBF => { + if offset < 0x8000 { + return None; + } + usize::from(offset) + } + _ => usize::from(offset), + }; + let linear = page * 0x10000 + page_offset; + Some(linear % rom_len) +} + +pub(crate) fn sa1_rom_index(address: u32, rom_len: usize) -> Option { + if rom_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + match bank { + 0xC0..=0xFF => { + let linear = usize::from(bank - 0xC0) * 0x10000 + usize::from(offset); + Some(linear % rom_len) + } + _ => lorom_rom_index(address, rom_len), + } +} + +pub(crate) fn lorom_ram_index(address: u32, ram_len: usize) -> Option { + if ram_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if !matches!(bank, 0x70..=0x7D | 0xF0..=0xFF) || offset >= 0x8000 { + return None; + } + + let page = usize::from(bank & 0x0F); + let linear = page * 0x8000 + usize::from(offset); + Some(linear % ram_len) +} + +pub(crate) fn hirom_ram_index(address: u32, ram_len: usize) -> Option { + if ram_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + if !matches!(bank, 0x20..=0x3F | 0xA0..=0xBF) || !(0x6000..=0x7FFF).contains(&offset) { + return None; + } + + let page = usize::from(bank & 0x1F); + let linear = page * 0x2000 + usize::from(offset - 0x6000); + Some(linear % ram_len) +} + +pub(crate) fn sa1_ram_index(address: u32, ram_len: usize) -> Option { + if ram_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + let linear = match bank { + 0x00..=0x3F | 0x80..=0xBF if (0x6000..=0x7FFF).contains(&offset) => { + usize::from(offset - 0x6000) + } + 0x40..=0x4F => usize::from(bank & 0x0F) * 0x10000 + usize::from(offset), + _ => return None, + }; + Some(linear % ram_len) +} + +pub(crate) fn superfx_ram_index(address: u32, ram_len: usize) -> Option { + if ram_len == 0 { + return None; + } + + let address = address & ADDRESS_MASK; + let bank = ((address >> 16) & 0xFF) as u8; + let offset = (address & 0xFFFF) as u16; + + let linear = match bank { + 0x00..=0x3F | 0x80..=0xBF if (0x6000..=0x7FFF).contains(&offset) => { + usize::from(offset - 0x6000) + } + 0x70..=0x71 | 0xF0..=0xF1 => usize::from(bank & 0x01) * 0x10000 + usize::from(offset), + _ => return None, + }; + Some(linear % ram_len) +} + +#[cfg(test)] +mod tests { + use super::{ + hirom_ram_index, hirom_rom_index, lorom_ram_index, lorom_rom_index, sa1_ram_index, + sa1_rom_index, superfx_ram_index, + }; + + #[test] + fn lorom_banks_and_mirrors_map_into_linear_rom_storage() { + assert_eq!(lorom_rom_index(0x008000, 0x10000), Some(0x0000)); + assert_eq!(lorom_rom_index(0x00FFFF, 0x10000), Some(0x7FFF)); + assert_eq!(lorom_rom_index(0x018000, 0x10000), Some(0x8000)); + assert_eq!(lorom_rom_index(0x400000, 0x10000), Some(0x0000)); + assert_eq!(lorom_rom_index(0x408000, 0x10000), Some(0x0000)); + assert_eq!(lorom_rom_index(0x708000, 0x400000), Some(0x380000)); + assert_eq!(lorom_rom_index(0x808000, 0x10000), Some(0x0000)); + assert_eq!(lorom_rom_index(0xC18000, 0x10000), Some(0x8000)); + assert_eq!(lorom_rom_index(0x007FFF, 0x10000), None); + assert_eq!(lorom_rom_index(0x7E8000, 0x400000), None); + } + + #[test] + fn hirom_banks_and_mirrors_map_into_linear_rom_storage() { + assert_eq!(hirom_rom_index(0xC00000, 0x20000), Some(0x00000)); + assert_eq!(hirom_rom_index(0xC0FFFF, 0x20000), Some(0x0FFFF)); + assert_eq!(hirom_rom_index(0xC10000, 0x20000), Some(0x10000)); + assert_eq!(hirom_rom_index(0x400000, 0x20000), Some(0x00000)); + assert_eq!(hirom_rom_index(0x408000, 0x20000), Some(0x08000)); + assert_eq!(hirom_rom_index(0x008000, 0x20000), Some(0x08000)); + assert_eq!(hirom_rom_index(0x00FFFF, 0x20000), Some(0x0FFFF)); + assert_eq!(hirom_rom_index(0x808000, 0x20000), Some(0x08000)); + assert_eq!(hirom_rom_index(0x007FFF, 0x20000), None); + assert_eq!(hirom_rom_index(0x7E8000, 0x20000), None); + } + + #[test] + fn lorom_sram_banks_map_to_battery_ram_windows() { + assert_eq!(lorom_ram_index(0x700000, 0x2000), Some(0x0000)); + assert_eq!(lorom_ram_index(0x701FFF, 0x2000), Some(0x1FFF)); + assert_eq!(lorom_ram_index(0x702000, 0x2000), Some(0x0000)); + assert_eq!(lorom_ram_index(0x710000, 0x10000), Some(0x8000)); + assert_eq!(lorom_ram_index(0xF00000, 0x2000), Some(0x0000)); + assert_eq!(lorom_ram_index(0x7E0000, 0x2000), None); + assert_eq!(lorom_ram_index(0x708000, 0x2000), None); + } + + #[test] + fn hirom_sram_banks_map_to_battery_ram_windows() { + assert_eq!(hirom_ram_index(0x206000, 0x2000), Some(0x0000)); + assert_eq!(hirom_ram_index(0x207FFF, 0x2000), Some(0x1FFF)); + assert_eq!(hirom_ram_index(0x216000, 0x10000), Some(0x2000)); + assert_eq!(hirom_ram_index(0xA06000, 0x2000), Some(0x0000)); + assert_eq!(hirom_ram_index(0x205FFF, 0x2000), None); + assert_eq!(hirom_ram_index(0x208000, 0x2000), None); + assert_eq!(hirom_ram_index(0x406000, 0x2000), None); + } + + #[test] + fn sa1_default_super_mmc_rom_banks_map_full_64k_pages() { + assert_eq!(sa1_rom_index(0x008000, 0x20000), Some(0x00000)); + assert_eq!(sa1_rom_index(0x00FFFF, 0x20000), Some(0x07FFF)); + assert_eq!(sa1_rom_index(0xC00000, 0x20000), Some(0x00000)); + assert_eq!(sa1_rom_index(0xC08000, 0x20000), Some(0x08000)); + assert_eq!(sa1_rom_index(0xC10000, 0x20000), Some(0x10000)); + } + + #[test] + fn sa1_bwram_banks_map_to_linear_ram_storage() { + assert_eq!(sa1_ram_index(0x006000, 0x2000), Some(0x0000)); + assert_eq!(sa1_ram_index(0x007FFF, 0x2000), Some(0x1FFF)); + assert_eq!(sa1_ram_index(0x806000, 0x2000), Some(0x0000)); + assert_eq!(sa1_ram_index(0x400000, 0x20000), Some(0x00000)); + assert_eq!(sa1_ram_index(0x40FFFF, 0x20000), Some(0x0FFFF)); + assert_eq!(sa1_ram_index(0x410000, 0x20000), Some(0x10000)); + assert_eq!(sa1_ram_index(0x4F1234, 0x20000), Some(0x11234)); + assert_eq!(sa1_ram_index(0x005FFF, 0x20000), None); + assert_eq!(sa1_ram_index(0x008000, 0x20000), None); + assert_eq!(sa1_ram_index(0xC00000, 0x20000), None); + assert_eq!(sa1_ram_index(0x700000, 0x20000), None); + } + + #[test] + fn superfx_game_ram_maps_direct_and_system_windows() { + assert_eq!(superfx_ram_index(0x700000, 0x2000), Some(0x0000)); + assert_eq!(superfx_ram_index(0x701FFF, 0x2000), Some(0x1FFF)); + assert_eq!(superfx_ram_index(0x702000, 0x2000), Some(0x0000)); + assert_eq!(superfx_ram_index(0x710000, 0x2000), Some(0x0000)); + assert_eq!(superfx_ram_index(0xF00000, 0x2000), Some(0x0000)); + assert_eq!(superfx_ram_index(0x006000, 0x2000), Some(0x0000)); + assert_eq!(superfx_ram_index(0x007FFF, 0x2000), Some(0x1FFF)); + assert_eq!(superfx_ram_index(0x016000, 0x20000), Some(0x0000)); + assert_eq!(superfx_ram_index(0x3F7FFF, 0x20000), Some(0x1FFF)); + assert_eq!(superfx_ram_index(0x806000, 0x20000), Some(0x0000)); + assert_eq!(superfx_ram_index(0xBF7FFF, 0x20000), Some(0x1FFF)); + assert_eq!(superfx_ram_index(0x710000, 0x20000), Some(0x10000)); + assert_eq!(superfx_ram_index(0x005FFF, 0x2000), None); + } +} diff --git a/snes/core/src/memory.rs b/snes/core/src/memory.rs new file mode 100644 index 00000000..1c45f865 --- /dev/null +++ b/snes/core/src/memory.rs @@ -0,0 +1,140 @@ +const WRAM_LEN: usize = 128 * 1024; +const WMADD_MASK: u32 = 0x01_FFFF; + +#[derive(Debug, Clone)] +pub(crate) struct Memory { + wram: [u8; WRAM_LEN], + wmadd: u32, +} + +impl Default for Memory { + fn default() -> Self { + Self { + wram: [0; WRAM_LEN], + wmadd: 0, + } + } +} + +impl Memory { + pub(crate) fn new() -> Self { + Self::default() + } + + pub(crate) fn read_cpu_bus(&mut self, bank: u8, offset: u16) -> Option { + match (bank, offset) { + (0x7E..=0x7F, _) => Some(self.wram[wram_index(bank, offset)]), + (0x00..=0x3F | 0x80..=0xBF, 0x0000..=0x1FFF) => Some(self.wram[usize::from(offset)]), + _ => None, + } + } + + pub(crate) fn peek_cpu_bus(&self, bank: u8, offset: u16) -> Option { + match (bank, offset) { + (0x7E..=0x7F, _) => Some(self.wram[wram_index(bank, offset)]), + (0x00..=0x3F | 0x80..=0xBF, 0x0000..=0x1FFF) => Some(self.wram[usize::from(offset)]), + _ => None, + } + } + + pub(crate) fn write_cpu_bus(&mut self, bank: u8, offset: u16, value: u8) -> bool { + match (bank, offset) { + (0x7E..=0x7F, _) => { + self.wram[wram_index(bank, offset)] = value; + true + } + (0x00..=0x3F | 0x80..=0xBF, 0x0000..=0x1FFF) => { + self.wram[usize::from(offset)] = value; + true + } + _ => false, + } + } + + pub(crate) fn read_mmio(&mut self, offset: u16) -> Option { + match offset { + 0x2180 => { + let value = self.wram[self.wmadd as usize]; + self.wmadd = wrap_wmadd(self.wmadd + 1); + Some(value) + } + _ => None, + } + } + + pub(crate) fn peek_mmio(&self, offset: u16) -> Option { + match offset { + 0x2180 => Some(self.wram[self.wmadd as usize]), + 0x2181 => Some(self.wmadd as u8), + 0x2182 => Some((self.wmadd >> 8) as u8), + 0x2183 => Some(((self.wmadd >> 16) as u8) & 0x01), + _ => None, + } + } + + pub(crate) fn write_mmio(&mut self, offset: u16, value: u8) -> bool { + match offset { + 0x2180 => { + self.wram[self.wmadd as usize] = value; + self.wmadd = wrap_wmadd(self.wmadd + 1); + true + } + 0x2181 => { + self.wmadd = (self.wmadd & !0x0000FF) | u32::from(value); + true + } + 0x2182 => { + self.wmadd = (self.wmadd & !0x00FF00) | (u32::from(value) << 8); + true + } + 0x2183 => { + self.wmadd = (self.wmadd & !0x010000) | (u32::from(value & 0x01) << 16); + true + } + _ => false, + } + } + + pub(crate) fn peek_wram(&self, address: usize) -> u8 { + self.wram[address % WRAM_LEN] + } + + #[cfg(test)] + pub(crate) fn wmadd(&self) -> u32 { + self.wmadd + } +} + +fn wrap_wmadd(value: u32) -> u32 { + value & WMADD_MASK +} + +fn wram_index(bank: u8, offset: u16) -> usize { + (usize::from(bank - 0x7E) << 16) | usize::from(offset) +} + +#[cfg(test)] +mod tests { + use super::Memory; + + #[test] + fn wram_ports_read_write_and_auto_increment() { + let mut memory = Memory::new(); + + assert!(memory.write_mmio(0x2181, 0x00)); + assert!(memory.write_mmio(0x2182, 0x00)); + assert!(memory.write_mmio(0x2183, 0x00)); + assert!(memory.write_mmio(0x2180, 0x5A)); + assert!(memory.write_mmio(0x2180, 0xC3)); + + assert_eq!(memory.peek_wram(0), 0x5A); + assert_eq!(memory.peek_wram(1), 0xC3); + assert_eq!(memory.wmadd(), 2); + + assert!(memory.write_mmio(0x2181, 0x00)); + assert!(memory.write_mmio(0x2182, 0x00)); + assert!(memory.write_mmio(0x2183, 0x00)); + assert_eq!(memory.read_mmio(0x2180), Some(0x5A)); + assert_eq!(memory.read_mmio(0x2180), Some(0xC3)); + } +} diff --git a/snes/core/src/ppu1.rs b/snes/core/src/ppu1.rs new file mode 100644 index 00000000..4e53c016 --- /dev/null +++ b/snes/core/src/ppu1.rs @@ -0,0 +1,582 @@ +const VRAM_LEN: usize = 64 * 1024; +const OAM_LEN: usize = 544; +const BG_LAYER_COUNT: usize = 4; + +#[derive(Debug, Clone, Copy, Default, PartialEq, Eq)] +pub struct Mode7Registers { + pub m7sel: u8, + pub a: i16, + pub b: i16, + pub c: i16, + pub d: i16, + pub x: i16, + pub y: i16, +} + +#[derive(Debug, Clone)] +pub(crate) struct Ppu1 { + registers: [u8; 0x40], + vram: [u8; VRAM_LEN], + oam: [u8; OAM_LEN], + vmain: u8, + vmadd: u16, + oam_byte_addr: u16, + bgofs_latch: u8, + bg_hofs_latch: [u8; BG_LAYER_COUNT], + bg_hofs: [u16; BG_LAYER_COUNT], + bg_vofs: [u16; BG_LAYER_COUNT], + mode7: Mode7Registers, + mode7_latch: u8, + mode7_multiply_operand: i8, +} + +impl Default for Ppu1 { + fn default() -> Self { + Self { + registers: [0; 0x40], + vram: [0; VRAM_LEN], + oam: [0; OAM_LEN], + vmain: 0, + vmadd: 0, + oam_byte_addr: 0, + bgofs_latch: 0, + bg_hofs_latch: [0; BG_LAYER_COUNT], + bg_hofs: [0; BG_LAYER_COUNT], + bg_vofs: [0; BG_LAYER_COUNT], + mode7: Mode7Registers::default(), + mode7_latch: 0, + mode7_multiply_operand: 0, + } + } +} + +impl Ppu1 { + pub(crate) fn new() -> Self { + Self::default() + } + + pub(crate) fn write(&mut self, offset: u16, value: u8) -> bool { + self.write_with_vram_access(offset, value, true) + } + + pub(crate) fn write_with_vram_access( + &mut self, + offset: u16, + value: u8, + allow_vram_port_write: bool, + ) -> bool { + match offset { + 0x2102 => { + self.store_register(offset, value); + self.oam_byte_addr = (self.oam_byte_addr & 0x0200) | (u16::from(value) << 1); + true + } + 0x2103 => { + self.store_register(offset, value); + self.oam_byte_addr = (self.oam_byte_addr & 0x01FE) | (u16::from(value & 0x01) << 9); + true + } + 0x2104 => { + self.store_register(offset, value); + self.oam[usize::from(self.oam_byte_addr % OAM_LEN as u16)] = value; + self.oam_byte_addr = (self.oam_byte_addr + 1) % OAM_LEN as u16; + true + } + 0x210D => { + self.store_register(offset, value); + self.write_bg_hofs(0, value); + true + } + 0x210E => { + self.store_register(offset, value); + self.write_bg_vofs(0, value); + true + } + 0x210F | 0x2111 | 0x2113 => { + self.store_register(offset, value); + self.write_bg_hofs(bg_hofs_index(offset), value); + true + } + 0x2110 | 0x2112 | 0x2114 => { + self.store_register(offset, value); + self.write_bg_vofs(bg_vofs_index(offset), value); + true + } + 0x2115 => { + self.store_register(offset, value); + self.vmain = value; + true + } + 0x2116 => { + self.store_register(offset, value); + self.vmadd = (self.vmadd & 0xFF00) | u16::from(value); + true + } + 0x2117 => { + self.store_register(offset, value); + self.vmadd = (self.vmadd & 0x00FF) | (u16::from(value) << 8); + true + } + 0x2118 => { + self.store_register(offset, value); + self.write_vram_byte(false, value, allow_vram_port_write); + true + } + 0x2119 => { + self.store_register(offset, value); + self.write_vram_byte(true, value, allow_vram_port_write); + true + } + 0x211A => { + self.store_register(offset, value); + self.mode7.m7sel = value; + true + } + 0x211B..=0x2120 => { + self.store_register(offset, value); + self.write_mode7_word(offset, value); + true + } + 0x2101 | 0x2105..=0x210C => { + self.store_register(offset, value); + true + } + _ => false, + } + } + + pub(crate) fn read(&mut self, offset: u16) -> Option { + match offset { + 0x2134..=0x2136 => Some(self.mode7_multiply_result_byte(offset)), + 0x2138 => { + let value = self.oam[usize::from(self.oam_byte_addr % OAM_LEN as u16)]; + self.oam_byte_addr = (self.oam_byte_addr + 1) % OAM_LEN as u16; + Some(value) + } + 0x2139 => Some(self.read_vram_byte(false, true)), + 0x213A => Some(self.read_vram_byte(true, true)), + 0x213E => Some(0x01), + _ => None, + } + } + + pub(crate) fn peek(&self, offset: u16) -> Option { + match offset { + 0x2101..=0x2120 => Some(self.registers[register_index(offset)]), + 0x2134..=0x2136 => Some(self.mode7_multiply_result_byte(offset)), + 0x2138 => Some(self.oam[usize::from(self.oam_byte_addr % OAM_LEN as u16)]), + 0x2139 => Some(self.read_vram_peek(false)), + 0x213A => Some(self.read_vram_peek(true)), + 0x213E => Some(0x01), + _ => None, + } + } + + pub(crate) fn peek_vram(&self, address: usize) -> u8 { + self.vram[address % VRAM_LEN] + } + + pub(crate) fn peek_oam(&self, address: usize) -> u8 { + self.oam[address % OAM_LEN] + } + + pub(crate) fn bg1_hofs(&self) -> u16 { + self.bg_hofs(0) + } + + pub(crate) fn bg1_vofs(&self) -> u16 { + self.bg_vofs(0) + } + + pub(crate) fn bg2_hofs(&self) -> u16 { + self.bg_hofs(1) + } + + pub(crate) fn bg2_vofs(&self) -> u16 { + self.bg_vofs(1) + } + + pub(crate) fn bg3_hofs(&self) -> u16 { + self.bg_hofs(2) + } + + pub(crate) fn bg3_vofs(&self) -> u16 { + self.bg_vofs(2) + } + + pub(crate) fn bg4_hofs(&self) -> u16 { + self.bg_hofs(3) + } + + pub(crate) fn bg4_vofs(&self) -> u16 { + self.bg_vofs(3) + } + + pub(crate) fn mode7_registers(&self) -> Mode7Registers { + self.mode7 + } + + #[cfg(test)] + pub(crate) fn vmadd(&self) -> u16 { + self.vmadd + } + + fn store_register(&mut self, offset: u16, value: u8) { + self.registers[register_index(offset)] = value; + } + + fn write_vram_byte(&mut self, high: bool, value: u8, allow_store: bool) { + if allow_store { + let byte_index = self.vram_byte_index(high); + self.vram[byte_index] = value; + } + if self.should_increment_after(high) { + self.vmadd = self.vmadd.wrapping_add(vram_increment_words(self.vmain)); + } + } + + fn read_vram_byte(&mut self, high: bool, advance: bool) -> u8 { + let value = self.vram[self.vram_byte_index(high)]; + if advance && self.should_increment_after(high) { + self.vmadd = self.vmadd.wrapping_add(vram_increment_words(self.vmain)); + } + value + } + + fn read_vram_peek(&self, high: bool) -> u8 { + self.vram[self.vram_byte_index(high)] + } + + fn vram_byte_index(&self, high: bool) -> usize { + let remapped = remap_vmadd(self.vmadd, self.vmain); + (usize::from(remapped) * 2 + usize::from(high)) % VRAM_LEN + } + + fn should_increment_after(&self, high: bool) -> bool { + let increment_after_high = self.vmain & 0x80 != 0; + if increment_after_high { high } else { !high } + } + + fn bg_hofs(&self, index: usize) -> u16 { + self.bg_hofs[index] + } + + fn bg_vofs(&self, index: usize) -> u16 { + self.bg_vofs[index] + } + + fn write_bg_hofs(&mut self, index: usize, value: u8) { + self.bg_hofs[index] = (u16::from(value) << 8) + | u16::from(self.bgofs_latch & 0xF8) + | u16::from(self.bg_hofs_latch[index] & 0x07); + self.bgofs_latch = value; + self.bg_hofs_latch[index] = value; + } + + fn write_bg_vofs(&mut self, index: usize, value: u8) { + self.bg_vofs[index] = (u16::from(value) << 8) | u16::from(self.bgofs_latch); + self.bgofs_latch = value; + } + + fn write_mode7_word(&mut self, offset: u16, value: u8) { + let word = i16::from_le_bytes([self.mode7_latch, value]); + match offset { + 0x211B => self.mode7.a = word, + 0x211C => { + self.mode7.b = word; + self.mode7_multiply_operand = value as i8; + } + 0x211D => self.mode7.c = word, + 0x211E => self.mode7.d = word, + 0x211F => self.mode7.x = mode7_center_coordinate(word), + 0x2120 => self.mode7.y = mode7_center_coordinate(word), + _ => unreachable!(), + } + self.mode7_latch = value; + } + + fn mode7_multiply_result_byte(&self, offset: u16) -> u8 { + let product = i32::from(self.mode7.a) * i32::from(self.mode7_multiply_operand); + ((product as u32) >> ((offset - 0x2134) * 8)) as u8 + } +} + +fn register_index(offset: u16) -> usize { + usize::from(offset - 0x2100) +} + +fn bg_hofs_index(offset: u16) -> usize { + usize::from((offset - 0x210D) / 2) +} + +fn bg_vofs_index(offset: u16) -> usize { + usize::from((offset - 0x210E) / 2) +} + +fn remap_vmadd(address: u16, vmain: u8) -> u16 { + match (vmain >> 2) & 0x03 { + 0 => address, + 1 => { + let rem = address & 0x00FF; + (address & 0xFF00) | ((rem << 3) & 0x00FF) | (rem >> 5) + } + 2 => { + let rem = address & 0x01FF; + (address & 0xFE00) | ((rem << 3) & 0x01FF) | (rem >> 6) + } + 3 => { + let rem = address & 0x03FF; + (address & 0xFC00) | ((rem << 3) & 0x03FF) | (rem >> 7) + } + _ => unreachable!(), + } +} + +fn vram_increment_words(vmain: u8) -> u16 { + match vmain & 0x03 { + 0 => 1, + 1 => 32, + _ => 128, + } +} + +fn mode7_center_coordinate(value: i16) -> i16 { + let value = value & 0x1FFF; + if value & 0x1000 != 0 { + value | !0x1FFF + } else { + value + } +} + +#[cfg(test)] +mod tests { + use super::Ppu1; + + #[test] + fn vram_data_writes_follow_vmain_increment_mode() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2115, 0x80)); + assert!(ppu1.write(0x2116, 0x00)); + assert!(ppu1.write(0x2117, 0x00)); + assert!(ppu1.write(0x2118, 0x34)); + assert!(ppu1.write(0x2119, 0x12)); + + assert_eq!(ppu1.peek_vram(0), 0x34); + assert_eq!(ppu1.peek_vram(1), 0x12); + assert_eq!(ppu1.vmadd(), 1); + } + + #[test] + fn vram_remap_mode1_rotates_lower_8_bits() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2115, 0x84)); + assert!(ppu1.write(0x2116, 0xE5)); + assert!(ppu1.write(0x2117, 0x12)); + assert!(ppu1.write(0x2118, 0x34)); + assert!(ppu1.write(0x2119, 0x12)); + + assert_eq!(ppu1.peek_vram(0x122F * 2), 0x34); + assert_eq!(ppu1.peek_vram(0x122F * 2 + 1), 0x12); + assert_eq!(ppu1.vmadd(), 0x12E6); + } + + #[test] + fn vram_remap_mode2_rotates_lower_9_bits() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2115, 0x88)); + assert!(ppu1.write(0x2116, 0xE5)); + assert!(ppu1.write(0x2117, 0x23)); + assert!(ppu1.write(0x2118, 0x78)); + assert!(ppu1.write(0x2119, 0x56)); + + assert_eq!(ppu1.peek_vram(0x232F * 2), 0x78); + assert_eq!(ppu1.peek_vram(0x232F * 2 + 1), 0x56); + assert_eq!(ppu1.vmadd(), 0x23E6); + } + + #[test] + fn vram_remap_mode3_rotates_lower_10_bits() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2115, 0x8C)); + assert!(ppu1.write(0x2116, 0xE5)); + assert!(ppu1.write(0x2117, 0x43)); + assert!(ppu1.write(0x2118, 0xBC)); + assert!(ppu1.write(0x2119, 0x9A)); + + assert_eq!(ppu1.peek_vram(0x432F * 2), 0xBC); + assert_eq!(ppu1.peek_vram(0x432F * 2 + 1), 0x9A); + assert_eq!(ppu1.vmadd(), 0x43E6); + } + + #[test] + fn oam_writes_cover_low_and_high_tables() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2102, 0x00)); + assert!(ppu1.write(0x2103, 0x00)); + for value in [0x40, 0x50, 0x00, 0x30, 0x60, 0x50, 0x04, 0x30] { + assert!(ppu1.write(0x2104, value)); + } + + assert_eq!(ppu1.peek_oam(0), 0x40); + assert_eq!(ppu1.peek_oam(1), 0x50); + assert_eq!(ppu1.peek_oam(2), 0x00); + assert_eq!(ppu1.peek_oam(3), 0x30); + assert_eq!(ppu1.peek_oam(4), 0x60); + assert_eq!(ppu1.peek_oam(5), 0x50); + assert_eq!(ppu1.peek_oam(6), 0x04); + assert_eq!(ppu1.peek_oam(7), 0x30); + + assert!(ppu1.write(0x2102, 0x00)); + assert!(ppu1.write(0x2103, 0x01)); + for _ in 0..4 { + assert!(ppu1.write(0x2104, 0xAA)); + } + + assert_eq!(ppu1.peek_oam(512), 0xAA); + assert_eq!(ppu1.peek_oam(513), 0xAA); + assert_eq!(ppu1.peek_oam(514), 0xAA); + assert_eq!(ppu1.peek_oam(515), 0xAA); + } + + #[test] + fn oam_reads_follow_the_current_oam_address() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x2102, 0x00)); + assert!(ppu1.write(0x2103, 0x00)); + for value in [0x12, 0x34, 0x56, 0x78] { + assert!(ppu1.write(0x2104, value)); + } + + assert!(ppu1.write(0x2102, 0x00)); + assert!(ppu1.write(0x2103, 0x00)); + assert_eq!(ppu1.read(0x2138), Some(0x12)); + assert_eq!(ppu1.read(0x2138), Some(0x34)); + assert_eq!(ppu1.read(0x2138), Some(0x56)); + assert_eq!(ppu1.read(0x2138), Some(0x78)); + } + + #[test] + fn bg_scroll_registers_track_common_two_write_sequences() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x210D, 0x34)); + assert!(ppu1.write(0x210D, 0x02)); + assert!(ppu1.write(0x210E, 0x78)); + assert!(ppu1.write(0x210E, 0x01)); + assert!(ppu1.write(0x210F, 0x56)); + assert!(ppu1.write(0x210F, 0x03)); + assert!(ppu1.write(0x2110, 0x9A)); + assert!(ppu1.write(0x2110, 0x00)); + assert!(ppu1.write(0x2111, 0xBC)); + assert!(ppu1.write(0x2111, 0x02)); + assert!(ppu1.write(0x2112, 0xDE)); + assert!(ppu1.write(0x2112, 0x01)); + assert!(ppu1.write(0x2113, 0x24)); + assert!(ppu1.write(0x2113, 0x03)); + assert!(ppu1.write(0x2114, 0x68)); + assert!(ppu1.write(0x2114, 0x00)); + + assert_eq!(ppu1.bg1_hofs(), 0x0234); + assert_eq!(ppu1.bg1_vofs(), 0x0178); + assert_eq!(ppu1.bg2_hofs(), 0x0356); + assert_eq!(ppu1.bg2_vofs(), 0x009A); + assert_eq!(ppu1.bg3_hofs(), 0x02BC); + assert_eq!(ppu1.bg3_vofs(), 0x01DE); + assert_eq!(ppu1.bg4_hofs(), 0x0324); + assert_eq!(ppu1.bg4_vofs(), 0x0068); + } + + #[test] + fn mode7_registers_preserve_two_write_words_and_raw_peeks() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x211A, 0x80)); + assert!(ppu1.write(0x211B, 0x34)); + assert!(ppu1.write(0x211B, 0x12)); + assert!(ppu1.write(0x211C, 0x00)); + assert!(ppu1.write(0x211C, 0xFF)); + assert!(ppu1.write(0x211D, 0x78)); + assert!(ppu1.write(0x211D, 0x56)); + assert!(ppu1.write(0x211E, 0x00)); + assert!(ppu1.write(0x211E, 0x01)); + assert!(ppu1.write(0x211F, 0xFE)); + assert!(ppu1.write(0x211F, 0xFF)); + assert!(ppu1.write(0x2120, 0x02)); + assert!(ppu1.write(0x2120, 0x00)); + + let mode7 = ppu1.mode7_registers(); + assert_eq!(mode7.m7sel, 0x80); + assert_eq!(mode7.a, 0x1234); + assert_eq!(mode7.b, -256); + assert_eq!(mode7.c, 0x5678); + assert_eq!(mode7.d, 0x0100); + assert_eq!(mode7.x, -2); + assert_eq!(mode7.y, 2); + assert_eq!(ppu1.peek(0x211A), Some(0x80)); + assert_eq!(ppu1.peek(0x211B), Some(0x12)); + assert_eq!(ppu1.peek(0x211F), Some(0xFF)); + } + + #[test] + fn mode7_registers_share_the_previous_byte_latch() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x211B, 0x34)); + assert!(ppu1.write(0x211C, 0x12)); + + let mode7 = ppu1.mode7_registers(); + assert_eq!(mode7.a, 0x3400); + assert_eq!(mode7.b, 0x1234); + } + + #[test] + fn mode7_center_coordinates_are_13_bit_signed() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x211F, 0xFF)); + assert!(ppu1.write(0x211F, 0x0F)); + assert!(ppu1.write(0x2120, 0x34)); + assert!(ppu1.write(0x2120, 0x12)); + + let mode7 = ppu1.mode7_registers(); + assert_eq!(mode7.x, 0x0FFF); + assert_eq!(mode7.y, -0x0DCC); + assert_eq!(ppu1.peek(0x211F), Some(0x0F)); + assert_eq!(ppu1.peek(0x2120), Some(0x12)); + + assert!(ppu1.write(0x211F, 0xBC)); + assert!(ppu1.write(0x211F, 0x2A)); + + assert_eq!(ppu1.mode7_registers().x, 0x0ABC); + assert_eq!(ppu1.peek(0x211F), Some(0x2A)); + } + + #[test] + fn mode7_multiply_reads_return_signed_24_bit_product() { + let mut ppu1 = Ppu1::new(); + + assert!(ppu1.write(0x211B, 0x34)); + assert!(ppu1.write(0x211B, 0x12)); + assert!(ppu1.write(0x211C, 0x00)); + assert!(ppu1.write(0x211C, 0xFF)); + + assert_eq!(ppu1.read(0x2134), Some(0xCC)); + assert_eq!(ppu1.read(0x2135), Some(0xED)); + assert_eq!(ppu1.read(0x2136), Some(0xFF)); + + assert!(ppu1.write(0x211B, 0xFE)); + assert!(ppu1.write(0x211B, 0xFF)); + assert!(ppu1.write(0x211C, 0x7F)); + + assert_eq!(ppu1.peek(0x2134), Some(0x02)); + assert_eq!(ppu1.peek(0x2135), Some(0xFF)); + assert_eq!(ppu1.peek(0x2136), Some(0xFF)); + } +} diff --git a/snes/core/src/ppu2.rs b/snes/core/src/ppu2.rs new file mode 100644 index 00000000..ed30aa70 --- /dev/null +++ b/snes/core/src/ppu2.rs @@ -0,0 +1,184 @@ +const CGRAM_LEN: usize = 512; + +#[derive(Debug, Clone)] +pub(crate) struct Ppu2 { + registers: [u8; 0x40], + cgram: [u8; CGRAM_LEN], + inidisp: u8, + cgadd: u8, + cgram_latch: u8, + cgram_byte: bool, + fixed_color: u16, +} + +impl Default for Ppu2 { + fn default() -> Self { + Self { + registers: [0; 0x40], + cgram: [0; CGRAM_LEN], + inidisp: 0, + cgadd: 0, + cgram_latch: 0, + cgram_byte: false, + fixed_color: 0, + } + } +} + +impl Ppu2 { + pub(crate) fn new() -> Self { + Self::default() + } + + pub(crate) fn write(&mut self, offset: u16, value: u8) -> bool { + match offset { + 0x2100 => { + self.store_register(offset, value); + self.inidisp = value; + true + } + 0x2121 => { + self.store_register(offset, value); + self.cgadd = value; + self.cgram_byte = false; + true + } + 0x2122 => { + self.store_register(offset, value); + if self.cgram_byte { + let index = (usize::from(self.cgadd) * 2) % CGRAM_LEN; + self.cgram[index] = self.cgram_latch; + self.cgram[(index + 1) % CGRAM_LEN] = value; + self.cgadd = self.cgadd.wrapping_add(1); + } else { + self.cgram_latch = value; + } + self.cgram_byte = !self.cgram_byte; + true + } + 0x2123..=0x2131 | 0x2133 => { + self.store_register(offset, value); + true + } + 0x2132 => { + self.store_register(offset, value); + self.write_fixed_color(value); + true + } + _ => false, + } + } + + pub(crate) fn read(&mut self, offset: u16) -> Option { + match offset { + 0x213B => { + let index = + (usize::from(self.cgadd) * 2 + usize::from(self.cgram_byte)) % CGRAM_LEN; + let value = self.cgram[index]; + if self.cgram_byte { + self.cgadd = self.cgadd.wrapping_add(1); + } + self.cgram_byte = !self.cgram_byte; + Some(value) + } + 0x213C | 0x213D => Some(0), + 0x213F => Some(0x01), + _ => None, + } + } + + pub(crate) fn peek(&self, offset: u16) -> Option { + match offset { + 0x2100 | 0x2121..=0x2133 => Some(self.registers[register_index(offset)]), + 0x213B => { + let index = + (usize::from(self.cgadd) * 2 + usize::from(self.cgram_byte)) % CGRAM_LEN; + Some(self.cgram[index]) + } + 0x213C | 0x213D => Some(0), + 0x213F => Some(0x01), + _ => None, + } + } + + #[cfg(test)] + pub(crate) fn inidisp(&self) -> u8 { + self.inidisp + } + + pub(crate) fn peek_cgram(&self, index: usize) -> u8 { + self.cgram[index % CGRAM_LEN] + } + + pub(crate) fn fixed_color(&self) -> u16 { + self.fixed_color + } + + pub(crate) fn force_blank(&self) -> bool { + self.inidisp & 0x80 != 0 + } + + pub(crate) fn interlace_enabled(&self) -> bool { + self.registers[register_index(0x2133)] & 0x01 != 0 + } + + pub(crate) fn obj_interlace_enabled(&self) -> bool { + self.registers[register_index(0x2133)] & 0x02 != 0 + } + + pub(crate) fn pseudo_hires_enabled(&self) -> bool { + self.registers[register_index(0x2133)] & 0x08 != 0 + } + + fn store_register(&mut self, offset: u16, value: u8) { + self.registers[register_index(offset)] = value; + } + + fn write_fixed_color(&mut self, value: u8) { + let intensity = u16::from(value & 0x1F); + if value & 0x20 != 0 { + self.fixed_color = (self.fixed_color & !0x001F) | intensity; + } + if value & 0x40 != 0 { + self.fixed_color = (self.fixed_color & !0x03E0) | (intensity << 5); + } + if value & 0x80 != 0 { + self.fixed_color = (self.fixed_color & !0x7C00) | (intensity << 10); + } + } +} + +fn register_index(offset: u16) -> usize { + usize::from(offset - 0x2100) +} + +#[cfg(test)] +mod tests { + use super::Ppu2; + + #[test] + fn cgram_data_writes_commit_after_second_byte() { + let mut ppu2 = Ppu2::new(); + + assert!(ppu2.write(0x2121, 0x01)); + assert!(ppu2.write(0x2122, 0x7F)); + assert_eq!(ppu2.peek_cgram(2), 0x00); + assert!(ppu2.write(0x2122, 0x00)); + + assert_eq!(ppu2.inidisp(), 0x00); + assert_eq!(ppu2.peek_cgram(2), 0x7F); + assert_eq!(ppu2.peek_cgram(3), 0x00); + } + + #[test] + fn fixed_color_writes_update_selected_planes() { + let mut ppu2 = Ppu2::new(); + + assert!(ppu2.write(0x2132, 0x80 | 31)); + assert!(ppu2.write(0x2132, 0x40 | 7)); + assert!(ppu2.write(0x2132, 0x20 | 15)); + + assert_eq!(ppu2.fixed_color(), (31 << 10) | (7 << 5) | 15); + assert_eq!(ppu2.peek(0x2132), Some(0x20 | 15)); + } +} diff --git a/snes/core/src/scheduler.rs b/snes/core/src/scheduler.rs new file mode 100644 index 00000000..99229a62 --- /dev/null +++ b/snes/core/src/scheduler.rs @@ -0,0 +1,165 @@ +use crate::bus::{Bus, CpuBus, ScheduledCpuBus}; +use crate::cpu::{Cpu, CpuFault, CpuState}; +use nerust_sound_traits::MixerInput; + +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +#[allow(dead_code)] +pub(crate) enum SchedulerEventKind { + BusWrite, + InterruptChange, + BusArbitration, +} + +#[derive(Clone, Copy, Debug, Eq, PartialEq)] +pub(crate) struct CpuRun { + pub(crate) cycles: u32, + pub(crate) crossed_event_boundary: bool, +} + +pub(crate) trait Component { + fn next_event_cycles(&self) -> u32; + #[allow(dead_code)] + fn step(&mut self, cycles: u32); +} + +pub(crate) trait CpuLike { + fn execute_until(&mut self, bus: &mut dyn CpuBus, allowed_cycles: u32) -> CpuRun; +} + +#[derive(Clone, Debug, Default)] +pub(crate) struct Scheduler { + master_cycles: u64, +} + +impl Scheduler { + pub(crate) fn new() -> Self { + Self::default() + } + + pub(crate) fn master_cycles(&self) -> u64 { + self.master_cycles + } + + pub(crate) fn reset(&mut self) { + self.master_cycles = 0; + } + + pub(crate) fn advance(&mut self, cycles: u64) { + self.master_cycles = self.master_cycles.wrapping_add(cycles); + } + + pub(crate) fn run_for_cycles( + &mut self, + cpu: &mut Cpu, + bus: &mut Bus, + cycles: u64, + ) -> Result<(), CpuFault> { + if cycles == 0 { + return Ok(()); + } + + let mut remaining_cycles = cycles; + while remaining_cycles > 0 && cpu.current_state() != CpuState::Stopped { + let external_event_cycles = Component::next_event_cycles(bus); + let allowed_cycles = remaining_cycles + .min(u64::from(external_event_cycles)) + .min(u64::from(u32::MAX)) as u32; + + let start_cycles = cpu.cycles(); + let mut scheduled_bus = ScheduledCpuBus::new(bus); + let run = CpuLike::execute_until(cpu, &mut scheduled_bus, allowed_cycles.max(1)); + scheduled_bus.flush(); + + let consumed_cycles = cpu.cycles().wrapping_sub(start_cycles); + debug_assert_eq!(consumed_cycles as u32, run.cycles); + self.advance(consumed_cycles); + + if let Some(fault) = cpu.take_fault() { + return Err(fault); + } + if consumed_cycles == 0 { + break; + } + + remaining_cycles = remaining_cycles.saturating_sub(consumed_cycles); + + if run.crossed_event_boundary { + self.handle_event_boundary(SchedulerEventKind::InterruptChange); + } + } + + Ok(()) + } + + pub(crate) fn run_for_cycles_with_audio( + &mut self, + cpu: &mut Cpu, + bus: &mut Bus, + cycles: u64, + mixer: &mut M, + ) -> Result<(), CpuFault> { + if cycles == 0 { + return Ok(()); + } + + let mut remaining_cycles = cycles; + while remaining_cycles > 0 && cpu.current_state() != CpuState::Stopped { + let external_event_cycles = Component::next_event_cycles(bus); + let allowed_cycles = remaining_cycles + .min(u64::from(external_event_cycles)) + .min(u64::from(u32::MAX)) as u32; + + let start_cycles = cpu.cycles(); + let mut scheduled_bus = ScheduledCpuBus::new_with_audio(bus, mixer); + let run = CpuLike::execute_until(cpu, &mut scheduled_bus, allowed_cycles.max(1)); + scheduled_bus.flush(); + + let consumed_cycles = cpu.cycles().wrapping_sub(start_cycles); + debug_assert_eq!(consumed_cycles as u32, run.cycles); + self.advance(consumed_cycles); + + if let Some(fault) = cpu.take_fault() { + return Err(fault); + } + if consumed_cycles == 0 { + break; + } + + remaining_cycles = remaining_cycles.saturating_sub(consumed_cycles); + + if run.crossed_event_boundary { + self.handle_event_boundary(SchedulerEventKind::InterruptChange); + } + } + + Ok(()) + } + + fn handle_event_boundary(&mut self, kind: SchedulerEventKind) { + match kind { + SchedulerEventKind::BusWrite + | SchedulerEventKind::InterruptChange + | SchedulerEventKind::BusArbitration => {} + } + } +} + +impl Component for Bus { + fn next_event_cycles(&self) -> u32 { + Bus::next_event_cycles(self) + } + + fn step(&mut self, cycles: u32) { + self.step_cpu_cycles(cycles); + } +} + +impl CpuLike for Cpu { + fn execute_until(&mut self, bus: &mut dyn CpuBus, allowed_cycles: u32) -> CpuRun { + let (cycles, crossed_event_boundary) = Cpu::execute_until(self, bus, allowed_cycles); + CpuRun { + cycles, + crossed_event_boundary, + } + } +} diff --git a/snes/render/Cargo.toml b/snes/render/Cargo.toml new file mode 100644 index 00000000..40493715 --- /dev/null +++ b/snes/render/Cargo.toml @@ -0,0 +1,11 @@ +[package] +name = "nerust_snes_render" +version.workspace = true +authors.workspace = true +license.workspace = true +edition.workspace = true +rust-version.workspace = true + +[dependencies] +nerust_snes_core.workspace = true +thiserror.workspace = true diff --git a/snes/render/src/backdrop.rs b/snes/render/src/backdrop.rs new file mode 100644 index 00000000..ccf7001b --- /dev/null +++ b/snes/render/src/backdrop.rs @@ -0,0 +1,285 @@ +use nerust_snes_core::{Core, PresentedBackdropLine, PresentedColorWindowLine}; + +use super::color::{opaque_black_screen, put_pixel, snes_color_to_rgba}; + +const COLOR_WINDOW_SHIFT: u8 = 4; +const WINDOW1_ENABLE: u8 = 0x02; +const WINDOW1_OUTSIDE: u8 = 0x01; +const WINDOW2_ENABLE: u8 = 0x08; +const WINDOW2_OUTSIDE: u8 = 0x04; +const COLOR_WINDOW_LOGIC_SHIFT: u8 = 2; +const COLOR_WINDOW_SELECTOR_MASK: u8 = 0x03; +const CGWSEL_CLIP_SHIFT: u8 = 6; +const CGWSEL_PREVENT_SHIFT: u8 = 4; +const CGADSUB_SUBTRACT: u8 = 0x80; +const CGADSUB_HALF: u8 = 0x40; +const CGADSUB_ENABLE_BACKDROP: u8 = 0x20; + +pub(super) fn render_presented_backdrop( + core: &Core, + width: usize, + height: usize, + use_presented_inidisp: bool, + cgram_hdma_active: bool, +) -> Vec { + let fallback_backdrop = current_backdrop_line(core); + let fallback_window = current_color_window_line(core); + let color_math = BackdropColorMath::from_core(core); + let mut rgba = opaque_black_screen(width, height); + + for screen_y in 0..height { + let presented_y = screen_y / (height / 224).max(1); + let mut backdrop = core + .presented_backdrop_line(presented_y) + .unwrap_or(fallback_backdrop); + if !use_presented_inidisp { + // When HDMA doesn't target INIDISP, scanline 0 may have stale + // captured values from before the test modifies registers. + if presented_y == 0 { + let current_inidisp = core.peek(0x002100); + if backdrop.inidisp & 0x80 != 0 && current_inidisp & 0x80 == 0 { + backdrop.inidisp = current_inidisp; + } + } + } + // Scanline 0's captured CGRAM colour comes from the previous frame, + // not the current frame's first HDMA write. When CGRAM HDMA is + // active and scanline 0's colour is 0 (uninitialized), use + // scanline 1's value which reflects the first HDMA entry. + if presented_y == 0 && cgram_hdma_active && backdrop.color0 == 0 { + if let Some(next) = core.presented_backdrop_line(1) { + backdrop.color0 = next.color0; + } + } + let window = core + .presented_color_window_line(presented_y) + .unwrap_or(fallback_window); + for screen_x in 0..width { + let line_color = presented_backdrop_pixel_rgba(backdrop, window, screen_x, color_math); + put_pixel(&mut rgba, width, screen_x, screen_y, line_color); + } + } + + rgba +} + +pub(super) fn current_backdrop_line(core: &Core) -> PresentedBackdropLine { + PresentedBackdropLine { + inidisp: core.peek(0x002100), + color0: u16::from_le_bytes([core.peek_cgram(0), core.peek_cgram(1)]) & 0x7FFF, + } +} + +fn current_color_window_line(core: &Core) -> PresentedColorWindowLine { + PresentedColorWindowLine { + wh0: core.peek(0x002126), + wh1: core.peek(0x002127), + wh2: core.peek(0x002128), + wh3: core.peek(0x002129), + } +} + +fn presented_backdrop_pixel_rgba( + line: PresentedBackdropLine, + window: PresentedColorWindowLine, + screen_x: usize, + color_math: BackdropColorMath, +) -> [u8; 4] { + let brightness = line.inidisp & 0x0F; + if line.inidisp & 0x80 != 0 || brightness == 0 { + [0x00, 0x00, 0x00, 0xFF] + } else { + snes_color_to_rgba( + color_math.apply_to_backdrop(line.color0, window, screen_x), + brightness, + ) + } +} + +#[derive(Debug, Clone, Copy)] +struct BackdropColorMath { + wobjsel: u8, + wobjlog: u8, + cgwsel: u8, + cgadsub: u8, + fixed_color: u16, +} + +impl BackdropColorMath { + fn from_core(core: &Core) -> Self { + Self { + wobjsel: core.peek(0x002125), + wobjlog: core.peek(0x00212B), + cgwsel: core.peek(0x002130), + cgadsub: core.peek(0x002131), + fixed_color: core.fixed_color(), + } + } + + fn apply_to_backdrop( + self, + color: u16, + window: PresentedColorWindowLine, + screen_x: usize, + ) -> u16 { + let in_color_window = self.in_color_window(window, screen_x); + let clipped = selector_matches((self.cgwsel >> CGWSEL_CLIP_SHIFT) & 0x03, in_color_window); + let prevented = selector_matches( + (self.cgwsel >> CGWSEL_PREVENT_SHIFT) & 0x03, + in_color_window, + ); + let main_color = if clipped { 0 } else { color }; + if prevented || self.cgadsub & CGADSUB_ENABLE_BACKDROP == 0 { + return main_color; + } + + add_subtract_color( + main_color, + self.fixed_color, + self.cgadsub & CGADSUB_SUBTRACT != 0, + self.cgadsub & CGADSUB_HALF != 0, + ) + } + + fn in_color_window(self, window: PresentedColorWindowLine, screen_x: usize) -> bool { + let settings = (self.wobjsel >> COLOR_WINDOW_SHIFT) & 0x0F; + let win1 = window_state( + settings & WINDOW1_ENABLE != 0, + settings & WINDOW1_OUTSIDE != 0, + window_contains(window.wh0, window.wh1, screen_x), + ); + let win2 = window_state( + settings & WINDOW2_ENABLE != 0, + settings & WINDOW2_OUTSIDE != 0, + window_contains(window.wh2, window.wh3, screen_x), + ); + + match (win1, win2) { + (None, None) => true, + (Some(value), None) | (None, Some(value)) => value, + (Some(win1), Some(win2)) => { + match (self.wobjlog >> COLOR_WINDOW_LOGIC_SHIFT) & COLOR_WINDOW_SELECTOR_MASK { + 0 => win1 || win2, + 1 => win1 && win2, + 2 => win1 ^ win2, + _ => !(win1 ^ win2), + } + } + } + } +} + +fn window_contains(left: u8, right: u8, screen_x: usize) -> bool { + left <= right && (usize::from(left)..=usize::from(right)).contains(&screen_x) +} + +fn window_state(enabled: bool, outside: bool, contains: bool) -> Option { + enabled.then_some(if outside { !contains } else { contains }) +} + +fn selector_matches(selector: u8, in_window: bool) -> bool { + match selector { + 0 => false, + 1 => !in_window, + 2 => in_window, + _ => true, + } +} + +fn add_subtract_color(base: u16, fixed: u16, subtract: bool, half: bool) -> u16 { + let mut red = combine_channel(base & 0x1F, fixed & 0x1F, subtract); + let mut green = combine_channel((base >> 5) & 0x1F, (fixed >> 5) & 0x1F, subtract); + let mut blue = combine_channel((base >> 10) & 0x1F, (fixed >> 10) & 0x1F, subtract); + if half { + red /= 2; + green /= 2; + blue /= 2; + } + red | (green << 5) | (blue << 10) +} + +fn combine_channel(base: u16, fixed: u16, subtract: bool) -> u16 { + if subtract { + base.saturating_sub(fixed) + } else { + (base + fixed).min(0x1F) + } +} + +#[cfg(test)] +mod tests { + use super::{ + BackdropColorMath, add_subtract_color, selector_matches, window_contains, window_state, + }; + use nerust_snes_core::{PresentedBackdropLine, PresentedColorWindowLine}; + + #[test] + fn color_window_clip_inside_plus_fixed_color_yields_fixed_color() { + let math = BackdropColorMath { + wobjsel: 0x20, + wobjlog: 0x00, + cgwsel: 0x90, + cgadsub: 0x20, + fixed_color: (31 << 10) | 15, + }; + let window = PresentedColorWindowLine { + wh0: 10, + wh1: 20, + wh2: 0, + wh3: 0, + }; + + assert_eq!(math.apply_to_backdrop(0x7FFF, window, 9), 0x7FFF); + assert_eq!(math.apply_to_backdrop(0x7FFF, window, 10), (31 << 10) | 15); + assert_eq!(math.apply_to_backdrop(0x7FFF, window, 20), (31 << 10) | 15); + assert_eq!(math.apply_to_backdrop(0x7FFF, window, 21), 0x7FFF); + } + + #[test] + fn disabled_window_range_never_contains_pixels() { + assert!(!window_contains(0xFF, 0x00, 0)); + assert_eq!(window_state(true, false, false), Some(false)); + assert_eq!(window_state(true, true, false), Some(true)); + } + + #[test] + fn color_math_selectors_match_expected_regions() { + assert!(!selector_matches(0, true)); + assert!(selector_matches(1, false)); + assert!(selector_matches(2, true)); + assert!(selector_matches(3, false)); + } + + #[test] + fn color_math_adds_and_subtracts_5bit_channels() { + assert_eq!(add_subtract_color(0x001F, 0x0001, false, false), 0x001F); + assert_eq!(add_subtract_color(0x0010, 0x0001, true, false), 0x000F); + assert_eq!(add_subtract_color(0x0010, 0x0002, false, true), 0x0009); + } + + #[test] + fn force_blank_takes_priority_over_color_math() { + let math = BackdropColorMath { + wobjsel: 0x20, + wobjlog: 0x00, + cgwsel: 0x90, + cgadsub: 0x20, + fixed_color: 0x7C1F, + }; + let line = PresentedBackdropLine { + inidisp: 0x8F, + color0: 0x7FFF, + }; + let window = PresentedColorWindowLine { + wh0: 0, + wh1: 255, + wh2: 0, + wh3: 0, + }; + + assert_eq!( + super::presented_backdrop_pixel_rgba(line, window, 0, math), + [0, 0, 0, 0xFF] + ); + } +} diff --git a/snes/render/src/bg1.rs b/snes/render/src/bg1.rs new file mode 100644 index 00000000..29331294 --- /dev/null +++ b/snes/render/src/bg1.rs @@ -0,0 +1,521 @@ +use nerust_snes_core::Core; + +use super::{ + BgLayer, RenderError, SCREEN_HEIGHT, + color::cgram_raw_color, + main_screen_for_line, + mode7::render_mode7_bg1, + presented_bg_line, + tile::{bg_chr_2bpp_pixel, bg_chr_8bpp_pixel, chr_4bpp_pixel, read_tilemap_entry}, + use_presented_bg_scroll, +}; +use nerust_snes_core::PresentedColorWindowLine; + +pub(super) fn render_bg1( + core: &Core, + layer: BgLayer, + brightness: u8, + current_tm: u8, + use_presented_tm: bool, + interlace_enabled: bool, + render_width: usize, + render_height: usize, + rgba: &mut [u8], + raw_output: &mut [u16], + hofs_extra: u16, +) -> Result<(), RenderError> { + if !screen_uses_layer(core, layer, current_tm, use_presented_tm, render_height) { + return Ok(()); + } + + let bgmode = core.peek(0x002105); + let screen_mode = bgmode & 0x07; + let Some(mode) = BgRenderMode::from_bgmode(layer, screen_mode)? else { + return Ok(()); + }; + let high_res_mode = screen_mode == 5 || screen_mode == 6; + if mode == BgRenderMode::Mode7 { + render_mode7_bg1( + core, + brightness, + current_tm, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + rgba, + ); + return Ok(()); + } + + // For Mode7 we write directly to RGBA; for other modes we write to raw_output + // No-op for raw_output in Mode7 path + + let bgsc = core.peek(layer.bgsc_register()); + let bg12nba = core.peek(0x00210B); + let bg34nba = core.peek(0x00210C); + // In Mode 5/6, tiles are always 16 pixels wide. The tile size bit + // (BGMODE bits A/B/C/D) controls the height: 8 or 16 pixels tall. + // In all other modes, tiles are square (8x8 or 16x16). + let (tile_size, tile_height) = if high_res_mode { + (16, if bgmode & layer.tile_size_mask() != 0 { 16 } else { 8 }) + } else { + let s = if bgmode & layer.tile_size_mask() != 0 { 16 } else { 8 }; + (s, s) + }; + let context = Bg1RenderContext { + mode, + tilemap_base: (usize::from(bgsc & 0xFC)) << 9, + chr_base: layer.chr_base(bg12nba, bg34nba), + tile_size, + tile_height, + tilemap_width_tiles: if bgsc & 0x01 != 0 { 64 } else { 32 }, + bpp2_palette_base: bpp2_palette_base(layer, screen_mode), + high_res_mode, + }; + let tilemap_height_tiles = if bgsc & 0x02 != 0 { 64 } else { 32 }; + let tilemap_width_pixels = context.tilemap_width_tiles * context.tile_size; + let tilemap_height_pixels = tilemap_height_tiles * context.tile_height; + let (current_hofs, current_vofs) = layer.current_scroll(core); + let use_presented_scroll = use_presented_bg_scroll(core, layer); + + let hofs_mask = if high_res_mode { 0x7FF } else { 0x3FF }; + + // Window masking: TMW ($212E) controls which layers are masked + // by the color window on the main screen. + let tmw = core.peek(0x00212E); + let layer_tm_mask = layer.tm_mask(); + let window_masked = tmw & layer_tm_mask != 0; + let window_settings = if layer == BgLayer::Bg1 || layer == BgLayer::Bg2 { + core.peek(0x002123) + } else { + core.peek(0x002124) + }; + let layer_window_shift = match layer { + BgLayer::Bg1 => 0, + BgLayer::Bg2 => 4, + BgLayer::Bg3 => 0, + BgLayer::Bg4 => 4, + }; + let win1_setting = (window_settings >> layer_window_shift) & 0x03; + let win2_setting = (window_settings >> (layer_window_shift + 2)) & 0x03; + let wbglog_shift = match layer { + BgLayer::Bg1 => 0, + BgLayer::Bg2 => 2, + BgLayer::Bg3 => 4, + BgLayer::Bg4 => 6, + }; + let window_logic = (core.peek(0x00212A) >> wbglog_shift) & 0x03; + + // Mosaic effect: MOZA register ($2106) + // Bits 0-3: mosaic size, Bits 4-7: enable for BG1-BG4 + let moza = core.peek(0x002106); + let mosaic_size = usize::from(moza & 0x0F) + 1; + let mosaic_enabled = (moza >> (4 + layer.bit_index())) & 0x01 != 0; + + for screen_y in 0..render_height { + let presented_y = screen_y; + if main_screen_for_line(core, presented_y, current_tm, use_presented_tm) & layer_tm_mask + == 0 + { + continue; + } + // Use per-scanline window data if available; otherwise fall back to + // current register values (which retain the previous frame's HDMA writes). + let window_line = core + .presented_color_window_line(presented_y) + .or_else(|| { + // If no captured data, try the current frame's data from the "current" arrays + // by calling presented_color_window_line with a different approach. + None + }) + .unwrap_or(PresentedColorWindowLine { + wh0: core.peek(0x002126), + wh1: core.peek(0x002127), + wh2: core.peek(0x002128), + wh3: core.peek(0x002129), + }); + let wh0 = window_line.wh0; + let wh1 = window_line.wh1; + let wh2 = window_line.wh2; + let wh3 = window_line.wh3; + let presented = use_presented_scroll + .then(|| presented_bg_line(core, layer, presented_y)) + .flatten(); + let hofs = (presented.map_or(usize::from(current_hofs.wrapping_add(hofs_extra)), |line| { + usize::from(line.hofs.wrapping_add(hofs_extra)) + }) & hofs_mask) + % tilemap_width_pixels.max(1); + let raw_vofs = presented.map_or(current_vofs, |line| line.vofs); + // VOFFS bit 0 adjustment: only for true screen interlace (SETINI bit 3). + // Mode 5/6 pseudo-512 mode (SETINI bit 0) does not apply this adjustment. + let vofs_adjust = interlace_enabled && !high_res_mode; + let interlace_field = vofs_adjust && (screen_y & 1) == 1; + let effective_vofs = if interlace_field { + (raw_vofs & 0x3FE) | 0x0001 + } else if vofs_adjust { + raw_vofs & 0x3FE + } else { + raw_vofs & 0x3FF + }; + let vofs = (usize::from(effective_vofs)) % tilemap_height_pixels.max(1); + let bg_y = (presented_y + 1 + vofs) % tilemap_height_pixels; + // Mosaic: quantize Y to block boundary + let mos_y = if mosaic_enabled { + (screen_y / mosaic_size) * mosaic_size + } else { + screen_y + }; + let pixel_bg_y = if mosaic_enabled { + ((mos_y) + 1 + vofs) % tilemap_height_pixels + } else { + bg_y + }; + let row_offset = screen_y * render_width; + for screen_x in 0..render_width { + if window_masked + && in_window( + win1_setting, + win2_setting, + window_logic, + screen_x, + wh0, + wh1, + wh2, + wh3, + ) + { + continue; + } + let bg_x = if mosaic_enabled { + let mos_x = (screen_x / mosaic_size) * mosaic_size; + (mos_x + hofs) % tilemap_width_pixels + } else { + (screen_x + hofs) % tilemap_width_pixels + }; + if let Some(raw) = bg1_pixel(core, &context, bg_x, pixel_bg_y) { + raw_output[row_offset + screen_x] = raw; + } + } + } + + Ok(()) +} + +fn in_window( + win1_setting: u8, + win2_setting: u8, + logic: u8, + screen_x: usize, + wh0: u8, + wh1: u8, + wh2: u8, + wh3: u8, +) -> bool { + // When WH0 > WH1 (inverted), the window covers ALL pixels. + let inv1 = wh0 > wh1; + let in_win1_range = if inv1 { + true + } else { + (wh0..=wh1).contains(&(screen_x as u8)) + }; + let in_win1 = if win1_setting == 0 { + false + } else if win1_setting & 0x01 != 0 { + // 01 = mask inside range; 11 = mask outside when non-inverted, + // mask inside when inverted (inverted window covers all pixels, + // so "mask inside" effectively masks everything). + if win1_setting == 0x03 && !inv1 { + !in_win1_range + } else { + in_win1_range + } + } else { + !in_win1_range + }; + + let inv2 = wh2 > wh3; + let in_win2_range = if inv2 { + true + } else { + (wh2..=wh3).contains(&(screen_x as u8)) + }; + let in_win2 = if win2_setting == 0 { + false + } else if win2_setting & 0x01 != 0 { + if win2_setting == 0x03 && !inv2 { + !in_win2_range + } else { + in_win2_range + } + } else { + !in_win2_range + }; + + match logic { + 0 => in_win1 || in_win2, + 1 => in_win1 && in_win2, + 2 => in_win1 ^ in_win2, + _ => !(in_win1 ^ in_win2), + } +} + +fn screen_uses_layer( + core: &Core, + layer: BgLayer, + current_tm: u8, + use_presented_tm: bool, + render_height: usize, +) -> bool { + if !use_presented_tm { + return current_tm & layer.tm_mask() != 0; + } + + (0..render_height).any(|screen_y| { + main_screen_for_line(core, screen_y, current_tm, use_presented_tm) + & layer.tm_mask() + != 0 + }) +} + +fn bg1_pixel(core: &Core, context: &Bg1RenderContext, bg_x: usize, bg_y: usize) -> Option { + let mut tile_x = bg_x / context.tile_size; + let tile_y = bg_y / context.tile_height; + let entry = read_tilemap_entry( + core, + context.tilemap_base, + context.tilemap_width_tiles, + tile_x, + tile_y, + ); + + let mut tile_pixel_x = bg_x % context.tile_size; + if context.high_res_mode { + let opt = usize::from((entry >> 8) & 0x03); + if opt > tile_pixel_x { + tile_x = tile_x.wrapping_sub(1); + let prev_entry = read_tilemap_entry( + core, + context.tilemap_base, + context.tilemap_width_tiles, + tile_x, + tile_y, + ); + return bg1_pixel_opt_wrapped(core, context, prev_entry, opt, tile_pixel_x, bg_y); + } + tile_pixel_x -= opt; + } + let mut tile_pixel_y = bg_y % context.tile_height; + if entry & 0x4000 != 0 { + tile_pixel_x = context.tile_size - 1 - tile_pixel_x; + } + if entry & 0x8000 != 0 { + tile_pixel_y = context.tile_height - 1 - tile_pixel_y; + } + + let subtile_x = tile_pixel_x / 8; + let subtile_y = tile_pixel_y / 8; + let pixel_x = tile_pixel_x % 8; + let pixel_y = tile_pixel_y % 8; + let tile_number = if context.high_res_mode { + usize::from(entry & 0x00FF) + subtile_x + subtile_y * 16 + } else { + usize::from(entry & 0x03FF) + subtile_x + subtile_y * 16 + }; + let tile_addr = context.chr_base + tile_number * context.mode.tile_bytes(); + let color = match context.mode { + BgRenderMode::Bpp2 => bg_chr_2bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Bpp4 => chr_4bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Bpp8 => bg_chr_8bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Mode7 => unreachable!("Mode7 uses its own renderer"), + }; + if color == 0 && context.mode != BgRenderMode::Bpp8 { + return None; + } + + let tile_palette = if context.high_res_mode { + usize::from((entry >> 10) & 0x03) + } else { + usize::from((entry >> 10) & 0x07) + }; + let color_index = match context.mode { + BgRenderMode::Bpp2 => context.bpp2_palette_base + tile_palette * 4 + usize::from(color), + BgRenderMode::Bpp4 => tile_palette * 16 + usize::from(color), + BgRenderMode::Bpp8 => usize::from(color), + BgRenderMode::Mode7 => unreachable!("Mode7 uses its own renderer"), + }; + Some(cgram_raw_color(core, color_index)) +} + +fn bg1_pixel_opt_wrapped( + core: &Core, + context: &Bg1RenderContext, + entry: u16, + opt: usize, + pixel_x_in: usize, + bg_y: usize, +) -> Option { + let mut tpix_x = pixel_x_in + context.tile_size - opt; + let mut tile_pixel_y = bg_y % context.tile_height; + if entry & 0x4000 != 0 { + tpix_x = context.tile_size - 1 - tpix_x; + } + if entry & 0x8000 != 0 { + tile_pixel_y = context.tile_height - 1 - tile_pixel_y; + } + let subtile_x = tpix_x / 8; + let subtile_y = tile_pixel_y / 8; + let pixel_x = tpix_x % 8; + let pixel_y = tile_pixel_y % 8; + let tile_number = usize::from(entry & 0x00FF) + subtile_x + subtile_y * 16; + let tile_addr = context.chr_base + tile_number * context.mode.tile_bytes(); + let color = match context.mode { + BgRenderMode::Bpp2 => bg_chr_2bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Bpp4 => chr_4bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Bpp8 => bg_chr_8bpp_pixel(core, tile_addr, pixel_x, pixel_y), + BgRenderMode::Mode7 => unreachable!("Mode7 uses its own renderer"), + }; + if color == 0 && context.mode != BgRenderMode::Bpp8 { + return None; + } + let tile_palette = usize::from((entry >> 11) & 0x03); + let color_index = match context.mode { + BgRenderMode::Bpp2 => context.bpp2_palette_base + tile_palette * 4 + usize::from(color), + BgRenderMode::Bpp4 => tile_palette * 16 + usize::from(color), + BgRenderMode::Bpp8 => usize::from(color), + BgRenderMode::Mode7 => unreachable!("Mode7 uses its own renderer"), + }; + Some(cgram_raw_color(core, color_index)) +} + +#[derive(Debug, Clone, Copy)] +struct Bg1RenderContext { + mode: BgRenderMode, + tilemap_base: usize, + chr_base: usize, + tile_size: usize, + tile_height: usize, + tilemap_width_tiles: usize, + bpp2_palette_base: usize, + high_res_mode: bool, +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +enum BgRenderMode { + Bpp2, + Bpp4, + Bpp8, + Mode7, +} + +impl BgRenderMode { + fn from_bgmode(layer: BgLayer, mode: u8) -> Result, RenderError> { + match (layer, mode) { + (BgLayer::Bg1 | BgLayer::Bg2 | BgLayer::Bg3 | BgLayer::Bg4, 0) => Ok(Some(Self::Bpp2)), + (BgLayer::Bg1 | BgLayer::Bg2, 1) => Ok(Some(Self::Bpp4)), + (BgLayer::Bg3, 1) => Ok(Some(Self::Bpp2)), + (BgLayer::Bg4, 1) => Ok(None), + (BgLayer::Bg1 | BgLayer::Bg2, 2) => Ok(Some(Self::Bpp4)), + (BgLayer::Bg1, 3) => Ok(Some(Self::Bpp8)), + (BgLayer::Bg2, 3) => Ok(Some(Self::Bpp4)), + (BgLayer::Bg1, 4) => Ok(Some(Self::Bpp8)), + (BgLayer::Bg2, 4) => Ok(Some(Self::Bpp2)), + (BgLayer::Bg1, 5 | 6) => Ok(Some(Self::Bpp4)), + (BgLayer::Bg2, 5) => Ok(Some(Self::Bpp2)), + (BgLayer::Bg1, 7) => Ok(Some(Self::Mode7)), + (_, 2..=7) => Ok(None), + _ => Err(RenderError::UnsupportedBgMode { mode }), + } + } + + const fn tile_bytes(self) -> usize { + match self { + Self::Bpp2 => 16, + Self::Bpp4 => 32, + Self::Bpp8 => 64, + Self::Mode7 => 0, + } + } +} + +fn bpp2_palette_base(layer: BgLayer, screen_mode: u8) -> usize { + match screen_mode { + 0 => layer.mode0_palette_base(), + 1 if layer == BgLayer::Bg3 => 0, + _ => 0, + } +} + +impl BgLayer { + const fn bgsc_register(self) -> u32 { + match self { + Self::Bg1 => 0x002107, + Self::Bg2 => 0x002108, + Self::Bg3 => 0x002109, + Self::Bg4 => 0x00210A, + } + } + + const fn tile_size_mask(self) -> u8 { + match self { + Self::Bg1 => 0x10, + Self::Bg2 => 0x20, + Self::Bg3 => 0x40, + Self::Bg4 => 0x80, + } + } + + const fn chr_base(self, bg12nba: u8, bg34nba: u8) -> usize { + match self { + Self::Bg1 => ((bg12nba & 0x0F) as usize) << 13, + Self::Bg2 => ((bg12nba >> 4) as usize) << 13, + Self::Bg3 => ((bg34nba & 0x0F) as usize) << 13, + Self::Bg4 => ((bg34nba >> 4) as usize) << 13, + } + } + + fn current_scroll(self, core: &Core) -> (u16, u16) { + match self { + Self::Bg1 => (core.bg1_hofs(), core.bg1_vofs()), + Self::Bg2 => (core.bg2_hofs(), core.bg2_vofs()), + Self::Bg3 => (core.bg3_hofs(), core.bg3_vofs()), + Self::Bg4 => (core.bg4_hofs(), core.bg4_vofs()), + } + } + + const fn mode0_palette_base(self) -> usize { + match self { + Self::Bg1 => 0, + Self::Bg2 => 32, + Self::Bg3 => 64, + Self::Bg4 => 96, + } + } +} + +#[cfg(test)] +mod tests { + use super::{BgLayer, BgRenderMode, bpp2_palette_base}; + + #[test] + fn bpp2_palette_base_uses_mode0_layer_blocks() { + assert_eq!(bpp2_palette_base(BgLayer::Bg1, 0), 0); + assert_eq!(bpp2_palette_base(BgLayer::Bg2, 0), 32); + assert_eq!(bpp2_palette_base(BgLayer::Bg3, 0), 64); + assert_eq!(bpp2_palette_base(BgLayer::Bg4, 0), 96); + } + + #[test] + fn mode1_bg3_uses_first_palette_block() { + assert_eq!(bpp2_palette_base(BgLayer::Bg3, 1), 0); + } + + #[test] + fn all_snes_bg_modes_have_render_mapping() { + for mode in 0..=7 { + for layer in [BgLayer::Bg1, BgLayer::Bg2, BgLayer::Bg3, BgLayer::Bg4] { + assert!(BgRenderMode::from_bgmode(layer, mode).is_ok()); + } + } + } +} diff --git a/snes/render/src/color.rs b/snes/render/src/color.rs new file mode 100644 index 00000000..d03b1bc9 --- /dev/null +++ b/snes/render/src/color.rs @@ -0,0 +1,91 @@ +use nerust_snes_core::Core; + +pub(super) fn cgram_color_rgba(core: &Core, color_index: usize, brightness: u8) -> [u8; 4] { + let base = color_index * 2; + let color = u16::from_le_bytes([core.peek_cgram(base), core.peek_cgram(base + 1)]) & 0x7FFF; + snes_color_to_rgba(color, brightness) +} + +pub(super) fn snes_color_to_rgba(color: u16, brightness: u8) -> [u8; 4] { + let red = scale_channel((color & 0x1F) as u8, brightness); + let green = scale_channel(((color >> 5) & 0x1F) as u8, brightness); + let blue = scale_channel(((color >> 10) & 0x1F) as u8, brightness); + [red, green, blue, 0xFF] +} + +fn scale_channel(channel: u8, brightness: u8) -> u8 { + if brightness == 0 { + return 0; + } + let expanded = (u16::from(channel) << 3) | (u16::from(channel) >> 2); + ((expanded * (u16::from(brightness) + 1) + 8) / 16) as u8 +} + +pub(super) fn cgram_raw_color(core: &Core, color_index: usize) -> u16 { + let base = color_index * 2; + u16::from_le_bytes([core.peek_cgram(base), core.peek_cgram(base + 1)]) & 0x7FFF +} + +pub(super) fn apply_color_math(main_15: u16, sub_15: u16, subtract: bool, half: bool) -> u16 { + let mr = (main_15 >> 0) & 0x1F; + let mg = (main_15 >> 5) & 0x1F; + let mb = (main_15 >> 10) & 0x1F; + let sr = (sub_15 >> 0) & 0x1F; + let sg = (sub_15 >> 5) & 0x1F; + let sb = (sub_15 >> 10) & 0x1F; + + let mut r = if subtract { + mr.saturating_sub(sr) + } else { + (mr + sr).min(31) + }; + let mut g = if subtract { + mg.saturating_sub(sg) + } else { + (mg + sg).min(31) + }; + let mut b = if subtract { + mb.saturating_sub(sb) + } else { + (mb + sb).min(31) + }; + + if half { + r = (r + 1) >> 1; + g = (g + 1) >> 1; + b = (b + 1) >> 1; + } + + r | (g << 5) | (b << 10) +} + +pub(super) fn put_pixel(rgba: &mut [u8], width: usize, x: usize, y: usize, color: [u8; 4]) { + let offset = (y * width + x) * 4; + rgba[offset..offset + 4].copy_from_slice(&color); +} + +pub(super) fn opaque_black_screen(width: usize, height: usize) -> Vec { + let mut rgba = vec![0; width * height * 4]; + for pixel in rgba.chunks_exact_mut(4) { + pixel[3] = 0xFF; + } + rgba +} + +#[cfg(test)] +mod tests { + use super::scale_channel; + + #[test] + fn brightness_scaling_reaches_black_and_full_intensity() { + assert_eq!(scale_channel(0x1F, 0x00), 0x00); + assert_eq!(scale_channel(0x1F, 0x0F), 0xFF); + } + + #[test] + fn bit_replication_maps_5bit_to_8bit_correctly() { + assert_eq!(scale_channel(0x00, 0x0F), 0x00); + assert_eq!(scale_channel(0x1F, 0x0F), 0xFF); + assert_eq!(scale_channel(0x10, 0x0F), 132); // (16<<3)|(16>>2) = 128+4 = 132 + } +} diff --git a/snes/render/src/lib.rs b/snes/render/src/lib.rs new file mode 100644 index 00000000..6a311cef --- /dev/null +++ b/snes/render/src/lib.rs @@ -0,0 +1,592 @@ +mod backdrop; +mod bg1; +mod color; +mod mode7; +mod obj; +mod tile; + +use backdrop::render_presented_backdrop; +use bg1::render_bg1; +use color::{apply_color_math, opaque_black_screen, snes_color_to_rgba}; +use nerust_snes_core::Core; +use obj::render_obj; + +pub const SCREEN_WIDTH: usize = 256; +pub const SCREEN_HEIGHT: usize = 224; + +/// Sentinel value for "no pixel" in raw output buffers. +/// 0xFFFF (bit 15 set) is not a valid 15-bit SNES color, so +/// it safely distinguishes "transparent/no pixel" from CGRAM[0]=0x0000 (black). +const TRANSPARENT: u16 = 0xFFFF; + +pub const MODE5_6_WIDTH: usize = 512; +pub const INTERLACE_HEIGHT: usize = 448; + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub(crate) enum BgLayer { + Bg1, + Bg2, + Bg3, + Bg4, +} + +impl BgLayer { + const fn tm_mask(self) -> u8 { + match self { + Self::Bg1 => 0x01, + Self::Bg2 => 0x02, + Self::Bg3 => 0x04, + Self::Bg4 => 0x08, + } + } + + const fn bit_index(self) -> usize { + match self { + Self::Bg1 => 0, + Self::Bg2 => 1, + Self::Bg3 => 2, + Self::Bg4 => 3, + } + } + + const fn scroll_targets(self) -> (u8, u8) { + match self { + Self::Bg1 => (0x0D, 0x0E), + Self::Bg2 => (0x0F, 0x10), + Self::Bg3 => (0x11, 0x12), + Self::Bg4 => (0x13, 0x14), + } + } +} + +pub(crate) fn use_presented_main_screen(core: &Core) -> bool { + if !hdma_targets_bbus(core, &[0x2C]) { + return false; + } + + let mut first = None; + for line in 0..SCREEN_HEIGHT { + let Some(screen) = core.presented_main_screen_line(line) else { + continue; + }; + let Some(first_screen) = first else { + first = Some(screen); + continue; + }; + if screen != first_screen { + return true; + } + } + false +} + +pub(crate) fn main_screen_for_line( + core: &Core, + screen_y: usize, + current_tm: u8, + use_presented_tm: bool, +) -> u8 { + if use_presented_tm { + core.presented_main_screen_line(screen_y) + .map_or(current_tm, |line| line.tm) + } else { + current_tm + } +} + +pub(crate) fn use_presented_bg_scroll(core: &Core, layer: BgLayer) -> bool { + let (hofs, vofs) = layer.scroll_targets(); + if !hdma_targets_bbus(core, &[hofs, vofs]) { + return false; + } + + let mut first = None; + for line in 0..SCREEN_HEIGHT { + let Some(scroll) = presented_bg_line(core, layer, line) else { + continue; + }; + let Some(first_scroll) = first else { + first = Some(scroll); + continue; + }; + if scroll != first_scroll { + return true; + } + } + false +} + +pub(crate) fn presented_bg_line( + core: &Core, + layer: BgLayer, + screen_y: usize, +) -> Option { + match layer { + BgLayer::Bg1 => core.presented_bg1_line(screen_y), + BgLayer::Bg2 => core.presented_bg2_line(screen_y), + BgLayer::Bg3 => core.presented_bg3_line(screen_y), + BgLayer::Bg4 => core.presented_bg4_line(screen_y), + } +} + +fn hdma_targets_bbus(core: &Core, targets: &[u8]) -> bool { + let hdmaen = core.peek(0x00420C); + for channel in 0..8 { + if hdmaen & (1 << channel) == 0 { + continue; + } + + let base = 0x004300 + channel * 0x10; + let dmap = core.peek(base); + let bbad = core.peek(base + 0x01); + for offset in dma_transfer_offsets(dmap) { + let target = bbad.wrapping_add(*offset); + if targets.contains(&target) { + return true; + } + } + } + false +} + +fn dma_transfer_offsets(dmap: u8) -> &'static [u8] { + match dmap & 0x07 { + 0 => &[0], + 1 => &[0, 1], + 2 | 6 => &[0, 0], + 3 | 7 => &[0, 0, 1, 1], + 4 => &[0, 1, 2, 3], + 5 => &[0, 1, 0, 1], + _ => &[0], + } +} + +#[derive(Debug, thiserror::Error)] +pub enum RenderError { + #[error( + "unsupported BG mode {mode}; SNES renderer expects a normal SNES BG mode in the range 0-7" + )] + UnsupportedBgMode { mode: u8 }, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub struct RenderedScreen { + pub rgba: Vec, + pub width: usize, + pub height: usize, +} + +pub fn render_screen(core: &Core) -> Result { + let tm = core.peek(0x00212C); + let ts = core.peek(0x00212D); + let use_presented_tm: bool = use_presented_main_screen(core); + let use_presented_inidisp = hdma_targets_bbus(core, &[0x00]); + let cgram_hdma_active = hdma_targets_bbus(core, &[0x21]); + + let bgmode = core.peek(0x002105); + let screen_mode = bgmode & 0x07; + let high_res_mode = screen_mode == 5 || screen_mode == 6; + let interlace_enabled = core.interlace_enabled(); + let obj_interlace = core.obj_interlace_enabled(); + let pseudo_hires = core.pseudo_hires_enabled(); + let color_math_supported = screen_mode <= 4 || pseudo_hires; + + let render_width = if high_res_mode || pseudo_hires { + MODE5_6_WIDTH + } else { + SCREEN_WIDTH + }; + let render_height = if interlace_enabled { + INTERLACE_HEIGHT + } else { + SCREEN_HEIGHT + }; + let pixel_count = render_width * render_height; + + if tm == 0 && !use_presented_tm { + return Ok(RenderedScreen { + rgba: render_presented_backdrop( + core, + render_width, + render_height, + use_presented_inidisp, + cgram_hdma_active, + ), + width: render_width, + height: render_height, + }); + } + + let inidisp = core.peek(0x002100); + let brightness = inidisp & 0x0F; + if brightness == 0 && !use_presented_inidisp { + return Ok(RenderedScreen { + rgba: opaque_black_screen(render_width, render_height), + width: render_width, + height: render_height, + }); + } + + let render_brightness = if brightness == 0 { 15 } else { brightness }; + + // --- Render backdrop to RGBA --- + let mut rgba = render_presented_backdrop( + core, + render_width, + render_height, + use_presented_inidisp, + cgram_hdma_active, + ); + + // --- Main screen: render BG layers to raw 15-bit buffer --- + let mut main_raw = vec![TRANSPARENT; pixel_count]; + + render_bg1( + core, + BgLayer::Bg4, + render_brightness, + tm, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut main_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg3, + render_brightness, + tm, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut main_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg2, + render_brightness, + tm, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut main_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg1, + render_brightness, + tm, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut main_raw, + 0, + )?; + + // --- Sub screen: render BG layers for color math and Mode 5/6 interleaving --- + let mut sub_raw = vec![TRANSPARENT; pixel_count]; + if ts != 0 { + render_bg1( + core, + BgLayer::Bg4, + render_brightness, + ts, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut sub_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg3, + render_brightness, + ts, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut sub_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg2, + render_brightness, + ts, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut sub_raw, + 0, + )?; + render_bg1( + core, + BgLayer::Bg1, + render_brightness, + ts, + use_presented_tm, + interlace_enabled, + render_width, + render_height, + &mut rgba, + &mut sub_raw, + 0, + )?; + + if color_math_supported { + let cgwsel = core.peek(0x002130); + let cgadsub = core.peek(0x002131); + let fixed_color = core.fixed_color(); + let cgwsel_enable_main = (cgwsel >> 0) & 0x03; + let cgwsel_disable_main = (cgwsel >> 4) & 0x03; + + let wobjsel = core.peek(0x002125); + let settings = (wobjsel >> 4) & 0x0F; + let window1_setting = settings & 0x03; + let window2_setting = (settings >> 2) & 0x03; + let in_color_window = window1_setting == 0 && window2_setting == 0; + + let cgadsub_bg1 = cgadsub & 0x01 != 0; + let cgadsub_bg2 = cgadsub & 0x02 != 0; + let cgadsub_bg3 = cgadsub & 0x04 != 0; + let cgadsub_bg4 = cgadsub & 0x08 != 0; + let cgadsub_obj = cgadsub & 0x10 != 0; + let cgadsub_backdrop = cgadsub & 0x20 != 0; + let subtract = cgadsub & 0x80 != 0; + let half = cgadsub & 0x40 != 0; + + let backdrop_color0 = + u16::from_le_bytes([core.peek_cgram(0), core.peek_cgram(1)]) & 0x7FFF; + + for i in 0..pixel_count { + let main_raw_val = main_raw[i]; + let sub_raw_val = sub_raw[i]; + + if main_raw_val == TRANSPARENT { + continue; + } + + let layer_participates = cgadsub_bg1 + || cgadsub_bg2 + || cgadsub_bg3 + || cgadsub_bg4 + || cgadsub_obj + || (cgadsub_backdrop && main_raw_val == backdrop_color0); + if !layer_participates { + continue; + } + + let enable = match cgwsel_enable_main { + 0 => false, + 1 => !in_color_window, + 2 => in_color_window, + _ => true, + }; + if !enable { + continue; + } + + let disable = match cgwsel_disable_main { + 0 => false, + 1 => !in_color_window, + 2 => in_color_window, + _ => true, + }; + if disable { + continue; + } + + let sub_source = if sub_raw_val != TRANSPARENT { + sub_raw_val + } else { + fixed_color + }; + main_raw[i] = apply_color_math(main_raw_val, sub_source, subtract, half); + } + } + } + + // --- Composite BG raw data onto RGBA backdrop --- + for i in 0..pixel_count { + let raw = if (high_res_mode || pseudo_hires) && ts != 0 { + if interlace_enabled { + let screen_y = i / render_width; + if screen_y & 1 != 0 { sub_raw[i] } else { main_raw[i] } + } else { + let screen_x = i % render_width; + if screen_x & 1 != 0 { main_raw[i] } else { sub_raw[i] } + } + } else { + main_raw[i] + }; + if raw != TRANSPARENT { + let color = snes_color_to_rgba(raw, render_brightness); + let offset = i * 4; + rgba[offset..offset + 4].copy_from_slice(&color); + } + } + + render_obj( + core, + render_brightness, + tm, + use_presented_tm, + interlace_enabled, + obj_interlace, + render_width, + render_height, + &mut rgba, + ); + + // Apply per-scanline INIDISP forced blanking: scanlines with + // forced blanking (bit 7) or zero brightness must be black. + if use_presented_inidisp { + for screen_y in 0..render_height { + let presented_y = screen_y / (render_height / SCREEN_HEIGHT).max(1); + if let Some(backdrop) = core.presented_backdrop_line(presented_y) { + if backdrop.inidisp & 0x80 != 0 || backdrop.inidisp & 0x0F == 0 { + let row_start = screen_y * render_width * 4; + for pixel in rgba[row_start..row_start + render_width * 4].chunks_exact_mut(4) { + pixel[0] = 0; + pixel[1] = 0; + pixel[2] = 0; + pixel[3] = 0xFF; + } + } + } + } + } + + Ok(RenderedScreen { + rgba, + width: render_width, + height: render_height, + }) +} + +#[cfg(test)] +mod tests { + use super::render_screen; + use nerust_snes_core::{Core, CpuState}; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + + fn build_lorom(reset_vector: u16) -> Vec { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"TEST SCREEN ROM "); + rom[0x7FD5] = 0x30; + rom[0x7FD7] = 0x08; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&reset_vector.to_le_bytes()); + rom + } + + fn run_until_stopped(core: &mut Core, max_steps: usize) { + for _ in 0..max_steps { + core.step().unwrap(); + if core.current_state() == CpuState::Stopped { + return; + } + } + + panic!("core did not stop within {max_steps} steps"); + } + + #[test] + fn brightness_zero_renders_opaque_black_frame() { + let core = Core::from_rom_bytes(&build_lorom(0x8000)).unwrap(); + + let rendered = render_screen(&core).unwrap(); + + assert_eq!(&rendered.rgba[..4], &[0x00, 0x00, 0x00, 0xFF]); + assert_eq!( + &rendered.rgba[rendered.rgba.len() - 4..], + &[0x00, 0x00, 0x00, 0xFF] + ); + } + + #[test] + fn mode0_bg1_uses_the_first_cgram_palette_block() { + let program = [ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x8F, 0x8D, 0x00, 0x21, 0x9C, 0x05, 0x21, + 0xA9, 0x01, 0x8D, 0x2C, 0x21, 0x9C, 0x07, 0x21, 0xA9, 0x01, 0x8D, 0x0B, 0x21, 0xA9, + 0x80, 0x8D, 0x15, 0x21, 0x9C, 0x16, 0x21, 0xA9, 0x10, 0x8D, 0x17, 0x21, 0xA9, 0xFF, + 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, 0x8D, 0x18, + 0x21, 0x8D, 0x19, 0x21, 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, 0x8D, 0x18, 0x21, 0x8D, + 0x19, 0x21, 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, + 0x8D, 0x18, 0x21, 0x8D, 0x19, 0x21, 0x9C, 0x21, 0x21, 0xA9, 0x1F, 0x8D, 0x22, 0x21, + 0x9C, 0x22, 0x21, 0xA9, 0x03, 0x8D, 0x21, 0x21, 0xA9, 0xFF, 0x8D, 0x22, 0x21, 0xA9, + 0x7F, 0x8D, 0x22, 0x21, 0xA9, 0x0F, 0x8D, 0x00, 0x21, 0xDB, + ]; + let mut rom = build_lorom(0x8000); + rom[..program.len()].copy_from_slice(&program); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 256); + + let rendered = render_screen(&core).unwrap(); + assert_eq!(&rendered.rgba[..4], &[0xFF, 0xFF, 0xFF, 0xFF]); + assert_eq!( + &rendered.rgba[rendered.rgba.len() - 4..], + &[0xFF, 0xFF, 0xFF, 0xFF] + ); + } + + #[test] + fn backdrop_color_math_renders_under_enabled_main_screen_layers() { + let program = [ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x8F, 0x8D, 0x00, 0x21, 0x9C, 0x21, 0x21, + 0xA9, 0xFF, 0x8D, 0x22, 0x21, 0xA9, 0x7F, 0x8D, 0x22, 0x21, 0x9C, 0x26, 0x21, 0xA9, + 0xFF, 0x8D, 0x27, 0x21, 0xA9, 0x20, 0x8D, 0x25, 0x21, 0x9C, 0x2B, 0x21, 0xA9, 0x90, + 0x8D, 0x30, 0x21, 0xA9, 0x20, 0x8D, 0x31, 0x21, 0xA9, 0x3F, 0x8D, 0x32, 0x21, 0xA9, + 0x01, 0x8D, 0x2C, 0x21, 0xA9, 0x0F, 0x8D, 0x00, 0x21, 0xDB, + ]; + let mut rom = build_lorom(0x8000); + rom[..program.len()].copy_from_slice(&program); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 256); + + let rendered = render_screen(&core).unwrap(); + assert_eq!(&rendered.rgba[..4], &[0xFF, 0x00, 0x00, 0xFF]); + } + + #[test] + fn mode7_bg1_uses_tilemap_low_bytes_and_tile_pixels_high_bytes() { + let program = [ + 0x18, 0xFB, 0xC2, 0x30, 0xE2, 0x20, 0xA9, 0x8F, 0x8D, 0x00, 0x21, 0xA9, 0x07, 0x8D, + 0x05, 0x21, 0xA9, 0x01, 0x8D, 0x2C, 0x21, 0x9C, 0x1A, 0x21, 0x9C, 0x1B, 0x21, 0xA9, + 0x01, 0x8D, 0x1B, 0x21, 0x9C, 0x1E, 0x21, 0xA9, 0x01, 0x8D, 0x1E, 0x21, 0x9C, 0x15, + 0x21, 0x9C, 0x16, 0x21, 0x9C, 0x17, 0x21, 0xA9, 0x02, 0x8D, 0x18, 0x21, 0xA9, 0x88, + 0x8D, 0x16, 0x21, 0x9C, 0x17, 0x21, 0xA9, 0x05, 0x8D, 0x19, 0x21, 0xA9, 0x05, 0x8D, + 0x21, 0x21, 0xA9, 0x1F, 0x8D, 0x22, 0x21, 0x9C, 0x22, 0x21, 0xA9, 0x0F, 0x8D, 0x00, + 0x21, 0xDB, + ]; + let mut rom = build_lorom(0x8000); + rom[..program.len()].copy_from_slice(&program); + + let mut core = Core::from_rom_bytes(&rom).unwrap(); + run_until_stopped(&mut core, 256); + + let rendered = render_screen(&core).unwrap(); + assert_eq!(&rendered.rgba[..4], &[0xFF, 0x00, 0x00, 0xFF]); + } +} diff --git a/snes/render/src/mode7.rs b/snes/render/src/mode7.rs new file mode 100644 index 00000000..c559ad00 --- /dev/null +++ b/snes/render/src/mode7.rs @@ -0,0 +1,230 @@ +use nerust_snes_core::Core; + +use super::{ + BgLayer, SCREEN_HEIGHT, + color::{cgram_color_rgba, put_pixel}, + main_screen_for_line, presented_bg_line, use_presented_bg_scroll, +}; + +pub(super) fn render_mode7_bg1( + core: &Core, + brightness: u8, + current_tm: u8, + use_presented_tm: bool, + interlace_enabled: bool, + render_width: usize, + render_height: usize, + rgba: &mut [u8], +) { + let registers = core.mode7_registers(); + let a = i32::from(registers.a); + let b = i32::from(registers.b); + let c = i32::from(registers.c); + let d = i32::from(registers.d); + let center_x = i32::from(registers.x); + let center_y = i32::from(registers.y); + let m7sel = registers.m7sel; + let repeat = m7sel & 0x03; + let extbg = m7sel & 0x80 != 0; + let raw_hofs = i32::from(core.bg1_hofs()) & 0x3FF; + let raw_vofs = i32::from(core.bg1_vofs()) & 0x3FF; + // Mode 7 scroll offsets are 10-bit signed values. + // Sign-extend from 10 bits to match bsnes behavior. + let current_hofs = if raw_hofs & 0x200 != 0 { + raw_hofs | !0x3FF + } else { + raw_hofs + }; + let current_vofs = if raw_vofs & 0x200 != 0 { + raw_vofs | !0x3FF + } else { + raw_vofs + }; + let use_presented_scroll = use_presented_bg_scroll(core, BgLayer::Bg1); + + let height_ratio = (render_height / SCREEN_HEIGHT).max(1); + for screen_y in 0..render_height { + let presented_y = screen_y / height_ratio; + if main_screen_for_line(core, presented_y, current_tm, use_presented_tm) + & BgLayer::Bg1.tm_mask() + == 0 + { + continue; + } + let presented = use_presented_scroll + .then(|| presented_bg_line(core, BgLayer::Bg1, presented_y)) + .flatten(); + let raw_vofs = presented.map_or(current_vofs, |line| { + let raw = i32::from(line.vofs) & 0x3FF; + if raw & 0x200 != 0 { raw | !0x3FF } else { raw } + }); + let interlace_field = interlace_enabled && (screen_y & 1) == 1; + let effective_vofs = if interlace_field { + (raw_vofs & !1) | 1 + } else if interlace_enabled { + raw_vofs & !1 + } else { + raw_vofs + }; + let hofs = presented.map_or(current_hofs, |line| { + let raw = i32::from(line.hofs) & 0x3FF; + if raw & 0x200 != 0 { raw | !0x3FF } else { raw } + }); + let vofs = effective_vofs; + + // bsnes-style two-step Mode 7 coordinate computation: + // 1. Per-scanline origin (with 6-bit sub-pixel truncation) + // 2. Per-pixel contribution + let dx = hofs - center_x; + let dy = vofs - center_y; + let mode7_screen_y = presented_y as i32; + let origin_x = + ((a * dx) & !63) + ((b * dy) & !63) + ((b * mode7_screen_y) & !63) + (center_x << 8); + let origin_y = + ((c * dx) & !63) + ((d * dy) & !63) + ((d * mode7_screen_y) & !63) + (center_y << 8); + + for screen_x in 0..render_width { + let mode7_screen_x = screen_x as i32; + let transformed_x = (origin_x + a * mode7_screen_x) >> 8; + let transformed_y = (origin_y + c * mode7_screen_x) >> 8; + + let palette = mode7_pixel_value(core, transformed_x, transformed_y, repeat); + // In EXTBG mode, BG1 pixels with bit 5 set are handled by + // BG2 instead (BG2 overlay pass follows this one). + if extbg && palette & 0x20 != 0 { + continue; + } + let color = cgram_color_rgba(core, usize::from(palette), brightness); + put_pixel(rgba, render_width, screen_x, screen_y, color); + } + } + + // In EXTBG mode, BG2 overlays on top of BG1 using the same Mode 7 + // coordinates but interpreting the pixel byte differently: + // bits 0-6 = BG2 color index (0-127) + // bit 7 = BG2 priority + // When BG2 color index is 0, the pixel is transparent and BG1 shows through. + if extbg { + render_mode7_bg2_overlay( + core, + brightness, + a, + b, + c, + d, + center_x, + center_y, + repeat, + current_hofs, + current_vofs, + use_presented_scroll, + interlace_enabled, + render_width, + render_height, + rgba, + ); + } +} + +fn render_mode7_bg2_overlay( + core: &Core, + brightness: u8, + a: i32, + b: i32, + c: i32, + d: i32, + center_x: i32, + center_y: i32, + repeat: u8, + current_hofs: i32, + current_vofs: i32, + use_presented_scroll: bool, + interlace_enabled: bool, + render_width: usize, + render_height: usize, + rgba: &mut [u8], +) { + let height_ratio = (render_height / SCREEN_HEIGHT).max(1); + for screen_y in 0..render_height { + let presented_y = screen_y / height_ratio; + let presented = use_presented_scroll + .then(|| presented_bg_line(core, BgLayer::Bg1, presented_y)) + .flatten(); + let raw_vofs = presented.map_or(current_vofs, |line| { + let raw = i32::from(line.vofs) & 0x3FF; + if raw & 0x200 != 0 { raw | !0x3FF } else { raw } + }); + let interlace_field = interlace_enabled && (screen_y & 1) == 1; + let effective_vofs = if interlace_field { + (raw_vofs & !1) | 1 + } else if interlace_enabled { + raw_vofs & !1 + } else { + raw_vofs + }; + let hofs = presented.map_or(current_hofs, |line| { + let raw = i32::from(line.hofs) & 0x3FF; + if raw & 0x200 != 0 { raw | !0x3FF } else { raw } + }); + let vofs = effective_vofs; + + let dx = hofs - center_x; + let dy = vofs - center_y; + let mode7_screen_y = presented_y as i32; + let origin_x = + ((a * dx) & !63) + ((b * dy) & !63) + ((b * mode7_screen_y) & !63) + (center_x << 8); + let origin_y = + ((c * dx) & !63) + ((d * dy) & !63) + ((d * mode7_screen_y) & !63) + (center_y << 8); + + for screen_x in 0..render_width { + let mode7_screen_x = screen_x as i32; + let transformed_x = (origin_x + a * mode7_screen_x) >> 8; + let transformed_y = (origin_y + c * mode7_screen_x) >> 8; + + // BG2 pixel interpretation (per Fullsnes EXTBG): + // bits 0-2: BG1 color index (already handled in BG1 pass) + // bit 5: BG2 enable (1 = force BG2 overlay) + // bits 0-6: BG2 color index (when BG2 is enabled) + let raw = mode7_pixel_value(core, transformed_x, transformed_y, repeat); + if raw & 0x20 == 0 { + continue; + } + let bg2_color = raw & 0x7F; + if bg2_color == 0 { + continue; + } + let color = cgram_color_rgba(core, usize::from(bg2_color), brightness); + put_pixel(rgba, render_width, screen_x, screen_y, color); + } + } +} + +pub(super) fn mode7_pixel_value( + core: &Core, + transformed_x: i32, + transformed_y: i32, + repeat: u8, +) -> u8 { + let out_of_bounds_mask: i32 = !1023; + let out_of_bounds = (transformed_x | transformed_y) & out_of_bounds_mask != 0; + + let tile_x = ((transformed_x >> 3) as u32 & 0x7F) as usize; + let tile_y = ((transformed_y >> 3) as u32 & 0x7F) as usize; + let pixel_x = (transformed_x as u32 & 0x07) as usize; + let pixel_y = (transformed_y as u32 & 0x07) as usize; + + let tile_number = if repeat == 3 && out_of_bounds { + 0 + } else { + usize::from(core.peek_vram((tile_y * 128 + tile_x) * 2)) + }; + + if repeat == 2 && out_of_bounds { + 0 + } else { + core.peek_vram((tile_number * 64 + pixel_y * 8 + pixel_x) * 2 + 1) + } +} + +#[cfg(test)] +mod tests {} diff --git a/snes/render/src/obj.rs b/snes/render/src/obj.rs new file mode 100644 index 00000000..b9c9c600 --- /dev/null +++ b/snes/render/src/obj.rs @@ -0,0 +1,308 @@ +use nerust_snes_core::Core; + +use super::{ + SCREEN_HEIGHT, + color::{cgram_color_rgba, put_pixel}, + main_screen_for_line, + tile::chr_4bpp_pixel, +}; + +const OBJ_TILE_SIZE: u8 = 8; +const OBJ_SPRITES_PER_SCANLINE_LIMIT: usize = 32; +const OBJ_TILE_SLIVERS_PER_SCANLINE_LIMIT: usize = 34; + +pub(super) fn render_obj( + core: &Core, + brightness: u8, + current_tm: u8, + use_presented_tm: bool, + interlace_enabled: bool, + obj_interlace: bool, + render_width: usize, + render_height: usize, + rgba: &mut [u8], +) { + if !screen_uses_obj(core, current_tm, use_presented_tm, render_height) { + return; + } + + let obsel = core.peek(0x002101); + let (small_size, large_size) = obj_size_pair((obsel >> 5) & 0x07); + let sprites = collect_obj_sprites(core, small_size, large_size); + + let height_ratio = (render_height / SCREEN_HEIGHT).max(1); + + for screen_y in 0..render_height { + let presented_y = screen_y / height_ratio; + if main_screen_for_line(core, presented_y, current_tm, use_presented_tm) & 0x10 == 0 { + continue; + } + let interlace_field = interlace_enabled && (screen_y & 1) == 1; + let slivers = obj_slivers_for_scanline(&sprites, presented_y); + for sliver in slivers.iter().rev() { + if obj_interlace && ((sliver.sprite.attributes & 0x01) != 0) != interlace_field { + continue; + } + render_obj_sliver( + core, + obsel, + brightness, + rgba, + render_width, + screen_y, + presented_y, + *sliver, + obj_interlace, + ); + } + } +} + +fn screen_uses_obj( + core: &Core, + current_tm: u8, + use_presented_tm: bool, + render_height: usize, +) -> bool { + if !use_presented_tm { + return current_tm & 0x10 != 0; + } + + let height_ratio = (render_height / SCREEN_HEIGHT).max(1); + (0..render_height).step_by(height_ratio).any(|screen_y| { + main_screen_for_line(core, screen_y / height_ratio, current_tm, use_presented_tm) & 0x10 + != 0 + }) +} + +fn collect_obj_sprites(core: &Core, small_size: ObjSize, large_size: ObjSize) -> Vec { + (0..128) + .map(|sprite_index| { + let base = sprite_index * 4; + let x_low = core.peek_oam(base); + let y = core.peek_oam(base + 1); + let tile = core.peek_oam(base + 2); + let attributes = core.peek_oam(base + 3); + let extra = core.peek_oam(512 + sprite_index / 4); + let pair_shift = (sprite_index % 4) * 2; + let x_high = (extra >> pair_shift) & 0x01 != 0; + let large = (extra >> (pair_shift + 1)) & 0x01 != 0; + let size = if large { large_size } else { small_size }; + + let x = if x_high { + i16::from(x_low) - 256 + } else { + i16::from(x_low) + }; + let mut y = i16::from(y); + if y >= SCREEN_HEIGHT as i16 { + y -= 256; + } + + ObjSprite { + x, + y, + tile, + attributes, + size, + } + }) + .collect() +} + +fn obj_slivers_for_scanline(sprites: &[ObjSprite], screen_y: usize) -> Vec { + let mut selected_sprites = 0; + let mut slivers = Vec::new(); + + for &sprite in sprites { + if !obj_contains_scanline(sprite, screen_y) { + continue; + } + if selected_sprites == OBJ_SPRITES_PER_SCANLINE_LIMIT { + break; + } + selected_sprites += 1; + + let columns = sprite.size.width / OBJ_TILE_SIZE; + for tile_column in 0..columns { + if slivers.len() == OBJ_TILE_SLIVERS_PER_SCANLINE_LIMIT { + return slivers; + } + slivers.push(ObjSliver { + sprite, + tile_column, + }); + } + } + + slivers +} + +fn obj_contains_scanline(sprite: ObjSprite, screen_y: usize) -> bool { + let screen_y = screen_y as i16; + let height = i16::from(sprite.size.height); + screen_y >= sprite.y && screen_y < sprite.y + height +} + +fn render_obj_sliver( + core: &Core, + obsel: u8, + brightness: u8, + rgba: &mut [u8], + render_width: usize, + screen_y: usize, + presented_y: usize, + sliver: ObjSliver, + obj_interlace: bool, +) { + let sprite_y = presented_y as i16 - sliver.sprite.y; + let source_y = if sliver.sprite.attributes & 0x80 != 0 { + sliver.sprite.size.height - 1 - sprite_y as u8 + } else { + sprite_y as u8 + }; + let tile_row = usize::from(source_y / OBJ_TILE_SIZE); + let pixel_y = usize::from(source_y % OBJ_TILE_SIZE); + let sliver_x_start = sliver.tile_column * OBJ_TILE_SIZE; + + for pixel_in_sliver in 0..OBJ_TILE_SIZE { + let sprite_x = sliver_x_start + pixel_in_sliver; + let target_x = sliver.sprite.x + i16::from(sprite_x); + if !(0..render_width as i16).contains(&target_x) { + continue; + } + + let source_x = if sliver.sprite.attributes & 0x40 != 0 { + sliver.sprite.size.width - 1 - sprite_x + } else { + sprite_x + }; + let tile_column = usize::from(source_x / OBJ_TILE_SIZE); + let pixel_x = usize::from(source_x % OBJ_TILE_SIZE); + let tile_number = if obj_interlace { + usize::from(sliver.sprite.tile) + tile_column + tile_row * 16 + } else { + (usize::from(sliver.sprite.tile) | (usize::from(sliver.sprite.attributes & 0x01) << 8)) + + tile_column + + tile_row * 16 + }; + let tile_addr = obj_tile_address(obsel, tile_number); + let color = chr_4bpp_pixel(core, tile_addr, pixel_x, pixel_y); + if color == 0 { + continue; + } + + let palette = usize::from((sliver.sprite.attributes >> 1) & 0x07); + let color = cgram_color_rgba(core, 128 + palette * 16 + usize::from(color), brightness); + put_pixel(rgba, render_width, target_x as usize, screen_y, color); + } +} + +fn obj_tile_address(obsel: u8, tile_number: usize) -> usize { + let base = usize::from(obsel & 0x07) * 0x4000; + let gap = usize::from((obsel >> 3) & 0x03) * 0x2000; + base + tile_number * 32 + ((tile_number >> 8) * gap) +} + +fn obj_size_pair(size_select: u8) -> (ObjSize, ObjSize) { + match size_select { + 0 => (ObjSize::new(8, 8), ObjSize::new(16, 16)), + 1 => (ObjSize::new(8, 8), ObjSize::new(32, 32)), + 2 => (ObjSize::new(8, 8), ObjSize::new(64, 64)), + 3 => (ObjSize::new(16, 16), ObjSize::new(32, 32)), + 4 => (ObjSize::new(16, 16), ObjSize::new(64, 64)), + 5 => (ObjSize::new(32, 32), ObjSize::new(64, 64)), + 6 => (ObjSize::new(16, 32), ObjSize::new(32, 64)), + _ => (ObjSize::new(16, 32), ObjSize::new(32, 32)), + } +} + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +struct ObjSize { + width: u8, + height: u8, +} + +impl ObjSize { + const fn new(width: u8, height: u8) -> Self { + Self { width, height } + } +} + +#[derive(Debug, Clone, Copy)] +struct ObjSprite { + x: i16, + y: i16, + tile: u8, + attributes: u8, + size: ObjSize, +} + +#[derive(Debug, Clone, Copy)] +struct ObjSliver { + sprite: ObjSprite, + tile_column: u8, +} + +#[cfg(test)] +mod tests { + use super::{ObjSize, ObjSprite, obj_slivers_for_scanline, obj_tile_address}; + + #[test] + fn obj_tile_address_applies_gap_to_secondary_page() { + assert_eq!(obj_tile_address(0b0000_1000, 0x00FF), 0x1FE0); + assert_eq!(obj_tile_address(0b0000_1000, 0x0100), 0x4000); + } + + #[test] + fn obj_scanline_selection_keeps_only_first_thirty_two_sprites() { + let sprites = (0..36) + .map(|index| test_obj(index, 0, 8, 8)) + .collect::>(); + + let slivers = obj_slivers_for_scanline(&sprites, 0); + + assert_eq!(slivers.len(), 32); + assert_eq!(slivers.first().unwrap().sprite.tile, 0); + assert_eq!(slivers.last().unwrap().sprite.tile, 31); + } + + #[test] + fn obj_scanline_selection_keeps_only_first_thirty_four_tile_slivers() { + let sprites = (0..12) + .map(|index| test_obj(index, 0, 32, 32)) + .collect::>(); + + let slivers = obj_slivers_for_scanline(&sprites, 0); + + assert_eq!(slivers.len(), 34); + assert_eq!(slivers[31].sprite.tile, 7); + assert_eq!(slivers[31].tile_column, 3); + assert_eq!(slivers[32].sprite.tile, 8); + assert_eq!(slivers[32].tile_column, 0); + assert_eq!(slivers[33].sprite.tile, 8); + assert_eq!(slivers[33].tile_column, 1); + } + + #[test] + fn obj_scanline_selection_counts_offscreen_sprite_tile_slivers() { + let sprites = (0..9) + .map(|index| test_obj(index, -256, 32, 32)) + .collect::>(); + + let slivers = obj_slivers_for_scanline(&sprites, 0); + + assert_eq!(slivers.len(), 34); + assert_eq!(slivers.last().unwrap().sprite.tile, 8); + } + + fn test_obj(index: usize, x: i16, width: u8, height: u8) -> ObjSprite { + ObjSprite { + x, + y: 0, + tile: index as u8, + attributes: 0, + size: ObjSize::new(width, height), + } + } +} diff --git a/snes/render/src/tile.rs b/snes/render/src/tile.rs new file mode 100644 index 00000000..8c814dae --- /dev/null +++ b/snes/render/src/tile.rs @@ -0,0 +1,152 @@ +use nerust_snes_core::Core; + +pub(super) fn read_tilemap_entry( + core: &Core, + tilemap_base: usize, + tilemap_width_tiles: usize, + tile_x: usize, + tile_y: usize, +) -> u16 { + let quadrant_columns = tilemap_width_tiles / 32; + let quadrant = (tile_y / 32) * quadrant_columns + (tile_x / 32); + let quadrant_base = tilemap_base.wrapping_add(quadrant.wrapping_mul(2048)); + let entry_offset = ((tile_y % 32) * 32 + (tile_x % 32)) * 2; + u16::from_le_bytes([ + core.peek_vram(quadrant_base + entry_offset), + core.peek_vram(quadrant_base + entry_offset + 1), + ]) +} + +#[cfg(test)] +fn decode_2bpp_pixel(tile: &[u8], x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (tile[row] >> shift) & 0x01; + let plane1 = (tile[row + 1] >> shift) & 0x01; + plane0 | (plane1 << 1) +} + +pub(super) fn bg_chr_2bpp_pixel(core: &Core, tile_addr: usize, x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (core.peek_vram(tile_addr + row) >> shift) & 0x01; + let plane1 = (core.peek_vram(tile_addr + row + 1) >> shift) & 0x01; + plane0 | (plane1 << 1) +} + +#[cfg(test)] +fn decode_4bpp_pixel(tile: &[u8], x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (tile[row] >> shift) & 0x01; + let plane1 = (tile[row + 1] >> shift) & 0x01; + let plane2 = (tile[0x10 + row] >> shift) & 0x01; + let plane3 = (tile[0x10 + row + 1] >> shift) & 0x01; + plane0 | (plane1 << 1) | (plane2 << 2) | (plane3 << 3) +} + +pub(super) fn chr_4bpp_pixel(core: &Core, tile_addr: usize, x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (core.peek_vram(tile_addr + row) >> shift) & 0x01; + let plane1 = (core.peek_vram(tile_addr + row + 1) >> shift) & 0x01; + let plane2 = (core.peek_vram(tile_addr + 0x10 + row) >> shift) & 0x01; + let plane3 = (core.peek_vram(tile_addr + 0x10 + row + 1) >> shift) & 0x01; + plane0 | (plane1 << 1) | (plane2 << 2) | (plane3 << 3) +} + +#[cfg(test)] +fn decode_8bpp_pixel(tile: &[u8], x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (tile[row] >> shift) & 0x01; + let plane1 = (tile[row + 1] >> shift) & 0x01; + let plane2 = (tile[0x10 + row] >> shift) & 0x01; + let plane3 = (tile[0x10 + row + 1] >> shift) & 0x01; + let plane4 = (tile[0x20 + row] >> shift) & 0x01; + let plane5 = (tile[0x20 + row + 1] >> shift) & 0x01; + let plane6 = (tile[0x30 + row] >> shift) & 0x01; + let plane7 = (tile[0x30 + row + 1] >> shift) & 0x01; + plane0 + | (plane1 << 1) + | (plane2 << 2) + | (plane3 << 3) + | (plane4 << 4) + | (plane5 << 5) + | (plane6 << 6) + | (plane7 << 7) +} + +pub(super) fn bg_chr_8bpp_pixel(core: &Core, tile_addr: usize, x: usize, y: usize) -> u8 { + let row = y * 2; + let shift = 7 - x; + let plane0 = (core.peek_vram(tile_addr + row) >> shift) & 0x01; + let plane1 = (core.peek_vram(tile_addr + row + 1) >> shift) & 0x01; + let plane2 = (core.peek_vram(tile_addr + 0x10 + row) >> shift) & 0x01; + let plane3 = (core.peek_vram(tile_addr + 0x10 + row + 1) >> shift) & 0x01; + let plane4 = (core.peek_vram(tile_addr + 0x20 + row) >> shift) & 0x01; + let plane5 = (core.peek_vram(tile_addr + 0x20 + row + 1) >> shift) & 0x01; + let plane6 = (core.peek_vram(tile_addr + 0x30 + row) >> shift) & 0x01; + let plane7 = (core.peek_vram(tile_addr + 0x30 + row + 1) >> shift) & 0x01; + plane0 + | (plane1 << 1) + | (plane2 << 2) + | (plane3 << 3) + | (plane4 << 4) + | (plane5 << 5) + | (plane6 << 6) + | (plane7 << 7) +} + +#[cfg(test)] +mod tests { + use super::{decode_2bpp_pixel, decode_4bpp_pixel, decode_8bpp_pixel}; + + #[test] + fn decode_2bpp_pixel_reads_planar_tile_bits() { + let tile = [ + 0b0101_0101, + 0b0011_0011, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + 0, + ]; + + assert_eq!(decode_2bpp_pixel(&tile, 0, 0), 0); + assert_eq!(decode_2bpp_pixel(&tile, 1, 0), 1); + assert_eq!(decode_2bpp_pixel(&tile, 3, 0), 3); + assert_eq!(decode_2bpp_pixel(&tile, 4, 0), 0); + } + + #[test] + fn decode_4bpp_pixel_reads_all_four_bitplanes() { + let mut tile = [0; 32]; + tile[0] = 0b1000_0000; + tile[0x10] = 0b1000_0000; + tile[0x11] = 0b1000_0000; + + assert_eq!(decode_4bpp_pixel(&tile, 0, 0), 0b1101); + } + + #[test] + fn decode_8bpp_pixel_reads_all_eight_bitplanes() { + let mut tile = [0; 64]; + tile[0] = 0b1000_0000; + tile[0x10] = 0b1000_0000; + tile[0x20] = 0b1000_0000; + tile[0x30] = 0b1000_0000; + + assert_eq!(decode_8bpp_pixel(&tile, 0, 0), 0b0101_0101); + } +} diff --git a/snes/rom_test/Cargo.toml b/snes/rom_test/Cargo.toml new file mode 100644 index 00000000..11e4f91d --- /dev/null +++ b/snes/rom_test/Cargo.toml @@ -0,0 +1,20 @@ +[package] +name = "nerust_snes_rom_test" +version.workspace = true +authors.workspace = true +license.workspace = true +edition.workspace = true +rust-version.workspace = true +build = "build.rs" + +[dependencies] +clap.workspace = true +nerust_crc64_hasher.workspace = true +nerust_snes_core.workspace = true +nerust_snes_render.workspace = true +png.workspace = true +serde.workspace = true +serde_derive.workspace = true +serde_yaml.workspace = true +sevenz-rust2.workspace = true +thiserror.workspace = true diff --git a/snes/rom_test/build.rs b/snes/rom_test/build.rs new file mode 100644 index 00000000..1c1e0840 --- /dev/null +++ b/snes/rom_test/build.rs @@ -0,0 +1,61 @@ +use std::env; +use std::fmt::Write as _; +use std::fs; +use std::path::PathBuf; + +fn main() { + let manifest_path = + PathBuf::from(env::var("CARGO_MANIFEST_DIR").expect("manifest dir")).join("rom_tests.yaml"); + println!("cargo::rerun-if-changed={}", manifest_path.display()); + + let manifest_source = + fs::read_to_string(&manifest_path).expect("ROM test manifest should be readable"); + let case_ids = manifest_source + .lines() + .filter_map(extract_case_id) + .collect::>(); + assert!( + !case_ids.is_empty(), + "ROM test manifest must contain at least one case id" + ); + + let mut generated = String::new(); + writeln!( + generated, + "// @generated by snes/rom_test/build.rs - do not edit manually.\n\ + const GENERATED_ROM_CASE_COUNT: usize = {};", + case_ids.len() + ) + .unwrap(); + + for (index, case_id) in case_ids.iter().enumerate() { + writeln!( + generated, + "#[test]\nfn {}() {{\n run_generated_manifest_case({case_id:?});\n}}\n", + test_name(index, case_id), + ) + .unwrap(); + } + + let out_dir = PathBuf::from(env::var("OUT_DIR").expect("OUT_DIR should be available")); + fs::write(out_dir.join("generated_rom_manifest_tests.rs"), generated) + .expect("generated ROM tests should be written"); +} + +fn extract_case_id(line: &str) -> Option { + line.trim_start() + .strip_prefix("- id: ") + .map(|case_id| case_id.trim().to_string()) +} + +fn test_name(index: usize, case_id: &str) -> String { + let mut name = format!("rom_case_{index:04}_"); + for character in case_id.chars() { + if character.is_ascii_alphanumeric() { + name.push(character.to_ascii_lowercase()); + } else { + name.push('_'); + } + } + name +} diff --git a/snes/rom_test/rom_tests.yaml b/snes/rom_test/rom_tests.yaml new file mode 100644 index 00000000..3fd90d4e --- /dev/null +++ b/snes/rom_test/rom_tests.yaml @@ -0,0 +1,3134 @@ +# yamllint disable rule:line-length +rom_root: ../../roms +cases: + - id: cputest-basic-final-state + description: > + The upstream gilyon basic 65C816 CPU test ROM reaches the published final state from cputest/tests-basic.txt. + + rom: snes-tests/cputest/cputest-basic.sfc + max_steps: 6651904 + check_interval_steps: 6651904 + expected_screen_hash: "0xB6B9DE953F18A401" + assertions: + - kind: bus_u16 + address: "0x0010" + expected: "0x0452" + - kind: bus_u16 + address: "0x0012" + expected: "0xCC19" + - kind: bus_u16 + address: "0x0014" + expected: "0x3456" + - kind: bus_u16 + address: "0x0016" + expected: "0x5678" + - kind: bus_u16 + address: "0x0018" + expected: "0x0028" + - kind: bus_u16 + address: "0x001A" + expected: "0x01EF" + - kind: bus_u16 + address: "0x001C" + expected: "0x0000" + - kind: bus_u8 + address: "0x001E" + expected: "0x00" + - id: cputest-full-final-state + description: > + The upstream gilyon full 65C816 CPU test ROM reaches the published final state from cputest/tests-full.txt. + + rom: snes-tests/cputest/cputest-full.sfc + max_steps: 9633792 + check_interval_steps: 9633792 + expected_screen_hash: "0xA05D7EE0B5E1FD17" + assertions: + - kind: bus_u16 + address: "0x0010" + expected: "0x0649" + - kind: bus_u16 + address: "0x0012" + expected: "0xCC5A" + - kind: bus_u16 + address: "0x0014" + expected: "0x3456" + - kind: bus_u16 + address: "0x0016" + expected: "0x5678" + - kind: bus_u16 + address: "0x0018" + expected: "0x0028" + - kind: bus_u16 + address: "0x001A" + expected: "0x01EF" + - kind: bus_u16 + address: "0x001C" + expected: "0x0000" + - kind: bus_u8 + address: "0x001E" + expected: "0x00" + - id: spctest-opcodes-final-state + description: > + The public SPC-700 instruction test ROM completes all non-SLEEP/STOP opcode cases, leaves the CPU-visible result port clear, and preserves the final APU-side test/result state with a deterministic final screen capture. + + rom: snes-tests/spctest/spctest.sfc + max_steps: 4000000 + check_interval_steps: 4000000 + expected_screen_hash: "0x6355F99FAC09A849" + assertions: + - kind: bus_u16 + address: "0x002142" + expected: "0x0000" + - kind: apu_ram_u16 + address: "0x0010" + expected: "0x0557" + - kind: apu_ram_u8 + address: "0x0012" + expected: "0x58" + - kind: apu_ram_u8 + address: "0x0015" + expected: "0x48" + - id: apu-dsp-register-smoke-final-state + description: > + The self-authored APU DSP register smoke ROM uploads an SPC700 program through the IPL protocol and verifies DSP data register round-trips, DSP address reads, auxiliary APU IO bytes, and CPU-visible APU result ports. + + rom: snes-apu-tests/dsp-register-smoke/build/ApuDspRegisterSmoke.sfc + max_steps: 2400 + check_interval_steps: 2400 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0xA5" + - kind: wram_u8 + address: "0x0001" + expected: "0x7F" + - kind: wram_u8 + address: "0x0002" + expected: "0x40" + - kind: wram_u8 + address: "0x0003" + expected: "0x2C" + - kind: apu_ram_u8 + address: "0x0020" + expected: "0x7F" + - kind: apu_ram_u8 + address: "0x0021" + expected: "0x40" + - kind: apu_ram_u8 + address: "0x0022" + expected: "0x2C" + - kind: apu_ram_u8 + address: "0x0023" + expected: "0x12" + - kind: apu_ram_u8 + address: "0x0024" + expected: "0x34" + - id: arguments-after-jsr-300k-screen-state + description: > + The undisbeliever 65816 arguments-after-JSR example renders a deterministic text screen at 300000 steps after repeatedly reading fixed 16-bit and 24-bit arguments following JSR/JSL calls. + + rom: snes-test-roms/bin/65816-examples/arguments-after-jsr.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x5EE4948C7C61C2A5" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: textbuffer-hello-world-300k-screen-state + description: > + The undisbeliever TextBuffer hello-world example renders a deterministic frame counter and greeting at 300000 steps, covering LoROM bank-81 resource reads together with NMI-driven TextBuffer VRAM updates. + + rom: snes-test-roms/bin/examples/textbuffer-hello-world.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x0519133F376900A8" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vram-writes-without-dma-final-state + description: > + The undisbeliever VRAM write example populates CGRAM color 1 and writes the expected second 2bpp tile into VRAM. + + rom: snes-test-roms/bin/examples/vram-writes-without-dma.sfc + max_steps: 300000 + check_interval_steps: 256 + expected_screen_hash: "0x164C473087C35D5D" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x2012" + expected: "0x42" + - kind: vram_u8 + address: "0x2016" + expected: "0x7E" + - kind: vram_u8 + address: "0x2018" + expected: "0x42" + - kind: vram_u8 + address: "0x201C" + expected: "0x42" + - id: hdma-to-cgram-final-state + description: > + The undisbeliever HDMA example drives CGRAM color 1 to the final gradient entry produced by the direct HDMA tables. + + rom: snes-test-roms/bin/examples/hdma-to-cgram.sfc + max_steps: 500000 + check_interval_steps: 256 + expected_screen_hash: "0x573DA5CCE4D37653" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x0400" + - id: hdma-repeat-entry-300k-screen-state + description: > + The undisbeliever HDMA repeat-entry example uses HDMA to update BG1HOFS for each scanline, producing a horizontal scroll gradient. + + rom: snes-test-roms/bin/examples/hdma-repeat-entry.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xA70C4BB46FFD192F" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-double-buffered-parallax-300k-screen-state + description: > + The undisbeliever double-buffered HDMA parallax example updates BG1HOFS through alternating direct HDMA tables. + + rom: snes-test-roms/bin/examples/hdma-double-buffered-parallax.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xDC8BB6AB64B78DB4" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-double-buffered-indirect-shear-300k-screen-state + description: > + The undisbeliever double-buffered indirect HDMA shear example updates BG1HOFS through indirect scanline arrays. + + rom: >- + snes-test-roms/bin/examples/hdma-double-buffered-indirect-shear.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x15E6EE7BD6A90B95" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-160scanline-entry-300k-screen-state + description: > + The undisbeliever 160-scanline HDMA entry example renders a deterministic BG1 horizontal-offset step pattern at 300000 steps, covering split long non-repeat HDMA entries that target BG1HOFS. + + rom: snes-test-roms/bin/examples/hdma-160scanline-hdma-entry.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xCA867431445F45F8" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-indirect-mapping-300k-screen-state + description: > + The undisbeliever indirect HDMA mapping example renders a deterministic BG1 horizontal scroll gradient at 300000 steps, covering contiguous indirect BG1HOFS tables split across HDMA entries. + + rom: snes-test-roms/bin/examples/hdma-indirect-mapping.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xA54807DAE4E757BC" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-indirect-repeating-pattern-300k-screen-state + description: > + The undisbeliever indirect repeating-pattern HDMA example renders deterministic repeated BG1 horizontal scroll waves at 300000 steps, covering repeated indirect table pointers. + + rom: >- + snes-test-roms/bin/examples/hdma-indirect-repeating-pattern.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x741CCA01312348AC" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-2bpp-remapping-final-state + description: > + The undisbeliever VMAIN 2bpp remapping ROM renders the deterministic radial test image at 8500000 steps after writing its remapped tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-with-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x9C85794034B6E29D" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x0000" + expected: "0x81" + - kind: vram_u8 + address: "0x0002" + expected: "0x40" + - kind: vram_u8 + address: "0x0006" + expected: "0x18" + - kind: vram_u8 + address: "0x0010" + expected: "0x01" + - kind: vram_u8 + address: "0x0012" + expected: "0x80" + - kind: vram_u8 + address: "0x001C" + expected: "0x06" + - kind: vram_u8 + address: "0x001E" + expected: "0x81" + - id: vmain-1bpp-no-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 1bpp no-remapping ROM renders the deterministic radial test image at 8500000 steps after writing bitplane 0 through VMDATAL and clearing bitplane 1 through fixed VMDATAH DMA. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-no-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x71C78EC78270F557" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-1bpp-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 1bpp remapping ROM renders the deterministic radial test image at 8500000 steps after writing bitplane 0 through remapped VMDATAL and clearing bitplane 1 through fixed VMDATAH DMA. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-1bpp-with-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x71C78EC78270F557" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-2bpp-no-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 2bpp no-remapping ROM renders the deterministic radial test image at 8500000 steps after writing its linear 2bpp tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-no-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x9C85794034B6E29D" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-2bpp-split-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 2bpp split-bitplane remapping ROM renders the deterministic radial test image at 8500000 steps after writing separate bitplanes through remapped VMDATA DMA transfers. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-2bpp-split-with-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x9C85794034B6E29D" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-4bpp-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 4bpp remapping ROM renders the deterministic radial test image at 8500000 steps after writing its remapped tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x97DCE715B9555BA2" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - id: vmain-4bpp-no-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 4bpp no-remapping ROM renders the deterministic radial test image at 8500000 steps after writing its linear tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x97DCE715B9555BA2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-4bpp-no-remapping-word-8500k-screen-state + description: > + The undisbeliever VMAIN 4bpp no-remapping word-write ROM renders the deterministic radial test image at 8500000 steps after writing its linear tile buffer through paired $2118/$2119 writes. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-no-remapping-word.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x97DCE715B9555BA2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-4bpp-with-remapping-word-8500k-screen-state + description: > + The undisbeliever VMAIN 4bpp remapping word-write ROM renders the deterministic radial test image at 8500000 steps after writing its remapped tile buffer through paired $2118/$2119 writes. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-4bpp-with-remapping-word.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x97DCE715B9555BA2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-8bpp-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 8bpp remapping ROM renders the deterministic radial test image at 8500000 steps after writing its remapped tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-with-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0xFDED1B889D95799F" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - id: vmain-8bpp-no-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN 8bpp no-remapping ROM renders the deterministic radial test image at 8500000 steps after writing its linear tile buffer through $2118/$2119. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-8bpp-no-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0xFDED1B889D95799F" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x03" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-no-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN Mode 7 no-remapping ROM renders the deterministic diagonal line image at 8500000 steps after writing tilemap bytes through VMDATAL and tile pixels through VMDATAH. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-no-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x2DEE4A88526CD0C2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-8bit-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN Mode 7 8-bit remapping ROM renders the same deterministic diagonal image through remapped VMDATAH row uploads. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-8bit-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x2DEE4A88526CD0C2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-10bit-remapping-8500k-screen-state + description: > + The undisbeliever VMAIN Mode 7 10-bit remapping ROM renders the same deterministic diagonal image through remapped VMDATAH column uploads. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-with-10bit-remapping.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x2DEE4A88526CD0C2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-tilemap-8500k-screen-state + description: > + The undisbeliever VMAIN Mode 7 tilemap-image ROM renders a deterministic radial image by using tilemap bytes as chunky pixel data. + + rom: >- + snes-test-roms/bin/vmain-address-remapping/vmain-mode7-image-tilemap.sfc + max_steps: 8500000 + check_interval_steps: 8500000 + expected_screen_hash: "0x2DEE4A88526CD0C2" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: inidisp-forgot-to-force-blank-final-state + description: > + The undisbeliever INIDISP force-blank hardware test reaches its steady IRQ-driven loop after loading VRAM, OAM, and CGRAM assets. + + rom: snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank.sfc + max_steps: 69632 + check_interval_steps: 69632 + expected_screen_hash: "0x27B04E15F9FEB305" + assertions: + - kind: cgram_u16 + address: "0x0002" + expected: "0x0C87" + - kind: vram_u8 + address: "0x0000" + expected: "0x18" + - kind: vram_u8 + address: "0x0004" + expected: "0x1A" + - kind: vram_u8 + address: "0x2003" + expected: "0x00" + - kind: vram_u8 + address: "0x2005" + expected: "0x00" + - kind: vram_u8 + address: "0x200F" + expected: "0x00" + - kind: oam_u16 + address: "0x0000" + expected: "0x5040" + - kind: oam_u16 + address: "0x0004" + expected: "0x5060" + - kind: oam_u16 + address: "0x0200" + expected: "0xAAAA" + - kind: oam_u16 + address: "0x0202" + expected: "0x5555" + - id: inidisp-forgot-to-force-blank-2-final-state + description: > + The undisbeliever follow-up force-blank hardware test reaches its steady HV-IRQ loop after re-uploading PPU data during active display. + + rom: snes-test-roms/bin/hardware-tests/inidisp_forgot_to_force_blank_2.sfc + max_steps: 5000 + check_interval_steps: 5000 + expected_screen_hash: "0x2A3E0C7153EFF887" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: cgram_u16 + address: "0x0002" + expected: "0x0C87" + - kind: vram_u8 + address: "0x2003" + expected: "0x7F" + - kind: vram_u8 + address: "0x2005" + expected: "0x7F" + - kind: vram_u8 + address: "0x200F" + expected: "0x7F" + - kind: oam_u16 + address: "0x0000" + expected: "0x5040" + - kind: oam_u16 + address: "0x0004" + expected: "0x5060" + - kind: oam_u16 + address: "0x0200" + expected: "0xAAAA" + - kind: oam_u16 + address: "0x0202" + expected: "0x5555" + - id: inidisp-enable-display-mid-frame-final-state + description: > + The undisbeliever mid-frame display-enable hardware test reaches its steady loop with the configured IRQ position and loaded PPU resources. + + rom: snes-test-roms/bin/hardware-tests/inidisp_enable_display_mid_frame.sfc + max_steps: 114688 + check_interval_steps: 114688 + expected_screen_hash: "0x256BB929C92455FA" + assertions: + - kind: bus_u8 + address: "0x004200" + expected: "0xB1" + - kind: bus_u16 + address: "0x004207" + expected: "0x000F" + - kind: bus_u16 + address: "0x004209" + expected: "0x0059" + - kind: cgram_u16 + address: "0x0002" + expected: "0x0C87" + - kind: vram_u8 + address: "0x2003" + expected: "0x7F" + - kind: vram_u8 + address: "0x2005" + expected: "0x7F" + - kind: vram_u8 + address: "0x200F" + expected: "0x7F" + - kind: oam_u16 + address: "0x0000" + expected: "0x5040" + - kind: oam_u16 + address: "0x0004" + expected: "0x5060" + - kind: oam_u16 + address: "0x0200" + expected: "0xAAAA" + - kind: oam_u16 + address: "0x0202" + expected: "0x5555" + - id: inidisp-extend-vblank-300k-screen-state + description: > + The undisbeliever extend-VBlank demo reaches a deterministic paced-timing screen state at 7626752 steps with the current IRQ-driven forced-blank flow, and should keep matching that rendered frame hash when screenshots are captured from the final checked state. + + rom: snes-test-roms/bin/effects/inidisp_extend_vblank.sfc + max_steps: 7626752 + check_interval_steps: 7626752 + expected_screen_hash: "0xDD3BE684D8AE384B" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x09" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x11" + - kind: bus_u8 + address: "0x004200" + expected: "0x31" + - kind: bus_u16 + address: "0x004207" + expected: "0x00F0" + - kind: bus_u16 + address: "0x004209" + expected: "0x00D6" + - id: inidisp-fadein-fadeout-300k-screen-state + description: > + The undisbeliever INIDISP fade demo renders a deterministic low-brightness map image at 300000 steps, covering VBlank brightness updates while the screen remains enabled. + + rom: snes-test-roms/bin/effects/inidisp_fadein_fadeout.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x6863F6EDAE5267ED" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x01" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: inidisp-fadein-fadeout-1000k-screen-state + description: > + The undisbeliever INIDISP fade demo renders a deterministic higher brightness map image at 1000000 steps, covering the software fade-in loop. + + rom: snes-test-roms/bin/effects/inidisp_fadein_fadeout.sfc + max_steps: 1000000 + check_interval_steps: 1000000 + expected_screen_hash: "0xD662D016385E123F" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x03" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: hdma-textbox-wipe-300k-screen-state + description: > + The undisbeliever HDMA textbox wipe effect uses HDMA to switch main-screen layers between BG1/BG2/OBJ and BG3 scanline regions. + + rom: snes-test-roms/bin/effects/hdma-textbox-wipe.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x12CDB162BB7BE9F1" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - id: repeating-hdma-pattern-300k-screen-state + description: > + The undisbeliever repeating HDMA pattern effect renders deterministic BG3 cloud waves at 300000 steps, covering double-buffered indirect HDMA data reused across the visible display. + + rom: snes-test-roms/bin/effects/repeating_hdma_pattern.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x98F06010DC2F2DA5" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x01" + - kind: bus_u8 + address: "0x00212C" + expected: "0x04" + - id: window-shapes-single-300k-screen-state + description: > + The undisbeliever single window shapes effect renders a deterministic color-window triangle at 300000 steps using HDMA-updated WH0/WH1 and fixed-color math on the backdrop. + + rom: snes-test-roms/bin/effects/window-shapes-single.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xCD6FBF100DF02484" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002125" + expected: "0x20" + - kind: bus_u8 + address: "0x002130" + expected: "0x90" + - kind: bus_u8 + address: "0x002131" + expected: "0x20" + - id: window-precalculated-single-300k-screen-state + description: > + The undisbeliever precalculated single-window effect renders a deterministic color-window exclamation mark at 300000 steps using a double-buffered HDMA table targeting WH0/WH1. + + rom: snes-test-roms/bin/effects/window-precalculated-single.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xF6742E5F14A62CF4" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002125" + expected: "0x20" + - kind: bus_u8 + address: "0x002130" + expected: "0x70" + - kind: bus_u8 + address: "0x002131" + expected: "0x00" + - id: window-precalculated-symmetrical-300k-screen-state + description: > + The undisbeliever precalculated symmetrical single-window effect renders deterministic color-window shapes at 300000 steps using a generated HDMA table targeting WH0/WH1. + + rom: snes-test-roms/bin/effects/window-precalculated-symmetrical.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xBA0B0EE07528FDC6" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002125" + expected: "0x20" + - kind: bus_u8 + address: "0x002130" + expected: "0x70" + - kind: bus_u8 + address: "0x002131" + expected: "0x00" + - id: window-mask-logic-300k-screen-state + description: > + The undisbeliever window mask logic effect renders deterministic overlapping color-window regions behind BG1 text at 300000 steps, covering WOBJSEL/WOBJLOG backdrop color math while main-screen layers remain enabled. + + rom: snes-test-roms/bin/effects/window-mask-logic.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x2917479C919BB726" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002125" + expected: "0xA0" + - kind: bus_u8 + address: "0x00212B" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - kind: bus_u8 + address: "0x002130" + expected: "0x90" + - kind: bus_u8 + address: "0x002131" + expected: "0x20" + - id: vmain-1bpp-tiles-0-300k-screen-state + description: > + The undisbeliever VMAIN 1bpp tiles-0 demo renders deterministic text at 300000 steps after converting 1bpp tile data into transparent 2bpp tiles with VMDATAL and VMDATAH DMA transfers. + + rom: snes-test-roms/bin/effects/vmain-1bpp-tiles-0.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x9E1FB4791831EA80" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-1bpp-tiles-1-300k-screen-state + description: > + The undisbeliever VMAIN 1bpp tiles-1 demo renders deterministic text at 300000 steps after converting 1bpp tile data into opaque 2bpp tiles with fixed-source VMDATAH DMA. + + rom: snes-test-roms/bin/effects/vmain-1bpp-tiles-1.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x7C8B0EE8F1650C4F" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-horizontal-scrolling-5000k-screen-state + description: > + The undisbeliever horizontal scrolling VMAIN demo renders a deterministic BG1 tilemap state at 5000000 steps after repeatedly uploading columns with VMAIN increment-by-32 DMA transfers. + + rom: snes-test-roms/bin/effects/vmain-horizontal-scrolling.sfc + max_steps: 5000000 + check_interval_steps: 5000000 + expected_screen_hash: "0xCBE9FCCE3E06CB19" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-vertical-scrolling-5000k-screen-state + description: > + The undisbeliever vertical scrolling VMAIN demo renders the deterministic BG1 tilemap state at 5000000 steps after repeatedly uploading split rows into a 64x32 tilemap. + + rom: snes-test-roms/bin/effects/vmain-vertical-scrolling.sfc + max_steps: 5000000 + check_interval_steps: 5000000 + expected_screen_hash: "0xBF3ECAC5F3DB8EB4" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-vertical-scrolling-2-rows-5000k-screen-state + description: > + The undisbeliever vertical scrolling two-row VMAIN demo renders the deterministic BG1 tilemap state at 5000000 steps after transferring two split tilemap rows through paired DMA channels. + + rom: snes-test-roms/bin/effects/vmain-vertical-scrolling-2-rows.sfc + max_steps: 5000000 + check_interval_steps: 5000000 + expected_screen_hash: "0x16AB6302EF753358" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-tilemap-columns-5000k-screen-state + description: > + The undisbeliever Mode 7 tilemap-columns VMAIN demo renders a deterministic set of vertical bars at 5000000 steps after VBlank DMA transfers whole Mode 7 tilemap columns with increment-by-128. + + rom: snes-test-roms/bin/effects/vmain-mode7-tilemap-columns.sfc + max_steps: 5000000 + check_interval_steps: 5000000 + expected_screen_hash: "0xB03B6DA399D20694" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: vmain-mode7-tilemap-rows-5000k-screen-state + description: > + The undisbeliever Mode 7 tilemap-rows VMAIN demo renders a deterministic set of horizontal bars at 5000000 steps after VBlank DMA transfers whole Mode 7 tilemap rows with increment-by-1. + + rom: snes-test-roms/bin/effects/vmain-mode7-tilemap-rows.sfc + max_steps: 5000000 + check_interval_steps: 5000000 + expected_screen_hash: "0x742C899411F142F9" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x07" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: inidisp-brightness-0-screen-state + description: > + The undisbeliever INIDISP brightness-0 hardware test reaches a stable black-screen wait state with brightness forced to zero, and should keep matching that rendered frame hash when captured at 30000 steps. + + rom: snes-test-roms/bin/hardware-tests/inidisp_brightness_0.sfc + max_steps: 30000 + check_interval_steps: 30000 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x00" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - kind: bus_u8 + address: "0x004200" + expected: "0x00" + - kind: cgram_u16 + address: "0x0002" + expected: "0x0000" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: hirom-gsu-test-300k-screen-state + description: > + The public-domain HiROM+GSU-2 integration test reaches a deterministic rendered report at 300000 steps while exercising Super FX VCR reads, Game Pak RAM access, and R15-triggered GSU execution used by its pixel and demo programs. + + rom: snes-coprocessor-tests/hirom-gsu-test/build/HiRomGsuTest.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xFC95F36A460D3625" + assertions: + - kind: wram_u8 + address: "0x0003" + expected: "0x01" + - kind: wram_u8 + address: "0x0004" + expected: "0x01" + - kind: wram_u8 + address: "0x0005" + expected: "0x04" + - kind: wram_u8 + address: "0x0007" + expected: "0x3E" + - kind: wram_u8 + address: "0x000A" + expected: "0x01" + - kind: bus_u8 + address: "0x00303B" + expected: "0x04" + - kind: bus_u8 + address: "0x003039" + expected: "0x01" + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002000" + expected: "0x0A" + - kind: bus_u8 + address: "0x002002" + expected: "0x53" + - kind: bus_u8 + address: "0x002003" + expected: "0x2D" + - kind: bus_u8 + address: "0x002004" + expected: "0x4D" + - kind: bus_u8 + address: "0x002005" + expected: "0x53" + - kind: bus_u8 + address: "0x002006" + expected: "0x55" + - kind: bus_u8 + address: "0x002007" + expected: "0x31" + - kind: vram_u16 + address: "0x8000" + expected: "0x66AA" + - kind: vram_u16 + address: "0x8002" + expected: "0xCC55" + - kind: vram_u16 + address: "0x8004" + expected: "0x99AA" + - kind: vram_u16 + address: "0x8006" + expected: "0x3355" + - kind: vram_u16 + address: "0x801E" + expected: "0xFF0F" + - kind: oam_u16 + address: "0x0000" + expected: "0x9C78" + - kind: oam_u16 + address: "0x0002" + expected: "0x3000" + - id: sa1-bwram-smoke-final-state + description: > + The self-authored SA-1 BWRAM smoke ROM declares an SA-1 cartridge header and verifies host-visible BWRAM protection/write-enable behavior plus BMAPS page selection from S-CPU code. + + rom: snes-coprocessor-tests/sa1-bwram-smoke/build/Sa1BwramSmoke.sfc + max_steps: 1200 + check_interval_steps: 1200 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0x00" + - kind: wram_u8 + address: "0x0001" + expected: "0x5A" + - kind: wram_u8 + address: "0x0002" + expected: "0xA5" + - kind: wram_u8 + address: "0x0003" + expected: "0x5A" + - kind: bus_u8 + address: "0x002224" + expected: "0x00" + - kind: bus_u8 + address: "0x002226" + expected: "0x80" + - id: cx4-smoke-final-state + description: > + The self-authored CX4 smoke ROM declares a CX4 cartridge header and verifies host-visible CX4 multiply, identification, and busy-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/cx4-smoke/build/Cx4Smoke.sfc + max_steps: 1200 + check_interval_steps: 1200 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0x8C" + - kind: wram_u8 + address: "0x0001" + expected: "0x04" + - kind: wram_u8 + address: "0x0002" + expected: "0x00" + - kind: wram_u8 + address: "0x0003" + expected: "0x36" + - kind: wram_u8 + address: "0x0004" + expected: "0x43" + - kind: wram_u8 + address: "0x0005" + expected: "0x05" + - kind: wram_u8 + address: "0x0006" + expected: "0x00" + - kind: bus_u8 + address: "0x007F5E" + expected: "0x00" + - id: dsp1-smoke-final-state + description: > + The self-authored DSP-1 smoke ROM declares a DSP-1 LoROM cartridge header and verifies host-visible DSP-1 multiply, ROM-version, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1Smoke.sfc + max_steps: 1200 + check_interval_steps: 1200 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0x00" + - kind: wram_u8 + address: "0x0001" + expected: "0x20" + - kind: wram_u8 + address: "0x0002" + expected: "0x00" + - kind: wram_u8 + address: "0x0003" + expected: "0x01" + - kind: wram_u8 + address: "0x0004" + expected: "0x84" + - kind: bus_u8 + address: "0x20C000" + expected: "0x84" + - id: dsp1a-smoke-final-state + description: > + The self-authored DSP-1A-compatible smoke ROM declares a DSP-1A-style LoROM cartridge header and verifies the shared DSP-1 multiply, ROM-version, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1aSmoke.sfc + max_steps: 1200 + check_interval_steps: 1200 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0x00" + - kind: wram_u8 + address: "0x0001" + expected: "0x20" + - kind: wram_u8 + address: "0x0002" + expected: "0x00" + - kind: wram_u8 + address: "0x0003" + expected: "0x01" + - kind: wram_u8 + address: "0x0004" + expected: "0x84" + - kind: bus_u8 + address: "0x20C000" + expected: "0x84" + - id: dsp1b-smoke-final-state + description: > + The self-authored DSP-1B smoke ROM declares a DSP-1B HiROM cartridge header and verifies host-visible DSP-1B multiply, ROM-version, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1bSmoke.sfc + max_steps: 1200 + check_interval_steps: 1200 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u8 + address: "0x0000" + expected: "0x00" + - kind: wram_u8 + address: "0x0001" + expected: "0x20" + - kind: wram_u8 + address: "0x0002" + expected: "0x01" + - kind: wram_u8 + address: "0x0003" + expected: "0x01" + - kind: wram_u8 + address: "0x0004" + expected: "0x84" + - kind: bus_u8 + address: "0x007000" + expected: "0x84" + - id: dsp1-geometry-smoke-final-state + description: > + The self-authored DSP-1 geometry smoke ROM declares a DSP-1 LoROM cartridge header and verifies host-visible trigonometric, 2D/3D rotation, vector-length, radius, inverse, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1GeometrySmoke.sfc + max_steps: 3000 + check_interval_steps: 3000 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u16 + address: "0x0010" + expected: "0x0000" + - kind: wram_u16 + address: "0x0012" + expected: "0x4000" + - kind: wram_u16 + address: "0x0014" + expected: "0x0123" + - kind: wram_u16 + address: "0x0016" + expected: "0xFEDC" + - kind: wram_u16 + address: "0x0018" + expected: "0x0003" + - kind: wram_u16 + address: "0x001A" + expected: "0xFFFC" + - kind: wram_u16 + address: "0x001C" + expected: "0x000C" + - kind: wram_u16 + address: "0x001E" + expected: "0x000D" + - kind: wram_u16 + address: "0x0020" + expected: "0x00A9" + - kind: wram_u16 + address: "0x0022" + expected: "0x0000" + - kind: wram_u16 + address: "0x0024" + expected: "0x7FFF" + - kind: wram_u16 + address: "0x0026" + expected: "0x0001" + - kind: wram_u8 + address: "0x0028" + expected: "0x84" + - kind: bus_u8 + address: "0x20C000" + expected: "0x84" + - id: dsp1a-geometry-smoke-final-state + description: > + The self-authored DSP-1A-compatible geometry smoke ROM declares a DSP-1A-style LoROM cartridge header and verifies the shared DSP-1 trigonometric, 2D/3D rotation, vector-length, radius, inverse, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1aGeometrySmoke.sfc + max_steps: 3000 + check_interval_steps: 3000 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u16 + address: "0x0010" + expected: "0x0000" + - kind: wram_u16 + address: "0x0012" + expected: "0x4000" + - kind: wram_u16 + address: "0x0014" + expected: "0x0123" + - kind: wram_u16 + address: "0x0016" + expected: "0xFEDC" + - kind: wram_u16 + address: "0x0018" + expected: "0x0003" + - kind: wram_u16 + address: "0x001A" + expected: "0xFFFC" + - kind: wram_u16 + address: "0x001C" + expected: "0x000C" + - kind: wram_u16 + address: "0x001E" + expected: "0x000D" + - kind: wram_u16 + address: "0x0020" + expected: "0x00A9" + - kind: wram_u16 + address: "0x0022" + expected: "0x0000" + - kind: wram_u16 + address: "0x0024" + expected: "0x7FFF" + - kind: wram_u16 + address: "0x0026" + expected: "0x0001" + - kind: wram_u8 + address: "0x0028" + expected: "0x84" + - kind: bus_u8 + address: "0x20C000" + expected: "0x84" + - id: dsp1b-geometry-smoke-final-state + description: > + The self-authored DSP-1B geometry smoke ROM declares a DSP-1B HiROM cartridge header and verifies host-visible DSP-1B trigonometric, 2D/3D rotation, vector-length, radius, inverse, and ready-status behavior from S-CPU code. + + rom: snes-coprocessor-tests/dsp1-smoke/build/Dsp1bGeometrySmoke.sfc + max_steps: 3000 + check_interval_steps: 3000 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: wram_u16 + address: "0x0010" + expected: "0x0000" + - kind: wram_u16 + address: "0x0012" + expected: "0x4000" + - kind: wram_u16 + address: "0x0014" + expected: "0x0123" + - kind: wram_u16 + address: "0x0016" + expected: "0xFEDC" + - kind: wram_u16 + address: "0x0018" + expected: "0x0003" + - kind: wram_u16 + address: "0x001A" + expected: "0xFFFC" + - kind: wram_u16 + address: "0x001C" + expected: "0x000C" + - kind: wram_u16 + address: "0x001E" + expected: "0x000D" + - kind: wram_u16 + address: "0x0020" + expected: "0x00A9" + - kind: wram_u16 + address: "0x0022" + expected: "0x0000" + - kind: wram_u16 + address: "0x0024" + expected: "0x7FFF" + - kind: wram_u16 + address: "0x0026" + expected: "0x0001" + - kind: wram_u8 + address: "0x0028" + expected: "0x84" + - kind: bus_u8 + address: "0x007000" + expected: "0x84" + - id: inidisp-brightness-delay-100k-screen-state + description: > + The undisbeliever INIDISP brightness-delay hardware test reaches a deterministic paced-timing screen state at 16384 steps while the delayed brightness writes are still holding the display at zero brightness. + + rom: snes-test-roms/bin/hardware-tests/inidisp_brightness_delay.sfc + max_steps: 16384 + check_interval_steps: 16384 + expected_screen_hash: "0xBD1C16C241905E87" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x00" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x00" + - kind: bus_u8 + address: "0x004200" + expected: "0x90" + - kind: cgram_u16 + address: "0x0002" + expected: "0xFFFF" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: vram-mid-scanline-100k-white-screen-state + description: > + The undisbeliever mid-scanline VRAM write hardware test keeps its BG1 tile data intact and renders a deterministic white screen at 100000 steps while active-display writes through $2118/$2119 stay ignored. + + rom: snes-test-roms/bin/hardware-tests/vram-mid-scanline-test.sfc + max_steps: 100000 + check_interval_steps: 100000 + expected_screen_hash: "0xA7140ABD926FF413" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x002115" + expected: "0x80" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - kind: bus_u8 + address: "0x004200" + expected: "0x00" + - kind: cgram_u16 + address: "0x0006" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x2003" + expected: "0xFF" + - kind: vram_u8 + address: "0x2005" + expected: "0xFF" + - kind: vram_u8 + address: "0x200F" + expected: "0xFF" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: hdmaen-latch-test-300k-screen-state + description: > + The undisbeliever HDMAEN latch hardware test renders the alternating backdrop stripe pattern at 300000 steps once HIRQ, WAI, and mid-frame HDMA activation are paced against the current CPU timing model. + + rom: snes-test-roms/bin/hardware-tests/hdmaen_latch_test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xFE59F82F1E93CFA4" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x00" + - id: hdmaen-latch-test-2-300k-screen-state + description: > + The undisbeliever HDMAEN latch timing sweep test reaches the same alternating backdrop stripe pattern at 300000 steps while keeping HIRQ enabled for the next per-delay sweep. + + rom: snes-test-roms/bin/hardware-tests/hdmaen_latch_test_2.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xFE59F82F1E93CFA4" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x10" + - id: wrmpyb-in-flight-300k-screen-state + description: > + The undisbeliever WRMPYB in-flight hardware test renders the modelled 5A22 multiply timing table at 300000 steps, including the hardware-observed zero result when the second WRMPYB write lands seven CPU cycles after the previous multiply start. + + rom: snes-test-roms/bin/hardware-tests/wrmpyb-in-flight.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x3DE75D479A103EF6" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: reset-position-300k-screen-state + description: > + The undisbeliever reset-position hardware test reaches a deterministic text output at 300000 steps, covering software counter latch, OPHCT/OPVCT byte order, and coarse HVBJOY H/V timing from reset. + + rom: snes-test-roms/bin/hardware-tests/reset-position-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x3A1FF072F7F6F82C" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: hdma-timing-demonstration-300k-screen-state + description: > + The undisbeliever HDMA timing demonstration renders a deterministic backdrop gradient at 300000 steps, covering paired HDMA channels that update CGADD and CGDATA during active display. + + rom: snes-test-roms/bin/hardware-tests/hdma-timing-demonstration.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x618B2CAF9D84F5AD" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: object-dropout-300k-screen-state + description: > + The undisbeliever object dropout hardware test renders the deterministic OBJ overflow pattern at 300000 steps, covering the per-scanline sprite and tile-sliver limits including offscreen sprites at X=-256. + + rom: snes-test-roms/bin/hardware-tests/object-dropout-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x3347C7633FF81D85" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: joypad-bounce-200k-screen-state + description: > + The undisbeliever joypad bounce hardware test renders deterministic Mode 0 BG1-BG4 line indicators at 200000 steps while HDMA updates each BG vertical scroll register. + + rom: snes-test-roms/bin/hardware-tests/joypad_bounce_test.sfc + max_steps: 200000 + check_interval_steps: 200000 + expected_screen_hash: "0x5B99D0174EAB1953" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x1F" + - id: joypad-rapid-read-no-input-final-state + description: > + The undisbeliever joypad rapid read hardware test reaches a stable no-input display state once JOYOUT and JOYSER reads are implemented for a standard controller. + + rom: snes-test-roms/bin/hardware-tests/joypad_rapid_read_test.sfc + max_steps: 53248 + check_interval_steps: 53248 + expected_screen_hash: "0x00B9B6854716FB49" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: cgram_u16 + address: "0x0002" + expected: "0x0000" + - kind: vram_u8 + address: "0x0002" + expected: "0x01" + - kind: vram_u8 + address: "0x0007" + expected: "0x08" + - kind: vram_u8 + address: "0x0015" + expected: "0x1C" + - kind: vram_u8 + address: "0x2001" + expected: "0xC0" + - kind: vram_u8 + address: "0x2011" + expected: "0x0C" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: clear-autojoy-after-active-no-input-final-state + description: > + The undisbeliever clear-autojoy-after-autojoy-active hardware test reaches a stable no-input display state once autojoy completion leaves manual JOYSER reads exhausted until relatched. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-after-autojoy-active.sfc + max_steps: 16384 + check_interval_steps: 16384 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x00" + - kind: bus_u16 + address: "0x004218" + expected: "0x0000" + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x0001" + expected: "0x20" + - kind: vram_u8 + address: "0x001F" + expected: "0x20" + - kind: vram_u8 + address: "0x2010" + expected: "0x38" + - kind: vram_u8 + address: "0x2012" + expected: "0x6C" + - kind: vram_u8 + address: "0x2014" + expected: "0xC6" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: clear-autojoy-during-autojoy-no-input-final-state + description: > + The undisbeliever clear-autojoy-during-autojoy hardware test reaches a stable no-input display state once clearing autojoy during the active window does not corrupt the final no-input JOY state. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-during-autojoy.sfc + max_steps: 16384 + check_interval_steps: 16384 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x00" + - kind: bus_u16 + address: "0x004218" + expected: "0x0000" + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x0001" + expected: "0x20" + - kind: vram_u8 + address: "0x001F" + expected: "0x20" + - kind: vram_u8 + address: "0x2010" + expected: "0x38" + - kind: vram_u8 + address: "0x2012" + expected: "0x6C" + - kind: vram_u8 + address: "0x2014" + expected: "0xC6" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: joyser0-read-during-autojoy-no-input-final-state + description: > + The undisbeliever JOYSER0 read during autojoy hardware test reaches a stable no-input display state once JOYSER reads share state with the active autojoy window. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/joyser0-read-during-autojoy.sfc + max_steps: 49152 + check_interval_steps: 49152 + expected_screen_hash: "0xC5F8C8BED7A97DF3" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x31" + - kind: bus_u16 + address: "0x004207" + expected: "0x00C8" + - kind: bus_u16 + address: "0x004209" + expected: "0x00E0" + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x0001" + expected: "0x20" + - kind: vram_u8 + address: "0x001F" + expected: "0x20" + - kind: vram_u8 + address: "0x2010" + expected: "0x38" + - kind: vram_u8 + address: "0x2012" + expected: "0x6C" + - kind: vram_u8 + address: "0x2014" + expected: "0xC6" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: auto-joy-timing-300k-screen-state + description: > + The undisbeliever HVBJOY autojoy timing hardware test renders deterministic OPHCT start/end timing bounds at 300000 steps, covering the autojoy active flag's coarse start and clear windows. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/auto-joy-timing-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xA88B5A2C44D7FD34" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: clear-autojoy-timing-300k-screen-state + description: > + The undisbeliever clear-autojoy-timing hardware test renders deterministic HVBJOY poll counts at 300000 steps, covering active-window behavior when NMITIMEN clears autojoy mid-read. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-timing-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x1C509DCEC3A8A475" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: blip-autojoy-test-300k-screen-state + description: > + The undisbeliever AUTOJOY blip hardware test renders a deterministic no-input IRQ timing table at 300000 steps, covering rapid NMITIMEN autojoy disable/re-enable during active autojoy. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x1F6EE8AC51D1A874" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: blip-autojoy-test-automatic-300k-screen-state + description: > + The undisbeliever automatic AUTOJOY blip hardware test renders a deterministic no-input HVBJOY.0 count screen at 300000 steps, covering automatic rapid autojoy disable/re-enable loops. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-test-automatic.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x4C53A210FB34C019" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: blip-autojoy-timing-test-300k-screen-state + description: > + The undisbeliever blip AUTOJOY timing hardware test renders deterministic HVBJOY count bounds at 300000 steps, covering short NMITIMEN autojoy-off windows during the first autojoy cycle. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-timing-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0x33C79963D63E7B29" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: blip-autojoy-latches-joypad-300k-screen-state + description: > + The undisbeliever blipping AUTOJOY enable latches-joypad hardware test renders a deterministic no-input serial-read table at 300000 steps, covering rapid autojoy disable/re-enable around manual JOYSER0 reads. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/blip-autojoy-latches-joypad-test.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xFEAFDE8611AD723D" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: clear-autojoy-1st-vb-sl-300k-screen-state + description: > + The undisbeliever clear-AUTOJOY-on-first-VBlank-scanline hardware test renders a deterministic no-input IRQ timing table at 300000 steps, covering early VBlank autojoy disable behavior. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/clear-autojoy-1st-vb-sl.sfc + max_steps: 300000 + check_interval_steps: 300000 + expected_screen_hash: "0xFA8ECF09843DDE0D" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x002105" + expected: "0x00" + - kind: bus_u8 + address: "0x00212C" + expected: "0x01" + - id: joypad-latch-clear-during-autojoy-no-input-final-state + description: > + The undisbeliever joypad-latch-clear-during-autojoy hardware test reaches a deterministic no-input display state once manual JOYSER latch clearing during active autojoy does not corrupt the final JOY state. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-clear-during-autojoy.sfc + max_steps: 110592 + check_interval_steps: 110592 + expected_screen_hash: "0x99E592A55875DB6A" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: joypad-latch-set-during-autojoy-no-input-final-state + description: > + The undisbeliever joypad-latch-set-during-autojoy hardware test reaches a deterministic no-input display state once manual JOYSER latch setting during active autojoy is shared with the serial controller state. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/joypad-latch-set-during-autojoy.sfc + max_steps: 110592 + check_interval_steps: 110592 + expected_screen_hash: "0x16D2DE27375F62FE" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: enable-autojoy-late-no-input-final-state + description: > + The undisbeliever enable-autojoy-late hardware test reaches a deterministic no-input display state once IRQ-timed same-frame autojoy arming is covered across the tested H/V positions. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test.sfc + max_steps: 110592 + check_interval_steps: 110592 + expected_screen_hash: "0x08080EBE1D43AF88" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - id: enable-autojoy-late-2-no-input-final-state + description: > + The undisbeliever enable-autojoy-late-test-2 hardware test reaches a stable no-input display state once same-frame autojoy arming is supported in the coarse timing model. + + rom: >- + snes-test-roms/bin/hardware-tests/auto-joypad/enable-autojoy-late-test-2.sfc + max_steps: 110592 + check_interval_steps: 110592 + expected_screen_hash: "0xC62139DA6C909817" + assertions: + - kind: bus_u8 + address: "0x002100" + expected: "0x0F" + - kind: bus_u8 + address: "0x004200" + expected: "0x01" + - kind: cgram_u16 + address: "0x0002" + expected: "0x7FFF" + - kind: vram_u8 + address: "0x0001" + expected: "0x20" + - kind: vram_u8 + address: "0x001F" + expected: "0x20" + - kind: vram_u8 + address: "0x2010" + expected: "0x38" + - kind: vram_u8 + address: "0x2012" + expected: "0x6C" + - kind: vram_u8 + address: "0x2014" + expected: "0xC6" + - kind: oam_u16 + address: "0x0000" + expected: "0xF080" + - id: peter-lemon-snes-cpu-cmp + description: | + The self-authored CPU CMP test ROM verifies correct CMP instruction behavior across all addressing modes, including edge cases for negative results, zero results, and unsigned underflow. + rom: snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.sfc + max_steps: 4764880 + check_interval_steps: 4764880 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/CMP/CPUCMP.png + expected_screen_hash: 0x9FA423204172007E + - id: peter-lemon-snes-cpu-adc + description: | + The self-authored CPU ADC test ROM verifies correct ADC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.sfc + max_steps: 3454538 + check_interval_steps: 3454538 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/ADC/CPUADC.png + expected_screen_hash: 0x4A6307060A412176 + - id: peter-lemon-snes-cpu-and + description: | + The self-authored CPU AND test ROM verifies correct AND instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.sfc + max_steps: 2799367 + check_interval_steps: 2799367 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/AND/CPUAND.png + expected_screen_hash: 0x1B76573A8CDE5B29 + - id: peter-lemon-snes-cpu-asl + description: | + The self-authored CPU ASL test ROM verifies correct ASL instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.sfc + max_steps: 3692782 + check_interval_steps: 3692782 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/ASL/CPUASL.png + expected_screen_hash: 0x270B715ED335207B + - id: peter-lemon-snes-cpu-bit + description: | + The self-authored CPU BIT test ROM verifies correct BIT instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.sfc + max_steps: 3692782 + check_interval_steps: 3692782 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/BIT/CPUBIT.png + expected_screen_hash: 0x291284D0A7AD833E + - id: peter-lemon-snes-cpu-bra + description: | + The self-authored CPU BRA test ROM verifies correct BRA instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.sfc + max_steps: 3692782 + check_interval_steps: 3692782 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/BRA/CPUBRA.png + expected_screen_hash: 0x643A00BDEFB4F30D + - id: peter-lemon-snes-cpu-dec + description: | + The self-authored CPU DEC test ROM verifies correct DEC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.sfc + max_steps: 1310342 + check_interval_steps: 1310342 + reference_png: snes/peter-lemon-snes/CPUTest/CPU/DEC/CPUDEC.png + - id: peter-lemon-snes-cpu-eor + description: | + The self-authored CPU EOR test ROM verifies correct EOR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.sfc + max_steps: 2322879 + check_interval_steps: 2322879 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/EOR/CPUEOR.png + expected_screen_hash: 0x9E3FA5C99C10BD68 + - id: peter-lemon-snes-cpu-inc + description: | + The self-authored CPU INC test ROM verifies correct INC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.sfc + max_steps: 1310342 + check_interval_steps: 1310342 + reference_png: snes/peter-lemon-snes/CPUTest/CPU/INC/CPUINC.png + - id: peter-lemon-snes-cpu-jmp + description: | + The self-authored CPU JMP test ROM verifies correct JMP instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.sfc + max_steps: 1072098 + check_interval_steps: 1072098 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/JMP/CPUJMP.png + expected_screen_hash: 0x0013810BB30450A3 + - id: peter-lemon-snes-cpu-ldr + description: | + The self-authored CPU LDR test ROM verifies correct LDR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.sfc + max_steps: 3335416 + check_interval_steps: 3335416 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/LDR/CPULDR.png + expected_screen_hash: 0xBF4684BD3981DC35 + - id: peter-lemon-snes-cpu-lsr + description: | + The self-authored CPU LSR test ROM verifies correct LSR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.sfc + max_steps: 1072098 + check_interval_steps: 1072098 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/LSR/CPULSR.png + expected_screen_hash: 0xD24E9136BDDF2416 + - id: peter-lemon-snes-cpu-mov + description: | + The self-authored CPU MOV test ROM verifies correct MOV instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.sfc + max_steps: 1072098 + check_interval_steps: 1072098 + reference_png: snes/peter-lemon-snes/CPUTest/CPU/MOV/CPUMOV.png + - id: peter-lemon-snes-cpu-msc + description: | + The self-authored CPU MSC test ROM verifies correct MSC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.sfc + max_steps: 3097172 + check_interval_steps: 3097172 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/MSC/CPUMSC.png + expected_screen_hash: 0xF57D3F255B69C0D3 + reset_at_steps: [100000] + - id: peter-lemon-snes-cpu-ora + description: | + The self-authored CPU ORA test ROM verifies correct ORA instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.sfc + max_steps: 3097172 + check_interval_steps: 3097172 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/ORA/CPUORA.png + expected_screen_hash: 0x02A73EF65F92CEA2 + - id: peter-lemon-snes-cpu-phl + description: | + The self-authored CPU PHL test ROM verifies correct PHL instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.sfc + max_steps: 2978050 + check_interval_steps: 2978050 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/PHL/CPUPHL.png + expected_screen_hash: 0x832F2C322B814DAA + - id: peter-lemon-snes-cpu-psr + description: | + The self-authored CPU PSR test ROM verifies correct PSR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.sfc + max_steps: 1250781 + check_interval_steps: 1250781 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/PSR/CPUPSR.png + expected_screen_hash: 0x47250BC0A20F1244 + - id: peter-lemon-snes-cpu-ret + description: | + The self-authored CPU RET test ROM verifies correct RET instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.sfc + max_steps: 1012537 + check_interval_steps: 1012537 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/RET/CPURET.png + expected_screen_hash: 0xB0A1A127D4AB3A28 + - id: peter-lemon-snes-cpu-rol + description: | + The self-authored CPU ROL test ROM verifies correct ROL instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.sfc + max_steps: 1012537 + check_interval_steps: 1012537 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/ROL/CPUROL.png + expected_screen_hash: 0x833F3680D0538274 + - id: peter-lemon-snes-cpu-ror + description: | + The self-authored CPU ROR test ROM verifies correct ROR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.sfc + max_steps: 1012537 + check_interval_steps: 1012537 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/ROR/CPUROR.png + expected_screen_hash: 0xB809D1ED9753496E + - id: peter-lemon-snes-cpu-sbc + description: | + The self-authored CPU SBC test ROM verifies correct SBC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.sfc + max_steps: 3097172 + check_interval_steps: 3097172 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/SBC/CPUSBC.png + expected_screen_hash: 0x7BCF082D0B67D0B6 + - id: peter-lemon-snes-cpu-str + description: | + The self-authored CPU STR test ROM verifies correct STR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.sfc + max_steps: 4228831 + check_interval_steps: 4228831 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/STR/CPUSTR.png + expected_screen_hash: 0x03B5E2805B76FD30 + - id: peter-lemon-snes-cpu-trn + description: | + The self-authored CPU TRN test ROM verifies correct TRN instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.sfc + max_steps: 3394977 + check_interval_steps: 3394977 + # reference_png: snes/peter-lemon-snes/CPUTest/CPU/TRN/CPUTRN.png + expected_screen_hash: 0xC7A76245F825519E + - id: peter-lemon-snes-spc700-adc + description: | + The self-authored SPC700 ADC test ROM verifies correct ADC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.sfc + max_steps: 92736477 + check_interval_steps: 92736477 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/ADC/SPC700ADC.png + - id: peter-lemon-snes-spc700-and + description: | + The self-authored SPC700 AND test ROM verifies correct AND instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.sfc + max_steps: 100777212 + check_interval_steps: 100777212 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/AND/SPC700AND.png + - id: peter-lemon-snes-spc700-dec + description: | + The self-authored SPC700 DEC test ROM verifies correct DEC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.sfc + max_steps: 50000000 + check_interval_steps: 50000000 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/DEC/SPC700DEC.png + - id: peter-lemon-snes-spc700-eor + description: | + The self-authored SPC700 EOR test ROM verifies correct EOR instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.sfc + max_steps: 92557794 + check_interval_steps: 92557794 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/EOR/SPC700EOR.png + - id: peter-lemon-snes-spc700-inc + description: | + The self-authored SPC700 INC test ROM verifies correct INC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.sfc + max_steps: 50000000 + check_interval_steps: 50000000 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/INC/SPC700INC.png + - id: peter-lemon-snes-spc700-ora + description: | + The self-authored SPC700 ORA test ROM verifies correct ORA instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.sfc + max_steps: 100777212 + check_interval_steps: 100777212 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/ORA/SPC700ORA.png + - id: peter-lemon-snes-spc700-sbc + description: | + The self-authored SPC700 SBC test ROM verifies correct SBC instruction behavior across all addressing modes, including edge cases for negative results, zero results, unsigned overflow, and carry flag behavior. + rom: snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.sfc + max_steps: 93570331 + check_interval_steps: 93570331 + reference_png: snes/peter-lemon-snes/CPUTest/SPC700/SBC/SPC700SBC.png + - id: peter-lemon-snes-bank-hiromfastrom + description: | + Test that the CPU master clock rate is correct when MEMSEL is set to fast mode. + rom: snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.sfc + max_steps: 952976 + check_interval_steps: 952976 + reference_png: snes/peter-lemon-snes/BANK/HiROMFastROM/BANKHiROMFastROM.png + - id: peter-lemon-snes-bank-hiromslowrom + description: | + Test that the CPU master clock rate is correct when MEMSEL is set to slow mode. + rom: snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.sfc + max_steps: 952976 + check_interval_steps: 952976 + reference_png: snes/peter-lemon-snes/BANK/HiROMSlowROM/BANKHiROMSlowROM.png + - id: peter-lemon-snes-bank-loromfastrom + description: | + Test that the CPU master clock rate is correct when MEMSEL is set to fast mode. + rom: snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.sfc + max_steps: 952976 + check_interval_steps: 952976 + reference_png: snes/peter-lemon-snes/BANK/LoROMFastROM/BANKLoROMFastROM.png + - id: peter-lemon-snes-bank-loromslowrom + description: | + Test that the CPU master clock rate is correct when MEMSEL is set to slow mode. + rom: snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.sfc + max_steps: 952976 + check_interval_steps: 952976 + reference_png: snes/peter-lemon-snes/BANK/LoROMSlowROM/BANKLoROMSlowROM.png + - id: peter-lemon-snes-bank-wram + description: | + Test that the CPU master clock rate is correct when MEMSEL is set to fast mode and WRAM is accessed. + rom: snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.sfc + max_steps: 952976 + check_interval_steps: 952976 + reference_png: snes/peter-lemon-snes/BANK/WRAM/BANKWRAM.png + - id: peter-lemon-snes-gsu-adc + description: | + Peter Lemon's GSU ADC test verifies SuperFX add-with-carry instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.sfc + max_steps: 4705319 + check_interval_steps: 4705319 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADC/GSUADC.png + - id: peter-lemon-snes-gsu-add + description: | + Peter Lemon's GSU ADD test verifies SuperFX addition instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.sfc + max_steps: 3990587 + check_interval_steps: 3990587 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ADD/GSUADD.png + - id: peter-lemon-snes-gsu-asr + description: | + Peter Lemon's GSU ASR test verifies SuperFX arithmetic shift right instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.sfc + max_steps: 2918489 + check_interval_steps: 2918489 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ASR/GSUASR.png + - id: peter-lemon-snes-gsu-cmp + description: | + Peter Lemon's GSU CMP test verifies SuperFX compare instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/CMP/GSUCMP.png + - id: peter-lemon-snes-gsu-dec + description: | + Peter Lemon's GSU DEC test verifies SuperFX decrement instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/DEC/GSUDEC.png + - id: peter-lemon-snes-gsu-div2 + description: | + Peter Lemon's GSU DIV2 test verifies SuperFX divide by 2 instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/DIV2/GSUDIV2.png + - id: peter-lemon-snes-gsu-hib + description: | + Peter Lemon's GSU HIB test verifies SuperFX high byte instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/HIB/GSUHIB.png + - id: peter-lemon-snes-gsu-ibt + description: | + Peter Lemon's GSU IBT test verifies SuperFX instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/IBT/GSUIBT.png + - id: peter-lemon-snes-gsu-inc + description: | + Peter Lemon's GSU INC test verifies SuperFX increment instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/INC/GSUINC.png + - id: peter-lemon-snes-gsu-iwt + description: | + Peter Lemon's GSU IWT test verifies SuperFX instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/IWT/GSUIWT.png + - id: peter-lemon-snes-gsu-lob + description: | + Peter Lemon's GSU LOB test verifies SuperFX low byte instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LOB/GSULOB.png + - id: peter-lemon-snes-gsu-lsr + description: | + Peter Lemon's GSU LSR test verifies SuperFX logical shift right instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LSR/GSULSR.png + - id: peter-lemon-snes-gsu-merge + description: | + Peter Lemon's GSU MERGE test verifies SuperFX merge instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MERGE/GSUMERGE.png + - id: peter-lemon-snes-gsu-move + description: | + Peter Lemon's GSU MOVE test verifies SuperFX move instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVE/GSUMOVE.png + - id: peter-lemon-snes-gsu-moves + description: | + Peter Lemon's GSU MOVES test verifies SuperFX moves instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MOVES/GSUMOVES.png + - id: peter-lemon-snes-gsu-not + description: | + Peter Lemon's GSU NOT test verifies SuperFX NOT instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/NOT/GSUNOT.png + - id: peter-lemon-snes-gsu-rol + description: | + Peter Lemon's GSU ROL test verifies SuperFX rotate left instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROL/GSUROL.png + - id: peter-lemon-snes-gsu-ror + description: | + Peter Lemon's GSU ROR test verifies SuperFX rotate right instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/ROR/GSUROR.png + - id: peter-lemon-snes-gsu-sbc + description: | + Peter Lemon's GSU SBC test verifies SuperFX subtract with carry instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SBC/GSUSBC.png + - id: peter-lemon-snes-gsu-sex + description: | + Peter Lemon's GSU SEX test verifies SuperFX sign extend instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SEX/GSUSEX.png + - id: peter-lemon-snes-gsu-sub + description: | + Peter Lemon's GSU SUB test verifies SuperFX subtract instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.sfc + max_steps: 3990587 + check_interval_steps: 3990587 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SUB/GSUSUB.png + - id: peter-lemon-snes-gsu-swap + description: | + Peter Lemon's GSU SWAP test verifies SuperFX swap instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/SWAP/GSUSWAP.png + - id: peter-lemon-snes-gsu-umult + description: | + Peter Lemon's GSU UMULT test verifies SuperFX unsigned multiply instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/UMULT/GSUUMULT.png + - id: peter-lemon-snes-gsu-and + description: | + Peter Lemon's GSU AND test verifies SuperFX logical AND instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/AND/GSUAND.png + - id: peter-lemon-snes-gsu-bic + description: | + Peter Lemon's GSU BIC test verifies SuperFX bit clear instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/BIC/GSUBIC.png + - id: peter-lemon-snes-gsu-cacheinject + description: | + Peter Lemon's GSU CACHEINJECT test verifies SuperFX cache injection instruction. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/CACHEINJECT/GSUCACHEINJECT.png + - id: peter-lemon-snes-gsu-fmult + description: | + Peter Lemon's GSU FMULT test verifies SuperFX fractional multiply instruction + across all registers, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/FMULT/GSUFMULT.png + - id: peter-lemon-snes-gsu-lmult + description: | + Peter Lemon's GSU LMULT test verifies SuperFX long multiply instruction + across all registers, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/LMULT/GSULMULT.png + - id: peter-lemon-snes-gsu-mult + description: | + Peter Lemon's GSU MULT test verifies SuperFX multiply instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/MULT/GSUMULT.png + - id: peter-lemon-snes-gsu-or + description: | + Peter Lemon's GSU OR test verifies SuperFX logical OR instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/OR/GSUOR.png + - id: peter-lemon-snes-gsu-xor + description: | + Peter Lemon's GSU XOR test verifies SuperFX logical XOR instruction + across all registers and immediate values, checking VSCZ flags. + rom: snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/GSUTest/XOR/GSUXOR.png + - id: peter-lemon-snes-gsu-2bpp-fillpoly-256x128 + description: | + Peter Lemon's GSU 2BPP 256x128 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x128/GSU2BPP256x128FillPoly.png + - id: peter-lemon-snes-gsu-2bpp-fillpoly-256x160 + description: | + Peter Lemon's GSU 2BPP 256x160 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x160/GSU2BPP256x160FillPoly.png + - id: peter-lemon-snes-gsu-2bpp-fillpoly-256x192 + description: | + Peter Lemon's GSU 2BPP 256x192 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/FillPoly/256x192/GSU2BPP256x192FillPoly.png + - id: peter-lemon-snes-gsu-2bpp-plotline-256x128 + description: | + Peter Lemon's GSU 2BPP 256x128 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x128/GSU2BPP256x128PlotLine.png + - id: peter-lemon-snes-gsu-2bpp-plotline-256x160 + description: | + Peter Lemon's GSU 2BPP 256x160 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x160/GSU2BPP256x160PlotLine.png + - id: peter-lemon-snes-gsu-2bpp-plotline-256x192 + description: | + Peter Lemon's GSU 2BPP 256x192 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotLine/256x192/GSU2BPP256x192PlotLine.png + - id: peter-lemon-snes-gsu-2bpp-plotpixel-256x128 + description: | + Peter Lemon's GSU 2BPP 256x128 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x128/GSU2BPP256x128PlotPixel.png + - id: peter-lemon-snes-gsu-2bpp-plotpixel-256x160 + description: | + Peter Lemon's GSU 2BPP 256x160 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x160/GSU2BPP256x160PlotPixel.png + - id: peter-lemon-snes-gsu-2bpp-plotpixel-256x192 + description: | + Peter Lemon's GSU 2BPP 256x192 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 2BPP (4-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/2BPP/PlotPixel/256x192/GSU2BPP256x192PlotPixel.png + - id: peter-lemon-snes-gsu-4bpp-fillpoly-256x128 + description: | + Peter Lemon's GSU 4BPP 256x128 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x128/GSU4BPP256x128FillPoly.png + - id: peter-lemon-snes-gsu-4bpp-fillpoly-256x160 + description: | + Peter Lemon's GSU 4BPP 256x160 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x160/GSU4BPP256x160FillPoly.png + - id: peter-lemon-snes-gsu-4bpp-fillpoly-256x192 + description: | + Peter Lemon's GSU 4BPP 256x192 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/FillPoly/256x192/GSU4BPP256x192FillPoly.png + - id: peter-lemon-snes-gsu-4bpp-plotline-256x128 + description: | + Peter Lemon's GSU 4BPP 256x128 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x128/GSU4BPP256x128PlotLine.png + - id: peter-lemon-snes-gsu-4bpp-plotline-256x160 + description: | + Peter Lemon's GSU 4BPP 256x160 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x160/GSU4BPP256x160PlotLine.png + - id: peter-lemon-snes-gsu-4bpp-plotline-256x192 + description: | + Peter Lemon's GSU 4BPP 256x192 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotLine/256x192/GSU4BPP256x192PlotLine.png + - id: peter-lemon-snes-gsu-4bpp-plotpixel-256x128 + description: | + Peter Lemon's GSU 4BPP 256x128 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x128/GSU4BPP256x128PlotPixel.png + - id: peter-lemon-snes-gsu-4bpp-plotpixel-256x160 + description: | + Peter Lemon's GSU 4BPP 256x160 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x160/GSU4BPP256x160PlotPixel.png + - id: peter-lemon-snes-gsu-4bpp-plotpixel-256x192 + description: | + Peter Lemon's GSU 4BPP 256x192 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 4BPP (16-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/4BPP/PlotPixel/256x192/GSU4BPP256x192PlotPixel.png + - id: peter-lemon-snes-gsu-8bpp-fillpoly-256x128 + description: | + Peter Lemon's GSU 8BPP 256x128 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x128/GSU8BPP256x128FillPoly.png + - id: peter-lemon-snes-gsu-8bpp-fillpoly-256x160 + description: | + Peter Lemon's GSU 8BPP 256x160 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x160/GSU8BPP256x160FillPoly.png + - id: peter-lemon-snes-gsu-8bpp-fillpoly-256x192 + description: | + Peter Lemon's GSU 8BPP 256x192 Fill Poly test verifies SuperFX PLOT instruction + with polygon fill rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/FillPoly/256x192/GSU8BPP256x192FillPoly.png + - id: peter-lemon-snes-gsu-8bpp-plotline-256x128 + description: | + Peter Lemon's GSU 8BPP 256x128 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x128/GSU8BPP256x128PlotLine.png + - id: peter-lemon-snes-gsu-8bpp-plotline-256x160 + description: | + Peter Lemon's GSU 8BPP 256x160 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x160/GSU8BPP256x160PlotLine.png + - id: peter-lemon-snes-gsu-8bpp-plotline-256x192 + description: | + Peter Lemon's GSU 8BPP 256x192 Plot Line test verifies SuperFX PLOT instruction + with line rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotLine/256x192/GSU8BPP256x192PlotLine.png + - id: peter-lemon-snes-gsu-8bpp-plotpixel-256x128 + description: | + Peter Lemon's GSU 8BPP 256x128 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x128/GSU8BPP256x128PlotPixel.png + - id: peter-lemon-snes-gsu-8bpp-plotpixel-256x160 + description: | + Peter Lemon's GSU 8BPP 256x160 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x160/GSU8BPP256x160PlotPixel.png + - id: peter-lemon-snes-gsu-8bpp-plotpixel-256x192 + description: | + Peter Lemon's GSU 8BPP 256x192 Plot Pixel test verifies SuperFX PLOT instruction + with pixel rendering in 8BPP (256-color) mode. + rom: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.sfc + max_steps: 4586197 + check_interval_steps: 4586197 + reference_png: snes/peter-lemon-snes/CHIP/GSU/8BPP/PlotPixel/256x192/GSU8BPP256x192PlotPixel.png + - id: peter-lemon-snes-ppu-bgmap-8x8-2bpp-bg1-32x328-pal + description: | + Peter Lemon's PPU BG Map 8x8 2BPP 32x328 PAL test verifies correct rendering of + background maps in 2BPP (4-color) mode with a 32x328 tilemap and palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG1Map2BPP32x328PAL/8x8BG1Map2BPP32x328PAL.png + - id: peter-lemon-snes-ppu-bgmap-8x8-2bpp-bg2-32x328-pal + description: | + Peter Lemon's PPU BG Map 8x8 2BPP 32x328 PAL test verifies correct rendering of + background maps in 2BPP (4-color) mode with a 32x328 tilemap and palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG2Map2BPP32x328PAL/8x8BG2Map2BPP32x328PAL.png + - id: peter-lemon-snes-ppu-bgmap-8x8-2bpp-bg3-32x328-pal + description: | + Peter Lemon's PPU BG Map 8x8 2BPP 32x328 PAL test verifies correct rendering of + background maps in 2BPP (4-color) mode with a 32x328 tilemap and palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG3Map2BPP32x328PAL/8x8BG3Map2BPP32x328PAL.png + - id: peter-lemon-snes-ppu-bgmap-8x8-2bpp-bg4-32x328-pal + description: | + Peter Lemon's PPU BG Map 8x8 2BPP 32x328 PAL test verifies correct rendering of + background maps in 2BPP (4-color) mode with a 32x328 tilemap and palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/2BPP/8x8BG4Map2BPP32x328PAL/8x8BG4Map2BPP32x328PAL.png + - id: peter-lemon-snes-ppu-bgmap-8x8-4bpp-32x328-pal + description: | + Peter Lemon's PPU BG Map 8x8 4BPP 32x328 PAL test verifies correct rendering of + background maps in 4BPP (16-color) mode with a 32x328 tilemap and palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/4BPP/8x8BGMap4BPP32x328PAL/8x8BGMap4BPP32x328PAL.png + - id: peter-lemon-snes-ppu-bgmap-8x8-8bpp-tileflip-pal + description: | + Peter Lemon's PPU BG Map 8x8 8BPP Tile Flip PAL test verifies correct rendering of + background maps in 8BPP (256-color) mode with tile flipping and a palette. + rom: snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/BGMAP/8x8/8BPP/TileFlip/8x8BGMapTileFlip.png + - id: peter-lemon-snes-ppu-blend-hicolor-1241dlair + description: | + Peter Lemon's PPU Blend HiColor 1241 D'Lair test verifies correct rendering of + SuperFX HiColor blending effects in the 1241 D'Lair demo. + rom: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor1241DLair/HiColor1241DLair.png + - id: peter-lemon-snes-ppu-blend-hicolor-3840 + description: | + Peter Lemon's PPU Blend HiColor 3840 test verifies correct rendering of + SuperFX HiColor blending effects in the 3840 demo. + rom: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor3840/HiColor3840.png + - id: peter-lemon-snes-ppu-blend-hicolor-575myst + description: | + Peter Lemon's PPU Blend HiColor 575 Myst test verifies correct rendering of + SuperFX HiColor blending effects in the 575 Myst demo. + rom: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Blend/HiColor/HiColor575Myst/HiColor575Myst.png + - id: peter-lemon-snes-ppu-greenspace + description: | + Peter Lemon's PPU Green Space test verifies correct rendering of the green space + demo, which tests various PPU features and effects. + rom: snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/GreenSpace/GreenSpace.png + - id: peter-lemon-snes-ppu-interlace-font + description: | + Peter Lemon's PPU Interlace Font test verifies correct rendering of interlaced + text in the interlace font demo, which tests PPU interlace mode and text rendering. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceFont/InterlaceFont.png + - id: peter-lemon-snes-ppu-interlace-moogle + description: | + Peter Lemon's PPU Interlace Moogle test verifies correct rendering of interlaced + sprites in the interlace moogle demo, which tests PPU interlace mode and sprite rendering. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceMoogle/InterlaceMoogle.png + - id: peter-lemon-snes-ppu-interlace-rpg + description: | + Peter Lemon's PPU Interlace RPG test verifies correct rendering of interlaced + backgrounds and sprites in the interlace RPG demo, which tests PPU interlace mode and various rendering features. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceRPG/InterlaceRPG.png + - id: peter-lemon-snes-ppu-interlace-scroll + description: | + Peter Lemon's PPU Interlace Scroll test verifies correct rendering of interlaced + scrolling backgrounds in the interlace scroll demo, which tests PPU interlace mode and scrolling features. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceScroll/InterlaceScroll.png + - id: peter-lemon-snes-compress-lz77-lz77wramgfx + description: | + Peter Lemon's Compress LZ77 LZ77 WRAM GFX test verifies correct decompression of + LZ77 compressed graphics data from WRAM, testing the SuperFX's LZ77 decompression capabilities. + rom: snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/Compress/LZ77/LZ77WRAMGFX/LZ77WRAMGFX.png + - id: peter-lemon-snes-helloworld + description: | + Peter Lemon's Hello World test verifies basic SuperFX functionality by rendering + a simple "Hello World" message on the screen, testing core CPU and PPU features. + rom: snes/peter-lemon-snes/HelloWorld/HelloWorld.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/HelloWorld/HelloWorld.png + - id: snes-peter-lemon-snes-MSU-VIDEO15FPS15Col16Pal-VIDEO15FPS15Col16Pal + description: | + Peter Lemon's MSU VIDEO 15FPS 15 Color 16 Pal test verifies correct playback of + a 15 frames per second video with 15 colors and a 16-color palette using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and video rendering. + rom: snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/VIDEO15FPS15Col16Pal/VIDEO15FPS15Col16Pal.png + - id: snes-peter-lemon-snes-MSU-VIDEO15FPS16Col8Pal-VIDEO15FPS16Col8Pal + description: | + Peter Lemon's MSU VIDEO 15FPS 16 Color 8 Pal test verifies correct playback of + a 15 frames per second video with 16 colors and an 8-color palette using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and video rendering. + rom: snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/VIDEO15FPS16Col8Pal/VIDEO15FPS16Col8Pal.png + - id: snes-peter-lemon-snes-MSU-Touhou-BadApple!15FPS16ColInterlace-Touhou-BadApple!15FPS16ColInterlace + description: | + Peter Lemon's MSU Touhou Bad Apple! 15FPS 16 Color Interlace test verifies correct playback of + a 15 frames per second interlaced video with 16 colors using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and interlaced video rendering. + rom: snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/Touhou-BadApple!15FPS16ColInterlace/Touhou-BadApple!15FPS16ColInterlace.png + - id: snes-peter-lemon-snes-MSU-VIDEO15FPS15Col8Pal-VIDEO15FPS15Col8Pal + description: | + Peter Lemon's MSU VIDEO 15FPS 15 Color 8 Pal test verifies correct playback of + a 15 frames per second video with 15 colors and an 8-color palette using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and video rendering. + rom: snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/VIDEO15FPS15Col8Pal/VIDEO15FPS15Col8Pal.png + - id: snes-peter-lemon-snes-MSU-Touhou-BadApple!30FPS4ColInterlace-Touhou-BadApple!30FPS4ColInterlace + description: | + Peter Lemon's MSU Touhou Bad Apple! 30FPS 4 Color Interlace test verifies correct playback of + a 30 frames per second interlaced video with 4 colors using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and interlaced video rendering. + rom: snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/Touhou-BadApple!30FPS4ColInterlace/Touhou-BadApple!30FPS4ColInterlace.png + - id: snes-peter-lemon-snes-MSU-VIDEO15FPS16Col-VIDEO15FPS16Col + description: | + Peter Lemon's MSU VIDEO 15FPS 16 Color test verifies correct playback of + a 15 frames per second video with 16 colors using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and video rendering. + rom: snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/VIDEO15FPS16Col/VIDEO15FPS16Col.png + - id: snes-peter-lemon-snes-MSU-VIDEO15FPS16ColInterlace-VIDEO15FPS16ColInterlace + description: | + Peter Lemon's MSU VIDEO 15FPS 16 Color Interlace test verifies correct playback of + a 15 frames per second interlaced video with 16 colors using the MSU-1 audio expansion, testing SuperFX's MSU-1 capabilities and interlaced video rendering. + rom: snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/MSU/VIDEO15FPS16ColInterlace/VIDEO15FPS16ColInterlace.png + - id: snes-peter-lemon-snes-INPUT-XBandKeyboard-XBandKeyboard + description: | + Peter Lemon's INPUT XBand Keyboard test verifies correct input handling of the + XBand keyboard peripheral, testing SuperFX's input capabilities and compatibility with the XBand keyboard. + rom: snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/INPUT/XBandKeyboard/XBandKeyboard.png + - id: snes-peter-lemon-snes-INPUT-ControllerLatency-ControllerLatency + description: | + Peter Lemon's INPUT Controller Latency test verifies correct input handling of the + controller, testing SuperFX's input capabilities and controller latency. + rom: snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/INPUT/ControllerLatency/ControllerLatency.png + - id: snes-peter-lemon-snes-PPU-Interlace-InterlaceSimpsonsHDMA-InterlaceSimpsonsHDMA + description: | + Peter Lemon's PPU Interlace Simpsons HDMA test verifies correct rendering of interlaced + backgrounds and sprites with HDMA effects in the interlace Simpsons HDMA demo, which tests PPU interlace mode, HDMA functionality, and various rendering features. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceSimpsonsHDMA/InterlaceSimpsonsHDMA.png + - id: snes-peter-lemon-snes-PPU-Interlace-InterlaceMystHDMA-InterlaceMystHDMA + description: | + Peter Lemon's PPU Interlace Myst HDMA test verifies correct rendering of interlaced + backgrounds and sprites with HDMA effects in the interlace Myst HDMA demo, which tests PPU interlace mode, HDMA functionality, and various rendering features. + rom: snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Interlace/InterlaceMystHDMA/InterlaceMystHDMA.png + - id: snes-peter-lemon-snes-PPU-Rings-Rings + description: | + Peter Lemon's PPU Rings test verifies correct rendering of the rings demo, which + tests various PPU features and effects, including sprite rendering, color math, and transformations. + rom: snes/peter-lemon-snes/PPU/Rings/Rings.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Rings/Rings.png + - id: snes-peter-lemon-snes-PPU-Window-WindowMultiHDMA-WindowMultiHDMA + description: | + Peter Lemon's PPU Window Multi HDMA test verifies correct rendering of multiple + HDMA effects applied to the window layer in the Window Multi HDMA demo, which tests PPU window functionality, HDMA capabilities, and various rendering features. + rom: snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Window/WindowMultiHDMA/WindowMultiHDMA.png + - id: snes-peter-lemon-snes-PPU-Window-WindowHDMA-WindowHDMA + description: | + Peter Lemon's PPU Window HDMA test verifies correct rendering of HDMA effects applied + to the window layer in the Window HDMA demo, which tests PPU window functionality, HDMA capabilities, and various rendering features. + rom: snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Window/WindowHDMA/WindowHDMA.png + - id: snes-peter-lemon-snes-PPU-Mode7-Perspective-Perspective + description: | + Peter Lemon's PPU Mode7 Perspective test verifies correct rendering of perspective + transformations in the Mode 7 Perspective demo, which tests PPU Mode 7 capabilities and perspective transformation effects. + rom: snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + # reference_png: snes/peter-lemon-snes/PPU/Mode7/Perspective/Perspective.png + expected_screen_hash: 0x5A2E5D38B6AD2A33 + - id: snes-peter-lemon-snes-PPU-Mode7-RotZoom-RotZoom + description: | + Peter Lemon's PPU Mode7 RotZoom test verifies correct rendering of rotation and zoom + transformations in the Mode 7 RotZoom demo, which tests PPU Mode 7 capabilities and rotation/zoom effects. + rom: snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Mode7/RotZoom/RotZoom.png + - id: snes-peter-lemon-snes-PPU-Mode7-StarWars-StarWars + description: | + Peter Lemon's PPU Mode7 StarWars test verifies correct rendering of the StarWars demo, + which tests PPU Mode 7 capabilities and various rendering effects. + rom: snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Mode7/StarWars/StarWars.png + - id: snes-peter-lemon-snes-PPU-Mosaic-Mode3-MosaicMode3 + description: | + Peter Lemon's PPU Mosaic Mode 3 test verifies correct rendering of mosaic effects + in Mode 3 in the Mosaic Mode 3 demo, which tests PPU mosaic functionality and Mode 3 rendering capabilities. + rom: snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Mosaic/Mode3/MosaicMode3.png + - id: snes-peter-lemon-snes-PPU-Mosaic-Mode5-MosaicMode5 + description: | + Peter Lemon's PPU Mosaic Mode 5 test verifies correct rendering of mosaic effects + in Mode 5 in the Mosaic Mode 5 demo, which tests PPU mosaic functionality and Mode 5 rendering capabilities. + rom: snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/Mosaic/Mode5/MosaicMode5.png + - id: snes-peter-lemon-snes-PPU-HDMA-RedSpaceIndirectHDMA-RedSpaceIndirectHDMA + description: | + Peter Lemon's PPU HDMA Red Space Indirect HDMA test verifies correct rendering of + indirect HDMA effects in the Red Space Indirect HDMA demo, which tests PPU HDMA functionality, indirect addressing modes, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedSpaceIndirectHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/RedSpaceIndirectHDMA/RedspaceIndirectHDMA.png + - id: snes-peter-lemon-snes-PPU-HDMA-WaveHDMA-WaveHDMA + description: | + Peter Lemon's PPU HDMA Wave HDMA test verifies correct rendering of wave HDMA effects + in the Wave HDMA demo, which tests PPU HDMA functionality, wave transformations, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/WaveHDMA/WaveHDMA.png + - id: snes-peter-lemon-snes-PPU-HDMA-Mode7HDMA-Mode7HDMA + description: | + Peter Lemon's PPU HDMA Mode 7 HDMA test verifies correct rendering of HDMA effects + applied to Mode 7 transformations in the Mode 7 HDMA demo, which tests PPU HDMA functionality, Mode 7 capabilities, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/Mode7HDMA/Mode7HDMA.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor128PerTileRow-HiColor128PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 128 Per Tile Row test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 128 colors per tile row in the HiColor 128 Per Tile Row demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/HiColor128PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor128PerTileRow-TEST-RGB_24bits_palette_color_test_chart128PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 128 Per Tile Row RGB 24bits Palette Color Test Chart test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 128 colors per tile row using a 24-bit RGB palette color test chart in the HiColor 128 Per Tile Row RGB 24bits Palette Color Test Chart demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/RGB_24bits_palette_color_test_chart128PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor128PerTileRow-TEST-mandrill128PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 128 Per Tile Row Mandrill test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 128 colors per tile row using a mandrill image in the HiColor 128 Per Tile Row Mandrill demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/mandrill128PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor128PerTileRow-TEST-lenna128PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 128 Per Tile Row Lenna test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 128 colors per tile row using a Lenna image in the HiColor 128 Per Tile Row Lenna demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/lenna128PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor128PerTileRow-TEST-DQ128PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 128 Per Tile Row DQ test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 128 colors per tile row using a DQ image in the HiColor 128 Per Tile Row DQ demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor128PerTileRow/TEST/DQ128PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-RedSpace9BitHDMA-RedSpace9BitHDMA + description: | + Peter Lemon's PPU HDMA Red Space 9 Bit HDMA test verifies correct rendering of + 9-bit color HDMA effects in the Red Space 9 Bit HDMA demo, which tests PPU HDMA functionality, 9-bit color rendering capabilities, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/RedSpace9BitHDMA/RedSpace9BitHDMA.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRowPseudoHiRes-TEST-lenna64PerTileRowHiRes + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Pseudo HiRes Lenna test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in pseudo hi-res mode using a Lenna image in the HiColor 64 Per Tile Row Pseudo HiRes Lenna demo, which tests PPU HDMA functionality, HiColor rendering capabilities, pseudo hi-res mode, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/lenna64PerTileRowHiRes.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRowPseudoHiRes-TEST-mandrill64PerTileRowHiRes + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Pseudo HiRes Mandrill test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in pseudo hi-res mode using a mandrill image in the HiColor 64 Per Tile Row Pseudo HiRes Mandrill demo, which tests PPU HDMA functionality, HiColor rendering capabilities, pseudo hi-res mode, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/mandrill64PerTileRowHiRes.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRowPseudoHiRes-TEST-RGB_24bits_palette_color_test_chart64PerTileRowHiRes + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Pseudo HiRes RGB 24bits Palette Color Test Chart test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in pseudo hi-res mode using a 24-bit RGB palette color test chart in the HiColor 64 Per Tile Row Pseudo HiRes RGB 24bits Palette Color Test Chart demo, which tests PPU HDMA functionality, HiColor rendering capabilities, pseudo hi-res mode, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/TEST/RGB_24bits_palette_color_test_chart64PerTileRowHiRes.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRowPseudoHiRes-HiColor64PerTileRowPseudoHiRes + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Pseudo HiRes test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in pseudo hi-res mode in the HiColor 64 Per Tile Row Pseudo HiRes demo, which tests PPU HDMA functionality, HiColor rendering capabilities, pseudo hi-res mode, and various rendering features. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRowPseudoHiRes/HiColor64PerTileRowPseudoHiRes.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRow-TEST-RGB_24bits_palette_color_test_chart64PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row RGB 24bits Palette Color Test Chart test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row using a 24-bit RGB palette color test chart in the HiColor 64 Per Tile Row RGB 24bits Palette Color Test Chart demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/RGB_24bits_palette_color_test_chart64PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRow-TEST-mandrill64PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Mandrill test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in pseudo hi-res mode using a mandrill image in the HiColor 64 Per Tile Row Mandrill demo, which tests PPU HDMA functionality, HiColor rendering capabilities, pseudo hi-res mode, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/mandrill64PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRow-TEST-DQ64PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row DQ test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row using a DQ image in the HiColor 64 Per Tile Row DQ demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/DQ64PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRow-TEST-lenna64PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row Lenna test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row using a Lenna image in the HiColor 64 Per Tile Row Lenna demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/TEST/lenna64PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-HiColor64PerTileRow-HiColor64PerTileRow + description: | + Peter Lemon's PPU HDMA HiColor 64 Per Tile Row test verifies correct rendering of + HiColor (15-bit color) HDMA effects with 64 colors per tile row in the HiColor 64 Per Tile Row demo, which tests PPU HDMA functionality, HiColor rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/HiColor64PerTileRow/HiColor64PerTileRow.png + - id: snes-peter-lemon-snes-PPU-HDMA-RedSpaceHDMA-RedSpaceHDMA + description: | + Peter Lemon's PPU HDMA Red Space test verifies correct rendering of + HDMA effects in the Red Space demo, which tests PPU HDMA functionality and accurate color reproduction. + rom: snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedSpaceHDMA.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PPU/HDMA/RedSpaceHDMA/RedspaceHDMA.png + - id: snes-peter-lemon-snes-Games-MonsterFarmJump-MonsterFarmJump + description: | + Peter Lemon's Monster Farm Jump test verifies correct rendering of + gameplay and graphics in the Monster Farm Jump demo, which tests game mechanics, PPU functionality, and accurate color reproduction. + rom: snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/Games/MonsterFarmJump/MonsterFarmJump.png + - id: snes-peter-lemon-snes-PlotPixel-Mode7-PlotPixelMode7 + description: | + Peter Lemon's Plot Pixel Mode 7 test verifies correct rendering of + Mode 7 graphics in the Plot Pixel Mode 7 demo, which tests PPU functionality, Mode 7 rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PlotPixel/Mode7/PlotPixelMode7.png + - id: snes-peter-lemon-snes-PlotLine-Mode7-PlotLineMode7 + description: | + Peter Lemon's Plot Line Mode 7 test verifies correct rendering of + Mode 7 graphics in the Plot Line Mode 7 demo, which tests PPU functionality, Mode 7 rendering capabilities, and accurate color reproduction. + rom: snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.sfc + max_steps: 1667708 + check_interval_steps: 1667708 + reference_png: snes/peter-lemon-snes/PlotLine/Mode7/PlotLineMode7.png diff --git a/snes/rom_test/src/bin/rom_tool.rs b/snes/rom_test/src/bin/rom_tool.rs new file mode 100644 index 00000000..a146577f --- /dev/null +++ b/snes/rom_test/src/bin/rom_tool.rs @@ -0,0 +1,456 @@ +use clap::{Arg, ArgAction, Command}; +use nerust_snes_core::{Cartridge, EnhancementChip}; +use nerust_snes_render::render_screen; +use nerust_snes_rom_test::manifest::{RomManifest, load_default_manifest, load_manifest}; +use nerust_snes_rom_test::report::{default_output_root, write_html_report}; +use nerust_snes_rom_test::results::{CaseOutcome, ValidationOptions}; +use nerust_snes_rom_test::runner::{ + discover_msu1_audio_tracks, has_msu1_data_sidecar, load_core_for_case, + validate_case_with_options, +}; +use std::fs; +use std::path::{Path, PathBuf}; +use std::time::Instant; + +const SNES_NTSC_MASTER_CLOCK_HZ: f64 = 21_477_272.0; +const SNES_MASTER_CLOCKS_PER_SCANLINE: u64 = 1364; +const SNES_SCANLINES_PER_FRAME: u64 = 262; +const CPU_MASTER_CLOCKS_PER_CYCLE: u64 = 6; +const DEFAULT_BENCHMARK_THRESHOLD: &str = "5.0"; + +fn main() { + if let Err(message) = run() { + eprintln!("{message}"); + std::process::exit(1); + } +} + +fn run() -> Result<(), String> { + let matches = Command::new("rom_tool") + .about("SNES ROM test validation and HTML capture tooling") + .arg( + Arg::new("manifest") + .long("manifest") + .value_name("PATH") + .global(true), + ) + .arg( + Arg::new("case") + .long("case") + .value_name("ID") + .action(ArgAction::Append) + .global(true), + ) + .subcommand( + Command::new("validate") + .about("Validate configured SNES ROM cases and generate an HTML report") + .arg(Arg::new("output-dir").long("output-dir").value_name("DIR")), + ) + .subcommand( + Command::new("benchmark") + .about("Benchmark selected SNES ROM cases against NTSC real time") + .arg( + Arg::new("frames") + .long("frames") + .value_name("COUNT") + .default_value("120") + .value_parser(clap::value_parser!(u64)), + ) + .arg( + Arg::new("no-render") + .long("no-render") + .action(ArgAction::SetTrue) + .help("Skip per-frame software rendering and measure core execution only"), + ) + .arg( + Arg::new("threshold") + .long("threshold") + .value_name("RATIO") + .default_value(DEFAULT_BENCHMARK_THRESHOLD) + .value_parser(clap::value_parser!(f64)) + .help("Minimum emulation speed ratio required for each benchmark case"), + ) + .arg( + Arg::new("enhancement-only") + .long("enhancement-only") + .action(ArgAction::SetTrue) + .help( + "Benchmark only cases with an enhancement-chip header or MSU-1 sidecars", + ), + ) + .arg( + Arg::new("fail-on-slow") + .long("fail-on-slow") + .action(ArgAction::SetTrue) + .help("Exit with an error when any selected case runs below threshold"), + ), + ) + .subcommand(Command::new("list").about("List configured SNES ROM cases")) + .get_matches(); + + let manifest = matches + .get_one::("manifest") + .map(PathBuf::from) + .map_or_else( + || load_default_manifest().map_err(|error| error.to_string()), + |path| load_manifest(&path).map_err(|error| error.to_string()), + )?; + let case_ids = matches + .get_many::("case") + .map(|values| values.cloned().collect::>()) + .unwrap_or_default(); + + match matches.subcommand() { + Some(("validate", subcommand_matches)) => run_validate( + &manifest, + &case_ids, + subcommand_matches + .get_one::("output-dir") + .map(PathBuf::from) + .unwrap_or_else(|| default_output_root().join("validate")), + ), + Some(("benchmark", subcommand_matches)) => run_benchmark( + &manifest, + &case_ids, + *subcommand_matches + .get_one::("frames") + .ok_or_else(|| "missing benchmark frame count".to_string())?, + !subcommand_matches.get_flag("no-render"), + *subcommand_matches + .get_one::("threshold") + .ok_or_else(|| "missing benchmark threshold".to_string())?, + subcommand_matches.get_flag("enhancement-only"), + subcommand_matches.get_flag("fail-on-slow"), + ), + Some(("list", _)) => run_list(&manifest, &case_ids), + _ => Err("subcommand required: validate, benchmark, or list".to_string()), + } +} + +fn run_list(manifest: &RomManifest, case_ids: &[String]) -> Result<(), String> { + for case in manifest + .select(case_ids) + .map_err(|error| error.to_string())? + { + println!( + "{} rom={} max_steps={} description={}", + case.id, + case.rom.display(), + case.max_steps, + case.description + ); + } + Ok(()) +} + +fn run_benchmark( + manifest: &RomManifest, + case_ids: &[String], + frames: u64, + render_each_frame: bool, + threshold: f64, + enhancement_only: bool, + fail_on_slow: bool, +) -> Result<(), String> { + if case_ids.is_empty() && !enhancement_only { + return Err("benchmark requires at least one --case ID or --enhancement-only".to_string()); + } + if frames == 0 { + return Err("benchmark requires --frames > 0".to_string()); + } + if !threshold.is_finite() || threshold <= 0.0 { + return Err("benchmark requires --threshold > 0".to_string()); + } + + let selected_cases = manifest + .select(case_ids) + .map_err(|error| error.to_string())?; + let mut cases = Vec::new(); + for case in selected_cases { + let metadata = benchmark_metadata(case.rom_path())?; + if !enhancement_only || metadata.is_enhancement_case() { + cases.push(BenchmarkCase { case, metadata }); + } + } + if cases.is_empty() { + return Err("benchmark --enhancement-only matched no enhancement ROM cases".to_string()); + } + let total = cases.len(); + let cycles_per_frame = cpu_cycles_for_frames(1); + let mut realtime_cases = 0_usize; + + println!( + "mode=benchmark cases={} frames={} cycles_per_frame={} render_each_frame={} threshold={:.2}x enhancement_only={}", + total, frames, cycles_per_frame, render_each_frame, threshold, enhancement_only + ); + + for (index, entry) in cases.into_iter().enumerate() { + let case = entry.case; + println!( + "[{}/{}] case={} rom={} enhancement={:?} msu1_data={} msu1_audio_tracks={} description={}", + index + 1, + total, + case.id, + case.rom_path().display(), + entry.metadata.enhancement_chip, + entry.metadata.has_msu1_data, + entry.metadata.msu1_audio_track_count, + case.description + ); + + let mut core = load_core_for_case(case)?; + let start_cycles = core.master_cycles(); + let started = Instant::now(); + let mut frames_executed = 0_u64; + for _ in 0..frames { + if matches!(core.current_state(), nerust_snes_core::CpuState::Stopped) { + break; + } + core.run_for_cycles(cycles_per_frame) + .map_err(|error| format!("core error during benchmark: {error}"))?; + frames_executed += 1; + if render_each_frame { + render_screen(&core) + .map_err(|error| format!("failed to render benchmark frame: {error}"))?; + } + } + + let wall_seconds = started.elapsed().as_secs_f64(); + let cycles_executed = core.master_cycles().saturating_sub(start_cycles); + let emulated_seconds = emulated_seconds_for_cpu_cycles(cycles_executed); + let realtime_ratio = if wall_seconds > 0.0 { + emulated_seconds / wall_seconds + } else { + f64::INFINITY + }; + let realtime_status = if realtime_ratio >= threshold { + realtime_cases += 1; + "pass" + } else { + "slow" + }; + + println!( + " status={} frames={} cycles={} emulated_seconds={:.3} wall_seconds={:.3} speed={:.2}x", + realtime_status, + frames_executed, + cycles_executed, + emulated_seconds, + wall_seconds, + realtime_ratio + ); + } + + let slow_cases = total.saturating_sub(realtime_cases); + println!("summary realtime={} slow={}", realtime_cases, slow_cases); + + if fail_on_slow && slow_cases > 0 { + return Err(format!( + "{slow_cases} SNES ROM benchmark case(s) ran below the {threshold:.2}x threshold" + )); + } + + Ok(()) +} + +struct BenchmarkCase<'a> { + case: &'a nerust_snes_rom_test::manifest::RomCase, + metadata: BenchmarkMetadata, +} + +#[derive(Debug, Clone, PartialEq, Eq)] +struct BenchmarkMetadata { + enhancement_chip: EnhancementChip, + has_msu1_data: bool, + msu1_audio_track_count: usize, +} + +impl BenchmarkMetadata { + fn is_enhancement_case(&self) -> bool { + self.enhancement_chip != EnhancementChip::None + || self.has_msu1_data + || self.msu1_audio_track_count > 0 + } +} + +fn benchmark_metadata(rom_path: &Path) -> Result { + let rom = fs::read(rom_path) + .map_err(|error| format!("failed to read ROM `{}`: {error}", rom_path.display()))?; + let cartridge = Cartridge::from_bytes(&rom).map_err(|error| { + format!( + "failed to parse SNES cartridge header from `{}`: {error}", + rom_path.display() + ) + })?; + + Ok(BenchmarkMetadata { + enhancement_chip: cartridge.header().enhancement_chip(), + has_msu1_data: has_msu1_data_sidecar(rom_path)?, + msu1_audio_track_count: discover_msu1_audio_tracks(rom_path)?.len(), + }) +} + +fn run_validate( + manifest: &RomManifest, + case_ids: &[String], + output_dir: PathBuf, +) -> Result<(), String> { + let cases = manifest + .select(case_ids) + .map_err(|error| error.to_string())?; + let total = cases.len(); + let mut outcomes = Vec::with_capacity(total); + + println!( + "mode=validate cases={} output_dir={}", + total, + output_dir.display() + ); + + for (index, case) in cases.into_iter().enumerate() { + println!( + "[{}/{}] case={} rom={} description={}", + index + 1, + total, + case.id, + case.rom_path().display(), + case.description + ); + let outcome = validate_case_with_options(case, ValidationOptions::report()); + print_outcome(&outcome); + outcomes.push(outcome); + } + + let summary = write_html_report(&output_dir, "SNES ROM validation report", &outcomes)?; + println!( + "report={} passed={} failed={}", + summary.report_path.display(), + summary.passed, + summary.failed + ); + + if summary.failed > 0 { + return Err(format!( + "{} SNES ROM case(s) failed validation; see {}", + summary.failed, + summary.report_path.display() + )); + } + + Ok(()) +} + +fn print_outcome(outcome: &CaseOutcome) { + match outcome { + CaseOutcome::Completed(validation) => { + println!( + " status={} steps={} final_hash=0x{:016X}", + if validation.passed() { "pass" } else { "fail" }, + validation.steps_executed, + validation.final_screen_hash + ); + for failure in &validation.failures { + println!(" failure={failure}"); + } + } + + CaseOutcome::InternalError { + case_id, message, .. + } => { + println!(" case={case_id} status=error message={message}"); + } + } +} + +fn cpu_cycles_for_frames(frames: u64) -> u64 { + let master_clocks = u128::from(frames) + * u128::from(SNES_SCANLINES_PER_FRAME) + * u128::from(SNES_MASTER_CLOCKS_PER_SCANLINE); + ((master_clocks + u128::from(CPU_MASTER_CLOCKS_PER_CYCLE / 2)) + / u128::from(CPU_MASTER_CLOCKS_PER_CYCLE)) as u64 +} + +fn emulated_seconds_for_cpu_cycles(cycles: u64) -> f64 { + (cycles as f64) * (CPU_MASTER_CLOCKS_PER_CYCLE as f64) / SNES_NTSC_MASTER_CLOCK_HZ +} + +#[cfg(test)] +mod tests { + use super::{benchmark_metadata, cpu_cycles_for_frames, emulated_seconds_for_cpu_cycles}; + use nerust_snes_core::EnhancementChip; + use std::fs; + use std::path::PathBuf; + use std::sync::atomic::{AtomicUsize, Ordering}; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + static TEMP_COUNTER: AtomicUsize = AtomicUsize::new(0); + + #[test] + fn cpu_cycles_for_frames_rounds_ntsc_master_clock_budget() { + assert_eq!(cpu_cycles_for_frames(1), 59_561); + assert_eq!(cpu_cycles_for_frames(3), 178_684); + } + + #[test] + fn emulated_seconds_use_ntsc_master_clock_rate() { + let seconds = emulated_seconds_for_cpu_cycles(3_579_545); + assert!((seconds - 1.0).abs() < 0.001); + } + + #[test] + fn benchmark_metadata_reports_plain_lorom_without_sidecars() { + let directory = unique_temp_dir("plain-lorom"); + fs::create_dir_all(&directory).expect("temp directory should be created"); + let rom_path = directory.join("plain.sfc"); + fs::write(&rom_path, build_lorom(0x20, 0x00)).expect("ROM should be written"); + + let metadata = benchmark_metadata(&rom_path).expect("metadata should load"); + assert_eq!(metadata.enhancement_chip, EnhancementChip::None); + assert!(!metadata.has_msu1_data); + assert_eq!(metadata.msu1_audio_track_count, 0); + assert!(!metadata.is_enhancement_case()); + + fs::remove_dir_all(directory).expect("temp directory should be removed"); + } + + #[test] + fn benchmark_metadata_reports_sa1_and_msu1_sidecars() { + let directory = unique_temp_dir("sa1-msu1"); + fs::create_dir_all(&directory).expect("temp directory should be created"); + let rom_path = directory.join("speed.sfc"); + fs::write(&rom_path, build_lorom(0x23, 0x34)).expect("ROM should be written"); + fs::write(directory.join("speed.msu"), []).expect("MSU data sidecar should be written"); + fs::write(directory.join("speed-1.pcm"), []).expect("MSU audio sidecar should be written"); + fs::write(directory.join("speed-invalid.pcm"), []) + .expect("ignored MSU audio sidecar should be written"); + + let metadata = benchmark_metadata(&rom_path).expect("metadata should load"); + assert_eq!(metadata.enhancement_chip, EnhancementChip::Sa1); + assert!(metadata.has_msu1_data); + assert_eq!(metadata.msu1_audio_track_count, 1); + assert!(metadata.is_enhancement_case()); + + fs::remove_dir_all(directory).expect("temp directory should be removed"); + } + + fn unique_temp_dir(label: &str) -> PathBuf { + std::env::temp_dir().join(format!( + "nerust-rom-tool-{label}-{}-{}", + std::process::id(), + TEMP_COUNTER.fetch_add(1, Ordering::Relaxed) + )) + } + + fn build_lorom(map_mode: u8, chipset: u8) -> Vec { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"BENCH METADATA TEST "); + rom[HEADER_OFFSET + 0x15] = map_mode; + rom[HEADER_OFFSET + 0x16] = chipset; + rom[HEADER_OFFSET + 0x17] = 0x08; + rom[HEADER_OFFSET + 0x18] = 0x00; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2] + .copy_from_slice(&0x8000_u16.to_le_bytes()); + rom + } +} diff --git a/snes/rom_test/src/lib.rs b/snes/rom_test/src/lib.rs new file mode 100644 index 00000000..acb3d6bd --- /dev/null +++ b/snes/rom_test/src/lib.rs @@ -0,0 +1,5 @@ +pub mod manifest; +pub mod media; +pub mod report; +pub mod results; +pub mod runner; diff --git a/snes/rom_test/src/manifest.rs b/snes/rom_test/src/manifest.rs new file mode 100644 index 00000000..f0aa2540 --- /dev/null +++ b/snes/rom_test/src/manifest.rs @@ -0,0 +1,515 @@ +use serde_derive::Deserialize; +use std::collections::BTreeSet; +use std::fs; +use std::path::{Path, PathBuf}; + +const APU_RAM_SIZE: u32 = 0x1_0000; + +#[derive(Debug, thiserror::Error)] +pub enum ManifestError { + #[error("failed to read ROM manifest `{path}`: {source}")] + Io { + path: PathBuf, + #[source] + source: std::io::Error, + }, + #[error("failed to parse ROM manifest `{path}`: {source}")] + Parse { + path: PathBuf, + #[source] + source: serde_yaml::Error, + }, + #[error("invalid ROM manifest: {message}")] + Invalid { message: String }, +} + +#[derive(Debug, Deserialize)] +pub struct RomManifest { + #[serde(default)] + rom_root: PathBuf, + pub cases: Vec, +} + +#[derive(Debug, Deserialize)] +pub struct RomCase { + pub id: String, + pub description: String, + pub rom: PathBuf, + pub max_steps: u64, + #[serde(default = "default_check_interval_steps")] + pub check_interval_steps: u64, + #[serde(default)] + pub expected_screen_hash: Option, + #[serde(default)] + pub reference_png: Option, + #[serde(default)] + pub assertions: Vec, + #[serde(default)] + pub reset_at_steps: Vec, + #[serde(skip)] + resolved_rom_path: PathBuf, + #[serde(skip)] + resolved_png_path: Option, +} + +#[derive(Debug, Deserialize)] +#[serde(tag = "kind", rename_all = "snake_case")] +pub enum Assertion { + BusU8 { address: String, expected: String }, + BusU16 { address: String, expected: String }, + ApuRamU8 { address: String, expected: String }, + ApuRamU16 { address: String, expected: String }, + WramU8 { address: String, expected: String }, + WramU16 { address: String, expected: String }, + VramU8 { address: String, expected: String }, + VramU16 { address: String, expected: String }, + CgramU8 { address: String, expected: String }, + CgramU16 { address: String, expected: String }, + OamU8 { address: String, expected: String }, + OamU16 { address: String, expected: String }, +} + +pub fn load_default_manifest() -> Result { + let manifest_path = PathBuf::from(env!("CARGO_MANIFEST_DIR")).join("rom_tests.yaml"); + load_manifest(&manifest_path) +} + +pub fn load_manifest(path: &Path) -> Result { + let manifest_source = fs::read_to_string(path).map_err(|source| ManifestError::Io { + path: path.to_path_buf(), + source, + })?; + let mut manifest = serde_yaml::from_str::(&manifest_source).map_err(|source| { + ManifestError::Parse { + path: path.to_path_buf(), + source, + } + })?; + manifest.resolve(path)?; + Ok(manifest) +} + +impl RomManifest { + pub fn case(&self, case_id: &str) -> Option<&RomCase> { + self.cases.iter().find(|case| case.id == case_id) + } + + pub fn select<'a>(&'a self, case_ids: &[String]) -> Result, ManifestError> { + if !case_ids.is_empty() { + let available = self + .cases + .iter() + .map(|case| case.id.as_str()) + .collect::>(); + let missing = case_ids + .iter() + .map(String::as_str) + .filter(|case_id| !available.contains(case_id)) + .collect::>(); + if !missing.is_empty() { + return Err(ManifestError::Invalid { + message: format!( + "unknown ROM case id(s): {}", + missing.into_iter().collect::>().join(", ") + ), + }); + } + } + + let mut selected = self + .cases + .iter() + .filter(|case| case_ids.is_empty() || case_ids.contains(&case.id)) + .collect::>(); + selected.sort_by(|left, right| left.id.cmp(&right.id)); + + if selected.is_empty() { + return Err(ManifestError::Invalid { + message: if case_ids.is_empty() { + "no ROM cases matched all cases".to_string() + } else { + format!("no ROM cases matched {}", case_ids.join(", ")) + }, + }); + } + + Ok(selected) + } + + fn resolve(&mut self, manifest_path: &Path) -> Result<(), ManifestError> { + if self.cases.is_empty() { + return Err(ManifestError::Invalid { + message: "ROM manifest must contain at least one case".to_string(), + }); + } + + let manifest_dir = manifest_path + .parent() + .ok_or_else(|| ManifestError::Invalid { + message: format!( + "ROM manifest path `{}` does not have a parent directory", + manifest_path.display() + ), + })?; + let rom_root = manifest_dir.join(&self.rom_root); + + let mut seen_case_ids = BTreeSet::new(); + for case in &mut self.cases { + if !seen_case_ids.insert(case.id.clone()) { + return Err(ManifestError::Invalid { + message: format!("duplicate ROM case id `{}`", case.id), + }); + } + case.resolve(&rom_root)?; + } + + Ok(()) + } +} + +impl RomCase { + pub fn rom_path(&self) -> &Path { + &self.resolved_rom_path + } + + pub fn png_path(&self) -> Option<&Path> { + self.resolved_png_path.as_deref() + } + + pub fn expected_screen_hash(&self) -> Result, ManifestError> { + self.expected_screen_hash + .as_deref() + .map(|value| parse_value(value, "expected_screen_hash")) + .transpose() + } + + fn resolve(&mut self, rom_root: &Path) -> Result<(), ManifestError> { + if self.max_steps == 0 { + return Err(ManifestError::Invalid { + message: format!("ROM case `{}` must have max_steps > 0", self.id), + }); + } + if self.check_interval_steps == 0 { + return Err(ManifestError::Invalid { + message: format!("ROM case `{}` must have check_interval_steps > 0", self.id), + }); + } + if self.assertions.is_empty() + && self.expected_screen_hash.is_none() + && self.reference_png.is_none() + { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{}` must contain at least one assertion, expected_screen_hash, or reference_png", + self.id + ), + }); + } + + self.resolved_rom_path = rom_root.join(&self.rom); + if !self.resolved_rom_path.is_file() { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{}` points to missing ROM `{}`", + self.id, + self.resolved_rom_path.display() + ), + }); + } + + self.resolved_png_path = self.reference_png.as_ref().map(|png| rom_root.join(png)); + if let Some(ref png_path) = self.resolved_png_path { + if !png_path.is_file() { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{}` points to missing reference PNG `{}`", + self.id, + png_path.display() + ), + }); + } + } + + for assertion in &self.assertions { + assertion.validate(&self.id)?; + } + if self.expected_screen_hash.is_some() { + self.expected_screen_hash() + .map_err(|error| ManifestError::Invalid { + message: format!( + "ROM case `{}` has invalid expected_screen_hash: {error}", + self.id + ), + })?; + } + + // Validate reset_at_steps is sorted and within max_steps + for (i, step) in self.reset_at_steps.windows(2).enumerate() { + if step[0] >= step[1] { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{}` has unsorted or duplicate reset_at_steps values at index {}", + self.id, i + ), + }); + } + } + if let Some(&last_step) = self.reset_at_steps.last() + && last_step >= self.max_steps + { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{}` has reset_at_steps value {} >= max_steps {}", + self.id, last_step, self.max_steps + ), + }); + } + + Ok(()) + } +} + +impl Assertion { + pub fn address(&self) -> Result { + match self { + Self::BusU8 { address, .. } + | Self::BusU16 { address, .. } + | Self::ApuRamU8 { address, .. } + | Self::ApuRamU16 { address, .. } + | Self::WramU8 { address, .. } + | Self::WramU16 { address, .. } + | Self::VramU8 { address, .. } + | Self::VramU16 { address, .. } + | Self::CgramU8 { address, .. } + | Self::CgramU16 { address, .. } + | Self::OamU8 { address, .. } + | Self::OamU16 { address, .. } => parse_value(address, "address").and_then(|value| { + u32::try_from(value).map_err(|_| ManifestError::Invalid { + message: format!("address `{address}` does not fit in u32"), + }) + }), + } + } + + pub fn expected_u8(&self) -> Result { + match self { + Self::BusU8 { expected, .. } + | Self::ApuRamU8 { expected, .. } + | Self::WramU8 { expected, .. } + | Self::VramU8 { expected, .. } + | Self::CgramU8 { expected, .. } + | Self::OamU8 { expected, .. } => parse_value(expected, "expected").and_then(|value| { + u8::try_from(value).map_err(|_| ManifestError::Invalid { + message: format!("expected value `{expected}` does not fit in u8"), + }) + }), + Self::BusU16 { .. } + | Self::ApuRamU16 { .. } + | Self::WramU16 { .. } + | Self::VramU16 { .. } + | Self::CgramU16 { .. } + | Self::OamU16 { .. } => Err(ManifestError::Invalid { + message: "expected_u8 called for 16-bit assertion".to_string(), + }), + } + } + + pub fn expected_u16(&self) -> Result { + match self { + Self::BusU16 { expected, .. } + | Self::ApuRamU16 { expected, .. } + | Self::WramU16 { expected, .. } + | Self::VramU16 { expected, .. } + | Self::CgramU16 { expected, .. } + | Self::OamU16 { expected, .. } => { + parse_value(expected, "expected").and_then(|value| { + u16::try_from(value).map_err(|_| ManifestError::Invalid { + message: format!("expected value `{expected}` does not fit in u16"), + }) + }) + } + Self::BusU8 { .. } + | Self::ApuRamU8 { .. } + | Self::WramU8 { .. } + | Self::VramU8 { .. } + | Self::CgramU8 { .. } + | Self::OamU8 { .. } => Err(ManifestError::Invalid { + message: "expected_u16 called for 8-bit assertion".to_string(), + }), + } + } + + fn validate(&self, case_id: &str) -> Result<(), ManifestError> { + let address = self.address().map_err(|error| ManifestError::Invalid { + message: format!("ROM case `{case_id}` has invalid assertion address: {error}"), + })?; + + match self { + Self::ApuRamU8 { .. } if address >= APU_RAM_SIZE => { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{case_id}` has APU RAM u8 assertion address 0x{address:04X} outside 64 KiB APU RAM" + ), + }); + } + Self::ApuRamU16 { .. } if address >= APU_RAM_SIZE - 1 => { + return Err(ManifestError::Invalid { + message: format!( + "ROM case `{case_id}` has APU RAM u16 assertion address 0x{address:04X} crossing 64 KiB APU RAM" + ), + }); + } + _ => {} + } + + match self { + Self::BusU8 { .. } + | Self::ApuRamU8 { .. } + | Self::WramU8 { .. } + | Self::VramU8 { .. } + | Self::CgramU8 { .. } + | Self::OamU8 { .. } => { + self.expected_u8().map_err(|error| ManifestError::Invalid { + message: format!("ROM case `{case_id}` has invalid 8-bit assertion: {error}"), + })?; + } + Self::BusU16 { .. } + | Self::ApuRamU16 { .. } + | Self::WramU16 { .. } + | Self::VramU16 { .. } + | Self::CgramU16 { .. } + | Self::OamU16 { .. } => { + self.expected_u16() + .map_err(|error| ManifestError::Invalid { + message: format!( + "ROM case `{case_id}` has invalid 16-bit assertion: {error}" + ), + })?; + } + } + + Ok(()) + } +} + +fn default_check_interval_steps() -> u64 { + 1024 +} + +fn parse_value(value: &str, label: &str) -> Result { + let trimmed = value.trim(); + let (radix, digits) = match trimmed + .strip_prefix("0x") + .or_else(|| trimmed.strip_prefix("0X")) + { + Some(hex) => (16, hex), + None => (10, trimmed), + }; + + u64::from_str_radix(digits, radix).map_err(|_| ManifestError::Invalid { + message: format!("invalid {label} literal `{value}`"), + }) +} + +#[cfg(test)] +mod tests { + use super::{Assertion, RomCase, RomManifest}; + use std::path::PathBuf; + + fn dummy_case(id: &str) -> RomCase { + RomCase { + id: id.to_string(), + description: format!("case {id}"), + rom: PathBuf::from(format!("{id}.sfc")), + max_steps: 1, + check_interval_steps: 1, + expected_screen_hash: None, + reference_png: None, + assertions: vec![Assertion::BusU8 { + address: "0x00".to_string(), + expected: "0x00".to_string(), + }], + reset_at_steps: vec![], + resolved_rom_path: PathBuf::from(format!("/tmp/{id}.sfc")), + resolved_png_path: None, + } + } + + #[test] + fn select_rejects_unknown_requested_case_ids() { + let manifest = RomManifest { + rom_root: PathBuf::new(), + cases: vec![dummy_case("alpha"), dummy_case("beta")], + }; + + let error = manifest + .select(&["alpha".to_string(), "missing".to_string()]) + .unwrap_err(); + + assert!( + error + .to_string() + .contains("unknown ROM case id(s): missing"), + "unexpected error: {error}" + ); + } + + #[test] + fn select_returns_cases_sorted_by_id() { + let manifest = RomManifest { + rom_root: PathBuf::new(), + cases: vec![dummy_case("beta"), dummy_case("alpha")], + }; + + let selected = manifest.select(&[]).unwrap(); + + assert_eq!( + selected + .iter() + .map(|case| case.id.as_str()) + .collect::>(), + vec!["alpha", "beta"] + ); + } + + #[test] + fn expected_screen_hash_parses_hex_u64_values() { + let mut case = dummy_case("hash"); + case.expected_screen_hash = Some("0x2F605F796DA9D7E0".to_string()); + + assert_eq!( + case.expected_screen_hash().unwrap(), + Some(0x2F60_5F79_6DA9_D7E0) + ); + } + + #[test] + fn validation_rejects_out_of_bounds_apu_ram_assertions() { + let assertion = Assertion::ApuRamU16 { + address: "0xFFFF".to_string(), + expected: "0x0000".to_string(), + }; + + let error = assertion.validate("apu-case").unwrap_err(); + + assert!( + error.to_string().contains("crossing 64 KiB APU RAM"), + "unexpected error: {error}" + ); + } + + #[test] + fn validation_rejects_large_apu_ram_addresses_without_overflowing() { + let assertion = Assertion::ApuRamU16 { + address: "0xFFFFFFFF".to_string(), + expected: "0x0000".to_string(), + }; + + let error = assertion.validate("apu-case").unwrap_err(); + + assert!( + error.to_string().contains("crossing 64 KiB APU RAM"), + "unexpected error: {error}" + ); + } +} diff --git a/snes/rom_test/src/media.rs b/snes/rom_test/src/media.rs new file mode 100644 index 00000000..9435d1d5 --- /dev/null +++ b/snes/rom_test/src/media.rs @@ -0,0 +1,132 @@ +use nerust_crc64_hasher::Crc64Hasher; +use png::{BitDepth, ColorType, Decoder, Encoder}; +use std::fs; +use std::hash::Hasher; +use std::io::Cursor; +use std::path::Path; + +pub const SCREEN_WIDTH: usize = 256; +pub const SCREEN_HEIGHT: usize = 224; + +pub fn screen_hash_rgba(rgba: &[u8]) -> u64 { + let mut hasher = Crc64Hasher::new(); + hasher.write(rgba); + hasher.finish() +} + +pub fn load_png_rgba(path: &Path) -> Result, String> { + let file = fs::read(path).map_err(|e| format!("failed to read `{}`: {e}", path.display()))?; + let cursor = Cursor::new(file); + let decoder = Decoder::new(cursor); + let mut reader = decoder + .read_info() + .map_err(|e| format!("failed to decode `{}`: {e}", path.display()))?; + let width = reader.info().width as usize; + let height = reader.info().height as usize; + let pixel_count = width * height; + let buf_size = reader.output_buffer_size().unwrap_or(pixel_count * 4); + let mut raw = vec![0u8; buf_size]; + let _info = reader + .next_frame(&mut raw) + .map_err(|e| format!("failed to read `{}`: {e}", path.display()))?; + + let output_size = pixel_count * 4; + let rgba = if raw.len() >= output_size { + raw[..output_size].to_vec() + } else { + // Paletted PNG with bit_depth < 8: pixels are packed (e.g. 4-bit = 2 pixels/byte). + // The decoder provides raw packed bytes; expand to RGBA via palette lookup. + let bits_per_pixel = match reader.info().bit_depth { + png::BitDepth::One => 1, + png::BitDepth::Two => 2, + png::BitDepth::Four => 4, + png::BitDepth::Eight => 8, + png::BitDepth::Sixteen => 16, + }; + let pixels_per_byte = if bits_per_pixel < 8 { + 8 / bits_per_pixel + } else { + 1 + }; + let palette = reader.info().palette.as_ref(); + let trns = reader.info().trns.as_ref(); + let mut rgba = Vec::with_capacity(output_size); + for i in 0..pixel_count { + let (r, g, b, a) = if pixels_per_byte > 1 && palette.is_some() { + // Packed indexed pixels: extract nibble/bit and look up palette. + let byte_idx = i / pixels_per_byte; + let shift = ((i % pixels_per_byte) * bits_per_pixel) as u8; + let idx = if byte_idx < raw.len() { + (raw[byte_idx] >> shift) & ((1u8 << bits_per_pixel) - 1) + } else { + 0 + } as usize; + let pal = palette.unwrap(); + if idx * 3 + 2 < pal.len() { + let alpha = trns.and_then(|t| t.get(idx).copied()).unwrap_or(0xFF); + (pal[idx * 3], pal[idx * 3 + 1], pal[idx * 3 + 2], alpha) + } else { + (0, 0, 0, 0xFF) + } + } else { + // Full-byte format (RGB, RGBA, or grayscale). + let src_bpp = if raw.len() >= pixel_count * 3 { 3 } else { 1 }; + let src = i * src_bpp; + let r = if src < raw.len() { raw[src] } else { 0 }; + let g = if src_bpp > 1 && src + 1 < raw.len() { + raw[src + 1] + } else { + r + }; + let b = if src_bpp > 2 && src + 2 < raw.len() { + raw[src + 2] + } else { + r + }; + (r, g, b, 0xFF) + }; + rgba.push(r); + rgba.push(g); + rgba.push(b); + rgba.push(a); + } + rgba + }; + Ok(rgba) +} + +pub fn png_hash_from_path(path: &Path) -> Result { + let rgba = load_png_rgba(path)?; + let mut hasher = Crc64Hasher::new(); + hasher.write(&rgba); + Ok(hasher.finish()) +} + +pub fn encode_screenshot_png( + rgba: &[u8], + width: u32, + height: u32, +) -> Result, png::EncodingError> { + let mut encoded = Cursor::new(Vec::new()); + let mut encoder = Encoder::new(&mut encoded, width, height); + encoder.set_color(ColorType::Rgba); + encoder.set_depth(BitDepth::Eight); + let mut writer = encoder.write_header()?; + writer.write_image_data(rgba)?; + drop(writer); + Ok(encoded.into_inner()) +} + +#[cfg(test)] +mod tests { + use super::screen_hash_rgba; + + #[test] + fn screen_hash_changes_with_pixel_content() { + let first = [0x00, 0x10, 0x20, 0xFF, 0x40, 0x50, 0x60, 0xFF]; + let second = [0x00, 0x10, 0x20, 0xFF, 0x40, 0x50, 0x61, 0xFF]; + + assert_eq!(screen_hash_rgba(&first), screen_hash_rgba(&first)); + assert_ne!(screen_hash_rgba(&first), screen_hash_rgba(&second)); + } +} diff --git a/snes/rom_test/src/report.rs b/snes/rom_test/src/report.rs new file mode 100644 index 00000000..a117ca11 --- /dev/null +++ b/snes/rom_test/src/report.rs @@ -0,0 +1,167 @@ +use crate::results::CaseOutcome; +use std::fmt::Write as _; +use std::fs; +use std::path::{Path, PathBuf}; + +#[derive(Debug, Clone)] +pub struct ReportSummary { + pub report_path: PathBuf, + pub passed: usize, + pub failed: usize, +} + +pub fn default_output_root() -> PathBuf { + Path::new(env!("CARGO_MANIFEST_DIR")).join("../target/snes-rom-tests") +} + +pub fn write_html_report( + output_dir: &Path, + title: &str, + outcomes: &[CaseOutcome], +) -> Result { + fs::create_dir_all(output_dir) + .map_err(|error| format!("failed to create `{}`: {error}", output_dir.display()))?; + let screenshots_dir = output_dir.join("screenshots"); + fs::create_dir_all(&screenshots_dir) + .map_err(|error| format!("failed to create `{}`: {error}", screenshots_dir.display()))?; + + let passed = outcomes.iter().filter(|outcome| outcome.passed()).count(); + let failed = outcomes.len().saturating_sub(passed); + let mut html = String::new(); + + write!( + html, + "{}\ + ", + escape_html(title) + ) + .unwrap(); + + write!( + html, + "

    {}

    Total cases: {} / passed: {} / failed: {}

    ", + escape_html(title), + outcomes.len(), + passed, + failed + ) + .unwrap(); + + for outcome in outcomes { + match outcome { + CaseOutcome::Completed(validation) => { + let screenshot_rel = if let Some(bytes) = &validation.screenshot_png { + let relative = + format!("screenshots/{}.png", sanitize_for_path(&validation.case_id)); + let absolute = output_dir.join(&relative); + fs::write(&absolute, bytes).map_err(|error| { + format!("failed to write `{}`: {error}", absolute.display()) + })?; + Some(relative) + } else { + None + }; + let status_class = if validation.passed() { "pass" } else { "fail" }; + let status_label = if validation.passed() { "PASS" } else { "FAIL" }; + write!( + html, + "

    {}

    {}

    \ +

    Status: {}

    \ +

    ROM: {}

    \ +

    Steps executed: {} / Final screen hash: 0x{:016X}

    ", + escape_html(&validation.case_id), + escape_html(&validation.description), + status_class, + status_label, + escape_html(&validation.rom), + validation.steps_executed, + validation.final_screen_hash + ) + .unwrap(); + + if let Some(relative) = screenshot_rel { + write!( + html, + "

    \"{}

    ", + escape_html(&relative), + escape_html(&relative), + escape_html(&validation.case_id) + ) + .unwrap(); + } else { + html.push_str("

    Screenshot: unavailable

    "); + } + + if validation.failures.is_empty() { + html.push_str("

    No assertion failures.

    "); + } else { + html.push_str("

    Failures

      "); + for failure in &validation.failures { + write!(html, "
    • {}
    • ", escape_html(failure)).unwrap(); + } + html.push_str("
    "); + } + html.push_str("
    "); + } + CaseOutcome::InternalError { + case_id, + description, + rom, + message, + } => { + write!( + html, + "

    {}

    {}

    \ +

    Status: ERROR

    \ +

    ROM: {}

    {}

    ", + escape_html(case_id), + escape_html(description), + escape_html(rom), + escape_html(message) + ) + .unwrap(); + } + } + } + + html.push_str(""); + let report_path = output_dir.join("index.html"); + fs::write(&report_path, html) + .map_err(|error| format!("failed to write `{}`: {error}", report_path.display()))?; + + Ok(ReportSummary { + report_path, + passed, + failed, + }) +} + +fn escape_html(value: &str) -> String { + value + .replace('&', "&") + .replace('<', "<") + .replace('>', ">") + .replace('"', """) +} + +fn sanitize_for_path(value: &str) -> String { + value + .chars() + .map(|character| { + if character.is_ascii_alphanumeric() || character == '-' || character == '_' { + character + } else { + '_' + } + }) + .collect() +} diff --git a/snes/rom_test/src/results.rs b/snes/rom_test/src/results.rs new file mode 100644 index 00000000..69be97bd --- /dev/null +++ b/snes/rom_test/src/results.rs @@ -0,0 +1,52 @@ +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub struct ValidationOptions { + pub capture_screenshot_png: bool, +} + +impl ValidationOptions { + pub const fn testing() -> Self { + Self { + capture_screenshot_png: false, + } + } + + pub const fn report() -> Self { + Self { + capture_screenshot_png: true, + } + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub struct Validation { + pub case_id: String, + pub description: String, + pub rom: String, + pub steps_executed: u64, + pub final_screen_hash: u64, + pub screenshot_png: Option>, + pub failures: Vec, +} + +impl Validation { + pub fn passed(&self) -> bool { + self.failures.is_empty() + } +} + +#[derive(Debug, Clone, PartialEq, Eq)] +pub enum CaseOutcome { + Completed(Validation), + InternalError { + case_id: String, + description: String, + rom: String, + message: String, + }, +} + +impl CaseOutcome { + pub fn passed(&self) -> bool { + matches!(self, Self::Completed(validation) if validation.passed()) + } +} diff --git a/snes/rom_test/src/runner.rs b/snes/rom_test/src/runner.rs new file mode 100644 index 00000000..06793e5d --- /dev/null +++ b/snes/rom_test/src/runner.rs @@ -0,0 +1,550 @@ +use crate::manifest::{Assertion, ManifestError, RomCase}; +use crate::media::{encode_screenshot_png, load_png_rgba, png_hash_from_path, screen_hash_rgba}; +use crate::results::{CaseOutcome, Validation, ValidationOptions}; +use nerust_snes_core::{Core, CpuState}; +use nerust_snes_render::render_screen; +use std::fs; +use std::io::ErrorKind; +use std::path::Path; + +pub fn validate_case(case: &RomCase) -> CaseOutcome { + validate_case_with_options(case, ValidationOptions::testing()) +} + +pub fn validate_case_with_options(case: &RomCase, options: ValidationOptions) -> CaseOutcome { + let should_wait_for_final_screen = + case.expected_screen_hash.is_some() || case.png_path().is_some(); + let mut core = match load_core_for_case(case) { + Ok(core) => core, + Err(error) => return internal_error(case, error), + }; + + let mut steps_executed = 0_u64; + let mut next_reset_index = 0_usize; + + while steps_executed < case.max_steps { + // Check for scheduled reset before stepping + if let Some(&reset_at) = case.reset_at_steps.get(next_reset_index) + && steps_executed == reset_at + { + core.reset_cpu(); + next_reset_index += 1; + } + + match core.step() { + Ok(()) => { + steps_executed += 1; + } + Err(error) => { + return internal_error( + case, + format!("core error after {steps_executed} steps: {error}"), + ); + } + } + + if steps_executed.is_multiple_of(case.check_interval_steps) { + match assertion_failures(case, &core) { + Ok(failures) if failures.is_empty() && !should_wait_for_final_screen => { + return finalize_validation(case, steps_executed, failures, &core, options); + } + Ok(_) => {} + Err(error) => { + return internal_error(case, error.to_string()); + } + } + } + } + + match assertion_failures(case, &core) { + Ok(mut failures) => { + if !failures.is_empty() { + let reason = if core.current_state() == CpuState::Stopped { + format!("core stopped after {steps_executed} steps before expectations matched") + } else { + format!("expectations did not match within {} steps", case.max_steps) + }; + failures.insert(0, reason); + } + finalize_validation(case, steps_executed, failures, &core, options) + } + Err(error) => internal_error(case, error.to_string()), + } +} + +pub fn load_core_for_case(case: &RomCase) -> Result { + let rom = fs::read(case.rom_path()).map_err(|error| { + format!( + "failed to read ROM `{}`: {error}", + case.rom_path().display() + ) + })?; + let msu1_sidecars = load_msu1_sidecars(case.rom_path())?; + + Core::from_rom_bytes_with_msu1_sidecars( + &rom, + msu1_sidecars.data.as_deref(), + &msu1_sidecars.audio_tracks, + ) + .map_err(|error| { + format!( + "failed to construct SNES core from `{}`: {error}", + case.rom_path().display() + ) + }) +} + +struct Msu1Sidecars { + data: Option>, + audio_tracks: Vec, +} + +fn load_msu1_sidecars(rom_path: &Path) -> Result { + Ok(Msu1Sidecars { + data: load_msu1_data_sidecar(rom_path)?, + audio_tracks: discover_msu1_audio_tracks(rom_path)?, + }) +} + +fn load_msu1_data_sidecar(rom_path: &Path) -> Result>, String> { + // Try .msu file first (uncompressed sidecar). + let data_path = rom_path.with_extension("msu"); + match fs::read(&data_path) { + Ok(bytes) => return Ok(Some(bytes)), + Err(error) if error.kind() == ErrorKind::NotFound => {} + Err(error) => { + return Err(format!( + "failed to read MSU-1 data sidecar `{}`: {error}", + data_path.display() + )); + } + } + + // Try .msu.7z file (compressed sidecar, decompress to memory). + let compressed_path = rom_path.with_extension("msu.7z"); + let compressed = match fs::read(&compressed_path) { + Ok(bytes) => bytes, + Err(error) if error.kind() == ErrorKind::NotFound => return Ok(None), + Err(error) => { + return Err(format!( + "failed to read MSU-1 compressed sidecar `{}`: {error}", + compressed_path.display() + )); + } + }; + decompress_msu_7z(&compressed).map(Some) +} + +/// Decompress a 7z archive containing an MSU-1 data file. +/// +/// The archive is expected to hold a single file (the .msu data). +/// Its contents are decompressed entirely to memory and returned. +fn decompress_msu_7z(compressed: &[u8]) -> Result, String> { + use std::io::Cursor; + + let cursor = Cursor::new(compressed); + let mut reader = sevenz_rust2::ArchiveReader::new(cursor, sevenz_rust2::Password::empty()) + .map_err(|e| format!("failed to open MSU-1 7z archive: {e}"))?; + + let mut result: Option> = None; + reader + .for_each_entries(|_entry, entry_reader| { + let mut data = Vec::new(); + entry_reader.read_to_end(&mut data)?; + result = Some(data); + // Stop after the first entry (a 7z archive should contain a single file). + Ok(false) + }) + .map_err(|e| format!("failed to decompress MSU-1 7z archive: {e}"))?; + + result.ok_or_else(|| "MSU-1 7z archive contains no files".to_string()) +} + +pub fn discover_msu1_audio_tracks(rom_path: &Path) -> Result, String> { + let Some(stem) = rom_path.file_stem().and_then(|stem| stem.to_str()) else { + return Ok(Vec::new()); + }; + let prefix = format!("{stem}-"); + let directory = rom_path + .parent() + .filter(|parent| !parent.as_os_str().is_empty()) + .unwrap_or_else(|| Path::new(".")); + let entries = fs::read_dir(directory).map_err(|error| { + format!( + "failed to scan MSU-1 audio sidecars in `{}`: {error}", + directory.display() + ) + })?; + let mut tracks = Vec::new(); + for entry in entries { + let entry = entry.map_err(|error| { + format!( + "failed to scan MSU-1 audio sidecars in `{}`: {error}", + directory.display() + ) + })?; + let path = entry.path(); + if !path + .extension() + .and_then(|extension| extension.to_str()) + .is_some_and(|extension| extension.eq_ignore_ascii_case("pcm")) + { + continue; + } + + let Some(file_stem) = path.file_stem().and_then(|file_stem| file_stem.to_str()) else { + continue; + }; + if let Some(track) = file_stem + .strip_prefix(&prefix) + .and_then(|track| track.parse::().ok()) + { + tracks.push(track); + } + } + tracks.sort_unstable(); + tracks.dedup(); + Ok(tracks) +} + +pub fn has_msu1_data_sidecar(rom_path: &Path) -> Result { + let data_path = rom_path.with_extension("msu"); + match fs::metadata(&data_path) { + Ok(metadata) => Ok(metadata.is_file()), + Err(error) if error.kind() == ErrorKind::NotFound => Ok(false), + Err(error) => Err(format!( + "failed to stat MSU-1 data sidecar `{}`: {error}", + data_path.display() + )), + } +} + +fn finalize_validation( + case: &RomCase, + steps_executed: u64, + mut failures: Vec, + core: &Core, + options: ValidationOptions, +) -> CaseOutcome { + let rendered = match render_screen(core) { + Ok(rendered) => rendered, + Err(error) => { + return internal_error( + case, + format!("failed to render final screen after {steps_executed} steps: {error}"), + ); + } + }; + let final_screen_hash = screen_hash_rgba(&rendered.rgba); + if let Some(png_path) = case.png_path() { + match png_hash_from_path(png_path) { + Ok(png_hash) if png_hash != final_screen_hash => { + failures.push(format!( + "screen_hash: reference PNG 0x{png_hash:016X}, rendered 0x{final_screen_hash:016X}" + )); + if let Ok(png_rgba) = load_png_rgba(png_path) { + let png_pitch = if rendered.height > 0 { + png_rgba.len() / rendered.height + } else { + rendered.width * 4 + }; + let our_pitch = rendered.width * 4; + for y in 0..rendered.height { + for x in 0..rendered.width { + let png_idx = y * png_pitch + x * 4; + let our_idx = y * our_pitch + x * 4; + if png_idx + 4 <= png_rgba.len() && our_idx + 4 <= rendered.rgba.len() { + let pr = png_rgba[png_idx]; + let pg = png_rgba[png_idx + 1]; + let pb = png_rgba[png_idx + 2]; + let pa = png_rgba[png_idx + 3]; + let or = rendered.rgba[our_idx]; + let og = rendered.rgba[our_idx + 1]; + let ob = rendered.rgba[our_idx + 2]; + let oa = rendered.rgba[our_idx + 3]; + if (pr, pg, pb, pa) != (or, og, ob, oa) { + let screen_x = x; + let screen_y = y; + failures.push(format!( + "first pixel diff at ({screen_x}, {screen_y}): PNG ({pr},{pg},{pb},{pa}), rendered ({or},{og},{ob},{oa})" + )); + break; + } + } + } + if failures + .last() + .map_or(false, |f| f.starts_with("first pixel diff")) + { + break; + } + } + if !failures.iter().any(|f| f.starts_with("first pixel diff")) { + failures.push(format!( + "pixel diff: different sizes? PNG {} bytes, rendered {}x{}", + png_rgba.len(), + rendered.width, + rendered.height, + )); + } + } + } + Ok(_) => {} + Err(error) => { + return internal_error( + case, + format!( + "failed to hash reference PNG `{}`: {error}", + png_path.display() + ), + ); + } + } + } else if let Ok(Some(expected_screen_hash)) = case.expected_screen_hash() { + if expected_screen_hash != final_screen_hash { + failures.push(format!( + "screen_hash: expected 0x{expected_screen_hash:016X}, got 0x{final_screen_hash:016X}" + )); + } + } + let screenshot_png = if options.capture_screenshot_png { + match encode_screenshot_png( + &rendered.rgba, + rendered.width as u32, + rendered.height as u32, + ) { + Ok(bytes) => Some(bytes), + Err(error) => { + return internal_error( + case, + format!( + "failed to encode final screenshot after {steps_executed} steps: {error}" + ), + ); + } + } + } else { + None + }; + + CaseOutcome::Completed(Validation { + case_id: case.id.clone(), + description: case.description.clone(), + rom: case.rom_path().display().to_string(), + steps_executed, + final_screen_hash, + screenshot_png, + failures, + }) +} + +fn internal_error(case: &RomCase, message: String) -> CaseOutcome { + CaseOutcome::InternalError { + case_id: case.id.clone(), + description: case.description.clone(), + rom: case.rom_path().display().to_string(), + message, + } +} + +fn assertion_failures(case: &RomCase, core: &Core) -> Result, ManifestError> { + case.assertions + .iter() + .map(|assertion| match assertion { + Assertion::BusU8 { .. } + | Assertion::ApuRamU8 { .. } + | Assertion::WramU8 { .. } + | Assertion::VramU8 { .. } + | Assertion::CgramU8 { .. } + | Assertion::OamU8 { .. } => evaluate_u8_assertion(assertion, core), + Assertion::BusU16 { .. } + | Assertion::ApuRamU16 { .. } + | Assertion::WramU16 { .. } + | Assertion::VramU16 { .. } + | Assertion::CgramU16 { .. } + | Assertion::OamU16 { .. } => evaluate_u16_assertion(assertion, core), + }) + .filter_map(Result::transpose) + .collect() +} + +fn evaluate_u8_assertion( + assertion: &Assertion, + core: &Core, +) -> Result, ManifestError> { + let address = assertion.address()?; + let expected = assertion.expected_u8()?; + let actual = match assertion { + Assertion::BusU8 { .. } => core.peek(address), + Assertion::ApuRamU8 { .. } => core.peek_apu_ram(address as u16), + Assertion::WramU8 { .. } => core.peek_wram(address as usize), + Assertion::VramU8 { .. } => core.peek_vram(address as usize), + Assertion::CgramU8 { .. } => core.peek_cgram(address as usize), + Assertion::OamU8 { .. } => core.peek_oam(address as usize), + _ => { + return Err(ManifestError::Invalid { + message: "evaluate_u8_assertion called for 16-bit assertion".to_string(), + }); + } + }; + + if actual == expected { + Ok(None) + } else { + Ok(Some(format!( + "{} @ 0x{address:06X}: expected 0x{expected:02X}, got 0x{actual:02X}", + assertion_kind(assertion) + ))) + } +} + +fn evaluate_u16_assertion( + assertion: &Assertion, + core: &Core, +) -> Result, ManifestError> { + let address = assertion.address()?; + let expected = assertion.expected_u16()?; + let actual = match assertion { + Assertion::BusU16 { .. } => { + u16::from_le_bytes([core.peek(address), core.peek(address + 1)]) + } + Assertion::ApuRamU16 { .. } => u16::from_le_bytes([ + core.peek_apu_ram(address as u16), + core.peek_apu_ram((address as u16) + 1), + ]), + Assertion::WramU16 { .. } => u16::from_le_bytes([ + core.peek_wram(address as usize), + core.peek_wram(address as usize + 1), + ]), + Assertion::VramU16 { .. } => u16::from_le_bytes([ + core.peek_vram(address as usize), + core.peek_vram(address as usize + 1), + ]), + Assertion::CgramU16 { .. } => u16::from_le_bytes([ + core.peek_cgram(address as usize), + core.peek_cgram(address as usize + 1), + ]), + Assertion::OamU16 { .. } => u16::from_le_bytes([ + core.peek_oam(address as usize), + core.peek_oam(address as usize + 1), + ]), + _ => { + return Err(ManifestError::Invalid { + message: "evaluate_u16_assertion called for 8-bit assertion".to_string(), + }); + } + }; + + if actual == expected { + Ok(None) + } else { + Ok(Some(format!( + "{} @ 0x{address:06X}: expected 0x{expected:04X}, got 0x{actual:04X}", + assertion_kind(assertion) + ))) + } +} + +fn assertion_kind(assertion: &Assertion) -> &'static str { + match assertion { + Assertion::BusU8 { .. } => "bus_u8", + Assertion::BusU16 { .. } => "bus_u16", + Assertion::ApuRamU8 { .. } => "apu_ram_u8", + Assertion::ApuRamU16 { .. } => "apu_ram_u16", + Assertion::WramU8 { .. } => "wram_u8", + Assertion::WramU16 { .. } => "wram_u16", + Assertion::VramU8 { .. } => "vram_u8", + Assertion::VramU16 { .. } => "vram_u16", + Assertion::CgramU8 { .. } => "cgram_u8", + Assertion::CgramU16 { .. } => "cgram_u16", + Assertion::OamU8 { .. } => "oam_u8", + Assertion::OamU16 { .. } => "oam_u16", + } +} + +#[cfg(test)] +mod tests { + use super::{discover_msu1_audio_tracks, validate_case}; + use crate::manifest::load_manifest; + use crate::results::CaseOutcome; + use std::fs; + use std::path::PathBuf; + use std::time::{SystemTime, UNIX_EPOCH}; + + const HEADER_OFFSET: usize = 0x7FC0; + const RESET_VECTOR_OFFSET: usize = 0x7FFC; + + fn unique_temp_path(name: &str, extension: &str) -> PathBuf { + let unique = SystemTime::now() + .duration_since(UNIX_EPOCH) + .expect("system time should be after unix epoch") + .as_nanos(); + std::env::temp_dir().join(format!("nerust-snes-rom-test-{name}-{unique}.{extension}")) + } + + fn write_test_rom(path: &PathBuf) { + let mut rom = vec![0; 0x10000]; + rom[HEADER_OFFSET..HEADER_OFFSET + 21].copy_from_slice(b"TEST HASH ROM "); + rom[0x7FD5] = 0x30; + rom[0x7FD7] = 0x08; + rom[RESET_VECTOR_OFFSET..RESET_VECTOR_OFFSET + 2].copy_from_slice(&0x8000u16.to_le_bytes()); + rom[0x0000] = 0xEA; + fs::write(path, rom).expect("test rom should be written"); + } + + #[test] + fn msu1_audio_discovery_matches_decimal_pcm_tracks() { + let directory = unique_temp_path("msu1-audio-discovery", "dir"); + let _ = fs::remove_dir_all(&directory); + fs::create_dir_all(&directory).expect("temporary directory should be created"); + fs::write(directory.join("Game-1.pcm"), []).expect("pcm file should be written"); + fs::write(directory.join("Game-3.PCM"), []).expect("pcm file should be written"); + fs::write(directory.join("Game-0012.pcm"), []).expect("pcm file should be written"); + fs::write(directory.join("Game-12.pcm"), []).expect("pcm file should be written"); + fs::write(directory.join("Game-70000.pcm"), []).expect("pcm file should be written"); + fs::write(directory.join("Other-2.pcm"), []).expect("pcm file should be written"); + fs::write(directory.join("Game.msu"), []).expect("msu data file should be written"); + + let tracks = discover_msu1_audio_tracks(&directory.join("Game.sfc")) + .expect("audio track discovery should succeed"); + + let _ = fs::remove_dir_all(&directory); + assert_eq!(tracks, [1, 3, 12]); + } + + #[test] + fn expected_screen_hash_mismatch_is_reported_as_a_failure() { + let rom_path = unique_temp_path("hash-mismatch", "sfc"); + let manifest_path = unique_temp_path("hash-mismatch", "yaml"); + write_test_rom(&rom_path); + fs::write( + &manifest_path, + format!( + "rom_root: .\ncases:\n - id: hash-mismatch\n description: Hash mismatch test\n rom: {}\n max_steps: 32\n check_interval_steps: 16\n expected_screen_hash: \"0x0000000000000000\"\n", + rom_path.display() + ), + ) + .expect("manifest should be written"); + + let manifest = load_manifest(&manifest_path).expect("manifest should load"); + let outcome = validate_case(manifest.case("hash-mismatch").expect("case should exist")); + + match outcome { + CaseOutcome::Completed(validation) => { + assert_eq!(validation.steps_executed, 32); + assert!( + validation + .failures + .iter() + .any(|failure| failure.starts_with("screen_hash: expected")), + "expected screen hash failure, got {:?}", + validation.failures + ); + } + other => panic!("expected completed validation result, got {other:?}"), + } + + fs::remove_file(rom_path).ok(); + fs::remove_file(manifest_path).ok(); + } +} diff --git a/snes/rom_test/tests/lib.rs b/snes/rom_test/tests/lib.rs new file mode 100644 index 00000000..ca85d1c6 --- /dev/null +++ b/snes/rom_test/tests/lib.rs @@ -0,0 +1,46 @@ +use nerust_snes_rom_test::manifest::{RomManifest, load_default_manifest}; +use nerust_snes_rom_test::results::CaseOutcome; +use nerust_snes_rom_test::runner::validate_case; +use std::sync::OnceLock; + +#[test] +fn rom_manifest_is_well_formed() { + let manifest = manifest(); + assert_eq!( + GENERATED_ROM_CASE_COUNT, + manifest.cases.len(), + "generated test count should match the manifest case count" + ); +} + +fn manifest() -> &'static RomManifest { + static MANIFEST: OnceLock = OnceLock::new(); + MANIFEST.get_or_init(|| load_default_manifest().expect("ROM manifest should load")) +} + +fn run_generated_manifest_case(case_id: &str) { + let case = manifest() + .case(case_id) + .unwrap_or_else(|| panic!("ROM case `{case_id}` should exist in the manifest")); + let outcome = validate_case(case); + + match outcome { + CaseOutcome::Completed(validation) if validation.passed() => {} + CaseOutcome::Completed(validation) => { + panic!( + "{} ({} steps, final screen hash 0x{:016X}):\n{}", + validation.case_id, + validation.steps_executed, + validation.final_screen_hash, + validation.failures.join("\n") + ); + } + CaseOutcome::InternalError { + case_id, message, .. + } => { + panic!("{case_id}: {message}"); + } + } +} + +include!(concat!(env!("OUT_DIR"), "/generated_rom_manifest_tests.rs")); diff --git a/sound/android/src/android.rs b/sound/android/src/android.rs index 5182c333..bbc1104d 100644 --- a/sound/android/src/android.rs +++ b/sound/android/src/android.rs @@ -1,15 +1,9 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - //! CPAL-based `AndroidSound` implementation, compiled only on Android. use cpal::traits::{DeviceTrait, HostTrait, StreamTrait}; -use nerust_sound_traits::{MixerInput, Sound}; +use nerust_sound_traits::{AudioFilterProfile, MixerInput, Sound}; use nerust_soundfilter::resampler::{Resampler, SimpleDownSampler}; -use nerust_soundfilter::{Filter, NesFilter}; +use nerust_soundfilter::{Filter, NesFilter, SnesFilter}; use std::sync::Arc; use std::sync::atomic::{AtomicBool, Ordering}; use std::sync::mpsc::{SyncSender, TrySendError, sync_channel}; @@ -32,13 +26,13 @@ pub struct AndroidSound { playing: Arc, /// Request that the callback discard any queued samples before resuming. needs_clear: Arc, - /// NES-specific audio filter chain (low-pass + two high-pass stages). - filter: NesFilter, + /// Audio filter chain (Nes/Snes). + filter: AndroidFilter, /// Master volume/mute gain in `[0.0, 1.0]`. gain: f32, - /// Resampler from the NES source rate to the device playback rate. + /// Resampler from the source rate to the device playback rate. resampler: SimpleDownSampler, - /// Effective source sample rate returned to the NES core. + /// Effective source sample rate returned to the core. source_sample_rate: u32, } @@ -51,6 +45,29 @@ pub struct AndroidSound { // the Rust `cpal::Stream` wrapper after the transfer. unsafe impl Send for AndroidSound {} +enum AndroidFilter { + Nes(NesFilter), + Snes(SnesFilter), +} + +impl AndroidFilter { + fn new(profile: AudioFilterProfile, sample_rate: f32) -> Self { + match profile { + AudioFilterProfile::Nes => Self::Nes(NesFilter::new(sample_rate)), + AudioFilterProfile::Snes => Self::Snes(SnesFilter::new(sample_rate)), + } + } +} + +impl Filter for AndroidFilter { + fn step(&mut self, data: f32) -> f32 { + match self { + Self::Nes(filter) => filter.step(data), + Self::Snes(filter) => filter.step(data), + } + } +} + impl AndroidSound { /// Create an `AndroidSound` backend. /// @@ -63,11 +80,12 @@ impl AndroidSound { /// Returns `Err` (with a descriptive message) if the audio device or stream /// cannot be opened. Callers must surface this error rather than falling /// back silently. - pub fn with_gain( + pub fn with_gain_and_filter( requested_playback_sample_rate: i32, latency_ms: u16, - output_rate: i32, + source_sample_rate: i32, gain: f32, + filter_profile: AudioFilterProfile, ) -> Result { let host = cpal::default_host(); @@ -90,16 +108,17 @@ impl AndroidSound { let playing = Arc::new(AtomicBool::new(false)); let needs_clear = Arc::new(AtomicBool::new(true)); - let output_rate_u32 = u32::try_from(output_rate) - .map_err(|_| format!("output_rate must be non-negative, got {output_rate}"))?; + let requested_source_rate_u32 = u32::try_from(source_sample_rate).map_err(|_| { + format!("source_sample_rate must be non-negative, got {source_sample_rate}") + })?; // Cap the source rate to at most OVERSAMPLE_FACTOR × the playback rate // to bound the amount of work done by the resampler. - let source_sample_rate = output_rate_u32 + let effective_source_sample_rate = requested_source_rate_u32 .min(playback_sample_rate.saturating_mul(OVERSAMPLE_FACTOR)) .max(playback_sample_rate); - let filter = NesFilter::new(playback_sample_rate as f32); + let filter = AndroidFilter::new(filter_profile, playback_sample_rate as f32); let mut stream_config = supported_config.config(); stream_config.sample_rate = playback_sample_rate; let configured_buffer_size = @@ -139,7 +158,7 @@ impl AndroidSound { while data_receiver.try_recv().is_ok() {} } let playing = callback_playing.load(Ordering::Acquire); - // Interleave the mono NES audio across all device channels. + // Interleave the mono audio across all device channels. for frame in output.chunks_mut(channels as usize) { let sample = if playing { data_receiver.try_recv().unwrap_or(0.0) @@ -164,12 +183,28 @@ impl AndroidSound { filter, gain, resampler: SimpleDownSampler::new( - f64::from(source_sample_rate), + f64::from(effective_source_sample_rate), f64::from(playback_sample_rate), ), - source_sample_rate, + source_sample_rate: effective_source_sample_rate, }) } + + pub fn with_gain( + requested_playback_sample_rate: i32, + latency_ms: u16, + output_rate: i32, + gain: f32, + ) -> Result { + // Backwards-compatible wrapper: default to NES profile + Self::with_gain_and_filter( + requested_playback_sample_rate, + latency_ms, + output_rate, + gain, + AudioFilterProfile::Nes, + ) + } } impl Sound for AndroidSound { diff --git a/sound/android/src/lib.rs b/sound/android/src/lib.rs index 1732e349..8a051552 100644 --- a/sound/android/src/lib.rs +++ b/sound/android/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - //! Android-native audio backend built on CPAL / AAudio. //! //! On Android API 26+, CPAL selects AAudio as the audio backend automatically. diff --git a/sound/filter/src/lib.rs b/sound/filter/src/lib.rs index 62946b3f..bda90f3e 100644 --- a/sound/filter/src/lib.rs +++ b/sound/filter/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub mod resampler; use std::f32; @@ -92,6 +86,7 @@ impl Filter for ChaindFilter { } pub type NesFilter = ChaindFilter, IirFilter>; +pub type SnesFilter = ChaindFilter; impl NesFilter { pub fn new(sample_rate: f32) -> Self { @@ -100,3 +95,12 @@ impl NesFilter { .chain(IirFilter::get_highpass_filter(sample_rate, 442.0)) } } + +impl SnesFilter { + pub fn new(sample_rate: f32) -> Self { + let lowpass_cutoff = 16000.0_f32.min(sample_rate * 0.45).max(1.0); + let highpass_cutoff = 20.0_f32.min(sample_rate * 0.10).max(1.0); + IirFilter::get_lowpass_filter(sample_rate, lowpass_cutoff) + .chain(IirFilter::get_highpass_filter(sample_rate, highpass_cutoff)) + } +} diff --git a/sound/filter/src/resampler.rs b/sound/filter/src/resampler.rs index 4115d365..765381fb 100644 --- a/sound/filter/src/resampler.rs +++ b/sound/filter/src/resampler.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use super::{Filter, IirFilter}; /// Trait for single-sample audio resamplers. diff --git a/sound/openal/src/lib.rs b/sound/openal/src/lib.rs index 062ef612..43503d3c 100644 --- a/sound/openal/src/lib.rs +++ b/sound/openal/src/lib.rs @@ -1,13 +1,7 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use alto::*; -use nerust_sound_traits::{MixerInput, Sound}; +use nerust_sound_traits::{AudioFilterProfile, MixerInput, Sound}; use nerust_soundfilter::resampler::{Resampler, SimpleDownSampler}; -use nerust_soundfilter::{Filter, NesFilter}; +use nerust_soundfilter::{Filter, NesFilter, SnesFilter}; #[cfg(target_os = "macos")] use std::os::unix::process::CommandExt; #[cfg(target_os = "macos")] @@ -446,12 +440,36 @@ impl OpenAlState { } } +#[derive(Debug)] +enum OpenAlFilter { + Nes(NesFilter), + Snes(SnesFilter), +} + +impl OpenAlFilter { + fn new(profile: AudioFilterProfile, sample_rate: f32) -> Self { + match profile { + AudioFilterProfile::Nes => Self::Nes(NesFilter::new(sample_rate)), + AudioFilterProfile::Snes => Self::Snes(SnesFilter::new(sample_rate)), + } + } +} + +impl Filter for OpenAlFilter { + fn step(&mut self, data: f32) -> f32 { + match self { + Self::Nes(filter) => filter.step(data), + Self::Snes(filter) => filter.step(data), + } + } +} + #[derive(Debug)] pub struct OpenAl { stop_sender: Sender<()>, playing_sender: Sender, data_sender: Sender, - filter: NesFilter, + filter: OpenAlFilter, gain: f32, thread: Option>, source_sample_rate: u32, @@ -474,6 +492,24 @@ impl OpenAl { buffer_width: usize, buffer_count: usize, gain: f32, + ) -> Self { + Self::with_gain_and_filter( + sample_rate, + output_rate, + buffer_width, + buffer_count, + gain, + AudioFilterProfile::Nes, + ) + } + + pub fn with_gain_and_filter( + sample_rate: i32, + output_rate: i32, + buffer_width: usize, + buffer_count: usize, + gain: f32, + filter_profile: AudioFilterProfile, ) -> Self { let requested_playback_sample_rate = sample_rate; let (src, playback_sample_rate) = @@ -491,7 +527,7 @@ impl OpenAl { let source_sample_rate = requested_source_rate .min(playback_sample_rate_u32.saturating_mul(CORE_AUDIO_OVERSAMPLE)) .max(playback_sample_rate_u32); - let filter = NesFilter::new(playback_sample_rate as f32); + let filter = OpenAlFilter::new(filter_profile, playback_sample_rate as f32); let (playing_sender, playing_recv) = channel(); let (data_sender, data_recv) = channel(); let (stop_sender, stop_recv) = channel(); diff --git a/sound/traits/src/lib.rs b/sound/traits/src/lib.rs index f7bc28d3..66a72d18 100644 --- a/sound/traits/src/lib.rs +++ b/sound/traits/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - pub trait Sound { fn start(&mut self); fn pause(&mut self); @@ -21,3 +15,9 @@ pub trait MixerInput { 48_000 } } + +#[derive(Debug, Clone, Copy, PartialEq, Eq)] +pub enum AudioFilterProfile { + Nes, + Snes, +} diff --git a/timer/src/lib.rs b/timer/src/lib.rs index 529244bb..c7ec000f 100644 --- a/timer/src/lib.rs +++ b/timer/src/lib.rs @@ -1,9 +1,3 @@ -// Copyright (c) 2018 Mitsuharu Seki -// -// This Source Code Form is subject to the terms of the Mozilla Public -// License, v. 2.0. If a copy of the MPL was not distributed with this -// file, You can obtain one at http://mozilla.org/MPL/2.0/. - use std::collections::VecDeque; use std::thread; use std::time::{Duration, Instant}; diff --git a/util/crc64_hasher/Cargo.toml b/util/crc64_hasher/Cargo.toml new file mode 100644 index 00000000..ad4e9865 --- /dev/null +++ b/util/crc64_hasher/Cargo.toml @@ -0,0 +1,13 @@ +[package] +name = "nerust_crc64_hasher" +version.workspace = true +authors.workspace = true +description.workspace = true +license.workspace = true +repository.workspace = true +homepage.workspace = true +edition.workspace = true +rust-version.workspace = true + +[dependencies] +crc.workspace = true diff --git a/util/crc64_hasher/src/lib.rs b/util/crc64_hasher/src/lib.rs new file mode 100644 index 00000000..971014a3 --- /dev/null +++ b/util/crc64_hasher/src/lib.rs @@ -0,0 +1,57 @@ +use std::hash::Hasher; + +use crc::{CRC_64_XZ, Crc, Digest}; + +const CRC64_LEGACY_ECMA: Crc = Crc::::new(&CRC_64_XZ); + +pub struct Crc64Hasher(Digest<'static, u64>); + +impl Crc64Hasher { + pub fn new() -> Self { + Self(CRC64_LEGACY_ECMA.digest()) + } +} + +pub fn crc64(bytes: &[u8]) -> u64 { + let mut hasher = Crc64Hasher::new(); + hasher.write(bytes); + hasher.finish() +} + +impl Hasher for Crc64Hasher { + fn write(&mut self, bytes: &[u8]) { + self.0.update(bytes); + } + + fn finish(&self) -> u64 { + self.0.clone().finalize() + } +} + +impl Default for Crc64Hasher { + fn default() -> Self { + Self::new() + } +} + +#[cfg(test)] +mod tests { + use super::crc64; + + #[test] + fn crc64_changes_with_input() { + let first = [0x00, 0x10, 0x20, 0xFF, 0x40, 0x50, 0x60, 0xFF]; + let second = [0x00, 0x10, 0x20, 0xFF, 0x40, 0x50, 0x61, 0xFF]; + + assert_eq!(crc64(&first), crc64(&first)); + assert_ne!(crc64(&first), crc64(&second)); + } + + #[test] + fn crc64_consistency() { + let data = [0x00, 0x10, 0x20, 0xFF, 0x40, 0x50, 0x60, 0xFF]; + let hash1 = crc64(&data); + let hash2 = crc64(&data); + assert_eq!(hash1, hash2); + } +}